1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26
27 #include <drm/amdgpu_drm.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_atombios.h"
31 #include "amdgpu_ih.h"
32 #include "amdgpu_uvd.h"
33 #include "amdgpu_vce.h"
34 #include "amdgpu_ucode.h"
35 #include "atom.h"
36 #include "amd_pcie.h"
37
38 #include "gmc/gmc_8_1_d.h"
39 #include "gmc/gmc_8_1_sh_mask.h"
40
41 #include "oss/oss_3_0_d.h"
42 #include "oss/oss_3_0_sh_mask.h"
43
44 #include "bif/bif_5_0_d.h"
45 #include "bif/bif_5_0_sh_mask.h"
46
47 #include "gca/gfx_8_0_d.h"
48 #include "gca/gfx_8_0_sh_mask.h"
49
50 #include "smu/smu_7_1_1_d.h"
51 #include "smu/smu_7_1_1_sh_mask.h"
52
53 #include "uvd/uvd_5_0_d.h"
54 #include "uvd/uvd_5_0_sh_mask.h"
55
56 #include "vce/vce_3_0_d.h"
57 #include "vce/vce_3_0_sh_mask.h"
58
59 #include "dce/dce_10_0_d.h"
60 #include "dce/dce_10_0_sh_mask.h"
61
62 #include "vid.h"
63 #include "vi.h"
64 #include "gmc_v8_0.h"
65 #include "gmc_v7_0.h"
66 #include "gfx_v8_0.h"
67 #include "sdma_v2_4.h"
68 #include "sdma_v3_0.h"
69 #include "dce_v10_0.h"
70 #include "dce_v11_0.h"
71 #include "iceland_ih.h"
72 #include "tonga_ih.h"
73 #include "cz_ih.h"
74 #include "uvd_v5_0.h"
75 #include "uvd_v6_0.h"
76 #include "vce_v3_0.h"
77 #if defined(CONFIG_DRM_AMD_ACP)
78 #include "amdgpu_acp.h"
79 #endif
80 #include "amdgpu_vkms.h"
81 #include "mxgpu_vi.h"
82 #include "amdgpu_dm.h"
83
84 #define ixPCIE_LC_L1_PM_SUBSTATE 0x100100C6
85 #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
86 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
87 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
88 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
89 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
90 #define ixPCIE_L1_PM_SUB_CNTL 0x378
91 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
92 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
93 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
94 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
95 #define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
96 #define LINK_CAP 0x64
97 #define PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
98 #define ixCPM_CONTROL 0x1400118
99 #define ixPCIE_LC_CNTL7 0x100100BC
100 #define PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK 0x00000400L
101 #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT 0x00000007
102 #define PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT 0x00000009
103 #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L
104 #define PCIE_L1_PM_SUB_CNTL 0x378
105 #define ASIC_IS_P22(asic_type, rid) ((asic_type >= CHIP_POLARIS10) && \
106 (asic_type <= CHIP_POLARIS12) && \
107 (rid >= 0x6E))
108 /* Topaz */
109 static const struct amdgpu_video_codecs topaz_video_codecs_encode =
110 {
111 .codec_count = 0,
112 .codec_array = NULL,
113 };
114
115 /* Tonga, CZ, ST, Fiji */
116 static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] =
117 {
118 {
119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
120 .max_width = 4096,
121 .max_height = 2304,
122 .max_pixels_per_frame = 4096 * 2304,
123 .max_level = 0,
124 },
125 };
126
127 static const struct amdgpu_video_codecs tonga_video_codecs_encode =
128 {
129 .codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array),
130 .codec_array = tonga_video_codecs_encode_array,
131 };
132
133 /* Polaris */
134 static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] =
135 {
136 {
137 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
138 .max_width = 4096,
139 .max_height = 4096,
140 .max_pixels_per_frame = 4096 * 4096,
141 .max_level = 0,
142 },
143 {
144 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
145 .max_width = 4096,
146 .max_height = 4096,
147 .max_pixels_per_frame = 4096 * 4096,
148 .max_level = 0,
149 },
150 };
151
152 static const struct amdgpu_video_codecs polaris_video_codecs_encode =
153 {
154 .codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array),
155 .codec_array = polaris_video_codecs_encode_array,
156 };
157
158 /* Topaz */
159 static const struct amdgpu_video_codecs topaz_video_codecs_decode =
160 {
161 .codec_count = 0,
162 .codec_array = NULL,
163 };
164
165 /* Tonga */
166 static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
167 {
168 {
169 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
170 .max_width = 1920,
171 .max_height = 1088,
172 .max_pixels_per_frame = 1920 * 1088,
173 .max_level = 3,
174 },
175 {
176 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
177 .max_width = 1920,
178 .max_height = 1088,
179 .max_pixels_per_frame = 1920 * 1088,
180 .max_level = 5,
181 },
182 {
183 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
184 .max_width = 4096,
185 .max_height = 4096,
186 .max_pixels_per_frame = 4096 * 4096,
187 .max_level = 52,
188 },
189 {
190 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
191 .max_width = 1920,
192 .max_height = 1088,
193 .max_pixels_per_frame = 1920 * 1088,
194 .max_level = 4,
195 },
196 };
197
198 static const struct amdgpu_video_codecs tonga_video_codecs_decode =
199 {
200 .codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array),
201 .codec_array = tonga_video_codecs_decode_array,
202 };
203
204 /* CZ, ST, Fiji, Polaris */
205 static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
206 {
207 {
208 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
209 .max_width = 1920,
210 .max_height = 1088,
211 .max_pixels_per_frame = 1920 * 1088,
212 .max_level = 3,
213 },
214 {
215 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
216 .max_width = 1920,
217 .max_height = 1088,
218 .max_pixels_per_frame = 1920 * 1088,
219 .max_level = 5,
220 },
221 {
222 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
223 .max_width = 4096,
224 .max_height = 4096,
225 .max_pixels_per_frame = 4096 * 4096,
226 .max_level = 52,
227 },
228 {
229 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
230 .max_width = 1920,
231 .max_height = 1088,
232 .max_pixels_per_frame = 1920 * 1088,
233 .max_level = 4,
234 },
235 {
236 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
237 .max_width = 4096,
238 .max_height = 4096,
239 .max_pixels_per_frame = 4096 * 4096,
240 .max_level = 186,
241 },
242 };
243
244 static const struct amdgpu_video_codecs cz_video_codecs_decode =
245 {
246 .codec_count = ARRAY_SIZE(cz_video_codecs_decode_array),
247 .codec_array = cz_video_codecs_decode_array,
248 };
249
vi_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)250 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode,
251 const struct amdgpu_video_codecs **codecs)
252 {
253 switch (adev->asic_type) {
254 case CHIP_TOPAZ:
255 if (encode)
256 *codecs = &topaz_video_codecs_encode;
257 else
258 *codecs = &topaz_video_codecs_decode;
259 return 0;
260 case CHIP_TONGA:
261 if (encode)
262 *codecs = &tonga_video_codecs_encode;
263 else
264 *codecs = &tonga_video_codecs_decode;
265 return 0;
266 case CHIP_POLARIS10:
267 case CHIP_POLARIS11:
268 case CHIP_POLARIS12:
269 case CHIP_VEGAM:
270 if (encode)
271 *codecs = &polaris_video_codecs_encode;
272 else
273 *codecs = &cz_video_codecs_decode;
274 return 0;
275 case CHIP_FIJI:
276 case CHIP_CARRIZO:
277 case CHIP_STONEY:
278 if (encode)
279 *codecs = &tonga_video_codecs_encode;
280 else
281 *codecs = &cz_video_codecs_decode;
282 return 0;
283 default:
284 return -EINVAL;
285 }
286 }
287
288 /*
289 * Indirect registers accessor
290 */
vi_pcie_rreg(struct amdgpu_device * adev,u32 reg)291 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
292 {
293 unsigned long flags;
294 u32 r;
295
296 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
297 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
298 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
299 r = RREG32_NO_KIQ(mmPCIE_DATA);
300 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
301 return r;
302 }
303
vi_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)304 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
305 {
306 unsigned long flags;
307
308 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
309 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
310 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
311 WREG32_NO_KIQ(mmPCIE_DATA, v);
312 (void)RREG32_NO_KIQ(mmPCIE_DATA);
313 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
314 }
315
vi_smc_rreg(struct amdgpu_device * adev,u32 reg)316 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
317 {
318 unsigned long flags;
319 u32 r;
320
321 spin_lock_irqsave(&adev->smc_idx_lock, flags);
322 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
323 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
324 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
325 return r;
326 }
327
vi_smc_wreg(struct amdgpu_device * adev,u32 reg,u32 v)328 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
329 {
330 unsigned long flags;
331
332 spin_lock_irqsave(&adev->smc_idx_lock, flags);
333 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
334 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
335 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
336 }
337
338 /* smu_8_0_d.h */
339 #define mmMP0PUB_IND_INDEX 0x180
340 #define mmMP0PUB_IND_DATA 0x181
341
cz_smc_rreg(struct amdgpu_device * adev,u32 reg)342 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
343 {
344 unsigned long flags;
345 u32 r;
346
347 spin_lock_irqsave(&adev->smc_idx_lock, flags);
348 WREG32(mmMP0PUB_IND_INDEX, (reg));
349 r = RREG32(mmMP0PUB_IND_DATA);
350 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
351 return r;
352 }
353
cz_smc_wreg(struct amdgpu_device * adev,u32 reg,u32 v)354 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
355 {
356 unsigned long flags;
357
358 spin_lock_irqsave(&adev->smc_idx_lock, flags);
359 WREG32(mmMP0PUB_IND_INDEX, (reg));
360 WREG32(mmMP0PUB_IND_DATA, (v));
361 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
362 }
363
vi_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)364 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
365 {
366 unsigned long flags;
367 u32 r;
368
369 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
370 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
371 r = RREG32(mmUVD_CTX_DATA);
372 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
373 return r;
374 }
375
vi_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)376 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
377 {
378 unsigned long flags;
379
380 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
381 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
382 WREG32(mmUVD_CTX_DATA, (v));
383 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
384 }
385
vi_didt_rreg(struct amdgpu_device * adev,u32 reg)386 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
387 {
388 unsigned long flags;
389 u32 r;
390
391 spin_lock_irqsave(&adev->didt_idx_lock, flags);
392 WREG32(mmDIDT_IND_INDEX, (reg));
393 r = RREG32(mmDIDT_IND_DATA);
394 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
395 return r;
396 }
397
vi_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)398 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
399 {
400 unsigned long flags;
401
402 spin_lock_irqsave(&adev->didt_idx_lock, flags);
403 WREG32(mmDIDT_IND_INDEX, (reg));
404 WREG32(mmDIDT_IND_DATA, (v));
405 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
406 }
407
vi_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)408 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
409 {
410 unsigned long flags;
411 u32 r;
412
413 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
414 WREG32(mmGC_CAC_IND_INDEX, (reg));
415 r = RREG32(mmGC_CAC_IND_DATA);
416 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
417 return r;
418 }
419
vi_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)420 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
421 {
422 unsigned long flags;
423
424 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
425 WREG32(mmGC_CAC_IND_INDEX, (reg));
426 WREG32(mmGC_CAC_IND_DATA, (v));
427 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
428 }
429
430
431 static const u32 tonga_mgcg_cgcg_init[] =
432 {
433 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
434 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
435 mmPCIE_DATA, 0x000f0000, 0x00000000,
436 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
437 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
438 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
439 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
440 };
441
442 static const u32 fiji_mgcg_cgcg_init[] =
443 {
444 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
445 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
446 mmPCIE_DATA, 0x000f0000, 0x00000000,
447 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
448 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
449 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
450 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
451 };
452
453 static const u32 iceland_mgcg_cgcg_init[] =
454 {
455 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
456 mmPCIE_DATA, 0x000f0000, 0x00000000,
457 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
458 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
459 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
460 };
461
462 static const u32 cz_mgcg_cgcg_init[] =
463 {
464 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
465 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
466 mmPCIE_DATA, 0x000f0000, 0x00000000,
467 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
468 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
469 };
470
471 static const u32 stoney_mgcg_cgcg_init[] =
472 {
473 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
474 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
475 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
476 };
477
vi_init_golden_registers(struct amdgpu_device * adev)478 static void vi_init_golden_registers(struct amdgpu_device *adev)
479 {
480 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
481 mutex_lock(&adev->grbm_idx_mutex);
482
483 if (amdgpu_sriov_vf(adev)) {
484 xgpu_vi_init_golden_registers(adev);
485 mutex_unlock(&adev->grbm_idx_mutex);
486 return;
487 }
488
489 switch (adev->asic_type) {
490 case CHIP_TOPAZ:
491 amdgpu_device_program_register_sequence(adev,
492 iceland_mgcg_cgcg_init,
493 ARRAY_SIZE(iceland_mgcg_cgcg_init));
494 break;
495 case CHIP_FIJI:
496 amdgpu_device_program_register_sequence(adev,
497 fiji_mgcg_cgcg_init,
498 ARRAY_SIZE(fiji_mgcg_cgcg_init));
499 break;
500 case CHIP_TONGA:
501 amdgpu_device_program_register_sequence(adev,
502 tonga_mgcg_cgcg_init,
503 ARRAY_SIZE(tonga_mgcg_cgcg_init));
504 break;
505 case CHIP_CARRIZO:
506 amdgpu_device_program_register_sequence(adev,
507 cz_mgcg_cgcg_init,
508 ARRAY_SIZE(cz_mgcg_cgcg_init));
509 break;
510 case CHIP_STONEY:
511 amdgpu_device_program_register_sequence(adev,
512 stoney_mgcg_cgcg_init,
513 ARRAY_SIZE(stoney_mgcg_cgcg_init));
514 break;
515 case CHIP_POLARIS10:
516 case CHIP_POLARIS11:
517 case CHIP_POLARIS12:
518 case CHIP_VEGAM:
519 default:
520 break;
521 }
522 mutex_unlock(&adev->grbm_idx_mutex);
523 }
524
525 /**
526 * vi_get_xclk - get the xclk
527 *
528 * @adev: amdgpu_device pointer
529 *
530 * Returns the reference clock used by the gfx engine
531 * (VI).
532 */
vi_get_xclk(struct amdgpu_device * adev)533 static u32 vi_get_xclk(struct amdgpu_device *adev)
534 {
535 u32 reference_clock = adev->clock.spll.reference_freq;
536 u32 tmp;
537
538 if (adev->flags & AMD_IS_APU) {
539 switch (adev->asic_type) {
540 case CHIP_STONEY:
541 /* vbios says 48Mhz, but the actual freq is 100Mhz */
542 return 10000;
543 default:
544 return reference_clock;
545 }
546 }
547
548 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
549 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
550 return 1000;
551
552 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
553 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
554 return reference_clock / 4;
555
556 return reference_clock;
557 }
558
559 /**
560 * vi_srbm_select - select specific register instances
561 *
562 * @adev: amdgpu_device pointer
563 * @me: selected ME (micro engine)
564 * @pipe: pipe
565 * @queue: queue
566 * @vmid: VMID
567 *
568 * Switches the currently active registers instances. Some
569 * registers are instanced per VMID, others are instanced per
570 * me/pipe/queue combination.
571 */
vi_srbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)572 void vi_srbm_select(struct amdgpu_device *adev,
573 u32 me, u32 pipe, u32 queue, u32 vmid)
574 {
575 u32 srbm_gfx_cntl = 0;
576 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
577 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
578 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
579 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
580 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
581 }
582
vi_read_disabled_bios(struct amdgpu_device * adev)583 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
584 {
585 u32 bus_cntl;
586 u32 d1vga_control = 0;
587 u32 d2vga_control = 0;
588 u32 vga_render_control = 0;
589 u32 rom_cntl;
590 bool r;
591
592 bus_cntl = RREG32(mmBUS_CNTL);
593 if (adev->mode_info.num_crtc) {
594 d1vga_control = RREG32(mmD1VGA_CONTROL);
595 d2vga_control = RREG32(mmD2VGA_CONTROL);
596 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
597 }
598 rom_cntl = RREG32_SMC(ixROM_CNTL);
599
600 /* enable the rom */
601 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
602 if (adev->mode_info.num_crtc) {
603 /* Disable VGA mode */
604 WREG32(mmD1VGA_CONTROL,
605 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
606 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
607 WREG32(mmD2VGA_CONTROL,
608 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
609 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
610 WREG32(mmVGA_RENDER_CONTROL,
611 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
612 }
613 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
614
615 r = amdgpu_read_bios(adev);
616
617 /* restore regs */
618 WREG32(mmBUS_CNTL, bus_cntl);
619 if (adev->mode_info.num_crtc) {
620 WREG32(mmD1VGA_CONTROL, d1vga_control);
621 WREG32(mmD2VGA_CONTROL, d2vga_control);
622 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
623 }
624 WREG32_SMC(ixROM_CNTL, rom_cntl);
625 return r;
626 }
627
vi_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes)628 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
629 u8 *bios, u32 length_bytes)
630 {
631 u32 *dw_ptr;
632 unsigned long flags;
633 u32 i, length_dw;
634
635 if (bios == NULL)
636 return false;
637 if (length_bytes == 0)
638 return false;
639 /* APU vbios image is part of sbios image */
640 if (adev->flags & AMD_IS_APU)
641 return false;
642
643 dw_ptr = (u32 *)bios;
644 length_dw = ALIGN(length_bytes, 4) / 4;
645 /* take the smc lock since we are using the smc index */
646 spin_lock_irqsave(&adev->smc_idx_lock, flags);
647 /* set rom index to 0 */
648 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
649 WREG32(mmSMC_IND_DATA_11, 0);
650 /* set index to data for continous read */
651 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
652 for (i = 0; i < length_dw; i++)
653 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
654 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
655
656 return true;
657 }
658
659 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
660 {mmGRBM_STATUS},
661 {mmGRBM_STATUS2},
662 {mmGRBM_STATUS_SE0},
663 {mmGRBM_STATUS_SE1},
664 {mmGRBM_STATUS_SE2},
665 {mmGRBM_STATUS_SE3},
666 {mmSRBM_STATUS},
667 {mmSRBM_STATUS2},
668 {mmSRBM_STATUS3},
669 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
670 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
671 {mmCP_STAT},
672 {mmCP_STALLED_STAT1},
673 {mmCP_STALLED_STAT2},
674 {mmCP_STALLED_STAT3},
675 {mmCP_CPF_BUSY_STAT},
676 {mmCP_CPF_STALLED_STAT1},
677 {mmCP_CPF_STATUS},
678 {mmCP_CPC_BUSY_STAT},
679 {mmCP_CPC_STALLED_STAT1},
680 {mmCP_CPC_STATUS},
681 {mmGB_ADDR_CONFIG},
682 {mmMC_ARB_RAMCFG},
683 {mmGB_TILE_MODE0},
684 {mmGB_TILE_MODE1},
685 {mmGB_TILE_MODE2},
686 {mmGB_TILE_MODE3},
687 {mmGB_TILE_MODE4},
688 {mmGB_TILE_MODE5},
689 {mmGB_TILE_MODE6},
690 {mmGB_TILE_MODE7},
691 {mmGB_TILE_MODE8},
692 {mmGB_TILE_MODE9},
693 {mmGB_TILE_MODE10},
694 {mmGB_TILE_MODE11},
695 {mmGB_TILE_MODE12},
696 {mmGB_TILE_MODE13},
697 {mmGB_TILE_MODE14},
698 {mmGB_TILE_MODE15},
699 {mmGB_TILE_MODE16},
700 {mmGB_TILE_MODE17},
701 {mmGB_TILE_MODE18},
702 {mmGB_TILE_MODE19},
703 {mmGB_TILE_MODE20},
704 {mmGB_TILE_MODE21},
705 {mmGB_TILE_MODE22},
706 {mmGB_TILE_MODE23},
707 {mmGB_TILE_MODE24},
708 {mmGB_TILE_MODE25},
709 {mmGB_TILE_MODE26},
710 {mmGB_TILE_MODE27},
711 {mmGB_TILE_MODE28},
712 {mmGB_TILE_MODE29},
713 {mmGB_TILE_MODE30},
714 {mmGB_TILE_MODE31},
715 {mmGB_MACROTILE_MODE0},
716 {mmGB_MACROTILE_MODE1},
717 {mmGB_MACROTILE_MODE2},
718 {mmGB_MACROTILE_MODE3},
719 {mmGB_MACROTILE_MODE4},
720 {mmGB_MACROTILE_MODE5},
721 {mmGB_MACROTILE_MODE6},
722 {mmGB_MACROTILE_MODE7},
723 {mmGB_MACROTILE_MODE8},
724 {mmGB_MACROTILE_MODE9},
725 {mmGB_MACROTILE_MODE10},
726 {mmGB_MACROTILE_MODE11},
727 {mmGB_MACROTILE_MODE12},
728 {mmGB_MACROTILE_MODE13},
729 {mmGB_MACROTILE_MODE14},
730 {mmGB_MACROTILE_MODE15},
731 {mmCC_RB_BACKEND_DISABLE, true},
732 {mmGC_USER_RB_BACKEND_DISABLE, true},
733 {mmGB_BACKEND_MAP, false},
734 {mmPA_SC_RASTER_CONFIG, true},
735 {mmPA_SC_RASTER_CONFIG_1, true},
736 };
737
vi_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)738 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
739 bool indexed, u32 se_num,
740 u32 sh_num, u32 reg_offset)
741 {
742 if (indexed) {
743 uint32_t val;
744 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
745 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
746
747 switch (reg_offset) {
748 case mmCC_RB_BACKEND_DISABLE:
749 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
750 case mmGC_USER_RB_BACKEND_DISABLE:
751 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
752 case mmPA_SC_RASTER_CONFIG:
753 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
754 case mmPA_SC_RASTER_CONFIG_1:
755 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
756 }
757
758 mutex_lock(&adev->grbm_idx_mutex);
759 if (se_num != 0xffffffff || sh_num != 0xffffffff)
760 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
761
762 val = RREG32(reg_offset);
763
764 if (se_num != 0xffffffff || sh_num != 0xffffffff)
765 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
766 mutex_unlock(&adev->grbm_idx_mutex);
767 return val;
768 } else {
769 unsigned idx;
770
771 switch (reg_offset) {
772 case mmGB_ADDR_CONFIG:
773 return adev->gfx.config.gb_addr_config;
774 case mmMC_ARB_RAMCFG:
775 return adev->gfx.config.mc_arb_ramcfg;
776 case mmGB_TILE_MODE0:
777 case mmGB_TILE_MODE1:
778 case mmGB_TILE_MODE2:
779 case mmGB_TILE_MODE3:
780 case mmGB_TILE_MODE4:
781 case mmGB_TILE_MODE5:
782 case mmGB_TILE_MODE6:
783 case mmGB_TILE_MODE7:
784 case mmGB_TILE_MODE8:
785 case mmGB_TILE_MODE9:
786 case mmGB_TILE_MODE10:
787 case mmGB_TILE_MODE11:
788 case mmGB_TILE_MODE12:
789 case mmGB_TILE_MODE13:
790 case mmGB_TILE_MODE14:
791 case mmGB_TILE_MODE15:
792 case mmGB_TILE_MODE16:
793 case mmGB_TILE_MODE17:
794 case mmGB_TILE_MODE18:
795 case mmGB_TILE_MODE19:
796 case mmGB_TILE_MODE20:
797 case mmGB_TILE_MODE21:
798 case mmGB_TILE_MODE22:
799 case mmGB_TILE_MODE23:
800 case mmGB_TILE_MODE24:
801 case mmGB_TILE_MODE25:
802 case mmGB_TILE_MODE26:
803 case mmGB_TILE_MODE27:
804 case mmGB_TILE_MODE28:
805 case mmGB_TILE_MODE29:
806 case mmGB_TILE_MODE30:
807 case mmGB_TILE_MODE31:
808 idx = (reg_offset - mmGB_TILE_MODE0);
809 return adev->gfx.config.tile_mode_array[idx];
810 case mmGB_MACROTILE_MODE0:
811 case mmGB_MACROTILE_MODE1:
812 case mmGB_MACROTILE_MODE2:
813 case mmGB_MACROTILE_MODE3:
814 case mmGB_MACROTILE_MODE4:
815 case mmGB_MACROTILE_MODE5:
816 case mmGB_MACROTILE_MODE6:
817 case mmGB_MACROTILE_MODE7:
818 case mmGB_MACROTILE_MODE8:
819 case mmGB_MACROTILE_MODE9:
820 case mmGB_MACROTILE_MODE10:
821 case mmGB_MACROTILE_MODE11:
822 case mmGB_MACROTILE_MODE12:
823 case mmGB_MACROTILE_MODE13:
824 case mmGB_MACROTILE_MODE14:
825 case mmGB_MACROTILE_MODE15:
826 idx = (reg_offset - mmGB_MACROTILE_MODE0);
827 return adev->gfx.config.macrotile_mode_array[idx];
828 default:
829 return RREG32(reg_offset);
830 }
831 }
832 }
833
vi_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)834 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
835 u32 sh_num, u32 reg_offset, u32 *value)
836 {
837 uint32_t i;
838
839 *value = 0;
840 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
841 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
842
843 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
844 continue;
845
846 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
847 reg_offset);
848 return 0;
849 }
850 return -EINVAL;
851 }
852
853 /**
854 * vi_asic_pci_config_reset - soft reset GPU
855 *
856 * @adev: amdgpu_device pointer
857 *
858 * Use PCI Config method to reset the GPU.
859 *
860 * Returns 0 for success.
861 */
vi_asic_pci_config_reset(struct amdgpu_device * adev)862 static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
863 {
864 u32 i;
865 int r = -EINVAL;
866
867 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
868
869 /* disable BM */
870 pci_clear_master(adev->pdev);
871 /* reset */
872 amdgpu_device_pci_config_reset(adev);
873
874 udelay(100);
875
876 /* wait for asic to come out of reset */
877 for (i = 0; i < adev->usec_timeout; i++) {
878 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
879 /* enable BM */
880 pci_set_master(adev->pdev);
881 adev->has_hw_reset = true;
882 r = 0;
883 break;
884 }
885 udelay(1);
886 }
887
888 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
889
890 return r;
891 }
892
vi_asic_supports_baco(struct amdgpu_device * adev)893 static int vi_asic_supports_baco(struct amdgpu_device *adev)
894 {
895 switch (adev->asic_type) {
896 case CHIP_FIJI:
897 case CHIP_TONGA:
898 case CHIP_POLARIS10:
899 case CHIP_POLARIS11:
900 case CHIP_POLARIS12:
901 case CHIP_TOPAZ:
902 return amdgpu_dpm_is_baco_supported(adev);
903 default:
904 return 0;
905 }
906 }
907
908 static enum amd_reset_method
vi_asic_reset_method(struct amdgpu_device * adev)909 vi_asic_reset_method(struct amdgpu_device *adev)
910 {
911 int baco_reset;
912
913 if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
914 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
915 return amdgpu_reset_method;
916
917 if (amdgpu_reset_method != -1)
918 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
919 amdgpu_reset_method);
920
921 switch (adev->asic_type) {
922 case CHIP_FIJI:
923 case CHIP_TONGA:
924 case CHIP_POLARIS10:
925 case CHIP_POLARIS11:
926 case CHIP_POLARIS12:
927 case CHIP_TOPAZ:
928 baco_reset = amdgpu_dpm_is_baco_supported(adev);
929 break;
930 default:
931 baco_reset = 0;
932 break;
933 }
934
935 if (baco_reset)
936 return AMD_RESET_METHOD_BACO;
937 else
938 return AMD_RESET_METHOD_LEGACY;
939 }
940
941 /**
942 * vi_asic_reset - soft reset GPU
943 *
944 * @adev: amdgpu_device pointer
945 *
946 * Look up which blocks are hung and attempt
947 * to reset them.
948 * Returns 0 for success.
949 */
vi_asic_reset(struct amdgpu_device * adev)950 static int vi_asic_reset(struct amdgpu_device *adev)
951 {
952 int r;
953
954 /* APUs don't have full asic reset */
955 if (adev->flags & AMD_IS_APU)
956 return 0;
957
958 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
959 dev_info(adev->dev, "BACO reset\n");
960 r = amdgpu_dpm_baco_reset(adev);
961 } else {
962 dev_info(adev->dev, "PCI CONFIG reset\n");
963 r = vi_asic_pci_config_reset(adev);
964 }
965
966 return r;
967 }
968
vi_get_config_memsize(struct amdgpu_device * adev)969 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
970 {
971 return RREG32(mmCONFIG_MEMSIZE);
972 }
973
vi_set_uvd_clock(struct amdgpu_device * adev,u32 clock,u32 cntl_reg,u32 status_reg)974 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
975 u32 cntl_reg, u32 status_reg)
976 {
977 int r, i;
978 struct atom_clock_dividers dividers;
979 uint32_t tmp;
980
981 r = amdgpu_atombios_get_clock_dividers(adev,
982 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
983 clock, false, ÷rs);
984 if (r)
985 return r;
986
987 tmp = RREG32_SMC(cntl_reg);
988
989 if (adev->flags & AMD_IS_APU)
990 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
991 else
992 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
993 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
994 tmp |= dividers.post_divider;
995 WREG32_SMC(cntl_reg, tmp);
996
997 for (i = 0; i < 100; i++) {
998 tmp = RREG32_SMC(status_reg);
999 if (adev->flags & AMD_IS_APU) {
1000 if (tmp & 0x10000)
1001 break;
1002 } else {
1003 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1004 break;
1005 }
1006 mdelay(10);
1007 }
1008 if (i == 100)
1009 return -ETIMEDOUT;
1010 return 0;
1011 }
1012
1013 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0
1014 #define ixGNB_CLK1_STATUS 0xD822010C
1015 #define ixGNB_CLK2_DFS_CNTL 0xD8220110
1016 #define ixGNB_CLK2_STATUS 0xD822012C
1017 #define ixGNB_CLK3_DFS_CNTL 0xD8220130
1018 #define ixGNB_CLK3_STATUS 0xD822014C
1019
vi_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)1020 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1021 {
1022 int r;
1023
1024 if (adev->flags & AMD_IS_APU) {
1025 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
1026 if (r)
1027 return r;
1028
1029 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
1030 if (r)
1031 return r;
1032 } else {
1033 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1034 if (r)
1035 return r;
1036
1037 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1038 if (r)
1039 return r;
1040 }
1041
1042 return 0;
1043 }
1044
vi_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)1045 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1046 {
1047 int r, i;
1048 struct atom_clock_dividers dividers;
1049 u32 tmp;
1050 u32 reg_ctrl;
1051 u32 reg_status;
1052 u32 status_mask;
1053 u32 reg_mask;
1054
1055 if (adev->flags & AMD_IS_APU) {
1056 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
1057 reg_status = ixGNB_CLK3_STATUS;
1058 status_mask = 0x00010000;
1059 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
1060 } else {
1061 reg_ctrl = ixCG_ECLK_CNTL;
1062 reg_status = ixCG_ECLK_STATUS;
1063 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
1064 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
1065 }
1066
1067 r = amdgpu_atombios_get_clock_dividers(adev,
1068 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1069 ecclk, false, ÷rs);
1070 if (r)
1071 return r;
1072
1073 for (i = 0; i < 100; i++) {
1074 if (RREG32_SMC(reg_status) & status_mask)
1075 break;
1076 mdelay(10);
1077 }
1078
1079 if (i == 100)
1080 return -ETIMEDOUT;
1081
1082 tmp = RREG32_SMC(reg_ctrl);
1083 tmp &= ~reg_mask;
1084 tmp |= dividers.post_divider;
1085 WREG32_SMC(reg_ctrl, tmp);
1086
1087 for (i = 0; i < 100; i++) {
1088 if (RREG32_SMC(reg_status) & status_mask)
1089 break;
1090 mdelay(10);
1091 }
1092
1093 if (i == 100)
1094 return -ETIMEDOUT;
1095
1096 return 0;
1097 }
1098
vi_enable_aspm(struct amdgpu_device * adev)1099 static void vi_enable_aspm(struct amdgpu_device *adev)
1100 {
1101 u32 data, orig;
1102
1103 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1104 data |= PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT <<
1105 PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
1106 data |= PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT <<
1107 PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
1108 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1109 data |= PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK;
1110 if (orig != data)
1111 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1112 }
1113
vi_program_aspm(struct amdgpu_device * adev)1114 static void vi_program_aspm(struct amdgpu_device *adev)
1115 {
1116 u32 data, data1, orig;
1117 bool bL1SS = false;
1118 bool bClkReqSupport = true;
1119
1120 if (!amdgpu_device_should_use_aspm(adev))
1121 return;
1122
1123 if (adev->asic_type < CHIP_POLARIS10)
1124 return;
1125
1126 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1127 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
1128 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1129 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1130 if (orig != data)
1131 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1132
1133 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1134 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1135 data |= 0x0024 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT;
1136 data |= PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
1137 if (orig != data)
1138 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1139
1140 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1141 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1142 if (orig != data)
1143 WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1144
1145 orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1146 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1147 if (orig != data)
1148 WREG32_PCIE(ixPCIE_P_CNTL, data);
1149
1150 data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE);
1151 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1);
1152 if (data & PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK &&
1153 (data & (PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK |
1154 PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK |
1155 PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK |
1156 PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK))) {
1157 bL1SS = true;
1158 } else if (data1 & (PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK |
1159 PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK |
1160 PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK |
1161 PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK)) {
1162 bL1SS = true;
1163 }
1164
1165 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6);
1166 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK;
1167 if (orig != data)
1168 WREG32_PCIE(ixPCIE_LC_CNTL6, data);
1169
1170 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1171 data |= PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1172 if (orig != data)
1173 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1174
1175 pci_read_config_dword(adev->pdev, LINK_CAP, &data);
1176 if (!(data & PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK))
1177 bClkReqSupport = false;
1178
1179 if (bClkReqSupport) {
1180 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1181 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK);
1182 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1183 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
1184 if (orig != data)
1185 WREG32_SMC(ixTHM_CLK_CNTL, data);
1186
1187 orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1188 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1189 MISC_CLK_CTRL__ZCLK_SEL_MASK | MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK);
1190 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1191 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT);
1192 data |= (0x20 << MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT);
1193 if (orig != data)
1194 WREG32_SMC(ixMISC_CLK_CTRL, data);
1195
1196 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1197 data |= CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK;
1198 if (orig != data)
1199 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1200
1201 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1202 data |= CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK;
1203 if (orig != data)
1204 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1205
1206 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1207 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1208 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1209 if (orig != data)
1210 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1211
1212 orig = data = RREG32_PCIE(ixCPM_CONTROL);
1213 data |= (CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK |
1214 CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK);
1215 if (orig != data)
1216 WREG32_PCIE(ixCPM_CONTROL, data);
1217
1218 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL);
1219 data &= ~PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK;
1220 data |= (0xE << PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT);
1221 if (orig != data)
1222 WREG32_PCIE(ixPCIE_CONFIG_CNTL, data);
1223
1224 orig = data = RREG32(mmBIF_CLK_CTRL);
1225 data |= BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK;
1226 if (orig != data)
1227 WREG32(mmBIF_CLK_CTRL, data);
1228
1229 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL7);
1230 data |= PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK;
1231 if (orig != data)
1232 WREG32_PCIE(ixPCIE_LC_CNTL7, data);
1233
1234 orig = data = RREG32_PCIE(ixPCIE_HW_DEBUG);
1235 data |= PCIE_HW_DEBUG__HW_01_DEBUG_MASK;
1236 if (orig != data)
1237 WREG32_PCIE(ixPCIE_HW_DEBUG, data);
1238
1239 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1240 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
1241 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK;
1242 if (bL1SS)
1243 data &= ~PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK;
1244 if (orig != data)
1245 WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1246
1247 }
1248
1249 vi_enable_aspm(adev);
1250
1251 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1252 data1 = RREG32_PCIE(ixPCIE_LC_STATUS1);
1253 if (((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) &&
1254 data1 & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK &&
1255 data1 & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK) {
1256 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1257 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1258 if (orig != data)
1259 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1260 }
1261
1262 if ((adev->asic_type == CHIP_POLARIS12 &&
1263 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) ||
1264 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) {
1265 orig = data = RREG32_PCIE(ixPCIE_LC_TRAINING_CNTL);
1266 data &= ~PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK;
1267 if (orig != data)
1268 WREG32_PCIE(ixPCIE_LC_TRAINING_CNTL, data);
1269 }
1270 }
1271
vi_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)1272 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1273 bool enable)
1274 {
1275 u32 tmp;
1276
1277 /* not necessary on CZ */
1278 if (adev->flags & AMD_IS_APU)
1279 return;
1280
1281 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1282 if (enable)
1283 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1284 else
1285 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1286
1287 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1288 }
1289
1290 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1291 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1292 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1293
vi_get_rev_id(struct amdgpu_device * adev)1294 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1295 {
1296 if (adev->flags & AMD_IS_APU)
1297 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1298 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1299 else
1300 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1301 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1302 }
1303
vi_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)1304 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1305 {
1306 if (!ring || !ring->funcs->emit_wreg) {
1307 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1308 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1309 } else {
1310 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1311 }
1312 }
1313
vi_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)1314 static void vi_invalidate_hdp(struct amdgpu_device *adev,
1315 struct amdgpu_ring *ring)
1316 {
1317 if (!ring || !ring->funcs->emit_wreg) {
1318 WREG32(mmHDP_DEBUG0, 1);
1319 RREG32(mmHDP_DEBUG0);
1320 } else {
1321 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
1322 }
1323 }
1324
vi_need_full_reset(struct amdgpu_device * adev)1325 static bool vi_need_full_reset(struct amdgpu_device *adev)
1326 {
1327 switch (adev->asic_type) {
1328 case CHIP_CARRIZO:
1329 case CHIP_STONEY:
1330 /* CZ has hang issues with full reset at the moment */
1331 return false;
1332 case CHIP_FIJI:
1333 case CHIP_TONGA:
1334 /* XXX: soft reset should work on fiji and tonga */
1335 return true;
1336 case CHIP_POLARIS10:
1337 case CHIP_POLARIS11:
1338 case CHIP_POLARIS12:
1339 case CHIP_TOPAZ:
1340 default:
1341 /* change this when we support soft reset */
1342 return true;
1343 }
1344 }
1345
vi_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)1346 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1347 uint64_t *count1)
1348 {
1349 uint32_t perfctr = 0;
1350 uint64_t cnt0_of, cnt1_of;
1351 int tmp;
1352
1353 /* This reports 0 on APUs, so return to avoid writing/reading registers
1354 * that may or may not be different from their GPU counterparts
1355 */
1356 if (adev->flags & AMD_IS_APU)
1357 return;
1358
1359 /* Set the 2 events that we wish to watch, defined above */
1360 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1361 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1362 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1363
1364 /* Write to enable desired perf counters */
1365 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1366 /* Zero out and enable the perf counters
1367 * Write 0x5:
1368 * Bit 0 = Start all counters(1)
1369 * Bit 2 = Global counter reset enable(1)
1370 */
1371 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1372
1373 msleep(1000);
1374
1375 /* Load the shadow and disable the perf counters
1376 * Write 0x2:
1377 * Bit 0 = Stop counters(0)
1378 * Bit 1 = Load the shadow counters(1)
1379 */
1380 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1381
1382 /* Read register values to get any >32bit overflow */
1383 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1384 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1385 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1386
1387 /* Get the values and add the overflow */
1388 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1389 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1390 }
1391
vi_get_pcie_replay_count(struct amdgpu_device * adev)1392 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1393 {
1394 uint64_t nak_r, nak_g;
1395
1396 /* Get the number of NAKs received and generated */
1397 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1398 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1399
1400 /* Add the total number of NAKs, i.e the number of replays */
1401 return (nak_r + nak_g);
1402 }
1403
vi_need_reset_on_init(struct amdgpu_device * adev)1404 static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1405 {
1406 u32 clock_cntl, pc;
1407
1408 if (adev->flags & AMD_IS_APU)
1409 return false;
1410
1411 /* check if the SMC is already running */
1412 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1413 pc = RREG32_SMC(ixSMC_PC_C);
1414 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1415 (0x20100 <= pc))
1416 return true;
1417
1418 return false;
1419 }
1420
vi_pre_asic_init(struct amdgpu_device * adev)1421 static void vi_pre_asic_init(struct amdgpu_device *adev)
1422 {
1423 }
1424
1425 static const struct amdgpu_asic_funcs vi_asic_funcs =
1426 {
1427 .read_disabled_bios = &vi_read_disabled_bios,
1428 .read_bios_from_rom = &vi_read_bios_from_rom,
1429 .read_register = &vi_read_register,
1430 .reset = &vi_asic_reset,
1431 .reset_method = &vi_asic_reset_method,
1432 .get_xclk = &vi_get_xclk,
1433 .set_uvd_clocks = &vi_set_uvd_clocks,
1434 .set_vce_clocks = &vi_set_vce_clocks,
1435 .get_config_memsize = &vi_get_config_memsize,
1436 .flush_hdp = &vi_flush_hdp,
1437 .invalidate_hdp = &vi_invalidate_hdp,
1438 .need_full_reset = &vi_need_full_reset,
1439 .init_doorbell_index = &legacy_doorbell_index_init,
1440 .get_pcie_usage = &vi_get_pcie_usage,
1441 .need_reset_on_init = &vi_need_reset_on_init,
1442 .get_pcie_replay_count = &vi_get_pcie_replay_count,
1443 .supports_baco = &vi_asic_supports_baco,
1444 .pre_asic_init = &vi_pre_asic_init,
1445 .query_video_codecs = &vi_query_video_codecs,
1446 };
1447
1448 #define CZ_REV_BRISTOL(rev) \
1449 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1450
vi_common_early_init(struct amdgpu_ip_block * ip_block)1451 static int vi_common_early_init(struct amdgpu_ip_block *ip_block)
1452 {
1453 struct amdgpu_device *adev = ip_block->adev;
1454
1455 if (adev->flags & AMD_IS_APU) {
1456 adev->smc_rreg = &cz_smc_rreg;
1457 adev->smc_wreg = &cz_smc_wreg;
1458 } else {
1459 adev->smc_rreg = &vi_smc_rreg;
1460 adev->smc_wreg = &vi_smc_wreg;
1461 }
1462 adev->pcie_rreg = &vi_pcie_rreg;
1463 adev->pcie_wreg = &vi_pcie_wreg;
1464 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1465 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1466 adev->didt_rreg = &vi_didt_rreg;
1467 adev->didt_wreg = &vi_didt_wreg;
1468 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1469 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1470
1471 adev->asic_funcs = &vi_asic_funcs;
1472
1473 adev->rev_id = vi_get_rev_id(adev);
1474 adev->external_rev_id = 0xFF;
1475 switch (adev->asic_type) {
1476 case CHIP_TOPAZ:
1477 adev->cg_flags = 0;
1478 adev->pg_flags = 0;
1479 adev->external_rev_id = 0x1;
1480 break;
1481 case CHIP_FIJI:
1482 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1483 AMD_CG_SUPPORT_GFX_MGLS |
1484 AMD_CG_SUPPORT_GFX_RLC_LS |
1485 AMD_CG_SUPPORT_GFX_CP_LS |
1486 AMD_CG_SUPPORT_GFX_CGTS |
1487 AMD_CG_SUPPORT_GFX_CGTS_LS |
1488 AMD_CG_SUPPORT_GFX_CGCG |
1489 AMD_CG_SUPPORT_GFX_CGLS |
1490 AMD_CG_SUPPORT_SDMA_MGCG |
1491 AMD_CG_SUPPORT_SDMA_LS |
1492 AMD_CG_SUPPORT_BIF_LS |
1493 AMD_CG_SUPPORT_HDP_MGCG |
1494 AMD_CG_SUPPORT_HDP_LS |
1495 AMD_CG_SUPPORT_ROM_MGCG |
1496 AMD_CG_SUPPORT_MC_MGCG |
1497 AMD_CG_SUPPORT_MC_LS |
1498 AMD_CG_SUPPORT_UVD_MGCG;
1499 adev->pg_flags = 0;
1500 adev->external_rev_id = adev->rev_id + 0x3c;
1501 break;
1502 case CHIP_TONGA:
1503 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1504 AMD_CG_SUPPORT_GFX_CGCG |
1505 AMD_CG_SUPPORT_GFX_CGLS |
1506 AMD_CG_SUPPORT_SDMA_MGCG |
1507 AMD_CG_SUPPORT_SDMA_LS |
1508 AMD_CG_SUPPORT_BIF_LS |
1509 AMD_CG_SUPPORT_HDP_MGCG |
1510 AMD_CG_SUPPORT_HDP_LS |
1511 AMD_CG_SUPPORT_ROM_MGCG |
1512 AMD_CG_SUPPORT_MC_MGCG |
1513 AMD_CG_SUPPORT_MC_LS |
1514 AMD_CG_SUPPORT_DRM_LS |
1515 AMD_CG_SUPPORT_UVD_MGCG;
1516 adev->pg_flags = 0;
1517 adev->external_rev_id = adev->rev_id + 0x14;
1518 break;
1519 case CHIP_POLARIS11:
1520 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1521 AMD_CG_SUPPORT_GFX_RLC_LS |
1522 AMD_CG_SUPPORT_GFX_CP_LS |
1523 AMD_CG_SUPPORT_GFX_CGCG |
1524 AMD_CG_SUPPORT_GFX_CGLS |
1525 AMD_CG_SUPPORT_GFX_3D_CGCG |
1526 AMD_CG_SUPPORT_GFX_3D_CGLS |
1527 AMD_CG_SUPPORT_SDMA_MGCG |
1528 AMD_CG_SUPPORT_SDMA_LS |
1529 AMD_CG_SUPPORT_BIF_MGCG |
1530 AMD_CG_SUPPORT_BIF_LS |
1531 AMD_CG_SUPPORT_HDP_MGCG |
1532 AMD_CG_SUPPORT_HDP_LS |
1533 AMD_CG_SUPPORT_ROM_MGCG |
1534 AMD_CG_SUPPORT_MC_MGCG |
1535 AMD_CG_SUPPORT_MC_LS |
1536 AMD_CG_SUPPORT_DRM_LS |
1537 AMD_CG_SUPPORT_UVD_MGCG |
1538 AMD_CG_SUPPORT_VCE_MGCG;
1539 adev->pg_flags = 0;
1540 adev->external_rev_id = adev->rev_id + 0x5A;
1541 break;
1542 case CHIP_POLARIS10:
1543 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1544 AMD_CG_SUPPORT_GFX_RLC_LS |
1545 AMD_CG_SUPPORT_GFX_CP_LS |
1546 AMD_CG_SUPPORT_GFX_CGCG |
1547 AMD_CG_SUPPORT_GFX_CGLS |
1548 AMD_CG_SUPPORT_GFX_3D_CGCG |
1549 AMD_CG_SUPPORT_GFX_3D_CGLS |
1550 AMD_CG_SUPPORT_SDMA_MGCG |
1551 AMD_CG_SUPPORT_SDMA_LS |
1552 AMD_CG_SUPPORT_BIF_MGCG |
1553 AMD_CG_SUPPORT_BIF_LS |
1554 AMD_CG_SUPPORT_HDP_MGCG |
1555 AMD_CG_SUPPORT_HDP_LS |
1556 AMD_CG_SUPPORT_ROM_MGCG |
1557 AMD_CG_SUPPORT_MC_MGCG |
1558 AMD_CG_SUPPORT_MC_LS |
1559 AMD_CG_SUPPORT_DRM_LS |
1560 AMD_CG_SUPPORT_UVD_MGCG |
1561 AMD_CG_SUPPORT_VCE_MGCG;
1562 adev->pg_flags = 0;
1563 adev->external_rev_id = adev->rev_id + 0x50;
1564 break;
1565 case CHIP_POLARIS12:
1566 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1567 AMD_CG_SUPPORT_GFX_RLC_LS |
1568 AMD_CG_SUPPORT_GFX_CP_LS |
1569 AMD_CG_SUPPORT_GFX_CGCG |
1570 AMD_CG_SUPPORT_GFX_CGLS |
1571 AMD_CG_SUPPORT_GFX_3D_CGCG |
1572 AMD_CG_SUPPORT_GFX_3D_CGLS |
1573 AMD_CG_SUPPORT_SDMA_MGCG |
1574 AMD_CG_SUPPORT_SDMA_LS |
1575 AMD_CG_SUPPORT_BIF_MGCG |
1576 AMD_CG_SUPPORT_BIF_LS |
1577 AMD_CG_SUPPORT_HDP_MGCG |
1578 AMD_CG_SUPPORT_HDP_LS |
1579 AMD_CG_SUPPORT_ROM_MGCG |
1580 AMD_CG_SUPPORT_MC_MGCG |
1581 AMD_CG_SUPPORT_MC_LS |
1582 AMD_CG_SUPPORT_DRM_LS |
1583 AMD_CG_SUPPORT_UVD_MGCG |
1584 AMD_CG_SUPPORT_VCE_MGCG;
1585 adev->pg_flags = 0;
1586 adev->external_rev_id = adev->rev_id + 0x64;
1587 break;
1588 case CHIP_VEGAM:
1589 adev->cg_flags = 0;
1590 /*AMD_CG_SUPPORT_GFX_MGCG |
1591 AMD_CG_SUPPORT_GFX_RLC_LS |
1592 AMD_CG_SUPPORT_GFX_CP_LS |
1593 AMD_CG_SUPPORT_GFX_CGCG |
1594 AMD_CG_SUPPORT_GFX_CGLS |
1595 AMD_CG_SUPPORT_GFX_3D_CGCG |
1596 AMD_CG_SUPPORT_GFX_3D_CGLS |
1597 AMD_CG_SUPPORT_SDMA_MGCG |
1598 AMD_CG_SUPPORT_SDMA_LS |
1599 AMD_CG_SUPPORT_BIF_MGCG |
1600 AMD_CG_SUPPORT_BIF_LS |
1601 AMD_CG_SUPPORT_HDP_MGCG |
1602 AMD_CG_SUPPORT_HDP_LS |
1603 AMD_CG_SUPPORT_ROM_MGCG |
1604 AMD_CG_SUPPORT_MC_MGCG |
1605 AMD_CG_SUPPORT_MC_LS |
1606 AMD_CG_SUPPORT_DRM_LS |
1607 AMD_CG_SUPPORT_UVD_MGCG |
1608 AMD_CG_SUPPORT_VCE_MGCG;*/
1609 adev->pg_flags = 0;
1610 adev->external_rev_id = adev->rev_id + 0x6E;
1611 break;
1612 case CHIP_CARRIZO:
1613 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1614 AMD_CG_SUPPORT_GFX_MGCG |
1615 AMD_CG_SUPPORT_GFX_MGLS |
1616 AMD_CG_SUPPORT_GFX_RLC_LS |
1617 AMD_CG_SUPPORT_GFX_CP_LS |
1618 AMD_CG_SUPPORT_GFX_CGTS |
1619 AMD_CG_SUPPORT_GFX_CGTS_LS |
1620 AMD_CG_SUPPORT_GFX_CGCG |
1621 AMD_CG_SUPPORT_GFX_CGLS |
1622 AMD_CG_SUPPORT_BIF_LS |
1623 AMD_CG_SUPPORT_HDP_MGCG |
1624 AMD_CG_SUPPORT_HDP_LS |
1625 AMD_CG_SUPPORT_SDMA_MGCG |
1626 AMD_CG_SUPPORT_SDMA_LS |
1627 AMD_CG_SUPPORT_VCE_MGCG;
1628 /* rev0 hardware requires workarounds to support PG */
1629 adev->pg_flags = 0;
1630 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1631 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1632 AMD_PG_SUPPORT_GFX_PIPELINE |
1633 AMD_PG_SUPPORT_CP |
1634 AMD_PG_SUPPORT_UVD |
1635 AMD_PG_SUPPORT_VCE;
1636 }
1637 adev->external_rev_id = adev->rev_id + 0x1;
1638 break;
1639 case CHIP_STONEY:
1640 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1641 AMD_CG_SUPPORT_GFX_MGCG |
1642 AMD_CG_SUPPORT_GFX_MGLS |
1643 AMD_CG_SUPPORT_GFX_RLC_LS |
1644 AMD_CG_SUPPORT_GFX_CP_LS |
1645 AMD_CG_SUPPORT_GFX_CGTS |
1646 AMD_CG_SUPPORT_GFX_CGTS_LS |
1647 AMD_CG_SUPPORT_GFX_CGLS |
1648 AMD_CG_SUPPORT_BIF_LS |
1649 AMD_CG_SUPPORT_HDP_MGCG |
1650 AMD_CG_SUPPORT_HDP_LS |
1651 AMD_CG_SUPPORT_SDMA_MGCG |
1652 AMD_CG_SUPPORT_SDMA_LS |
1653 AMD_CG_SUPPORT_VCE_MGCG;
1654 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1655 AMD_PG_SUPPORT_GFX_SMG |
1656 AMD_PG_SUPPORT_GFX_PIPELINE |
1657 AMD_PG_SUPPORT_CP |
1658 AMD_PG_SUPPORT_UVD |
1659 AMD_PG_SUPPORT_VCE;
1660 adev->external_rev_id = adev->rev_id + 0x61;
1661 break;
1662 default:
1663 /* FIXME: not supported yet */
1664 return -EINVAL;
1665 }
1666
1667 if (amdgpu_sriov_vf(adev)) {
1668 amdgpu_virt_init_setting(adev);
1669 xgpu_vi_mailbox_set_irq_funcs(adev);
1670 }
1671
1672 return 0;
1673 }
1674
vi_common_late_init(struct amdgpu_ip_block * ip_block)1675 static int vi_common_late_init(struct amdgpu_ip_block *ip_block)
1676 {
1677 struct amdgpu_device *adev = ip_block->adev;
1678
1679 if (amdgpu_sriov_vf(adev))
1680 xgpu_vi_mailbox_get_irq(adev);
1681
1682 return 0;
1683 }
1684
vi_common_sw_init(struct amdgpu_ip_block * ip_block)1685 static int vi_common_sw_init(struct amdgpu_ip_block *ip_block)
1686 {
1687 struct amdgpu_device *adev = ip_block->adev;
1688
1689 if (amdgpu_sriov_vf(adev))
1690 xgpu_vi_mailbox_add_irq_id(adev);
1691
1692 return 0;
1693 }
1694
vi_common_hw_init(struct amdgpu_ip_block * ip_block)1695 static int vi_common_hw_init(struct amdgpu_ip_block *ip_block)
1696 {
1697 struct amdgpu_device *adev = ip_block->adev;
1698
1699 /* move the golden regs per IP block */
1700 vi_init_golden_registers(adev);
1701 /* enable aspm */
1702 vi_program_aspm(adev);
1703 /* enable the doorbell aperture */
1704 vi_enable_doorbell_aperture(adev, true);
1705
1706 return 0;
1707 }
1708
vi_common_hw_fini(struct amdgpu_ip_block * ip_block)1709 static int vi_common_hw_fini(struct amdgpu_ip_block *ip_block)
1710 {
1711 struct amdgpu_device *adev = ip_block->adev;
1712
1713 /* enable the doorbell aperture */
1714 vi_enable_doorbell_aperture(adev, false);
1715
1716 if (amdgpu_sriov_vf(adev))
1717 xgpu_vi_mailbox_put_irq(adev);
1718
1719 return 0;
1720 }
1721
vi_common_suspend(struct amdgpu_ip_block * ip_block)1722 static int vi_common_suspend(struct amdgpu_ip_block *ip_block)
1723 {
1724 return vi_common_hw_fini(ip_block);
1725 }
1726
vi_common_resume(struct amdgpu_ip_block * ip_block)1727 static int vi_common_resume(struct amdgpu_ip_block *ip_block)
1728 {
1729 return vi_common_hw_init(ip_block);
1730 }
1731
vi_common_is_idle(void * handle)1732 static bool vi_common_is_idle(void *handle)
1733 {
1734 return true;
1735 }
1736
vi_update_bif_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1737 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1738 bool enable)
1739 {
1740 uint32_t temp, data;
1741
1742 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1743
1744 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1745 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1746 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1747 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1748 else
1749 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1750 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1751 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1752
1753 if (temp != data)
1754 WREG32_PCIE(ixPCIE_CNTL2, data);
1755 }
1756
vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1757 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1758 bool enable)
1759 {
1760 uint32_t temp, data;
1761
1762 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1763
1764 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1765 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1766 else
1767 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1768
1769 if (temp != data)
1770 WREG32(mmHDP_HOST_PATH_CNTL, data);
1771 }
1772
vi_update_hdp_light_sleep(struct amdgpu_device * adev,bool enable)1773 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1774 bool enable)
1775 {
1776 uint32_t temp, data;
1777
1778 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1779
1780 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1781 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1782 else
1783 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1784
1785 if (temp != data)
1786 WREG32(mmHDP_MEM_POWER_LS, data);
1787 }
1788
vi_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)1789 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1790 bool enable)
1791 {
1792 uint32_t temp, data;
1793
1794 temp = data = RREG32(0x157a);
1795
1796 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1797 data |= 1;
1798 else
1799 data &= ~1;
1800
1801 if (temp != data)
1802 WREG32(0x157a, data);
1803 }
1804
1805
vi_update_rom_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1806 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1807 bool enable)
1808 {
1809 uint32_t temp, data;
1810
1811 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1812
1813 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1814 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1815 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1816 else
1817 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1818 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1819
1820 if (temp != data)
1821 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1822 }
1823
vi_common_set_clockgating_state_by_smu(void * handle,enum amd_clockgating_state state)1824 static int vi_common_set_clockgating_state_by_smu(void *handle,
1825 enum amd_clockgating_state state)
1826 {
1827 uint32_t msg_id, pp_state = 0;
1828 uint32_t pp_support_state = 0;
1829 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1830
1831 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1832 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1833 pp_support_state = PP_STATE_SUPPORT_LS;
1834 pp_state = PP_STATE_LS;
1835 }
1836 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1837 pp_support_state |= PP_STATE_SUPPORT_CG;
1838 pp_state |= PP_STATE_CG;
1839 }
1840 if (state == AMD_CG_STATE_UNGATE)
1841 pp_state = 0;
1842 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1843 PP_BLOCK_SYS_MC,
1844 pp_support_state,
1845 pp_state);
1846 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1847 }
1848
1849 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1850 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1851 pp_support_state = PP_STATE_SUPPORT_LS;
1852 pp_state = PP_STATE_LS;
1853 }
1854 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1855 pp_support_state |= PP_STATE_SUPPORT_CG;
1856 pp_state |= PP_STATE_CG;
1857 }
1858 if (state == AMD_CG_STATE_UNGATE)
1859 pp_state = 0;
1860 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1861 PP_BLOCK_SYS_SDMA,
1862 pp_support_state,
1863 pp_state);
1864 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1865 }
1866
1867 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1868 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1869 pp_support_state = PP_STATE_SUPPORT_LS;
1870 pp_state = PP_STATE_LS;
1871 }
1872 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1873 pp_support_state |= PP_STATE_SUPPORT_CG;
1874 pp_state |= PP_STATE_CG;
1875 }
1876 if (state == AMD_CG_STATE_UNGATE)
1877 pp_state = 0;
1878 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1879 PP_BLOCK_SYS_HDP,
1880 pp_support_state,
1881 pp_state);
1882 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1883 }
1884
1885
1886 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1887 if (state == AMD_CG_STATE_UNGATE)
1888 pp_state = 0;
1889 else
1890 pp_state = PP_STATE_LS;
1891
1892 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1893 PP_BLOCK_SYS_BIF,
1894 PP_STATE_SUPPORT_LS,
1895 pp_state);
1896 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1897 }
1898 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1899 if (state == AMD_CG_STATE_UNGATE)
1900 pp_state = 0;
1901 else
1902 pp_state = PP_STATE_CG;
1903
1904 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1905 PP_BLOCK_SYS_BIF,
1906 PP_STATE_SUPPORT_CG,
1907 pp_state);
1908 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1909 }
1910
1911 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1912
1913 if (state == AMD_CG_STATE_UNGATE)
1914 pp_state = 0;
1915 else
1916 pp_state = PP_STATE_LS;
1917
1918 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1919 PP_BLOCK_SYS_DRM,
1920 PP_STATE_SUPPORT_LS,
1921 pp_state);
1922 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1923 }
1924
1925 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1926
1927 if (state == AMD_CG_STATE_UNGATE)
1928 pp_state = 0;
1929 else
1930 pp_state = PP_STATE_CG;
1931
1932 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1933 PP_BLOCK_SYS_ROM,
1934 PP_STATE_SUPPORT_CG,
1935 pp_state);
1936 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1937 }
1938 return 0;
1939 }
1940
vi_common_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1941 static int vi_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1942 enum amd_clockgating_state state)
1943 {
1944 struct amdgpu_device *adev = ip_block->adev;
1945
1946 if (amdgpu_sriov_vf(adev))
1947 return 0;
1948
1949 switch (adev->asic_type) {
1950 case CHIP_FIJI:
1951 vi_update_bif_medium_grain_light_sleep(adev,
1952 state == AMD_CG_STATE_GATE);
1953 vi_update_hdp_medium_grain_clock_gating(adev,
1954 state == AMD_CG_STATE_GATE);
1955 vi_update_hdp_light_sleep(adev,
1956 state == AMD_CG_STATE_GATE);
1957 vi_update_rom_medium_grain_clock_gating(adev,
1958 state == AMD_CG_STATE_GATE);
1959 break;
1960 case CHIP_CARRIZO:
1961 case CHIP_STONEY:
1962 vi_update_bif_medium_grain_light_sleep(adev,
1963 state == AMD_CG_STATE_GATE);
1964 vi_update_hdp_medium_grain_clock_gating(adev,
1965 state == AMD_CG_STATE_GATE);
1966 vi_update_hdp_light_sleep(adev,
1967 state == AMD_CG_STATE_GATE);
1968 vi_update_drm_light_sleep(adev,
1969 state == AMD_CG_STATE_GATE);
1970 break;
1971 case CHIP_TONGA:
1972 case CHIP_POLARIS10:
1973 case CHIP_POLARIS11:
1974 case CHIP_POLARIS12:
1975 case CHIP_VEGAM:
1976 vi_common_set_clockgating_state_by_smu(adev, state);
1977 break;
1978 default:
1979 break;
1980 }
1981 return 0;
1982 }
1983
vi_common_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)1984 static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1985 enum amd_powergating_state state)
1986 {
1987 return 0;
1988 }
1989
vi_common_get_clockgating_state(void * handle,u64 * flags)1990 static void vi_common_get_clockgating_state(void *handle, u64 *flags)
1991 {
1992 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1993 int data;
1994
1995 if (amdgpu_sriov_vf(adev))
1996 *flags = 0;
1997
1998 /* AMD_CG_SUPPORT_BIF_LS */
1999 data = RREG32_PCIE(ixPCIE_CNTL2);
2000 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
2001 *flags |= AMD_CG_SUPPORT_BIF_LS;
2002
2003 /* AMD_CG_SUPPORT_HDP_LS */
2004 data = RREG32(mmHDP_MEM_POWER_LS);
2005 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
2006 *flags |= AMD_CG_SUPPORT_HDP_LS;
2007
2008 /* AMD_CG_SUPPORT_HDP_MGCG */
2009 data = RREG32(mmHDP_HOST_PATH_CNTL);
2010 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
2011 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
2012
2013 /* AMD_CG_SUPPORT_ROM_MGCG */
2014 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
2015 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
2016 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
2017 }
2018
2019 static const struct amd_ip_funcs vi_common_ip_funcs = {
2020 .name = "vi_common",
2021 .early_init = vi_common_early_init,
2022 .late_init = vi_common_late_init,
2023 .sw_init = vi_common_sw_init,
2024 .hw_init = vi_common_hw_init,
2025 .hw_fini = vi_common_hw_fini,
2026 .suspend = vi_common_suspend,
2027 .resume = vi_common_resume,
2028 .is_idle = vi_common_is_idle,
2029 .set_clockgating_state = vi_common_set_clockgating_state,
2030 .set_powergating_state = vi_common_set_powergating_state,
2031 .get_clockgating_state = vi_common_get_clockgating_state,
2032 };
2033
2034 static const struct amdgpu_ip_block_version vi_common_ip_block =
2035 {
2036 .type = AMD_IP_BLOCK_TYPE_COMMON,
2037 .major = 1,
2038 .minor = 0,
2039 .rev = 0,
2040 .funcs = &vi_common_ip_funcs,
2041 };
2042
vi_set_virt_ops(struct amdgpu_device * adev)2043 void vi_set_virt_ops(struct amdgpu_device *adev)
2044 {
2045 adev->virt.ops = &xgpu_vi_virt_ops;
2046 }
2047
vi_set_ip_blocks(struct amdgpu_device * adev)2048 int vi_set_ip_blocks(struct amdgpu_device *adev)
2049 {
2050 amdgpu_device_set_sriov_virtual_display(adev);
2051
2052 switch (adev->asic_type) {
2053 case CHIP_TOPAZ:
2054 /* topaz has no DCE, UVD, VCE */
2055 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2056 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
2057 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
2058 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2059 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
2060 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2061 if (adev->enable_virtual_display)
2062 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2063 break;
2064 case CHIP_FIJI:
2065 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2066 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
2067 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2068 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2069 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2070 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2071 if (adev->enable_virtual_display)
2072 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2073 #if defined(CONFIG_DRM_AMD_DC)
2074 else if (amdgpu_device_has_dc_support(adev))
2075 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2076 #endif
2077 else
2078 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
2079 if (!amdgpu_sriov_vf(adev)) {
2080 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
2081 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
2082 }
2083 break;
2084 case CHIP_TONGA:
2085 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2086 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2087 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2088 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2089 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2090 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2091 if (adev->enable_virtual_display)
2092 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2093 #if defined(CONFIG_DRM_AMD_DC)
2094 else if (amdgpu_device_has_dc_support(adev))
2095 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2096 #endif
2097 else
2098 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
2099 if (!amdgpu_sriov_vf(adev)) {
2100 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
2101 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
2102 }
2103 break;
2104 case CHIP_POLARIS10:
2105 case CHIP_POLARIS11:
2106 case CHIP_POLARIS12:
2107 case CHIP_VEGAM:
2108 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2109 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
2110 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2111 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2112 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
2113 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2114 if (adev->enable_virtual_display)
2115 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2116 #if defined(CONFIG_DRM_AMD_DC)
2117 else if (amdgpu_device_has_dc_support(adev))
2118 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2119 #endif
2120 else
2121 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
2122 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
2123 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
2124 break;
2125 case CHIP_CARRIZO:
2126 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2127 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2128 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
2129 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2130 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2131 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2132 if (adev->enable_virtual_display)
2133 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2134 #if defined(CONFIG_DRM_AMD_DC)
2135 else if (amdgpu_device_has_dc_support(adev))
2136 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2137 #endif
2138 else
2139 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2140 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
2141 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
2142 #if defined(CONFIG_DRM_AMD_ACP)
2143 amdgpu_device_ip_block_add(adev, &acp_ip_block);
2144 #endif
2145 break;
2146 case CHIP_STONEY:
2147 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2148 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2149 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
2150 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
2151 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2152 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2153 if (adev->enable_virtual_display)
2154 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2155 #if defined(CONFIG_DRM_AMD_DC)
2156 else if (amdgpu_device_has_dc_support(adev))
2157 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2158 #endif
2159 else
2160 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2161 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
2162 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
2163 #if defined(CONFIG_DRM_AMD_ACP)
2164 amdgpu_device_ip_block_add(adev, &acp_ip_block);
2165 #endif
2166 break;
2167 default:
2168 /* FIXME: not supported yet */
2169 return -EINVAL;
2170 }
2171
2172 return 0;
2173 }
2174
legacy_doorbell_index_init(struct amdgpu_device * adev)2175 void legacy_doorbell_index_init(struct amdgpu_device *adev)
2176 {
2177 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
2178 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
2179 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
2180 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
2181 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
2182 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
2183 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
2184 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
2185 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
2186 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
2187 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
2188 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
2189 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
2190 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
2191 }
2192