1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 /*
37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44 /*
45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that
46 * combines a tri-speed ethernet MAC and PHY, with the following
47 * features:
48 *
49 * o Jumbo frame support up to 16K
50 * o Transmit and receive flow control
51 * o IPv4 checksum offload
52 * o VLAN tag insertion and stripping
53 * o TCP large send
54 * o 64-bit multicast hash table filter
55 * o 64 entry CAM filter
56 * o 16K RX FIFO and 48K TX FIFO memory
57 * o Interrupt moderation
58 *
59 * The VT6122 supports up to four transmit DMA queues. The descriptors
60 * in the transmit ring can address up to 7 data fragments; frames which
61 * span more than 7 data buffers must be coalesced, but in general the
62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
63 * long. The receive descriptors address only a single buffer.
64 *
65 * There are two peculiar design issues with the VT6122. One is that
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
68 * systems, but on architectures that generate unaligned access traps, we
69 * have to do some copying.
70 *
71 * The other issue has to do with the way 64-bit addresses are handled.
72 * The DMA descriptors only allow you to specify 48 bits of addressing
73 * information. The remaining 16 bits are specified using one of the
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
76 * memory, you must have to make sure your network data buffers reside
77 * in the same 48-bit 'segment.'
78 *
79 * Special thanks to Ryan Fu at VIA Networking for providing documentation
80 * and sample NICs for testing.
81 */
82
83 #ifdef HAVE_KERNEL_OPTION_HEADERS
84 #include "opt_device_polling.h"
85 #endif
86
87 #include <sys/param.h>
88 #include <sys/endian.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
91 #include <sys/mbuf.h>
92 #include <sys/malloc.h>
93 #include <sys/module.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/sysctl.h>
97
98 #include <net/if.h>
99 #include <net/if_arp.h>
100 #include <net/ethernet.h>
101 #include <net/if_dl.h>
102 #include <net/if_var.h>
103 #include <net/if_media.h>
104 #include <net/if_types.h>
105 #include <net/if_vlan_var.h>
106
107 #include <net/bpf.h>
108
109 #include <machine/bus.h>
110 #include <machine/resource.h>
111 #include <sys/bus.h>
112 #include <sys/rman.h>
113
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
116
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
119
120 MODULE_DEPEND(vge, pci, 1, 1, 1);
121 MODULE_DEPEND(vge, ether, 1, 1, 1);
122 MODULE_DEPEND(vge, miibus, 1, 1, 1);
123
124 /* "device miibus" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
126
127 #include <dev/vge/if_vgereg.h>
128 #include <dev/vge/if_vgevar.h>
129
130 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
131
132 /* Tunables */
133 static int msi_disable = 0;
134 TUNABLE_INT("hw.vge.msi_disable", &msi_disable);
135
136 /*
137 * The SQE error counter of MIB seems to report bogus value.
138 * Vendor's workaround does not seem to work on PCIe based
139 * controllers. Disable it until we find better workaround.
140 */
141 #undef VGE_ENABLE_SQEERR
142
143 /*
144 * Various supported device vendors/types and their names.
145 */
146 static struct vge_type vge_devs[] = {
147 { VIA_VENDORID, VIA_DEVICEID_61XX,
148 "VIA Networking Velocity Gigabit Ethernet" },
149 { 0, 0, NULL }
150 };
151
152 static int vge_attach(device_t);
153 static int vge_detach(device_t);
154 static int vge_probe(device_t);
155 static int vge_resume(device_t);
156 static int vge_shutdown(device_t);
157 static int vge_suspend(device_t);
158
159 static void vge_cam_clear(struct vge_softc *);
160 static int vge_cam_set(struct vge_softc *, uint8_t *);
161 static void vge_clrwol(struct vge_softc *);
162 static void vge_discard_rxbuf(struct vge_softc *, int);
163 static int vge_dma_alloc(struct vge_softc *);
164 static void vge_dma_free(struct vge_softc *);
165 static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
166 #ifdef VGE_EEPROM
167 static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *);
168 #endif
169 static int vge_encap(struct vge_softc *, struct mbuf **);
170 #ifndef __NO_STRICT_ALIGNMENT
171 static __inline void
172 vge_fixup_rx(struct mbuf *);
173 #endif
174 static void vge_freebufs(struct vge_softc *);
175 static void vge_ifmedia_sts(if_t, struct ifmediareq *);
176 static int vge_ifmedia_upd(if_t);
177 static int vge_ifmedia_upd_locked(struct vge_softc *);
178 static void vge_init(void *);
179 static void vge_init_locked(struct vge_softc *);
180 static void vge_intr(void *);
181 static void vge_intr_holdoff(struct vge_softc *);
182 static int vge_ioctl(if_t, u_long, caddr_t);
183 static void vge_link_statchg(void *);
184 static int vge_miibus_readreg(device_t, int, int);
185 static int vge_miibus_writereg(device_t, int, int, int);
186 static void vge_miipoll_start(struct vge_softc *);
187 static void vge_miipoll_stop(struct vge_softc *);
188 static int vge_newbuf(struct vge_softc *, int);
189 static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int);
190 static void vge_reset(struct vge_softc *);
191 static int vge_rx_list_init(struct vge_softc *);
192 static int vge_rxeof(struct vge_softc *, int);
193 static void vge_rxfilter(struct vge_softc *);
194 static void vge_setmedia(struct vge_softc *);
195 static void vge_setvlan(struct vge_softc *);
196 static void vge_setwol(struct vge_softc *);
197 static void vge_start(if_t);
198 static void vge_start_locked(if_t);
199 static void vge_stats_clear(struct vge_softc *);
200 static void vge_stats_update(struct vge_softc *);
201 static void vge_stop(struct vge_softc *);
202 static void vge_sysctl_node(struct vge_softc *);
203 static int vge_tx_list_init(struct vge_softc *);
204 static void vge_txeof(struct vge_softc *);
205 static void vge_watchdog(void *);
206
207 static device_method_t vge_methods[] = {
208 /* Device interface */
209 DEVMETHOD(device_probe, vge_probe),
210 DEVMETHOD(device_attach, vge_attach),
211 DEVMETHOD(device_detach, vge_detach),
212 DEVMETHOD(device_suspend, vge_suspend),
213 DEVMETHOD(device_resume, vge_resume),
214 DEVMETHOD(device_shutdown, vge_shutdown),
215
216 /* MII interface */
217 DEVMETHOD(miibus_readreg, vge_miibus_readreg),
218 DEVMETHOD(miibus_writereg, vge_miibus_writereg),
219
220 DEVMETHOD_END
221 };
222
223 static driver_t vge_driver = {
224 "vge",
225 vge_methods,
226 sizeof(struct vge_softc)
227 };
228
229 DRIVER_MODULE(vge, pci, vge_driver, 0, 0);
230 DRIVER_MODULE(miibus, vge, miibus_driver, 0, 0);
231
232 #ifdef VGE_EEPROM
233 /*
234 * Read a word of data stored in the EEPROM at address 'addr.'
235 */
236 static void
vge_eeprom_getword(struct vge_softc * sc,int addr,uint16_t * dest)237 vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest)
238 {
239 int i;
240 uint16_t word = 0;
241
242 /*
243 * Enter EEPROM embedded programming mode. In order to
244 * access the EEPROM at all, we first have to set the
245 * EELOAD bit in the CHIPCFG2 register.
246 */
247 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
248 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
249
250 /* Select the address of the word we want to read */
251 CSR_WRITE_1(sc, VGE_EEADDR, addr);
252
253 /* Issue read command */
254 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
255
256 /* Wait for the done bit to be set. */
257 for (i = 0; i < VGE_TIMEOUT; i++) {
258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
259 break;
260 }
261
262 if (i == VGE_TIMEOUT) {
263 device_printf(sc->vge_dev, "EEPROM read timed out\n");
264 *dest = 0;
265 return;
266 }
267
268 /* Read the result */
269 word = CSR_READ_2(sc, VGE_EERDDAT);
270
271 /* Turn off EEPROM access mode. */
272 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
273 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
274
275 *dest = word;
276 }
277 #endif
278
279 /*
280 * Read a sequence of words from the EEPROM.
281 */
282 static void
vge_read_eeprom(struct vge_softc * sc,caddr_t dest,int off,int cnt,int swap)283 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap)
284 {
285 int i;
286 #ifdef VGE_EEPROM
287 uint16_t word = 0, *ptr;
288
289 for (i = 0; i < cnt; i++) {
290 vge_eeprom_getword(sc, off + i, &word);
291 ptr = (uint16_t *)(dest + (i * 2));
292 if (swap)
293 *ptr = ntohs(word);
294 else
295 *ptr = word;
296 }
297 #else
298 for (i = 0; i < ETHER_ADDR_LEN; i++)
299 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
300 #endif
301 }
302
303 static void
vge_miipoll_stop(struct vge_softc * sc)304 vge_miipoll_stop(struct vge_softc *sc)
305 {
306 int i;
307
308 CSR_WRITE_1(sc, VGE_MIICMD, 0);
309
310 for (i = 0; i < VGE_TIMEOUT; i++) {
311 DELAY(1);
312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
313 break;
314 }
315
316 if (i == VGE_TIMEOUT)
317 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
318 }
319
320 static void
vge_miipoll_start(struct vge_softc * sc)321 vge_miipoll_start(struct vge_softc *sc)
322 {
323 int i;
324
325 /* First, make sure we're idle. */
326
327 CSR_WRITE_1(sc, VGE_MIICMD, 0);
328 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
329
330 for (i = 0; i < VGE_TIMEOUT; i++) {
331 DELAY(1);
332 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
333 break;
334 }
335
336 if (i == VGE_TIMEOUT) {
337 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
338 return;
339 }
340
341 /* Now enable auto poll mode. */
342
343 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
344
345 /* And make sure it started. */
346
347 for (i = 0; i < VGE_TIMEOUT; i++) {
348 DELAY(1);
349 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
350 break;
351 }
352
353 if (i == VGE_TIMEOUT)
354 device_printf(sc->vge_dev, "failed to start MII autopoll\n");
355 }
356
357 static int
vge_miibus_readreg(device_t dev,int phy,int reg)358 vge_miibus_readreg(device_t dev, int phy, int reg)
359 {
360 struct vge_softc *sc;
361 int i;
362 uint16_t rval = 0;
363
364 sc = device_get_softc(dev);
365
366 vge_miipoll_stop(sc);
367
368 /* Specify the register we want to read. */
369 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
370
371 /* Issue read command. */
372 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
373
374 /* Wait for the read command bit to self-clear. */
375 for (i = 0; i < VGE_TIMEOUT; i++) {
376 DELAY(1);
377 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
378 break;
379 }
380
381 if (i == VGE_TIMEOUT)
382 device_printf(sc->vge_dev, "MII read timed out\n");
383 else
384 rval = CSR_READ_2(sc, VGE_MIIDATA);
385
386 vge_miipoll_start(sc);
387
388 return (rval);
389 }
390
391 static int
vge_miibus_writereg(device_t dev,int phy,int reg,int data)392 vge_miibus_writereg(device_t dev, int phy, int reg, int data)
393 {
394 struct vge_softc *sc;
395 int i, rval = 0;
396
397 sc = device_get_softc(dev);
398
399 vge_miipoll_stop(sc);
400
401 /* Specify the register we want to write. */
402 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
403
404 /* Specify the data we want to write. */
405 CSR_WRITE_2(sc, VGE_MIIDATA, data);
406
407 /* Issue write command. */
408 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
409
410 /* Wait for the write command bit to self-clear. */
411 for (i = 0; i < VGE_TIMEOUT; i++) {
412 DELAY(1);
413 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
414 break;
415 }
416
417 if (i == VGE_TIMEOUT) {
418 device_printf(sc->vge_dev, "MII write timed out\n");
419 rval = EIO;
420 }
421
422 vge_miipoll_start(sc);
423
424 return (rval);
425 }
426
427 static void
vge_cam_clear(struct vge_softc * sc)428 vge_cam_clear(struct vge_softc *sc)
429 {
430 int i;
431
432 /*
433 * Turn off all the mask bits. This tells the chip
434 * that none of the entries in the CAM filter are valid.
435 * desired entries will be enabled as we fill the filter in.
436 */
437
438 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
439 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
440 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
441 for (i = 0; i < 8; i++)
442 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
443
444 /* Clear the VLAN filter too. */
445
446 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
447 for (i = 0; i < 8; i++)
448 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
449
450 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
453
454 sc->vge_camidx = 0;
455 }
456
457 static int
vge_cam_set(struct vge_softc * sc,uint8_t * addr)458 vge_cam_set(struct vge_softc *sc, uint8_t *addr)
459 {
460 int i, error = 0;
461
462 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
463 return (ENOSPC);
464
465 /* Select the CAM data page. */
466 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
467 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
468
469 /* Set the filter entry we want to update and enable writing. */
470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
471
472 /* Write the address to the CAM registers */
473 for (i = 0; i < ETHER_ADDR_LEN; i++)
474 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
475
476 /* Issue a write command. */
477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
478
479 /* Wake for it to clear. */
480 for (i = 0; i < VGE_TIMEOUT; i++) {
481 DELAY(1);
482 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
483 break;
484 }
485
486 if (i == VGE_TIMEOUT) {
487 device_printf(sc->vge_dev, "setting CAM filter failed\n");
488 error = EIO;
489 goto fail;
490 }
491
492 /* Select the CAM mask page. */
493 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
494 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
495
496 /* Set the mask bit that enables this filter. */
497 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
498 1<<(sc->vge_camidx & 7));
499
500 sc->vge_camidx++;
501
502 fail:
503 /* Turn off access to CAM. */
504 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
505 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
507
508 return (error);
509 }
510
511 static void
vge_setvlan(struct vge_softc * sc)512 vge_setvlan(struct vge_softc *sc)
513 {
514 if_t ifp;
515 uint8_t cfg;
516
517 VGE_LOCK_ASSERT(sc);
518
519 ifp = sc->vge_ifp;
520 cfg = CSR_READ_1(sc, VGE_RXCFG);
521 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
522 cfg |= VGE_VTAG_OPT2;
523 else
524 cfg &= ~VGE_VTAG_OPT2;
525 CSR_WRITE_1(sc, VGE_RXCFG, cfg);
526 }
527
528 static u_int
vge_set_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)529 vge_set_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
530 {
531 struct vge_softc *sc = arg;
532
533 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
534 return (0);
535
536 (void )vge_cam_set(sc, LLADDR(sdl));
537
538 return (1);
539 }
540
541 static u_int
vge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)542 vge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
543 {
544 uint32_t h, *hashes = arg;
545
546 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
547 if (h < 32)
548 hashes[0] |= (1 << h);
549 else
550 hashes[1] |= (1 << (h - 32));
551
552 return (1);
553 }
554
555 /*
556 * Program the multicast filter. We use the 64-entry CAM filter
557 * for perfect filtering. If there's more than 64 multicast addresses,
558 * we use the hash filter instead.
559 */
560 static void
vge_rxfilter(struct vge_softc * sc)561 vge_rxfilter(struct vge_softc *sc)
562 {
563 if_t ifp;
564 uint32_t hashes[2];
565 uint8_t rxcfg;
566
567 VGE_LOCK_ASSERT(sc);
568
569 /* First, zot all the multicast entries. */
570 hashes[0] = 0;
571 hashes[1] = 0;
572
573 rxcfg = CSR_READ_1(sc, VGE_RXCTL);
574 rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST |
575 VGE_RXCTL_RX_PROMISC);
576 /*
577 * Always allow VLAN oversized frames and frames for
578 * this host.
579 */
580 rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST;
581
582 ifp = sc->vge_ifp;
583 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
584 rxcfg |= VGE_RXCTL_RX_BCAST;
585 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
586 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
587 rxcfg |= VGE_RXCTL_RX_PROMISC;
588 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
589 hashes[0] = 0xFFFFFFFF;
590 hashes[1] = 0xFFFFFFFF;
591 }
592 goto done;
593 }
594
595 vge_cam_clear(sc);
596
597 /* Now program new ones */
598 if_foreach_llmaddr(ifp, vge_set_maddr, sc);
599
600 /* If there were too many addresses, use the hash filter. */
601 if (sc->vge_camidx == VGE_CAM_MAXADDRS) {
602 vge_cam_clear(sc);
603 if_foreach_llmaddr(ifp, vge_hash_maddr, hashes);
604 }
605
606 done:
607 if (hashes[0] != 0 || hashes[1] != 0)
608 rxcfg |= VGE_RXCTL_RX_MCAST;
609 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
610 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
611 CSR_WRITE_1(sc, VGE_RXCTL, rxcfg);
612 }
613
614 static void
vge_reset(struct vge_softc * sc)615 vge_reset(struct vge_softc *sc)
616 {
617 int i;
618
619 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
620
621 for (i = 0; i < VGE_TIMEOUT; i++) {
622 DELAY(5);
623 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
624 break;
625 }
626
627 if (i == VGE_TIMEOUT) {
628 device_printf(sc->vge_dev, "soft reset timed out\n");
629 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
630 DELAY(2000);
631 }
632
633 DELAY(5000);
634 }
635
636 /*
637 * Probe for a VIA gigabit chip. Check the PCI vendor and device
638 * IDs against our list and return a device name if we find a match.
639 */
640 static int
vge_probe(device_t dev)641 vge_probe(device_t dev)
642 {
643 struct vge_type *t;
644
645 t = vge_devs;
646
647 while (t->vge_name != NULL) {
648 if ((pci_get_vendor(dev) == t->vge_vid) &&
649 (pci_get_device(dev) == t->vge_did)) {
650 device_set_desc(dev, t->vge_name);
651 return (BUS_PROBE_DEFAULT);
652 }
653 t++;
654 }
655
656 return (ENXIO);
657 }
658
659 /*
660 * Map a single buffer address.
661 */
662
663 struct vge_dmamap_arg {
664 bus_addr_t vge_busaddr;
665 };
666
667 static void
vge_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)668 vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
669 {
670 struct vge_dmamap_arg *ctx;
671
672 if (error != 0)
673 return;
674
675 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
676
677 ctx = (struct vge_dmamap_arg *)arg;
678 ctx->vge_busaddr = segs[0].ds_addr;
679 }
680
681 static int
vge_dma_alloc(struct vge_softc * sc)682 vge_dma_alloc(struct vge_softc *sc)
683 {
684 struct vge_dmamap_arg ctx;
685 struct vge_txdesc *txd;
686 struct vge_rxdesc *rxd;
687 bus_addr_t lowaddr, tx_ring_end, rx_ring_end;
688 int error, i;
689
690 /*
691 * It seems old PCI controllers do not support DAC. DAC
692 * configuration can be enabled by accessing VGE_CHIPCFG3
693 * register but honor EEPROM configuration instead of
694 * blindly overriding DAC configuration. PCIe based
695 * controllers are supposed to support 64bit DMA so enable
696 * 64bit DMA on these controllers.
697 */
698 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
699 lowaddr = BUS_SPACE_MAXADDR;
700 else
701 lowaddr = BUS_SPACE_MAXADDR_32BIT;
702
703 again:
704 /* Create parent ring tag. */
705 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */
706 1, 0, /* algnmnt, boundary */
707 lowaddr, /* lowaddr */
708 BUS_SPACE_MAXADDR, /* highaddr */
709 NULL, NULL, /* filter, filterarg */
710 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
711 0, /* nsegments */
712 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
713 0, /* flags */
714 NULL, NULL, /* lockfunc, lockarg */
715 &sc->vge_cdata.vge_ring_tag);
716 if (error != 0) {
717 device_printf(sc->vge_dev,
718 "could not create parent DMA tag.\n");
719 goto fail;
720 }
721
722 /* Create tag for Tx ring. */
723 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */
724 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */
725 BUS_SPACE_MAXADDR, /* lowaddr */
726 BUS_SPACE_MAXADDR, /* highaddr */
727 NULL, NULL, /* filter, filterarg */
728 VGE_TX_LIST_SZ, /* maxsize */
729 1, /* nsegments */
730 VGE_TX_LIST_SZ, /* maxsegsize */
731 0, /* flags */
732 NULL, NULL, /* lockfunc, lockarg */
733 &sc->vge_cdata.vge_tx_ring_tag);
734 if (error != 0) {
735 device_printf(sc->vge_dev,
736 "could not allocate Tx ring DMA tag.\n");
737 goto fail;
738 }
739
740 /* Create tag for Rx ring. */
741 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */
742 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */
743 BUS_SPACE_MAXADDR, /* lowaddr */
744 BUS_SPACE_MAXADDR, /* highaddr */
745 NULL, NULL, /* filter, filterarg */
746 VGE_RX_LIST_SZ, /* maxsize */
747 1, /* nsegments */
748 VGE_RX_LIST_SZ, /* maxsegsize */
749 0, /* flags */
750 NULL, NULL, /* lockfunc, lockarg */
751 &sc->vge_cdata.vge_rx_ring_tag);
752 if (error != 0) {
753 device_printf(sc->vge_dev,
754 "could not allocate Rx ring DMA tag.\n");
755 goto fail;
756 }
757
758 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
759 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag,
760 (void **)&sc->vge_rdata.vge_tx_ring,
761 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
762 &sc->vge_cdata.vge_tx_ring_map);
763 if (error != 0) {
764 device_printf(sc->vge_dev,
765 "could not allocate DMA'able memory for Tx ring.\n");
766 goto fail;
767 }
768
769 ctx.vge_busaddr = 0;
770 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag,
771 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring,
772 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
773 if (error != 0 || ctx.vge_busaddr == 0) {
774 device_printf(sc->vge_dev,
775 "could not load DMA'able memory for Tx ring.\n");
776 goto fail;
777 }
778 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr;
779
780 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
781 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag,
782 (void **)&sc->vge_rdata.vge_rx_ring,
783 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
784 &sc->vge_cdata.vge_rx_ring_map);
785 if (error != 0) {
786 device_printf(sc->vge_dev,
787 "could not allocate DMA'able memory for Rx ring.\n");
788 goto fail;
789 }
790
791 ctx.vge_busaddr = 0;
792 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag,
793 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring,
794 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
795 if (error != 0 || ctx.vge_busaddr == 0) {
796 device_printf(sc->vge_dev,
797 "could not load DMA'able memory for Rx ring.\n");
798 goto fail;
799 }
800 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr;
801
802 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
803 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ;
804 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ;
805 if ((VGE_ADDR_HI(tx_ring_end) !=
806 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) ||
807 (VGE_ADDR_HI(rx_ring_end) !=
808 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) ||
809 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) {
810 device_printf(sc->vge_dev, "4GB boundary crossed, "
811 "switching to 32bit DMA address mode.\n");
812 vge_dma_free(sc);
813 /* Limit DMA address space to 32bit and try again. */
814 lowaddr = BUS_SPACE_MAXADDR_32BIT;
815 goto again;
816 }
817
818 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
819 lowaddr = VGE_BUF_DMA_MAXADDR;
820 else
821 lowaddr = BUS_SPACE_MAXADDR_32BIT;
822 /* Create parent buffer tag. */
823 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */
824 1, 0, /* algnmnt, boundary */
825 lowaddr, /* lowaddr */
826 BUS_SPACE_MAXADDR, /* highaddr */
827 NULL, NULL, /* filter, filterarg */
828 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
829 0, /* nsegments */
830 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
831 0, /* flags */
832 NULL, NULL, /* lockfunc, lockarg */
833 &sc->vge_cdata.vge_buffer_tag);
834 if (error != 0) {
835 device_printf(sc->vge_dev,
836 "could not create parent buffer DMA tag.\n");
837 goto fail;
838 }
839
840 /* Create tag for Tx buffers. */
841 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */
842 1, 0, /* algnmnt, boundary */
843 BUS_SPACE_MAXADDR, /* lowaddr */
844 BUS_SPACE_MAXADDR, /* highaddr */
845 NULL, NULL, /* filter, filterarg */
846 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */
847 VGE_MAXTXSEGS, /* nsegments */
848 MCLBYTES, /* maxsegsize */
849 0, /* flags */
850 NULL, NULL, /* lockfunc, lockarg */
851 &sc->vge_cdata.vge_tx_tag);
852 if (error != 0) {
853 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n");
854 goto fail;
855 }
856
857 /* Create tag for Rx buffers. */
858 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */
859 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
860 BUS_SPACE_MAXADDR, /* lowaddr */
861 BUS_SPACE_MAXADDR, /* highaddr */
862 NULL, NULL, /* filter, filterarg */
863 MCLBYTES, /* maxsize */
864 1, /* nsegments */
865 MCLBYTES, /* maxsegsize */
866 0, /* flags */
867 NULL, NULL, /* lockfunc, lockarg */
868 &sc->vge_cdata.vge_rx_tag);
869 if (error != 0) {
870 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n");
871 goto fail;
872 }
873
874 /* Create DMA maps for Tx buffers. */
875 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
876 txd = &sc->vge_cdata.vge_txdesc[i];
877 txd->tx_m = NULL;
878 txd->tx_dmamap = NULL;
879 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0,
880 &txd->tx_dmamap);
881 if (error != 0) {
882 device_printf(sc->vge_dev,
883 "could not create Tx dmamap.\n");
884 goto fail;
885 }
886 }
887 /* Create DMA maps for Rx buffers. */
888 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0,
889 &sc->vge_cdata.vge_rx_sparemap)) != 0) {
890 device_printf(sc->vge_dev,
891 "could not create spare Rx dmamap.\n");
892 goto fail;
893 }
894 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
895 rxd = &sc->vge_cdata.vge_rxdesc[i];
896 rxd->rx_m = NULL;
897 rxd->rx_dmamap = NULL;
898 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0,
899 &rxd->rx_dmamap);
900 if (error != 0) {
901 device_printf(sc->vge_dev,
902 "could not create Rx dmamap.\n");
903 goto fail;
904 }
905 }
906
907 fail:
908 return (error);
909 }
910
911 static void
vge_dma_free(struct vge_softc * sc)912 vge_dma_free(struct vge_softc *sc)
913 {
914 struct vge_txdesc *txd;
915 struct vge_rxdesc *rxd;
916 int i;
917
918 /* Tx ring. */
919 if (sc->vge_cdata.vge_tx_ring_tag != NULL) {
920 if (sc->vge_rdata.vge_tx_ring_paddr)
921 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag,
922 sc->vge_cdata.vge_tx_ring_map);
923 if (sc->vge_rdata.vge_tx_ring)
924 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag,
925 sc->vge_rdata.vge_tx_ring,
926 sc->vge_cdata.vge_tx_ring_map);
927 sc->vge_rdata.vge_tx_ring = NULL;
928 sc->vge_rdata.vge_tx_ring_paddr = 0;
929 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag);
930 sc->vge_cdata.vge_tx_ring_tag = NULL;
931 }
932 /* Rx ring. */
933 if (sc->vge_cdata.vge_rx_ring_tag != NULL) {
934 if (sc->vge_rdata.vge_rx_ring_paddr)
935 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag,
936 sc->vge_cdata.vge_rx_ring_map);
937 if (sc->vge_rdata.vge_rx_ring)
938 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag,
939 sc->vge_rdata.vge_rx_ring,
940 sc->vge_cdata.vge_rx_ring_map);
941 sc->vge_rdata.vge_rx_ring = NULL;
942 sc->vge_rdata.vge_rx_ring_paddr = 0;
943 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag);
944 sc->vge_cdata.vge_rx_ring_tag = NULL;
945 }
946 /* Tx buffers. */
947 if (sc->vge_cdata.vge_tx_tag != NULL) {
948 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
949 txd = &sc->vge_cdata.vge_txdesc[i];
950 if (txd->tx_dmamap != NULL) {
951 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag,
952 txd->tx_dmamap);
953 txd->tx_dmamap = NULL;
954 }
955 }
956 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag);
957 sc->vge_cdata.vge_tx_tag = NULL;
958 }
959 /* Rx buffers. */
960 if (sc->vge_cdata.vge_rx_tag != NULL) {
961 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
962 rxd = &sc->vge_cdata.vge_rxdesc[i];
963 if (rxd->rx_dmamap != NULL) {
964 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag,
965 rxd->rx_dmamap);
966 rxd->rx_dmamap = NULL;
967 }
968 }
969 if (sc->vge_cdata.vge_rx_sparemap != NULL) {
970 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag,
971 sc->vge_cdata.vge_rx_sparemap);
972 sc->vge_cdata.vge_rx_sparemap = NULL;
973 }
974 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag);
975 sc->vge_cdata.vge_rx_tag = NULL;
976 }
977
978 if (sc->vge_cdata.vge_buffer_tag != NULL) {
979 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag);
980 sc->vge_cdata.vge_buffer_tag = NULL;
981 }
982 if (sc->vge_cdata.vge_ring_tag != NULL) {
983 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag);
984 sc->vge_cdata.vge_ring_tag = NULL;
985 }
986 }
987
988 /*
989 * Attach the interface. Allocate softc structures, do ifmedia
990 * setup and ethernet/BPF attach.
991 */
992 static int
vge_attach(device_t dev)993 vge_attach(device_t dev)
994 {
995 u_char eaddr[ETHER_ADDR_LEN];
996 struct vge_softc *sc;
997 if_t ifp;
998 int error = 0, cap, i, msic, rid;
999
1000 sc = device_get_softc(dev);
1001 sc->vge_dev = dev;
1002
1003 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1004 MTX_DEF);
1005 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0);
1006
1007 /*
1008 * Map control/status registers.
1009 */
1010 pci_enable_busmaster(dev);
1011
1012 rid = PCIR_BAR(1);
1013 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1014 RF_ACTIVE);
1015
1016 if (sc->vge_res == NULL) {
1017 device_printf(dev, "couldn't map ports/memory\n");
1018 error = ENXIO;
1019 goto fail;
1020 }
1021
1022 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) {
1023 sc->vge_flags |= VGE_FLAG_PCIE;
1024 sc->vge_expcap = cap;
1025 } else
1026 sc->vge_flags |= VGE_FLAG_JUMBO;
1027 if (pci_has_pm(dev))
1028 sc->vge_flags |= VGE_FLAG_PMCAP;
1029 rid = 0;
1030 msic = pci_msi_count(dev);
1031 if (msi_disable == 0 && msic > 0) {
1032 msic = 1;
1033 if (pci_alloc_msi(dev, &msic) == 0) {
1034 if (msic == 1) {
1035 sc->vge_flags |= VGE_FLAG_MSI;
1036 device_printf(dev, "Using %d MSI message\n",
1037 msic);
1038 rid = 1;
1039 } else
1040 pci_release_msi(dev);
1041 }
1042 }
1043
1044 /* Allocate interrupt */
1045 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1046 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE);
1047 if (sc->vge_irq == NULL) {
1048 device_printf(dev, "couldn't map interrupt\n");
1049 error = ENXIO;
1050 goto fail;
1051 }
1052
1053 /* Reset the adapter. */
1054 vge_reset(sc);
1055 /* Reload EEPROM. */
1056 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
1057 for (i = 0; i < VGE_TIMEOUT; i++) {
1058 DELAY(5);
1059 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
1060 break;
1061 }
1062 if (i == VGE_TIMEOUT)
1063 device_printf(dev, "EEPROM reload timed out\n");
1064 /*
1065 * Clear PACPI as EEPROM reload will set the bit. Otherwise
1066 * MAC will receive magic packet which in turn confuses
1067 * controller.
1068 */
1069 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
1070
1071 /*
1072 * Get station address from the EEPROM.
1073 */
1074 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0);
1075 /*
1076 * Save configured PHY address.
1077 * It seems the PHY address of PCIe controllers just
1078 * reflects media jump strapping status so we assume the
1079 * internal PHY address of PCIe controller is at 1.
1080 */
1081 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
1082 sc->vge_phyaddr = 1;
1083 else
1084 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &
1085 VGE_MIICFG_PHYADDR;
1086 /* Clear WOL and take hardware from powerdown. */
1087 vge_clrwol(sc);
1088 vge_sysctl_node(sc);
1089 error = vge_dma_alloc(sc);
1090 if (error)
1091 goto fail;
1092
1093 ifp = sc->vge_ifp = if_alloc(IFT_ETHER);
1094 vge_miipoll_start(sc);
1095 /* Do MII setup */
1096 error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd,
1097 vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY,
1098 MIIF_DOPAUSE);
1099 if (error != 0) {
1100 device_printf(dev, "attaching PHYs failed\n");
1101 goto fail;
1102 }
1103
1104 if_setsoftc(ifp, sc);
1105 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1106 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1107 if_setioctlfn(ifp, vge_ioctl);
1108 if_setcapabilities(ifp, IFCAP_VLAN_MTU);
1109 if_setstartfn(ifp, vge_start);
1110 if_sethwassist(ifp, VGE_CSUM_FEATURES);
1111 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
1112 IFCAP_VLAN_HWTAGGING, 0);
1113 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0)
1114 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0);
1115 if_setcapenable(ifp, if_getcapabilities(ifp));
1116 #ifdef DEVICE_POLLING
1117 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
1118 #endif
1119 if_setinitfn(ifp, vge_init);
1120 if_setsendqlen(ifp, VGE_TX_DESC_CNT - 1);
1121 if_setsendqready(ifp);
1122
1123 /*
1124 * Call MI attach routine.
1125 */
1126 ether_ifattach(ifp, eaddr);
1127
1128 /* Tell the upper layer(s) we support long frames. */
1129 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1130
1131 /* Hook interrupt last to avoid having to lock softc */
1132 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE,
1133 NULL, vge_intr, sc, &sc->vge_intrhand);
1134
1135 if (error) {
1136 device_printf(dev, "couldn't set up irq\n");
1137 ether_ifdetach(ifp);
1138 goto fail;
1139 }
1140
1141 fail:
1142 if (error)
1143 vge_detach(dev);
1144
1145 return (error);
1146 }
1147
1148 /*
1149 * Shutdown hardware and free up resources. This can be called any
1150 * time after the mutex has been initialized. It is called in both
1151 * the error case in attach and the normal detach case so it needs
1152 * to be careful about only freeing resources that have actually been
1153 * allocated.
1154 */
1155 static int
vge_detach(device_t dev)1156 vge_detach(device_t dev)
1157 {
1158 struct vge_softc *sc;
1159 if_t ifp;
1160
1161 sc = device_get_softc(dev);
1162 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized"));
1163 ifp = sc->vge_ifp;
1164
1165 #ifdef DEVICE_POLLING
1166 if (if_getcapenable(ifp) & IFCAP_POLLING)
1167 ether_poll_deregister(ifp);
1168 #endif
1169
1170 /* These should only be active if attach succeeded */
1171 if (device_is_attached(dev)) {
1172 ether_ifdetach(ifp);
1173 VGE_LOCK(sc);
1174 vge_stop(sc);
1175 VGE_UNLOCK(sc);
1176 callout_drain(&sc->vge_watchdog);
1177 }
1178 bus_generic_detach(dev);
1179
1180 if (sc->vge_intrhand)
1181 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand);
1182 if (sc->vge_irq)
1183 bus_release_resource(dev, SYS_RES_IRQ,
1184 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq);
1185 if (sc->vge_flags & VGE_FLAG_MSI)
1186 pci_release_msi(dev);
1187 if (sc->vge_res)
1188 bus_release_resource(dev, SYS_RES_MEMORY,
1189 PCIR_BAR(1), sc->vge_res);
1190 if (ifp)
1191 if_free(ifp);
1192
1193 vge_dma_free(sc);
1194 mtx_destroy(&sc->vge_mtx);
1195
1196 return (0);
1197 }
1198
1199 static void
vge_discard_rxbuf(struct vge_softc * sc,int prod)1200 vge_discard_rxbuf(struct vge_softc *sc, int prod)
1201 {
1202 struct vge_rxdesc *rxd;
1203 int i;
1204
1205 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1206 rxd->rx_desc->vge_sts = 0;
1207 rxd->rx_desc->vge_ctl = 0;
1208
1209 /*
1210 * Note: the manual fails to document the fact that for
1211 * proper operation, the driver needs to replentish the RX
1212 * DMA ring 4 descriptors at a time (rather than one at a
1213 * time, like most chips). We can allocate the new buffers
1214 * but we should not set the OWN bits until we're ready
1215 * to hand back 4 of them in one shot.
1216 */
1217 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) {
1218 for (i = VGE_RXCHUNK; i > 0; i--) {
1219 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN);
1220 rxd = rxd->rxd_prev;
1221 }
1222 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK;
1223 }
1224 }
1225
1226 static int
vge_newbuf(struct vge_softc * sc,int prod)1227 vge_newbuf(struct vge_softc *sc, int prod)
1228 {
1229 struct vge_rxdesc *rxd;
1230 struct mbuf *m;
1231 bus_dma_segment_t segs[1];
1232 bus_dmamap_t map;
1233 int i, nsegs;
1234
1235 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1236 if (m == NULL)
1237 return (ENOBUFS);
1238 /*
1239 * This is part of an evil trick to deal with strict-alignment
1240 * architectures. The VIA chip requires RX buffers to be aligned
1241 * on 32-bit boundaries, but that will hose strict-alignment
1242 * architectures. To get around this, we leave some empty space
1243 * at the start of each buffer and for non-strict-alignment hosts,
1244 * we copy the buffer back two bytes to achieve word alignment.
1245 * This is slightly more efficient than allocating a new buffer,
1246 * copying the contents, and discarding the old buffer.
1247 */
1248 m->m_len = m->m_pkthdr.len = MCLBYTES;
1249 m_adj(m, VGE_RX_BUF_ALIGN);
1250
1251 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag,
1252 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1253 m_freem(m);
1254 return (ENOBUFS);
1255 }
1256 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1257
1258 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1259 if (rxd->rx_m != NULL) {
1260 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap,
1261 BUS_DMASYNC_POSTREAD);
1262 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap);
1263 }
1264 map = rxd->rx_dmamap;
1265 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap;
1266 sc->vge_cdata.vge_rx_sparemap = map;
1267 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap,
1268 BUS_DMASYNC_PREREAD);
1269 rxd->rx_m = m;
1270
1271 rxd->rx_desc->vge_sts = 0;
1272 rxd->rx_desc->vge_ctl = 0;
1273 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
1274 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) |
1275 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I);
1276
1277 /*
1278 * Note: the manual fails to document the fact that for
1279 * proper operation, the driver needs to replenish the RX
1280 * DMA ring 4 descriptors at a time (rather than one at a
1281 * time, like most chips). We can allocate the new buffers
1282 * but we should not set the OWN bits until we're ready
1283 * to hand back 4 of them in one shot.
1284 */
1285 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) {
1286 for (i = VGE_RXCHUNK; i > 0; i--) {
1287 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN);
1288 rxd = rxd->rxd_prev;
1289 }
1290 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK;
1291 }
1292
1293 return (0);
1294 }
1295
1296 static int
vge_tx_list_init(struct vge_softc * sc)1297 vge_tx_list_init(struct vge_softc *sc)
1298 {
1299 struct vge_ring_data *rd;
1300 struct vge_txdesc *txd;
1301 int i;
1302
1303 VGE_LOCK_ASSERT(sc);
1304
1305 sc->vge_cdata.vge_tx_prodidx = 0;
1306 sc->vge_cdata.vge_tx_considx = 0;
1307 sc->vge_cdata.vge_tx_cnt = 0;
1308
1309 rd = &sc->vge_rdata;
1310 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ);
1311 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
1312 txd = &sc->vge_cdata.vge_txdesc[i];
1313 txd->tx_m = NULL;
1314 txd->tx_desc = &rd->vge_tx_ring[i];
1315 }
1316
1317 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1318 sc->vge_cdata.vge_tx_ring_map,
1319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1320
1321 return (0);
1322 }
1323
1324 static int
vge_rx_list_init(struct vge_softc * sc)1325 vge_rx_list_init(struct vge_softc *sc)
1326 {
1327 struct vge_ring_data *rd;
1328 struct vge_rxdesc *rxd;
1329 int i;
1330
1331 VGE_LOCK_ASSERT(sc);
1332
1333 sc->vge_cdata.vge_rx_prodidx = 0;
1334 sc->vge_cdata.vge_head = NULL;
1335 sc->vge_cdata.vge_tail = NULL;
1336 sc->vge_cdata.vge_rx_commit = 0;
1337
1338 rd = &sc->vge_rdata;
1339 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ);
1340 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
1341 rxd = &sc->vge_cdata.vge_rxdesc[i];
1342 rxd->rx_m = NULL;
1343 rxd->rx_desc = &rd->vge_rx_ring[i];
1344 if (i == 0)
1345 rxd->rxd_prev =
1346 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1];
1347 else
1348 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1];
1349 if (vge_newbuf(sc, i) != 0)
1350 return (ENOBUFS);
1351 }
1352
1353 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1354 sc->vge_cdata.vge_rx_ring_map,
1355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1356
1357 sc->vge_cdata.vge_rx_commit = 0;
1358
1359 return (0);
1360 }
1361
1362 static void
vge_freebufs(struct vge_softc * sc)1363 vge_freebufs(struct vge_softc *sc)
1364 {
1365 struct vge_txdesc *txd;
1366 struct vge_rxdesc *rxd;
1367 if_t ifp;
1368 int i;
1369
1370 VGE_LOCK_ASSERT(sc);
1371
1372 ifp = sc->vge_ifp;
1373 /*
1374 * Free RX and TX mbufs still in the queues.
1375 */
1376 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
1377 rxd = &sc->vge_cdata.vge_rxdesc[i];
1378 if (rxd->rx_m != NULL) {
1379 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag,
1380 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
1381 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag,
1382 rxd->rx_dmamap);
1383 m_freem(rxd->rx_m);
1384 rxd->rx_m = NULL;
1385 }
1386 }
1387
1388 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
1389 txd = &sc->vge_cdata.vge_txdesc[i];
1390 if (txd->tx_m != NULL) {
1391 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag,
1392 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1393 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag,
1394 txd->tx_dmamap);
1395 m_freem(txd->tx_m);
1396 txd->tx_m = NULL;
1397 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1398 }
1399 }
1400 }
1401
1402 #ifndef __NO_STRICT_ALIGNMENT
1403 static __inline void
vge_fixup_rx(struct mbuf * m)1404 vge_fixup_rx(struct mbuf *m)
1405 {
1406 int i;
1407 uint16_t *src, *dst;
1408
1409 src = mtod(m, uint16_t *);
1410 dst = src - 1;
1411
1412 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1413 *dst++ = *src++;
1414
1415 m->m_data -= ETHER_ALIGN;
1416 }
1417 #endif
1418
1419 /*
1420 * RX handler. We support the reception of jumbo frames that have
1421 * been fragmented across multiple 2K mbuf cluster buffers.
1422 */
1423 static int
vge_rxeof(struct vge_softc * sc,int count)1424 vge_rxeof(struct vge_softc *sc, int count)
1425 {
1426 struct mbuf *m;
1427 if_t ifp;
1428 int prod, prog, total_len;
1429 struct vge_rxdesc *rxd;
1430 struct vge_rx_desc *cur_rx;
1431 uint32_t rxstat, rxctl;
1432
1433 VGE_LOCK_ASSERT(sc);
1434
1435 ifp = sc->vge_ifp;
1436
1437 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1438 sc->vge_cdata.vge_rx_ring_map,
1439 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1440
1441 prod = sc->vge_cdata.vge_rx_prodidx;
1442 for (prog = 0; count > 0 &&
1443 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;
1444 VGE_RX_DESC_INC(prod)) {
1445 cur_rx = &sc->vge_rdata.vge_rx_ring[prod];
1446 rxstat = le32toh(cur_rx->vge_sts);
1447 if ((rxstat & VGE_RDSTS_OWN) != 0)
1448 break;
1449 count--;
1450 prog++;
1451 rxctl = le32toh(cur_rx->vge_ctl);
1452 total_len = VGE_RXBYTES(rxstat);
1453 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1454 m = rxd->rx_m;
1455
1456 /*
1457 * If the 'start of frame' bit is set, this indicates
1458 * either the first fragment in a multi-fragment receive,
1459 * or an intermediate fragment. Either way, we want to
1460 * accumulate the buffers.
1461 */
1462 if ((rxstat & VGE_RXPKT_SOF) != 0) {
1463 if (vge_newbuf(sc, prod) != 0) {
1464 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1465 VGE_CHAIN_RESET(sc);
1466 vge_discard_rxbuf(sc, prod);
1467 continue;
1468 }
1469 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN;
1470 if (sc->vge_cdata.vge_head == NULL) {
1471 sc->vge_cdata.vge_head = m;
1472 sc->vge_cdata.vge_tail = m;
1473 } else {
1474 m->m_flags &= ~M_PKTHDR;
1475 sc->vge_cdata.vge_tail->m_next = m;
1476 sc->vge_cdata.vge_tail = m;
1477 }
1478 continue;
1479 }
1480
1481 /*
1482 * Bad/error frames will have the RXOK bit cleared.
1483 * However, there's one error case we want to allow:
1484 * if a VLAN tagged frame arrives and the chip can't
1485 * match it against the CAM filter, it considers this
1486 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1487 * We don't want to drop the frame though: our VLAN
1488 * filtering is done in software.
1489 * We also want to receive bad-checksummed frames and
1490 * and frames with bad-length.
1491 */
1492 if ((rxstat & VGE_RDSTS_RXOK) == 0 &&
1493 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR |
1494 VGE_RDSTS_CSUMERR)) == 0) {
1495 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1496 /*
1497 * If this is part of a multi-fragment packet,
1498 * discard all the pieces.
1499 */
1500 VGE_CHAIN_RESET(sc);
1501 vge_discard_rxbuf(sc, prod);
1502 continue;
1503 }
1504
1505 if (vge_newbuf(sc, prod) != 0) {
1506 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1507 VGE_CHAIN_RESET(sc);
1508 vge_discard_rxbuf(sc, prod);
1509 continue;
1510 }
1511
1512 /* Chain received mbufs. */
1513 if (sc->vge_cdata.vge_head != NULL) {
1514 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN);
1515 /*
1516 * Special case: if there's 4 bytes or less
1517 * in this buffer, the mbuf can be discarded:
1518 * the last 4 bytes is the CRC, which we don't
1519 * care about anyway.
1520 */
1521 if (m->m_len <= ETHER_CRC_LEN) {
1522 sc->vge_cdata.vge_tail->m_len -=
1523 (ETHER_CRC_LEN - m->m_len);
1524 m_freem(m);
1525 } else {
1526 m->m_len -= ETHER_CRC_LEN;
1527 m->m_flags &= ~M_PKTHDR;
1528 sc->vge_cdata.vge_tail->m_next = m;
1529 }
1530 m = sc->vge_cdata.vge_head;
1531 m->m_flags |= M_PKTHDR;
1532 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1533 } else {
1534 m->m_flags |= M_PKTHDR;
1535 m->m_pkthdr.len = m->m_len =
1536 (total_len - ETHER_CRC_LEN);
1537 }
1538
1539 #ifndef __NO_STRICT_ALIGNMENT
1540 vge_fixup_rx(m);
1541 #endif
1542 m->m_pkthdr.rcvif = ifp;
1543
1544 /* Do RX checksumming if enabled */
1545 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
1546 (rxctl & VGE_RDCTL_FRAG) == 0) {
1547 /* Check IP header checksum */
1548 if ((rxctl & VGE_RDCTL_IPPKT) != 0)
1549 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1550 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0)
1551 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1552
1553 /* Check TCP/UDP checksum */
1554 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) &&
1555 rxctl & VGE_RDCTL_PROTOCSUMOK) {
1556 m->m_pkthdr.csum_flags |=
1557 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1558 m->m_pkthdr.csum_data = 0xffff;
1559 }
1560 }
1561
1562 if ((rxstat & VGE_RDSTS_VTAG) != 0) {
1563 /*
1564 * The 32-bit rxctl register is stored in little-endian.
1565 * However, the 16-bit vlan tag is stored in big-endian,
1566 * so we have to byte swap it.
1567 */
1568 m->m_pkthdr.ether_vtag =
1569 bswap16(rxctl & VGE_RDCTL_VLANID);
1570 m->m_flags |= M_VLANTAG;
1571 }
1572
1573 VGE_UNLOCK(sc);
1574 if_input(ifp, m);
1575 VGE_LOCK(sc);
1576 sc->vge_cdata.vge_head = NULL;
1577 sc->vge_cdata.vge_tail = NULL;
1578 }
1579
1580 if (prog > 0) {
1581 sc->vge_cdata.vge_rx_prodidx = prod;
1582 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1583 sc->vge_cdata.vge_rx_ring_map,
1584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1585 /* Update residue counter. */
1586 if (sc->vge_cdata.vge_rx_commit != 0) {
1587 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT,
1588 sc->vge_cdata.vge_rx_commit);
1589 sc->vge_cdata.vge_rx_commit = 0;
1590 }
1591 }
1592 return (prog);
1593 }
1594
1595 static void
vge_txeof(struct vge_softc * sc)1596 vge_txeof(struct vge_softc *sc)
1597 {
1598 if_t ifp;
1599 struct vge_tx_desc *cur_tx;
1600 struct vge_txdesc *txd;
1601 uint32_t txstat;
1602 int cons, prod;
1603
1604 VGE_LOCK_ASSERT(sc);
1605
1606 ifp = sc->vge_ifp;
1607
1608 if (sc->vge_cdata.vge_tx_cnt == 0)
1609 return;
1610
1611 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1612 sc->vge_cdata.vge_tx_ring_map,
1613 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1614
1615 /*
1616 * Go through our tx list and free mbufs for those
1617 * frames that have been transmitted.
1618 */
1619 cons = sc->vge_cdata.vge_tx_considx;
1620 prod = sc->vge_cdata.vge_tx_prodidx;
1621 for (; cons != prod; VGE_TX_DESC_INC(cons)) {
1622 cur_tx = &sc->vge_rdata.vge_tx_ring[cons];
1623 txstat = le32toh(cur_tx->vge_sts);
1624 if ((txstat & VGE_TDSTS_OWN) != 0)
1625 break;
1626 sc->vge_cdata.vge_tx_cnt--;
1627 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1628
1629 txd = &sc->vge_cdata.vge_txdesc[cons];
1630 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap,
1631 BUS_DMASYNC_POSTWRITE);
1632 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap);
1633
1634 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n",
1635 __func__));
1636 m_freem(txd->tx_m);
1637 txd->tx_m = NULL;
1638 txd->tx_desc->vge_frag[0].vge_addrhi = 0;
1639 }
1640 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1641 sc->vge_cdata.vge_tx_ring_map,
1642 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1643 sc->vge_cdata.vge_tx_considx = cons;
1644 if (sc->vge_cdata.vge_tx_cnt == 0)
1645 sc->vge_timer = 0;
1646 }
1647
1648 static void
vge_link_statchg(void * xsc)1649 vge_link_statchg(void *xsc)
1650 {
1651 struct vge_softc *sc;
1652 if_t ifp;
1653 uint8_t physts;
1654
1655 sc = xsc;
1656 ifp = sc->vge_ifp;
1657 VGE_LOCK_ASSERT(sc);
1658
1659 physts = CSR_READ_1(sc, VGE_PHYSTS0);
1660 if ((physts & VGE_PHYSTS_RESETSTS) == 0) {
1661 if ((physts & VGE_PHYSTS_LINK) == 0) {
1662 sc->vge_flags &= ~VGE_FLAG_LINK;
1663 if_link_state_change(sc->vge_ifp,
1664 LINK_STATE_DOWN);
1665 } else {
1666 sc->vge_flags |= VGE_FLAG_LINK;
1667 if_link_state_change(sc->vge_ifp,
1668 LINK_STATE_UP);
1669 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |
1670 VGE_CR2_FDX_RXFLOWCTL_ENABLE);
1671 if ((physts & VGE_PHYSTS_FDX) != 0) {
1672 if ((physts & VGE_PHYSTS_TXFLOWCAP) != 0)
1673 CSR_WRITE_1(sc, VGE_CRS2,
1674 VGE_CR2_FDX_TXFLOWCTL_ENABLE);
1675 if ((physts & VGE_PHYSTS_RXFLOWCAP) != 0)
1676 CSR_WRITE_1(sc, VGE_CRS2,
1677 VGE_CR2_FDX_RXFLOWCTL_ENABLE);
1678 }
1679 if (!if_sendq_empty(ifp))
1680 vge_start_locked(ifp);
1681 }
1682 }
1683 /*
1684 * Restart MII auto-polling because link state change interrupt
1685 * will disable it.
1686 */
1687 vge_miipoll_start(sc);
1688 }
1689
1690 #ifdef DEVICE_POLLING
1691 static int
vge_poll(if_t ifp,enum poll_cmd cmd,int count)1692 vge_poll (if_t ifp, enum poll_cmd cmd, int count)
1693 {
1694 struct vge_softc *sc = if_getsoftc(ifp);
1695 int rx_npkts = 0;
1696
1697 VGE_LOCK(sc);
1698 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
1699 goto done;
1700
1701 rx_npkts = vge_rxeof(sc, count);
1702 vge_txeof(sc);
1703
1704 if (!if_sendq_empty(ifp))
1705 vge_start_locked(ifp);
1706
1707 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1708 uint32_t status;
1709 status = CSR_READ_4(sc, VGE_ISR);
1710 if (status == 0xFFFFFFFF)
1711 goto done;
1712 if (status)
1713 CSR_WRITE_4(sc, VGE_ISR, status);
1714
1715 /*
1716 * XXX check behaviour on receiver stalls.
1717 */
1718
1719 if (status & VGE_ISR_TXDMA_STALL ||
1720 status & VGE_ISR_RXDMA_STALL) {
1721 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1722 vge_init_locked(sc);
1723 }
1724
1725 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1726 vge_rxeof(sc, count);
1727 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1728 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1729 }
1730 }
1731 done:
1732 VGE_UNLOCK(sc);
1733 return (rx_npkts);
1734 }
1735 #endif /* DEVICE_POLLING */
1736
1737 static void
vge_intr(void * arg)1738 vge_intr(void *arg)
1739 {
1740 struct vge_softc *sc;
1741 if_t ifp;
1742 uint32_t status;
1743
1744 sc = arg;
1745 VGE_LOCK(sc);
1746
1747 ifp = sc->vge_ifp;
1748 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 ||
1749 (if_getflags(ifp) & IFF_UP) == 0) {
1750 VGE_UNLOCK(sc);
1751 return;
1752 }
1753
1754 #ifdef DEVICE_POLLING
1755 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1756 status = CSR_READ_4(sc, VGE_ISR);
1757 CSR_WRITE_4(sc, VGE_ISR, status);
1758 if (status != 0xFFFFFFFF && (status & VGE_ISR_LINKSTS) != 0)
1759 vge_link_statchg(sc);
1760 VGE_UNLOCK(sc);
1761 return;
1762 }
1763 #endif
1764
1765 /* Disable interrupts */
1766 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1767 status = CSR_READ_4(sc, VGE_ISR);
1768 CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD);
1769 /* If the card has gone away the read returns 0xffff. */
1770 if (status == 0xFFFFFFFF || (status & VGE_INTRS) == 0)
1771 goto done;
1772 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1773 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO))
1774 vge_rxeof(sc, VGE_RX_DESC_CNT);
1775 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1776 vge_rxeof(sc, VGE_RX_DESC_CNT);
1777 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1778 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1779 }
1780
1781 if (status & (VGE_ISR_TXOK0|VGE_ISR_TXOK_HIPRIO))
1782 vge_txeof(sc);
1783
1784 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) {
1785 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1786 vge_init_locked(sc);
1787 }
1788
1789 if (status & VGE_ISR_LINKSTS)
1790 vge_link_statchg(sc);
1791 }
1792 done:
1793 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1794 /* Re-enable interrupts */
1795 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1796
1797 if (!if_sendq_empty(ifp))
1798 vge_start_locked(ifp);
1799 }
1800 VGE_UNLOCK(sc);
1801 }
1802
1803 static int
vge_encap(struct vge_softc * sc,struct mbuf ** m_head)1804 vge_encap(struct vge_softc *sc, struct mbuf **m_head)
1805 {
1806 struct vge_txdesc *txd;
1807 struct vge_tx_frag *frag;
1808 struct mbuf *m;
1809 bus_dma_segment_t txsegs[VGE_MAXTXSEGS];
1810 int error, i, nsegs, padlen;
1811 uint32_t cflags;
1812
1813 VGE_LOCK_ASSERT(sc);
1814
1815 M_ASSERTPKTHDR((*m_head));
1816
1817 /* Argh. This chip does not autopad short frames. */
1818 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) {
1819 m = *m_head;
1820 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len;
1821 if (M_WRITABLE(m) == 0) {
1822 /* Get a writable copy. */
1823 m = m_dup(*m_head, M_NOWAIT);
1824 m_freem(*m_head);
1825 if (m == NULL) {
1826 *m_head = NULL;
1827 return (ENOBUFS);
1828 }
1829 *m_head = m;
1830 }
1831 if (M_TRAILINGSPACE(m) < padlen) {
1832 m = m_defrag(m, M_NOWAIT);
1833 if (m == NULL) {
1834 m_freem(*m_head);
1835 *m_head = NULL;
1836 return (ENOBUFS);
1837 }
1838 }
1839 /*
1840 * Manually pad short frames, and zero the pad space
1841 * to avoid leaking data.
1842 */
1843 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1844 m->m_pkthdr.len += padlen;
1845 m->m_len = m->m_pkthdr.len;
1846 *m_head = m;
1847 }
1848
1849 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx];
1850
1851 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag,
1852 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1853 if (error == EFBIG) {
1854 m = m_collapse(*m_head, M_NOWAIT, VGE_MAXTXSEGS);
1855 if (m == NULL) {
1856 m_freem(*m_head);
1857 *m_head = NULL;
1858 return (ENOMEM);
1859 }
1860 *m_head = m;
1861 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag,
1862 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1863 if (error != 0) {
1864 m_freem(*m_head);
1865 *m_head = NULL;
1866 return (error);
1867 }
1868 } else if (error != 0)
1869 return (error);
1870 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap,
1871 BUS_DMASYNC_PREWRITE);
1872
1873 m = *m_head;
1874 cflags = 0;
1875
1876 /* Configure checksum offload. */
1877 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1878 cflags |= VGE_TDCTL_IPCSUM;
1879 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1880 cflags |= VGE_TDCTL_TCPCSUM;
1881 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1882 cflags |= VGE_TDCTL_UDPCSUM;
1883
1884 /* Configure VLAN. */
1885 if ((m->m_flags & M_VLANTAG) != 0)
1886 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG;
1887 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16);
1888 /*
1889 * XXX
1890 * Velocity family seems to support TSO but no information
1891 * for MSS configuration is available. Also the number of
1892 * fragments supported by a descriptor is too small to hold
1893 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF,
1894 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build
1895 * longer chain of buffers but no additional information is
1896 * available.
1897 *
1898 * When telling the chip how many segments there are, we
1899 * must use nsegs + 1 instead of just nsegs. Darned if I
1900 * know why. This also means we can't use the last fragment
1901 * field of Tx descriptor.
1902 */
1903 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) |
1904 VGE_TD_LS_NORM);
1905 for (i = 0; i < nsegs; i++) {
1906 frag = &txd->tx_desc->vge_frag[i];
1907 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr));
1908 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) |
1909 (VGE_BUFLEN(txsegs[i].ds_len) << 16));
1910 }
1911
1912 sc->vge_cdata.vge_tx_cnt++;
1913 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx);
1914
1915 /*
1916 * Finally request interrupt and give the first descriptor
1917 * ownership to hardware.
1918 */
1919 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC);
1920 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN);
1921 txd->tx_m = m;
1922
1923 return (0);
1924 }
1925
1926 /*
1927 * Main transmit routine.
1928 */
1929
1930 static void
vge_start(if_t ifp)1931 vge_start(if_t ifp)
1932 {
1933 struct vge_softc *sc;
1934
1935 sc = if_getsoftc(ifp);
1936 VGE_LOCK(sc);
1937 vge_start_locked(ifp);
1938 VGE_UNLOCK(sc);
1939 }
1940
1941 static void
vge_start_locked(if_t ifp)1942 vge_start_locked(if_t ifp)
1943 {
1944 struct vge_softc *sc;
1945 struct vge_txdesc *txd;
1946 struct mbuf *m_head;
1947 int enq, idx;
1948
1949 sc = if_getsoftc(ifp);
1950
1951 VGE_LOCK_ASSERT(sc);
1952
1953 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 ||
1954 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1955 IFF_DRV_RUNNING)
1956 return;
1957
1958 idx = sc->vge_cdata.vge_tx_prodidx;
1959 VGE_TX_DESC_DEC(idx);
1960 for (enq = 0; !if_sendq_empty(ifp) &&
1961 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) {
1962 m_head = if_dequeue(ifp);
1963 if (m_head == NULL)
1964 break;
1965 /*
1966 * Pack the data into the transmit ring. If we
1967 * don't have room, set the OACTIVE flag and wait
1968 * for the NIC to drain the ring.
1969 */
1970 if (vge_encap(sc, &m_head)) {
1971 if (m_head == NULL)
1972 break;
1973 if_sendq_prepend(ifp, m_head);
1974 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1975 break;
1976 }
1977
1978 txd = &sc->vge_cdata.vge_txdesc[idx];
1979 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q);
1980 VGE_TX_DESC_INC(idx);
1981
1982 enq++;
1983 /*
1984 * If there's a BPF listener, bounce a copy of this frame
1985 * to him.
1986 */
1987 ETHER_BPF_MTAP(ifp, m_head);
1988 }
1989
1990 if (enq > 0) {
1991 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1992 sc->vge_cdata.vge_tx_ring_map,
1993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1994 /* Issue a transmit command. */
1995 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1996 /*
1997 * Set a timeout in case the chip goes out to lunch.
1998 */
1999 sc->vge_timer = 5;
2000 }
2001 }
2002
2003 static void
vge_init(void * xsc)2004 vge_init(void *xsc)
2005 {
2006 struct vge_softc *sc = xsc;
2007
2008 VGE_LOCK(sc);
2009 vge_init_locked(sc);
2010 VGE_UNLOCK(sc);
2011 }
2012
2013 static void
vge_init_locked(struct vge_softc * sc)2014 vge_init_locked(struct vge_softc *sc)
2015 {
2016 if_t ifp = sc->vge_ifp;
2017 int error, i;
2018
2019 VGE_LOCK_ASSERT(sc);
2020
2021 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2022 return;
2023
2024 /*
2025 * Cancel pending I/O and free all RX/TX buffers.
2026 */
2027 vge_stop(sc);
2028 vge_reset(sc);
2029 vge_miipoll_start(sc);
2030
2031 /*
2032 * Initialize the RX and TX descriptors and mbufs.
2033 */
2034
2035 error = vge_rx_list_init(sc);
2036 if (error != 0) {
2037 device_printf(sc->vge_dev, "no memory for Rx buffers.\n");
2038 return;
2039 }
2040 vge_tx_list_init(sc);
2041 /* Clear MAC statistics. */
2042 vge_stats_clear(sc);
2043 /* Set our station address */
2044 for (i = 0; i < ETHER_ADDR_LEN; i++)
2045 CSR_WRITE_1(sc, VGE_PAR0 + i, if_getlladdr(sc->vge_ifp)[i]);
2046
2047 /*
2048 * Set receive FIFO threshold. Also allow transmission and
2049 * reception of VLAN tagged frames.
2050 */
2051 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT);
2052 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES);
2053
2054 /* Set DMA burst length */
2055 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
2056 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
2057
2058 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
2059
2060 /* Set collision backoff algorithm */
2061 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
2062 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT);
2063 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2064
2065 /* Disable LPSEL field in priority resolution */
2066 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2067
2068 /*
2069 * Load the addresses of the DMA queues into the chip.
2070 * Note that we only use one transmit queue.
2071 */
2072
2073 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR,
2074 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr));
2075 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
2076 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr));
2077 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
2078
2079 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
2080 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr));
2081 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
2082 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
2083
2084 /* Configure interrupt moderation. */
2085 vge_intr_holdoff(sc);
2086
2087 /* Enable and wake up the RX descriptor queue */
2088 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
2089 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
2090
2091 /* Enable the TX descriptor queue */
2092 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
2093
2094 /* Init the cam filter. */
2095 vge_cam_clear(sc);
2096
2097 /* Set up receiver filter. */
2098 vge_rxfilter(sc);
2099 vge_setvlan(sc);
2100
2101 /* Initialize pause timer. */
2102 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
2103 /*
2104 * Initialize flow control parameters.
2105 * TX XON high threshold : 48
2106 * TX pause low threshold : 24
2107 * Disable hald-duplex flow control
2108 */
2109 CSR_WRITE_1(sc, VGE_CRC2, 0xFF);
2110 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);
2111
2112 /* Enable jumbo frame reception (if desired) */
2113
2114 /* Start the MAC. */
2115 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
2116 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
2117 CSR_WRITE_1(sc, VGE_CRS0,
2118 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START);
2119
2120 #ifdef DEVICE_POLLING
2121 /*
2122 * Disable interrupts except link state change if we are polling.
2123 */
2124 if (if_getcapenable(ifp) & IFCAP_POLLING) {
2125 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING);
2126 } else /* otherwise ... */
2127 #endif
2128 {
2129 /*
2130 * Enable interrupts.
2131 */
2132 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2133 }
2134 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2135 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2136
2137 sc->vge_flags &= ~VGE_FLAG_LINK;
2138 vge_ifmedia_upd_locked(sc);
2139
2140 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2141 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2142 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
2143 }
2144
2145 /*
2146 * Set media options.
2147 */
2148 static int
vge_ifmedia_upd(if_t ifp)2149 vge_ifmedia_upd(if_t ifp)
2150 {
2151 struct vge_softc *sc;
2152 int error;
2153
2154 sc = if_getsoftc(ifp);
2155 VGE_LOCK(sc);
2156 error = vge_ifmedia_upd_locked(sc);
2157 VGE_UNLOCK(sc);
2158
2159 return (error);
2160 }
2161
2162 static int
vge_ifmedia_upd_locked(struct vge_softc * sc)2163 vge_ifmedia_upd_locked(struct vge_softc *sc)
2164 {
2165 struct mii_data *mii;
2166 struct mii_softc *miisc;
2167 int error;
2168
2169 mii = device_get_softc(sc->vge_miibus);
2170 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2171 PHY_RESET(miisc);
2172 vge_setmedia(sc);
2173 error = mii_mediachg(mii);
2174
2175 return (error);
2176 }
2177
2178 /*
2179 * Report current media status.
2180 */
2181 static void
vge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2182 vge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2183 {
2184 struct vge_softc *sc;
2185 struct mii_data *mii;
2186
2187 sc = if_getsoftc(ifp);
2188 mii = device_get_softc(sc->vge_miibus);
2189
2190 VGE_LOCK(sc);
2191 if ((if_getflags(ifp) & IFF_UP) == 0) {
2192 VGE_UNLOCK(sc);
2193 return;
2194 }
2195 mii_pollstat(mii);
2196 ifmr->ifm_active = mii->mii_media_active;
2197 ifmr->ifm_status = mii->mii_media_status;
2198 VGE_UNLOCK(sc);
2199 }
2200
2201 static void
vge_setmedia(struct vge_softc * sc)2202 vge_setmedia(struct vge_softc *sc)
2203 {
2204 struct mii_data *mii;
2205 struct ifmedia_entry *ife;
2206
2207 mii = device_get_softc(sc->vge_miibus);
2208 ife = mii->mii_media.ifm_cur;
2209
2210 /*
2211 * If the user manually selects a media mode, we need to turn
2212 * on the forced MAC mode bit in the DIAGCTL register. If the
2213 * user happens to choose a full duplex mode, we also need to
2214 * set the 'force full duplex' bit. This applies only to
2215 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
2216 * mode is disabled, and in 1000baseT mode, full duplex is
2217 * always implied, so we turn on the forced mode bit but leave
2218 * the FDX bit cleared.
2219 */
2220
2221 switch (IFM_SUBTYPE(ife->ifm_media)) {
2222 case IFM_AUTO:
2223 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2224 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2225 break;
2226 case IFM_1000_T:
2227 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2228 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2229 break;
2230 case IFM_100_TX:
2231 case IFM_10_T:
2232 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2233 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
2234 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2235 } else {
2236 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2237 }
2238 break;
2239 default:
2240 device_printf(sc->vge_dev, "unknown media type: %x\n",
2241 IFM_SUBTYPE(ife->ifm_media));
2242 break;
2243 }
2244 }
2245
2246 static int
vge_ioctl(if_t ifp,u_long command,caddr_t data)2247 vge_ioctl(if_t ifp, u_long command, caddr_t data)
2248 {
2249 struct vge_softc *sc = if_getsoftc(ifp);
2250 struct ifreq *ifr = (struct ifreq *) data;
2251 struct mii_data *mii;
2252 int error = 0, mask;
2253
2254 switch (command) {
2255 case SIOCSIFMTU:
2256 VGE_LOCK(sc);
2257 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU)
2258 error = EINVAL;
2259 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
2260 if (ifr->ifr_mtu > ETHERMTU &&
2261 (sc->vge_flags & VGE_FLAG_JUMBO) == 0)
2262 error = EINVAL;
2263 else
2264 if_setmtu(ifp, ifr->ifr_mtu);
2265 }
2266 VGE_UNLOCK(sc);
2267 break;
2268 case SIOCSIFFLAGS:
2269 VGE_LOCK(sc);
2270 if ((if_getflags(ifp) & IFF_UP) != 0) {
2271 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
2272 ((if_getflags(ifp) ^ sc->vge_if_flags) &
2273 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2274 vge_rxfilter(sc);
2275 else
2276 vge_init_locked(sc);
2277 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2278 vge_stop(sc);
2279 sc->vge_if_flags = if_getflags(ifp);
2280 VGE_UNLOCK(sc);
2281 break;
2282 case SIOCADDMULTI:
2283 case SIOCDELMULTI:
2284 VGE_LOCK(sc);
2285 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2286 vge_rxfilter(sc);
2287 VGE_UNLOCK(sc);
2288 break;
2289 case SIOCGIFMEDIA:
2290 case SIOCSIFMEDIA:
2291 mii = device_get_softc(sc->vge_miibus);
2292 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2293 break;
2294 case SIOCSIFCAP:
2295 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2296 #ifdef DEVICE_POLLING
2297 if (mask & IFCAP_POLLING) {
2298 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2299 error = ether_poll_register(vge_poll, ifp);
2300 if (error)
2301 return (error);
2302 VGE_LOCK(sc);
2303 /* Disable interrupts */
2304 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING);
2305 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2306 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2307 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2308 VGE_UNLOCK(sc);
2309 } else {
2310 error = ether_poll_deregister(ifp);
2311 /* Enable interrupts. */
2312 VGE_LOCK(sc);
2313 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2314 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2315 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2316 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2317 VGE_UNLOCK(sc);
2318 }
2319 }
2320 #endif /* DEVICE_POLLING */
2321 VGE_LOCK(sc);
2322 if ((mask & IFCAP_TXCSUM) != 0 &&
2323 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2324 if_togglecapenable(ifp, IFCAP_TXCSUM);
2325 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2326 if_sethwassistbits(ifp, VGE_CSUM_FEATURES, 0);
2327 else
2328 if_sethwassistbits(ifp, 0, VGE_CSUM_FEATURES);
2329 }
2330 if ((mask & IFCAP_RXCSUM) != 0 &&
2331 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
2332 if_togglecapenable(ifp, IFCAP_RXCSUM);
2333 if ((mask & IFCAP_WOL_UCAST) != 0 &&
2334 (if_getcapabilities(ifp) & IFCAP_WOL_UCAST) != 0)
2335 if_togglecapenable(ifp, IFCAP_WOL_UCAST);
2336 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2337 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
2338 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
2339 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2340 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2341 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2342 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2343 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2344 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2345 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2346 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) {
2347 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2348 vge_setvlan(sc);
2349 }
2350 VGE_UNLOCK(sc);
2351 VLAN_CAPABILITIES(ifp);
2352 break;
2353 default:
2354 error = ether_ioctl(ifp, command, data);
2355 break;
2356 }
2357
2358 return (error);
2359 }
2360
2361 static void
vge_watchdog(void * arg)2362 vge_watchdog(void *arg)
2363 {
2364 struct vge_softc *sc;
2365 if_t ifp;
2366
2367 sc = arg;
2368 VGE_LOCK_ASSERT(sc);
2369 vge_stats_update(sc);
2370 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
2371 if (sc->vge_timer == 0 || --sc->vge_timer > 0)
2372 return;
2373
2374 ifp = sc->vge_ifp;
2375 if_printf(ifp, "watchdog timeout\n");
2376 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2377
2378 vge_txeof(sc);
2379 vge_rxeof(sc, VGE_RX_DESC_CNT);
2380
2381 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2382 vge_init_locked(sc);
2383 }
2384
2385 /*
2386 * Stop the adapter and free any mbufs allocated to the
2387 * RX and TX lists.
2388 */
2389 static void
vge_stop(struct vge_softc * sc)2390 vge_stop(struct vge_softc *sc)
2391 {
2392 if_t ifp;
2393
2394 VGE_LOCK_ASSERT(sc);
2395 ifp = sc->vge_ifp;
2396 sc->vge_timer = 0;
2397 callout_stop(&sc->vge_watchdog);
2398
2399 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2400
2401 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2402 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2403 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2404 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2405 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2406 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2407
2408 vge_stats_update(sc);
2409 VGE_CHAIN_RESET(sc);
2410 vge_txeof(sc);
2411 vge_freebufs(sc);
2412 }
2413
2414 /*
2415 * Device suspend routine. Stop the interface and save some PCI
2416 * settings in case the BIOS doesn't restore them properly on
2417 * resume.
2418 */
2419 static int
vge_suspend(device_t dev)2420 vge_suspend(device_t dev)
2421 {
2422 struct vge_softc *sc;
2423
2424 sc = device_get_softc(dev);
2425
2426 VGE_LOCK(sc);
2427 vge_stop(sc);
2428 vge_setwol(sc);
2429 sc->vge_flags |= VGE_FLAG_SUSPENDED;
2430 VGE_UNLOCK(sc);
2431
2432 return (0);
2433 }
2434
2435 /*
2436 * Device resume routine. Restore some PCI settings in case the BIOS
2437 * doesn't, re-enable busmastering, and restart the interface if
2438 * appropriate.
2439 */
2440 static int
vge_resume(device_t dev)2441 vge_resume(device_t dev)
2442 {
2443 struct vge_softc *sc;
2444 if_t ifp;
2445
2446 sc = device_get_softc(dev);
2447 VGE_LOCK(sc);
2448 vge_clrwol(sc);
2449 /* Restart MII auto-polling. */
2450 vge_miipoll_start(sc);
2451 ifp = sc->vge_ifp;
2452 /* Reinitialize interface if necessary. */
2453 if ((if_getflags(ifp) & IFF_UP) != 0) {
2454 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2455 vge_init_locked(sc);
2456 }
2457 sc->vge_flags &= ~VGE_FLAG_SUSPENDED;
2458 VGE_UNLOCK(sc);
2459
2460 return (0);
2461 }
2462
2463 /*
2464 * Stop all chip I/O so that the kernel's probe routines don't
2465 * get confused by errant DMAs when rebooting.
2466 */
2467 static int
vge_shutdown(device_t dev)2468 vge_shutdown(device_t dev)
2469 {
2470
2471 return (vge_suspend(dev));
2472 }
2473
2474 #define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2475 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2476
2477 static void
vge_sysctl_node(struct vge_softc * sc)2478 vge_sysctl_node(struct vge_softc *sc)
2479 {
2480 struct sysctl_ctx_list *ctx;
2481 struct sysctl_oid_list *child, *parent;
2482 struct sysctl_oid *tree;
2483 struct vge_hw_stats *stats;
2484
2485 stats = &sc->vge_stats;
2486 ctx = device_get_sysctl_ctx(sc->vge_dev);
2487 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev));
2488
2489 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_holdoff",
2490 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff");
2491 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rx_coal_pkt",
2492 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet");
2493 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "tx_coal_pkt",
2494 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet");
2495
2496 /* Pull in device tunables. */
2497 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT;
2498 resource_int_value(device_get_name(sc->vge_dev),
2499 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff);
2500 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT;
2501 resource_int_value(device_get_name(sc->vge_dev),
2502 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt);
2503 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT;
2504 resource_int_value(device_get_name(sc->vge_dev),
2505 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt);
2506
2507 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
2508 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VGE statistics");
2509 parent = SYSCTL_CHILDREN(tree);
2510
2511 /* Rx statistics. */
2512 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
2513 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics");
2514 child = SYSCTL_CHILDREN(tree);
2515 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames",
2516 &stats->rx_frames, "frames");
2517 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2518 &stats->rx_good_frames, "Good frames");
2519 VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
2520 &stats->rx_fifo_oflows, "FIFO overflows");
2521 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts",
2522 &stats->rx_runts, "Too short frames");
2523 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs",
2524 &stats->rx_runts_errs, "Too short frames with errors");
2525 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
2526 &stats->rx_pkts_64, "64 bytes frames");
2527 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
2528 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
2529 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
2530 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
2531 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
2532 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
2533 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
2534 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
2535 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
2536 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
2537 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
2538 &stats->rx_pkts_1519_max, "1519 to max frames");
2539 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs",
2540 &stats->rx_pkts_1519_max_errs, "1519 to max frames with error");
2541 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo",
2542 &stats->rx_jumbos, "Jumbo frames");
2543 VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs",
2544 &stats->rx_crcerrs, "CRC errors");
2545 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
2546 &stats->rx_pause_frames, "Pause frames");
2547 VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
2548 &stats->rx_alignerrs, "Alignment errors");
2549 VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs",
2550 &stats->rx_nobufs, "Frames with no buffer event");
2551 VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs",
2552 &stats->rx_symerrs, "Frames with symbol errors");
2553 VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
2554 &stats->rx_lenerrs, "Frames with length mismatched");
2555
2556 /* Tx statistics. */
2557 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
2558 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics");
2559 child = SYSCTL_CHILDREN(tree);
2560 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2561 &stats->tx_good_frames, "Good frames");
2562 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
2563 &stats->tx_pkts_64, "64 bytes frames");
2564 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
2565 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
2566 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
2567 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
2568 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
2569 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
2570 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
2571 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
2572 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
2573 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
2574 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo",
2575 &stats->tx_jumbos, "Jumbo frames");
2576 VGE_SYSCTL_STAT_ADD32(ctx, child, "colls",
2577 &stats->tx_colls, "Collisions");
2578 VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2579 &stats->tx_latecolls, "Late collisions");
2580 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
2581 &stats->tx_pause, "Pause frames");
2582 #ifdef VGE_ENABLE_SQEERR
2583 VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs",
2584 &stats->tx_sqeerrs, "SQE errors");
2585 #endif
2586 /* Clear MAC statistics. */
2587 vge_stats_clear(sc);
2588 }
2589
2590 #undef VGE_SYSCTL_STAT_ADD32
2591
2592 static void
vge_stats_clear(struct vge_softc * sc)2593 vge_stats_clear(struct vge_softc *sc)
2594 {
2595 int i;
2596
2597 CSR_WRITE_1(sc, VGE_MIBCSR,
2598 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE);
2599 CSR_WRITE_1(sc, VGE_MIBCSR,
2600 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR);
2601 for (i = VGE_TIMEOUT; i > 0; i--) {
2602 DELAY(1);
2603 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0)
2604 break;
2605 }
2606 if (i == 0)
2607 device_printf(sc->vge_dev, "MIB clear timed out!\n");
2608 CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) &
2609 ~VGE_MIBCSR_FREEZE);
2610 }
2611
2612 static void
vge_stats_update(struct vge_softc * sc)2613 vge_stats_update(struct vge_softc *sc)
2614 {
2615 struct vge_hw_stats *stats;
2616 if_t ifp;
2617 uint32_t mib[VGE_MIB_CNT], val;
2618 int i;
2619
2620 VGE_LOCK_ASSERT(sc);
2621
2622 stats = &sc->vge_stats;
2623 ifp = sc->vge_ifp;
2624
2625 CSR_WRITE_1(sc, VGE_MIBCSR,
2626 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH);
2627 for (i = VGE_TIMEOUT; i > 0; i--) {
2628 DELAY(1);
2629 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0)
2630 break;
2631 }
2632 if (i == 0) {
2633 device_printf(sc->vge_dev, "MIB counter dump timed out!\n");
2634 vge_stats_clear(sc);
2635 return;
2636 }
2637
2638 bzero(mib, sizeof(mib));
2639 reset_idx:
2640 /* Set MIB read index to 0. */
2641 CSR_WRITE_1(sc, VGE_MIBCSR,
2642 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI);
2643 for (i = 0; i < VGE_MIB_CNT; i++) {
2644 val = CSR_READ_4(sc, VGE_MIBDATA);
2645 if (i != VGE_MIB_DATA_IDX(val)) {
2646 /* Reading interrupted. */
2647 goto reset_idx;
2648 }
2649 mib[i] = val & VGE_MIB_DATA_MASK;
2650 }
2651
2652 /* Rx stats. */
2653 stats->rx_frames += mib[VGE_MIB_RX_FRAMES];
2654 stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES];
2655 stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS];
2656 stats->rx_runts += mib[VGE_MIB_RX_RUNTS];
2657 stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS];
2658 stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64];
2659 stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127];
2660 stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255];
2661 stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511];
2662 stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023];
2663 stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518];
2664 stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX];
2665 stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS];
2666 stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS];
2667 stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS];
2668 stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE];
2669 stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS];
2670 stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS];
2671 stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS];
2672 stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS];
2673
2674 /* Tx stats. */
2675 stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES];
2676 stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64];
2677 stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127];
2678 stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255];
2679 stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511];
2680 stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023];
2681 stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518];
2682 stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS];
2683 stats->tx_colls += mib[VGE_MIB_TX_COLLS];
2684 stats->tx_pause += mib[VGE_MIB_TX_PAUSE];
2685 #ifdef VGE_ENABLE_SQEERR
2686 stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS];
2687 #endif
2688 stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS];
2689
2690 /* Update counters in ifnet. */
2691 if_inc_counter(ifp, IFCOUNTER_OPACKETS, mib[VGE_MIB_TX_GOOD_FRAMES]);
2692
2693 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2694 mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]);
2695
2696 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2697 mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]);
2698
2699 if_inc_counter(ifp, IFCOUNTER_IPACKETS, mib[VGE_MIB_RX_GOOD_FRAMES]);
2700
2701 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2702 mib[VGE_MIB_RX_FIFO_OVERRUNS] +
2703 mib[VGE_MIB_RX_RUNTS] +
2704 mib[VGE_MIB_RX_RUNTS_ERRS] +
2705 mib[VGE_MIB_RX_CRCERRS] +
2706 mib[VGE_MIB_RX_ALIGNERRS] +
2707 mib[VGE_MIB_RX_NOBUFS] +
2708 mib[VGE_MIB_RX_SYMERRS] +
2709 mib[VGE_MIB_RX_LENERRS]);
2710 }
2711
2712 static void
vge_intr_holdoff(struct vge_softc * sc)2713 vge_intr_holdoff(struct vge_softc *sc)
2714 {
2715 uint8_t intctl;
2716
2717 VGE_LOCK_ASSERT(sc);
2718
2719 /*
2720 * Set Tx interrupt supression threshold.
2721 * It's possible to use single-shot timer in VGE_CRS1 register
2722 * in Tx path such that driver can remove most of Tx completion
2723 * interrupts. However this requires additional access to
2724 * VGE_CRS1 register to reload the timer in addintion to
2725 * activating Tx kick command. Another downside is we don't know
2726 * what single-shot timer value should be used in advance so
2727 * reclaiming transmitted mbufs could be delayed a lot which in
2728 * turn slows down Tx operation.
2729 */
2730 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR);
2731 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt);
2732
2733 /* Set Rx interrupt suppresion threshold. */
2734 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
2735 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt);
2736
2737 intctl = CSR_READ_1(sc, VGE_INTCTL1);
2738 intctl &= ~VGE_INTCTL_SC_RELOAD;
2739 intctl |= VGE_INTCTL_HC_RELOAD;
2740 if (sc->vge_tx_coal_pkt <= 0)
2741 intctl |= VGE_INTCTL_TXINTSUP_DISABLE;
2742 else
2743 intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE;
2744 if (sc->vge_rx_coal_pkt <= 0)
2745 intctl |= VGE_INTCTL_RXINTSUP_DISABLE;
2746 else
2747 intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE;
2748 CSR_WRITE_1(sc, VGE_INTCTL1, intctl);
2749 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF);
2750 if (sc->vge_int_holdoff > 0) {
2751 /* Set interrupt holdoff timer. */
2752 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
2753 CSR_WRITE_1(sc, VGE_INTHOLDOFF,
2754 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff));
2755 /* Enable holdoff timer. */
2756 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
2757 }
2758 }
2759
2760 static void
vge_setlinkspeed(struct vge_softc * sc)2761 vge_setlinkspeed(struct vge_softc *sc)
2762 {
2763 struct mii_data *mii;
2764 int aneg, i;
2765
2766 VGE_LOCK_ASSERT(sc);
2767
2768 mii = device_get_softc(sc->vge_miibus);
2769 mii_pollstat(mii);
2770 aneg = 0;
2771 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2772 (IFM_ACTIVE | IFM_AVALID)) {
2773 switch IFM_SUBTYPE(mii->mii_media_active) {
2774 case IFM_10_T:
2775 case IFM_100_TX:
2776 return;
2777 case IFM_1000_T:
2778 aneg++;
2779 default:
2780 break;
2781 }
2782 }
2783 /* Clear forced MAC speed/duplex configuration. */
2784 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2785 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2786 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0);
2787 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR,
2788 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
2789 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
2790 BMCR_AUTOEN | BMCR_STARTNEG);
2791 DELAY(1000);
2792 if (aneg != 0) {
2793 /* Poll link state until vge(4) get a 10/100 link. */
2794 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
2795 mii_pollstat(mii);
2796 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
2797 == (IFM_ACTIVE | IFM_AVALID)) {
2798 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2799 case IFM_10_T:
2800 case IFM_100_TX:
2801 return;
2802 default:
2803 break;
2804 }
2805 }
2806 VGE_UNLOCK(sc);
2807 pause("vgelnk", hz);
2808 VGE_LOCK(sc);
2809 }
2810 if (i == MII_ANEGTICKS_GIGE)
2811 device_printf(sc->vge_dev, "establishing link failed, "
2812 "WOL may not work!");
2813 }
2814 /*
2815 * No link, force MAC to have 100Mbps, full-duplex link.
2816 * This is the last resort and may/may not work.
2817 */
2818 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
2819 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
2820 }
2821
2822 static void
vge_setwol(struct vge_softc * sc)2823 vge_setwol(struct vge_softc *sc)
2824 {
2825 if_t ifp;
2826 uint8_t val;
2827
2828 VGE_LOCK_ASSERT(sc);
2829
2830 if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) {
2831 /* No PME capability, PHY power down. */
2832 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
2833 BMCR_PDOWN);
2834 vge_miipoll_stop(sc);
2835 return;
2836 }
2837
2838 ifp = sc->vge_ifp;
2839
2840 /* Clear WOL on pattern match. */
2841 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2842 /* Disable WOL on magic/unicast packet. */
2843 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2844 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2845 VGE_WOLCFG_PMEOVR);
2846 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
2847 vge_setlinkspeed(sc);
2848 val = 0;
2849 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0)
2850 val |= VGE_WOLCR1_UCAST;
2851 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2852 val |= VGE_WOLCR1_MAGIC;
2853 CSR_WRITE_1(sc, VGE_WOLCR1S, val);
2854 val = 0;
2855 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2856 val |= VGE_WOLCFG_SAM | VGE_WOLCFG_SAB;
2857 CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR);
2858 /* Disable MII auto-polling. */
2859 vge_miipoll_stop(sc);
2860 }
2861 CSR_SETBIT_1(sc, VGE_DIAGCTL,
2862 VGE_DIAGCTL_MACFORCE | VGE_DIAGCTL_FDXFORCE);
2863 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
2864
2865 /* Clear WOL status on pattern match. */
2866 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2867 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
2868
2869 val = CSR_READ_1(sc, VGE_PWRSTAT);
2870 val |= VGE_STICKHW_SWPTAG;
2871 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2872 /* Put hardware into sleep. */
2873 val = CSR_READ_1(sc, VGE_PWRSTAT);
2874 val |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1;
2875 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2876 /* Request PME if WOL is requested. */
2877 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2878 pci_enable_pme(sc->vge_dev);
2879 }
2880
2881 static void
vge_clrwol(struct vge_softc * sc)2882 vge_clrwol(struct vge_softc *sc)
2883 {
2884 uint8_t val;
2885
2886 val = CSR_READ_1(sc, VGE_PWRSTAT);
2887 val &= ~VGE_STICKHW_SWPTAG;
2888 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2889 /* Disable WOL and clear power state indicator. */
2890 val = CSR_READ_1(sc, VGE_PWRSTAT);
2891 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1);
2892 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2893
2894 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
2895 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2896
2897 /* Clear WOL on pattern match. */
2898 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2899 /* Disable WOL on magic/unicast packet. */
2900 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2901 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2902 VGE_WOLCFG_PMEOVR);
2903 /* Clear WOL status on pattern match. */
2904 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2905 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
2906 }
2907