1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
5 * Tiffany Lin <tiffany.lin@mediatek.com>
6 */
7
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <media/v4l2-event.h>
16 #include <media/v4l2-mem2mem.h>
17 #include <media/videobuf2-dma-contig.h>
18
19 #include "mtk_vcodec_enc.h"
20 #include "mtk_vcodec_enc_pm.h"
21 #include "../common/mtk_vcodec_intr.h"
22
23 static const struct mtk_video_fmt mtk_video_formats_output[] = {
24 {
25 .fourcc = V4L2_PIX_FMT_NV12M,
26 .type = MTK_FMT_FRAME,
27 .num_planes = 2,
28 },
29 {
30 .fourcc = V4L2_PIX_FMT_NV21M,
31 .type = MTK_FMT_FRAME,
32 .num_planes = 2,
33 },
34 {
35 .fourcc = V4L2_PIX_FMT_YUV420M,
36 .type = MTK_FMT_FRAME,
37 .num_planes = 3,
38 },
39 {
40 .fourcc = V4L2_PIX_FMT_YVU420M,
41 .type = MTK_FMT_FRAME,
42 .num_planes = 3,
43 },
44 };
45
46 static const struct mtk_video_fmt mtk_video_formats_capture_h264[] = {
47 {
48 .fourcc = V4L2_PIX_FMT_H264,
49 .type = MTK_FMT_ENC,
50 .num_planes = 1,
51 },
52 };
53
54 static const struct mtk_video_fmt mtk_video_formats_capture_vp8[] = {
55 {
56 .fourcc = V4L2_PIX_FMT_VP8,
57 .type = MTK_FMT_ENC,
58 .num_planes = 1,
59 },
60 };
61
clean_irq_status(unsigned int irq_status,void __iomem * addr)62 static void clean_irq_status(unsigned int irq_status, void __iomem *addr)
63 {
64 if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE)
65 writel(MTK_VENC_IRQ_STATUS_PAUSE, addr);
66
67 if (irq_status & MTK_VENC_IRQ_STATUS_SWITCH)
68 writel(MTK_VENC_IRQ_STATUS_SWITCH, addr);
69
70 if (irq_status & MTK_VENC_IRQ_STATUS_DRAM)
71 writel(MTK_VENC_IRQ_STATUS_DRAM, addr);
72
73 if (irq_status & MTK_VENC_IRQ_STATUS_SPS)
74 writel(MTK_VENC_IRQ_STATUS_SPS, addr);
75
76 if (irq_status & MTK_VENC_IRQ_STATUS_PPS)
77 writel(MTK_VENC_IRQ_STATUS_PPS, addr);
78
79 if (irq_status & MTK_VENC_IRQ_STATUS_FRM)
80 writel(MTK_VENC_IRQ_STATUS_FRM, addr);
81
82 }
mtk_vcodec_enc_irq_handler(int irq,void * priv)83 static irqreturn_t mtk_vcodec_enc_irq_handler(int irq, void *priv)
84 {
85 struct mtk_vcodec_enc_dev *dev = priv;
86 struct mtk_vcodec_enc_ctx *ctx;
87 unsigned long flags;
88 void __iomem *addr;
89 int core_id;
90
91 spin_lock_irqsave(&dev->irqlock, flags);
92 ctx = dev->curr_ctx;
93 spin_unlock_irqrestore(&dev->irqlock, flags);
94
95 core_id = dev->venc_pdata->core_id;
96 if (core_id < 0 || core_id >= NUM_MAX_VCODEC_REG_BASE) {
97 mtk_v4l2_venc_err(ctx, "Invalid core id: %d, ctx id: %d", core_id, ctx->id);
98 return IRQ_HANDLED;
99 }
100
101 mtk_v4l2_venc_dbg(1, ctx, "id: %d, core id: %d", ctx->id, core_id);
102
103 addr = dev->reg_base[core_id] + MTK_VENC_IRQ_ACK_OFFSET;
104
105 ctx->irq_status = readl(dev->reg_base[core_id] +
106 (MTK_VENC_IRQ_STATUS_OFFSET));
107
108 clean_irq_status(ctx->irq_status, addr);
109
110 wake_up_enc_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0);
111 return IRQ_HANDLED;
112 }
113
fops_vcodec_open(struct file * file)114 static int fops_vcodec_open(struct file *file)
115 {
116 struct mtk_vcodec_enc_dev *dev = video_drvdata(file);
117 struct mtk_vcodec_enc_ctx *ctx = NULL;
118 int ret = 0;
119 struct vb2_queue *src_vq;
120 unsigned long flags;
121
122 ctx = kzalloc_obj(*ctx);
123 if (!ctx)
124 return -ENOMEM;
125
126 mutex_lock(&dev->dev_mutex);
127 /*
128 * Use simple counter to uniquely identify this context. Only
129 * used for logging.
130 */
131 ctx->id = dev->id_counter++;
132 v4l2_fh_init(&ctx->fh, video_devdata(file));
133 v4l2_fh_add(&ctx->fh, file);
134 INIT_LIST_HEAD(&ctx->list);
135 ctx->dev = dev;
136 init_waitqueue_head(&ctx->queue[0]);
137 mutex_init(&ctx->q_mutex);
138
139 ctx->type = MTK_INST_ENCODER;
140 ret = mtk_vcodec_enc_ctrls_setup(ctx);
141 if (ret) {
142 mtk_v4l2_venc_err(ctx, "Failed to setup controls() (%d)", ret);
143 goto err_ctrls_setup;
144 }
145 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev_enc, ctx,
146 &mtk_vcodec_enc_queue_init);
147 if (IS_ERR((__force void *)ctx->m2m_ctx)) {
148 ret = PTR_ERR((__force void *)ctx->m2m_ctx);
149 mtk_v4l2_venc_err(ctx, "Failed to v4l2_m2m_ctx_init() (%d)", ret);
150 goto err_m2m_ctx_init;
151 }
152 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
153 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
154 ctx->empty_flush_buf.vb.vb2_buf.vb2_queue = src_vq;
155 mtk_vcodec_enc_set_default_params(ctx);
156
157 if (v4l2_fh_is_singular(&ctx->fh)) {
158 /*
159 * load fireware to checks if it was loaded already and
160 * does nothing in that case
161 */
162 ret = mtk_vcodec_fw_load_firmware(dev->fw_handler);
163 if (ret < 0) {
164 /*
165 * Return 0 if downloading firmware successfully,
166 * otherwise it is failed
167 */
168 mtk_v4l2_venc_err(ctx, "vpu_load_firmware failed!");
169 goto err_load_fw;
170 }
171
172 dev->enc_capability =
173 mtk_vcodec_fw_get_venc_capa(dev->fw_handler);
174 mtk_v4l2_venc_dbg(0, ctx, "encoder capability %x", dev->enc_capability);
175 }
176
177 mtk_v4l2_venc_dbg(2, ctx, "Create instance [%d]@%p m2m_ctx=%p ",
178 ctx->id, ctx, ctx->m2m_ctx);
179
180 spin_lock_irqsave(&dev->dev_ctx_lock, flags);
181 list_add(&ctx->list, &dev->ctx_list);
182 spin_unlock_irqrestore(&dev->dev_ctx_lock, flags);
183
184 mutex_unlock(&dev->dev_mutex);
185 mtk_v4l2_venc_dbg(0, ctx, "%s encoder [%d]", dev_name(&dev->plat_dev->dev),
186 ctx->id);
187 return ret;
188
189 /* Deinit when failure occurred */
190 err_load_fw:
191 v4l2_m2m_ctx_release(ctx->m2m_ctx);
192 err_m2m_ctx_init:
193 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
194 err_ctrls_setup:
195 v4l2_fh_del(&ctx->fh, file);
196 v4l2_fh_exit(&ctx->fh);
197 kfree(ctx);
198 mutex_unlock(&dev->dev_mutex);
199
200 return ret;
201 }
202
fops_vcodec_release(struct file * file)203 static int fops_vcodec_release(struct file *file)
204 {
205 struct mtk_vcodec_enc_dev *dev = video_drvdata(file);
206 struct mtk_vcodec_enc_ctx *ctx = file_to_enc_ctx(file);
207 unsigned long flags;
208
209 mtk_v4l2_venc_dbg(1, ctx, "[%d] encoder", ctx->id);
210 mutex_lock(&dev->dev_mutex);
211
212 v4l2_m2m_ctx_release(ctx->m2m_ctx);
213 mtk_vcodec_enc_release(ctx);
214 v4l2_fh_del(&ctx->fh, file);
215 v4l2_fh_exit(&ctx->fh);
216 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
217
218 spin_lock_irqsave(&dev->dev_ctx_lock, flags);
219 list_del_init(&ctx->list);
220 spin_unlock_irqrestore(&dev->dev_ctx_lock, flags);
221 kfree(ctx);
222 mutex_unlock(&dev->dev_mutex);
223 return 0;
224 }
225
226 static const struct v4l2_file_operations mtk_vcodec_fops = {
227 .owner = THIS_MODULE,
228 .open = fops_vcodec_open,
229 .release = fops_vcodec_release,
230 .poll = v4l2_m2m_fop_poll,
231 .unlocked_ioctl = video_ioctl2,
232 .mmap = v4l2_m2m_fop_mmap,
233 };
234
mtk_vcodec_probe(struct platform_device * pdev)235 static int mtk_vcodec_probe(struct platform_device *pdev)
236 {
237 struct mtk_vcodec_enc_dev *dev;
238 struct video_device *vfd_enc;
239 phandle rproc_phandle;
240 enum mtk_vcodec_fw_type fw_type;
241 int ret;
242
243 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
244 if (!dev)
245 return -ENOMEM;
246
247 INIT_LIST_HEAD(&dev->ctx_list);
248 dev->plat_dev = pdev;
249
250 if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu",
251 &rproc_phandle)) {
252 fw_type = VPU;
253 } else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
254 &rproc_phandle)) {
255 fw_type = SCP;
256 } else {
257 dev_err(&pdev->dev, "[MTK VCODEC] Could not get venc IPI device");
258 return -ENODEV;
259 }
260 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
261
262 dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, ENCODER);
263 if (IS_ERR(dev->fw_handler))
264 return PTR_ERR(dev->fw_handler);
265
266 dev->venc_pdata = of_device_get_match_data(&pdev->dev);
267 ret = mtk_vcodec_init_enc_clk(dev);
268 if (ret < 0) {
269 dev_err(&pdev->dev, "[MTK VCODEC] Failed to get mtk vcodec clock source!");
270 goto err_enc_pm;
271 }
272
273 pm_runtime_enable(&pdev->dev);
274
275 dev->reg_base[dev->venc_pdata->core_id] =
276 devm_platform_ioremap_resource(pdev, 0);
277 if (IS_ERR(dev->reg_base[dev->venc_pdata->core_id])) {
278 ret = PTR_ERR(dev->reg_base[dev->venc_pdata->core_id]);
279 goto err_res;
280 }
281
282 dev->enc_irq = platform_get_irq(pdev, 0);
283 if (dev->enc_irq < 0) {
284 ret = dev->enc_irq;
285 goto err_res;
286 }
287
288 irq_set_status_flags(dev->enc_irq, IRQ_NOAUTOEN);
289 ret = devm_request_irq(&pdev->dev, dev->enc_irq,
290 mtk_vcodec_enc_irq_handler,
291 0, pdev->name, dev);
292 if (ret) {
293 dev_err(&pdev->dev,
294 "[MTK VCODEC] Failed to install dev->enc_irq %d (%d) core_id (%d)",
295 dev->enc_irq, ret, dev->venc_pdata->core_id);
296 ret = -EINVAL;
297 goto err_res;
298 }
299
300 mutex_init(&dev->enc_mutex);
301 mutex_init(&dev->dev_mutex);
302 spin_lock_init(&dev->dev_ctx_lock);
303 spin_lock_init(&dev->irqlock);
304
305 snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s",
306 "[MTK_V4L2_VENC]");
307
308 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
309 if (ret) {
310 dev_err(&pdev->dev, "[MTK VCODEC] v4l2_device_register err=%d", ret);
311 goto err_res;
312 }
313
314 /* allocate video device for encoder and register it */
315 vfd_enc = video_device_alloc();
316 if (!vfd_enc) {
317 dev_err(&pdev->dev, "[MTK VCODEC] Failed to allocate video device");
318 ret = -ENOMEM;
319 goto err_enc_alloc;
320 }
321 vfd_enc->fops = &mtk_vcodec_fops;
322 vfd_enc->ioctl_ops = &mtk_venc_ioctl_ops;
323 vfd_enc->release = video_device_release;
324 vfd_enc->lock = &dev->dev_mutex;
325 vfd_enc->v4l2_dev = &dev->v4l2_dev;
326 vfd_enc->vfl_dir = VFL_DIR_M2M;
327 vfd_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE |
328 V4L2_CAP_STREAMING;
329
330 snprintf(vfd_enc->name, sizeof(vfd_enc->name), "%s",
331 MTK_VCODEC_ENC_NAME);
332 video_set_drvdata(vfd_enc, dev);
333 dev->vfd_enc = vfd_enc;
334 platform_set_drvdata(pdev, dev);
335
336 dev->m2m_dev_enc = v4l2_m2m_init(&mtk_venc_m2m_ops);
337 if (IS_ERR((__force void *)dev->m2m_dev_enc)) {
338 dev_err(&pdev->dev, "[MTK VCODEC] Failed to init mem2mem enc device");
339 ret = PTR_ERR((__force void *)dev->m2m_dev_enc);
340 goto err_enc_mem_init;
341 }
342
343 dev->encode_workqueue =
344 alloc_ordered_workqueue(MTK_VCODEC_ENC_NAME,
345 WQ_MEM_RECLAIM |
346 WQ_FREEZABLE);
347 if (!dev->encode_workqueue) {
348 dev_err(&pdev->dev, "[MTK VCODEC] Failed to create encode workqueue");
349 ret = -EINVAL;
350 goto err_event_workq;
351 }
352
353 ret = video_register_device(vfd_enc, VFL_TYPE_VIDEO, -1);
354 if (ret) {
355 dev_err(&pdev->dev, "[MTK VCODEC] Failed to register video device");
356 goto err_enc_reg;
357 }
358
359 mtk_vcodec_dbgfs_init(dev, true);
360 dev_dbg(&pdev->dev, "[MTK VCODEC] encoder %d registered as /dev/video%d",
361 dev->venc_pdata->core_id, vfd_enc->num);
362
363 return 0;
364
365 err_enc_reg:
366 destroy_workqueue(dev->encode_workqueue);
367 err_event_workq:
368 v4l2_m2m_release(dev->m2m_dev_enc);
369 err_enc_mem_init:
370 video_unregister_device(vfd_enc);
371 err_enc_alloc:
372 v4l2_device_unregister(&dev->v4l2_dev);
373 err_res:
374 pm_runtime_disable(dev->pm.dev);
375 err_enc_pm:
376 mtk_vcodec_fw_release(dev->fw_handler);
377 return ret;
378 }
379
380 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
381 .capture_formats = mtk_video_formats_capture_h264,
382 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
383 .output_formats = mtk_video_formats_output,
384 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
385 .min_bitrate = 64,
386 .max_bitrate = 60000000,
387 .core_id = VENC_SYS,
388 };
389
390 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
391 .capture_formats = mtk_video_formats_capture_vp8,
392 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_vp8),
393 .output_formats = mtk_video_formats_output,
394 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
395 .min_bitrate = 64,
396 .max_bitrate = 9000000,
397 .core_id = VENC_LT_SYS,
398 };
399
400 static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
401 .uses_ext = true,
402 .capture_formats = mtk_video_formats_capture_h264,
403 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
404 .output_formats = mtk_video_formats_output,
405 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
406 .min_bitrate = 64,
407 .max_bitrate = 40000000,
408 .core_id = VENC_SYS,
409 };
410
411 static const struct mtk_vcodec_enc_pdata mt8188_pdata = {
412 .uses_ext = true,
413 .capture_formats = mtk_video_formats_capture_h264,
414 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
415 .output_formats = mtk_video_formats_output,
416 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
417 .min_bitrate = 64,
418 .max_bitrate = 50000000,
419 .core_id = VENC_SYS,
420 .uses_34bit = true,
421 };
422
423 static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
424 .uses_ext = true,
425 .capture_formats = mtk_video_formats_capture_h264,
426 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
427 .output_formats = mtk_video_formats_output,
428 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
429 .min_bitrate = 64,
430 .max_bitrate = 100000000,
431 .core_id = VENC_SYS,
432 };
433
434 static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
435 .uses_ext = true,
436 .capture_formats = mtk_video_formats_capture_h264,
437 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
438 .output_formats = mtk_video_formats_output,
439 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
440 .min_bitrate = 64,
441 .max_bitrate = 100000000,
442 .core_id = VENC_SYS,
443 };
444
445 static const struct of_device_id mtk_vcodec_enc_match[] = {
446 {.compatible = "mediatek,mt8173-vcodec-enc",
447 .data = &mt8173_avc_pdata},
448 {.compatible = "mediatek,mt8173-vcodec-enc-vp8",
449 .data = &mt8173_vp8_pdata},
450 {.compatible = "mediatek,mt8183-vcodec-enc", .data = &mt8183_pdata},
451 {.compatible = "mediatek,mt8188-vcodec-enc", .data = &mt8188_pdata},
452 {.compatible = "mediatek,mt8192-vcodec-enc", .data = &mt8192_pdata},
453 {.compatible = "mediatek,mt8195-vcodec-enc", .data = &mt8195_pdata},
454 {},
455 };
456 MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match);
457
mtk_vcodec_enc_remove(struct platform_device * pdev)458 static void mtk_vcodec_enc_remove(struct platform_device *pdev)
459 {
460 struct mtk_vcodec_enc_dev *dev = platform_get_drvdata(pdev);
461
462 destroy_workqueue(dev->encode_workqueue);
463 if (dev->m2m_dev_enc)
464 v4l2_m2m_release(dev->m2m_dev_enc);
465
466 if (dev->vfd_enc)
467 video_unregister_device(dev->vfd_enc);
468
469 mtk_vcodec_dbgfs_deinit(&dev->dbgfs);
470 v4l2_device_unregister(&dev->v4l2_dev);
471 pm_runtime_disable(dev->pm.dev);
472 mtk_vcodec_fw_release(dev->fw_handler);
473 }
474
475 static struct platform_driver mtk_vcodec_enc_driver = {
476 .probe = mtk_vcodec_probe,
477 .remove = mtk_vcodec_enc_remove,
478 .driver = {
479 .name = MTK_VCODEC_ENC_NAME,
480 .of_match_table = mtk_vcodec_enc_match,
481 },
482 };
483
484 module_platform_driver(mtk_vcodec_enc_driver);
485
486
487 MODULE_LICENSE("GPL v2");
488 MODULE_DESCRIPTION("Mediatek video codec V4L2 encoder driver");
489