1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale vf610 GPIO support through PORT and GPIO
4 *
5 * Copyright (c) 2014 Toradex AG.
6 *
7 * Author: Stefan Agner <stefan@agner.ch>.
8 */
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21
22 #define VF610_GPIO_PER_PORT 32
23
24 struct fsl_gpio_soc_data {
25 /* SoCs has a Port Data Direction Register (PDDR) */
26 bool have_paddr;
27 bool have_dual_base;
28 };
29
30 struct vf610_gpio_port {
31 struct gpio_chip gc;
32 void __iomem *base;
33 void __iomem *gpio_base;
34 const struct fsl_gpio_soc_data *sdata;
35 u8 irqc[VF610_GPIO_PER_PORT];
36 struct clk *clk_port;
37 struct clk *clk_gpio;
38 int irq;
39 };
40
41 #define GPIO_PDOR 0x00
42 #define GPIO_PSOR 0x04
43 #define GPIO_PCOR 0x08
44 #define GPIO_PTOR 0x0c
45 #define GPIO_PDIR 0x10
46 #define GPIO_PDDR 0x14
47
48 #define PORT_PCR(n) ((n) * 0x4)
49 #define PORT_PCR_IRQC_OFFSET 16
50
51 #define PORT_ISFR 0xa0
52 #define PORT_DFER 0xc0
53 #define PORT_DFCR 0xc4
54 #define PORT_DFWR 0xc8
55
56 #define PORT_INT_OFF 0x0
57 #define PORT_INT_LOGIC_ZERO 0x8
58 #define PORT_INT_RISING_EDGE 0x9
59 #define PORT_INT_FALLING_EDGE 0xa
60 #define PORT_INT_EITHER_EDGE 0xb
61 #define PORT_INT_LOGIC_ONE 0xc
62
63 #define IMX8ULP_GPIO_BASE_OFF 0x40
64 #define IMX8ULP_BASE_OFF 0x80
65
66 static const struct fsl_gpio_soc_data vf610_data = {
67 .have_dual_base = true,
68 };
69
70 static const struct fsl_gpio_soc_data imx_data = {
71 .have_paddr = true,
72 .have_dual_base = true,
73 };
74
75 static const struct fsl_gpio_soc_data imx8ulp_data = {
76 .have_paddr = true,
77 };
78
79 static const struct of_device_id vf610_gpio_dt_ids[] = {
80 { .compatible = "fsl,vf610-gpio", .data = &vf610_data },
81 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
82 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
83 { /* sentinel */ }
84 };
85
vf610_gpio_writel(u32 val,void __iomem * reg)86 static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
87 {
88 writel_relaxed(val, reg);
89 }
90
vf610_gpio_readl(void __iomem * reg)91 static inline u32 vf610_gpio_readl(void __iomem *reg)
92 {
93 return readl_relaxed(reg);
94 }
95
vf610_gpio_get(struct gpio_chip * gc,unsigned int gpio)96 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
97 {
98 struct vf610_gpio_port *port = gpiochip_get_data(gc);
99 u32 mask = BIT(gpio);
100 unsigned long offset = GPIO_PDIR;
101
102 if (port->sdata->have_paddr) {
103 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
104 if (mask)
105 offset = GPIO_PDOR;
106 }
107
108 return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
109 }
110
vf610_gpio_set(struct gpio_chip * gc,unsigned int gpio,int val)111 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
112 {
113 struct vf610_gpio_port *port = gpiochip_get_data(gc);
114 u32 mask = BIT(gpio);
115 unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
116
117 vf610_gpio_writel(mask, port->gpio_base + offset);
118 }
119
vf610_gpio_direction_input(struct gpio_chip * chip,unsigned int gpio)120 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
121 {
122 struct vf610_gpio_port *port = gpiochip_get_data(chip);
123 u32 mask = BIT(gpio);
124 u32 val;
125
126 if (port->sdata->have_paddr) {
127 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
128 val &= ~mask;
129 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
130 }
131
132 return pinctrl_gpio_direction_input(chip, gpio);
133 }
134
vf610_gpio_direction_output(struct gpio_chip * chip,unsigned int gpio,int value)135 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
136 int value)
137 {
138 struct vf610_gpio_port *port = gpiochip_get_data(chip);
139 u32 mask = BIT(gpio);
140 u32 val;
141
142 vf610_gpio_set(chip, gpio, value);
143
144 if (port->sdata->have_paddr) {
145 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
146 val |= mask;
147 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
148 }
149
150 return pinctrl_gpio_direction_output(chip, gpio);
151 }
152
vf610_gpio_get_direction(struct gpio_chip * gc,unsigned int gpio)153 static int vf610_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
154 {
155 struct vf610_gpio_port *port = gpiochip_get_data(gc);
156 u32 mask = BIT(gpio);
157
158 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
159
160 if (mask)
161 return GPIO_LINE_DIRECTION_OUT;
162
163 return GPIO_LINE_DIRECTION_IN;
164 }
165
vf610_gpio_irq_handler(struct irq_desc * desc)166 static void vf610_gpio_irq_handler(struct irq_desc *desc)
167 {
168 struct vf610_gpio_port *port =
169 gpiochip_get_data(irq_desc_get_handler_data(desc));
170 struct irq_chip *chip = irq_desc_get_chip(desc);
171 int pin;
172 unsigned long irq_isfr;
173
174 chained_irq_enter(chip, desc);
175
176 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
177
178 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
179 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
180
181 generic_handle_domain_irq(port->gc.irq.domain, pin);
182 }
183
184 chained_irq_exit(chip, desc);
185 }
186
vf610_gpio_irq_ack(struct irq_data * d)187 static void vf610_gpio_irq_ack(struct irq_data *d)
188 {
189 struct vf610_gpio_port *port =
190 gpiochip_get_data(irq_data_get_irq_chip_data(d));
191 int gpio = d->hwirq;
192
193 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
194 }
195
vf610_gpio_irq_set_type(struct irq_data * d,u32 type)196 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
197 {
198 struct vf610_gpio_port *port =
199 gpiochip_get_data(irq_data_get_irq_chip_data(d));
200 u8 irqc;
201
202 switch (type) {
203 case IRQ_TYPE_EDGE_RISING:
204 irqc = PORT_INT_RISING_EDGE;
205 break;
206 case IRQ_TYPE_EDGE_FALLING:
207 irqc = PORT_INT_FALLING_EDGE;
208 break;
209 case IRQ_TYPE_EDGE_BOTH:
210 irqc = PORT_INT_EITHER_EDGE;
211 break;
212 case IRQ_TYPE_LEVEL_LOW:
213 irqc = PORT_INT_LOGIC_ZERO;
214 break;
215 case IRQ_TYPE_LEVEL_HIGH:
216 irqc = PORT_INT_LOGIC_ONE;
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 port->irqc[d->hwirq] = irqc;
223
224 if (type & IRQ_TYPE_LEVEL_MASK)
225 irq_set_handler_locked(d, handle_level_irq);
226 else
227 irq_set_handler_locked(d, handle_edge_irq);
228
229 return 0;
230 }
231
vf610_gpio_irq_mask(struct irq_data * d)232 static void vf610_gpio_irq_mask(struct irq_data *d)
233 {
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct vf610_gpio_port *port = gpiochip_get_data(gc);
236 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
237 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
238
239 vf610_gpio_writel(0, pcr_base);
240 gpiochip_disable_irq(gc, gpio_num);
241 }
242
vf610_gpio_irq_unmask(struct irq_data * d)243 static void vf610_gpio_irq_unmask(struct irq_data *d)
244 {
245 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
246 struct vf610_gpio_port *port = gpiochip_get_data(gc);
247 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
248 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
249
250 gpiochip_enable_irq(gc, gpio_num);
251 vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
252 pcr_base);
253 }
254
vf610_gpio_irq_set_wake(struct irq_data * d,u32 enable)255 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
256 {
257 struct vf610_gpio_port *port =
258 gpiochip_get_data(irq_data_get_irq_chip_data(d));
259
260 if (enable)
261 enable_irq_wake(port->irq);
262 else
263 disable_irq_wake(port->irq);
264
265 return 0;
266 }
267
268 static const struct irq_chip vf610_irqchip = {
269 .name = "gpio-vf610",
270 .irq_ack = vf610_gpio_irq_ack,
271 .irq_mask = vf610_gpio_irq_mask,
272 .irq_unmask = vf610_gpio_irq_unmask,
273 .irq_set_type = vf610_gpio_irq_set_type,
274 .irq_set_wake = vf610_gpio_irq_set_wake,
275 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
276 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
277 GPIOCHIP_IRQ_RESOURCE_HELPERS,
278 };
279
vf610_gpio_disable_clk(void * data)280 static void vf610_gpio_disable_clk(void *data)
281 {
282 clk_disable_unprepare(data);
283 }
284
vf610_gpio_probe(struct platform_device * pdev)285 static int vf610_gpio_probe(struct platform_device *pdev)
286 {
287 struct device *dev = &pdev->dev;
288 struct vf610_gpio_port *port;
289 struct gpio_chip *gc;
290 struct gpio_irq_chip *girq;
291 int i;
292 int ret;
293 bool dual_base;
294
295 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
296 if (!port)
297 return -ENOMEM;
298
299 port->sdata = device_get_match_data(dev);
300
301 dual_base = port->sdata->have_dual_base;
302
303 /*
304 * Handle legacy compatible combinations which used two reg values
305 * for the i.MX8ULP and i.MX93.
306 */
307 if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
308 (device_is_compatible(dev, "fsl,imx93-gpio") ||
309 (device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
310 dual_base = true;
311
312 if (dual_base) {
313 port->base = devm_platform_ioremap_resource(pdev, 0);
314 if (IS_ERR(port->base))
315 return PTR_ERR(port->base);
316
317 port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
318 if (IS_ERR(port->gpio_base))
319 return PTR_ERR(port->gpio_base);
320 } else {
321 port->base = devm_platform_ioremap_resource(pdev, 0);
322 if (IS_ERR(port->base))
323 return PTR_ERR(port->base);
324
325 port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
326 port->base = port->base + IMX8ULP_BASE_OFF;
327 }
328
329 port->irq = platform_get_irq(pdev, 0);
330 if (port->irq < 0)
331 return port->irq;
332
333 port->clk_port = devm_clk_get(dev, "port");
334 ret = PTR_ERR_OR_ZERO(port->clk_port);
335 if (!ret) {
336 ret = clk_prepare_enable(port->clk_port);
337 if (ret)
338 return ret;
339 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
340 port->clk_port);
341 if (ret)
342 return ret;
343 } else if (ret == -EPROBE_DEFER) {
344 /*
345 * Percolate deferrals, for anything else,
346 * just live without the clocking.
347 */
348 return ret;
349 }
350
351 port->clk_gpio = devm_clk_get(dev, "gpio");
352 ret = PTR_ERR_OR_ZERO(port->clk_gpio);
353 if (!ret) {
354 ret = clk_prepare_enable(port->clk_gpio);
355 if (ret)
356 return ret;
357 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
358 port->clk_gpio);
359 if (ret)
360 return ret;
361 } else if (ret == -EPROBE_DEFER) {
362 return ret;
363 }
364
365 gc = &port->gc;
366 gc->parent = dev;
367 gc->label = dev_name(dev);
368 gc->ngpio = VF610_GPIO_PER_PORT;
369 gc->base = -1;
370
371 gc->request = gpiochip_generic_request;
372 gc->free = gpiochip_generic_free;
373 gc->direction_input = vf610_gpio_direction_input;
374 gc->get = vf610_gpio_get;
375 gc->direction_output = vf610_gpio_direction_output;
376 gc->set = vf610_gpio_set;
377 /*
378 * only IP has Port Data Direction Register(PDDR) can
379 * support get direction
380 */
381 if (port->sdata->have_paddr)
382 gc->get_direction = vf610_gpio_get_direction;
383
384 /* Mask all GPIO interrupts */
385 for (i = 0; i < gc->ngpio; i++)
386 vf610_gpio_writel(0, port->base + PORT_PCR(i));
387
388 /* Clear the interrupt status register for all GPIO's */
389 vf610_gpio_writel(~0, port->base + PORT_ISFR);
390
391 girq = &gc->irq;
392 gpio_irq_chip_set_chip(girq, &vf610_irqchip);
393 girq->parent_handler = vf610_gpio_irq_handler;
394 girq->num_parents = 1;
395 girq->parents = devm_kcalloc(&pdev->dev, 1,
396 sizeof(*girq->parents),
397 GFP_KERNEL);
398 if (!girq->parents)
399 return -ENOMEM;
400 girq->parents[0] = port->irq;
401 girq->default_type = IRQ_TYPE_NONE;
402 girq->handler = handle_edge_irq;
403
404 return devm_gpiochip_add_data(dev, gc, port);
405 }
406
407 static struct platform_driver vf610_gpio_driver = {
408 .driver = {
409 .name = "gpio-vf610",
410 .of_match_table = vf610_gpio_dt_ids,
411 },
412 .probe = vf610_gpio_probe,
413 };
414
415 builtin_platform_driver(vf610_gpio_driver);
416