xref: /linux/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __DSI_PHY_H__
7 #define __DSI_PHY_H__
8 
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/regulator/consumer.h>
12 
13 #include "dsi.h"
14 
15 struct msm_dsi_phy_ops {
16 	int (*pll_init)(struct msm_dsi_phy *phy);
17 	int (*enable)(struct msm_dsi_phy *phy,
18 			struct msm_dsi_phy_clk_request *clk_req);
19 	void (*disable)(struct msm_dsi_phy *phy);
20 	void (*save_pll_state)(struct msm_dsi_phy *phy);
21 	int (*restore_pll_state)(struct msm_dsi_phy *phy);
22 	bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
23 	int (*parse_dt_properties)(struct msm_dsi_phy *phy);
24 };
25 
26 struct msm_dsi_phy_cfg {
27 	const struct regulator_bulk_data *regulator_data;
28 	int num_regulators;
29 	struct msm_dsi_phy_ops ops;
30 
31 	unsigned long	min_pll_rate;
32 	unsigned long	max_pll_rate;
33 
34 	const resource_size_t io_start[DSI_MAX];
35 	const int num_dsi_phy;
36 	const int quirks;
37 	bool has_phy_regulator;
38 	bool has_phy_lane;
39 };
40 
41 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
42 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
43 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
44 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs;
45 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs;
46 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
47 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
48 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
49 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs;
50 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
51 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
52 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
53 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
54 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
55 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
56 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs;
57 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
58 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
59 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
60 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
61 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
62 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
63 
64 struct msm_dsi_dphy_timing {
65 	u32 clk_zero;
66 	u32 clk_trail;
67 	u32 clk_prepare;
68 	u32 hs_exit;
69 	u32 hs_zero;
70 	u32 hs_prepare;
71 	u32 hs_trail;
72 	u32 hs_rqst;
73 	u32 ta_go;
74 	u32 ta_sure;
75 	u32 ta_get;
76 
77 	struct msm_dsi_phy_shared_timings shared_timings;
78 
79 	/* For PHY v2 only */
80 	u32 hs_rqst_ckln;
81 	u32 hs_prep_dly;
82 	u32 hs_prep_dly_ckln;
83 	u8 hs_halfbyte_en;
84 	u8 hs_halfbyte_en_ckln;
85 };
86 
87 #define DSI_BYTE_PLL_CLK		0
88 #define DSI_PIXEL_PLL_CLK		1
89 #define NUM_PROVIDED_CLKS		2
90 
91 #define DSI_LANE_MAX			5
92 
93 struct msm_dsi_phy {
94 	struct platform_device *pdev;
95 	void __iomem *base;
96 	void __iomem *pll_base;
97 	void __iomem *reg_base;
98 	void __iomem *lane_base;
99 	phys_addr_t base_size;
100 	phys_addr_t pll_size;
101 	phys_addr_t reg_size;
102 	phys_addr_t lane_size;
103 	int id;
104 
105 	struct clk *ahb_clk;
106 	struct regulator_bulk_data *supplies;
107 
108 	struct msm_dsi_dphy_timing timing;
109 	const struct msm_dsi_phy_cfg *cfg;
110 	void *tuning_cfg;
111 
112 	enum msm_dsi_phy_usecase usecase;
113 	bool regulator_ldo_mode;
114 	bool cphy_mode;
115 
116 	struct clk_hw *vco_hw;
117 	bool pll_on;
118 
119 	struct clk_hw_onecell_data *provided_clocks;
120 
121 	bool state_saved;
122 };
123 
124 /*
125  * PHY internal functions
126  */
127 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
128 			     struct msm_dsi_phy_clk_request *clk_req);
129 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
130 				struct msm_dsi_phy_clk_request *clk_req);
131 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
132 				struct msm_dsi_phy_clk_request *clk_req);
133 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
134 				struct msm_dsi_phy_clk_request *clk_req);
135 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
136 				struct msm_dsi_phy_clk_request *clk_req);
137 
138 #endif /* __DSI_PHY_H__ */
139