1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0.h" 35 36 #include "vcn/vcn_4_0_0_offset.h" 37 #include "vcn/vcn_4_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = { 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 89 }; 90 91 static int amdgpu_ih_clientid_vcns[] = { 92 SOC15_IH_CLIENTID_VCN, 93 SOC15_IH_CLIENTID_VCN1 94 }; 95 96 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 97 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 105 106 /** 107 * vcn_v4_0_early_init - set function pointers and load microcode 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 * Load microcode from filesystem 113 */ 114 static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block) 115 { 116 struct amdgpu_device *adev = ip_block->adev; 117 int i, r; 118 119 if (amdgpu_sriov_vf(adev)) { 120 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 122 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 123 adev->vcn.harvest_config |= 1 << i; 124 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i); 125 } 126 } 127 } 128 129 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 130 /* re-use enc ring as unified ring */ 131 adev->vcn.inst[i].num_enc_rings = 1; 132 133 vcn_v4_0_set_unified_ring_funcs(adev); 134 vcn_v4_0_set_irq_funcs(adev); 135 vcn_v4_0_set_ras_funcs(adev); 136 137 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 138 adev->vcn.inst[i].set_pg_state = vcn_v4_0_set_pg_state; 139 140 r = amdgpu_vcn_early_init(adev, i); 141 if (r) 142 return r; 143 } 144 145 return 0; 146 } 147 148 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 149 { 150 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 151 152 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 153 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 154 fw_shared->sq.is_enabled = 1; 155 156 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 157 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 158 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 159 160 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == 161 IP_VERSION(4, 0, 2)) { 162 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 163 fw_shared->drm_key_wa.method = 164 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 165 } 166 167 if (amdgpu_vcnfw_log) 168 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 169 170 return 0; 171 } 172 173 /** 174 * vcn_v4_0_sw_init - sw init for VCN block 175 * 176 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 177 * 178 * Load firmware and sw initialization 179 */ 180 static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 181 { 182 struct amdgpu_ring *ring; 183 struct amdgpu_device *adev = ip_block->adev; 184 int i, r; 185 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); 186 uint32_t *ptr; 187 188 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 189 if (adev->vcn.harvest_config & (1 << i)) 190 continue; 191 192 r = amdgpu_vcn_sw_init(adev, i); 193 if (r) 194 return r; 195 196 amdgpu_vcn_setup_ucode(adev, i); 197 198 r = amdgpu_vcn_resume(adev, i); 199 if (r) 200 return r; 201 202 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */ 203 if (i == 0) 204 atomic_set(&adev->vcn.inst[i].sched_score, 1); 205 else 206 atomic_set(&adev->vcn.inst[i].sched_score, 0); 207 208 /* VCN UNIFIED TRAP */ 209 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 210 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 211 if (r) 212 return r; 213 214 /* VCN POISON TRAP */ 215 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 216 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq); 217 if (r) 218 return r; 219 220 ring = &adev->vcn.inst[i].ring_enc[0]; 221 ring->use_doorbell = true; 222 if (amdgpu_sriov_vf(adev)) 223 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * 224 (adev->vcn.inst[i].num_enc_rings + 1) + 1; 225 else 226 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 227 ring->vm_hub = AMDGPU_MMHUB0(0); 228 sprintf(ring->name, "vcn_unified_%d", i); 229 230 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 231 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 232 if (r) 233 return r; 234 235 vcn_v4_0_fw_shared_init(adev, i); 236 237 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 238 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 239 } 240 241 /* TODO: Add queue reset mask when FW fully supports it */ 242 adev->vcn.supported_reset = 243 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 244 245 if (amdgpu_sriov_vf(adev)) { 246 r = amdgpu_virt_alloc_mm_table(adev); 247 if (r) 248 return r; 249 } 250 251 252 r = amdgpu_vcn_ras_sw_init(adev); 253 if (r) 254 return r; 255 256 /* Allocate memory for VCN IP Dump buffer */ 257 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 258 if (!ptr) { 259 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 260 adev->vcn.ip_dump = NULL; 261 } else { 262 adev->vcn.ip_dump = ptr; 263 } 264 265 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 266 if (r) 267 return r; 268 269 return 0; 270 } 271 272 /** 273 * vcn_v4_0_sw_fini - sw fini for VCN block 274 * 275 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 276 * 277 * VCN suspend and free up sw allocation 278 */ 279 static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 280 { 281 struct amdgpu_device *adev = ip_block->adev; 282 int i, r, idx; 283 284 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 285 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 286 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 287 288 if (adev->vcn.harvest_config & (1 << i)) 289 continue; 290 291 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 292 fw_shared->present_flag_0 = 0; 293 fw_shared->sq.is_enabled = 0; 294 } 295 296 drm_dev_exit(idx); 297 } 298 299 if (amdgpu_sriov_vf(adev)) 300 amdgpu_virt_free_mm_table(adev); 301 302 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 303 r = amdgpu_vcn_suspend(adev, i); 304 if (r) 305 return r; 306 } 307 308 amdgpu_vcn_sysfs_reset_mask_fini(adev); 309 310 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 311 r = amdgpu_vcn_sw_fini(adev, i); 312 if (r) 313 return r; 314 } 315 316 kfree(adev->vcn.ip_dump); 317 318 return 0; 319 } 320 321 /** 322 * vcn_v4_0_hw_init - start and test VCN block 323 * 324 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 325 * 326 * Initialize the hardware, boot up the VCPU and do some testing 327 */ 328 static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block) 329 { 330 struct amdgpu_device *adev = ip_block->adev; 331 struct amdgpu_ring *ring; 332 int i, r; 333 334 if (amdgpu_sriov_vf(adev)) { 335 r = vcn_v4_0_start_sriov(adev); 336 if (r) 337 return r; 338 339 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 340 if (adev->vcn.harvest_config & (1 << i)) 341 continue; 342 343 ring = &adev->vcn.inst[i].ring_enc[0]; 344 ring->wptr = 0; 345 ring->wptr_old = 0; 346 vcn_v4_0_unified_ring_set_wptr(ring); 347 ring->sched.ready = true; 348 } 349 } else { 350 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 351 if (adev->vcn.harvest_config & (1 << i)) 352 continue; 353 354 ring = &adev->vcn.inst[i].ring_enc[0]; 355 356 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 357 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 358 359 r = amdgpu_ring_test_helper(ring); 360 if (r) 361 return r; 362 } 363 } 364 365 return 0; 366 } 367 368 /** 369 * vcn_v4_0_hw_fini - stop the hardware block 370 * 371 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 372 * 373 * Stop the VCN block, mark ring as not ready any more 374 */ 375 static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) 376 { 377 struct amdgpu_device *adev = ip_block->adev; 378 int i; 379 380 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 381 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 382 383 if (adev->vcn.harvest_config & (1 << i)) 384 continue; 385 386 cancel_delayed_work_sync(&vinst->idle_work); 387 388 if (!amdgpu_sriov_vf(adev)) { 389 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 390 (vinst->cur_state != AMD_PG_STATE_GATE && 391 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 392 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 393 } 394 } 395 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 396 amdgpu_irq_put(adev, &vinst->ras_poison_irq, 0); 397 } 398 399 return 0; 400 } 401 402 /** 403 * vcn_v4_0_suspend - suspend VCN block 404 * 405 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 406 * 407 * HW fini and suspend VCN block 408 */ 409 static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block) 410 { 411 struct amdgpu_device *adev = ip_block->adev; 412 int r, i; 413 414 r = vcn_v4_0_hw_fini(ip_block); 415 if (r) 416 return r; 417 418 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 419 r = amdgpu_vcn_suspend(ip_block->adev, i); 420 if (r) 421 return r; 422 } 423 424 return 0; 425 } 426 427 /** 428 * vcn_v4_0_resume - resume VCN block 429 * 430 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 431 * 432 * Resume firmware and hw init VCN block 433 */ 434 static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block) 435 { 436 struct amdgpu_device *adev = ip_block->adev; 437 int r, i; 438 439 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 440 r = amdgpu_vcn_resume(ip_block->adev, i); 441 if (r) 442 return r; 443 } 444 445 r = vcn_v4_0_hw_init(ip_block); 446 447 return r; 448 } 449 450 /** 451 * vcn_v4_0_mc_resume - memory controller programming 452 * 453 * @vinst: VCN instance 454 * 455 * Let the VCN memory controller know it's offsets 456 */ 457 static void vcn_v4_0_mc_resume(struct amdgpu_vcn_inst *vinst) 458 { 459 struct amdgpu_device *adev = vinst->adev; 460 int inst = vinst->inst; 461 uint32_t offset, size; 462 const struct common_firmware_header *hdr; 463 464 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 465 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 466 467 /* cache window 0: fw */ 468 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 469 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 470 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 471 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 472 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 473 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 474 offset = 0; 475 } else { 476 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 477 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 478 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 479 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 480 offset = size; 481 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 482 } 483 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 484 485 /* cache window 1: stack */ 486 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 487 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 488 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 489 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 490 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 491 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 492 493 /* cache window 2: context */ 494 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 495 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 496 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 497 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 498 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 499 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 500 501 /* non-cache window */ 502 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 503 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 504 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 505 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 506 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 507 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 508 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 509 } 510 511 /** 512 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 513 * 514 * @vinst: VCN instance 515 * @indirect: indirectly write sram 516 * 517 * Let the VCN memory controller know it's offsets with dpg mode 518 */ 519 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 520 bool indirect) 521 { 522 struct amdgpu_device *adev = vinst->adev; 523 int inst_idx = vinst->inst; 524 uint32_t offset, size; 525 const struct common_firmware_header *hdr; 526 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 527 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 528 529 /* cache window 0: fw */ 530 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 531 if (!indirect) { 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 534 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 537 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 540 } else { 541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 542 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 544 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 547 } 548 offset = 0; 549 } else { 550 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 551 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 552 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 553 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 554 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 555 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 556 offset = size; 557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 558 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 559 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 560 } 561 562 if (!indirect) 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 565 else 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 568 569 /* cache window 1: stack */ 570 if (!indirect) { 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 573 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 576 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 579 } else { 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 585 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 586 } 587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 588 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 589 590 /* cache window 2: context */ 591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 592 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 593 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 594 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 595 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 596 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 597 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 598 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 600 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 601 602 /* non-cache window */ 603 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 604 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 605 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 607 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 608 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 609 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 610 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 611 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 612 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 613 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 614 615 /* VCN global tiling registers */ 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 617 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 618 } 619 620 /** 621 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 622 * 623 * @vinst: VCN instance 624 * 625 * Disable static power gating for VCN block 626 */ 627 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 628 { 629 struct amdgpu_device *adev = vinst->adev; 630 int inst = vinst->inst; 631 uint32_t data = 0; 632 633 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 634 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 635 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 636 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 637 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 638 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 639 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 640 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 641 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 642 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 643 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 644 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 645 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 646 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 647 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 648 649 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 650 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 651 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 652 } else { 653 uint32_t value; 654 655 value = (inst) ? 0x2200800 : 0; 656 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 657 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 658 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 659 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 660 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 661 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 662 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 663 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 664 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 665 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 666 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 667 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 668 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 669 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 670 671 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 672 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 673 } 674 675 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 676 data &= ~0x103; 677 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 678 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 679 UVD_POWER_STATUS__UVD_PG_EN_MASK; 680 681 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 682 683 return; 684 } 685 686 /** 687 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 688 * 689 * @vinst: VCN instance 690 * 691 * Enable static power gating for VCN block 692 */ 693 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 694 { 695 struct amdgpu_device *adev = vinst->adev; 696 int inst = vinst->inst; 697 uint32_t data; 698 699 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 700 /* Before power off, this indicator has to be turned on */ 701 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 702 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 703 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 704 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 705 706 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 707 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 708 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 715 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 716 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 717 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 718 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 719 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 720 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 721 722 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 723 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 724 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 725 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 726 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 727 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 728 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 729 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 730 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 731 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 732 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 733 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 734 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 735 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 736 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 737 } 738 739 return; 740 } 741 742 /** 743 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 744 * 745 * @vinst: VCN instance 746 * 747 * Disable clock gating for VCN block 748 */ 749 static void vcn_v4_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 750 { 751 struct amdgpu_device *adev = vinst->adev; 752 int inst = vinst->inst; 753 uint32_t data; 754 755 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 756 return; 757 758 /* VCN disable CGC */ 759 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 760 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 761 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 762 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 763 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 764 765 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 766 data &= ~(UVD_CGC_GATE__SYS_MASK 767 | UVD_CGC_GATE__UDEC_MASK 768 | UVD_CGC_GATE__MPEG2_MASK 769 | UVD_CGC_GATE__REGS_MASK 770 | UVD_CGC_GATE__RBC_MASK 771 | UVD_CGC_GATE__LMI_MC_MASK 772 | UVD_CGC_GATE__LMI_UMC_MASK 773 | UVD_CGC_GATE__IDCT_MASK 774 | UVD_CGC_GATE__MPRD_MASK 775 | UVD_CGC_GATE__MPC_MASK 776 | UVD_CGC_GATE__LBSI_MASK 777 | UVD_CGC_GATE__LRBBM_MASK 778 | UVD_CGC_GATE__UDEC_RE_MASK 779 | UVD_CGC_GATE__UDEC_CM_MASK 780 | UVD_CGC_GATE__UDEC_IT_MASK 781 | UVD_CGC_GATE__UDEC_DB_MASK 782 | UVD_CGC_GATE__UDEC_MP_MASK 783 | UVD_CGC_GATE__WCB_MASK 784 | UVD_CGC_GATE__VCPU_MASK 785 | UVD_CGC_GATE__MMSCH_MASK); 786 787 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 788 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 789 790 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 791 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 792 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 793 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 794 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 795 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 796 | UVD_CGC_CTRL__SYS_MODE_MASK 797 | UVD_CGC_CTRL__UDEC_MODE_MASK 798 | UVD_CGC_CTRL__MPEG2_MODE_MASK 799 | UVD_CGC_CTRL__REGS_MODE_MASK 800 | UVD_CGC_CTRL__RBC_MODE_MASK 801 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 802 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 803 | UVD_CGC_CTRL__IDCT_MODE_MASK 804 | UVD_CGC_CTRL__MPRD_MODE_MASK 805 | UVD_CGC_CTRL__MPC_MODE_MASK 806 | UVD_CGC_CTRL__LBSI_MODE_MASK 807 | UVD_CGC_CTRL__LRBBM_MODE_MASK 808 | UVD_CGC_CTRL__WCB_MODE_MASK 809 | UVD_CGC_CTRL__VCPU_MODE_MASK 810 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 811 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 812 813 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 814 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 815 | UVD_SUVD_CGC_GATE__SIT_MASK 816 | UVD_SUVD_CGC_GATE__SMP_MASK 817 | UVD_SUVD_CGC_GATE__SCM_MASK 818 | UVD_SUVD_CGC_GATE__SDB_MASK 819 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 820 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 821 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 822 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 823 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 824 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 825 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 826 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 827 | UVD_SUVD_CGC_GATE__SCLR_MASK 828 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 829 | UVD_SUVD_CGC_GATE__ENT_MASK 830 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 831 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 832 | UVD_SUVD_CGC_GATE__SITE_MASK 833 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 834 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 835 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 836 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 837 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 838 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 839 840 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 841 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 842 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 843 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 844 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 845 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 846 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 847 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 848 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 849 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 850 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 851 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 852 } 853 854 /** 855 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 856 * 857 * @vinst: VCN instance 858 * @sram_sel: sram select 859 * @indirect: indirectly write sram 860 * 861 * Disable clock gating for VCN block with dpg mode 862 */ 863 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 864 uint8_t sram_sel, 865 uint8_t indirect) 866 { 867 struct amdgpu_device *adev = vinst->adev; 868 int inst_idx = vinst->inst; 869 uint32_t reg_data = 0; 870 871 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 872 return; 873 874 /* enable sw clock gating control */ 875 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 876 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 877 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 878 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 879 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 880 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 881 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 882 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 883 UVD_CGC_CTRL__SYS_MODE_MASK | 884 UVD_CGC_CTRL__UDEC_MODE_MASK | 885 UVD_CGC_CTRL__MPEG2_MODE_MASK | 886 UVD_CGC_CTRL__REGS_MODE_MASK | 887 UVD_CGC_CTRL__RBC_MODE_MASK | 888 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 889 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 890 UVD_CGC_CTRL__IDCT_MODE_MASK | 891 UVD_CGC_CTRL__MPRD_MODE_MASK | 892 UVD_CGC_CTRL__MPC_MODE_MASK | 893 UVD_CGC_CTRL__LBSI_MODE_MASK | 894 UVD_CGC_CTRL__LRBBM_MODE_MASK | 895 UVD_CGC_CTRL__WCB_MODE_MASK | 896 UVD_CGC_CTRL__VCPU_MODE_MASK); 897 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 898 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 899 900 /* turn off clock gating */ 901 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 902 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 903 904 /* turn on SUVD clock gating */ 905 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 906 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 907 908 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 909 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 910 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 911 } 912 913 /** 914 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 915 * 916 * @vinst: VCN instance 917 * 918 * Enable clock gating for VCN block 919 */ 920 static void vcn_v4_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 921 { 922 struct amdgpu_device *adev = vinst->adev; 923 int inst = vinst->inst; 924 uint32_t data; 925 926 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 927 return; 928 929 /* enable VCN CGC */ 930 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 931 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 932 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 933 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 934 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 935 936 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 937 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 938 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 939 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 940 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 941 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 942 | UVD_CGC_CTRL__SYS_MODE_MASK 943 | UVD_CGC_CTRL__UDEC_MODE_MASK 944 | UVD_CGC_CTRL__MPEG2_MODE_MASK 945 | UVD_CGC_CTRL__REGS_MODE_MASK 946 | UVD_CGC_CTRL__RBC_MODE_MASK 947 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 948 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 949 | UVD_CGC_CTRL__IDCT_MODE_MASK 950 | UVD_CGC_CTRL__MPRD_MODE_MASK 951 | UVD_CGC_CTRL__MPC_MODE_MASK 952 | UVD_CGC_CTRL__LBSI_MODE_MASK 953 | UVD_CGC_CTRL__LRBBM_MODE_MASK 954 | UVD_CGC_CTRL__WCB_MODE_MASK 955 | UVD_CGC_CTRL__VCPU_MODE_MASK 956 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 957 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 958 959 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 960 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 961 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 962 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 963 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 964 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 965 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 966 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 967 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 968 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 969 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 970 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 971 } 972 973 static void vcn_v4_0_enable_ras(struct amdgpu_vcn_inst *vinst, 974 bool indirect) 975 { 976 struct amdgpu_device *adev = vinst->adev; 977 int inst_idx = vinst->inst; 978 uint32_t tmp; 979 980 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 981 return; 982 983 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 984 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 985 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 986 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 987 WREG32_SOC15_DPG_MODE(inst_idx, 988 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 989 tmp, 0, indirect); 990 991 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 992 WREG32_SOC15_DPG_MODE(inst_idx, 993 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 994 tmp, 0, indirect); 995 } 996 997 /** 998 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 999 * 1000 * @vinst: VCN instance 1001 * @indirect: indirectly write sram 1002 * 1003 * Start VCN block with dpg mode 1004 */ 1005 static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 1006 { 1007 struct amdgpu_device *adev = vinst->adev; 1008 int inst_idx = vinst->inst; 1009 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1010 struct amdgpu_ring *ring; 1011 uint32_t tmp; 1012 1013 /* disable register anti-hang mechanism */ 1014 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 1015 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1016 /* enable dynamic power gating mode */ 1017 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 1018 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1019 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 1020 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 1021 1022 if (indirect) 1023 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 1024 1025 /* enable clock gating */ 1026 vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect); 1027 1028 /* enable VCPU clock */ 1029 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1030 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 1031 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1032 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 1033 1034 /* disable master interupt */ 1035 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1036 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 1037 1038 /* setup regUVD_LMI_CTRL */ 1039 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1040 UVD_LMI_CTRL__REQ_MODE_MASK | 1041 UVD_LMI_CTRL__CRC_RESET_MASK | 1042 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1043 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1044 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1045 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1046 0x00100000L); 1047 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1048 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 1049 1050 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1051 VCN, inst_idx, regUVD_MPC_CNTL), 1052 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1053 1054 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1055 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 1056 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1057 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1058 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1059 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1060 1061 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1062 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 1063 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1064 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1065 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1066 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1067 1068 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1069 VCN, inst_idx, regUVD_MPC_SET_MUX), 1070 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1071 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1072 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1073 1074 vcn_v4_0_mc_resume_dpg_mode(vinst, indirect); 1075 1076 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1077 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1078 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1079 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 1080 1081 /* enable LMI MC and UMC channels */ 1082 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 1083 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1084 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 1085 1086 vcn_v4_0_enable_ras(vinst, indirect); 1087 1088 /* enable master interrupt */ 1089 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1090 VCN, inst_idx, regUVD_MASTINT_EN), 1091 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1092 1093 1094 if (indirect) 1095 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1096 1097 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1098 1099 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1100 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1101 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1102 1103 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1104 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1105 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1106 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1107 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1108 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1109 1110 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1111 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1112 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1113 1114 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1115 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1116 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1117 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1118 1119 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1120 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1121 VCN_RB1_DB_CTRL__EN_MASK); 1122 1123 return 0; 1124 } 1125 1126 1127 /** 1128 * vcn_v4_0_start - VCN start 1129 * 1130 * @vinst: VCN instance 1131 * 1132 * Start VCN block 1133 */ 1134 static int vcn_v4_0_start(struct amdgpu_vcn_inst *vinst) 1135 { 1136 struct amdgpu_device *adev = vinst->adev; 1137 int i = vinst->inst; 1138 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1139 struct amdgpu_ring *ring; 1140 uint32_t tmp; 1141 int j, k, r; 1142 1143 if (adev->vcn.harvest_config & (1 << i)) 1144 return 0; 1145 1146 if (adev->pm.dpm_enabled) 1147 amdgpu_dpm_enable_vcn(adev, true, i); 1148 1149 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1150 1151 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1152 return vcn_v4_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1153 1154 /* disable VCN power gating */ 1155 vcn_v4_0_disable_static_power_gating(vinst); 1156 1157 /* set VCN status busy */ 1158 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1159 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1160 1161 /*SW clock gating */ 1162 vcn_v4_0_disable_clock_gating(vinst); 1163 1164 /* enable VCPU clock */ 1165 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1166 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1167 1168 /* disable master interrupt */ 1169 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1170 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1171 1172 /* enable LMI MC and UMC channels */ 1173 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1174 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1175 1176 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1177 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1178 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1179 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1180 1181 /* setup regUVD_LMI_CTRL */ 1182 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1183 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1184 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1185 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1186 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1187 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1188 1189 /* setup regUVD_MPC_CNTL */ 1190 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1191 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1192 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1193 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1194 1195 /* setup UVD_MPC_SET_MUXA0 */ 1196 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1197 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1198 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1199 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1200 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1201 1202 /* setup UVD_MPC_SET_MUXB0 */ 1203 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1204 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1205 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1206 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1207 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1208 1209 /* setup UVD_MPC_SET_MUX */ 1210 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1211 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1212 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1213 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1214 1215 vcn_v4_0_mc_resume(vinst); 1216 1217 /* VCN global tiling registers */ 1218 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1219 adev->gfx.config.gb_addr_config); 1220 1221 /* unblock VCPU register access */ 1222 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1223 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1224 1225 /* release VCPU reset to boot */ 1226 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1227 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1228 1229 for (j = 0; j < 10; ++j) { 1230 uint32_t status; 1231 1232 for (k = 0; k < 100; ++k) { 1233 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1234 if (status & 2) 1235 break; 1236 mdelay(10); 1237 if (amdgpu_emu_mode == 1) 1238 msleep(1); 1239 } 1240 1241 if (amdgpu_emu_mode == 1) { 1242 r = -1; 1243 if (status & 2) { 1244 r = 0; 1245 break; 1246 } 1247 } else { 1248 r = 0; 1249 if (status & 2) 1250 break; 1251 1252 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1253 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1254 UVD_VCPU_CNTL__BLK_RST_MASK, 1255 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1256 mdelay(10); 1257 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1258 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1259 1260 mdelay(10); 1261 r = -1; 1262 } 1263 } 1264 1265 if (r) { 1266 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1267 return r; 1268 } 1269 1270 /* enable master interrupt */ 1271 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1272 UVD_MASTINT_EN__VCPU_EN_MASK, 1273 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1274 1275 /* clear the busy bit of VCN_STATUS */ 1276 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1277 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1278 1279 ring = &adev->vcn.inst[i].ring_enc[0]; 1280 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1281 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1282 VCN_RB1_DB_CTRL__EN_MASK); 1283 1284 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1285 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1286 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1287 1288 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1289 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1290 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1291 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1292 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1293 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1294 1295 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1296 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1297 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1298 1299 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1300 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1301 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1302 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1303 1304 return 0; 1305 } 1306 1307 static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc) 1308 { 1309 struct amdgpu_vcn_rb_metadata *rb_metadata = NULL; 1310 uint8_t *rb_ptr = (uint8_t *)ring_enc->ring; 1311 1312 rb_ptr += ring_enc->ring_size; 1313 rb_metadata = (struct amdgpu_vcn_rb_metadata *)rb_ptr; 1314 1315 memset(rb_metadata, 0, sizeof(struct amdgpu_vcn_rb_metadata)); 1316 rb_metadata->size = sizeof(struct amdgpu_vcn_rb_metadata); 1317 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1318 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG); 1319 rb_metadata->version = 1; 1320 rb_metadata->ring_id = vcn_inst & 0xFF; 1321 1322 return 0; 1323 } 1324 1325 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1326 { 1327 int i; 1328 struct amdgpu_ring *ring_enc; 1329 uint64_t cache_addr; 1330 uint64_t rb_enc_addr; 1331 uint64_t ctx_addr; 1332 uint32_t param, resp, expected; 1333 uint32_t offset, cache_size; 1334 uint32_t tmp, timeout; 1335 1336 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1337 uint32_t *table_loc; 1338 uint32_t table_size; 1339 uint32_t size, size_dw; 1340 uint32_t init_status; 1341 uint32_t enabled_vcn; 1342 1343 struct mmsch_v4_0_cmd_direct_write 1344 direct_wt = { {0} }; 1345 struct mmsch_v4_0_cmd_direct_read_modify_write 1346 direct_rd_mod_wt = { {0} }; 1347 struct mmsch_v4_0_cmd_end end = { {0} }; 1348 struct mmsch_v4_0_init_header header; 1349 1350 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1351 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1352 1353 direct_wt.cmd_header.command_type = 1354 MMSCH_COMMAND__DIRECT_REG_WRITE; 1355 direct_rd_mod_wt.cmd_header.command_type = 1356 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1357 end.cmd_header.command_type = 1358 MMSCH_COMMAND__END; 1359 1360 header.version = MMSCH_VERSION; 1361 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1362 for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) { 1363 header.inst[i].init_status = 0; 1364 header.inst[i].table_offset = 0; 1365 header.inst[i].table_size = 0; 1366 } 1367 1368 table_loc = (uint32_t *)table->cpu_addr; 1369 table_loc += header.total_size; 1370 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1371 if (adev->vcn.harvest_config & (1 << i)) 1372 continue; 1373 1374 // Must re/init fw_shared at beginning 1375 vcn_v4_0_fw_shared_init(adev, i); 1376 1377 table_size = 0; 1378 1379 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1380 regUVD_STATUS), 1381 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1382 1383 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1384 1385 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1386 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1387 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1388 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1389 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1390 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1391 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1392 offset = 0; 1393 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1394 regUVD_VCPU_CACHE_OFFSET0), 1395 0); 1396 } else { 1397 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1398 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1399 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1400 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1401 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1402 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1403 offset = cache_size; 1404 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1405 regUVD_VCPU_CACHE_OFFSET0), 1406 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1407 } 1408 1409 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1410 regUVD_VCPU_CACHE_SIZE0), 1411 cache_size); 1412 1413 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1414 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1415 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1416 lower_32_bits(cache_addr)); 1417 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1418 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1419 upper_32_bits(cache_addr)); 1420 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1421 regUVD_VCPU_CACHE_OFFSET1), 1422 0); 1423 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1424 regUVD_VCPU_CACHE_SIZE1), 1425 AMDGPU_VCN_STACK_SIZE); 1426 1427 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1428 AMDGPU_VCN_STACK_SIZE; 1429 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1430 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1431 lower_32_bits(cache_addr)); 1432 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1433 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1434 upper_32_bits(cache_addr)); 1435 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1436 regUVD_VCPU_CACHE_OFFSET2), 1437 0); 1438 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1439 regUVD_VCPU_CACHE_SIZE2), 1440 AMDGPU_VCN_CONTEXT_SIZE); 1441 1442 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1443 rb_setup = &fw_shared->rb_setup; 1444 1445 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1446 ring_enc->wptr = 0; 1447 rb_enc_addr = ring_enc->gpu_addr; 1448 1449 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1450 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1451 1452 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) { 1453 vcn_v4_0_init_ring_metadata(adev, i, ring_enc); 1454 1455 memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SETUP); 1456 if (!(adev->vcn.harvest_config & (1 << 0))) { 1457 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); 1458 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); 1459 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4; 1460 } 1461 if (!(adev->vcn.harvest_config & (1 << 1))) { 1462 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); 1463 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); 1464 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4; 1465 } 1466 fw_shared->decouple.is_enabled = 1; 1467 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG); 1468 } else { 1469 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1470 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1471 rb_setup->rb_size = ring_enc->ring_size / 4; 1472 } 1473 1474 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1475 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1476 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1477 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1478 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1479 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1480 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1481 regUVD_VCPU_NONCACHE_SIZE0), 1482 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1483 1484 /* add end packet */ 1485 MMSCH_V4_0_INSERT_END(); 1486 1487 /* refine header */ 1488 header.inst[i].init_status = 0; 1489 header.inst[i].table_offset = header.total_size; 1490 header.inst[i].table_size = table_size; 1491 header.total_size += table_size; 1492 } 1493 1494 /* Update init table header in memory */ 1495 size = sizeof(struct mmsch_v4_0_init_header); 1496 table_loc = (uint32_t *)table->cpu_addr; 1497 memcpy((void *)table_loc, &header, size); 1498 1499 /* message MMSCH (in VCN[0]) to initialize this client 1500 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1501 * of memory descriptor location 1502 */ 1503 ctx_addr = table->gpu_addr; 1504 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1505 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1506 1507 /* 2, update vmid of descriptor */ 1508 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1509 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1510 /* use domain0 for MM scheduler */ 1511 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1512 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1513 1514 /* 3, notify mmsch about the size of this descriptor */ 1515 size = header.total_size; 1516 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1517 1518 /* 4, set resp to zero */ 1519 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1520 1521 /* 5, kick off the initialization and wait until 1522 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1523 */ 1524 param = 0x00000001; 1525 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1526 tmp = 0; 1527 timeout = 1000; 1528 resp = 0; 1529 expected = MMSCH_VF_MAILBOX_RESP__OK; 1530 while (resp != expected) { 1531 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1532 if (resp != 0) 1533 break; 1534 1535 udelay(10); 1536 tmp = tmp + 10; 1537 if (tmp >= timeout) { 1538 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1539 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1540 "(expected=0x%08x, readback=0x%08x)\n", 1541 tmp, expected, resp); 1542 return -EBUSY; 1543 } 1544 } 1545 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1546 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1547 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1548 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1549 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1550 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1551 1552 return 0; 1553 } 1554 1555 /** 1556 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1557 * 1558 * @vinst: VCN instance 1559 * 1560 * Stop VCN block with dpg mode 1561 */ 1562 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1563 { 1564 struct amdgpu_device *adev = vinst->adev; 1565 int inst_idx = vinst->inst; 1566 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1567 uint32_t tmp; 1568 1569 vcn_v4_0_pause_dpg_mode(vinst, &state); 1570 /* Wait for power status to be 1 */ 1571 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1572 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1573 1574 /* wait for read ptr to be equal to write ptr */ 1575 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1576 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1577 1578 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1579 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1580 1581 /* disable dynamic power gating mode */ 1582 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1583 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1584 } 1585 1586 /** 1587 * vcn_v4_0_stop - VCN stop 1588 * 1589 * @vinst: VCN instance 1590 * 1591 * Stop VCN block 1592 */ 1593 static int vcn_v4_0_stop(struct amdgpu_vcn_inst *vinst) 1594 { 1595 struct amdgpu_device *adev = vinst->adev; 1596 int i = vinst->inst; 1597 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1598 uint32_t tmp; 1599 int r = 0; 1600 1601 if (adev->vcn.harvest_config & (1 << i)) 1602 return 0; 1603 1604 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1605 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1606 1607 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1608 vcn_v4_0_stop_dpg_mode(vinst); 1609 r = 0; 1610 goto done; 1611 } 1612 1613 /* wait for vcn idle */ 1614 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1615 if (r) 1616 goto done; 1617 1618 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1619 UVD_LMI_STATUS__READ_CLEAN_MASK | 1620 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1621 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1622 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1623 if (r) 1624 goto done; 1625 1626 /* disable LMI UMC channel */ 1627 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1628 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1629 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1630 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1631 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1632 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1633 if (r) 1634 goto done; 1635 1636 /* block VCPU register access */ 1637 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1638 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1639 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1640 1641 /* reset VCPU */ 1642 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1643 UVD_VCPU_CNTL__BLK_RST_MASK, 1644 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1645 1646 /* disable VCPU clock */ 1647 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1648 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1649 1650 /* apply soft reset */ 1651 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1652 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1653 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1654 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1655 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1656 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1657 1658 /* clear status */ 1659 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1660 1661 /* apply HW clock gating */ 1662 vcn_v4_0_enable_clock_gating(vinst); 1663 1664 /* enable VCN power gating */ 1665 vcn_v4_0_enable_static_power_gating(vinst); 1666 1667 done: 1668 if (adev->pm.dpm_enabled) 1669 amdgpu_dpm_enable_vcn(adev, false, i); 1670 1671 return 0; 1672 } 1673 1674 /** 1675 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1676 * 1677 * @vinst: VCN instance 1678 * @new_state: pause state 1679 * 1680 * Pause dpg mode for VCN block 1681 */ 1682 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1683 struct dpg_pause_state *new_state) 1684 { 1685 struct amdgpu_device *adev = vinst->adev; 1686 int inst_idx = vinst->inst; 1687 uint32_t reg_data = 0; 1688 int ret_code; 1689 1690 /* pause/unpause if state is changed */ 1691 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1692 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1693 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1694 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1695 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1696 1697 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1698 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1699 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1700 1701 if (!ret_code) { 1702 /* pause DPG */ 1703 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1704 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1705 1706 /* wait for ACK */ 1707 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1708 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1709 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1710 1711 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1712 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1713 } 1714 } else { 1715 /* unpause dpg, no need to wait */ 1716 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1717 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1718 } 1719 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1720 } 1721 1722 return 0; 1723 } 1724 1725 /** 1726 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1727 * 1728 * @ring: amdgpu_ring pointer 1729 * 1730 * Returns the current hardware unified read pointer 1731 */ 1732 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1733 { 1734 struct amdgpu_device *adev = ring->adev; 1735 1736 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1737 DRM_ERROR("wrong ring id is identified in %s", __func__); 1738 1739 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1740 } 1741 1742 /** 1743 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1744 * 1745 * @ring: amdgpu_ring pointer 1746 * 1747 * Returns the current hardware unified write pointer 1748 */ 1749 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1750 { 1751 struct amdgpu_device *adev = ring->adev; 1752 1753 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1754 DRM_ERROR("wrong ring id is identified in %s", __func__); 1755 1756 if (ring->use_doorbell) 1757 return *ring->wptr_cpu_addr; 1758 else 1759 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1760 } 1761 1762 /** 1763 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1764 * 1765 * @ring: amdgpu_ring pointer 1766 * 1767 * Commits the enc write pointer to the hardware 1768 */ 1769 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1770 { 1771 struct amdgpu_device *adev = ring->adev; 1772 1773 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1774 DRM_ERROR("wrong ring id is identified in %s", __func__); 1775 1776 if (ring->use_doorbell) { 1777 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1778 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1779 } else { 1780 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1781 } 1782 } 1783 1784 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1785 struct amdgpu_job *job) 1786 { 1787 struct drm_gpu_scheduler **scheds; 1788 1789 /* The create msg must be in the first IB submitted */ 1790 if (atomic_read(&job->base.entity->fence_seq)) 1791 return -EINVAL; 1792 1793 /* if VCN0 is harvested, we can't support AV1 */ 1794 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1795 return -EINVAL; 1796 1797 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1798 [AMDGPU_RING_PRIO_0].sched; 1799 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1800 return 0; 1801 } 1802 1803 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1804 uint64_t addr) 1805 { 1806 struct ttm_operation_ctx ctx = { false, false }; 1807 struct amdgpu_bo_va_mapping *map; 1808 uint32_t *msg, num_buffers; 1809 struct amdgpu_bo *bo; 1810 uint64_t start, end; 1811 unsigned int i; 1812 void *ptr; 1813 int r; 1814 1815 addr &= AMDGPU_GMC_HOLE_MASK; 1816 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1817 if (r) { 1818 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1819 return r; 1820 } 1821 1822 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1823 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1824 if (addr & 0x7) { 1825 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1826 return -EINVAL; 1827 } 1828 1829 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1830 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1831 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1832 if (r) { 1833 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1834 return r; 1835 } 1836 1837 r = amdgpu_bo_kmap(bo, &ptr); 1838 if (r) { 1839 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1840 return r; 1841 } 1842 1843 msg = ptr + addr - start; 1844 1845 /* Check length */ 1846 if (msg[1] > end - addr) { 1847 r = -EINVAL; 1848 goto out; 1849 } 1850 1851 if (msg[3] != RDECODE_MSG_CREATE) 1852 goto out; 1853 1854 num_buffers = msg[2]; 1855 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1856 uint32_t offset, size, *create; 1857 1858 if (msg[0] != RDECODE_MESSAGE_CREATE) 1859 continue; 1860 1861 offset = msg[1]; 1862 size = msg[2]; 1863 1864 if (offset + size > end) { 1865 r = -EINVAL; 1866 goto out; 1867 } 1868 1869 create = ptr + addr + offset - start; 1870 1871 /* H264, HEVC and VP9 can run on any instance */ 1872 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1873 continue; 1874 1875 r = vcn_v4_0_limit_sched(p, job); 1876 if (r) 1877 goto out; 1878 } 1879 1880 out: 1881 amdgpu_bo_kunmap(bo); 1882 return r; 1883 } 1884 1885 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1886 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1887 1888 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1889 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1890 1891 #define RENCODE_ENCODE_STANDARD_AV1 2 1892 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1893 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1894 1895 /* return the offset in ib if id is found, -1 otherwise 1896 * to speed up the searching we only search upto max_offset 1897 */ 1898 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1899 { 1900 int i; 1901 1902 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1903 if (ib->ptr[i + 1] == id) 1904 return i; 1905 } 1906 return -1; 1907 } 1908 1909 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1910 struct amdgpu_job *job, 1911 struct amdgpu_ib *ib) 1912 { 1913 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1914 struct amdgpu_vcn_decode_buffer *decode_buffer; 1915 uint64_t addr; 1916 uint32_t val; 1917 int idx; 1918 1919 /* The first instance can decode anything */ 1920 if (!ring->me) 1921 return 0; 1922 1923 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1924 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1925 RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1926 if (idx < 0) /* engine info is missing */ 1927 return 0; 1928 1929 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1930 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1931 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1932 1933 if (!(decode_buffer->valid_buf_flag & 0x1)) 1934 return 0; 1935 1936 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1937 decode_buffer->msg_buffer_address_lo; 1938 return vcn_v4_0_dec_msg(p, job, addr); 1939 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1940 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1941 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1942 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1943 return vcn_v4_0_limit_sched(p, job); 1944 } 1945 return 0; 1946 } 1947 1948 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1949 .type = AMDGPU_RING_TYPE_VCN_ENC, 1950 .align_mask = 0x3f, 1951 .nop = VCN_ENC_CMD_NO_OP, 1952 .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata), 1953 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1954 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1955 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1956 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1957 .emit_frame_size = 1958 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1959 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1960 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1961 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1962 1, /* vcn_v2_0_enc_ring_insert_end */ 1963 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1964 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1965 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1966 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1967 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1968 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1969 .insert_nop = amdgpu_ring_insert_nop, 1970 .insert_end = vcn_v2_0_enc_ring_insert_end, 1971 .pad_ib = amdgpu_ring_generic_pad_ib, 1972 .begin_use = amdgpu_vcn_ring_begin_use, 1973 .end_use = amdgpu_vcn_ring_end_use, 1974 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1975 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1976 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1977 }; 1978 1979 /** 1980 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1981 * 1982 * @adev: amdgpu_device pointer 1983 * 1984 * Set unified ring functions 1985 */ 1986 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1987 { 1988 int i; 1989 1990 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1991 if (adev->vcn.harvest_config & (1 << i)) 1992 continue; 1993 1994 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2)) 1995 vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true; 1996 1997 adev->vcn.inst[i].ring_enc[0].funcs = 1998 (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs; 1999 adev->vcn.inst[i].ring_enc[0].me = i; 2000 } 2001 } 2002 2003 /** 2004 * vcn_v4_0_is_idle - check VCN block is idle 2005 * 2006 * @ip_block: Pointer to the amdgpu_ip_block structure 2007 * 2008 * Check whether VCN block is idle 2009 */ 2010 static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block) 2011 { 2012 struct amdgpu_device *adev = ip_block->adev; 2013 int i, ret = 1; 2014 2015 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2016 if (adev->vcn.harvest_config & (1 << i)) 2017 continue; 2018 2019 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 2020 } 2021 2022 return ret; 2023 } 2024 2025 /** 2026 * vcn_v4_0_wait_for_idle - wait for VCN block idle 2027 * 2028 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 2029 * 2030 * Wait for VCN block idle 2031 */ 2032 static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2033 { 2034 struct amdgpu_device *adev = ip_block->adev; 2035 int i, ret = 0; 2036 2037 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2038 if (adev->vcn.harvest_config & (1 << i)) 2039 continue; 2040 2041 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 2042 UVD_STATUS__IDLE); 2043 if (ret) 2044 return ret; 2045 } 2046 2047 return ret; 2048 } 2049 2050 /** 2051 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 2052 * 2053 * @ip_block: amdgpu_ip_block pointer 2054 * @state: clock gating state 2055 * 2056 * Set VCN block clockgating state 2057 */ 2058 static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2059 enum amd_clockgating_state state) 2060 { 2061 struct amdgpu_device *adev = ip_block->adev; 2062 bool enable = state == AMD_CG_STATE_GATE; 2063 int i; 2064 2065 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2066 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 2067 2068 if (adev->vcn.harvest_config & (1 << i)) 2069 continue; 2070 2071 if (enable) { 2072 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 2073 return -EBUSY; 2074 vcn_v4_0_enable_clock_gating(vinst); 2075 } else { 2076 vcn_v4_0_disable_clock_gating(vinst); 2077 } 2078 } 2079 2080 return 0; 2081 } 2082 2083 static int vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 2084 enum amd_powergating_state state) 2085 { 2086 struct amdgpu_device *adev = vinst->adev; 2087 int ret = 0; 2088 2089 /* for SRIOV, guest should not control VCN Power-gating 2090 * MMSCH FW should control Power-gating and clock-gating 2091 * guest should avoid touching CGC and PG 2092 */ 2093 if (amdgpu_sriov_vf(adev)) { 2094 vinst->cur_state = AMD_PG_STATE_UNGATE; 2095 return 0; 2096 } 2097 2098 if (state == vinst->cur_state) 2099 return 0; 2100 2101 if (state == AMD_PG_STATE_GATE) 2102 ret = vcn_v4_0_stop(vinst); 2103 else 2104 ret = vcn_v4_0_start(vinst); 2105 2106 if (!ret) 2107 vinst->cur_state = state; 2108 2109 return ret; 2110 } 2111 2112 /** 2113 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state 2114 * 2115 * @adev: amdgpu_device pointer 2116 * @source: interrupt sources 2117 * @type: interrupt types 2118 * @state: interrupt states 2119 * 2120 * Set VCN block RAS interrupt state 2121 */ 2122 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 2123 struct amdgpu_irq_src *source, 2124 unsigned int type, 2125 enum amdgpu_interrupt_state state) 2126 { 2127 return 0; 2128 } 2129 2130 /** 2131 * vcn_v4_0_process_interrupt - process VCN block interrupt 2132 * 2133 * @adev: amdgpu_device pointer 2134 * @source: interrupt sources 2135 * @entry: interrupt entry from clients and sources 2136 * 2137 * Process VCN block interrupt 2138 */ 2139 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 2140 struct amdgpu_iv_entry *entry) 2141 { 2142 uint32_t ip_instance; 2143 2144 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) { 2145 ip_instance = entry->ring_id; 2146 } else { 2147 switch (entry->client_id) { 2148 case SOC15_IH_CLIENTID_VCN: 2149 ip_instance = 0; 2150 break; 2151 case SOC15_IH_CLIENTID_VCN1: 2152 ip_instance = 1; 2153 break; 2154 default: 2155 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2156 return 0; 2157 } 2158 } 2159 2160 DRM_DEBUG("IH: VCN TRAP\n"); 2161 2162 switch (entry->src_id) { 2163 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2164 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2165 break; 2166 default: 2167 DRM_ERROR("Unhandled interrupt: %d %d\n", 2168 entry->src_id, entry->src_data[0]); 2169 break; 2170 } 2171 2172 return 0; 2173 } 2174 2175 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 2176 .process = vcn_v4_0_process_interrupt, 2177 }; 2178 2179 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = { 2180 .set = vcn_v4_0_set_ras_interrupt_state, 2181 .process = amdgpu_vcn_process_poison_irq, 2182 }; 2183 2184 /** 2185 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 2186 * 2187 * @adev: amdgpu_device pointer 2188 * 2189 * Set VCN block interrupt irq functions 2190 */ 2191 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2192 { 2193 int i; 2194 2195 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2196 if (adev->vcn.harvest_config & (1 << i)) 2197 continue; 2198 2199 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2200 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 2201 2202 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2203 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs; 2204 } 2205 } 2206 2207 static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2208 { 2209 struct amdgpu_device *adev = ip_block->adev; 2210 int i, j; 2211 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); 2212 uint32_t inst_off, is_powered; 2213 2214 if (!adev->vcn.ip_dump) 2215 return; 2216 2217 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2218 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2219 if (adev->vcn.harvest_config & (1 << i)) { 2220 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2221 continue; 2222 } 2223 2224 inst_off = i * reg_count; 2225 is_powered = (adev->vcn.ip_dump[inst_off] & 2226 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2227 2228 if (is_powered) { 2229 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2230 for (j = 0; j < reg_count; j++) 2231 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name, 2232 adev->vcn.ip_dump[inst_off + j]); 2233 } else { 2234 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2235 } 2236 } 2237 } 2238 2239 static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 2240 { 2241 struct amdgpu_device *adev = ip_block->adev; 2242 int i, j; 2243 bool is_powered; 2244 uint32_t inst_off; 2245 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); 2246 2247 if (!adev->vcn.ip_dump) 2248 return; 2249 2250 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2251 if (adev->vcn.harvest_config & (1 << i)) 2252 continue; 2253 2254 inst_off = i * reg_count; 2255 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2256 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 2257 is_powered = (adev->vcn.ip_dump[inst_off] & 2258 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2259 2260 if (is_powered) 2261 for (j = 1; j < reg_count; j++) 2262 adev->vcn.ip_dump[inst_off + j] = 2263 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j], 2264 i)); 2265 } 2266 } 2267 2268 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2269 .name = "vcn_v4_0", 2270 .early_init = vcn_v4_0_early_init, 2271 .sw_init = vcn_v4_0_sw_init, 2272 .sw_fini = vcn_v4_0_sw_fini, 2273 .hw_init = vcn_v4_0_hw_init, 2274 .hw_fini = vcn_v4_0_hw_fini, 2275 .suspend = vcn_v4_0_suspend, 2276 .resume = vcn_v4_0_resume, 2277 .is_idle = vcn_v4_0_is_idle, 2278 .wait_for_idle = vcn_v4_0_wait_for_idle, 2279 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2280 .set_powergating_state = vcn_set_powergating_state, 2281 .dump_ip_state = vcn_v4_0_dump_ip_state, 2282 .print_ip_state = vcn_v4_0_print_ip_state, 2283 }; 2284 2285 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = { 2286 .type = AMD_IP_BLOCK_TYPE_VCN, 2287 .major = 4, 2288 .minor = 0, 2289 .rev = 0, 2290 .funcs = &vcn_v4_0_ip_funcs, 2291 }; 2292 2293 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2294 uint32_t instance, uint32_t sub_block) 2295 { 2296 uint32_t poison_stat = 0, reg_value = 0; 2297 2298 switch (sub_block) { 2299 case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2300 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2301 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2302 break; 2303 default: 2304 break; 2305 } 2306 2307 if (poison_stat) 2308 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2309 instance, sub_block); 2310 2311 return poison_stat; 2312 } 2313 2314 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2315 { 2316 uint32_t inst, sub; 2317 uint32_t poison_stat = 0; 2318 2319 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2320 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2321 poison_stat += 2322 vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2323 2324 return !!poison_stat; 2325 } 2326 2327 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2328 .query_poison_status = vcn_v4_0_query_ras_poison_status, 2329 }; 2330 2331 static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2332 .ras_block = { 2333 .hw_ops = &vcn_v4_0_ras_hw_ops, 2334 .ras_late_init = amdgpu_vcn_ras_late_init, 2335 }, 2336 }; 2337 2338 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2339 { 2340 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2341 case IP_VERSION(4, 0, 0): 2342 adev->vcn.ras = &vcn_v4_0_ras; 2343 break; 2344 default: 2345 break; 2346 } 2347 } 2348