1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include "amdgpu.h"
26 #include "amdgpu_vcn.h"
27 #include "amdgpu_pm.h"
28 #include "amdgpu_cs.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "soc15_hw_ip.h"
32 #include "vcn_v2_0.h"
33 #include "mmsch_v4_0.h"
34 #include "vcn_v4_0.h"
35
36 #include "vcn/vcn_4_0_0_offset.h"
37 #include "vcn/vcn_4_0_0_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
39
40 #include <drm/drm_drv.h>
41
42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
46
47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300
49 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000
50
51 #define VCN_HARVEST_MMSCH 0
52
53 #define RDECODE_MSG_CREATE 0x00000000
54 #define RDECODE_MESSAGE_CREATE 0x00000001
55
56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = {
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),
85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),
86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
90 };
91
92 static int amdgpu_ih_clientid_vcns[] = {
93 SOC15_IH_CLIENTID_VCN,
94 SOC15_IH_CLIENTID_VCN1
95 };
96
97 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
98 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
99 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
100 static int vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
101 enum amd_powergating_state state);
102 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
103 struct dpg_pause_state *new_state);
104 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
105 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
106
107 /**
108 * vcn_v4_0_early_init - set function pointers and load microcode
109 *
110 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
111 *
112 * Set ring and irq function pointers
113 * Load microcode from filesystem
114 */
vcn_v4_0_early_init(struct amdgpu_ip_block * ip_block)115 static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block)
116 {
117 struct amdgpu_device *adev = ip_block->adev;
118 int i, r;
119
120 if (amdgpu_sriov_vf(adev)) {
121 adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
122 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
123 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
124 adev->vcn.harvest_config |= 1 << i;
125 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
126 }
127 }
128 }
129
130 for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
131 /* re-use enc ring as unified ring */
132 adev->vcn.inst[i].num_enc_rings = 1;
133
134 vcn_v4_0_set_unified_ring_funcs(adev);
135 vcn_v4_0_set_irq_funcs(adev);
136 vcn_v4_0_set_ras_funcs(adev);
137
138 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
139 adev->vcn.inst[i].set_pg_state = vcn_v4_0_set_pg_state;
140
141 r = amdgpu_vcn_early_init(adev, i);
142 if (r)
143 return r;
144 }
145
146 return 0;
147 }
148
vcn_v4_0_fw_shared_init(struct amdgpu_device * adev,int inst_idx)149 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
150 {
151 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
152
153 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
154 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
155 fw_shared->sq.is_enabled = 1;
156
157 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
158 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
159 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
160
161 if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
162 IP_VERSION(4, 0, 2)) {
163 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;
164 fw_shared->drm_key_wa.method =
165 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;
166 }
167
168 if (amdgpu_vcnfw_log)
169 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
170
171 return 0;
172 }
173
174 /**
175 * vcn_v4_0_sw_init - sw init for VCN block
176 *
177 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
178 *
179 * Load firmware and sw initialization
180 */
vcn_v4_0_sw_init(struct amdgpu_ip_block * ip_block)181 static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
182 {
183 struct amdgpu_ring *ring;
184 struct amdgpu_device *adev = ip_block->adev;
185 int i, r;
186 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
187 uint32_t *ptr;
188
189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
190 if (adev->vcn.harvest_config & (1 << i))
191 continue;
192
193 r = amdgpu_vcn_sw_init(adev, i);
194 if (r)
195 return r;
196
197 amdgpu_vcn_setup_ucode(adev, i);
198
199 r = amdgpu_vcn_resume(adev, i);
200 if (r)
201 return r;
202
203 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
204 if (i == 0)
205 atomic_set(&adev->vcn.inst[i].sched_score, 1);
206 else
207 atomic_set(&adev->vcn.inst[i].sched_score, 0);
208
209 /* VCN UNIFIED TRAP */
210 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
211 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
212 if (r)
213 return r;
214
215 /* VCN POISON TRAP */
216 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
217 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
218 if (r)
219 return r;
220
221 ring = &adev->vcn.inst[i].ring_enc[0];
222 ring->use_doorbell = true;
223 if (amdgpu_sriov_vf(adev))
224 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i *
225 (adev->vcn.inst[i].num_enc_rings + 1) + 1;
226 else
227 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
228 ring->vm_hub = AMDGPU_MMHUB0(0);
229 sprintf(ring->name, "vcn_unified_%d", i);
230
231 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
232 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
233 if (r)
234 return r;
235
236 vcn_v4_0_fw_shared_init(adev, i);
237
238 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
239 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
240 }
241
242 adev->vcn.supported_reset =
243 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
244 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
245
246 if (amdgpu_sriov_vf(adev)) {
247 r = amdgpu_virt_alloc_mm_table(adev);
248 if (r)
249 return r;
250 }
251
252
253 r = amdgpu_vcn_ras_sw_init(adev);
254 if (r)
255 return r;
256
257 /* Allocate memory for VCN IP Dump buffer */
258 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
259 if (!ptr) {
260 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
261 adev->vcn.ip_dump = NULL;
262 } else {
263 adev->vcn.ip_dump = ptr;
264 }
265
266 r = amdgpu_vcn_sysfs_reset_mask_init(adev);
267 if (r)
268 return r;
269
270 return 0;
271 }
272
273 /**
274 * vcn_v4_0_sw_fini - sw fini for VCN block
275 *
276 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
277 *
278 * VCN suspend and free up sw allocation
279 */
vcn_v4_0_sw_fini(struct amdgpu_ip_block * ip_block)280 static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
281 {
282 struct amdgpu_device *adev = ip_block->adev;
283 int i, r, idx;
284
285 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
286 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
287 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
288
289 if (adev->vcn.harvest_config & (1 << i))
290 continue;
291
292 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
293 fw_shared->present_flag_0 = 0;
294 fw_shared->sq.is_enabled = 0;
295 }
296
297 drm_dev_exit(idx);
298 }
299
300 if (amdgpu_sriov_vf(adev))
301 amdgpu_virt_free_mm_table(adev);
302
303 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
304 r = amdgpu_vcn_suspend(adev, i);
305 if (r)
306 return r;
307 }
308
309 amdgpu_vcn_sysfs_reset_mask_fini(adev);
310
311 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
312 r = amdgpu_vcn_sw_fini(adev, i);
313 if (r)
314 return r;
315 }
316
317 kfree(adev->vcn.ip_dump);
318
319 return 0;
320 }
321
322 /**
323 * vcn_v4_0_hw_init - start and test VCN block
324 *
325 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
326 *
327 * Initialize the hardware, boot up the VCPU and do some testing
328 */
vcn_v4_0_hw_init(struct amdgpu_ip_block * ip_block)329 static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
330 {
331 struct amdgpu_device *adev = ip_block->adev;
332 struct amdgpu_ring *ring;
333 int i, r;
334
335 if (amdgpu_sriov_vf(adev)) {
336 r = vcn_v4_0_start_sriov(adev);
337 if (r)
338 return r;
339
340 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
341 if (adev->vcn.harvest_config & (1 << i))
342 continue;
343
344 ring = &adev->vcn.inst[i].ring_enc[0];
345 ring->wptr = 0;
346 ring->wptr_old = 0;
347 vcn_v4_0_unified_ring_set_wptr(ring);
348 ring->sched.ready = true;
349 }
350 } else {
351 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
352 if (adev->vcn.harvest_config & (1 << i))
353 continue;
354
355 ring = &adev->vcn.inst[i].ring_enc[0];
356
357 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
358 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
359
360 r = amdgpu_ring_test_helper(ring);
361 if (r)
362 return r;
363 }
364 }
365
366 return 0;
367 }
368
369 /**
370 * vcn_v4_0_hw_fini - stop the hardware block
371 *
372 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
373 *
374 * Stop the VCN block, mark ring as not ready any more
375 */
vcn_v4_0_hw_fini(struct amdgpu_ip_block * ip_block)376 static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
377 {
378 struct amdgpu_device *adev = ip_block->adev;
379 int i;
380
381 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
382 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
383
384 if (adev->vcn.harvest_config & (1 << i))
385 continue;
386
387 cancel_delayed_work_sync(&vinst->idle_work);
388
389 if (!amdgpu_sriov_vf(adev)) {
390 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
391 (vinst->cur_state != AMD_PG_STATE_GATE &&
392 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
393 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE);
394 }
395 }
396 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
397 amdgpu_irq_put(adev, &vinst->ras_poison_irq, 0);
398 }
399
400 return 0;
401 }
402
403 /**
404 * vcn_v4_0_suspend - suspend VCN block
405 *
406 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
407 *
408 * HW fini and suspend VCN block
409 */
vcn_v4_0_suspend(struct amdgpu_ip_block * ip_block)410 static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block)
411 {
412 struct amdgpu_device *adev = ip_block->adev;
413 int r, i;
414
415 r = vcn_v4_0_hw_fini(ip_block);
416 if (r)
417 return r;
418
419 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
420 r = amdgpu_vcn_suspend(ip_block->adev, i);
421 if (r)
422 return r;
423 }
424
425 return 0;
426 }
427
428 /**
429 * vcn_v4_0_resume - resume VCN block
430 *
431 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
432 *
433 * Resume firmware and hw init VCN block
434 */
vcn_v4_0_resume(struct amdgpu_ip_block * ip_block)435 static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block)
436 {
437 struct amdgpu_device *adev = ip_block->adev;
438 int r, i;
439
440 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
441 r = amdgpu_vcn_resume(ip_block->adev, i);
442 if (r)
443 return r;
444 }
445
446 r = vcn_v4_0_hw_init(ip_block);
447
448 return r;
449 }
450
451 /**
452 * vcn_v4_0_mc_resume - memory controller programming
453 *
454 * @vinst: VCN instance
455 *
456 * Let the VCN memory controller know it's offsets
457 */
vcn_v4_0_mc_resume(struct amdgpu_vcn_inst * vinst)458 static void vcn_v4_0_mc_resume(struct amdgpu_vcn_inst *vinst)
459 {
460 struct amdgpu_device *adev = vinst->adev;
461 int inst = vinst->inst;
462 uint32_t offset, size;
463 const struct common_firmware_header *hdr;
464
465 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
466 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
467
468 /* cache window 0: fw */
469 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
470 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
471 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
472 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
473 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
474 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
475 offset = 0;
476 } else {
477 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
478 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
479 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
480 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
481 offset = size;
482 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
483 }
484 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
485
486 /* cache window 1: stack */
487 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
488 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
489 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
490 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
491 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
492 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
493
494 /* cache window 2: context */
495 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
496 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
497 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
498 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
499 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
500 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
501
502 /* non-cache window */
503 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
504 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
505 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
506 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
507 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
508 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
509 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
510 }
511
512 /**
513 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
514 *
515 * @vinst: VCN instance
516 * @indirect: indirectly write sram
517 *
518 * Let the VCN memory controller know it's offsets with dpg mode
519 */
vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)520 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
521 bool indirect)
522 {
523 struct amdgpu_device *adev = vinst->adev;
524 int inst_idx = vinst->inst;
525 uint32_t offset, size;
526 const struct common_firmware_header *hdr;
527 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
528 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
529
530 /* cache window 0: fw */
531 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
532 if (!indirect) {
533 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
534 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
535 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
537 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
538 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
540 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
541 } else {
542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
543 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
545 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
547 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
548 }
549 offset = 0;
550 } else {
551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
552 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
553 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
555 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
556 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
557 offset = size;
558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
559 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
560 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
561 }
562
563 if (!indirect)
564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
565 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
566 else
567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
568 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
569
570 /* cache window 1: stack */
571 if (!indirect) {
572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
573 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
574 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
576 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
577 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
579 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
580 } else {
581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
582 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
584 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
586 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
587 }
588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
589 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
590
591 /* cache window 2: context */
592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
593 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
594 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
596 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
597 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
598 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
599 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
600 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
601 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
602
603 /* non-cache window */
604 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
605 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
606 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
607 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
608 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
609 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
611 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
612 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
613 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
614 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
615
616 /* VCN global tiling registers */
617 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
618 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
619 adev->gfx.config.gb_addr_config, 0, indirect);
620 }
621
622 /**
623 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
624 *
625 * @vinst: VCN instance
626 *
627 * Disable static power gating for VCN block
628 */
vcn_v4_0_disable_static_power_gating(struct amdgpu_vcn_inst * vinst)629 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
630 {
631 struct amdgpu_device *adev = vinst->adev;
632 int inst = vinst->inst;
633 uint32_t data = 0;
634
635 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
636 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
637 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
638 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
639 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
640 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
641 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
642 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
643 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
644 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
645 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
646 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
647 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
648 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
649 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
650
651 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
652 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
653 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
654 } else {
655 uint32_t value;
656
657 value = (inst) ? 0x2200800 : 0;
658 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
659 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
660 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
661 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
662 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
663 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
664 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
665 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
666 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
667 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
668 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
669 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
670 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
671 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
672
673 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
674 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF);
675 }
676
677 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
678 data &= ~0x103;
679 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
680 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
681 UVD_POWER_STATUS__UVD_PG_EN_MASK;
682
683 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
684
685 return;
686 }
687
688 /**
689 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
690 *
691 * @vinst: VCN instance
692 *
693 * Enable static power gating for VCN block
694 */
vcn_v4_0_enable_static_power_gating(struct amdgpu_vcn_inst * vinst)695 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
696 {
697 struct amdgpu_device *adev = vinst->adev;
698 int inst = vinst->inst;
699 uint32_t data;
700
701 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
702 /* Before power off, this indicator has to be turned on */
703 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
704 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
705 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
706 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
707
708 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
709 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
710 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
711 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
712 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
713 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
714 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
715 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
716 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
717 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
718 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
719 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
720 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
721 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
722 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
723
724 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
725 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
726 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
727 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
728 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
729 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
730 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
731 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
732 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
733 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
734 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
735 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
736 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
737 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
738 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
739 }
740
741 return;
742 }
743
744 /**
745 * vcn_v4_0_disable_clock_gating - disable VCN clock gating
746 *
747 * @vinst: VCN instance
748 *
749 * Disable clock gating for VCN block
750 */
vcn_v4_0_disable_clock_gating(struct amdgpu_vcn_inst * vinst)751 static void vcn_v4_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
752 {
753 struct amdgpu_device *adev = vinst->adev;
754 int inst = vinst->inst;
755 uint32_t data;
756
757 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
758 return;
759
760 /* VCN disable CGC */
761 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
762 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
763 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
764 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
765 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
766
767 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
768 data &= ~(UVD_CGC_GATE__SYS_MASK
769 | UVD_CGC_GATE__UDEC_MASK
770 | UVD_CGC_GATE__MPEG2_MASK
771 | UVD_CGC_GATE__REGS_MASK
772 | UVD_CGC_GATE__RBC_MASK
773 | UVD_CGC_GATE__LMI_MC_MASK
774 | UVD_CGC_GATE__LMI_UMC_MASK
775 | UVD_CGC_GATE__IDCT_MASK
776 | UVD_CGC_GATE__MPRD_MASK
777 | UVD_CGC_GATE__MPC_MASK
778 | UVD_CGC_GATE__LBSI_MASK
779 | UVD_CGC_GATE__LRBBM_MASK
780 | UVD_CGC_GATE__UDEC_RE_MASK
781 | UVD_CGC_GATE__UDEC_CM_MASK
782 | UVD_CGC_GATE__UDEC_IT_MASK
783 | UVD_CGC_GATE__UDEC_DB_MASK
784 | UVD_CGC_GATE__UDEC_MP_MASK
785 | UVD_CGC_GATE__WCB_MASK
786 | UVD_CGC_GATE__VCPU_MASK
787 | UVD_CGC_GATE__MMSCH_MASK);
788
789 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
790 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
791
792 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
793 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
794 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
795 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
796 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
797 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
798 | UVD_CGC_CTRL__SYS_MODE_MASK
799 | UVD_CGC_CTRL__UDEC_MODE_MASK
800 | UVD_CGC_CTRL__MPEG2_MODE_MASK
801 | UVD_CGC_CTRL__REGS_MODE_MASK
802 | UVD_CGC_CTRL__RBC_MODE_MASK
803 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
804 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
805 | UVD_CGC_CTRL__IDCT_MODE_MASK
806 | UVD_CGC_CTRL__MPRD_MODE_MASK
807 | UVD_CGC_CTRL__MPC_MODE_MASK
808 | UVD_CGC_CTRL__LBSI_MODE_MASK
809 | UVD_CGC_CTRL__LRBBM_MODE_MASK
810 | UVD_CGC_CTRL__WCB_MODE_MASK
811 | UVD_CGC_CTRL__VCPU_MODE_MASK
812 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
813 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
814
815 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
816 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
817 | UVD_SUVD_CGC_GATE__SIT_MASK
818 | UVD_SUVD_CGC_GATE__SMP_MASK
819 | UVD_SUVD_CGC_GATE__SCM_MASK
820 | UVD_SUVD_CGC_GATE__SDB_MASK
821 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
822 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
823 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
824 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
825 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
826 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
827 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
828 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
829 | UVD_SUVD_CGC_GATE__SCLR_MASK
830 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
831 | UVD_SUVD_CGC_GATE__ENT_MASK
832 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
833 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
834 | UVD_SUVD_CGC_GATE__SITE_MASK
835 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
836 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
837 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
838 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
839 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
840 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
841
842 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
843 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
844 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
845 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
846 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
847 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
848 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
849 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
850 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
851 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
852 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
853 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
854 }
855
856 /**
857 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
858 *
859 * @vinst: VCN instance
860 * @sram_sel: sram select
861 * @indirect: indirectly write sram
862 *
863 * Disable clock gating for VCN block with dpg mode
864 */
vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst * vinst,uint8_t sram_sel,uint8_t indirect)865 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
866 uint8_t sram_sel,
867 uint8_t indirect)
868 {
869 struct amdgpu_device *adev = vinst->adev;
870 int inst_idx = vinst->inst;
871 uint32_t reg_data = 0;
872
873 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
874 return;
875
876 /* enable sw clock gating control */
877 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
878 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
879 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
880 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
881 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
882 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
883 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
884 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
885 UVD_CGC_CTRL__SYS_MODE_MASK |
886 UVD_CGC_CTRL__UDEC_MODE_MASK |
887 UVD_CGC_CTRL__MPEG2_MODE_MASK |
888 UVD_CGC_CTRL__REGS_MODE_MASK |
889 UVD_CGC_CTRL__RBC_MODE_MASK |
890 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
891 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
892 UVD_CGC_CTRL__IDCT_MODE_MASK |
893 UVD_CGC_CTRL__MPRD_MODE_MASK |
894 UVD_CGC_CTRL__MPC_MODE_MASK |
895 UVD_CGC_CTRL__LBSI_MODE_MASK |
896 UVD_CGC_CTRL__LRBBM_MODE_MASK |
897 UVD_CGC_CTRL__WCB_MODE_MASK |
898 UVD_CGC_CTRL__VCPU_MODE_MASK);
899 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
900 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
901
902 /* turn off clock gating */
903 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
904 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
905
906 /* turn on SUVD clock gating */
907 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
908 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
909
910 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
911 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
912 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
913 }
914
915 /**
916 * vcn_v4_0_enable_clock_gating - enable VCN clock gating
917 *
918 * @vinst: VCN instance
919 *
920 * Enable clock gating for VCN block
921 */
vcn_v4_0_enable_clock_gating(struct amdgpu_vcn_inst * vinst)922 static void vcn_v4_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
923 {
924 struct amdgpu_device *adev = vinst->adev;
925 int inst = vinst->inst;
926 uint32_t data;
927
928 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
929 return;
930
931 /* enable VCN CGC */
932 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
933 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
934 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
935 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
936 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
937
938 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
939 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
940 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
941 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
942 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
943 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
944 | UVD_CGC_CTRL__SYS_MODE_MASK
945 | UVD_CGC_CTRL__UDEC_MODE_MASK
946 | UVD_CGC_CTRL__MPEG2_MODE_MASK
947 | UVD_CGC_CTRL__REGS_MODE_MASK
948 | UVD_CGC_CTRL__RBC_MODE_MASK
949 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
950 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
951 | UVD_CGC_CTRL__IDCT_MODE_MASK
952 | UVD_CGC_CTRL__MPRD_MODE_MASK
953 | UVD_CGC_CTRL__MPC_MODE_MASK
954 | UVD_CGC_CTRL__LBSI_MODE_MASK
955 | UVD_CGC_CTRL__LRBBM_MODE_MASK
956 | UVD_CGC_CTRL__WCB_MODE_MASK
957 | UVD_CGC_CTRL__VCPU_MODE_MASK
958 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
959 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
960
961 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
962 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
963 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
964 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
965 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
966 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
967 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
968 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
969 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
970 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
971 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
972 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
973 }
974
vcn_v4_0_enable_ras(struct amdgpu_vcn_inst * vinst,bool indirect)975 static void vcn_v4_0_enable_ras(struct amdgpu_vcn_inst *vinst,
976 bool indirect)
977 {
978 struct amdgpu_device *adev = vinst->adev;
979 int inst_idx = vinst->inst;
980 uint32_t tmp;
981
982 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
983 return;
984
985 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
986 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
987 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
988 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
989 WREG32_SOC15_DPG_MODE(inst_idx,
990 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
991 tmp, 0, indirect);
992
993 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
994 WREG32_SOC15_DPG_MODE(inst_idx,
995 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
996 tmp, 0, indirect);
997 }
998
999 /**
1000 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
1001 *
1002 * @vinst: VCN instance
1003 * @indirect: indirectly write sram
1004 *
1005 * Start VCN block with dpg mode
1006 */
vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)1007 static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
1008 {
1009 struct amdgpu_device *adev = vinst->adev;
1010 int inst_idx = vinst->inst;
1011 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1012 struct amdgpu_ring *ring;
1013 uint32_t tmp;
1014
1015 /* disable register anti-hang mechanism */
1016 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
1017 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1018 /* enable dynamic power gating mode */
1019 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
1020 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
1021 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
1022 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
1023
1024 if (indirect)
1025 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
1026
1027 /* enable clock gating */
1028 vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect);
1029
1030 /* enable VCPU clock */
1031 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1032 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
1033 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1034 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
1035
1036 /* disable master interupt */
1037 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1038 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
1039
1040 /* setup regUVD_LMI_CTRL */
1041 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1042 UVD_LMI_CTRL__REQ_MODE_MASK |
1043 UVD_LMI_CTRL__CRC_RESET_MASK |
1044 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1045 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1046 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1047 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1048 0x00100000L);
1049 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1050 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
1051
1052 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1053 VCN, inst_idx, regUVD_MPC_CNTL),
1054 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
1055
1056 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1057 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
1058 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1059 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1060 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1061 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
1062
1063 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1064 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
1065 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1066 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1067 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1068 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
1069
1070 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1071 VCN, inst_idx, regUVD_MPC_SET_MUX),
1072 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1073 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1074 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1075
1076 vcn_v4_0_mc_resume_dpg_mode(vinst, indirect);
1077
1078 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1079 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1080 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1081 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
1082
1083 /* enable LMI MC and UMC channels */
1084 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
1085 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1086 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
1087
1088 vcn_v4_0_enable_ras(vinst, indirect);
1089
1090 /* enable master interrupt */
1091 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1092 VCN, inst_idx, regUVD_MASTINT_EN),
1093 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1094
1095
1096 if (indirect)
1097 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
1098
1099 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1100
1101 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
1102 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1103 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
1104
1105 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1106 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1107 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1108 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1109 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1110 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1111
1112 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
1113 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
1114 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1115
1116 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1117 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1118 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1119 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1120
1121 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
1122 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1123 VCN_RB1_DB_CTRL__EN_MASK);
1124
1125 /* Keeping one read-back to ensure all register writes are done,
1126 * otherwise it may introduce race conditions.
1127 */
1128 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);
1129
1130 return 0;
1131 }
1132
1133
1134 /**
1135 * vcn_v4_0_start - VCN start
1136 *
1137 * @vinst: VCN instance
1138 *
1139 * Start VCN block
1140 */
vcn_v4_0_start(struct amdgpu_vcn_inst * vinst)1141 static int vcn_v4_0_start(struct amdgpu_vcn_inst *vinst)
1142 {
1143 struct amdgpu_device *adev = vinst->adev;
1144 int i = vinst->inst;
1145 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1146 struct amdgpu_ring *ring;
1147 uint32_t tmp;
1148 int j, k, r;
1149
1150 if (adev->vcn.harvest_config & (1 << i))
1151 return 0;
1152
1153 if (adev->pm.dpm_enabled)
1154 amdgpu_dpm_enable_vcn(adev, true, i);
1155
1156 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1157
1158 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1159 return vcn_v4_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
1160
1161 /* disable VCN power gating */
1162 vcn_v4_0_disable_static_power_gating(vinst);
1163
1164 /* set VCN status busy */
1165 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1166 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
1167
1168 /*SW clock gating */
1169 vcn_v4_0_disable_clock_gating(vinst);
1170
1171 /* enable VCPU clock */
1172 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1173 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1174
1175 /* disable master interrupt */
1176 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
1177 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1178
1179 /* enable LMI MC and UMC channels */
1180 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
1181 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1182
1183 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1184 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1185 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1186 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1187
1188 /* setup regUVD_LMI_CTRL */
1189 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1190 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1191 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1192 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1193 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1194 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1195
1196 /* setup regUVD_MPC_CNTL */
1197 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1198 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1199 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1200 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1201
1202 /* setup UVD_MPC_SET_MUXA0 */
1203 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1204 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1205 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1206 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1207 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1208
1209 /* setup UVD_MPC_SET_MUXB0 */
1210 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1211 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1212 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1213 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1214 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1215
1216 /* setup UVD_MPC_SET_MUX */
1217 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1218 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1219 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1220 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1221
1222 vcn_v4_0_mc_resume(vinst);
1223
1224 /* VCN global tiling registers */
1225 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1226 adev->gfx.config.gb_addr_config);
1227
1228 /* unblock VCPU register access */
1229 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1230 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1231
1232 /* release VCPU reset to boot */
1233 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1234 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1235
1236 for (j = 0; j < 10; ++j) {
1237 uint32_t status;
1238
1239 for (k = 0; k < 100; ++k) {
1240 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1241 if (status & 2)
1242 break;
1243 mdelay(10);
1244 if (amdgpu_emu_mode == 1)
1245 msleep(1);
1246 }
1247
1248 if (amdgpu_emu_mode == 1) {
1249 r = -1;
1250 if (status & 2) {
1251 r = 0;
1252 break;
1253 }
1254 } else {
1255 r = 0;
1256 if (status & 2)
1257 break;
1258
1259 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
1260 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1261 UVD_VCPU_CNTL__BLK_RST_MASK,
1262 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1263 mdelay(10);
1264 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1265 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1266
1267 mdelay(10);
1268 r = -1;
1269 }
1270 }
1271
1272 if (r) {
1273 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1274 return r;
1275 }
1276
1277 /* enable master interrupt */
1278 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1279 UVD_MASTINT_EN__VCPU_EN_MASK,
1280 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1281
1282 /* clear the busy bit of VCN_STATUS */
1283 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1284 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1285
1286 ring = &adev->vcn.inst[i].ring_enc[0];
1287 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1288 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1289 VCN_RB1_DB_CTRL__EN_MASK);
1290
1291 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1292 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1293 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1294
1295 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1296 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1297 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1298 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1299 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1300 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1301
1302 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1303 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1304 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1305
1306 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1307 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1308 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1309 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1310
1311 /* Keeping one read-back to ensure all register writes are done,
1312 * otherwise it may introduce race conditions.
1313 */
1314 RREG32_SOC15(VCN, i, regUVD_STATUS);
1315
1316 return 0;
1317 }
1318
vcn_v4_0_init_ring_metadata(struct amdgpu_device * adev,uint32_t vcn_inst,struct amdgpu_ring * ring_enc)1319 static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc)
1320 {
1321 struct amdgpu_vcn_rb_metadata *rb_metadata = NULL;
1322 uint8_t *rb_ptr = (uint8_t *)ring_enc->ring;
1323
1324 rb_ptr += ring_enc->ring_size;
1325 rb_metadata = (struct amdgpu_vcn_rb_metadata *)rb_ptr;
1326
1327 memset(rb_metadata, 0, sizeof(struct amdgpu_vcn_rb_metadata));
1328 rb_metadata->size = sizeof(struct amdgpu_vcn_rb_metadata);
1329 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1330 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG);
1331 rb_metadata->version = 1;
1332 rb_metadata->ring_id = vcn_inst & 0xFF;
1333
1334 return 0;
1335 }
1336
vcn_v4_0_start_sriov(struct amdgpu_device * adev)1337 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
1338 {
1339 int i;
1340 struct amdgpu_ring *ring_enc;
1341 uint64_t cache_addr;
1342 uint64_t rb_enc_addr;
1343 uint64_t ctx_addr;
1344 uint32_t param, resp, expected;
1345 uint32_t offset, cache_size;
1346 uint32_t tmp, timeout;
1347
1348 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1349 uint32_t *table_loc;
1350 uint32_t table_size;
1351 uint32_t size, size_dw;
1352 uint32_t init_status;
1353 uint32_t enabled_vcn;
1354
1355 struct mmsch_v4_0_cmd_direct_write
1356 direct_wt = { {0} };
1357 struct mmsch_v4_0_cmd_direct_read_modify_write
1358 direct_rd_mod_wt = { {0} };
1359 struct mmsch_v4_0_cmd_end end = { {0} };
1360 struct mmsch_v4_0_init_header header;
1361
1362 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1363 volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1364
1365 direct_wt.cmd_header.command_type =
1366 MMSCH_COMMAND__DIRECT_REG_WRITE;
1367 direct_rd_mod_wt.cmd_header.command_type =
1368 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1369 end.cmd_header.command_type =
1370 MMSCH_COMMAND__END;
1371
1372 header.version = MMSCH_VERSION;
1373 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
1374 for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
1375 header.inst[i].init_status = 0;
1376 header.inst[i].table_offset = 0;
1377 header.inst[i].table_size = 0;
1378 }
1379
1380 table_loc = (uint32_t *)table->cpu_addr;
1381 table_loc += header.total_size;
1382 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1383 if (adev->vcn.harvest_config & (1 << i))
1384 continue;
1385
1386 // Must re/init fw_shared at beginning
1387 vcn_v4_0_fw_shared_init(adev, i);
1388
1389 table_size = 0;
1390
1391 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1392 regUVD_STATUS),
1393 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1394
1395 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
1396
1397 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1398 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1399 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1400 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1401 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1402 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1403 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1404 offset = 0;
1405 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1406 regUVD_VCPU_CACHE_OFFSET0),
1407 0);
1408 } else {
1409 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1410 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1411 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1412 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1413 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1414 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1415 offset = cache_size;
1416 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1417 regUVD_VCPU_CACHE_OFFSET0),
1418 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1419 }
1420
1421 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1422 regUVD_VCPU_CACHE_SIZE0),
1423 cache_size);
1424
1425 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1426 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1427 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1428 lower_32_bits(cache_addr));
1429 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1430 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1431 upper_32_bits(cache_addr));
1432 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1433 regUVD_VCPU_CACHE_OFFSET1),
1434 0);
1435 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1436 regUVD_VCPU_CACHE_SIZE1),
1437 AMDGPU_VCN_STACK_SIZE);
1438
1439 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1440 AMDGPU_VCN_STACK_SIZE;
1441 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1442 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1443 lower_32_bits(cache_addr));
1444 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1445 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1446 upper_32_bits(cache_addr));
1447 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1448 regUVD_VCPU_CACHE_OFFSET2),
1449 0);
1450 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1451 regUVD_VCPU_CACHE_SIZE2),
1452 AMDGPU_VCN_CONTEXT_SIZE);
1453
1454 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1455 rb_setup = &fw_shared->rb_setup;
1456
1457 ring_enc = &adev->vcn.inst[i].ring_enc[0];
1458 ring_enc->wptr = 0;
1459 rb_enc_addr = ring_enc->gpu_addr;
1460
1461 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1462 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1463
1464 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) {
1465 vcn_v4_0_init_ring_metadata(adev, i, ring_enc);
1466
1467 memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SETUP);
1468 if (!(adev->vcn.harvest_config & (1 << 0))) {
1469 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
1470 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
1471 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4;
1472 }
1473 if (!(adev->vcn.harvest_config & (1 << 1))) {
1474 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
1475 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
1476 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4;
1477 }
1478 fw_shared->decouple.is_enabled = 1;
1479 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG);
1480 } else {
1481 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1482 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1483 rb_setup->rb_size = ring_enc->ring_size / 4;
1484 }
1485
1486 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1487 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1488 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1489 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1490 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1491 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1492 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1493 regUVD_VCPU_NONCACHE_SIZE0),
1494 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1495
1496 /* add end packet */
1497 MMSCH_V4_0_INSERT_END();
1498
1499 /* refine header */
1500 header.inst[i].init_status = 0;
1501 header.inst[i].table_offset = header.total_size;
1502 header.inst[i].table_size = table_size;
1503 header.total_size += table_size;
1504 }
1505
1506 /* Update init table header in memory */
1507 size = sizeof(struct mmsch_v4_0_init_header);
1508 table_loc = (uint32_t *)table->cpu_addr;
1509 memcpy((void *)table_loc, &header, size);
1510
1511 /* message MMSCH (in VCN[0]) to initialize this client
1512 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1513 * of memory descriptor location
1514 */
1515 ctx_addr = table->gpu_addr;
1516 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1517 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1518
1519 /* 2, update vmid of descriptor */
1520 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
1521 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1522 /* use domain0 for MM scheduler */
1523 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1524 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
1525
1526 /* 3, notify mmsch about the size of this descriptor */
1527 size = header.total_size;
1528 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
1529
1530 /* 4, set resp to zero */
1531 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
1532
1533 /* 5, kick off the initialization and wait until
1534 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1535 */
1536 param = 0x00000001;
1537 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
1538 tmp = 0;
1539 timeout = 1000;
1540 resp = 0;
1541 expected = MMSCH_VF_MAILBOX_RESP__OK;
1542 while (resp != expected) {
1543 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
1544 if (resp != 0)
1545 break;
1546
1547 udelay(10);
1548 tmp = tmp + 10;
1549 if (tmp >= timeout) {
1550 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1551 " waiting for regMMSCH_VF_MAILBOX_RESP "\
1552 "(expected=0x%08x, readback=0x%08x)\n",
1553 tmp, expected, resp);
1554 return -EBUSY;
1555 }
1556 }
1557 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1558 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
1559 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1560 && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
1561 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1562 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1563
1564 return 0;
1565 }
1566
1567 /**
1568 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1569 *
1570 * @vinst: VCN instance
1571 *
1572 * Stop VCN block with dpg mode
1573 */
vcn_v4_0_stop_dpg_mode(struct amdgpu_vcn_inst * vinst)1574 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
1575 {
1576 struct amdgpu_device *adev = vinst->adev;
1577 int inst_idx = vinst->inst;
1578 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1579 uint32_t tmp;
1580
1581 vcn_v4_0_pause_dpg_mode(vinst, &state);
1582 /* Wait for power status to be 1 */
1583 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1584 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1585
1586 /* wait for read ptr to be equal to write ptr */
1587 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1588 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1589
1590 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1591 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1592
1593 /* disable dynamic power gating mode */
1594 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1595 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1596
1597 /* Keeping one read-back to ensure all register writes are done,
1598 * otherwise it may introduce race conditions.
1599 */
1600 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);
1601 }
1602
1603 /**
1604 * vcn_v4_0_stop - VCN stop
1605 *
1606 * @vinst: VCN instance
1607 *
1608 * Stop VCN block
1609 */
vcn_v4_0_stop(struct amdgpu_vcn_inst * vinst)1610 static int vcn_v4_0_stop(struct amdgpu_vcn_inst *vinst)
1611 {
1612 struct amdgpu_device *adev = vinst->adev;
1613 int i = vinst->inst;
1614 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1615 uint32_t tmp;
1616 int r = 0;
1617
1618 if (adev->vcn.harvest_config & (1 << i))
1619 return 0;
1620
1621 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1622 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1623
1624 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1625 vcn_v4_0_stop_dpg_mode(vinst);
1626 r = 0;
1627 goto done;
1628 }
1629
1630 /* wait for vcn idle */
1631 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1632 if (r)
1633 goto done;
1634
1635 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1636 UVD_LMI_STATUS__READ_CLEAN_MASK |
1637 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1638 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1639 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1640 if (r)
1641 goto done;
1642
1643 /* disable LMI UMC channel */
1644 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1645 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1646 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1647 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1648 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1649 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1650 if (r)
1651 goto done;
1652
1653 /* block VCPU register access */
1654 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1655 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1656 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1657
1658 /* reset VCPU */
1659 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1660 UVD_VCPU_CNTL__BLK_RST_MASK,
1661 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1662
1663 /* disable VCPU clock */
1664 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1665 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1666
1667 /* apply soft reset */
1668 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1669 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1670 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1671 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1672 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1673 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1674
1675 /* clear status */
1676 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1677
1678 /* apply HW clock gating */
1679 vcn_v4_0_enable_clock_gating(vinst);
1680
1681 /* enable VCN power gating */
1682 vcn_v4_0_enable_static_power_gating(vinst);
1683
1684 /* Keeping one read-back to ensure all register writes are done,
1685 * otherwise it may introduce race conditions.
1686 */
1687 RREG32_SOC15(VCN, i, regUVD_STATUS);
1688
1689 done:
1690 if (adev->pm.dpm_enabled)
1691 amdgpu_dpm_enable_vcn(adev, false, i);
1692
1693 return 0;
1694 }
1695
1696 /**
1697 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
1698 *
1699 * @vinst: VCN instance
1700 * @new_state: pause state
1701 *
1702 * Pause dpg mode for VCN block
1703 */
vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst * vinst,struct dpg_pause_state * new_state)1704 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
1705 struct dpg_pause_state *new_state)
1706 {
1707 struct amdgpu_device *adev = vinst->adev;
1708 int inst_idx = vinst->inst;
1709 uint32_t reg_data = 0;
1710 int ret_code;
1711
1712 /* pause/unpause if state is changed */
1713 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1714 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1715 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1716 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1717 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1718
1719 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1720 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1721 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1722
1723 if (!ret_code) {
1724 /* pause DPG */
1725 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1726 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1727
1728 /* wait for ACK */
1729 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1730 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1731 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1732
1733 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1734 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1735 }
1736 } else {
1737 /* unpause dpg, no need to wait */
1738 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1739 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1740 }
1741 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1742 }
1743
1744 return 0;
1745 }
1746
1747 /**
1748 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
1749 *
1750 * @ring: amdgpu_ring pointer
1751 *
1752 * Returns the current hardware unified read pointer
1753 */
vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring * ring)1754 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
1755 {
1756 struct amdgpu_device *adev = ring->adev;
1757
1758 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1759 DRM_ERROR("wrong ring id is identified in %s", __func__);
1760
1761 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1762 }
1763
1764 /**
1765 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
1766 *
1767 * @ring: amdgpu_ring pointer
1768 *
1769 * Returns the current hardware unified write pointer
1770 */
vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring * ring)1771 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
1772 {
1773 struct amdgpu_device *adev = ring->adev;
1774
1775 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1776 DRM_ERROR("wrong ring id is identified in %s", __func__);
1777
1778 if (ring->use_doorbell)
1779 return *ring->wptr_cpu_addr;
1780 else
1781 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1782 }
1783
1784 /**
1785 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
1786 *
1787 * @ring: amdgpu_ring pointer
1788 *
1789 * Commits the enc write pointer to the hardware
1790 */
vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring * ring)1791 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
1792 {
1793 struct amdgpu_device *adev = ring->adev;
1794
1795 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1796 DRM_ERROR("wrong ring id is identified in %s", __func__);
1797
1798 if (ring->use_doorbell) {
1799 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1800 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1801 } else {
1802 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1803 }
1804 }
1805
vcn_v4_0_limit_sched(struct amdgpu_cs_parser * p,struct amdgpu_job * job)1806 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
1807 struct amdgpu_job *job)
1808 {
1809 struct drm_gpu_scheduler **scheds;
1810
1811 /* The create msg must be in the first IB submitted */
1812 if (atomic_read(&job->base.entity->fence_seq))
1813 return -EINVAL;
1814
1815 /* if VCN0 is harvested, we can't support AV1 */
1816 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1817 return -EINVAL;
1818
1819 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1820 [AMDGPU_RING_PRIO_0].sched;
1821 drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1822 return 0;
1823 }
1824
vcn_v4_0_dec_msg(struct amdgpu_cs_parser * p,struct amdgpu_job * job,uint64_t addr)1825 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1826 uint64_t addr)
1827 {
1828 struct ttm_operation_ctx ctx = { false, false };
1829 struct amdgpu_bo_va_mapping *map;
1830 uint32_t *msg, num_buffers;
1831 struct amdgpu_bo *bo;
1832 uint64_t start, end;
1833 unsigned int i;
1834 void *ptr;
1835 int r;
1836
1837 addr &= AMDGPU_GMC_HOLE_MASK;
1838 r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1839 if (r) {
1840 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
1841 return r;
1842 }
1843
1844 start = map->start * AMDGPU_GPU_PAGE_SIZE;
1845 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1846 if (addr & 0x7) {
1847 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1848 return -EINVAL;
1849 }
1850
1851 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1852 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1853 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1854 if (r) {
1855 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1856 return r;
1857 }
1858
1859 r = amdgpu_bo_kmap(bo, &ptr);
1860 if (r) {
1861 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1862 return r;
1863 }
1864
1865 msg = ptr + addr - start;
1866
1867 /* Check length */
1868 if (msg[1] > end - addr) {
1869 r = -EINVAL;
1870 goto out;
1871 }
1872
1873 if (msg[3] != RDECODE_MSG_CREATE)
1874 goto out;
1875
1876 num_buffers = msg[2];
1877 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1878 uint32_t offset, size, *create;
1879
1880 if (msg[0] != RDECODE_MESSAGE_CREATE)
1881 continue;
1882
1883 offset = msg[1];
1884 size = msg[2];
1885
1886 if (offset + size > end) {
1887 r = -EINVAL;
1888 goto out;
1889 }
1890
1891 create = ptr + addr + offset - start;
1892
1893 /* H264, HEVC and VP9 can run on any instance */
1894 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1895 continue;
1896
1897 r = vcn_v4_0_limit_sched(p, job);
1898 if (r)
1899 goto out;
1900 }
1901
1902 out:
1903 amdgpu_bo_kunmap(bo);
1904 return r;
1905 }
1906
1907 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002)
1908 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003)
1909
1910 #define RADEON_VCN_ENGINE_INFO (0x30000001)
1911 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16
1912
1913 #define RENCODE_ENCODE_STANDARD_AV1 2
1914 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
1915 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64
1916
1917 /* return the offset in ib if id is found, -1 otherwise
1918 * to speed up the searching we only search upto max_offset
1919 */
vcn_v4_0_enc_find_ib_param(struct amdgpu_ib * ib,uint32_t id,int max_offset)1920 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1921 {
1922 int i;
1923
1924 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1925 if (ib->ptr[i + 1] == id)
1926 return i;
1927 }
1928 return -1;
1929 }
1930
vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser * p,struct amdgpu_job * job,struct amdgpu_ib * ib)1931 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1932 struct amdgpu_job *job,
1933 struct amdgpu_ib *ib)
1934 {
1935 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1936 struct amdgpu_vcn_decode_buffer *decode_buffer;
1937 uint64_t addr;
1938 uint32_t val;
1939 int idx;
1940
1941 /* The first instance can decode anything */
1942 if (!ring->me)
1943 return 0;
1944
1945 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1946 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1947 RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1948 if (idx < 0) /* engine info is missing */
1949 return 0;
1950
1951 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1952 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1953 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
1954
1955 if (!(decode_buffer->valid_buf_flag & 0x1))
1956 return 0;
1957
1958 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1959 decode_buffer->msg_buffer_address_lo;
1960 return vcn_v4_0_dec_msg(p, job, addr);
1961 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1962 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1963 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1964 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1965 return vcn_v4_0_limit_sched(p, job);
1966 }
1967 return 0;
1968 }
1969
vcn_v4_0_ring_reset(struct amdgpu_ring * ring,unsigned int vmid)1970 static int vcn_v4_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
1971 {
1972 struct amdgpu_device *adev = ring->adev;
1973 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
1974
1975 if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
1976 return -EOPNOTSUPP;
1977
1978 vcn_v4_0_stop(vinst);
1979 vcn_v4_0_start(vinst);
1980
1981 return amdgpu_ring_test_helper(ring);
1982 }
1983
1984 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
1985 .type = AMDGPU_RING_TYPE_VCN_ENC,
1986 .align_mask = 0x3f,
1987 .nop = VCN_ENC_CMD_NO_OP,
1988 .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata),
1989 .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1990 .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1991 .set_wptr = vcn_v4_0_unified_ring_set_wptr,
1992 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
1993 .emit_frame_size =
1994 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1995 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1996 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1997 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1998 1, /* vcn_v2_0_enc_ring_insert_end */
1999 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2000 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2001 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2002 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2003 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2004 .test_ib = amdgpu_vcn_unified_ring_test_ib,
2005 .insert_nop = amdgpu_ring_insert_nop,
2006 .insert_end = vcn_v2_0_enc_ring_insert_end,
2007 .pad_ib = amdgpu_ring_generic_pad_ib,
2008 .begin_use = amdgpu_vcn_ring_begin_use,
2009 .end_use = amdgpu_vcn_ring_end_use,
2010 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2011 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2012 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2013 .reset = vcn_v4_0_ring_reset,
2014 };
2015
2016 /**
2017 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
2018 *
2019 * @adev: amdgpu_device pointer
2020 *
2021 * Set unified ring functions
2022 */
vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device * adev)2023 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
2024 {
2025 int i;
2026
2027 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2028 if (adev->vcn.harvest_config & (1 << i))
2029 continue;
2030
2031 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))
2032 vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
2033
2034 adev->vcn.inst[i].ring_enc[0].funcs =
2035 (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
2036 adev->vcn.inst[i].ring_enc[0].me = i;
2037 }
2038 }
2039
2040 /**
2041 * vcn_v4_0_is_idle - check VCN block is idle
2042 *
2043 * @ip_block: Pointer to the amdgpu_ip_block structure
2044 *
2045 * Check whether VCN block is idle
2046 */
vcn_v4_0_is_idle(struct amdgpu_ip_block * ip_block)2047 static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
2048 {
2049 struct amdgpu_device *adev = ip_block->adev;
2050 int i, ret = 1;
2051
2052 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2053 if (adev->vcn.harvest_config & (1 << i))
2054 continue;
2055
2056 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
2057 }
2058
2059 return ret;
2060 }
2061
2062 /**
2063 * vcn_v4_0_wait_for_idle - wait for VCN block idle
2064 *
2065 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
2066 *
2067 * Wait for VCN block idle
2068 */
vcn_v4_0_wait_for_idle(struct amdgpu_ip_block * ip_block)2069 static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
2070 {
2071 struct amdgpu_device *adev = ip_block->adev;
2072 int i, ret = 0;
2073
2074 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2075 if (adev->vcn.harvest_config & (1 << i))
2076 continue;
2077
2078 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
2079 UVD_STATUS__IDLE);
2080 if (ret)
2081 return ret;
2082 }
2083
2084 return ret;
2085 }
2086
2087 /**
2088 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
2089 *
2090 * @ip_block: amdgpu_ip_block pointer
2091 * @state: clock gating state
2092 *
2093 * Set VCN block clockgating state
2094 */
vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2095 static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2096 enum amd_clockgating_state state)
2097 {
2098 struct amdgpu_device *adev = ip_block->adev;
2099 bool enable = state == AMD_CG_STATE_GATE;
2100 int i;
2101
2102 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2103 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
2104
2105 if (adev->vcn.harvest_config & (1 << i))
2106 continue;
2107
2108 if (enable) {
2109 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
2110 return -EBUSY;
2111 vcn_v4_0_enable_clock_gating(vinst);
2112 } else {
2113 vcn_v4_0_disable_clock_gating(vinst);
2114 }
2115 }
2116
2117 return 0;
2118 }
2119
vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst * vinst,enum amd_powergating_state state)2120 static int vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
2121 enum amd_powergating_state state)
2122 {
2123 struct amdgpu_device *adev = vinst->adev;
2124 int ret = 0;
2125
2126 /* for SRIOV, guest should not control VCN Power-gating
2127 * MMSCH FW should control Power-gating and clock-gating
2128 * guest should avoid touching CGC and PG
2129 */
2130 if (amdgpu_sriov_vf(adev)) {
2131 vinst->cur_state = AMD_PG_STATE_UNGATE;
2132 return 0;
2133 }
2134
2135 if (state == vinst->cur_state)
2136 return 0;
2137
2138 if (state == AMD_PG_STATE_GATE)
2139 ret = vcn_v4_0_stop(vinst);
2140 else
2141 ret = vcn_v4_0_start(vinst);
2142
2143 if (!ret)
2144 vinst->cur_state = state;
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state
2151 *
2152 * @adev: amdgpu_device pointer
2153 * @source: interrupt sources
2154 * @type: interrupt types
2155 * @state: interrupt states
2156 *
2157 * Set VCN block RAS interrupt state
2158 */
vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)2159 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
2160 struct amdgpu_irq_src *source,
2161 unsigned int type,
2162 enum amdgpu_interrupt_state state)
2163 {
2164 return 0;
2165 }
2166
2167 /**
2168 * vcn_v4_0_process_interrupt - process VCN block interrupt
2169 *
2170 * @adev: amdgpu_device pointer
2171 * @source: interrupt sources
2172 * @entry: interrupt entry from clients and sources
2173 *
2174 * Process VCN block interrupt
2175 */
vcn_v4_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2176 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
2177 struct amdgpu_iv_entry *entry)
2178 {
2179 uint32_t ip_instance;
2180
2181 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) {
2182 ip_instance = entry->ring_id;
2183 } else {
2184 switch (entry->client_id) {
2185 case SOC15_IH_CLIENTID_VCN:
2186 ip_instance = 0;
2187 break;
2188 case SOC15_IH_CLIENTID_VCN1:
2189 ip_instance = 1;
2190 break;
2191 default:
2192 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2193 return 0;
2194 }
2195 }
2196
2197 DRM_DEBUG("IH: VCN TRAP\n");
2198
2199 switch (entry->src_id) {
2200 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2201 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2202 break;
2203 default:
2204 DRM_ERROR("Unhandled interrupt: %d %d\n",
2205 entry->src_id, entry->src_data[0]);
2206 break;
2207 }
2208
2209 return 0;
2210 }
2211
2212 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
2213 .process = vcn_v4_0_process_interrupt,
2214 };
2215
2216 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {
2217 .set = vcn_v4_0_set_ras_interrupt_state,
2218 .process = amdgpu_vcn_process_poison_irq,
2219 };
2220
2221 /**
2222 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
2223 *
2224 * @adev: amdgpu_device pointer
2225 *
2226 * Set VCN block interrupt irq functions
2227 */
vcn_v4_0_set_irq_funcs(struct amdgpu_device * adev)2228 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2229 {
2230 int i;
2231
2232 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2233 if (adev->vcn.harvest_config & (1 << i))
2234 continue;
2235
2236 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
2237 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
2238
2239 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
2240 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
2241 }
2242 }
2243
vcn_v4_0_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)2244 static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2245 {
2246 struct amdgpu_device *adev = ip_block->adev;
2247 int i, j;
2248 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
2249 uint32_t inst_off, is_powered;
2250
2251 if (!adev->vcn.ip_dump)
2252 return;
2253
2254 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
2255 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2256 if (adev->vcn.harvest_config & (1 << i)) {
2257 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
2258 continue;
2259 }
2260
2261 inst_off = i * reg_count;
2262 is_powered = (adev->vcn.ip_dump[inst_off] &
2263 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2264
2265 if (is_powered) {
2266 drm_printf(p, "\nActive Instance:VCN%d\n", i);
2267 for (j = 0; j < reg_count; j++)
2268 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
2269 adev->vcn.ip_dump[inst_off + j]);
2270 } else {
2271 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
2272 }
2273 }
2274 }
2275
vcn_v4_0_dump_ip_state(struct amdgpu_ip_block * ip_block)2276 static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
2277 {
2278 struct amdgpu_device *adev = ip_block->adev;
2279 int i, j;
2280 bool is_powered;
2281 uint32_t inst_off;
2282 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
2283
2284 if (!adev->vcn.ip_dump)
2285 return;
2286
2287 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2288 if (adev->vcn.harvest_config & (1 << i))
2289 continue;
2290
2291 inst_off = i * reg_count;
2292 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
2293 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
2294 is_powered = (adev->vcn.ip_dump[inst_off] &
2295 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2296
2297 if (is_powered)
2298 for (j = 1; j < reg_count; j++)
2299 adev->vcn.ip_dump[inst_off + j] =
2300 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
2301 i));
2302 }
2303 }
2304
2305 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
2306 .name = "vcn_v4_0",
2307 .early_init = vcn_v4_0_early_init,
2308 .sw_init = vcn_v4_0_sw_init,
2309 .sw_fini = vcn_v4_0_sw_fini,
2310 .hw_init = vcn_v4_0_hw_init,
2311 .hw_fini = vcn_v4_0_hw_fini,
2312 .suspend = vcn_v4_0_suspend,
2313 .resume = vcn_v4_0_resume,
2314 .is_idle = vcn_v4_0_is_idle,
2315 .wait_for_idle = vcn_v4_0_wait_for_idle,
2316 .set_clockgating_state = vcn_v4_0_set_clockgating_state,
2317 .set_powergating_state = vcn_set_powergating_state,
2318 .dump_ip_state = vcn_v4_0_dump_ip_state,
2319 .print_ip_state = vcn_v4_0_print_ip_state,
2320 };
2321
2322 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
2323 .type = AMD_IP_BLOCK_TYPE_VCN,
2324 .major = 4,
2325 .minor = 0,
2326 .rev = 0,
2327 .funcs = &vcn_v4_0_ip_funcs,
2328 };
2329
vcn_v4_0_query_poison_by_instance(struct amdgpu_device * adev,uint32_t instance,uint32_t sub_block)2330 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
2331 uint32_t instance, uint32_t sub_block)
2332 {
2333 uint32_t poison_stat = 0, reg_value = 0;
2334
2335 switch (sub_block) {
2336 case AMDGPU_VCN_V4_0_VCPU_VCODEC:
2337 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2338 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 if (poison_stat)
2345 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2346 instance, sub_block);
2347
2348 return poison_stat;
2349 }
2350
vcn_v4_0_query_ras_poison_status(struct amdgpu_device * adev)2351 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
2352 {
2353 uint32_t inst, sub;
2354 uint32_t poison_stat = 0;
2355
2356 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2357 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)
2358 poison_stat +=
2359 vcn_v4_0_query_poison_by_instance(adev, inst, sub);
2360
2361 return !!poison_stat;
2362 }
2363
2364 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {
2365 .query_poison_status = vcn_v4_0_query_ras_poison_status,
2366 };
2367
2368 static struct amdgpu_vcn_ras vcn_v4_0_ras = {
2369 .ras_block = {
2370 .hw_ops = &vcn_v4_0_ras_hw_ops,
2371 .ras_late_init = amdgpu_vcn_ras_late_init,
2372 },
2373 };
2374
vcn_v4_0_set_ras_funcs(struct amdgpu_device * adev)2375 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2376 {
2377 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2378 case IP_VERSION(4, 0, 0):
2379 adev->vcn.ras = &vcn_v4_0_ras;
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385