1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drm_drv.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_vcn.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "amdgpu_pm.h"
32 #include "amdgpu_psp.h"
33 #include "mmsch_v2_0.h"
34 #include "vcn_v2_0.h"
35
36 #include "vcn/vcn_2_0_0_offset.h"
37 #include "vcn/vcn_2_0_0_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39
40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
42 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000
43
44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
51
52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
56
57 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
91 };
92
93 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
94 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
95 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
96 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
97 enum amd_powergating_state state);
98 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
99 struct dpg_pause_state *new_state);
100 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
101 /**
102 * vcn_v2_0_early_init - set function pointers and load microcode
103 *
104 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
105 *
106 * Set ring and irq function pointers
107 * Load microcode from filesystem
108 */
vcn_v2_0_early_init(struct amdgpu_ip_block * ip_block)109 static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
110 {
111 struct amdgpu_device *adev = ip_block->adev;
112
113 if (amdgpu_sriov_vf(adev))
114 adev->vcn.inst[0].num_enc_rings = 1;
115 else
116 adev->vcn.inst[0].num_enc_rings = 2;
117
118 adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state;
119 vcn_v2_0_set_dec_ring_funcs(adev);
120 vcn_v2_0_set_enc_ring_funcs(adev);
121 vcn_v2_0_set_irq_funcs(adev);
122
123 return amdgpu_vcn_early_init(adev, 0);
124 }
125
126 /**
127 * vcn_v2_0_sw_init - sw init for VCN block
128 *
129 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
130 *
131 * Load firmware and sw initialization
132 */
vcn_v2_0_sw_init(struct amdgpu_ip_block * ip_block)133 static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
134 {
135 struct amdgpu_ring *ring;
136 int i, r;
137 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
138 uint32_t *ptr;
139 struct amdgpu_device *adev = ip_block->adev;
140 volatile struct amdgpu_fw_shared *fw_shared;
141
142 /* VCN DEC TRAP */
143 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
144 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
145 &adev->vcn.inst->irq);
146 if (r)
147 return r;
148
149 /* VCN ENC TRAP */
150 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
151 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
152 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
153 &adev->vcn.inst->irq);
154 if (r)
155 return r;
156 }
157
158 r = amdgpu_vcn_sw_init(adev, 0);
159 if (r)
160 return r;
161
162 amdgpu_vcn_setup_ucode(adev, 0);
163
164 r = amdgpu_vcn_resume(adev, 0);
165 if (r)
166 return r;
167
168 ring = &adev->vcn.inst->ring_dec;
169
170 ring->use_doorbell = true;
171 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
172 ring->vm_hub = AMDGPU_MMHUB0(0);
173
174 sprintf(ring->name, "vcn_dec");
175 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
176 AMDGPU_RING_PRIO_DEFAULT, NULL);
177 if (r)
178 return r;
179
180 adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
181 adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
182 adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
183 adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
184 adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
185 adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
186
187 adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
188 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
189 adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
190 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
191 adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
192 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
193 adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
194 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
195 adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
196 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
197
198 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
199 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
200
201 ring = &adev->vcn.inst->ring_enc[i];
202 ring->use_doorbell = true;
203 ring->vm_hub = AMDGPU_MMHUB0(0);
204 if (!amdgpu_sriov_vf(adev))
205 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
206 else
207 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
208 sprintf(ring->name, "vcn_enc%d", i);
209 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
210 hw_prio, NULL);
211 if (r)
212 return r;
213 }
214
215 adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
216
217 r = amdgpu_virt_alloc_mm_table(adev);
218 if (r)
219 return r;
220
221 fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
222 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
223
224 if (amdgpu_vcnfw_log)
225 amdgpu_vcn_fwlog_init(adev->vcn.inst);
226
227 /* Allocate memory for VCN IP Dump buffer */
228 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
229 if (!ptr) {
230 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
231 adev->vcn.ip_dump = NULL;
232 } else {
233 adev->vcn.ip_dump = ptr;
234 }
235
236 return 0;
237 }
238
239 /**
240 * vcn_v2_0_sw_fini - sw fini for VCN block
241 *
242 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
243 *
244 * VCN suspend and free up sw allocation
245 */
vcn_v2_0_sw_fini(struct amdgpu_ip_block * ip_block)246 static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
247 {
248 int r, idx;
249 struct amdgpu_device *adev = ip_block->adev;
250 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
251
252 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
253 fw_shared->present_flag_0 = 0;
254 drm_dev_exit(idx);
255 }
256
257 amdgpu_virt_free_mm_table(adev);
258
259 r = amdgpu_vcn_suspend(adev, 0);
260 if (r)
261 return r;
262
263 r = amdgpu_vcn_sw_fini(adev, 0);
264
265 kfree(adev->vcn.ip_dump);
266
267 return r;
268 }
269
270 /**
271 * vcn_v2_0_hw_init - start and test VCN block
272 *
273 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
274 *
275 * Initialize the hardware, boot up the VCPU and do some testing
276 */
vcn_v2_0_hw_init(struct amdgpu_ip_block * ip_block)277 static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block)
278 {
279 struct amdgpu_device *adev = ip_block->adev;
280 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
281 int i, r;
282
283 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
284 ring->doorbell_index, 0);
285
286 if (amdgpu_sriov_vf(adev))
287 vcn_v2_0_start_sriov(adev);
288
289 r = amdgpu_ring_test_helper(ring);
290 if (r)
291 return r;
292
293 //Disable vcn decode for sriov
294 if (amdgpu_sriov_vf(adev))
295 ring->sched.ready = false;
296
297 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
298 ring = &adev->vcn.inst->ring_enc[i];
299 r = amdgpu_ring_test_helper(ring);
300 if (r)
301 return r;
302 }
303
304 return 0;
305 }
306
307 /**
308 * vcn_v2_0_hw_fini - stop the hardware block
309 *
310 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
311 *
312 * Stop the VCN block, mark ring as not ready any more
313 */
vcn_v2_0_hw_fini(struct amdgpu_ip_block * ip_block)314 static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
315 {
316 struct amdgpu_device *adev = ip_block->adev;
317 struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
318
319 cancel_delayed_work_sync(&vinst->idle_work);
320
321 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
322 (vinst->cur_state != AMD_PG_STATE_GATE &&
323 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
324 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE);
325
326 return 0;
327 }
328
329 /**
330 * vcn_v2_0_suspend - suspend VCN block
331 *
332 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
333 *
334 * HW fini and suspend VCN block
335 */
vcn_v2_0_suspend(struct amdgpu_ip_block * ip_block)336 static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block)
337 {
338 int r;
339
340 r = vcn_v2_0_hw_fini(ip_block);
341 if (r)
342 return r;
343
344 r = amdgpu_vcn_suspend(ip_block->adev, 0);
345
346 return r;
347 }
348
349 /**
350 * vcn_v2_0_resume - resume VCN block
351 *
352 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
353 *
354 * Resume firmware and hw init VCN block
355 */
vcn_v2_0_resume(struct amdgpu_ip_block * ip_block)356 static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
357 {
358 int r;
359
360 r = amdgpu_vcn_resume(ip_block->adev, 0);
361 if (r)
362 return r;
363
364 r = vcn_v2_0_hw_init(ip_block);
365
366 return r;
367 }
368
369 /**
370 * vcn_v2_0_mc_resume - memory controller programming
371 *
372 * @vinst: Pointer to the VCN instance structure
373 *
374 * Let the VCN memory controller know it's offsets
375 */
vcn_v2_0_mc_resume(struct amdgpu_vcn_inst * vinst)376 static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst)
377 {
378 struct amdgpu_device *adev = vinst->adev;
379 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
380 uint32_t offset;
381
382 if (amdgpu_sriov_vf(adev))
383 return;
384
385 /* cache window 0: fw */
386 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
387 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
388 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
389 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
390 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
391 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
392 offset = 0;
393 } else {
394 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
395 lower_32_bits(adev->vcn.inst->gpu_addr));
396 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
397 upper_32_bits(adev->vcn.inst->gpu_addr));
398 offset = size;
399 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
400 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
401 }
402
403 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
404
405 /* cache window 1: stack */
406 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
407 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
408 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
409 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
410 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
411 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
412
413 /* cache window 2: context */
414 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
415 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
416 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
417 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
418 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
419 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
420
421 /* non-cache window */
422 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
423 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
424 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
425 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
426 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
427 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
428 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
429
430 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
431 }
432
vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)433 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
434 bool indirect)
435 {
436 struct amdgpu_device *adev = vinst->adev;
437 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
438 uint32_t offset;
439
440 /* cache window 0: fw */
441 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
442 if (!indirect) {
443 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
444 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
445 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
446 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
447 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
448 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
449 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
450 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
451 } else {
452 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
453 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
454 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
455 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
456 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
457 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
458 }
459 offset = 0;
460 } else {
461 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
462 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
463 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
464 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
465 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
466 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
467 offset = size;
468 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
469 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
470 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
471 }
472
473 if (!indirect)
474 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
475 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
476 else
477 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
478 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
479
480 /* cache window 1: stack */
481 if (!indirect) {
482 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
483 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
484 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
485 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
486 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
487 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
488 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
489 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
490 } else {
491 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
492 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
493 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
494 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
495 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
496 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
497 }
498 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
499 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
500
501 /* cache window 2: context */
502 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
503 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
504 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
505 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
506 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
507 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
508 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
509 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
510 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
511 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
512
513 /* non-cache window */
514 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
515 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
516 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
517 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
518 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
519 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
520 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
521 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
522 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
523 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
524 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
525
526 /* VCN global tiling registers */
527 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
528 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
529 }
530
531 /**
532 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
533 *
534 * @vinst: VCN instance
535 *
536 * Disable clock gating for VCN block
537 */
vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst * vinst)538 static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
539 {
540 struct amdgpu_device *adev = vinst->adev;
541 uint32_t data;
542
543 if (amdgpu_sriov_vf(adev))
544 return;
545
546 /* UVD disable CGC */
547 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
548 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
549 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
550 else
551 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
552 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
553 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
554 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
555
556 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
557 data &= ~(UVD_CGC_GATE__SYS_MASK
558 | UVD_CGC_GATE__UDEC_MASK
559 | UVD_CGC_GATE__MPEG2_MASK
560 | UVD_CGC_GATE__REGS_MASK
561 | UVD_CGC_GATE__RBC_MASK
562 | UVD_CGC_GATE__LMI_MC_MASK
563 | UVD_CGC_GATE__LMI_UMC_MASK
564 | UVD_CGC_GATE__IDCT_MASK
565 | UVD_CGC_GATE__MPRD_MASK
566 | UVD_CGC_GATE__MPC_MASK
567 | UVD_CGC_GATE__LBSI_MASK
568 | UVD_CGC_GATE__LRBBM_MASK
569 | UVD_CGC_GATE__UDEC_RE_MASK
570 | UVD_CGC_GATE__UDEC_CM_MASK
571 | UVD_CGC_GATE__UDEC_IT_MASK
572 | UVD_CGC_GATE__UDEC_DB_MASK
573 | UVD_CGC_GATE__UDEC_MP_MASK
574 | UVD_CGC_GATE__WCB_MASK
575 | UVD_CGC_GATE__VCPU_MASK
576 | UVD_CGC_GATE__SCPU_MASK);
577 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
578
579 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
580 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
581 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
582 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
583 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
584 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
585 | UVD_CGC_CTRL__SYS_MODE_MASK
586 | UVD_CGC_CTRL__UDEC_MODE_MASK
587 | UVD_CGC_CTRL__MPEG2_MODE_MASK
588 | UVD_CGC_CTRL__REGS_MODE_MASK
589 | UVD_CGC_CTRL__RBC_MODE_MASK
590 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
591 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
592 | UVD_CGC_CTRL__IDCT_MODE_MASK
593 | UVD_CGC_CTRL__MPRD_MODE_MASK
594 | UVD_CGC_CTRL__MPC_MODE_MASK
595 | UVD_CGC_CTRL__LBSI_MODE_MASK
596 | UVD_CGC_CTRL__LRBBM_MODE_MASK
597 | UVD_CGC_CTRL__WCB_MODE_MASK
598 | UVD_CGC_CTRL__VCPU_MODE_MASK
599 | UVD_CGC_CTRL__SCPU_MODE_MASK);
600 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
601
602 /* turn on */
603 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
604 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
605 | UVD_SUVD_CGC_GATE__SIT_MASK
606 | UVD_SUVD_CGC_GATE__SMP_MASK
607 | UVD_SUVD_CGC_GATE__SCM_MASK
608 | UVD_SUVD_CGC_GATE__SDB_MASK
609 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
610 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
611 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
612 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
613 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
614 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
615 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
616 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
617 | UVD_SUVD_CGC_GATE__SCLR_MASK
618 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
619 | UVD_SUVD_CGC_GATE__ENT_MASK
620 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
621 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
622 | UVD_SUVD_CGC_GATE__SITE_MASK
623 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
624 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
625 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
626 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
627 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
628 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
629
630 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
631 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
632 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
633 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
634 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
635 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
636 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
637 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
638 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
639 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
640 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
641 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
642 }
643
vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst * vinst,uint8_t sram_sel,uint8_t indirect)644 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
645 uint8_t sram_sel, uint8_t indirect)
646 {
647 struct amdgpu_device *adev = vinst->adev;
648 uint32_t reg_data = 0;
649
650 /* enable sw clock gating control */
651 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
652 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
653 else
654 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
655 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
656 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
657 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
658 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
659 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
660 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
661 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
662 UVD_CGC_CTRL__SYS_MODE_MASK |
663 UVD_CGC_CTRL__UDEC_MODE_MASK |
664 UVD_CGC_CTRL__MPEG2_MODE_MASK |
665 UVD_CGC_CTRL__REGS_MODE_MASK |
666 UVD_CGC_CTRL__RBC_MODE_MASK |
667 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
668 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
669 UVD_CGC_CTRL__IDCT_MODE_MASK |
670 UVD_CGC_CTRL__MPRD_MODE_MASK |
671 UVD_CGC_CTRL__MPC_MODE_MASK |
672 UVD_CGC_CTRL__LBSI_MODE_MASK |
673 UVD_CGC_CTRL__LRBBM_MODE_MASK |
674 UVD_CGC_CTRL__WCB_MODE_MASK |
675 UVD_CGC_CTRL__VCPU_MODE_MASK |
676 UVD_CGC_CTRL__SCPU_MODE_MASK);
677 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
678 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
679
680 /* turn off clock gating */
681 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
682 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
683
684 /* turn on SUVD clock gating */
685 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
686 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
687
688 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
689 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
690 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
691 }
692
693 /**
694 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
695 *
696 * @vinst: VCN instance
697 *
698 * Enable clock gating for VCN block
699 */
vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst * vinst)700 static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
701 {
702 struct amdgpu_device *adev = vinst->adev;
703 uint32_t data = 0;
704
705 if (amdgpu_sriov_vf(adev))
706 return;
707
708 /* enable UVD CGC */
709 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
710 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
711 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
712 else
713 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
714 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
715 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
716 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
717
718 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
719 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
720 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
721 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
722 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
723 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
724 | UVD_CGC_CTRL__SYS_MODE_MASK
725 | UVD_CGC_CTRL__UDEC_MODE_MASK
726 | UVD_CGC_CTRL__MPEG2_MODE_MASK
727 | UVD_CGC_CTRL__REGS_MODE_MASK
728 | UVD_CGC_CTRL__RBC_MODE_MASK
729 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
730 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
731 | UVD_CGC_CTRL__IDCT_MODE_MASK
732 | UVD_CGC_CTRL__MPRD_MODE_MASK
733 | UVD_CGC_CTRL__MPC_MODE_MASK
734 | UVD_CGC_CTRL__LBSI_MODE_MASK
735 | UVD_CGC_CTRL__LRBBM_MODE_MASK
736 | UVD_CGC_CTRL__WCB_MODE_MASK
737 | UVD_CGC_CTRL__VCPU_MODE_MASK
738 | UVD_CGC_CTRL__SCPU_MODE_MASK);
739 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
740
741 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
742 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
743 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
744 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
745 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
746 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
747 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
748 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
749 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
750 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
751 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
752 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
753 }
754
vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst * vinst)755 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
756 {
757 struct amdgpu_device *adev = vinst->adev;
758 uint32_t data = 0;
759
760 if (amdgpu_sriov_vf(adev))
761 return;
762
763 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
764 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
765 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
766 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
767 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
768 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
769 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
770 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
771 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
772 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
773 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
774
775 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
776 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
777 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);
778 } else {
779 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
780 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
781 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
782 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
783 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
784 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
785 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
786 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
787 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
788 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
789 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
790 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF);
791 }
792
793 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
794 * UVDU_PWR_STATUS are 0 (power on) */
795
796 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
797 data &= ~0x103;
798 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
799 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
800 UVD_POWER_STATUS__UVD_PG_EN_MASK;
801
802 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
803 }
804
vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst * vinst)805 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
806 {
807 struct amdgpu_device *adev = vinst->adev;
808 uint32_t data = 0;
809
810 if (amdgpu_sriov_vf(adev))
811 return;
812
813 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
814 /* Before power off, this indicator has to be turned on */
815 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
816 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
817 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
818 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
819
820
821 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
822 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
823 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
824 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
825 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
826 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
827 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
828 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
829 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
830 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
831
832 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
833
834 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
835 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
836 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
837 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
838 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
839 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
840 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
841 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
842 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
843 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
844 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);
845 }
846 }
847
vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)848 static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
849 {
850 struct amdgpu_device *adev = vinst->adev;
851 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
852 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
853 uint32_t rb_bufsz, tmp;
854
855 vcn_v2_0_enable_static_power_gating(vinst);
856
857 /* enable dynamic power gating mode */
858 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
859 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
860 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
861 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
862
863 if (indirect)
864 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
865
866 /* enable clock gating */
867 vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect);
868
869 /* enable VCPU clock */
870 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
871 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
872 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
873 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
874 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
875
876 /* disable master interupt */
877 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
878 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
879
880 /* setup mmUVD_LMI_CTRL */
881 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
882 UVD_LMI_CTRL__REQ_MODE_MASK |
883 UVD_LMI_CTRL__CRC_RESET_MASK |
884 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
885 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
886 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
887 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
888 0x00100000L);
889 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
890 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
891
892 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
893 UVD, 0, mmUVD_MPC_CNTL),
894 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
895
896 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
897 UVD, 0, mmUVD_MPC_SET_MUXA0),
898 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
899 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
900 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
901 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
902
903 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
904 UVD, 0, mmUVD_MPC_SET_MUXB0),
905 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
906 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
907 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
908 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
909
910 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
911 UVD, 0, mmUVD_MPC_SET_MUX),
912 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
913 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
914 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
915
916 vcn_v2_0_mc_resume_dpg_mode(vinst, indirect);
917
918 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
919 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
920 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
921 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
922
923 /* release VCPU reset to boot */
924 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
925 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
926
927 /* enable LMI MC and UMC channels */
928 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
929 UVD, 0, mmUVD_LMI_CTRL2),
930 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
931
932 /* enable master interrupt */
933 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
934 UVD, 0, mmUVD_MASTINT_EN),
935 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
936
937 if (indirect)
938 amdgpu_vcn_psp_update_sram(adev, 0, 0);
939
940 /* force RBC into idle state */
941 rb_bufsz = order_base_2(ring->ring_size);
942 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
943 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
944 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
945 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
946 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
947 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
948
949 /* Stall DPG before WPTR/RPTR reset */
950 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
951 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
952 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
953 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
954
955 /* set the write pointer delay */
956 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
957
958 /* set the wb address */
959 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
960 (upper_32_bits(ring->gpu_addr) >> 2));
961
962 /* program the RB_BASE for ring buffer */
963 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
964 lower_32_bits(ring->gpu_addr));
965 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
966 upper_32_bits(ring->gpu_addr));
967
968 /* Initialize the ring buffer's read and write pointers */
969 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
970
971 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
972
973 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
974 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
975 lower_32_bits(ring->wptr));
976
977 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
978 /* Unstall DPG */
979 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
980 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
981
982 /* Keeping one read-back to ensure all register writes are done,
983 * otherwise it may introduce race conditions.
984 */
985 RREG32_SOC15(UVD, 0, mmUVD_STATUS);
986
987 return 0;
988 }
989
vcn_v2_0_start(struct amdgpu_vcn_inst * vinst)990 static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
991 {
992 struct amdgpu_device *adev = vinst->adev;
993 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
994 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
995 uint32_t rb_bufsz, tmp;
996 uint32_t lmi_swap_cntl;
997 int i, j, r;
998
999 if (adev->pm.dpm_enabled)
1000 amdgpu_dpm_enable_vcn(adev, true, 0);
1001
1002 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1003 return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram);
1004
1005 vcn_v2_0_disable_static_power_gating(vinst);
1006
1007 /* set uvd status busy */
1008 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1009 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
1010
1011 /*SW clock gating */
1012 vcn_v2_0_disable_clock_gating(vinst);
1013
1014 /* enable VCPU clock */
1015 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
1016 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1017
1018 /* disable master interrupt */
1019 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
1020 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1021
1022 /* setup mmUVD_LMI_CTRL */
1023 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
1024 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
1025 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1026 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1027 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1028 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1029
1030 /* setup mmUVD_MPC_CNTL */
1031 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
1032 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1033 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1034 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
1035
1036 /* setup UVD_MPC_SET_MUXA0 */
1037 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
1038 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1039 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1040 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1041 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1042
1043 /* setup UVD_MPC_SET_MUXB0 */
1044 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
1045 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1046 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1047 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1048 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1049
1050 /* setup mmUVD_MPC_SET_MUX */
1051 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
1052 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1053 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1054 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1055
1056 vcn_v2_0_mc_resume(vinst);
1057
1058 /* release VCPU reset to boot */
1059 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1060 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1061
1062 /* enable LMI MC and UMC channels */
1063 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1064 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1065
1066 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1067 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1068 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1069 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1070
1071 /* disable byte swapping */
1072 lmi_swap_cntl = 0;
1073 #ifdef __BIG_ENDIAN
1074 /* swap (8 in 32) RB and IB */
1075 lmi_swap_cntl = 0xa;
1076 #endif
1077 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1078
1079 for (i = 0; i < 10; ++i) {
1080 uint32_t status;
1081
1082 for (j = 0; j < 100; ++j) {
1083 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1084 if (status & 2)
1085 break;
1086 mdelay(10);
1087 }
1088 r = 0;
1089 if (status & 2)
1090 break;
1091
1092 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1093 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1094 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1095 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1096 mdelay(10);
1097 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1098 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1099 mdelay(10);
1100 r = -1;
1101 }
1102
1103 if (r) {
1104 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1105 return r;
1106 }
1107
1108 /* enable master interrupt */
1109 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1110 UVD_MASTINT_EN__VCPU_EN_MASK,
1111 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1112
1113 /* clear the busy bit of VCN_STATUS */
1114 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1115 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1116
1117 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1118
1119 /* force RBC into idle state */
1120 rb_bufsz = order_base_2(ring->ring_size);
1121 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1122 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1123 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1124 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1125 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1126 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1127
1128 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1129 /* program the RB_BASE for ring buffer */
1130 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1131 lower_32_bits(ring->gpu_addr));
1132 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1133 upper_32_bits(ring->gpu_addr));
1134
1135 /* Initialize the ring buffer's read and write pointers */
1136 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1137
1138 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1139 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1140 lower_32_bits(ring->wptr));
1141 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1142
1143 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1144 ring = &adev->vcn.inst->ring_enc[0];
1145 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1146 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1147 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1148 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1149 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1150 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1151
1152 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1153 ring = &adev->vcn.inst->ring_enc[1];
1154 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1155 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1156 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1157 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1158 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1159 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1160
1161 /* Keeping one read-back to ensure all register writes are done,
1162 * otherwise it may introduce race conditions.
1163 */
1164 RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1165
1166 return 0;
1167 }
1168
vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst * vinst)1169 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
1170 {
1171 struct amdgpu_device *adev = vinst->adev;
1172 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1173 uint32_t tmp;
1174
1175 vcn_v2_0_pause_dpg_mode(vinst, &state);
1176 /* Wait for power status to be 1 */
1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1178 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1179
1180 /* wait for read ptr to be equal to write ptr */
1181 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1182 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1183
1184 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1185 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1186
1187 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1188 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1189
1190 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1191 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1192
1193 /* disable dynamic power gating mode */
1194 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1195 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1196
1197 /* Keeping one read-back to ensure all register writes are done,
1198 * otherwise it may introduce race conditions.
1199 */
1200 RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1201
1202 return 0;
1203 }
1204
vcn_v2_0_stop(struct amdgpu_vcn_inst * vinst)1205 static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)
1206 {
1207 struct amdgpu_device *adev = vinst->adev;
1208 uint32_t tmp;
1209 int r;
1210
1211 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1212 r = vcn_v2_0_stop_dpg_mode(vinst);
1213 if (r)
1214 return r;
1215 goto power_off;
1216 }
1217
1218 /* wait for uvd idle */
1219 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1220 if (r)
1221 return r;
1222
1223 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1224 UVD_LMI_STATUS__READ_CLEAN_MASK |
1225 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1226 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1227 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1228 if (r)
1229 return r;
1230
1231 /* stall UMC channel */
1232 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1233 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1234 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1235
1236 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1237 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1238 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1239 if (r)
1240 return r;
1241
1242 /* disable VCPU clock */
1243 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1244 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1245
1246 /* reset LMI UMC */
1247 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1248 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1249 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1250
1251 /* reset LMI */
1252 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1253 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1254 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1255
1256 /* reset VCPU */
1257 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1258 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1259 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1260
1261 /* clear status */
1262 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1263
1264 vcn_v2_0_enable_clock_gating(vinst);
1265 vcn_v2_0_enable_static_power_gating(vinst);
1266
1267 /* Keeping one read-back to ensure all register writes are done,
1268 * otherwise it may introduce race conditions.
1269 */
1270 RREG32_SOC15(VCN, 0, mmUVD_STATUS);
1271
1272 power_off:
1273 if (adev->pm.dpm_enabled)
1274 amdgpu_dpm_enable_vcn(adev, false, 0);
1275
1276 return 0;
1277 }
1278
vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst * vinst,struct dpg_pause_state * new_state)1279 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
1280 struct dpg_pause_state *new_state)
1281 {
1282 struct amdgpu_device *adev = vinst->adev;
1283 int inst_idx = vinst->inst;
1284 struct amdgpu_ring *ring;
1285 uint32_t reg_data = 0;
1286 int ret_code;
1287
1288 /* pause/unpause if state is changed */
1289 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1290 DRM_DEBUG("dpg pause state changed %d -> %d",
1291 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1292 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1293 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1294
1295 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1296 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1297 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1298
1299 if (!ret_code) {
1300 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1301 /* pause DPG */
1302 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1303 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1304
1305 /* wait for ACK */
1306 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1307 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1308 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1309
1310 /* Stall DPG before WPTR/RPTR reset */
1311 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1312 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1313 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1314 /* Restore */
1315 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1316 ring = &adev->vcn.inst->ring_enc[0];
1317 ring->wptr = 0;
1318 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1319 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1320 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1321 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1322 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1323 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1324
1325 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1326 ring = &adev->vcn.inst->ring_enc[1];
1327 ring->wptr = 0;
1328 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1329 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1330 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1331 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1332 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1333 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1334
1335 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1336 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1337 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1338 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1339 /* Unstall DPG */
1340 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1341 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1342
1343 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1344 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1345 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1346 }
1347 } else {
1348 /* unpause dpg, no need to wait */
1349 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1350 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1351 }
1352 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1353 }
1354
1355 return 0;
1356 }
1357
vcn_v2_0_is_idle(struct amdgpu_ip_block * ip_block)1358 static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
1359 {
1360 struct amdgpu_device *adev = ip_block->adev;
1361
1362 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1363 }
1364
vcn_v2_0_wait_for_idle(struct amdgpu_ip_block * ip_block)1365 static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1366 {
1367 struct amdgpu_device *adev = ip_block->adev;
1368 int ret;
1369
1370 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1371 UVD_STATUS__IDLE);
1372
1373 return ret;
1374 }
1375
vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1376 static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1377 enum amd_clockgating_state state)
1378 {
1379 struct amdgpu_device *adev = ip_block->adev;
1380 bool enable = (state == AMD_CG_STATE_GATE);
1381
1382 if (amdgpu_sriov_vf(adev))
1383 return 0;
1384
1385 if (enable) {
1386 /* wait for STATUS to clear */
1387 if (!vcn_v2_0_is_idle(ip_block))
1388 return -EBUSY;
1389 vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]);
1390 } else {
1391 /* disable HW gating and enable Sw gating */
1392 vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]);
1393 }
1394 return 0;
1395 }
1396
1397 /**
1398 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1399 *
1400 * @ring: amdgpu_ring pointer
1401 *
1402 * Returns the current hardware read pointer
1403 */
vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1404 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1405 {
1406 struct amdgpu_device *adev = ring->adev;
1407
1408 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1409 }
1410
1411 /**
1412 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1413 *
1414 * @ring: amdgpu_ring pointer
1415 *
1416 * Returns the current hardware write pointer
1417 */
vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1418 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1419 {
1420 struct amdgpu_device *adev = ring->adev;
1421
1422 if (ring->use_doorbell)
1423 return *ring->wptr_cpu_addr;
1424 else
1425 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1426 }
1427
1428 /**
1429 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1430 *
1431 * @ring: amdgpu_ring pointer
1432 *
1433 * Commits the write pointer to the hardware
1434 */
vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1435 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1436 {
1437 struct amdgpu_device *adev = ring->adev;
1438
1439 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1440 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1441 lower_32_bits(ring->wptr) | 0x80000000);
1442
1443 if (ring->use_doorbell) {
1444 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1445 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1446 } else {
1447 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1448 }
1449 }
1450
1451 /**
1452 * vcn_v2_0_dec_ring_insert_start - insert a start command
1453 *
1454 * @ring: amdgpu_ring pointer
1455 *
1456 * Write a start command to the ring.
1457 */
vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)1458 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1459 {
1460 struct amdgpu_device *adev = ring->adev;
1461
1462 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1463 amdgpu_ring_write(ring, 0);
1464 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1465 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1466 }
1467
1468 /**
1469 * vcn_v2_0_dec_ring_insert_end - insert a end command
1470 *
1471 * @ring: amdgpu_ring pointer
1472 *
1473 * Write a end command to the ring.
1474 */
vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)1475 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1476 {
1477 struct amdgpu_device *adev = ring->adev;
1478
1479 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0));
1480 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1481 }
1482
1483 /**
1484 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1485 *
1486 * @ring: amdgpu_ring pointer
1487 * @count: the number of NOP packets to insert
1488 *
1489 * Write a nop command to the ring.
1490 */
vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1491 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1492 {
1493 struct amdgpu_device *adev = ring->adev;
1494 int i;
1495
1496 WARN_ON(ring->wptr % 2 || count % 2);
1497
1498 for (i = 0; i < count / 2; i++) {
1499 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0));
1500 amdgpu_ring_write(ring, 0);
1501 }
1502 }
1503
1504 /**
1505 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1506 *
1507 * @ring: amdgpu_ring pointer
1508 * @addr: address
1509 * @seq: sequence number
1510 * @flags: fence related flags
1511 *
1512 * Write a fence and a trap command to the ring.
1513 */
vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1514 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1515 unsigned flags)
1516 {
1517 struct amdgpu_device *adev = ring->adev;
1518
1519 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1520 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0));
1521 amdgpu_ring_write(ring, seq);
1522
1523 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1524 amdgpu_ring_write(ring, addr & 0xffffffff);
1525
1526 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1527 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1528
1529 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1530 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1531
1532 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1533 amdgpu_ring_write(ring, 0);
1534
1535 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1536 amdgpu_ring_write(ring, 0);
1537
1538 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1539
1540 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1541 }
1542
1543 /**
1544 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1545 *
1546 * @ring: amdgpu_ring pointer
1547 * @job: job to retrieve vmid from
1548 * @ib: indirect buffer to execute
1549 * @flags: unused
1550 *
1551 * Write ring commands to execute the indirect buffer
1552 */
vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1553 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1554 struct amdgpu_job *job,
1555 struct amdgpu_ib *ib,
1556 uint32_t flags)
1557 {
1558 struct amdgpu_device *adev = ring->adev;
1559 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1560
1561 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0));
1562 amdgpu_ring_write(ring, vmid);
1563
1564 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0));
1565 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1566 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0));
1567 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1568 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0));
1569 amdgpu_ring_write(ring, ib->length_dw);
1570 }
1571
vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1572 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1573 uint32_t val, uint32_t mask)
1574 {
1575 struct amdgpu_device *adev = ring->adev;
1576
1577 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1578 amdgpu_ring_write(ring, reg << 2);
1579
1580 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1581 amdgpu_ring_write(ring, val);
1582
1583 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0));
1584 amdgpu_ring_write(ring, mask);
1585
1586 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1587
1588 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1589 }
1590
vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1591 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1592 unsigned vmid, uint64_t pd_addr)
1593 {
1594 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1595 uint32_t data0, data1, mask;
1596
1597 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1598
1599 /* wait for register write */
1600 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1601 data1 = lower_32_bits(pd_addr);
1602 mask = 0xffffffff;
1603 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1604 }
1605
vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1606 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1607 uint32_t reg, uint32_t val)
1608 {
1609 struct amdgpu_device *adev = ring->adev;
1610
1611 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1612 amdgpu_ring_write(ring, reg << 2);
1613
1614 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1615 amdgpu_ring_write(ring, val);
1616
1617 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1618
1619 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1620 }
1621
1622 /**
1623 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1624 *
1625 * @ring: amdgpu_ring pointer
1626 *
1627 * Returns the current hardware enc read pointer
1628 */
vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1629 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1630 {
1631 struct amdgpu_device *adev = ring->adev;
1632
1633 if (ring == &adev->vcn.inst->ring_enc[0])
1634 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1635 else
1636 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1637 }
1638
1639 /**
1640 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1641 *
1642 * @ring: amdgpu_ring pointer
1643 *
1644 * Returns the current hardware enc write pointer
1645 */
vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1646 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1647 {
1648 struct amdgpu_device *adev = ring->adev;
1649
1650 if (ring == &adev->vcn.inst->ring_enc[0]) {
1651 if (ring->use_doorbell)
1652 return *ring->wptr_cpu_addr;
1653 else
1654 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1655 } else {
1656 if (ring->use_doorbell)
1657 return *ring->wptr_cpu_addr;
1658 else
1659 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1660 }
1661 }
1662
1663 /**
1664 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1665 *
1666 * @ring: amdgpu_ring pointer
1667 *
1668 * Commits the enc write pointer to the hardware
1669 */
vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1670 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1671 {
1672 struct amdgpu_device *adev = ring->adev;
1673
1674 if (ring == &adev->vcn.inst->ring_enc[0]) {
1675 if (ring->use_doorbell) {
1676 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1677 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1678 } else {
1679 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1680 }
1681 } else {
1682 if (ring->use_doorbell) {
1683 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1684 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1685 } else {
1686 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1687 }
1688 }
1689 }
1690
1691 /**
1692 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1693 *
1694 * @ring: amdgpu_ring pointer
1695 * @addr: address
1696 * @seq: sequence number
1697 * @flags: fence related flags
1698 *
1699 * Write enc a fence and a trap command to the ring.
1700 */
vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1701 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1702 u64 seq, unsigned flags)
1703 {
1704 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1705
1706 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1707 amdgpu_ring_write(ring, addr);
1708 amdgpu_ring_write(ring, upper_32_bits(addr));
1709 amdgpu_ring_write(ring, seq);
1710 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1711 }
1712
vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring * ring)1713 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1714 {
1715 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1716 }
1717
1718 /**
1719 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1720 *
1721 * @ring: amdgpu_ring pointer
1722 * @job: job to retrive vmid from
1723 * @ib: indirect buffer to execute
1724 * @flags: unused
1725 *
1726 * Write enc ring commands to execute the indirect buffer
1727 */
vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1728 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1729 struct amdgpu_job *job,
1730 struct amdgpu_ib *ib,
1731 uint32_t flags)
1732 {
1733 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1734
1735 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1736 amdgpu_ring_write(ring, vmid);
1737 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1738 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1739 amdgpu_ring_write(ring, ib->length_dw);
1740 }
1741
vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1742 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1743 uint32_t val, uint32_t mask)
1744 {
1745 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1746 amdgpu_ring_write(ring, reg << 2);
1747 amdgpu_ring_write(ring, mask);
1748 amdgpu_ring_write(ring, val);
1749 }
1750
vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1751 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1752 unsigned int vmid, uint64_t pd_addr)
1753 {
1754 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1755
1756 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1757
1758 /* wait for reg writes */
1759 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1760 vmid * hub->ctx_addr_distance,
1761 lower_32_bits(pd_addr), 0xffffffff);
1762 }
1763
vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1764 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1765 {
1766 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1767 amdgpu_ring_write(ring, reg << 2);
1768 amdgpu_ring_write(ring, val);
1769 }
1770
vcn_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1771 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1772 struct amdgpu_irq_src *source,
1773 unsigned type,
1774 enum amdgpu_interrupt_state state)
1775 {
1776 return 0;
1777 }
1778
vcn_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1779 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1780 struct amdgpu_irq_src *source,
1781 struct amdgpu_iv_entry *entry)
1782 {
1783 DRM_DEBUG("IH: VCN TRAP\n");
1784
1785 switch (entry->src_id) {
1786 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1787 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1788 break;
1789 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1790 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1791 break;
1792 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1793 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1794 break;
1795 default:
1796 DRM_ERROR("Unhandled interrupt: %d %d\n",
1797 entry->src_id, entry->src_data[0]);
1798 break;
1799 }
1800
1801 return 0;
1802 }
1803
vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring * ring)1804 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1805 {
1806 struct amdgpu_device *adev = ring->adev;
1807 uint32_t tmp = 0;
1808 unsigned i;
1809 int r;
1810
1811 if (amdgpu_sriov_vf(adev))
1812 return 0;
1813
1814 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1815 r = amdgpu_ring_alloc(ring, 4);
1816 if (r)
1817 return r;
1818 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1819 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1820 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));
1821 amdgpu_ring_write(ring, 0xDEADBEEF);
1822 amdgpu_ring_commit(ring);
1823 for (i = 0; i < adev->usec_timeout; i++) {
1824 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1825 if (tmp == 0xDEADBEEF)
1826 break;
1827 udelay(1);
1828 }
1829
1830 if (i >= adev->usec_timeout)
1831 r = -ETIMEDOUT;
1832
1833 return r;
1834 }
1835
1836
vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst * vinst,enum amd_powergating_state state)1837 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
1838 enum amd_powergating_state state)
1839 {
1840 /* This doesn't actually powergate the VCN block.
1841 * That's done in the dpm code via the SMC. This
1842 * just re-inits the block as necessary. The actual
1843 * gating still happens in the dpm code. We should
1844 * revisit this when there is a cleaner line between
1845 * the smc and the hw blocks
1846 */
1847 int ret;
1848 struct amdgpu_device *adev = vinst->adev;
1849
1850 if (amdgpu_sriov_vf(adev)) {
1851 vinst->cur_state = AMD_PG_STATE_UNGATE;
1852 return 0;
1853 }
1854
1855 if (state == vinst->cur_state)
1856 return 0;
1857
1858 if (state == AMD_PG_STATE_GATE)
1859 ret = vcn_v2_0_stop(vinst);
1860 else
1861 ret = vcn_v2_0_start(vinst);
1862
1863 if (!ret)
1864 vinst->cur_state = state;
1865
1866 return ret;
1867 }
1868
vcn_v2_0_start_mmsch(struct amdgpu_device * adev,struct amdgpu_mm_table * table)1869 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1870 struct amdgpu_mm_table *table)
1871 {
1872 uint32_t data = 0, loop;
1873 uint64_t addr = table->gpu_addr;
1874 struct mmsch_v2_0_init_header *header;
1875 uint32_t size;
1876 int i;
1877
1878 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1879 size = header->header_size + header->vcn_table_size;
1880
1881 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1882 * of memory descriptor location
1883 */
1884 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1885 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1886
1887 /* 2, update vmid of descriptor */
1888 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1889 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1890 /* use domain0 for MM scheduler */
1891 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1892 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1893
1894 /* 3, notify mmsch about the size of this descriptor */
1895 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1896
1897 /* 4, set resp to zero */
1898 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1899
1900 adev->vcn.inst->ring_dec.wptr = 0;
1901 adev->vcn.inst->ring_dec.wptr_old = 0;
1902 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1903
1904 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
1905 adev->vcn.inst->ring_enc[i].wptr = 0;
1906 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1907 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1908 }
1909
1910 /* 5, kick off the initialization and wait until
1911 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1912 */
1913 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1914
1915 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1916 loop = 1000;
1917 while ((data & 0x10000002) != 0x10000002) {
1918 udelay(10);
1919 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1920 loop--;
1921 if (!loop)
1922 break;
1923 }
1924
1925 if (!loop) {
1926 DRM_ERROR("failed to init MMSCH, " \
1927 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1928 return -EBUSY;
1929 }
1930
1931 return 0;
1932 }
1933
vcn_v2_0_start_sriov(struct amdgpu_device * adev)1934 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1935 {
1936 int r;
1937 uint32_t tmp;
1938 struct amdgpu_ring *ring;
1939 uint32_t offset, size;
1940 uint32_t table_size = 0;
1941 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1942 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1943 struct mmsch_v2_0_cmd_end end = { {0} };
1944 struct mmsch_v2_0_init_header *header;
1945 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1946 uint8_t i = 0;
1947
1948 header = (struct mmsch_v2_0_init_header *)init_table;
1949 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1950 direct_rd_mod_wt.cmd_header.command_type =
1951 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1952 end.cmd_header.command_type = MMSCH_COMMAND__END;
1953
1954 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1955 header->version = MMSCH_VERSION;
1956 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1957
1958 header->vcn_table_offset = header->header_size;
1959
1960 init_table += header->vcn_table_offset;
1961
1962 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
1963
1964 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1965 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1966 0xFFFFFFFF, 0x00000004);
1967
1968 /* mc resume*/
1969 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1970 MMSCH_V2_0_INSERT_DIRECT_WT(
1971 SOC15_REG_OFFSET(UVD, i,
1972 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1973 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);
1974 MMSCH_V2_0_INSERT_DIRECT_WT(
1975 SOC15_REG_OFFSET(UVD, i,
1976 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1977 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);
1978 offset = 0;
1979 } else {
1980 MMSCH_V2_0_INSERT_DIRECT_WT(
1981 SOC15_REG_OFFSET(UVD, i,
1982 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1983 lower_32_bits(adev->vcn.inst->gpu_addr));
1984 MMSCH_V2_0_INSERT_DIRECT_WT(
1985 SOC15_REG_OFFSET(UVD, i,
1986 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1987 upper_32_bits(adev->vcn.inst->gpu_addr));
1988 offset = size;
1989 }
1990
1991 MMSCH_V2_0_INSERT_DIRECT_WT(
1992 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1993 0);
1994 MMSCH_V2_0_INSERT_DIRECT_WT(
1995 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1996 size);
1997
1998 MMSCH_V2_0_INSERT_DIRECT_WT(
1999 SOC15_REG_OFFSET(UVD, i,
2000 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
2001 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
2002 MMSCH_V2_0_INSERT_DIRECT_WT(
2003 SOC15_REG_OFFSET(UVD, i,
2004 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
2005 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
2006 MMSCH_V2_0_INSERT_DIRECT_WT(
2007 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
2008 0);
2009 MMSCH_V2_0_INSERT_DIRECT_WT(
2010 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
2011 AMDGPU_VCN_STACK_SIZE);
2012
2013 MMSCH_V2_0_INSERT_DIRECT_WT(
2014 SOC15_REG_OFFSET(UVD, i,
2015 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
2016 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
2017 AMDGPU_VCN_STACK_SIZE));
2018 MMSCH_V2_0_INSERT_DIRECT_WT(
2019 SOC15_REG_OFFSET(UVD, i,
2020 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
2021 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
2022 AMDGPU_VCN_STACK_SIZE));
2023 MMSCH_V2_0_INSERT_DIRECT_WT(
2024 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
2025 0);
2026 MMSCH_V2_0_INSERT_DIRECT_WT(
2027 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
2028 AMDGPU_VCN_CONTEXT_SIZE);
2029
2030 for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) {
2031 ring = &adev->vcn.inst->ring_enc[r];
2032 ring->wptr = 0;
2033 MMSCH_V2_0_INSERT_DIRECT_WT(
2034 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
2035 lower_32_bits(ring->gpu_addr));
2036 MMSCH_V2_0_INSERT_DIRECT_WT(
2037 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
2038 upper_32_bits(ring->gpu_addr));
2039 MMSCH_V2_0_INSERT_DIRECT_WT(
2040 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
2041 ring->ring_size / 4);
2042 }
2043
2044 ring = &adev->vcn.inst->ring_dec;
2045 ring->wptr = 0;
2046 MMSCH_V2_0_INSERT_DIRECT_WT(
2047 SOC15_REG_OFFSET(UVD, i,
2048 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
2049 lower_32_bits(ring->gpu_addr));
2050 MMSCH_V2_0_INSERT_DIRECT_WT(
2051 SOC15_REG_OFFSET(UVD, i,
2052 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
2053 upper_32_bits(ring->gpu_addr));
2054 /* force RBC into idle state */
2055 tmp = order_base_2(ring->ring_size);
2056 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
2057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
2058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
2059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
2060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
2061 MMSCH_V2_0_INSERT_DIRECT_WT(
2062 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
2063
2064 /* add end packet */
2065 tmp = sizeof(struct mmsch_v2_0_cmd_end);
2066 memcpy((void *)init_table, &end, tmp);
2067 table_size += (tmp / 4);
2068 header->vcn_table_size = table_size;
2069
2070 }
2071 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
2072 }
2073
vcn_v2_0_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)2074 static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2075 {
2076 struct amdgpu_device *adev = ip_block->adev;
2077 int i, j;
2078 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
2079 uint32_t inst_off, is_powered;
2080
2081 if (!adev->vcn.ip_dump)
2082 return;
2083
2084 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
2085 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2086 if (adev->vcn.harvest_config & (1 << i)) {
2087 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
2088 continue;
2089 }
2090
2091 inst_off = i * reg_count;
2092 is_powered = (adev->vcn.ip_dump[inst_off] &
2093 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2094
2095 if (is_powered) {
2096 drm_printf(p, "\nActive Instance:VCN%d\n", i);
2097 for (j = 0; j < reg_count; j++)
2098 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
2099 adev->vcn.ip_dump[inst_off + j]);
2100 } else {
2101 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
2102 }
2103 }
2104 }
2105
vcn_v2_0_dump_ip_state(struct amdgpu_ip_block * ip_block)2106 static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
2107 {
2108 struct amdgpu_device *adev = ip_block->adev;
2109 int i, j;
2110 bool is_powered;
2111 uint32_t inst_off;
2112 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
2113
2114 if (!adev->vcn.ip_dump)
2115 return;
2116
2117 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2118 if (adev->vcn.harvest_config & (1 << i))
2119 continue;
2120
2121 inst_off = i * reg_count;
2122 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
2123 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
2124 is_powered = (adev->vcn.ip_dump[inst_off] &
2125 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2126
2127 if (is_powered)
2128 for (j = 1; j < reg_count; j++)
2129 adev->vcn.ip_dump[inst_off + j] =
2130 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
2131 }
2132 }
2133
2134 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
2135 .name = "vcn_v2_0",
2136 .early_init = vcn_v2_0_early_init,
2137 .sw_init = vcn_v2_0_sw_init,
2138 .sw_fini = vcn_v2_0_sw_fini,
2139 .hw_init = vcn_v2_0_hw_init,
2140 .hw_fini = vcn_v2_0_hw_fini,
2141 .suspend = vcn_v2_0_suspend,
2142 .resume = vcn_v2_0_resume,
2143 .is_idle = vcn_v2_0_is_idle,
2144 .wait_for_idle = vcn_v2_0_wait_for_idle,
2145 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
2146 .set_powergating_state = vcn_set_powergating_state,
2147 .dump_ip_state = vcn_v2_0_dump_ip_state,
2148 .print_ip_state = vcn_v2_0_print_ip_state,
2149 };
2150
2151 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2152 .type = AMDGPU_RING_TYPE_VCN_DEC,
2153 .align_mask = 0xf,
2154 .secure_submission_supported = true,
2155 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2156 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2157 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2158 .emit_frame_size =
2159 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2160 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2161 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2162 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2163 6,
2164 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2165 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2166 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2167 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2168 .test_ring = vcn_v2_0_dec_ring_test_ring,
2169 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2170 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2171 .insert_start = vcn_v2_0_dec_ring_insert_start,
2172 .insert_end = vcn_v2_0_dec_ring_insert_end,
2173 .pad_ib = amdgpu_ring_generic_pad_ib,
2174 .begin_use = amdgpu_vcn_ring_begin_use,
2175 .end_use = amdgpu_vcn_ring_end_use,
2176 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2177 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2178 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2179 };
2180
2181 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2182 .type = AMDGPU_RING_TYPE_VCN_ENC,
2183 .align_mask = 0x3f,
2184 .nop = VCN_ENC_CMD_NO_OP,
2185 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2186 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2187 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2188 .emit_frame_size =
2189 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2190 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2191 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2192 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2193 1, /* vcn_v2_0_enc_ring_insert_end */
2194 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2195 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2196 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2197 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2198 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2199 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2200 .insert_nop = amdgpu_ring_insert_nop,
2201 .insert_end = vcn_v2_0_enc_ring_insert_end,
2202 .pad_ib = amdgpu_ring_generic_pad_ib,
2203 .begin_use = amdgpu_vcn_ring_begin_use,
2204 .end_use = amdgpu_vcn_ring_end_use,
2205 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2206 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2207 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2208 };
2209
vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)2210 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2211 {
2212 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
2213 }
2214
vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device * adev)2215 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2216 {
2217 int i;
2218
2219 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
2220 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2221 }
2222
2223 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2224 .set = vcn_v2_0_set_interrupt_state,
2225 .process = vcn_v2_0_process_interrupt,
2226 };
2227
vcn_v2_0_set_irq_funcs(struct amdgpu_device * adev)2228 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2229 {
2230 adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1;
2231 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2232 }
2233
2234 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2235 {
2236 .type = AMD_IP_BLOCK_TYPE_VCN,
2237 .major = 2,
2238 .minor = 0,
2239 .rev = 0,
2240 .funcs = &vcn_v2_0_ip_funcs,
2241 };
2242