1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drm_drv.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_vcn.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "amdgpu_pm.h"
32 #include "amdgpu_psp.h"
33 #include "mmsch_v2_0.h"
34 #include "vcn_v2_0.h"
35
36 #include "vcn/vcn_2_0_0_offset.h"
37 #include "vcn/vcn_2_0_0_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39
40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
42 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000
43
44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
51
52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
56
57 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
91 };
92
93 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
94 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
95 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
96 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
97 enum amd_powergating_state state);
98 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
99 struct dpg_pause_state *new_state);
100 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
101 static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst);
102
103 /**
104 * vcn_v2_0_early_init - set function pointers and load microcode
105 *
106 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
107 *
108 * Set ring and irq function pointers
109 * Load microcode from filesystem
110 */
vcn_v2_0_early_init(struct amdgpu_ip_block * ip_block)111 static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
112 {
113 struct amdgpu_device *adev = ip_block->adev;
114
115 if (amdgpu_sriov_vf(adev))
116 adev->vcn.inst[0].num_enc_rings = 1;
117 else
118 adev->vcn.inst[0].num_enc_rings = 2;
119
120 adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state;
121 vcn_v2_0_set_dec_ring_funcs(adev);
122 vcn_v2_0_set_enc_ring_funcs(adev);
123 vcn_v2_0_set_irq_funcs(adev);
124
125 return amdgpu_vcn_early_init(adev, 0);
126 }
127
128 /**
129 * vcn_v2_0_sw_init - sw init for VCN block
130 *
131 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
132 *
133 * Load firmware and sw initialization
134 */
vcn_v2_0_sw_init(struct amdgpu_ip_block * ip_block)135 static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
136 {
137 struct amdgpu_ring *ring;
138 int i, r;
139 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
140 uint32_t *ptr;
141 struct amdgpu_device *adev = ip_block->adev;
142 volatile struct amdgpu_fw_shared *fw_shared;
143
144 /* VCN DEC TRAP */
145 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
146 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
147 &adev->vcn.inst->irq);
148 if (r)
149 return r;
150
151 /* VCN ENC TRAP */
152 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
153 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
154 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
155 &adev->vcn.inst->irq);
156 if (r)
157 return r;
158 }
159
160 r = amdgpu_vcn_sw_init(adev, 0);
161 if (r)
162 return r;
163
164 amdgpu_vcn_setup_ucode(adev, 0);
165
166 r = amdgpu_vcn_resume(adev, 0);
167 if (r)
168 return r;
169
170 ring = &adev->vcn.inst->ring_dec;
171
172 ring->use_doorbell = true;
173 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
174 ring->vm_hub = AMDGPU_MMHUB0(0);
175
176 sprintf(ring->name, "vcn_dec");
177 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
178 AMDGPU_RING_PRIO_DEFAULT, NULL);
179 if (r)
180 return r;
181
182 adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
183 adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
184 adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
185 adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
186 adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
187 adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
188
189 adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
190 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
191 adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
192 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
193 adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
194 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
195 adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
196 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
197 adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
198 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
199
200 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
201 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
202
203 ring = &adev->vcn.inst->ring_enc[i];
204 ring->use_doorbell = true;
205 ring->vm_hub = AMDGPU_MMHUB0(0);
206 if (!amdgpu_sriov_vf(adev))
207 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
208 else
209 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
210 sprintf(ring->name, "vcn_enc%d", i);
211 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
212 hw_prio, NULL);
213 if (r)
214 return r;
215 }
216
217 adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
218 adev->vcn.inst[0].reset = vcn_v2_0_reset;
219
220 adev->vcn.supported_reset =
221 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
222 if (!amdgpu_sriov_vf(adev))
223 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
224
225 r = amdgpu_virt_alloc_mm_table(adev);
226 if (r)
227 return r;
228
229 fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
230 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
231
232 if (amdgpu_vcnfw_log)
233 amdgpu_vcn_fwlog_init(adev->vcn.inst);
234
235 /* Allocate memory for VCN IP Dump buffer */
236 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
237 if (!ptr) {
238 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
239 adev->vcn.ip_dump = NULL;
240 } else {
241 adev->vcn.ip_dump = ptr;
242 }
243
244 r = amdgpu_vcn_sysfs_reset_mask_init(adev);
245 if (r)
246 return r;
247
248 return 0;
249 }
250
251 /**
252 * vcn_v2_0_sw_fini - sw fini for VCN block
253 *
254 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
255 *
256 * VCN suspend and free up sw allocation
257 */
vcn_v2_0_sw_fini(struct amdgpu_ip_block * ip_block)258 static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
259 {
260 int r, idx;
261 struct amdgpu_device *adev = ip_block->adev;
262 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
263
264 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
265 fw_shared->present_flag_0 = 0;
266 drm_dev_exit(idx);
267 }
268
269 amdgpu_virt_free_mm_table(adev);
270
271 r = amdgpu_vcn_suspend(adev, 0);
272 if (r)
273 return r;
274
275 amdgpu_vcn_sysfs_reset_mask_fini(adev);
276
277 r = amdgpu_vcn_sw_fini(adev, 0);
278
279 kfree(adev->vcn.ip_dump);
280
281 return r;
282 }
283
284 /**
285 * vcn_v2_0_hw_init - start and test VCN block
286 *
287 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
288 *
289 * Initialize the hardware, boot up the VCPU and do some testing
290 */
vcn_v2_0_hw_init(struct amdgpu_ip_block * ip_block)291 static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block)
292 {
293 struct amdgpu_device *adev = ip_block->adev;
294 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
295 int i, r;
296
297 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
298 ring->doorbell_index, 0);
299
300 if (amdgpu_sriov_vf(adev))
301 vcn_v2_0_start_sriov(adev);
302
303 r = amdgpu_ring_test_helper(ring);
304 if (r)
305 return r;
306
307 //Disable vcn decode for sriov
308 if (amdgpu_sriov_vf(adev))
309 ring->sched.ready = false;
310
311 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
312 ring = &adev->vcn.inst->ring_enc[i];
313 r = amdgpu_ring_test_helper(ring);
314 if (r)
315 return r;
316 }
317
318 return 0;
319 }
320
321 /**
322 * vcn_v2_0_hw_fini - stop the hardware block
323 *
324 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
325 *
326 * Stop the VCN block, mark ring as not ready any more
327 */
vcn_v2_0_hw_fini(struct amdgpu_ip_block * ip_block)328 static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
329 {
330 struct amdgpu_device *adev = ip_block->adev;
331 struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
332
333 cancel_delayed_work_sync(&vinst->idle_work);
334
335 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
336 (vinst->cur_state != AMD_PG_STATE_GATE &&
337 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
338 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE);
339
340 return 0;
341 }
342
343 /**
344 * vcn_v2_0_suspend - suspend VCN block
345 *
346 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
347 *
348 * HW fini and suspend VCN block
349 */
vcn_v2_0_suspend(struct amdgpu_ip_block * ip_block)350 static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block)
351 {
352 int r;
353
354 r = vcn_v2_0_hw_fini(ip_block);
355 if (r)
356 return r;
357
358 r = amdgpu_vcn_suspend(ip_block->adev, 0);
359
360 return r;
361 }
362
363 /**
364 * vcn_v2_0_resume - resume VCN block
365 *
366 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
367 *
368 * Resume firmware and hw init VCN block
369 */
vcn_v2_0_resume(struct amdgpu_ip_block * ip_block)370 static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
371 {
372 int r;
373
374 r = amdgpu_vcn_resume(ip_block->adev, 0);
375 if (r)
376 return r;
377
378 r = vcn_v2_0_hw_init(ip_block);
379
380 return r;
381 }
382
383 /**
384 * vcn_v2_0_mc_resume - memory controller programming
385 *
386 * @vinst: Pointer to the VCN instance structure
387 *
388 * Let the VCN memory controller know it's offsets
389 */
vcn_v2_0_mc_resume(struct amdgpu_vcn_inst * vinst)390 static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst)
391 {
392 struct amdgpu_device *adev = vinst->adev;
393 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
394 uint32_t offset;
395
396 if (amdgpu_sriov_vf(adev))
397 return;
398
399 /* cache window 0: fw */
400 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
401 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
402 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
403 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
404 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
405 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
406 offset = 0;
407 } else {
408 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
409 lower_32_bits(adev->vcn.inst->gpu_addr));
410 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
411 upper_32_bits(adev->vcn.inst->gpu_addr));
412 offset = size;
413 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
414 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
415 }
416
417 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
418
419 /* cache window 1: stack */
420 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
421 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
422 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
423 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
424 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
425 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
426
427 /* cache window 2: context */
428 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
429 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
430 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
431 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
432 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
433 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
434
435 /* non-cache window */
436 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
437 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
438 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
439 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
440 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
441 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
442 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
443
444 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
445 }
446
vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)447 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
448 bool indirect)
449 {
450 struct amdgpu_device *adev = vinst->adev;
451 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
452 uint32_t offset;
453
454 /* cache window 0: fw */
455 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
456 if (!indirect) {
457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
458 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
459 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
461 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
462 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
463 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
464 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
465 } else {
466 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
467 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
468 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
469 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
470 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
471 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
472 }
473 offset = 0;
474 } else {
475 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
476 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
477 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
478 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
479 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
480 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
481 offset = size;
482 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
483 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
484 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
485 }
486
487 if (!indirect)
488 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
489 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
490 else
491 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
492 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
493
494 /* cache window 1: stack */
495 if (!indirect) {
496 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
497 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
498 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
499 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
500 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
501 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
502 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
503 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
504 } else {
505 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
506 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
507 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
508 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
509 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
510 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
511 }
512 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
513 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
514
515 /* cache window 2: context */
516 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
517 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
518 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
519 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
520 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
521 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
522 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
523 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
524 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
525 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
526
527 /* non-cache window */
528 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
529 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
530 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
531 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
532 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
533 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
534 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
535 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
536 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
537 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
538 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
539
540 /* VCN global tiling registers */
541 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
542 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
543 }
544
545 /**
546 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
547 *
548 * @vinst: VCN instance
549 *
550 * Disable clock gating for VCN block
551 */
vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst * vinst)552 static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
553 {
554 struct amdgpu_device *adev = vinst->adev;
555 uint32_t data;
556
557 if (amdgpu_sriov_vf(adev))
558 return;
559
560 /* UVD disable CGC */
561 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
562 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
563 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
564 else
565 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
566 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
567 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
568 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
569
570 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
571 data &= ~(UVD_CGC_GATE__SYS_MASK
572 | UVD_CGC_GATE__UDEC_MASK
573 | UVD_CGC_GATE__MPEG2_MASK
574 | UVD_CGC_GATE__REGS_MASK
575 | UVD_CGC_GATE__RBC_MASK
576 | UVD_CGC_GATE__LMI_MC_MASK
577 | UVD_CGC_GATE__LMI_UMC_MASK
578 | UVD_CGC_GATE__IDCT_MASK
579 | UVD_CGC_GATE__MPRD_MASK
580 | UVD_CGC_GATE__MPC_MASK
581 | UVD_CGC_GATE__LBSI_MASK
582 | UVD_CGC_GATE__LRBBM_MASK
583 | UVD_CGC_GATE__UDEC_RE_MASK
584 | UVD_CGC_GATE__UDEC_CM_MASK
585 | UVD_CGC_GATE__UDEC_IT_MASK
586 | UVD_CGC_GATE__UDEC_DB_MASK
587 | UVD_CGC_GATE__UDEC_MP_MASK
588 | UVD_CGC_GATE__WCB_MASK
589 | UVD_CGC_GATE__VCPU_MASK
590 | UVD_CGC_GATE__SCPU_MASK);
591 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
592
593 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
594 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
595 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
596 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
597 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
598 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
599 | UVD_CGC_CTRL__SYS_MODE_MASK
600 | UVD_CGC_CTRL__UDEC_MODE_MASK
601 | UVD_CGC_CTRL__MPEG2_MODE_MASK
602 | UVD_CGC_CTRL__REGS_MODE_MASK
603 | UVD_CGC_CTRL__RBC_MODE_MASK
604 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
605 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
606 | UVD_CGC_CTRL__IDCT_MODE_MASK
607 | UVD_CGC_CTRL__MPRD_MODE_MASK
608 | UVD_CGC_CTRL__MPC_MODE_MASK
609 | UVD_CGC_CTRL__LBSI_MODE_MASK
610 | UVD_CGC_CTRL__LRBBM_MODE_MASK
611 | UVD_CGC_CTRL__WCB_MODE_MASK
612 | UVD_CGC_CTRL__VCPU_MODE_MASK
613 | UVD_CGC_CTRL__SCPU_MODE_MASK);
614 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
615
616 /* turn on */
617 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
618 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
619 | UVD_SUVD_CGC_GATE__SIT_MASK
620 | UVD_SUVD_CGC_GATE__SMP_MASK
621 | UVD_SUVD_CGC_GATE__SCM_MASK
622 | UVD_SUVD_CGC_GATE__SDB_MASK
623 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
624 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
625 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
626 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
627 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
628 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
629 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
630 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
631 | UVD_SUVD_CGC_GATE__SCLR_MASK
632 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
633 | UVD_SUVD_CGC_GATE__ENT_MASK
634 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
635 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
636 | UVD_SUVD_CGC_GATE__SITE_MASK
637 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
638 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
639 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
640 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
641 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
642 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
643
644 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
645 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
646 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
647 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
648 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
649 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
650 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
651 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
652 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
653 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
654 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
655 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
656 }
657
vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst * vinst,uint8_t sram_sel,uint8_t indirect)658 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
659 uint8_t sram_sel, uint8_t indirect)
660 {
661 struct amdgpu_device *adev = vinst->adev;
662 uint32_t reg_data = 0;
663
664 /* enable sw clock gating control */
665 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
666 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
667 else
668 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
669 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
670 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
671 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
672 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
673 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
674 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
675 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
676 UVD_CGC_CTRL__SYS_MODE_MASK |
677 UVD_CGC_CTRL__UDEC_MODE_MASK |
678 UVD_CGC_CTRL__MPEG2_MODE_MASK |
679 UVD_CGC_CTRL__REGS_MODE_MASK |
680 UVD_CGC_CTRL__RBC_MODE_MASK |
681 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
682 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
683 UVD_CGC_CTRL__IDCT_MODE_MASK |
684 UVD_CGC_CTRL__MPRD_MODE_MASK |
685 UVD_CGC_CTRL__MPC_MODE_MASK |
686 UVD_CGC_CTRL__LBSI_MODE_MASK |
687 UVD_CGC_CTRL__LRBBM_MODE_MASK |
688 UVD_CGC_CTRL__WCB_MODE_MASK |
689 UVD_CGC_CTRL__VCPU_MODE_MASK |
690 UVD_CGC_CTRL__SCPU_MODE_MASK);
691 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
692 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
693
694 /* turn off clock gating */
695 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
696 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
697
698 /* turn on SUVD clock gating */
699 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
700 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
701
702 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
703 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
704 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
705 }
706
707 /**
708 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
709 *
710 * @vinst: VCN instance
711 *
712 * Enable clock gating for VCN block
713 */
vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst * vinst)714 static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
715 {
716 struct amdgpu_device *adev = vinst->adev;
717 uint32_t data = 0;
718
719 if (amdgpu_sriov_vf(adev))
720 return;
721
722 /* enable UVD CGC */
723 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
724 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
725 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
726 else
727 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
728 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
729 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
730 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
731
732 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
733 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
734 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
735 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
736 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
737 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
738 | UVD_CGC_CTRL__SYS_MODE_MASK
739 | UVD_CGC_CTRL__UDEC_MODE_MASK
740 | UVD_CGC_CTRL__MPEG2_MODE_MASK
741 | UVD_CGC_CTRL__REGS_MODE_MASK
742 | UVD_CGC_CTRL__RBC_MODE_MASK
743 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
744 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
745 | UVD_CGC_CTRL__IDCT_MODE_MASK
746 | UVD_CGC_CTRL__MPRD_MODE_MASK
747 | UVD_CGC_CTRL__MPC_MODE_MASK
748 | UVD_CGC_CTRL__LBSI_MODE_MASK
749 | UVD_CGC_CTRL__LRBBM_MODE_MASK
750 | UVD_CGC_CTRL__WCB_MODE_MASK
751 | UVD_CGC_CTRL__VCPU_MODE_MASK
752 | UVD_CGC_CTRL__SCPU_MODE_MASK);
753 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
754
755 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
756 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
757 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
758 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
759 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
760 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
761 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
762 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
763 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
764 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
765 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
766 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
767 }
768
vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst * vinst)769 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
770 {
771 struct amdgpu_device *adev = vinst->adev;
772 uint32_t data = 0;
773
774 if (amdgpu_sriov_vf(adev))
775 return;
776
777 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
778 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
779 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
780 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
781 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
782 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
783 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
784 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
785 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
786 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
787 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
788
789 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
790 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
791 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);
792 } else {
793 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
794 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
795 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
796 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
797 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
798 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
799 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
800 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
801 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
802 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
803 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
804 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF);
805 }
806
807 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
808 * UVDU_PWR_STATUS are 0 (power on) */
809
810 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
811 data &= ~0x103;
812 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
813 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
814 UVD_POWER_STATUS__UVD_PG_EN_MASK;
815
816 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
817 }
818
vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst * vinst)819 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
820 {
821 struct amdgpu_device *adev = vinst->adev;
822 uint32_t data = 0;
823
824 if (amdgpu_sriov_vf(adev))
825 return;
826
827 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
828 /* Before power off, this indicator has to be turned on */
829 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
830 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
831 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
832 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
833
834
835 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
836 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
837 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
838 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
839 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
840 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
841 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
842 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
843 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
844 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
845
846 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
847
848 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
849 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
850 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
851 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
852 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
853 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
854 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
855 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
856 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
857 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
858 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);
859 }
860 }
861
vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)862 static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
863 {
864 struct amdgpu_device *adev = vinst->adev;
865 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
866 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
867 uint32_t rb_bufsz, tmp;
868
869 vcn_v2_0_enable_static_power_gating(vinst);
870
871 /* enable dynamic power gating mode */
872 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
873 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
874 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
875 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
876
877 if (indirect)
878 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
879
880 /* enable clock gating */
881 vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect);
882
883 /* enable VCPU clock */
884 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
885 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
886 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
887 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
888 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
889
890 /* disable master interupt */
891 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
892 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
893
894 /* setup mmUVD_LMI_CTRL */
895 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
896 UVD_LMI_CTRL__REQ_MODE_MASK |
897 UVD_LMI_CTRL__CRC_RESET_MASK |
898 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
899 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
900 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
901 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
902 0x00100000L);
903 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
904 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
905
906 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
907 UVD, 0, mmUVD_MPC_CNTL),
908 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
909
910 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
911 UVD, 0, mmUVD_MPC_SET_MUXA0),
912 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
913 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
914 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
915 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
916
917 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
918 UVD, 0, mmUVD_MPC_SET_MUXB0),
919 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
920 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
921 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
922 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
923
924 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
925 UVD, 0, mmUVD_MPC_SET_MUX),
926 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
927 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
928 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
929
930 vcn_v2_0_mc_resume_dpg_mode(vinst, indirect);
931
932 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
933 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
934 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
935 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
936
937 /* release VCPU reset to boot */
938 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
939 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
940
941 /* enable LMI MC and UMC channels */
942 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
943 UVD, 0, mmUVD_LMI_CTRL2),
944 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
945
946 /* enable master interrupt */
947 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
948 UVD, 0, mmUVD_MASTINT_EN),
949 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
950
951 if (indirect)
952 amdgpu_vcn_psp_update_sram(adev, 0, 0);
953
954 /* force RBC into idle state */
955 rb_bufsz = order_base_2(ring->ring_size);
956 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
957 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
958 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
959 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
960 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
961 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
962
963 /* Stall DPG before WPTR/RPTR reset */
964 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
965 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
966 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
967 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
968
969 /* set the write pointer delay */
970 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
971
972 /* set the wb address */
973 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
974 (upper_32_bits(ring->gpu_addr) >> 2));
975
976 /* program the RB_BASE for ring buffer */
977 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
978 lower_32_bits(ring->gpu_addr));
979 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
980 upper_32_bits(ring->gpu_addr));
981
982 /* Initialize the ring buffer's read and write pointers */
983 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
984
985 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
986
987 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
988 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
989 lower_32_bits(ring->wptr));
990
991 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
992 /* Unstall DPG */
993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
994 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
995
996 /* Keeping one read-back to ensure all register writes are done,
997 * otherwise it may introduce race conditions.
998 */
999 RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1000
1001 return 0;
1002 }
1003
vcn_v2_0_start(struct amdgpu_vcn_inst * vinst)1004 static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
1005 {
1006 struct amdgpu_device *adev = vinst->adev;
1007 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1008 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1009 uint32_t rb_bufsz, tmp;
1010 uint32_t lmi_swap_cntl;
1011 int i, j, r;
1012
1013 if (adev->pm.dpm_enabled)
1014 amdgpu_dpm_enable_vcn(adev, true, 0);
1015
1016 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1017 return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram);
1018
1019 vcn_v2_0_disable_static_power_gating(vinst);
1020
1021 /* set uvd status busy */
1022 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1023 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
1024
1025 /*SW clock gating */
1026 vcn_v2_0_disable_clock_gating(vinst);
1027
1028 /* enable VCPU clock */
1029 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
1030 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1031
1032 /* disable master interrupt */
1033 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
1034 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1035
1036 /* setup mmUVD_LMI_CTRL */
1037 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
1038 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
1039 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1040 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1041 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1042 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1043
1044 /* setup mmUVD_MPC_CNTL */
1045 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
1046 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1047 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1048 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
1049
1050 /* setup UVD_MPC_SET_MUXA0 */
1051 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
1052 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1053 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1054 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1055 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1056
1057 /* setup UVD_MPC_SET_MUXB0 */
1058 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
1059 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1060 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1061 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1062 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1063
1064 /* setup mmUVD_MPC_SET_MUX */
1065 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
1066 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1067 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1068 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1069
1070 vcn_v2_0_mc_resume(vinst);
1071
1072 /* release VCPU reset to boot */
1073 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1074 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1075
1076 /* enable LMI MC and UMC channels */
1077 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1078 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1079
1080 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1081 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1082 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1083 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1084
1085 /* disable byte swapping */
1086 lmi_swap_cntl = 0;
1087 #ifdef __BIG_ENDIAN
1088 /* swap (8 in 32) RB and IB */
1089 lmi_swap_cntl = 0xa;
1090 #endif
1091 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1092
1093 for (i = 0; i < 10; ++i) {
1094 uint32_t status;
1095
1096 for (j = 0; j < 100; ++j) {
1097 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1098 if (status & 2)
1099 break;
1100 mdelay(10);
1101 }
1102 r = 0;
1103 if (status & 2)
1104 break;
1105
1106 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1107 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1108 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1109 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1110 mdelay(10);
1111 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1112 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1113 mdelay(10);
1114 r = -1;
1115 }
1116
1117 if (r) {
1118 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1119 return r;
1120 }
1121
1122 /* enable master interrupt */
1123 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1124 UVD_MASTINT_EN__VCPU_EN_MASK,
1125 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1126
1127 /* clear the busy bit of VCN_STATUS */
1128 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1129 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1130
1131 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1132
1133 /* force RBC into idle state */
1134 rb_bufsz = order_base_2(ring->ring_size);
1135 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1136 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1137 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1138 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1139 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1140 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1141
1142 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1143 /* program the RB_BASE for ring buffer */
1144 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1145 lower_32_bits(ring->gpu_addr));
1146 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1147 upper_32_bits(ring->gpu_addr));
1148
1149 /* Initialize the ring buffer's read and write pointers */
1150 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1151
1152 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1153 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1154 lower_32_bits(ring->wptr));
1155 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1156
1157 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1158 ring = &adev->vcn.inst->ring_enc[0];
1159 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1160 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1161 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1162 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1163 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1164 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1165
1166 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1167 ring = &adev->vcn.inst->ring_enc[1];
1168 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1169 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1170 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1171 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1172 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1173 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1174
1175 /* Keeping one read-back to ensure all register writes are done,
1176 * otherwise it may introduce race conditions.
1177 */
1178 RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1179
1180 return 0;
1181 }
1182
vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst * vinst)1183 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
1184 {
1185 struct amdgpu_device *adev = vinst->adev;
1186 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1187 uint32_t tmp;
1188
1189 vcn_v2_0_pause_dpg_mode(vinst, &state);
1190 /* Wait for power status to be 1 */
1191 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1192 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1193
1194 /* wait for read ptr to be equal to write ptr */
1195 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1196 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1197
1198 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1199 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1200
1201 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1202 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1203
1204 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1205 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1206
1207 /* disable dynamic power gating mode */
1208 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1209 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1210
1211 /* Keeping one read-back to ensure all register writes are done,
1212 * otherwise it may introduce race conditions.
1213 */
1214 RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1215
1216 return 0;
1217 }
1218
vcn_v2_0_stop(struct amdgpu_vcn_inst * vinst)1219 static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)
1220 {
1221 struct amdgpu_device *adev = vinst->adev;
1222 uint32_t tmp;
1223 int r;
1224
1225 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1226 r = vcn_v2_0_stop_dpg_mode(vinst);
1227 if (r)
1228 return r;
1229 goto power_off;
1230 }
1231
1232 /* wait for uvd idle */
1233 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1234 if (r)
1235 return r;
1236
1237 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1238 UVD_LMI_STATUS__READ_CLEAN_MASK |
1239 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1240 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1241 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1242 if (r)
1243 return r;
1244
1245 /* stall UMC channel */
1246 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1247 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1248 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1249
1250 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1251 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1252 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1253 if (r)
1254 return r;
1255
1256 /* disable VCPU clock */
1257 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1258 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1259
1260 /* reset LMI UMC */
1261 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1262 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1263 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1264
1265 /* reset LMI */
1266 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1267 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1268 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1269
1270 /* reset VCPU */
1271 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1272 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1273 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1274
1275 /* clear status */
1276 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1277
1278 vcn_v2_0_enable_clock_gating(vinst);
1279 vcn_v2_0_enable_static_power_gating(vinst);
1280
1281 /* Keeping one read-back to ensure all register writes are done,
1282 * otherwise it may introduce race conditions.
1283 */
1284 RREG32_SOC15(VCN, 0, mmUVD_STATUS);
1285
1286 power_off:
1287 if (adev->pm.dpm_enabled)
1288 amdgpu_dpm_enable_vcn(adev, false, 0);
1289
1290 return 0;
1291 }
1292
vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst * vinst,struct dpg_pause_state * new_state)1293 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
1294 struct dpg_pause_state *new_state)
1295 {
1296 struct amdgpu_device *adev = vinst->adev;
1297 int inst_idx = vinst->inst;
1298 struct amdgpu_ring *ring;
1299 uint32_t reg_data = 0;
1300 int ret_code;
1301
1302 /* pause/unpause if state is changed */
1303 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1304 DRM_DEBUG("dpg pause state changed %d -> %d",
1305 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1306 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1307 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1308
1309 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1310 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1311 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1312
1313 if (!ret_code) {
1314 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1315 /* pause DPG */
1316 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1317 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1318
1319 /* wait for ACK */
1320 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1321 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1322 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1323
1324 /* Stall DPG before WPTR/RPTR reset */
1325 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1326 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1327 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1328 /* Restore */
1329 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1330 ring = &adev->vcn.inst->ring_enc[0];
1331 ring->wptr = 0;
1332 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1333 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1334 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1335 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1336 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1337 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1338
1339 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1340 ring = &adev->vcn.inst->ring_enc[1];
1341 ring->wptr = 0;
1342 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1343 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1344 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1345 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1346 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1347 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1348
1349 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1350 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1351 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1352 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1353 /* Unstall DPG */
1354 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1355 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1356
1357 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1358 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1359 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1360 }
1361 } else {
1362 /* unpause dpg, no need to wait */
1363 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1364 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1365 }
1366 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1367 }
1368
1369 return 0;
1370 }
1371
vcn_v2_0_reset(struct amdgpu_vcn_inst * vinst)1372 static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst)
1373 {
1374 int r;
1375
1376 r = vcn_v2_0_stop(vinst);
1377 if (r)
1378 return r;
1379 return vcn_v2_0_start(vinst);
1380 }
1381
vcn_v2_0_is_idle(struct amdgpu_ip_block * ip_block)1382 static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
1383 {
1384 struct amdgpu_device *adev = ip_block->adev;
1385
1386 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1387 }
1388
vcn_v2_0_wait_for_idle(struct amdgpu_ip_block * ip_block)1389 static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1390 {
1391 struct amdgpu_device *adev = ip_block->adev;
1392 int ret;
1393
1394 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1395 UVD_STATUS__IDLE);
1396
1397 return ret;
1398 }
1399
vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1400 static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1401 enum amd_clockgating_state state)
1402 {
1403 struct amdgpu_device *adev = ip_block->adev;
1404 bool enable = (state == AMD_CG_STATE_GATE);
1405
1406 if (amdgpu_sriov_vf(adev))
1407 return 0;
1408
1409 if (enable) {
1410 /* wait for STATUS to clear */
1411 if (!vcn_v2_0_is_idle(ip_block))
1412 return -EBUSY;
1413 vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]);
1414 } else {
1415 /* disable HW gating and enable Sw gating */
1416 vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]);
1417 }
1418 return 0;
1419 }
1420
1421 /**
1422 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1423 *
1424 * @ring: amdgpu_ring pointer
1425 *
1426 * Returns the current hardware read pointer
1427 */
vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1428 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1429 {
1430 struct amdgpu_device *adev = ring->adev;
1431
1432 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1433 }
1434
1435 /**
1436 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1437 *
1438 * @ring: amdgpu_ring pointer
1439 *
1440 * Returns the current hardware write pointer
1441 */
vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1442 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1443 {
1444 struct amdgpu_device *adev = ring->adev;
1445
1446 if (ring->use_doorbell)
1447 return *ring->wptr_cpu_addr;
1448 else
1449 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1450 }
1451
1452 /**
1453 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1454 *
1455 * @ring: amdgpu_ring pointer
1456 *
1457 * Commits the write pointer to the hardware
1458 */
vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1459 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1460 {
1461 struct amdgpu_device *adev = ring->adev;
1462
1463 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1464 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1465 lower_32_bits(ring->wptr) | 0x80000000);
1466
1467 if (ring->use_doorbell) {
1468 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1469 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1470 } else {
1471 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1472 }
1473 }
1474
1475 /**
1476 * vcn_v2_0_dec_ring_insert_start - insert a start command
1477 *
1478 * @ring: amdgpu_ring pointer
1479 *
1480 * Write a start command to the ring.
1481 */
vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)1482 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1483 {
1484 struct amdgpu_device *adev = ring->adev;
1485
1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1487 amdgpu_ring_write(ring, 0);
1488 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1489 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1490 }
1491
1492 /**
1493 * vcn_v2_0_dec_ring_insert_end - insert a end command
1494 *
1495 * @ring: amdgpu_ring pointer
1496 *
1497 * Write a end command to the ring.
1498 */
vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)1499 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1500 {
1501 struct amdgpu_device *adev = ring->adev;
1502
1503 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0));
1504 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1505 }
1506
1507 /**
1508 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1509 *
1510 * @ring: amdgpu_ring pointer
1511 * @count: the number of NOP packets to insert
1512 *
1513 * Write a nop command to the ring.
1514 */
vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1515 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1516 {
1517 struct amdgpu_device *adev = ring->adev;
1518 int i;
1519
1520 WARN_ON(ring->wptr % 2 || count % 2);
1521
1522 for (i = 0; i < count / 2; i++) {
1523 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0));
1524 amdgpu_ring_write(ring, 0);
1525 }
1526 }
1527
1528 /**
1529 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1530 *
1531 * @ring: amdgpu_ring pointer
1532 * @addr: address
1533 * @seq: sequence number
1534 * @flags: fence related flags
1535 *
1536 * Write a fence and a trap command to the ring.
1537 */
vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1538 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1539 unsigned flags)
1540 {
1541 struct amdgpu_device *adev = ring->adev;
1542
1543 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1544 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0));
1545 amdgpu_ring_write(ring, seq);
1546
1547 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1548 amdgpu_ring_write(ring, addr & 0xffffffff);
1549
1550 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1551 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1552
1553 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1554 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1555
1556 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1557 amdgpu_ring_write(ring, 0);
1558
1559 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1560 amdgpu_ring_write(ring, 0);
1561
1562 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1563
1564 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1565 }
1566
1567 /**
1568 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1569 *
1570 * @ring: amdgpu_ring pointer
1571 * @job: job to retrieve vmid from
1572 * @ib: indirect buffer to execute
1573 * @flags: unused
1574 *
1575 * Write ring commands to execute the indirect buffer
1576 */
vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1577 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1578 struct amdgpu_job *job,
1579 struct amdgpu_ib *ib,
1580 uint32_t flags)
1581 {
1582 struct amdgpu_device *adev = ring->adev;
1583 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1584
1585 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0));
1586 amdgpu_ring_write(ring, vmid);
1587
1588 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0));
1589 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1590 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0));
1591 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1592 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0));
1593 amdgpu_ring_write(ring, ib->length_dw);
1594 }
1595
vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1596 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1597 uint32_t val, uint32_t mask)
1598 {
1599 struct amdgpu_device *adev = ring->adev;
1600
1601 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1602 amdgpu_ring_write(ring, reg << 2);
1603
1604 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1605 amdgpu_ring_write(ring, val);
1606
1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0));
1608 amdgpu_ring_write(ring, mask);
1609
1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1611
1612 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1613 }
1614
vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1615 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1616 unsigned vmid, uint64_t pd_addr)
1617 {
1618 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1619 uint32_t data0, data1, mask;
1620
1621 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1622
1623 /* wait for register write */
1624 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1625 data1 = lower_32_bits(pd_addr);
1626 mask = 0xffffffff;
1627 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1628 }
1629
vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1630 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1631 uint32_t reg, uint32_t val)
1632 {
1633 struct amdgpu_device *adev = ring->adev;
1634
1635 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1636 amdgpu_ring_write(ring, reg << 2);
1637
1638 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1639 amdgpu_ring_write(ring, val);
1640
1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1642
1643 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1644 }
1645
1646 /**
1647 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1648 *
1649 * @ring: amdgpu_ring pointer
1650 *
1651 * Returns the current hardware enc read pointer
1652 */
vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1653 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1654 {
1655 struct amdgpu_device *adev = ring->adev;
1656
1657 if (ring == &adev->vcn.inst->ring_enc[0])
1658 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1659 else
1660 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1661 }
1662
1663 /**
1664 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1665 *
1666 * @ring: amdgpu_ring pointer
1667 *
1668 * Returns the current hardware enc write pointer
1669 */
vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1670 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1671 {
1672 struct amdgpu_device *adev = ring->adev;
1673
1674 if (ring == &adev->vcn.inst->ring_enc[0]) {
1675 if (ring->use_doorbell)
1676 return *ring->wptr_cpu_addr;
1677 else
1678 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1679 } else {
1680 if (ring->use_doorbell)
1681 return *ring->wptr_cpu_addr;
1682 else
1683 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1684 }
1685 }
1686
1687 /**
1688 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1689 *
1690 * @ring: amdgpu_ring pointer
1691 *
1692 * Commits the enc write pointer to the hardware
1693 */
vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1694 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1695 {
1696 struct amdgpu_device *adev = ring->adev;
1697
1698 if (ring == &adev->vcn.inst->ring_enc[0]) {
1699 if (ring->use_doorbell) {
1700 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1701 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1702 } else {
1703 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1704 }
1705 } else {
1706 if (ring->use_doorbell) {
1707 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1708 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1709 } else {
1710 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1711 }
1712 }
1713 }
1714
1715 /**
1716 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1717 *
1718 * @ring: amdgpu_ring pointer
1719 * @addr: address
1720 * @seq: sequence number
1721 * @flags: fence related flags
1722 *
1723 * Write enc a fence and a trap command to the ring.
1724 */
vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1725 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1726 u64 seq, unsigned flags)
1727 {
1728 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1729
1730 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1731 amdgpu_ring_write(ring, addr);
1732 amdgpu_ring_write(ring, upper_32_bits(addr));
1733 amdgpu_ring_write(ring, seq);
1734 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1735 }
1736
vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring * ring)1737 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1738 {
1739 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1740 }
1741
1742 /**
1743 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1744 *
1745 * @ring: amdgpu_ring pointer
1746 * @job: job to retrive vmid from
1747 * @ib: indirect buffer to execute
1748 * @flags: unused
1749 *
1750 * Write enc ring commands to execute the indirect buffer
1751 */
vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1752 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1753 struct amdgpu_job *job,
1754 struct amdgpu_ib *ib,
1755 uint32_t flags)
1756 {
1757 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1758
1759 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1760 amdgpu_ring_write(ring, vmid);
1761 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1762 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1763 amdgpu_ring_write(ring, ib->length_dw);
1764 }
1765
vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1766 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1767 uint32_t val, uint32_t mask)
1768 {
1769 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1770 amdgpu_ring_write(ring, reg << 2);
1771 amdgpu_ring_write(ring, mask);
1772 amdgpu_ring_write(ring, val);
1773 }
1774
vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1775 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1776 unsigned int vmid, uint64_t pd_addr)
1777 {
1778 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1779
1780 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1781
1782 /* wait for reg writes */
1783 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1784 vmid * hub->ctx_addr_distance,
1785 lower_32_bits(pd_addr), 0xffffffff);
1786 }
1787
vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1788 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1789 {
1790 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1791 amdgpu_ring_write(ring, reg << 2);
1792 amdgpu_ring_write(ring, val);
1793 }
1794
vcn_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1795 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1796 struct amdgpu_irq_src *source,
1797 unsigned type,
1798 enum amdgpu_interrupt_state state)
1799 {
1800 return 0;
1801 }
1802
vcn_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1803 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1804 struct amdgpu_irq_src *source,
1805 struct amdgpu_iv_entry *entry)
1806 {
1807 DRM_DEBUG("IH: VCN TRAP\n");
1808
1809 switch (entry->src_id) {
1810 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1811 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1812 break;
1813 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1814 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1815 break;
1816 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1817 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1818 break;
1819 default:
1820 DRM_ERROR("Unhandled interrupt: %d %d\n",
1821 entry->src_id, entry->src_data[0]);
1822 break;
1823 }
1824
1825 return 0;
1826 }
1827
vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring * ring)1828 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1829 {
1830 struct amdgpu_device *adev = ring->adev;
1831 uint32_t tmp = 0;
1832 unsigned i;
1833 int r;
1834
1835 if (amdgpu_sriov_vf(adev))
1836 return 0;
1837
1838 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1839 r = amdgpu_ring_alloc(ring, 4);
1840 if (r)
1841 return r;
1842 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1843 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1844 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));
1845 amdgpu_ring_write(ring, 0xDEADBEEF);
1846 amdgpu_ring_commit(ring);
1847 for (i = 0; i < adev->usec_timeout; i++) {
1848 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1849 if (tmp == 0xDEADBEEF)
1850 break;
1851 udelay(1);
1852 }
1853
1854 if (i >= adev->usec_timeout)
1855 r = -ETIMEDOUT;
1856
1857 return r;
1858 }
1859
1860
vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst * vinst,enum amd_powergating_state state)1861 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
1862 enum amd_powergating_state state)
1863 {
1864 /* This doesn't actually powergate the VCN block.
1865 * That's done in the dpm code via the SMC. This
1866 * just re-inits the block as necessary. The actual
1867 * gating still happens in the dpm code. We should
1868 * revisit this when there is a cleaner line between
1869 * the smc and the hw blocks
1870 */
1871 int ret;
1872 struct amdgpu_device *adev = vinst->adev;
1873
1874 if (amdgpu_sriov_vf(adev)) {
1875 vinst->cur_state = AMD_PG_STATE_UNGATE;
1876 return 0;
1877 }
1878
1879 if (state == vinst->cur_state)
1880 return 0;
1881
1882 if (state == AMD_PG_STATE_GATE)
1883 ret = vcn_v2_0_stop(vinst);
1884 else
1885 ret = vcn_v2_0_start(vinst);
1886
1887 if (!ret)
1888 vinst->cur_state = state;
1889
1890 return ret;
1891 }
1892
vcn_v2_0_start_mmsch(struct amdgpu_device * adev,struct amdgpu_mm_table * table)1893 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1894 struct amdgpu_mm_table *table)
1895 {
1896 uint32_t data = 0, loop;
1897 uint64_t addr = table->gpu_addr;
1898 struct mmsch_v2_0_init_header *header;
1899 uint32_t size;
1900 int i;
1901
1902 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1903 size = header->header_size + header->vcn_table_size;
1904
1905 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1906 * of memory descriptor location
1907 */
1908 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1909 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1910
1911 /* 2, update vmid of descriptor */
1912 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1913 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1914 /* use domain0 for MM scheduler */
1915 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1916 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1917
1918 /* 3, notify mmsch about the size of this descriptor */
1919 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1920
1921 /* 4, set resp to zero */
1922 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1923
1924 adev->vcn.inst->ring_dec.wptr = 0;
1925 adev->vcn.inst->ring_dec.wptr_old = 0;
1926 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1927
1928 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
1929 adev->vcn.inst->ring_enc[i].wptr = 0;
1930 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1931 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1932 }
1933
1934 /* 5, kick off the initialization and wait until
1935 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1936 */
1937 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1938
1939 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1940 loop = 1000;
1941 while ((data & 0x10000002) != 0x10000002) {
1942 udelay(10);
1943 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1944 loop--;
1945 if (!loop)
1946 break;
1947 }
1948
1949 if (!loop) {
1950 DRM_ERROR("failed to init MMSCH, " \
1951 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1952 return -EBUSY;
1953 }
1954
1955 return 0;
1956 }
1957
vcn_v2_0_start_sriov(struct amdgpu_device * adev)1958 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1959 {
1960 int r;
1961 uint32_t tmp;
1962 struct amdgpu_ring *ring;
1963 uint32_t offset, size;
1964 uint32_t table_size = 0;
1965 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1966 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1967 struct mmsch_v2_0_cmd_end end = { {0} };
1968 struct mmsch_v2_0_init_header *header;
1969 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1970 uint8_t i = 0;
1971
1972 header = (struct mmsch_v2_0_init_header *)init_table;
1973 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1974 direct_rd_mod_wt.cmd_header.command_type =
1975 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1976 end.cmd_header.command_type = MMSCH_COMMAND__END;
1977
1978 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1979 header->version = MMSCH_VERSION;
1980 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1981
1982 header->vcn_table_offset = header->header_size;
1983
1984 init_table += header->vcn_table_offset;
1985
1986 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
1987
1988 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1989 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1990 0xFFFFFFFF, 0x00000004);
1991
1992 /* mc resume*/
1993 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1994 MMSCH_V2_0_INSERT_DIRECT_WT(
1995 SOC15_REG_OFFSET(UVD, i,
1996 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1997 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);
1998 MMSCH_V2_0_INSERT_DIRECT_WT(
1999 SOC15_REG_OFFSET(UVD, i,
2000 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
2001 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);
2002 offset = 0;
2003 } else {
2004 MMSCH_V2_0_INSERT_DIRECT_WT(
2005 SOC15_REG_OFFSET(UVD, i,
2006 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
2007 lower_32_bits(adev->vcn.inst->gpu_addr));
2008 MMSCH_V2_0_INSERT_DIRECT_WT(
2009 SOC15_REG_OFFSET(UVD, i,
2010 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
2011 upper_32_bits(adev->vcn.inst->gpu_addr));
2012 offset = size;
2013 }
2014
2015 MMSCH_V2_0_INSERT_DIRECT_WT(
2016 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
2017 0);
2018 MMSCH_V2_0_INSERT_DIRECT_WT(
2019 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
2020 size);
2021
2022 MMSCH_V2_0_INSERT_DIRECT_WT(
2023 SOC15_REG_OFFSET(UVD, i,
2024 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
2025 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
2026 MMSCH_V2_0_INSERT_DIRECT_WT(
2027 SOC15_REG_OFFSET(UVD, i,
2028 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
2029 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
2030 MMSCH_V2_0_INSERT_DIRECT_WT(
2031 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
2032 0);
2033 MMSCH_V2_0_INSERT_DIRECT_WT(
2034 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
2035 AMDGPU_VCN_STACK_SIZE);
2036
2037 MMSCH_V2_0_INSERT_DIRECT_WT(
2038 SOC15_REG_OFFSET(UVD, i,
2039 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
2040 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
2041 AMDGPU_VCN_STACK_SIZE));
2042 MMSCH_V2_0_INSERT_DIRECT_WT(
2043 SOC15_REG_OFFSET(UVD, i,
2044 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
2045 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
2046 AMDGPU_VCN_STACK_SIZE));
2047 MMSCH_V2_0_INSERT_DIRECT_WT(
2048 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
2049 0);
2050 MMSCH_V2_0_INSERT_DIRECT_WT(
2051 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
2052 AMDGPU_VCN_CONTEXT_SIZE);
2053
2054 for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) {
2055 ring = &adev->vcn.inst->ring_enc[r];
2056 ring->wptr = 0;
2057 MMSCH_V2_0_INSERT_DIRECT_WT(
2058 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
2059 lower_32_bits(ring->gpu_addr));
2060 MMSCH_V2_0_INSERT_DIRECT_WT(
2061 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
2062 upper_32_bits(ring->gpu_addr));
2063 MMSCH_V2_0_INSERT_DIRECT_WT(
2064 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
2065 ring->ring_size / 4);
2066 }
2067
2068 ring = &adev->vcn.inst->ring_dec;
2069 ring->wptr = 0;
2070 MMSCH_V2_0_INSERT_DIRECT_WT(
2071 SOC15_REG_OFFSET(UVD, i,
2072 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
2073 lower_32_bits(ring->gpu_addr));
2074 MMSCH_V2_0_INSERT_DIRECT_WT(
2075 SOC15_REG_OFFSET(UVD, i,
2076 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
2077 upper_32_bits(ring->gpu_addr));
2078 /* force RBC into idle state */
2079 tmp = order_base_2(ring->ring_size);
2080 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
2081 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
2082 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
2083 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
2084 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
2085 MMSCH_V2_0_INSERT_DIRECT_WT(
2086 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
2087
2088 /* add end packet */
2089 tmp = sizeof(struct mmsch_v2_0_cmd_end);
2090 memcpy((void *)init_table, &end, tmp);
2091 table_size += (tmp / 4);
2092 header->vcn_table_size = table_size;
2093
2094 }
2095 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
2096 }
2097
vcn_v2_0_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)2098 static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2099 {
2100 struct amdgpu_device *adev = ip_block->adev;
2101 int i, j;
2102 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
2103 uint32_t inst_off, is_powered;
2104
2105 if (!adev->vcn.ip_dump)
2106 return;
2107
2108 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
2109 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2110 if (adev->vcn.harvest_config & (1 << i)) {
2111 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
2112 continue;
2113 }
2114
2115 inst_off = i * reg_count;
2116 is_powered = (adev->vcn.ip_dump[inst_off] &
2117 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2118
2119 if (is_powered) {
2120 drm_printf(p, "\nActive Instance:VCN%d\n", i);
2121 for (j = 0; j < reg_count; j++)
2122 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
2123 adev->vcn.ip_dump[inst_off + j]);
2124 } else {
2125 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
2126 }
2127 }
2128 }
2129
vcn_v2_0_dump_ip_state(struct amdgpu_ip_block * ip_block)2130 static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
2131 {
2132 struct amdgpu_device *adev = ip_block->adev;
2133 int i, j;
2134 bool is_powered;
2135 uint32_t inst_off;
2136 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
2137
2138 if (!adev->vcn.ip_dump)
2139 return;
2140
2141 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2142 if (adev->vcn.harvest_config & (1 << i))
2143 continue;
2144
2145 inst_off = i * reg_count;
2146 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
2147 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
2148 is_powered = (adev->vcn.ip_dump[inst_off] &
2149 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2150
2151 if (is_powered)
2152 for (j = 1; j < reg_count; j++)
2153 adev->vcn.ip_dump[inst_off + j] =
2154 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
2155 }
2156 }
2157
2158 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
2159 .name = "vcn_v2_0",
2160 .early_init = vcn_v2_0_early_init,
2161 .sw_init = vcn_v2_0_sw_init,
2162 .sw_fini = vcn_v2_0_sw_fini,
2163 .hw_init = vcn_v2_0_hw_init,
2164 .hw_fini = vcn_v2_0_hw_fini,
2165 .suspend = vcn_v2_0_suspend,
2166 .resume = vcn_v2_0_resume,
2167 .is_idle = vcn_v2_0_is_idle,
2168 .wait_for_idle = vcn_v2_0_wait_for_idle,
2169 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
2170 .set_powergating_state = vcn_set_powergating_state,
2171 .dump_ip_state = vcn_v2_0_dump_ip_state,
2172 .print_ip_state = vcn_v2_0_print_ip_state,
2173 };
2174
2175 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2176 .type = AMDGPU_RING_TYPE_VCN_DEC,
2177 .align_mask = 0xf,
2178 .secure_submission_supported = true,
2179 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2180 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2181 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2182 .emit_frame_size =
2183 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2184 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2185 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2186 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2187 6,
2188 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2189 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2190 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2191 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2192 .test_ring = vcn_v2_0_dec_ring_test_ring,
2193 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2194 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2195 .insert_start = vcn_v2_0_dec_ring_insert_start,
2196 .insert_end = vcn_v2_0_dec_ring_insert_end,
2197 .pad_ib = amdgpu_ring_generic_pad_ib,
2198 .begin_use = amdgpu_vcn_ring_begin_use,
2199 .end_use = amdgpu_vcn_ring_end_use,
2200 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2201 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2202 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2203 .reset = amdgpu_vcn_ring_reset,
2204 };
2205
2206 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2207 .type = AMDGPU_RING_TYPE_VCN_ENC,
2208 .align_mask = 0x3f,
2209 .nop = VCN_ENC_CMD_NO_OP,
2210 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2211 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2212 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2213 .emit_frame_size =
2214 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2215 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2216 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2217 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2218 1, /* vcn_v2_0_enc_ring_insert_end */
2219 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2220 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2221 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2222 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2223 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2224 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2225 .insert_nop = amdgpu_ring_insert_nop,
2226 .insert_end = vcn_v2_0_enc_ring_insert_end,
2227 .pad_ib = amdgpu_ring_generic_pad_ib,
2228 .begin_use = amdgpu_vcn_ring_begin_use,
2229 .end_use = amdgpu_vcn_ring_end_use,
2230 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2231 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2232 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2233 .reset = amdgpu_vcn_ring_reset,
2234 };
2235
vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)2236 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2237 {
2238 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
2239 }
2240
vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device * adev)2241 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2242 {
2243 int i;
2244
2245 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
2246 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2247 }
2248
2249 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2250 .set = vcn_v2_0_set_interrupt_state,
2251 .process = vcn_v2_0_process_interrupt,
2252 };
2253
vcn_v2_0_set_irq_funcs(struct amdgpu_device * adev)2254 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2255 {
2256 adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1;
2257 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2258 }
2259
2260 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2261 {
2262 .type = AMD_IP_BLOCK_TYPE_VCN,
2263 .major = 2,
2264 .minor = 0,
2265 .rev = 0,
2266 .funcs = &vcn_v2_0_ip_funcs,
2267 };
2268