1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_psp.h" 33 #include "mmsch_v2_0.h" 34 #include "vcn_v2_0.h" 35 36 #include "vcn/vcn_2_0_0_offset.h" 37 #include "vcn/vcn_2_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 50 51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 55 56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = { 57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 90 }; 91 92 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 93 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 94 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 95 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 96 enum amd_powergating_state state); 97 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 98 struct dpg_pause_state *new_state); 99 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); 100 /** 101 * vcn_v2_0_early_init - set function pointers and load microcode 102 * 103 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 104 * 105 * Set ring and irq function pointers 106 * Load microcode from filesystem 107 */ 108 static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block) 109 { 110 struct amdgpu_device *adev = ip_block->adev; 111 112 if (amdgpu_sriov_vf(adev)) 113 adev->vcn.inst[0].num_enc_rings = 1; 114 else 115 adev->vcn.inst[0].num_enc_rings = 2; 116 117 adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state; 118 vcn_v2_0_set_dec_ring_funcs(adev); 119 vcn_v2_0_set_enc_ring_funcs(adev); 120 vcn_v2_0_set_irq_funcs(adev); 121 122 return amdgpu_vcn_early_init(adev, 0); 123 } 124 125 /** 126 * vcn_v2_0_sw_init - sw init for VCN block 127 * 128 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 129 * 130 * Load firmware and sw initialization 131 */ 132 static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) 133 { 134 struct amdgpu_ring *ring; 135 int i, r; 136 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); 137 uint32_t *ptr; 138 struct amdgpu_device *adev = ip_block->adev; 139 volatile struct amdgpu_fw_shared *fw_shared; 140 141 /* VCN DEC TRAP */ 142 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 143 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 144 &adev->vcn.inst->irq); 145 if (r) 146 return r; 147 148 /* VCN ENC TRAP */ 149 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 150 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 151 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 152 &adev->vcn.inst->irq); 153 if (r) 154 return r; 155 } 156 157 r = amdgpu_vcn_sw_init(adev, 0); 158 if (r) 159 return r; 160 161 amdgpu_vcn_setup_ucode(adev, 0); 162 163 r = amdgpu_vcn_resume(adev, 0); 164 if (r) 165 return r; 166 167 ring = &adev->vcn.inst->ring_dec; 168 169 ring->use_doorbell = true; 170 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 171 ring->vm_hub = AMDGPU_MMHUB0(0); 172 173 sprintf(ring->name, "vcn_dec"); 174 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 175 AMDGPU_RING_PRIO_DEFAULT, NULL); 176 if (r) 177 return r; 178 179 adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 180 adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 181 adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 182 adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 183 adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 184 adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 185 186 adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 187 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 188 adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 189 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 190 adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 191 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 192 adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 193 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 194 adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 195 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 196 197 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 198 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 199 200 ring = &adev->vcn.inst->ring_enc[i]; 201 ring->use_doorbell = true; 202 ring->vm_hub = AMDGPU_MMHUB0(0); 203 if (!amdgpu_sriov_vf(adev)) 204 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 205 else 206 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 207 sprintf(ring->name, "vcn_enc%d", i); 208 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 209 hw_prio, NULL); 210 if (r) 211 return r; 212 } 213 214 adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 215 216 r = amdgpu_virt_alloc_mm_table(adev); 217 if (r) 218 return r; 219 220 fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 221 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 222 223 if (amdgpu_vcnfw_log) 224 amdgpu_vcn_fwlog_init(adev->vcn.inst); 225 226 /* Allocate memory for VCN IP Dump buffer */ 227 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 228 if (!ptr) { 229 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 230 adev->vcn.ip_dump = NULL; 231 } else { 232 adev->vcn.ip_dump = ptr; 233 } 234 235 return 0; 236 } 237 238 /** 239 * vcn_v2_0_sw_fini - sw fini for VCN block 240 * 241 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 242 * 243 * VCN suspend and free up sw allocation 244 */ 245 static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) 246 { 247 int r, idx; 248 struct amdgpu_device *adev = ip_block->adev; 249 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 250 251 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 252 fw_shared->present_flag_0 = 0; 253 drm_dev_exit(idx); 254 } 255 256 amdgpu_virt_free_mm_table(adev); 257 258 r = amdgpu_vcn_suspend(adev, 0); 259 if (r) 260 return r; 261 262 r = amdgpu_vcn_sw_fini(adev, 0); 263 264 kfree(adev->vcn.ip_dump); 265 266 return r; 267 } 268 269 /** 270 * vcn_v2_0_hw_init - start and test VCN block 271 * 272 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 273 * 274 * Initialize the hardware, boot up the VCPU and do some testing 275 */ 276 static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block) 277 { 278 struct amdgpu_device *adev = ip_block->adev; 279 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 280 int i, r; 281 282 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 283 ring->doorbell_index, 0); 284 285 if (amdgpu_sriov_vf(adev)) 286 vcn_v2_0_start_sriov(adev); 287 288 r = amdgpu_ring_test_helper(ring); 289 if (r) 290 return r; 291 292 //Disable vcn decode for sriov 293 if (amdgpu_sriov_vf(adev)) 294 ring->sched.ready = false; 295 296 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 297 ring = &adev->vcn.inst->ring_enc[i]; 298 r = amdgpu_ring_test_helper(ring); 299 if (r) 300 return r; 301 } 302 303 return 0; 304 } 305 306 /** 307 * vcn_v2_0_hw_fini - stop the hardware block 308 * 309 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 310 * 311 * Stop the VCN block, mark ring as not ready any more 312 */ 313 static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) 314 { 315 struct amdgpu_device *adev = ip_block->adev; 316 struct amdgpu_vcn_inst *vinst = adev->vcn.inst; 317 318 cancel_delayed_work_sync(&vinst->idle_work); 319 320 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 321 (vinst->cur_state != AMD_PG_STATE_GATE && 322 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 323 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 324 325 return 0; 326 } 327 328 /** 329 * vcn_v2_0_suspend - suspend VCN block 330 * 331 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 332 * 333 * HW fini and suspend VCN block 334 */ 335 static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block) 336 { 337 int r; 338 339 r = vcn_v2_0_hw_fini(ip_block); 340 if (r) 341 return r; 342 343 r = amdgpu_vcn_suspend(ip_block->adev, 0); 344 345 return r; 346 } 347 348 /** 349 * vcn_v2_0_resume - resume VCN block 350 * 351 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 352 * 353 * Resume firmware and hw init VCN block 354 */ 355 static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block) 356 { 357 int r; 358 359 r = amdgpu_vcn_resume(ip_block->adev, 0); 360 if (r) 361 return r; 362 363 r = vcn_v2_0_hw_init(ip_block); 364 365 return r; 366 } 367 368 /** 369 * vcn_v2_0_mc_resume - memory controller programming 370 * 371 * @vinst: Pointer to the VCN instance structure 372 * 373 * Let the VCN memory controller know it's offsets 374 */ 375 static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst) 376 { 377 struct amdgpu_device *adev = vinst->adev; 378 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); 379 uint32_t offset; 380 381 if (amdgpu_sriov_vf(adev)) 382 return; 383 384 /* cache window 0: fw */ 385 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 386 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 387 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 388 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 389 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 390 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 391 offset = 0; 392 } else { 393 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 394 lower_32_bits(adev->vcn.inst->gpu_addr)); 395 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 396 upper_32_bits(adev->vcn.inst->gpu_addr)); 397 offset = size; 398 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 399 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 400 } 401 402 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 403 404 /* cache window 1: stack */ 405 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 406 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 407 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 408 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 409 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 410 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 411 412 /* cache window 2: context */ 413 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 414 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 415 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 416 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 417 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 418 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 419 420 /* non-cache window */ 421 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 422 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 423 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 424 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 425 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 426 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, 427 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 428 429 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 430 } 431 432 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 433 bool indirect) 434 { 435 struct amdgpu_device *adev = vinst->adev; 436 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); 437 uint32_t offset; 438 439 /* cache window 0: fw */ 440 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 441 if (!indirect) { 442 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 443 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 444 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 445 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 446 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 447 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 448 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 449 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 450 } else { 451 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 452 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 453 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 454 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 455 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 456 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 457 } 458 offset = 0; 459 } else { 460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 461 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 462 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 463 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 464 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 465 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 466 offset = size; 467 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 468 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 469 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 470 } 471 472 if (!indirect) 473 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 474 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 475 else 476 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 477 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 478 479 /* cache window 1: stack */ 480 if (!indirect) { 481 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 482 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 483 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 484 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 485 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 486 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 487 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 488 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 489 } else { 490 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 491 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 492 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 493 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 494 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 495 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 496 } 497 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 498 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 499 500 /* cache window 2: context */ 501 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 502 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 503 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 504 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 505 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 506 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 507 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 508 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 509 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 510 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 511 512 /* non-cache window */ 513 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 514 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 515 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 516 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 517 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 518 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 519 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 520 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 521 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 522 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 523 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 524 525 /* VCN global tiling registers */ 526 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 527 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 528 } 529 530 /** 531 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 532 * 533 * @vinst: VCN instance 534 * 535 * Disable clock gating for VCN block 536 */ 537 static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 538 { 539 struct amdgpu_device *adev = vinst->adev; 540 uint32_t data; 541 542 if (amdgpu_sriov_vf(adev)) 543 return; 544 545 /* UVD disable CGC */ 546 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 547 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 548 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 549 else 550 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 551 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 552 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 553 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 554 555 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 556 data &= ~(UVD_CGC_GATE__SYS_MASK 557 | UVD_CGC_GATE__UDEC_MASK 558 | UVD_CGC_GATE__MPEG2_MASK 559 | UVD_CGC_GATE__REGS_MASK 560 | UVD_CGC_GATE__RBC_MASK 561 | UVD_CGC_GATE__LMI_MC_MASK 562 | UVD_CGC_GATE__LMI_UMC_MASK 563 | UVD_CGC_GATE__IDCT_MASK 564 | UVD_CGC_GATE__MPRD_MASK 565 | UVD_CGC_GATE__MPC_MASK 566 | UVD_CGC_GATE__LBSI_MASK 567 | UVD_CGC_GATE__LRBBM_MASK 568 | UVD_CGC_GATE__UDEC_RE_MASK 569 | UVD_CGC_GATE__UDEC_CM_MASK 570 | UVD_CGC_GATE__UDEC_IT_MASK 571 | UVD_CGC_GATE__UDEC_DB_MASK 572 | UVD_CGC_GATE__UDEC_MP_MASK 573 | UVD_CGC_GATE__WCB_MASK 574 | UVD_CGC_GATE__VCPU_MASK 575 | UVD_CGC_GATE__SCPU_MASK); 576 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 577 578 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 579 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 580 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 581 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 582 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 583 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 584 | UVD_CGC_CTRL__SYS_MODE_MASK 585 | UVD_CGC_CTRL__UDEC_MODE_MASK 586 | UVD_CGC_CTRL__MPEG2_MODE_MASK 587 | UVD_CGC_CTRL__REGS_MODE_MASK 588 | UVD_CGC_CTRL__RBC_MODE_MASK 589 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 590 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 591 | UVD_CGC_CTRL__IDCT_MODE_MASK 592 | UVD_CGC_CTRL__MPRD_MODE_MASK 593 | UVD_CGC_CTRL__MPC_MODE_MASK 594 | UVD_CGC_CTRL__LBSI_MODE_MASK 595 | UVD_CGC_CTRL__LRBBM_MODE_MASK 596 | UVD_CGC_CTRL__WCB_MODE_MASK 597 | UVD_CGC_CTRL__VCPU_MODE_MASK 598 | UVD_CGC_CTRL__SCPU_MODE_MASK); 599 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 600 601 /* turn on */ 602 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 603 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 604 | UVD_SUVD_CGC_GATE__SIT_MASK 605 | UVD_SUVD_CGC_GATE__SMP_MASK 606 | UVD_SUVD_CGC_GATE__SCM_MASK 607 | UVD_SUVD_CGC_GATE__SDB_MASK 608 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 609 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 610 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 611 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 612 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 613 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 614 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 615 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 616 | UVD_SUVD_CGC_GATE__SCLR_MASK 617 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 618 | UVD_SUVD_CGC_GATE__ENT_MASK 619 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 620 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 621 | UVD_SUVD_CGC_GATE__SITE_MASK 622 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 623 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 624 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 625 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 626 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 627 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 628 629 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 630 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 631 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 632 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 633 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 634 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 635 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 636 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 637 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 638 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 639 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 640 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 641 } 642 643 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 644 uint8_t sram_sel, uint8_t indirect) 645 { 646 struct amdgpu_device *adev = vinst->adev; 647 uint32_t reg_data = 0; 648 649 /* enable sw clock gating control */ 650 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 651 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 652 else 653 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 654 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 655 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 656 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 657 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 658 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 659 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 660 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 661 UVD_CGC_CTRL__SYS_MODE_MASK | 662 UVD_CGC_CTRL__UDEC_MODE_MASK | 663 UVD_CGC_CTRL__MPEG2_MODE_MASK | 664 UVD_CGC_CTRL__REGS_MODE_MASK | 665 UVD_CGC_CTRL__RBC_MODE_MASK | 666 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 667 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 668 UVD_CGC_CTRL__IDCT_MODE_MASK | 669 UVD_CGC_CTRL__MPRD_MODE_MASK | 670 UVD_CGC_CTRL__MPC_MODE_MASK | 671 UVD_CGC_CTRL__LBSI_MODE_MASK | 672 UVD_CGC_CTRL__LRBBM_MODE_MASK | 673 UVD_CGC_CTRL__WCB_MODE_MASK | 674 UVD_CGC_CTRL__VCPU_MODE_MASK | 675 UVD_CGC_CTRL__SCPU_MODE_MASK); 676 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 677 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 678 679 /* turn off clock gating */ 680 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 681 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 682 683 /* turn on SUVD clock gating */ 684 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 685 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 686 687 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 688 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 689 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 690 } 691 692 /** 693 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 694 * 695 * @vinst: VCN instance 696 * 697 * Enable clock gating for VCN block 698 */ 699 static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 700 { 701 struct amdgpu_device *adev = vinst->adev; 702 uint32_t data = 0; 703 704 if (amdgpu_sriov_vf(adev)) 705 return; 706 707 /* enable UVD CGC */ 708 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 709 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 710 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 711 else 712 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 713 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 714 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 715 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 716 717 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 718 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 719 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 720 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 721 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 722 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 723 | UVD_CGC_CTRL__SYS_MODE_MASK 724 | UVD_CGC_CTRL__UDEC_MODE_MASK 725 | UVD_CGC_CTRL__MPEG2_MODE_MASK 726 | UVD_CGC_CTRL__REGS_MODE_MASK 727 | UVD_CGC_CTRL__RBC_MODE_MASK 728 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 729 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 730 | UVD_CGC_CTRL__IDCT_MODE_MASK 731 | UVD_CGC_CTRL__MPRD_MODE_MASK 732 | UVD_CGC_CTRL__MPC_MODE_MASK 733 | UVD_CGC_CTRL__LBSI_MODE_MASK 734 | UVD_CGC_CTRL__LRBBM_MODE_MASK 735 | UVD_CGC_CTRL__WCB_MODE_MASK 736 | UVD_CGC_CTRL__VCPU_MODE_MASK 737 | UVD_CGC_CTRL__SCPU_MODE_MASK); 738 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 739 740 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 741 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 742 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 743 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 744 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 745 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 746 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 747 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 748 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 749 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 750 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 751 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 752 } 753 754 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 755 { 756 struct amdgpu_device *adev = vinst->adev; 757 uint32_t data = 0; 758 759 if (amdgpu_sriov_vf(adev)) 760 return; 761 762 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 763 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 764 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 766 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 767 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 768 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 769 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 770 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 771 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 772 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 773 774 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 775 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 776 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF); 777 } else { 778 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 779 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 780 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 781 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 782 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 783 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 784 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 785 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 786 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 787 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 788 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 789 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); 790 } 791 792 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 793 * UVDU_PWR_STATUS are 0 (power on) */ 794 795 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 796 data &= ~0x103; 797 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 798 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 799 UVD_POWER_STATUS__UVD_PG_EN_MASK; 800 801 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 802 } 803 804 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 805 { 806 struct amdgpu_device *adev = vinst->adev; 807 uint32_t data = 0; 808 809 if (amdgpu_sriov_vf(adev)) 810 return; 811 812 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 813 /* Before power off, this indicator has to be turned on */ 814 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 815 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 816 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 817 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 818 819 820 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 821 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 822 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 823 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 824 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 825 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 826 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 827 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 828 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 829 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 830 831 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 832 833 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 834 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 835 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 836 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 837 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 838 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 839 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 840 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 841 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 842 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 843 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); 844 } 845 } 846 847 static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 848 { 849 struct amdgpu_device *adev = vinst->adev; 850 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 851 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 852 uint32_t rb_bufsz, tmp; 853 854 vcn_v2_0_enable_static_power_gating(vinst); 855 856 /* enable dynamic power gating mode */ 857 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 858 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 859 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 860 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 861 862 if (indirect) 863 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; 864 865 /* enable clock gating */ 866 vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect); 867 868 /* enable VCPU clock */ 869 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 870 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 871 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 872 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 873 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 874 875 /* disable master interupt */ 876 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 877 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 878 879 /* setup mmUVD_LMI_CTRL */ 880 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 881 UVD_LMI_CTRL__REQ_MODE_MASK | 882 UVD_LMI_CTRL__CRC_RESET_MASK | 883 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 884 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 885 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 886 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 887 0x00100000L); 888 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 889 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 890 891 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 892 UVD, 0, mmUVD_MPC_CNTL), 893 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 894 895 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 896 UVD, 0, mmUVD_MPC_SET_MUXA0), 897 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 898 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 899 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 900 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 901 902 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 903 UVD, 0, mmUVD_MPC_SET_MUXB0), 904 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 905 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 906 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 907 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 908 909 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 910 UVD, 0, mmUVD_MPC_SET_MUX), 911 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 912 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 913 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 914 915 vcn_v2_0_mc_resume_dpg_mode(vinst, indirect); 916 917 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 918 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 919 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 920 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 921 922 /* release VCPU reset to boot */ 923 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 924 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 925 926 /* enable LMI MC and UMC channels */ 927 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 928 UVD, 0, mmUVD_LMI_CTRL2), 929 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 930 931 /* enable master interrupt */ 932 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 933 UVD, 0, mmUVD_MASTINT_EN), 934 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 935 936 if (indirect) 937 amdgpu_vcn_psp_update_sram(adev, 0, 0); 938 939 /* force RBC into idle state */ 940 rb_bufsz = order_base_2(ring->ring_size); 941 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 942 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 943 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 944 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 945 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 946 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 947 948 /* Stall DPG before WPTR/RPTR reset */ 949 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 950 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 951 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 952 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 953 954 /* set the write pointer delay */ 955 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 956 957 /* set the wb address */ 958 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 959 (upper_32_bits(ring->gpu_addr) >> 2)); 960 961 /* program the RB_BASE for ring buffer */ 962 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 963 lower_32_bits(ring->gpu_addr)); 964 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 965 upper_32_bits(ring->gpu_addr)); 966 967 /* Initialize the ring buffer's read and write pointers */ 968 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 969 970 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 971 972 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 973 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 974 lower_32_bits(ring->wptr)); 975 976 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 977 /* Unstall DPG */ 978 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 979 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 980 return 0; 981 } 982 983 static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst) 984 { 985 struct amdgpu_device *adev = vinst->adev; 986 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 987 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 988 uint32_t rb_bufsz, tmp; 989 uint32_t lmi_swap_cntl; 990 int i, j, r; 991 992 if (adev->pm.dpm_enabled) 993 amdgpu_dpm_enable_vcn(adev, true, 0); 994 995 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 996 return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram); 997 998 vcn_v2_0_disable_static_power_gating(vinst); 999 1000 /* set uvd status busy */ 1001 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1002 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 1003 1004 /*SW clock gating */ 1005 vcn_v2_0_disable_clock_gating(vinst); 1006 1007 /* enable VCPU clock */ 1008 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 1009 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1010 1011 /* disable master interrupt */ 1012 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 1013 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1014 1015 /* setup mmUVD_LMI_CTRL */ 1016 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 1017 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 1018 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1019 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1020 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1021 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1022 1023 /* setup mmUVD_MPC_CNTL */ 1024 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 1025 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1026 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1027 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 1028 1029 /* setup UVD_MPC_SET_MUXA0 */ 1030 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 1031 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1032 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1033 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1034 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1035 1036 /* setup UVD_MPC_SET_MUXB0 */ 1037 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 1038 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1039 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1040 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1041 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1042 1043 /* setup mmUVD_MPC_SET_MUX */ 1044 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 1045 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1046 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1047 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1048 1049 vcn_v2_0_mc_resume(vinst); 1050 1051 /* release VCPU reset to boot */ 1052 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1053 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1054 1055 /* enable LMI MC and UMC channels */ 1056 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1057 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1058 1059 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1060 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1061 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1062 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1063 1064 /* disable byte swapping */ 1065 lmi_swap_cntl = 0; 1066 #ifdef __BIG_ENDIAN 1067 /* swap (8 in 32) RB and IB */ 1068 lmi_swap_cntl = 0xa; 1069 #endif 1070 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1071 1072 for (i = 0; i < 10; ++i) { 1073 uint32_t status; 1074 1075 for (j = 0; j < 100; ++j) { 1076 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1077 if (status & 2) 1078 break; 1079 mdelay(10); 1080 } 1081 r = 0; 1082 if (status & 2) 1083 break; 1084 1085 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1086 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1087 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1088 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1089 mdelay(10); 1090 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1091 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1092 mdelay(10); 1093 r = -1; 1094 } 1095 1096 if (r) { 1097 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1098 return r; 1099 } 1100 1101 /* enable master interrupt */ 1102 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1103 UVD_MASTINT_EN__VCPU_EN_MASK, 1104 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1105 1106 /* clear the busy bit of VCN_STATUS */ 1107 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1108 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1109 1110 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1111 1112 /* force RBC into idle state */ 1113 rb_bufsz = order_base_2(ring->ring_size); 1114 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1115 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1116 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1117 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1118 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1119 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1120 1121 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1122 /* program the RB_BASE for ring buffer */ 1123 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1124 lower_32_bits(ring->gpu_addr)); 1125 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1126 upper_32_bits(ring->gpu_addr)); 1127 1128 /* Initialize the ring buffer's read and write pointers */ 1129 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1130 1131 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1132 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1133 lower_32_bits(ring->wptr)); 1134 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1135 1136 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1137 ring = &adev->vcn.inst->ring_enc[0]; 1138 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1139 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1140 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1141 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1142 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1143 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1144 1145 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1146 ring = &adev->vcn.inst->ring_enc[1]; 1147 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1148 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1149 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1150 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1151 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1152 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1153 1154 return 0; 1155 } 1156 1157 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1158 { 1159 struct amdgpu_device *adev = vinst->adev; 1160 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1161 uint32_t tmp; 1162 1163 vcn_v2_0_pause_dpg_mode(vinst, &state); 1164 /* Wait for power status to be 1 */ 1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1166 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1167 1168 /* wait for read ptr to be equal to write ptr */ 1169 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1170 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1171 1172 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1173 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1174 1175 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1176 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1177 1178 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1179 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1180 1181 /* disable dynamic power gating mode */ 1182 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1183 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1184 1185 return 0; 1186 } 1187 1188 static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst) 1189 { 1190 struct amdgpu_device *adev = vinst->adev; 1191 uint32_t tmp; 1192 int r; 1193 1194 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1195 r = vcn_v2_0_stop_dpg_mode(vinst); 1196 if (r) 1197 return r; 1198 goto power_off; 1199 } 1200 1201 /* wait for uvd idle */ 1202 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1203 if (r) 1204 return r; 1205 1206 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1207 UVD_LMI_STATUS__READ_CLEAN_MASK | 1208 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1209 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1210 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1211 if (r) 1212 return r; 1213 1214 /* stall UMC channel */ 1215 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1216 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1217 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1218 1219 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1220 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1221 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1222 if (r) 1223 return r; 1224 1225 /* disable VCPU clock */ 1226 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1227 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1228 1229 /* reset LMI UMC */ 1230 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1231 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1232 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1233 1234 /* reset LMI */ 1235 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1236 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1237 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1238 1239 /* reset VCPU */ 1240 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1241 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1242 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1243 1244 /* clear status */ 1245 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1246 1247 vcn_v2_0_enable_clock_gating(vinst); 1248 vcn_v2_0_enable_static_power_gating(vinst); 1249 1250 power_off: 1251 if (adev->pm.dpm_enabled) 1252 amdgpu_dpm_enable_vcn(adev, false, 0); 1253 1254 return 0; 1255 } 1256 1257 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1258 struct dpg_pause_state *new_state) 1259 { 1260 struct amdgpu_device *adev = vinst->adev; 1261 int inst_idx = vinst->inst; 1262 struct amdgpu_ring *ring; 1263 uint32_t reg_data = 0; 1264 int ret_code; 1265 1266 /* pause/unpause if state is changed */ 1267 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1268 DRM_DEBUG("dpg pause state changed %d -> %d", 1269 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1270 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1271 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1272 1273 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1274 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1275 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1276 1277 if (!ret_code) { 1278 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 1279 /* pause DPG */ 1280 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1281 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1282 1283 /* wait for ACK */ 1284 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1285 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1286 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1287 1288 /* Stall DPG before WPTR/RPTR reset */ 1289 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1290 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1291 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1292 /* Restore */ 1293 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1294 ring = &adev->vcn.inst->ring_enc[0]; 1295 ring->wptr = 0; 1296 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1297 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1298 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1299 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1300 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1301 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1302 1303 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1304 ring = &adev->vcn.inst->ring_enc[1]; 1305 ring->wptr = 0; 1306 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1307 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1308 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1309 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1310 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1311 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1312 1313 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1314 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1315 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1316 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1317 /* Unstall DPG */ 1318 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1319 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1320 1321 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1322 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1323 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1324 } 1325 } else { 1326 /* unpause dpg, no need to wait */ 1327 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1328 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1329 } 1330 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1331 } 1332 1333 return 0; 1334 } 1335 1336 static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block) 1337 { 1338 struct amdgpu_device *adev = ip_block->adev; 1339 1340 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1341 } 1342 1343 static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1344 { 1345 struct amdgpu_device *adev = ip_block->adev; 1346 int ret; 1347 1348 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1349 UVD_STATUS__IDLE); 1350 1351 return ret; 1352 } 1353 1354 static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1355 enum amd_clockgating_state state) 1356 { 1357 struct amdgpu_device *adev = ip_block->adev; 1358 bool enable = (state == AMD_CG_STATE_GATE); 1359 1360 if (amdgpu_sriov_vf(adev)) 1361 return 0; 1362 1363 if (enable) { 1364 /* wait for STATUS to clear */ 1365 if (!vcn_v2_0_is_idle(ip_block)) 1366 return -EBUSY; 1367 vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]); 1368 } else { 1369 /* disable HW gating and enable Sw gating */ 1370 vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]); 1371 } 1372 return 0; 1373 } 1374 1375 /** 1376 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1377 * 1378 * @ring: amdgpu_ring pointer 1379 * 1380 * Returns the current hardware read pointer 1381 */ 1382 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1383 { 1384 struct amdgpu_device *adev = ring->adev; 1385 1386 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1387 } 1388 1389 /** 1390 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1391 * 1392 * @ring: amdgpu_ring pointer 1393 * 1394 * Returns the current hardware write pointer 1395 */ 1396 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1397 { 1398 struct amdgpu_device *adev = ring->adev; 1399 1400 if (ring->use_doorbell) 1401 return *ring->wptr_cpu_addr; 1402 else 1403 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1404 } 1405 1406 /** 1407 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1408 * 1409 * @ring: amdgpu_ring pointer 1410 * 1411 * Commits the write pointer to the hardware 1412 */ 1413 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1414 { 1415 struct amdgpu_device *adev = ring->adev; 1416 1417 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1418 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1419 lower_32_bits(ring->wptr) | 0x80000000); 1420 1421 if (ring->use_doorbell) { 1422 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1423 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1424 } else { 1425 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1426 } 1427 } 1428 1429 /** 1430 * vcn_v2_0_dec_ring_insert_start - insert a start command 1431 * 1432 * @ring: amdgpu_ring pointer 1433 * 1434 * Write a start command to the ring. 1435 */ 1436 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1437 { 1438 struct amdgpu_device *adev = ring->adev; 1439 1440 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1441 amdgpu_ring_write(ring, 0); 1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1443 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1444 } 1445 1446 /** 1447 * vcn_v2_0_dec_ring_insert_end - insert a end command 1448 * 1449 * @ring: amdgpu_ring pointer 1450 * 1451 * Write a end command to the ring. 1452 */ 1453 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1454 { 1455 struct amdgpu_device *adev = ring->adev; 1456 1457 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0)); 1458 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1459 } 1460 1461 /** 1462 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1463 * 1464 * @ring: amdgpu_ring pointer 1465 * @count: the number of NOP packets to insert 1466 * 1467 * Write a nop command to the ring. 1468 */ 1469 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1470 { 1471 struct amdgpu_device *adev = ring->adev; 1472 int i; 1473 1474 WARN_ON(ring->wptr % 2 || count % 2); 1475 1476 for (i = 0; i < count / 2; i++) { 1477 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0)); 1478 amdgpu_ring_write(ring, 0); 1479 } 1480 } 1481 1482 /** 1483 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1484 * 1485 * @ring: amdgpu_ring pointer 1486 * @addr: address 1487 * @seq: sequence number 1488 * @flags: fence related flags 1489 * 1490 * Write a fence and a trap command to the ring. 1491 */ 1492 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1493 unsigned flags) 1494 { 1495 struct amdgpu_device *adev = ring->adev; 1496 1497 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1498 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0)); 1499 amdgpu_ring_write(ring, seq); 1500 1501 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1502 amdgpu_ring_write(ring, addr & 0xffffffff); 1503 1504 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1505 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1506 1507 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1508 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1509 1510 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1511 amdgpu_ring_write(ring, 0); 1512 1513 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1514 amdgpu_ring_write(ring, 0); 1515 1516 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1517 1518 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1519 } 1520 1521 /** 1522 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1523 * 1524 * @ring: amdgpu_ring pointer 1525 * @job: job to retrieve vmid from 1526 * @ib: indirect buffer to execute 1527 * @flags: unused 1528 * 1529 * Write ring commands to execute the indirect buffer 1530 */ 1531 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1532 struct amdgpu_job *job, 1533 struct amdgpu_ib *ib, 1534 uint32_t flags) 1535 { 1536 struct amdgpu_device *adev = ring->adev; 1537 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1538 1539 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0)); 1540 amdgpu_ring_write(ring, vmid); 1541 1542 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0)); 1543 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1544 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0)); 1545 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1546 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0)); 1547 amdgpu_ring_write(ring, ib->length_dw); 1548 } 1549 1550 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1551 uint32_t val, uint32_t mask) 1552 { 1553 struct amdgpu_device *adev = ring->adev; 1554 1555 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1556 amdgpu_ring_write(ring, reg << 2); 1557 1558 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1559 amdgpu_ring_write(ring, val); 1560 1561 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0)); 1562 amdgpu_ring_write(ring, mask); 1563 1564 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1565 1566 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1567 } 1568 1569 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1570 unsigned vmid, uint64_t pd_addr) 1571 { 1572 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1573 uint32_t data0, data1, mask; 1574 1575 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1576 1577 /* wait for register write */ 1578 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1579 data1 = lower_32_bits(pd_addr); 1580 mask = 0xffffffff; 1581 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1582 } 1583 1584 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1585 uint32_t reg, uint32_t val) 1586 { 1587 struct amdgpu_device *adev = ring->adev; 1588 1589 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1590 amdgpu_ring_write(ring, reg << 2); 1591 1592 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1593 amdgpu_ring_write(ring, val); 1594 1595 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1596 1597 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1598 } 1599 1600 /** 1601 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1602 * 1603 * @ring: amdgpu_ring pointer 1604 * 1605 * Returns the current hardware enc read pointer 1606 */ 1607 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1608 { 1609 struct amdgpu_device *adev = ring->adev; 1610 1611 if (ring == &adev->vcn.inst->ring_enc[0]) 1612 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1613 else 1614 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1615 } 1616 1617 /** 1618 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1619 * 1620 * @ring: amdgpu_ring pointer 1621 * 1622 * Returns the current hardware enc write pointer 1623 */ 1624 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1625 { 1626 struct amdgpu_device *adev = ring->adev; 1627 1628 if (ring == &adev->vcn.inst->ring_enc[0]) { 1629 if (ring->use_doorbell) 1630 return *ring->wptr_cpu_addr; 1631 else 1632 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1633 } else { 1634 if (ring->use_doorbell) 1635 return *ring->wptr_cpu_addr; 1636 else 1637 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1638 } 1639 } 1640 1641 /** 1642 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1643 * 1644 * @ring: amdgpu_ring pointer 1645 * 1646 * Commits the enc write pointer to the hardware 1647 */ 1648 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1649 { 1650 struct amdgpu_device *adev = ring->adev; 1651 1652 if (ring == &adev->vcn.inst->ring_enc[0]) { 1653 if (ring->use_doorbell) { 1654 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1655 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1656 } else { 1657 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1658 } 1659 } else { 1660 if (ring->use_doorbell) { 1661 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1662 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1663 } else { 1664 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1665 } 1666 } 1667 } 1668 1669 /** 1670 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1671 * 1672 * @ring: amdgpu_ring pointer 1673 * @addr: address 1674 * @seq: sequence number 1675 * @flags: fence related flags 1676 * 1677 * Write enc a fence and a trap command to the ring. 1678 */ 1679 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1680 u64 seq, unsigned flags) 1681 { 1682 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1683 1684 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1685 amdgpu_ring_write(ring, addr); 1686 amdgpu_ring_write(ring, upper_32_bits(addr)); 1687 amdgpu_ring_write(ring, seq); 1688 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1689 } 1690 1691 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1692 { 1693 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1694 } 1695 1696 /** 1697 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1698 * 1699 * @ring: amdgpu_ring pointer 1700 * @job: job to retrive vmid from 1701 * @ib: indirect buffer to execute 1702 * @flags: unused 1703 * 1704 * Write enc ring commands to execute the indirect buffer 1705 */ 1706 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1707 struct amdgpu_job *job, 1708 struct amdgpu_ib *ib, 1709 uint32_t flags) 1710 { 1711 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1712 1713 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1714 amdgpu_ring_write(ring, vmid); 1715 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1716 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1717 amdgpu_ring_write(ring, ib->length_dw); 1718 } 1719 1720 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1721 uint32_t val, uint32_t mask) 1722 { 1723 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1724 amdgpu_ring_write(ring, reg << 2); 1725 amdgpu_ring_write(ring, mask); 1726 amdgpu_ring_write(ring, val); 1727 } 1728 1729 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1730 unsigned int vmid, uint64_t pd_addr) 1731 { 1732 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1733 1734 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1735 1736 /* wait for reg writes */ 1737 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1738 vmid * hub->ctx_addr_distance, 1739 lower_32_bits(pd_addr), 0xffffffff); 1740 } 1741 1742 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1743 { 1744 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1745 amdgpu_ring_write(ring, reg << 2); 1746 amdgpu_ring_write(ring, val); 1747 } 1748 1749 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 1750 struct amdgpu_irq_src *source, 1751 unsigned type, 1752 enum amdgpu_interrupt_state state) 1753 { 1754 return 0; 1755 } 1756 1757 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 1758 struct amdgpu_irq_src *source, 1759 struct amdgpu_iv_entry *entry) 1760 { 1761 DRM_DEBUG("IH: VCN TRAP\n"); 1762 1763 switch (entry->src_id) { 1764 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1765 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1766 break; 1767 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1768 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1769 break; 1770 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1771 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1772 break; 1773 default: 1774 DRM_ERROR("Unhandled interrupt: %d %d\n", 1775 entry->src_id, entry->src_data[0]); 1776 break; 1777 } 1778 1779 return 0; 1780 } 1781 1782 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 1783 { 1784 struct amdgpu_device *adev = ring->adev; 1785 uint32_t tmp = 0; 1786 unsigned i; 1787 int r; 1788 1789 if (amdgpu_sriov_vf(adev)) 1790 return 0; 1791 1792 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 1793 r = amdgpu_ring_alloc(ring, 4); 1794 if (r) 1795 return r; 1796 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1797 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1798 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); 1799 amdgpu_ring_write(ring, 0xDEADBEEF); 1800 amdgpu_ring_commit(ring); 1801 for (i = 0; i < adev->usec_timeout; i++) { 1802 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 1803 if (tmp == 0xDEADBEEF) 1804 break; 1805 udelay(1); 1806 } 1807 1808 if (i >= adev->usec_timeout) 1809 r = -ETIMEDOUT; 1810 1811 return r; 1812 } 1813 1814 1815 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 1816 enum amd_powergating_state state) 1817 { 1818 /* This doesn't actually powergate the VCN block. 1819 * That's done in the dpm code via the SMC. This 1820 * just re-inits the block as necessary. The actual 1821 * gating still happens in the dpm code. We should 1822 * revisit this when there is a cleaner line between 1823 * the smc and the hw blocks 1824 */ 1825 int ret; 1826 struct amdgpu_device *adev = vinst->adev; 1827 1828 if (amdgpu_sriov_vf(adev)) { 1829 vinst->cur_state = AMD_PG_STATE_UNGATE; 1830 return 0; 1831 } 1832 1833 if (state == vinst->cur_state) 1834 return 0; 1835 1836 if (state == AMD_PG_STATE_GATE) 1837 ret = vcn_v2_0_stop(vinst); 1838 else 1839 ret = vcn_v2_0_start(vinst); 1840 1841 if (!ret) 1842 vinst->cur_state = state; 1843 1844 return ret; 1845 } 1846 1847 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev, 1848 struct amdgpu_mm_table *table) 1849 { 1850 uint32_t data = 0, loop; 1851 uint64_t addr = table->gpu_addr; 1852 struct mmsch_v2_0_init_header *header; 1853 uint32_t size; 1854 int i; 1855 1856 header = (struct mmsch_v2_0_init_header *)table->cpu_addr; 1857 size = header->header_size + header->vcn_table_size; 1858 1859 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1860 * of memory descriptor location 1861 */ 1862 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1863 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1864 1865 /* 2, update vmid of descriptor */ 1866 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID); 1867 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1868 /* use domain0 for MM scheduler */ 1869 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1870 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); 1871 1872 /* 3, notify mmsch about the size of this descriptor */ 1873 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); 1874 1875 /* 4, set resp to zero */ 1876 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1877 1878 adev->vcn.inst->ring_dec.wptr = 0; 1879 adev->vcn.inst->ring_dec.wptr_old = 0; 1880 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); 1881 1882 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 1883 adev->vcn.inst->ring_enc[i].wptr = 0; 1884 adev->vcn.inst->ring_enc[i].wptr_old = 0; 1885 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); 1886 } 1887 1888 /* 5, kick off the initialization and wait until 1889 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1890 */ 1891 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1892 1893 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1894 loop = 1000; 1895 while ((data & 0x10000002) != 0x10000002) { 1896 udelay(10); 1897 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1898 loop--; 1899 if (!loop) 1900 break; 1901 } 1902 1903 if (!loop) { 1904 DRM_ERROR("failed to init MMSCH, " \ 1905 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data); 1906 return -EBUSY; 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 1913 { 1914 int r; 1915 uint32_t tmp; 1916 struct amdgpu_ring *ring; 1917 uint32_t offset, size; 1918 uint32_t table_size = 0; 1919 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} }; 1920 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 1921 struct mmsch_v2_0_cmd_end end = { {0} }; 1922 struct mmsch_v2_0_init_header *header; 1923 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1924 uint8_t i = 0; 1925 1926 header = (struct mmsch_v2_0_init_header *)init_table; 1927 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1928 direct_rd_mod_wt.cmd_header.command_type = 1929 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1930 end.cmd_header.command_type = MMSCH_COMMAND__END; 1931 1932 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) { 1933 header->version = MMSCH_VERSION; 1934 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2; 1935 1936 header->vcn_table_offset = header->header_size; 1937 1938 init_table += header->vcn_table_offset; 1939 1940 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); 1941 1942 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( 1943 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 1944 0xFFFFFFFF, 0x00000004); 1945 1946 /* mc resume*/ 1947 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1948 MMSCH_V2_0_INSERT_DIRECT_WT( 1949 SOC15_REG_OFFSET(UVD, i, 1950 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1951 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo); 1952 MMSCH_V2_0_INSERT_DIRECT_WT( 1953 SOC15_REG_OFFSET(UVD, i, 1954 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1955 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi); 1956 offset = 0; 1957 } else { 1958 MMSCH_V2_0_INSERT_DIRECT_WT( 1959 SOC15_REG_OFFSET(UVD, i, 1960 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1961 lower_32_bits(adev->vcn.inst->gpu_addr)); 1962 MMSCH_V2_0_INSERT_DIRECT_WT( 1963 SOC15_REG_OFFSET(UVD, i, 1964 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1965 upper_32_bits(adev->vcn.inst->gpu_addr)); 1966 offset = size; 1967 } 1968 1969 MMSCH_V2_0_INSERT_DIRECT_WT( 1970 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 1971 0); 1972 MMSCH_V2_0_INSERT_DIRECT_WT( 1973 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), 1974 size); 1975 1976 MMSCH_V2_0_INSERT_DIRECT_WT( 1977 SOC15_REG_OFFSET(UVD, i, 1978 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1979 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 1980 MMSCH_V2_0_INSERT_DIRECT_WT( 1981 SOC15_REG_OFFSET(UVD, i, 1982 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1983 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 1984 MMSCH_V2_0_INSERT_DIRECT_WT( 1985 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), 1986 0); 1987 MMSCH_V2_0_INSERT_DIRECT_WT( 1988 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), 1989 AMDGPU_VCN_STACK_SIZE); 1990 1991 MMSCH_V2_0_INSERT_DIRECT_WT( 1992 SOC15_REG_OFFSET(UVD, i, 1993 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1994 lower_32_bits(adev->vcn.inst->gpu_addr + offset + 1995 AMDGPU_VCN_STACK_SIZE)); 1996 MMSCH_V2_0_INSERT_DIRECT_WT( 1997 SOC15_REG_OFFSET(UVD, i, 1998 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1999 upper_32_bits(adev->vcn.inst->gpu_addr + offset + 2000 AMDGPU_VCN_STACK_SIZE)); 2001 MMSCH_V2_0_INSERT_DIRECT_WT( 2002 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), 2003 0); 2004 MMSCH_V2_0_INSERT_DIRECT_WT( 2005 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 2006 AMDGPU_VCN_CONTEXT_SIZE); 2007 2008 for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) { 2009 ring = &adev->vcn.inst->ring_enc[r]; 2010 ring->wptr = 0; 2011 MMSCH_V2_0_INSERT_DIRECT_WT( 2012 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), 2013 lower_32_bits(ring->gpu_addr)); 2014 MMSCH_V2_0_INSERT_DIRECT_WT( 2015 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), 2016 upper_32_bits(ring->gpu_addr)); 2017 MMSCH_V2_0_INSERT_DIRECT_WT( 2018 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 2019 ring->ring_size / 4); 2020 } 2021 2022 ring = &adev->vcn.inst->ring_dec; 2023 ring->wptr = 0; 2024 MMSCH_V2_0_INSERT_DIRECT_WT( 2025 SOC15_REG_OFFSET(UVD, i, 2026 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 2027 lower_32_bits(ring->gpu_addr)); 2028 MMSCH_V2_0_INSERT_DIRECT_WT( 2029 SOC15_REG_OFFSET(UVD, i, 2030 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 2031 upper_32_bits(ring->gpu_addr)); 2032 /* force RBC into idle state */ 2033 tmp = order_base_2(ring->ring_size); 2034 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 2035 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 2036 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 2037 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 2038 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 2039 MMSCH_V2_0_INSERT_DIRECT_WT( 2040 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 2041 2042 /* add end packet */ 2043 tmp = sizeof(struct mmsch_v2_0_cmd_end); 2044 memcpy((void *)init_table, &end, tmp); 2045 table_size += (tmp / 4); 2046 header->vcn_table_size = table_size; 2047 2048 } 2049 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); 2050 } 2051 2052 static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2053 { 2054 struct amdgpu_device *adev = ip_block->adev; 2055 int i, j; 2056 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); 2057 uint32_t inst_off, is_powered; 2058 2059 if (!adev->vcn.ip_dump) 2060 return; 2061 2062 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2063 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2064 if (adev->vcn.harvest_config & (1 << i)) { 2065 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2066 continue; 2067 } 2068 2069 inst_off = i * reg_count; 2070 is_powered = (adev->vcn.ip_dump[inst_off] & 2071 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2072 2073 if (is_powered) { 2074 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2075 for (j = 0; j < reg_count; j++) 2076 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name, 2077 adev->vcn.ip_dump[inst_off + j]); 2078 } else { 2079 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2080 } 2081 } 2082 } 2083 2084 static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 2085 { 2086 struct amdgpu_device *adev = ip_block->adev; 2087 int i, j; 2088 bool is_powered; 2089 uint32_t inst_off; 2090 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); 2091 2092 if (!adev->vcn.ip_dump) 2093 return; 2094 2095 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2096 if (adev->vcn.harvest_config & (1 << i)) 2097 continue; 2098 2099 inst_off = i * reg_count; 2100 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2101 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 2102 is_powered = (adev->vcn.ip_dump[inst_off] & 2103 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2104 2105 if (is_powered) 2106 for (j = 1; j < reg_count; j++) 2107 adev->vcn.ip_dump[inst_off + j] = 2108 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i)); 2109 } 2110 } 2111 2112 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 2113 .name = "vcn_v2_0", 2114 .early_init = vcn_v2_0_early_init, 2115 .sw_init = vcn_v2_0_sw_init, 2116 .sw_fini = vcn_v2_0_sw_fini, 2117 .hw_init = vcn_v2_0_hw_init, 2118 .hw_fini = vcn_v2_0_hw_fini, 2119 .suspend = vcn_v2_0_suspend, 2120 .resume = vcn_v2_0_resume, 2121 .is_idle = vcn_v2_0_is_idle, 2122 .wait_for_idle = vcn_v2_0_wait_for_idle, 2123 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2124 .set_powergating_state = vcn_set_powergating_state, 2125 .dump_ip_state = vcn_v2_0_dump_ip_state, 2126 .print_ip_state = vcn_v2_0_print_ip_state, 2127 }; 2128 2129 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2130 .type = AMDGPU_RING_TYPE_VCN_DEC, 2131 .align_mask = 0xf, 2132 .secure_submission_supported = true, 2133 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2134 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2135 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2136 .emit_frame_size = 2137 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2138 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2139 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2140 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2141 6, 2142 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2143 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2144 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2145 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2146 .test_ring = vcn_v2_0_dec_ring_test_ring, 2147 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2148 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2149 .insert_start = vcn_v2_0_dec_ring_insert_start, 2150 .insert_end = vcn_v2_0_dec_ring_insert_end, 2151 .pad_ib = amdgpu_ring_generic_pad_ib, 2152 .begin_use = amdgpu_vcn_ring_begin_use, 2153 .end_use = amdgpu_vcn_ring_end_use, 2154 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2155 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2156 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2157 }; 2158 2159 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2160 .type = AMDGPU_RING_TYPE_VCN_ENC, 2161 .align_mask = 0x3f, 2162 .nop = VCN_ENC_CMD_NO_OP, 2163 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2164 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2165 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2166 .emit_frame_size = 2167 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2168 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2169 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2170 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2171 1, /* vcn_v2_0_enc_ring_insert_end */ 2172 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2173 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2174 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2175 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2176 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2177 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2178 .insert_nop = amdgpu_ring_insert_nop, 2179 .insert_end = vcn_v2_0_enc_ring_insert_end, 2180 .pad_ib = amdgpu_ring_generic_pad_ib, 2181 .begin_use = amdgpu_vcn_ring_begin_use, 2182 .end_use = amdgpu_vcn_ring_end_use, 2183 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2184 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2185 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2186 }; 2187 2188 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2189 { 2190 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2191 } 2192 2193 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2194 { 2195 int i; 2196 2197 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) 2198 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2199 } 2200 2201 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2202 .set = vcn_v2_0_set_interrupt_state, 2203 .process = vcn_v2_0_process_interrupt, 2204 }; 2205 2206 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2207 { 2208 adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1; 2209 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2210 } 2211 2212 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2213 { 2214 .type = AMD_IP_BLOCK_TYPE_VCN, 2215 .major = 2, 2216 .minor = 0, 2217 .rev = 0, 2218 .funcs = &vcn_v2_0_ip_funcs, 2219 }; 2220