1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable, 242 int inst) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 /* 249 * don't poweron vcn/jpeg when they are skipped. 250 */ 251 if (!is_vcn_enabled(smu->adev)) 252 return 0; 253 254 if (!smu->ppt_funcs->dpm_set_vcn_enable) 255 return 0; 256 257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 258 return 0; 259 260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 261 if (!ret) 262 atomic_set(&power_gate->vcn_gated[inst], !enable); 263 264 return ret; 265 } 266 267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 268 bool enable) 269 { 270 struct smu_power_context *smu_power = &smu->smu_power; 271 struct smu_power_gate *power_gate = &smu_power->power_gate; 272 int ret = 0; 273 274 if (!is_vcn_enabled(smu->adev)) 275 return 0; 276 277 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 278 return 0; 279 280 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 281 return 0; 282 283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 284 if (!ret) 285 atomic_set(&power_gate->jpeg_gated, !enable); 286 287 return ret; 288 } 289 290 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 291 bool enable) 292 { 293 struct smu_power_context *smu_power = &smu->smu_power; 294 struct smu_power_gate *power_gate = &smu_power->power_gate; 295 int ret = 0; 296 297 if (!smu->ppt_funcs->dpm_set_vpe_enable) 298 return 0; 299 300 if (atomic_read(&power_gate->vpe_gated) ^ enable) 301 return 0; 302 303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 304 if (!ret) 305 atomic_set(&power_gate->vpe_gated, !enable); 306 307 return ret; 308 } 309 310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 311 bool enable) 312 { 313 struct smu_power_context *smu_power = &smu->smu_power; 314 struct smu_power_gate *power_gate = &smu_power->power_gate; 315 int ret = 0; 316 317 if (!smu->adev->enable_umsch_mm) 318 return 0; 319 320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 321 return 0; 322 323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 324 return 0; 325 326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 327 if (!ret) 328 atomic_set(&power_gate->umsch_mm_gated, !enable); 329 330 return ret; 331 } 332 333 static int smu_set_mall_enable(struct smu_context *smu) 334 { 335 int ret = 0; 336 337 if (!smu->ppt_funcs->set_mall_enable) 338 return 0; 339 340 ret = smu->ppt_funcs->set_mall_enable(smu); 341 342 return ret; 343 } 344 345 /** 346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 347 * 348 * @handle: smu_context pointer 349 * @block_type: the IP block to power gate/ungate 350 * @gate: to power gate if true, ungate otherwise 351 * @inst: the instance of the IP block to power gate/ungate 352 * 353 * This API uses no smu->mutex lock protection due to: 354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 355 * This is guarded to be race condition free by the caller. 356 * 2. Or get called on user setting request of power_dpm_force_performance_level. 357 * Under this case, the smu->mutex lock protection is already enforced on 358 * the parent API smu_force_performance_level of the call path. 359 */ 360 static int smu_dpm_set_power_gate(void *handle, 361 uint32_t block_type, 362 bool gate, 363 int inst) 364 { 365 struct smu_context *smu = handle; 366 int ret = 0; 367 368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 369 dev_WARN(smu->adev->dev, 370 "SMU uninitialized but power %s requested for %u!\n", 371 gate ? "gate" : "ungate", block_type); 372 return -EOPNOTSUPP; 373 } 374 375 switch (block_type) { 376 /* 377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 379 */ 380 case AMD_IP_BLOCK_TYPE_UVD: 381 case AMD_IP_BLOCK_TYPE_VCN: 382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 385 gate ? "gate" : "ungate", inst); 386 break; 387 case AMD_IP_BLOCK_TYPE_GFX: 388 ret = smu_gfx_off_control(smu, gate); 389 if (ret) 390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 391 gate ? "enable" : "disable"); 392 break; 393 case AMD_IP_BLOCK_TYPE_SDMA: 394 ret = smu_powergate_sdma(smu, gate); 395 if (ret) 396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 397 gate ? "gate" : "ungate"); 398 break; 399 case AMD_IP_BLOCK_TYPE_JPEG: 400 ret = smu_dpm_set_jpeg_enable(smu, !gate); 401 if (ret) 402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 403 gate ? "gate" : "ungate"); 404 break; 405 case AMD_IP_BLOCK_TYPE_VPE: 406 ret = smu_dpm_set_vpe_enable(smu, !gate); 407 if (ret) 408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 409 gate ? "gate" : "ungate"); 410 break; 411 default: 412 dev_err(smu->adev->dev, "Unsupported block type!\n"); 413 return -EINVAL; 414 } 415 416 return ret; 417 } 418 419 /** 420 * smu_set_user_clk_dependencies - set user profile clock dependencies 421 * 422 * @smu: smu_context pointer 423 * @clk: enum smu_clk_type type 424 * 425 * Enable/Disable the clock dependency for the @clk type. 426 */ 427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 428 { 429 if (smu->adev->in_suspend) 430 return; 431 432 if (clk == SMU_MCLK) { 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_FCLK) { 436 /* MCLK takes precedence over FCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 442 } else if (clk == SMU_SOCCLK) { 443 /* MCLK takes precedence over SOCCLK */ 444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 445 return; 446 447 smu->user_dpm_profile.clk_dependency = 0; 448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 449 } else 450 /* Add clk dependencies here, if any */ 451 return; 452 } 453 454 /** 455 * smu_restore_dpm_user_profile - reinstate user dpm profile 456 * 457 * @smu: smu_context pointer 458 * 459 * Restore the saved user power configurations include power limit, 460 * clock frequencies, fan control mode and fan speed. 461 */ 462 static void smu_restore_dpm_user_profile(struct smu_context *smu) 463 { 464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 465 int ret = 0; 466 467 if (!smu->adev->in_suspend) 468 return; 469 470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 471 return; 472 473 /* Enable restore flag */ 474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 475 476 /* set the user dpm power limit */ 477 if (smu->user_dpm_profile.power_limit) { 478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 479 if (ret) 480 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 481 } 482 483 /* set the user dpm clock configurations */ 484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 485 enum smu_clk_type clk_type; 486 487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 488 /* 489 * Iterate over smu clk type and force the saved user clk 490 * configs, skip if clock dependency is enabled 491 */ 492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 493 smu->user_dpm_profile.clk_mask[clk_type]) { 494 ret = smu_force_smuclk_levels(smu, clk_type, 495 smu->user_dpm_profile.clk_mask[clk_type]); 496 if (ret) 497 dev_err(smu->adev->dev, 498 "Failed to set clock type = %d\n", clk_type); 499 } 500 } 501 } 502 503 /* set the user dpm fan configurations */ 504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 507 if (ret != -EOPNOTSUPP) { 508 smu->user_dpm_profile.fan_speed_pwm = 0; 509 smu->user_dpm_profile.fan_speed_rpm = 0; 510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 512 } 513 514 if (smu->user_dpm_profile.fan_speed_pwm) { 515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 516 if (ret != -EOPNOTSUPP) 517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 518 } 519 520 if (smu->user_dpm_profile.fan_speed_rpm) { 521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 522 if (ret != -EOPNOTSUPP) 523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 524 } 525 } 526 527 /* Restore user customized OD settings */ 528 if (smu->user_dpm_profile.user_od) { 529 if (smu->ppt_funcs->restore_user_od_settings) { 530 ret = smu->ppt_funcs->restore_user_od_settings(smu); 531 if (ret) 532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 533 } 534 } 535 536 /* Disable restore flag */ 537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 538 } 539 540 static int smu_get_power_num_states(void *handle, 541 struct pp_states_info *state_info) 542 { 543 if (!state_info) 544 return -EINVAL; 545 546 /* not support power state */ 547 memset(state_info, 0, sizeof(struct pp_states_info)); 548 state_info->nums = 1; 549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 550 551 return 0; 552 } 553 554 bool is_support_sw_smu(struct amdgpu_device *adev) 555 { 556 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 557 if (adev->asic_type == CHIP_VEGA20) 558 return false; 559 560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 562 return true; 563 564 return false; 565 } 566 567 bool is_support_cclk_dpm(struct amdgpu_device *adev) 568 { 569 struct smu_context *smu = adev->powerplay.pp_handle; 570 571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 572 return false; 573 574 return true; 575 } 576 577 578 static int smu_sys_get_pp_table(void *handle, 579 char **table) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 588 return -EINVAL; 589 590 if (smu_table->hardcode_pptable) 591 *table = smu_table->hardcode_pptable; 592 else 593 *table = smu_table->power_play_table; 594 595 return smu_table->power_play_table_size; 596 } 597 598 static int smu_sys_set_pp_table(void *handle, 599 const char *buf, 600 size_t size) 601 { 602 struct smu_context *smu = handle; 603 struct smu_table_context *smu_table = &smu->smu_table; 604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 605 int ret = 0; 606 607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 608 return -EOPNOTSUPP; 609 610 if (header->usStructureSize != size) { 611 dev_err(smu->adev->dev, "pp table size not matched !\n"); 612 return -EIO; 613 } 614 615 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 616 kfree(smu_table->hardcode_pptable); 617 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 618 if (!smu_table->hardcode_pptable) 619 return -ENOMEM; 620 } 621 622 memcpy(smu_table->hardcode_pptable, buf, size); 623 smu_table->power_play_table = smu_table->hardcode_pptable; 624 smu_table->power_play_table_size = size; 625 626 /* 627 * Special hw_fini action(for Navi1x, the DPMs disablement will be 628 * skipped) may be needed for custom pptable uploading. 629 */ 630 smu->uploading_custom_pp_table = true; 631 632 ret = smu_reset(smu); 633 if (ret) 634 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 635 636 smu->uploading_custom_pp_table = false; 637 638 return ret; 639 } 640 641 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 642 { 643 struct smu_feature *feature = &smu->smu_feature; 644 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 645 int ret = 0; 646 647 /* 648 * With SCPM enabled, the allowed featuremasks setting(via 649 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 650 * That means there is no way to let PMFW knows the settings below. 651 * Thus, we just assume all the features are allowed under 652 * such scenario. 653 */ 654 if (smu->adev->scpm_enabled) { 655 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 656 return 0; 657 } 658 659 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 660 661 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 662 SMU_FEATURE_MAX/32); 663 if (ret) 664 return ret; 665 666 bitmap_or(feature->allowed, feature->allowed, 667 (unsigned long *)allowed_feature_mask, 668 feature->feature_num); 669 670 return ret; 671 } 672 673 static int smu_set_funcs(struct amdgpu_device *adev) 674 { 675 struct smu_context *smu = adev->powerplay.pp_handle; 676 677 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 678 smu->od_enabled = true; 679 680 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 681 case IP_VERSION(11, 0, 0): 682 case IP_VERSION(11, 0, 5): 683 case IP_VERSION(11, 0, 9): 684 navi10_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 0, 7): 687 case IP_VERSION(11, 0, 11): 688 case IP_VERSION(11, 0, 12): 689 case IP_VERSION(11, 0, 13): 690 sienna_cichlid_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(12, 0, 0): 693 case IP_VERSION(12, 0, 1): 694 renoir_set_ppt_funcs(smu); 695 break; 696 case IP_VERSION(11, 5, 0): 697 case IP_VERSION(11, 5, 2): 698 vangogh_set_ppt_funcs(smu); 699 break; 700 case IP_VERSION(13, 0, 1): 701 case IP_VERSION(13, 0, 3): 702 case IP_VERSION(13, 0, 8): 703 yellow_carp_set_ppt_funcs(smu); 704 break; 705 case IP_VERSION(13, 0, 4): 706 case IP_VERSION(13, 0, 11): 707 smu_v13_0_4_set_ppt_funcs(smu); 708 break; 709 case IP_VERSION(13, 0, 5): 710 smu_v13_0_5_set_ppt_funcs(smu); 711 break; 712 case IP_VERSION(11, 0, 8): 713 cyan_skillfish_set_ppt_funcs(smu); 714 break; 715 case IP_VERSION(11, 0, 2): 716 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 717 arcturus_set_ppt_funcs(smu); 718 /* OD is not supported on Arcturus */ 719 smu->od_enabled = false; 720 break; 721 case IP_VERSION(13, 0, 2): 722 aldebaran_set_ppt_funcs(smu); 723 /* Enable pp_od_clk_voltage node */ 724 smu->od_enabled = true; 725 break; 726 case IP_VERSION(13, 0, 0): 727 case IP_VERSION(13, 0, 10): 728 smu_v13_0_0_set_ppt_funcs(smu); 729 break; 730 case IP_VERSION(13, 0, 6): 731 case IP_VERSION(13, 0, 14): 732 case IP_VERSION(13, 0, 12): 733 smu_v13_0_6_set_ppt_funcs(smu); 734 /* Enable pp_od_clk_voltage node */ 735 smu->od_enabled = true; 736 break; 737 case IP_VERSION(13, 0, 7): 738 smu_v13_0_7_set_ppt_funcs(smu); 739 break; 740 case IP_VERSION(14, 0, 0): 741 case IP_VERSION(14, 0, 1): 742 case IP_VERSION(14, 0, 4): 743 case IP_VERSION(14, 0, 5): 744 smu_v14_0_0_set_ppt_funcs(smu); 745 break; 746 case IP_VERSION(14, 0, 2): 747 case IP_VERSION(14, 0, 3): 748 smu_v14_0_2_set_ppt_funcs(smu); 749 break; 750 default: 751 return -EINVAL; 752 } 753 754 return 0; 755 } 756 757 static int smu_early_init(struct amdgpu_ip_block *ip_block) 758 { 759 struct amdgpu_device *adev = ip_block->adev; 760 struct smu_context *smu; 761 int r; 762 763 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 764 if (!smu) 765 return -ENOMEM; 766 767 smu->adev = adev; 768 smu->pm_enabled = !!amdgpu_dpm; 769 smu->is_apu = false; 770 smu->smu_baco.state = SMU_BACO_STATE_NONE; 771 smu->smu_baco.platform_support = false; 772 smu->smu_baco.maco_support = false; 773 smu->user_dpm_profile.fan_mode = -1; 774 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 775 776 mutex_init(&smu->message_lock); 777 778 adev->powerplay.pp_handle = smu; 779 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 780 781 r = smu_set_funcs(adev); 782 if (r) 783 return r; 784 return smu_init_microcode(smu); 785 } 786 787 static int smu_set_default_dpm_table(struct smu_context *smu) 788 { 789 struct amdgpu_device *adev = smu->adev; 790 struct smu_power_context *smu_power = &smu->smu_power; 791 struct smu_power_gate *power_gate = &smu_power->power_gate; 792 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 793 int ret = 0; 794 795 if (!smu->ppt_funcs->set_default_dpm_table) 796 return 0; 797 798 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 799 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 800 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 801 } 802 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 803 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 804 805 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 806 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 807 ret = smu_dpm_set_vcn_enable(smu, true, i); 808 if (ret) 809 return ret; 810 } 811 } 812 813 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 814 ret = smu_dpm_set_jpeg_enable(smu, true); 815 if (ret) 816 goto err_out; 817 } 818 819 ret = smu->ppt_funcs->set_default_dpm_table(smu); 820 if (ret) 821 dev_err(smu->adev->dev, 822 "Failed to setup default dpm clock tables!\n"); 823 824 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 825 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 826 err_out: 827 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 828 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 829 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 830 } 831 832 return ret; 833 } 834 835 static int smu_apply_default_config_table_settings(struct smu_context *smu) 836 { 837 struct amdgpu_device *adev = smu->adev; 838 int ret = 0; 839 840 ret = smu_get_default_config_table_settings(smu, 841 &adev->pm.config_table); 842 if (ret) 843 return ret; 844 845 return smu_set_config_table(smu, &adev->pm.config_table); 846 } 847 848 static int smu_late_init(struct amdgpu_ip_block *ip_block) 849 { 850 struct amdgpu_device *adev = ip_block->adev; 851 struct smu_context *smu = adev->powerplay.pp_handle; 852 int ret = 0; 853 854 smu_set_fine_grain_gfx_freq_parameters(smu); 855 856 if (!smu->pm_enabled) 857 return 0; 858 859 ret = smu_post_init(smu); 860 if (ret) { 861 dev_err(adev->dev, "Failed to post smu init!\n"); 862 return ret; 863 } 864 865 /* 866 * Explicitly notify PMFW the power mode the system in. Since 867 * the PMFW may boot the ASIC with a different mode. 868 * For those supporting ACDC switch via gpio, PMFW will 869 * handle the switch automatically. Driver involvement 870 * is unnecessary. 871 */ 872 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 873 smu_set_ac_dc(smu); 874 875 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 876 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 877 return 0; 878 879 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 880 ret = smu_set_default_od_settings(smu); 881 if (ret) { 882 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 883 return ret; 884 } 885 } 886 887 ret = smu_populate_umd_state_clk(smu); 888 if (ret) { 889 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 890 return ret; 891 } 892 893 ret = smu_get_asic_power_limits(smu, 894 &smu->current_power_limit, 895 &smu->default_power_limit, 896 &smu->max_power_limit, 897 &smu->min_power_limit); 898 if (ret) { 899 dev_err(adev->dev, "Failed to get asic power limits!\n"); 900 return ret; 901 } 902 903 if (!amdgpu_sriov_vf(adev)) 904 smu_get_unique_id(smu); 905 906 smu_get_fan_parameters(smu); 907 908 smu_handle_task(smu, 909 smu->smu_dpm.dpm_level, 910 AMD_PP_TASK_COMPLETE_INIT); 911 912 ret = smu_apply_default_config_table_settings(smu); 913 if (ret && (ret != -EOPNOTSUPP)) { 914 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 915 return ret; 916 } 917 918 smu_restore_dpm_user_profile(smu); 919 920 return 0; 921 } 922 923 static int smu_init_fb_allocations(struct smu_context *smu) 924 { 925 struct amdgpu_device *adev = smu->adev; 926 struct smu_table_context *smu_table = &smu->smu_table; 927 struct smu_table *tables = smu_table->tables; 928 struct smu_table *driver_table = &(smu_table->driver_table); 929 uint32_t max_table_size = 0; 930 int ret, i; 931 932 /* VRAM allocation for tool table */ 933 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 934 ret = amdgpu_bo_create_kernel(adev, 935 tables[SMU_TABLE_PMSTATUSLOG].size, 936 tables[SMU_TABLE_PMSTATUSLOG].align, 937 tables[SMU_TABLE_PMSTATUSLOG].domain, 938 &tables[SMU_TABLE_PMSTATUSLOG].bo, 939 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 940 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 941 if (ret) { 942 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 943 return ret; 944 } 945 } 946 947 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 948 /* VRAM allocation for driver table */ 949 for (i = 0; i < SMU_TABLE_COUNT; i++) { 950 if (tables[i].size == 0) 951 continue; 952 953 /* If one of the tables has VRAM domain restriction, keep it in 954 * VRAM 955 */ 956 if ((tables[i].domain & 957 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 958 AMDGPU_GEM_DOMAIN_VRAM) 959 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 960 961 if (i == SMU_TABLE_PMSTATUSLOG) 962 continue; 963 964 if (max_table_size < tables[i].size) 965 max_table_size = tables[i].size; 966 } 967 968 driver_table->size = max_table_size; 969 driver_table->align = PAGE_SIZE; 970 971 ret = amdgpu_bo_create_kernel(adev, 972 driver_table->size, 973 driver_table->align, 974 driver_table->domain, 975 &driver_table->bo, 976 &driver_table->mc_address, 977 &driver_table->cpu_addr); 978 if (ret) { 979 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 980 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 981 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 982 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 983 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 984 } 985 986 return ret; 987 } 988 989 static int smu_fini_fb_allocations(struct smu_context *smu) 990 { 991 struct smu_table_context *smu_table = &smu->smu_table; 992 struct smu_table *tables = smu_table->tables; 993 struct smu_table *driver_table = &(smu_table->driver_table); 994 995 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 996 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 997 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 998 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 999 1000 amdgpu_bo_free_kernel(&driver_table->bo, 1001 &driver_table->mc_address, 1002 &driver_table->cpu_addr); 1003 1004 return 0; 1005 } 1006 1007 /** 1008 * smu_alloc_memory_pool - allocate memory pool in the system memory 1009 * 1010 * @smu: amdgpu_device pointer 1011 * 1012 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1013 * and DramLogSetDramAddr can notify it changed. 1014 * 1015 * Returns 0 on success, error on failure. 1016 */ 1017 static int smu_alloc_memory_pool(struct smu_context *smu) 1018 { 1019 struct amdgpu_device *adev = smu->adev; 1020 struct smu_table_context *smu_table = &smu->smu_table; 1021 struct smu_table *memory_pool = &smu_table->memory_pool; 1022 uint64_t pool_size = smu->pool_size; 1023 int ret = 0; 1024 1025 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1026 return ret; 1027 1028 memory_pool->size = pool_size; 1029 memory_pool->align = PAGE_SIZE; 1030 memory_pool->domain = 1031 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1032 AMDGPU_GEM_DOMAIN_VRAM : 1033 AMDGPU_GEM_DOMAIN_GTT; 1034 1035 switch (pool_size) { 1036 case SMU_MEMORY_POOL_SIZE_256_MB: 1037 case SMU_MEMORY_POOL_SIZE_512_MB: 1038 case SMU_MEMORY_POOL_SIZE_1_GB: 1039 case SMU_MEMORY_POOL_SIZE_2_GB: 1040 ret = amdgpu_bo_create_kernel(adev, 1041 memory_pool->size, 1042 memory_pool->align, 1043 memory_pool->domain, 1044 &memory_pool->bo, 1045 &memory_pool->mc_address, 1046 &memory_pool->cpu_addr); 1047 if (ret) 1048 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1049 break; 1050 default: 1051 break; 1052 } 1053 1054 return ret; 1055 } 1056 1057 static int smu_free_memory_pool(struct smu_context *smu) 1058 { 1059 struct smu_table_context *smu_table = &smu->smu_table; 1060 struct smu_table *memory_pool = &smu_table->memory_pool; 1061 1062 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1063 return 0; 1064 1065 amdgpu_bo_free_kernel(&memory_pool->bo, 1066 &memory_pool->mc_address, 1067 &memory_pool->cpu_addr); 1068 1069 memset(memory_pool, 0, sizeof(struct smu_table)); 1070 1071 return 0; 1072 } 1073 1074 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1075 { 1076 struct smu_table_context *smu_table = &smu->smu_table; 1077 struct smu_table *dummy_read_1_table = 1078 &smu_table->dummy_read_1_table; 1079 struct amdgpu_device *adev = smu->adev; 1080 int ret = 0; 1081 1082 if (!dummy_read_1_table->size) 1083 return 0; 1084 1085 ret = amdgpu_bo_create_kernel(adev, 1086 dummy_read_1_table->size, 1087 dummy_read_1_table->align, 1088 dummy_read_1_table->domain, 1089 &dummy_read_1_table->bo, 1090 &dummy_read_1_table->mc_address, 1091 &dummy_read_1_table->cpu_addr); 1092 if (ret) 1093 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1094 1095 return ret; 1096 } 1097 1098 static void smu_free_dummy_read_table(struct smu_context *smu) 1099 { 1100 struct smu_table_context *smu_table = &smu->smu_table; 1101 struct smu_table *dummy_read_1_table = 1102 &smu_table->dummy_read_1_table; 1103 1104 1105 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1106 &dummy_read_1_table->mc_address, 1107 &dummy_read_1_table->cpu_addr); 1108 1109 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1110 } 1111 1112 static int smu_smc_table_sw_init(struct smu_context *smu) 1113 { 1114 int ret; 1115 1116 /** 1117 * Create smu_table structure, and init smc tables such as 1118 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1119 */ 1120 ret = smu_init_smc_tables(smu); 1121 if (ret) { 1122 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1123 return ret; 1124 } 1125 1126 /** 1127 * Create smu_power_context structure, and allocate smu_dpm_context and 1128 * context size to fill the smu_power_context data. 1129 */ 1130 ret = smu_init_power(smu); 1131 if (ret) { 1132 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1133 return ret; 1134 } 1135 1136 /* 1137 * allocate vram bos to store smc table contents. 1138 */ 1139 ret = smu_init_fb_allocations(smu); 1140 if (ret) 1141 return ret; 1142 1143 ret = smu_alloc_memory_pool(smu); 1144 if (ret) 1145 return ret; 1146 1147 ret = smu_alloc_dummy_read_table(smu); 1148 if (ret) 1149 return ret; 1150 1151 ret = smu_i2c_init(smu); 1152 if (ret) 1153 return ret; 1154 1155 return 0; 1156 } 1157 1158 static int smu_smc_table_sw_fini(struct smu_context *smu) 1159 { 1160 int ret; 1161 1162 smu_i2c_fini(smu); 1163 1164 smu_free_dummy_read_table(smu); 1165 1166 ret = smu_free_memory_pool(smu); 1167 if (ret) 1168 return ret; 1169 1170 ret = smu_fini_fb_allocations(smu); 1171 if (ret) 1172 return ret; 1173 1174 ret = smu_fini_power(smu); 1175 if (ret) { 1176 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1177 return ret; 1178 } 1179 1180 ret = smu_fini_smc_tables(smu); 1181 if (ret) { 1182 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1183 return ret; 1184 } 1185 1186 return 0; 1187 } 1188 1189 static void smu_throttling_logging_work_fn(struct work_struct *work) 1190 { 1191 struct smu_context *smu = container_of(work, struct smu_context, 1192 throttling_logging_work); 1193 1194 smu_log_thermal_throttling(smu); 1195 } 1196 1197 static void smu_interrupt_work_fn(struct work_struct *work) 1198 { 1199 struct smu_context *smu = container_of(work, struct smu_context, 1200 interrupt_work); 1201 1202 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1203 smu->ppt_funcs->interrupt_work(smu); 1204 } 1205 1206 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1207 { 1208 struct smu_context *smu = 1209 container_of(work, struct smu_context, swctf_delayed_work.work); 1210 struct smu_temperature_range *range = 1211 &smu->thermal_range; 1212 struct amdgpu_device *adev = smu->adev; 1213 uint32_t hotspot_tmp, size; 1214 1215 /* 1216 * If the hotspot temperature is confirmed as below SW CTF setting point 1217 * after the delay enforced, nothing will be done. 1218 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1219 */ 1220 if (range->software_shutdown_temp && 1221 smu->ppt_funcs->read_sensor && 1222 !smu->ppt_funcs->read_sensor(smu, 1223 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1224 &hotspot_tmp, 1225 &size) && 1226 hotspot_tmp / 1000 < range->software_shutdown_temp) 1227 return; 1228 1229 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1230 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1231 orderly_poweroff(true); 1232 } 1233 1234 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1235 { 1236 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1237 struct smu_dpm_policy_ctxt *policy_ctxt; 1238 struct smu_dpm_policy *policy; 1239 1240 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1241 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1242 if (policy) 1243 policy->current_level = XGMI_PLPD_DEFAULT; 1244 return; 1245 } 1246 1247 /* PMFW put PLPD into default policy after enabling the feature */ 1248 if (smu_feature_is_enabled(smu, 1249 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1250 if (policy) 1251 policy->current_level = XGMI_PLPD_DEFAULT; 1252 } else { 1253 policy_ctxt = dpm_ctxt->dpm_policies; 1254 if (policy_ctxt) 1255 policy_ctxt->policy_mask &= 1256 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1257 } 1258 } 1259 1260 static void smu_init_power_profile(struct smu_context *smu) 1261 { 1262 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1263 smu->power_profile_mode = 1264 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1265 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1266 } 1267 1268 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1269 { 1270 struct amdgpu_device *adev = ip_block->adev; 1271 struct smu_context *smu = adev->powerplay.pp_handle; 1272 int i, ret; 1273 1274 smu->pool_size = adev->pm.smu_prv_buffer_size; 1275 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1276 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1277 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1278 1279 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1280 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1281 atomic64_set(&smu->throttle_int_counter, 0); 1282 smu->watermarks_bitmap = 0; 1283 1284 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1285 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1286 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1287 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1288 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1289 1290 smu_init_power_profile(smu); 1291 smu->display_config = &adev->pm.pm_display_cfg; 1292 1293 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1294 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1295 1296 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1297 smu_swctf_delayed_work_handler); 1298 1299 ret = smu_smc_table_sw_init(smu); 1300 if (ret) { 1301 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1302 return ret; 1303 } 1304 1305 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1306 ret = smu_get_vbios_bootup_values(smu); 1307 if (ret) { 1308 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1309 return ret; 1310 } 1311 1312 ret = smu_init_pptable_microcode(smu); 1313 if (ret) { 1314 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1315 return ret; 1316 } 1317 1318 ret = smu_register_irq_handler(smu); 1319 if (ret) { 1320 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1321 return ret; 1322 } 1323 1324 /* If there is no way to query fan control mode, fan control is not supported */ 1325 if (!smu->ppt_funcs->get_fan_control_mode) 1326 smu->adev->pm.no_fan = true; 1327 1328 return 0; 1329 } 1330 1331 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1332 { 1333 struct amdgpu_device *adev = ip_block->adev; 1334 struct smu_context *smu = adev->powerplay.pp_handle; 1335 int ret; 1336 1337 ret = smu_smc_table_sw_fini(smu); 1338 if (ret) { 1339 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1340 return ret; 1341 } 1342 1343 if (smu->custom_profile_params) { 1344 kfree(smu->custom_profile_params); 1345 smu->custom_profile_params = NULL; 1346 } 1347 1348 smu_fini_microcode(smu); 1349 1350 return 0; 1351 } 1352 1353 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1354 { 1355 struct amdgpu_device *adev = smu->adev; 1356 struct smu_temperature_range *range = 1357 &smu->thermal_range; 1358 int ret = 0; 1359 1360 if (!smu->ppt_funcs->get_thermal_temperature_range) 1361 return 0; 1362 1363 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1364 if (ret) 1365 return ret; 1366 1367 adev->pm.dpm.thermal.min_temp = range->min; 1368 adev->pm.dpm.thermal.max_temp = range->max; 1369 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1370 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1371 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1372 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1373 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1374 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1375 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1376 1377 return ret; 1378 } 1379 1380 /** 1381 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1382 * 1383 * @smu: smu_context pointer 1384 * 1385 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1386 * Returns 0 on success, error on failure. 1387 */ 1388 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1389 { 1390 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1391 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1392 struct amdgpu_device *adev = smu->adev; 1393 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1394 uint64_t start, end; 1395 int ret, i, j; 1396 1397 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1398 if (ret) { 1399 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1400 return ret; 1401 } 1402 1403 /* 1404 * The exclusion ranges array we got might be filled with holes and duplicate 1405 * entries. For example: 1406 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1407 * We need to do some sortups to eliminate those holes and duplicate entries. 1408 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1409 */ 1410 for (i = 0; i < num_of_wbrf_ranges; i++) { 1411 start = wifi_bands[i].start; 1412 end = wifi_bands[i].end; 1413 1414 /* get the last valid entry to fill the intermediate hole */ 1415 if (!start && !end) { 1416 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1417 if (wifi_bands[j].start && wifi_bands[j].end) 1418 break; 1419 1420 /* no valid entry left */ 1421 if (j <= i) 1422 break; 1423 1424 start = wifi_bands[i].start = wifi_bands[j].start; 1425 end = wifi_bands[i].end = wifi_bands[j].end; 1426 wifi_bands[j].start = 0; 1427 wifi_bands[j].end = 0; 1428 num_of_wbrf_ranges = j; 1429 } 1430 1431 /* eliminate duplicate entries */ 1432 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1433 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1434 wifi_bands[j].start = 0; 1435 wifi_bands[j].end = 0; 1436 } 1437 } 1438 } 1439 1440 /* Send the sorted wifi_bands to PMFW */ 1441 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1442 /* Try to set the wifi_bands again */ 1443 if (unlikely(ret == -EBUSY)) { 1444 mdelay(5); 1445 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1446 } 1447 1448 return ret; 1449 } 1450 1451 /** 1452 * smu_wbrf_event_handler - handle notify events 1453 * 1454 * @nb: notifier block 1455 * @action: event type 1456 * @_arg: event data 1457 * 1458 * Calls relevant amdgpu function in response to wbrf event 1459 * notification from kernel. 1460 */ 1461 static int smu_wbrf_event_handler(struct notifier_block *nb, 1462 unsigned long action, void *_arg) 1463 { 1464 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1465 1466 switch (action) { 1467 case WBRF_CHANGED: 1468 schedule_delayed_work(&smu->wbrf_delayed_work, 1469 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1470 break; 1471 default: 1472 return NOTIFY_DONE; 1473 } 1474 1475 return NOTIFY_OK; 1476 } 1477 1478 /** 1479 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1480 * 1481 * @work: struct work_struct pointer 1482 * 1483 * Flood is over and driver will consume the latest exclusion ranges. 1484 */ 1485 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1486 { 1487 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1488 1489 smu_wbrf_handle_exclusion_ranges(smu); 1490 } 1491 1492 /** 1493 * smu_wbrf_support_check - check wbrf support 1494 * 1495 * @smu: smu_context pointer 1496 * 1497 * Verifies the ACPI interface whether wbrf is supported. 1498 */ 1499 static void smu_wbrf_support_check(struct smu_context *smu) 1500 { 1501 struct amdgpu_device *adev = smu->adev; 1502 1503 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1504 acpi_amd_wbrf_supported_consumer(adev->dev); 1505 1506 if (smu->wbrf_supported) 1507 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1508 } 1509 1510 /** 1511 * smu_wbrf_init - init driver wbrf support 1512 * 1513 * @smu: smu_context pointer 1514 * 1515 * Verifies the AMD ACPI interfaces and registers with the wbrf 1516 * notifier chain if wbrf feature is supported. 1517 * Returns 0 on success, error on failure. 1518 */ 1519 static int smu_wbrf_init(struct smu_context *smu) 1520 { 1521 int ret; 1522 1523 if (!smu->wbrf_supported) 1524 return 0; 1525 1526 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1527 1528 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1529 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1530 if (ret) 1531 return ret; 1532 1533 /* 1534 * Some wifiband exclusion ranges may be already there 1535 * before our driver loaded. To make sure our driver 1536 * is awared of those exclusion ranges. 1537 */ 1538 schedule_delayed_work(&smu->wbrf_delayed_work, 1539 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1540 1541 return 0; 1542 } 1543 1544 /** 1545 * smu_wbrf_fini - tear down driver wbrf support 1546 * 1547 * @smu: smu_context pointer 1548 * 1549 * Unregisters with the wbrf notifier chain. 1550 */ 1551 static void smu_wbrf_fini(struct smu_context *smu) 1552 { 1553 if (!smu->wbrf_supported) 1554 return; 1555 1556 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1557 1558 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1559 } 1560 1561 static int smu_smc_hw_setup(struct smu_context *smu) 1562 { 1563 struct smu_feature *feature = &smu->smu_feature; 1564 struct amdgpu_device *adev = smu->adev; 1565 uint8_t pcie_gen = 0, pcie_width = 0; 1566 uint64_t features_supported; 1567 int ret = 0; 1568 1569 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1570 case IP_VERSION(11, 0, 7): 1571 case IP_VERSION(11, 0, 11): 1572 case IP_VERSION(11, 5, 0): 1573 case IP_VERSION(11, 5, 2): 1574 case IP_VERSION(11, 0, 12): 1575 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1576 dev_info(adev->dev, "dpm has been enabled\n"); 1577 ret = smu_system_features_control(smu, true); 1578 if (ret) 1579 dev_err(adev->dev, "Failed system features control!\n"); 1580 return ret; 1581 } 1582 break; 1583 default: 1584 break; 1585 } 1586 1587 ret = smu_init_display_count(smu, 0); 1588 if (ret) { 1589 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1590 return ret; 1591 } 1592 1593 ret = smu_set_driver_table_location(smu); 1594 if (ret) { 1595 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1596 return ret; 1597 } 1598 1599 /* 1600 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1601 */ 1602 ret = smu_set_tool_table_location(smu); 1603 if (ret) { 1604 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1605 return ret; 1606 } 1607 1608 /* 1609 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1610 * pool location. 1611 */ 1612 ret = smu_notify_memory_pool_location(smu); 1613 if (ret) { 1614 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1615 return ret; 1616 } 1617 1618 /* 1619 * It is assumed the pptable used before runpm is same as 1620 * the one used afterwards. Thus, we can reuse the stored 1621 * copy and do not need to resetup the pptable again. 1622 */ 1623 if (!adev->in_runpm) { 1624 ret = smu_setup_pptable(smu); 1625 if (ret) { 1626 dev_err(adev->dev, "Failed to setup pptable!\n"); 1627 return ret; 1628 } 1629 } 1630 1631 /* smu_dump_pptable(smu); */ 1632 1633 /* 1634 * With SCPM enabled, PSP is responsible for the PPTable transferring 1635 * (to SMU). Driver involvement is not needed and permitted. 1636 */ 1637 if (!adev->scpm_enabled) { 1638 /* 1639 * Copy pptable bo in the vram to smc with SMU MSGs such as 1640 * SetDriverDramAddr and TransferTableDram2Smu. 1641 */ 1642 ret = smu_write_pptable(smu); 1643 if (ret) { 1644 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1645 return ret; 1646 } 1647 } 1648 1649 /* issue Run*Btc msg */ 1650 ret = smu_run_btc(smu); 1651 if (ret) 1652 return ret; 1653 1654 /* Enable UclkShadow on wbrf supported */ 1655 if (smu->wbrf_supported) { 1656 ret = smu_enable_uclk_shadow(smu, true); 1657 if (ret) { 1658 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1659 return ret; 1660 } 1661 } 1662 1663 /* 1664 * With SCPM enabled, these actions(and relevant messages) are 1665 * not needed and permitted. 1666 */ 1667 if (!adev->scpm_enabled) { 1668 ret = smu_feature_set_allowed_mask(smu); 1669 if (ret) { 1670 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1671 return ret; 1672 } 1673 } 1674 1675 ret = smu_system_features_control(smu, true); 1676 if (ret) { 1677 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1678 return ret; 1679 } 1680 1681 smu_init_xgmi_plpd_mode(smu); 1682 1683 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1684 if (ret) { 1685 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1686 return ret; 1687 } 1688 bitmap_copy(feature->supported, 1689 (unsigned long *)&features_supported, 1690 feature->feature_num); 1691 1692 if (!smu_is_dpm_running(smu)) 1693 dev_info(adev->dev, "dpm has been disabled\n"); 1694 1695 /* 1696 * Set initialized values (get from vbios) to dpm tables context such as 1697 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1698 * type of clks. 1699 */ 1700 ret = smu_set_default_dpm_table(smu); 1701 if (ret) { 1702 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1703 return ret; 1704 } 1705 1706 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1707 pcie_gen = 4; 1708 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1709 pcie_gen = 3; 1710 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1711 pcie_gen = 2; 1712 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1713 pcie_gen = 1; 1714 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1715 pcie_gen = 0; 1716 1717 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1718 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1719 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1720 */ 1721 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1722 pcie_width = 7; 1723 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1724 pcie_width = 6; 1725 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1726 pcie_width = 5; 1727 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1728 pcie_width = 4; 1729 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1730 pcie_width = 3; 1731 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1732 pcie_width = 2; 1733 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1734 pcie_width = 1; 1735 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1736 if (ret) { 1737 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1738 return ret; 1739 } 1740 1741 ret = smu_get_thermal_temperature_range(smu); 1742 if (ret) { 1743 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1744 return ret; 1745 } 1746 1747 ret = smu_enable_thermal_alert(smu); 1748 if (ret) { 1749 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1750 return ret; 1751 } 1752 1753 ret = smu_notify_display_change(smu); 1754 if (ret) { 1755 dev_err(adev->dev, "Failed to notify display change!\n"); 1756 return ret; 1757 } 1758 1759 /* 1760 * Set min deep sleep dce fclk with bootup value from vbios via 1761 * SetMinDeepSleepDcefclk MSG. 1762 */ 1763 ret = smu_set_min_dcef_deep_sleep(smu, 1764 smu->smu_table.boot_values.dcefclk / 100); 1765 if (ret) { 1766 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1767 return ret; 1768 } 1769 1770 /* Init wbrf support. Properly setup the notifier */ 1771 ret = smu_wbrf_init(smu); 1772 if (ret) 1773 dev_err(adev->dev, "Error during wbrf init call\n"); 1774 1775 return ret; 1776 } 1777 1778 static int smu_start_smc_engine(struct smu_context *smu) 1779 { 1780 struct amdgpu_device *adev = smu->adev; 1781 int ret = 0; 1782 1783 smu->smc_fw_state = SMU_FW_INIT; 1784 1785 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1786 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1787 if (smu->ppt_funcs->load_microcode) { 1788 ret = smu->ppt_funcs->load_microcode(smu); 1789 if (ret) 1790 return ret; 1791 } 1792 } 1793 } 1794 1795 if (smu->ppt_funcs->check_fw_status) { 1796 ret = smu->ppt_funcs->check_fw_status(smu); 1797 if (ret) { 1798 dev_err(adev->dev, "SMC is not ready\n"); 1799 return ret; 1800 } 1801 } 1802 1803 /* 1804 * Send msg GetDriverIfVersion to check if the return value is equal 1805 * with DRIVER_IF_VERSION of smc header. 1806 */ 1807 ret = smu_check_fw_version(smu); 1808 if (ret) 1809 return ret; 1810 1811 return ret; 1812 } 1813 1814 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1815 { 1816 int i, ret; 1817 struct amdgpu_device *adev = ip_block->adev; 1818 struct smu_context *smu = adev->powerplay.pp_handle; 1819 1820 if (amdgpu_sriov_multi_vf_mode(adev)) { 1821 smu->pm_enabled = false; 1822 return 0; 1823 } 1824 1825 ret = smu_start_smc_engine(smu); 1826 if (ret) { 1827 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1828 return ret; 1829 } 1830 1831 /* 1832 * Check whether wbrf is supported. This needs to be done 1833 * before SMU setup starts since part of SMU configuration 1834 * relies on this. 1835 */ 1836 smu_wbrf_support_check(smu); 1837 1838 if (smu->is_apu) { 1839 ret = smu_set_gfx_imu_enable(smu); 1840 if (ret) 1841 return ret; 1842 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1843 smu_dpm_set_vcn_enable(smu, true, i); 1844 smu_dpm_set_jpeg_enable(smu, true); 1845 smu_dpm_set_vpe_enable(smu, true); 1846 smu_dpm_set_umsch_mm_enable(smu, true); 1847 smu_set_mall_enable(smu); 1848 smu_set_gfx_cgpg(smu, true); 1849 } 1850 1851 if (!smu->pm_enabled) 1852 return 0; 1853 1854 ret = smu_get_driver_allowed_feature_mask(smu); 1855 if (ret) 1856 return ret; 1857 1858 ret = smu_smc_hw_setup(smu); 1859 if (ret) { 1860 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1861 return ret; 1862 } 1863 1864 /* 1865 * Move maximum sustainable clock retrieving here considering 1866 * 1. It is not needed on resume(from S3). 1867 * 2. DAL settings come between .hw_init and .late_init of SMU. 1868 * And DAL needs to know the maximum sustainable clocks. Thus 1869 * it cannot be put in .late_init(). 1870 */ 1871 ret = smu_init_max_sustainable_clocks(smu); 1872 if (ret) { 1873 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1874 return ret; 1875 } 1876 1877 adev->pm.dpm_enabled = true; 1878 1879 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1880 1881 return 0; 1882 } 1883 1884 static int smu_disable_dpms(struct smu_context *smu) 1885 { 1886 struct amdgpu_device *adev = smu->adev; 1887 int ret = 0; 1888 bool use_baco = !smu->is_apu && 1889 ((amdgpu_in_reset(adev) && 1890 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1891 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1892 1893 /* 1894 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1895 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1896 */ 1897 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1898 case IP_VERSION(13, 0, 0): 1899 case IP_VERSION(13, 0, 7): 1900 case IP_VERSION(13, 0, 10): 1901 case IP_VERSION(14, 0, 2): 1902 case IP_VERSION(14, 0, 3): 1903 return 0; 1904 default: 1905 break; 1906 } 1907 1908 /* 1909 * For custom pptable uploading, skip the DPM features 1910 * disable process on Navi1x ASICs. 1911 * - As the gfx related features are under control of 1912 * RLC on those ASICs. RLC reinitialization will be 1913 * needed to reenable them. That will cost much more 1914 * efforts. 1915 * 1916 * - SMU firmware can handle the DPM reenablement 1917 * properly. 1918 */ 1919 if (smu->uploading_custom_pp_table) { 1920 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1921 case IP_VERSION(11, 0, 0): 1922 case IP_VERSION(11, 0, 5): 1923 case IP_VERSION(11, 0, 9): 1924 case IP_VERSION(11, 0, 7): 1925 case IP_VERSION(11, 0, 11): 1926 case IP_VERSION(11, 5, 0): 1927 case IP_VERSION(11, 5, 2): 1928 case IP_VERSION(11, 0, 12): 1929 case IP_VERSION(11, 0, 13): 1930 return 0; 1931 default: 1932 break; 1933 } 1934 } 1935 1936 /* 1937 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1938 * on BACO in. Driver involvement is unnecessary. 1939 */ 1940 if (use_baco) { 1941 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1942 case IP_VERSION(11, 0, 7): 1943 case IP_VERSION(11, 0, 0): 1944 case IP_VERSION(11, 0, 5): 1945 case IP_VERSION(11, 0, 9): 1946 case IP_VERSION(13, 0, 7): 1947 return 0; 1948 default: 1949 break; 1950 } 1951 } 1952 1953 /* 1954 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1955 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1956 */ 1957 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1958 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1959 return 0; 1960 1961 /* 1962 * For gpu reset, runpm and hibernation through BACO, 1963 * BACO feature has to be kept enabled. 1964 */ 1965 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1966 ret = smu_disable_all_features_with_exception(smu, 1967 SMU_FEATURE_BACO_BIT); 1968 if (ret) 1969 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1970 } else { 1971 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1972 if (!adev->scpm_enabled) { 1973 ret = smu_system_features_control(smu, false); 1974 if (ret) 1975 dev_err(adev->dev, "Failed to disable smu features.\n"); 1976 } 1977 } 1978 1979 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1980 * otherwise SMU will hang while interacting with RLC if RLC is halted 1981 * this is a WA for Vangogh asic which fix the SMU hang issue. 1982 */ 1983 ret = smu_notify_rlc_state(smu, false); 1984 if (ret) { 1985 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1986 return ret; 1987 } 1988 1989 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1990 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1991 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1992 adev->gfx.rlc.funcs->stop(adev); 1993 1994 return ret; 1995 } 1996 1997 static int smu_smc_hw_cleanup(struct smu_context *smu) 1998 { 1999 struct amdgpu_device *adev = smu->adev; 2000 int ret = 0; 2001 2002 smu_wbrf_fini(smu); 2003 2004 cancel_work_sync(&smu->throttling_logging_work); 2005 cancel_work_sync(&smu->interrupt_work); 2006 2007 ret = smu_disable_thermal_alert(smu); 2008 if (ret) { 2009 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2010 return ret; 2011 } 2012 2013 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2014 2015 ret = smu_disable_dpms(smu); 2016 if (ret) { 2017 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2018 return ret; 2019 } 2020 2021 return 0; 2022 } 2023 2024 static int smu_reset_mp1_state(struct smu_context *smu) 2025 { 2026 struct amdgpu_device *adev = smu->adev; 2027 int ret = 0; 2028 2029 if ((!adev->in_runpm) && (!adev->in_suspend) && 2030 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2031 IP_VERSION(13, 0, 10) && 2032 !amdgpu_device_has_display_hardware(adev)) 2033 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2034 2035 return ret; 2036 } 2037 2038 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2039 { 2040 struct amdgpu_device *adev = ip_block->adev; 2041 struct smu_context *smu = adev->powerplay.pp_handle; 2042 int i, ret; 2043 2044 if (amdgpu_sriov_multi_vf_mode(adev)) 2045 return 0; 2046 2047 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2048 smu_dpm_set_vcn_enable(smu, false, i); 2049 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2050 } 2051 smu_dpm_set_jpeg_enable(smu, false); 2052 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2053 smu_dpm_set_vpe_enable(smu, false); 2054 smu_dpm_set_umsch_mm_enable(smu, false); 2055 2056 if (!smu->pm_enabled) 2057 return 0; 2058 2059 adev->pm.dpm_enabled = false; 2060 2061 ret = smu_smc_hw_cleanup(smu); 2062 if (ret) 2063 return ret; 2064 2065 ret = smu_reset_mp1_state(smu); 2066 if (ret) 2067 return ret; 2068 2069 return 0; 2070 } 2071 2072 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2073 { 2074 struct amdgpu_device *adev = ip_block->adev; 2075 struct smu_context *smu = adev->powerplay.pp_handle; 2076 2077 kfree(smu); 2078 } 2079 2080 static int smu_reset(struct smu_context *smu) 2081 { 2082 struct amdgpu_device *adev = smu->adev; 2083 struct amdgpu_ip_block *ip_block; 2084 int ret; 2085 2086 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2087 if (!ip_block) 2088 return -EINVAL; 2089 2090 ret = smu_hw_fini(ip_block); 2091 if (ret) 2092 return ret; 2093 2094 ret = smu_hw_init(ip_block); 2095 if (ret) 2096 return ret; 2097 2098 ret = smu_late_init(ip_block); 2099 if (ret) 2100 return ret; 2101 2102 return 0; 2103 } 2104 2105 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2106 { 2107 struct amdgpu_device *adev = ip_block->adev; 2108 struct smu_context *smu = adev->powerplay.pp_handle; 2109 int ret; 2110 uint64_t count; 2111 2112 if (amdgpu_sriov_multi_vf_mode(adev)) 2113 return 0; 2114 2115 if (!smu->pm_enabled) 2116 return 0; 2117 2118 adev->pm.dpm_enabled = false; 2119 2120 ret = smu_smc_hw_cleanup(smu); 2121 if (ret) 2122 return ret; 2123 2124 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2125 2126 smu_set_gfx_cgpg(smu, false); 2127 2128 /* 2129 * pwfw resets entrycount when device is suspended, so we save the 2130 * last value to be used when we resume to keep it consistent 2131 */ 2132 ret = smu_get_entrycount_gfxoff(smu, &count); 2133 if (!ret) 2134 adev->gfx.gfx_off_entrycount = count; 2135 2136 /* clear this on suspend so it will get reprogrammed on resume */ 2137 smu->workload_mask = 0; 2138 2139 return 0; 2140 } 2141 2142 static int smu_resume(struct amdgpu_ip_block *ip_block) 2143 { 2144 int ret; 2145 struct amdgpu_device *adev = ip_block->adev; 2146 struct smu_context *smu = adev->powerplay.pp_handle; 2147 2148 if (amdgpu_sriov_multi_vf_mode(adev)) 2149 return 0; 2150 2151 if (!smu->pm_enabled) 2152 return 0; 2153 2154 dev_info(adev->dev, "SMU is resuming...\n"); 2155 2156 ret = smu_start_smc_engine(smu); 2157 if (ret) { 2158 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2159 return ret; 2160 } 2161 2162 ret = smu_smc_hw_setup(smu); 2163 if (ret) { 2164 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2165 return ret; 2166 } 2167 2168 ret = smu_set_gfx_imu_enable(smu); 2169 if (ret) 2170 return ret; 2171 2172 smu_set_gfx_cgpg(smu, true); 2173 2174 smu->disable_uclk_switch = 0; 2175 2176 adev->pm.dpm_enabled = true; 2177 2178 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2179 2180 return 0; 2181 } 2182 2183 static int smu_display_configuration_change(void *handle, 2184 const struct amd_pp_display_configuration *display_config) 2185 { 2186 struct smu_context *smu = handle; 2187 2188 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2189 return -EOPNOTSUPP; 2190 2191 if (!display_config) 2192 return -EINVAL; 2193 2194 smu_set_min_dcef_deep_sleep(smu, 2195 display_config->min_dcef_deep_sleep_set_clk / 100); 2196 2197 return 0; 2198 } 2199 2200 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2201 enum amd_clockgating_state state) 2202 { 2203 return 0; 2204 } 2205 2206 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2207 enum amd_powergating_state state) 2208 { 2209 return 0; 2210 } 2211 2212 static int smu_enable_umd_pstate(void *handle, 2213 enum amd_dpm_forced_level *level) 2214 { 2215 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2216 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2217 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2218 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2219 2220 struct smu_context *smu = (struct smu_context*)(handle); 2221 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2222 2223 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2224 return -EINVAL; 2225 2226 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2227 /* enter umd pstate, save current level, disable gfx cg*/ 2228 if (*level & profile_mode_mask) { 2229 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2230 smu_gpo_control(smu, false); 2231 smu_gfx_ulv_control(smu, false); 2232 smu_deep_sleep_control(smu, false); 2233 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2234 } 2235 } else { 2236 /* exit umd pstate, restore level, enable gfx cg*/ 2237 if (!(*level & profile_mode_mask)) { 2238 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2239 *level = smu_dpm_ctx->saved_dpm_level; 2240 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2241 smu_deep_sleep_control(smu, true); 2242 smu_gfx_ulv_control(smu, true); 2243 smu_gpo_control(smu, true); 2244 } 2245 } 2246 2247 return 0; 2248 } 2249 2250 static int smu_bump_power_profile_mode(struct smu_context *smu, 2251 long *custom_params, 2252 u32 custom_params_max_idx) 2253 { 2254 u32 workload_mask = 0; 2255 int i, ret = 0; 2256 2257 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2258 if (smu->workload_refcount[i]) 2259 workload_mask |= 1 << i; 2260 } 2261 2262 if (smu->workload_mask == workload_mask) 2263 return 0; 2264 2265 if (smu->ppt_funcs->set_power_profile_mode) 2266 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2267 custom_params, 2268 custom_params_max_idx); 2269 2270 if (!ret) 2271 smu->workload_mask = workload_mask; 2272 2273 return ret; 2274 } 2275 2276 static void smu_power_profile_mode_get(struct smu_context *smu, 2277 enum PP_SMC_POWER_PROFILE profile_mode) 2278 { 2279 smu->workload_refcount[profile_mode]++; 2280 } 2281 2282 static void smu_power_profile_mode_put(struct smu_context *smu, 2283 enum PP_SMC_POWER_PROFILE profile_mode) 2284 { 2285 if (smu->workload_refcount[profile_mode]) 2286 smu->workload_refcount[profile_mode]--; 2287 } 2288 2289 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2290 enum amd_dpm_forced_level level, 2291 bool skip_display_settings) 2292 { 2293 int ret = 0; 2294 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2295 2296 if (!skip_display_settings) { 2297 ret = smu_display_config_changed(smu); 2298 if (ret) { 2299 dev_err(smu->adev->dev, "Failed to change display config!"); 2300 return ret; 2301 } 2302 } 2303 2304 ret = smu_apply_clocks_adjust_rules(smu); 2305 if (ret) { 2306 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2307 return ret; 2308 } 2309 2310 if (!skip_display_settings) { 2311 ret = smu_notify_smc_display_config(smu); 2312 if (ret) { 2313 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2314 return ret; 2315 } 2316 } 2317 2318 if (smu_dpm_ctx->dpm_level != level) { 2319 ret = smu_asic_set_performance_level(smu, level); 2320 if (ret) { 2321 if (ret == -EOPNOTSUPP) 2322 dev_info(smu->adev->dev, "set performance level %d not supported", 2323 level); 2324 else 2325 dev_err(smu->adev->dev, "Failed to set performance level %d", 2326 level); 2327 return ret; 2328 } 2329 2330 /* update the saved copy */ 2331 smu_dpm_ctx->dpm_level = level; 2332 } 2333 2334 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2335 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2336 smu_bump_power_profile_mode(smu, NULL, 0); 2337 2338 return ret; 2339 } 2340 2341 static int smu_handle_task(struct smu_context *smu, 2342 enum amd_dpm_forced_level level, 2343 enum amd_pp_task task_id) 2344 { 2345 int ret = 0; 2346 2347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2348 return -EOPNOTSUPP; 2349 2350 switch (task_id) { 2351 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2352 ret = smu_pre_display_config_changed(smu); 2353 if (ret) 2354 return ret; 2355 ret = smu_adjust_power_state_dynamic(smu, level, false); 2356 break; 2357 case AMD_PP_TASK_COMPLETE_INIT: 2358 ret = smu_adjust_power_state_dynamic(smu, level, true); 2359 break; 2360 case AMD_PP_TASK_READJUST_POWER_STATE: 2361 ret = smu_adjust_power_state_dynamic(smu, level, true); 2362 break; 2363 default: 2364 break; 2365 } 2366 2367 return ret; 2368 } 2369 2370 static int smu_handle_dpm_task(void *handle, 2371 enum amd_pp_task task_id, 2372 enum amd_pm_state_type *user_state) 2373 { 2374 struct smu_context *smu = handle; 2375 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2376 2377 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2378 2379 } 2380 2381 static int smu_switch_power_profile(void *handle, 2382 enum PP_SMC_POWER_PROFILE type, 2383 bool enable) 2384 { 2385 struct smu_context *smu = handle; 2386 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2387 int ret; 2388 2389 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2390 return -EOPNOTSUPP; 2391 2392 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2393 return -EINVAL; 2394 2395 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2396 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2397 if (enable) 2398 smu_power_profile_mode_get(smu, type); 2399 else 2400 smu_power_profile_mode_put(smu, type); 2401 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2402 if (ret) { 2403 if (enable) 2404 smu_power_profile_mode_put(smu, type); 2405 else 2406 smu_power_profile_mode_get(smu, type); 2407 return ret; 2408 } 2409 } 2410 2411 return 0; 2412 } 2413 2414 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2415 { 2416 struct smu_context *smu = handle; 2417 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2418 2419 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2420 return -EOPNOTSUPP; 2421 2422 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2423 return -EINVAL; 2424 2425 return smu_dpm_ctx->dpm_level; 2426 } 2427 2428 static int smu_force_performance_level(void *handle, 2429 enum amd_dpm_forced_level level) 2430 { 2431 struct smu_context *smu = handle; 2432 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2433 int ret = 0; 2434 2435 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2436 return -EOPNOTSUPP; 2437 2438 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2439 return -EINVAL; 2440 2441 ret = smu_enable_umd_pstate(smu, &level); 2442 if (ret) 2443 return ret; 2444 2445 ret = smu_handle_task(smu, level, 2446 AMD_PP_TASK_READJUST_POWER_STATE); 2447 2448 /* reset user dpm clock state */ 2449 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2450 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2451 smu->user_dpm_profile.clk_dependency = 0; 2452 } 2453 2454 return ret; 2455 } 2456 2457 static int smu_set_display_count(void *handle, uint32_t count) 2458 { 2459 struct smu_context *smu = handle; 2460 2461 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2462 return -EOPNOTSUPP; 2463 2464 return smu_init_display_count(smu, count); 2465 } 2466 2467 static int smu_force_smuclk_levels(struct smu_context *smu, 2468 enum smu_clk_type clk_type, 2469 uint32_t mask) 2470 { 2471 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2472 int ret = 0; 2473 2474 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2475 return -EOPNOTSUPP; 2476 2477 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2478 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2479 return -EINVAL; 2480 } 2481 2482 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2483 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2484 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2485 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2486 smu_set_user_clk_dependencies(smu, clk_type); 2487 } 2488 } 2489 2490 return ret; 2491 } 2492 2493 static int smu_force_ppclk_levels(void *handle, 2494 enum pp_clock_type type, 2495 uint32_t mask) 2496 { 2497 struct smu_context *smu = handle; 2498 enum smu_clk_type clk_type; 2499 2500 switch (type) { 2501 case PP_SCLK: 2502 clk_type = SMU_SCLK; break; 2503 case PP_MCLK: 2504 clk_type = SMU_MCLK; break; 2505 case PP_PCIE: 2506 clk_type = SMU_PCIE; break; 2507 case PP_SOCCLK: 2508 clk_type = SMU_SOCCLK; break; 2509 case PP_FCLK: 2510 clk_type = SMU_FCLK; break; 2511 case PP_DCEFCLK: 2512 clk_type = SMU_DCEFCLK; break; 2513 case PP_VCLK: 2514 clk_type = SMU_VCLK; break; 2515 case PP_VCLK1: 2516 clk_type = SMU_VCLK1; break; 2517 case PP_DCLK: 2518 clk_type = SMU_DCLK; break; 2519 case PP_DCLK1: 2520 clk_type = SMU_DCLK1; break; 2521 case OD_SCLK: 2522 clk_type = SMU_OD_SCLK; break; 2523 case OD_MCLK: 2524 clk_type = SMU_OD_MCLK; break; 2525 case OD_VDDC_CURVE: 2526 clk_type = SMU_OD_VDDC_CURVE; break; 2527 case OD_RANGE: 2528 clk_type = SMU_OD_RANGE; break; 2529 default: 2530 return -EINVAL; 2531 } 2532 2533 return smu_force_smuclk_levels(smu, clk_type, mask); 2534 } 2535 2536 /* 2537 * On system suspending or resetting, the dpm_enabled 2538 * flag will be cleared. So that those SMU services which 2539 * are not supported will be gated. 2540 * However, the mp1 state setting should still be granted 2541 * even if the dpm_enabled cleared. 2542 */ 2543 static int smu_set_mp1_state(void *handle, 2544 enum pp_mp1_state mp1_state) 2545 { 2546 struct smu_context *smu = handle; 2547 int ret = 0; 2548 2549 if (!smu->pm_enabled) 2550 return -EOPNOTSUPP; 2551 2552 if (smu->ppt_funcs && 2553 smu->ppt_funcs->set_mp1_state) 2554 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2555 2556 return ret; 2557 } 2558 2559 static int smu_set_df_cstate(void *handle, 2560 enum pp_df_cstate state) 2561 { 2562 struct smu_context *smu = handle; 2563 int ret = 0; 2564 2565 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2566 return -EOPNOTSUPP; 2567 2568 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2569 return 0; 2570 2571 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2572 if (ret) 2573 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2574 2575 return ret; 2576 } 2577 2578 int smu_write_watermarks_table(struct smu_context *smu) 2579 { 2580 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2581 return -EOPNOTSUPP; 2582 2583 return smu_set_watermarks_table(smu, NULL); 2584 } 2585 2586 static int smu_set_watermarks_for_clock_ranges(void *handle, 2587 struct pp_smu_wm_range_sets *clock_ranges) 2588 { 2589 struct smu_context *smu = handle; 2590 2591 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2592 return -EOPNOTSUPP; 2593 2594 if (smu->disable_watermark) 2595 return 0; 2596 2597 return smu_set_watermarks_table(smu, clock_ranges); 2598 } 2599 2600 int smu_set_ac_dc(struct smu_context *smu) 2601 { 2602 int ret = 0; 2603 2604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2605 return -EOPNOTSUPP; 2606 2607 /* controlled by firmware */ 2608 if (smu->dc_controlled_by_gpio) 2609 return 0; 2610 2611 ret = smu_set_power_source(smu, 2612 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2613 SMU_POWER_SOURCE_DC); 2614 if (ret) 2615 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2616 smu->adev->pm.ac_power ? "AC" : "DC"); 2617 2618 return ret; 2619 } 2620 2621 const struct amd_ip_funcs smu_ip_funcs = { 2622 .name = "smu", 2623 .early_init = smu_early_init, 2624 .late_init = smu_late_init, 2625 .sw_init = smu_sw_init, 2626 .sw_fini = smu_sw_fini, 2627 .hw_init = smu_hw_init, 2628 .hw_fini = smu_hw_fini, 2629 .late_fini = smu_late_fini, 2630 .suspend = smu_suspend, 2631 .resume = smu_resume, 2632 .is_idle = NULL, 2633 .check_soft_reset = NULL, 2634 .wait_for_idle = NULL, 2635 .soft_reset = NULL, 2636 .set_clockgating_state = smu_set_clockgating_state, 2637 .set_powergating_state = smu_set_powergating_state, 2638 }; 2639 2640 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2641 .type = AMD_IP_BLOCK_TYPE_SMC, 2642 .major = 11, 2643 .minor = 0, 2644 .rev = 0, 2645 .funcs = &smu_ip_funcs, 2646 }; 2647 2648 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2649 .type = AMD_IP_BLOCK_TYPE_SMC, 2650 .major = 12, 2651 .minor = 0, 2652 .rev = 0, 2653 .funcs = &smu_ip_funcs, 2654 }; 2655 2656 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2657 .type = AMD_IP_BLOCK_TYPE_SMC, 2658 .major = 13, 2659 .minor = 0, 2660 .rev = 0, 2661 .funcs = &smu_ip_funcs, 2662 }; 2663 2664 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2665 .type = AMD_IP_BLOCK_TYPE_SMC, 2666 .major = 14, 2667 .minor = 0, 2668 .rev = 0, 2669 .funcs = &smu_ip_funcs, 2670 }; 2671 2672 static int smu_load_microcode(void *handle) 2673 { 2674 struct smu_context *smu = handle; 2675 struct amdgpu_device *adev = smu->adev; 2676 int ret = 0; 2677 2678 if (!smu->pm_enabled) 2679 return -EOPNOTSUPP; 2680 2681 /* This should be used for non PSP loading */ 2682 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2683 return 0; 2684 2685 if (smu->ppt_funcs->load_microcode) { 2686 ret = smu->ppt_funcs->load_microcode(smu); 2687 if (ret) { 2688 dev_err(adev->dev, "Load microcode failed\n"); 2689 return ret; 2690 } 2691 } 2692 2693 if (smu->ppt_funcs->check_fw_status) { 2694 ret = smu->ppt_funcs->check_fw_status(smu); 2695 if (ret) { 2696 dev_err(adev->dev, "SMC is not ready\n"); 2697 return ret; 2698 } 2699 } 2700 2701 return ret; 2702 } 2703 2704 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2705 { 2706 int ret = 0; 2707 2708 if (smu->ppt_funcs->set_gfx_cgpg) 2709 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2710 2711 return ret; 2712 } 2713 2714 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2715 { 2716 struct smu_context *smu = handle; 2717 int ret = 0; 2718 2719 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2720 return -EOPNOTSUPP; 2721 2722 if (!smu->ppt_funcs->set_fan_speed_rpm) 2723 return -EOPNOTSUPP; 2724 2725 if (speed == U32_MAX) 2726 return -EINVAL; 2727 2728 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2729 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2730 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2731 smu->user_dpm_profile.fan_speed_rpm = speed; 2732 2733 /* Override custom PWM setting as they cannot co-exist */ 2734 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2735 smu->user_dpm_profile.fan_speed_pwm = 0; 2736 } 2737 2738 return ret; 2739 } 2740 2741 /** 2742 * smu_get_power_limit - Request one of the SMU Power Limits 2743 * 2744 * @handle: pointer to smu context 2745 * @limit: requested limit is written back to this variable 2746 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2747 * @pp_power_type: &pp_power_type type of power 2748 * Return: 0 on success, <0 on error 2749 * 2750 */ 2751 int smu_get_power_limit(void *handle, 2752 uint32_t *limit, 2753 enum pp_power_limit_level pp_limit_level, 2754 enum pp_power_type pp_power_type) 2755 { 2756 struct smu_context *smu = handle; 2757 struct amdgpu_device *adev = smu->adev; 2758 enum smu_ppt_limit_level limit_level; 2759 uint32_t limit_type; 2760 int ret = 0; 2761 2762 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2763 return -EOPNOTSUPP; 2764 2765 switch (pp_power_type) { 2766 case PP_PWR_TYPE_SUSTAINED: 2767 limit_type = SMU_DEFAULT_PPT_LIMIT; 2768 break; 2769 case PP_PWR_TYPE_FAST: 2770 limit_type = SMU_FAST_PPT_LIMIT; 2771 break; 2772 default: 2773 return -EOPNOTSUPP; 2774 } 2775 2776 switch (pp_limit_level) { 2777 case PP_PWR_LIMIT_CURRENT: 2778 limit_level = SMU_PPT_LIMIT_CURRENT; 2779 break; 2780 case PP_PWR_LIMIT_DEFAULT: 2781 limit_level = SMU_PPT_LIMIT_DEFAULT; 2782 break; 2783 case PP_PWR_LIMIT_MAX: 2784 limit_level = SMU_PPT_LIMIT_MAX; 2785 break; 2786 case PP_PWR_LIMIT_MIN: 2787 limit_level = SMU_PPT_LIMIT_MIN; 2788 break; 2789 default: 2790 return -EOPNOTSUPP; 2791 } 2792 2793 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2794 if (smu->ppt_funcs->get_ppt_limit) 2795 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2796 } else { 2797 switch (limit_level) { 2798 case SMU_PPT_LIMIT_CURRENT: 2799 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2800 case IP_VERSION(13, 0, 2): 2801 case IP_VERSION(13, 0, 6): 2802 case IP_VERSION(13, 0, 12): 2803 case IP_VERSION(13, 0, 14): 2804 case IP_VERSION(11, 0, 7): 2805 case IP_VERSION(11, 0, 11): 2806 case IP_VERSION(11, 0, 12): 2807 case IP_VERSION(11, 0, 13): 2808 ret = smu_get_asic_power_limits(smu, 2809 &smu->current_power_limit, 2810 NULL, NULL, NULL); 2811 break; 2812 default: 2813 break; 2814 } 2815 *limit = smu->current_power_limit; 2816 break; 2817 case SMU_PPT_LIMIT_DEFAULT: 2818 *limit = smu->default_power_limit; 2819 break; 2820 case SMU_PPT_LIMIT_MAX: 2821 *limit = smu->max_power_limit; 2822 break; 2823 case SMU_PPT_LIMIT_MIN: 2824 *limit = smu->min_power_limit; 2825 break; 2826 default: 2827 return -EINVAL; 2828 } 2829 } 2830 2831 return ret; 2832 } 2833 2834 static int smu_set_power_limit(void *handle, uint32_t limit) 2835 { 2836 struct smu_context *smu = handle; 2837 uint32_t limit_type = limit >> 24; 2838 int ret = 0; 2839 2840 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2841 return -EOPNOTSUPP; 2842 2843 limit &= (1<<24)-1; 2844 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2845 if (smu->ppt_funcs->set_power_limit) 2846 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2847 2848 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2849 dev_err(smu->adev->dev, 2850 "New power limit (%d) is out of range [%d,%d]\n", 2851 limit, smu->min_power_limit, smu->max_power_limit); 2852 return -EINVAL; 2853 } 2854 2855 if (!limit) 2856 limit = smu->current_power_limit; 2857 2858 if (smu->ppt_funcs->set_power_limit) { 2859 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2860 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2861 smu->user_dpm_profile.power_limit = limit; 2862 } 2863 2864 return ret; 2865 } 2866 2867 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2868 { 2869 int ret = 0; 2870 2871 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2872 return -EOPNOTSUPP; 2873 2874 if (smu->ppt_funcs->print_clk_levels) 2875 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2876 2877 return ret; 2878 } 2879 2880 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2881 { 2882 enum smu_clk_type clk_type; 2883 2884 switch (type) { 2885 case PP_SCLK: 2886 clk_type = SMU_SCLK; break; 2887 case PP_MCLK: 2888 clk_type = SMU_MCLK; break; 2889 case PP_PCIE: 2890 clk_type = SMU_PCIE; break; 2891 case PP_SOCCLK: 2892 clk_type = SMU_SOCCLK; break; 2893 case PP_FCLK: 2894 clk_type = SMU_FCLK; break; 2895 case PP_DCEFCLK: 2896 clk_type = SMU_DCEFCLK; break; 2897 case PP_VCLK: 2898 clk_type = SMU_VCLK; break; 2899 case PP_VCLK1: 2900 clk_type = SMU_VCLK1; break; 2901 case PP_DCLK: 2902 clk_type = SMU_DCLK; break; 2903 case PP_DCLK1: 2904 clk_type = SMU_DCLK1; break; 2905 case OD_SCLK: 2906 clk_type = SMU_OD_SCLK; break; 2907 case OD_MCLK: 2908 clk_type = SMU_OD_MCLK; break; 2909 case OD_VDDC_CURVE: 2910 clk_type = SMU_OD_VDDC_CURVE; break; 2911 case OD_RANGE: 2912 clk_type = SMU_OD_RANGE; break; 2913 case OD_VDDGFX_OFFSET: 2914 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2915 case OD_CCLK: 2916 clk_type = SMU_OD_CCLK; break; 2917 case OD_FAN_CURVE: 2918 clk_type = SMU_OD_FAN_CURVE; break; 2919 case OD_ACOUSTIC_LIMIT: 2920 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2921 case OD_ACOUSTIC_TARGET: 2922 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2923 case OD_FAN_TARGET_TEMPERATURE: 2924 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2925 case OD_FAN_MINIMUM_PWM: 2926 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2927 case OD_FAN_ZERO_RPM_ENABLE: 2928 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2929 case OD_FAN_ZERO_RPM_STOP_TEMP: 2930 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2931 default: 2932 clk_type = SMU_CLK_COUNT; break; 2933 } 2934 2935 return clk_type; 2936 } 2937 2938 static int smu_print_ppclk_levels(void *handle, 2939 enum pp_clock_type type, 2940 char *buf) 2941 { 2942 struct smu_context *smu = handle; 2943 enum smu_clk_type clk_type; 2944 2945 clk_type = smu_convert_to_smuclk(type); 2946 if (clk_type == SMU_CLK_COUNT) 2947 return -EINVAL; 2948 2949 return smu_print_smuclk_levels(smu, clk_type, buf); 2950 } 2951 2952 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2953 { 2954 struct smu_context *smu = handle; 2955 enum smu_clk_type clk_type; 2956 2957 clk_type = smu_convert_to_smuclk(type); 2958 if (clk_type == SMU_CLK_COUNT) 2959 return -EINVAL; 2960 2961 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2962 return -EOPNOTSUPP; 2963 2964 if (!smu->ppt_funcs->emit_clk_levels) 2965 return -ENOENT; 2966 2967 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2968 2969 } 2970 2971 static int smu_od_edit_dpm_table(void *handle, 2972 enum PP_OD_DPM_TABLE_COMMAND type, 2973 long *input, uint32_t size) 2974 { 2975 struct smu_context *smu = handle; 2976 int ret = 0; 2977 2978 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2979 return -EOPNOTSUPP; 2980 2981 if (smu->ppt_funcs->od_edit_dpm_table) { 2982 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2983 } 2984 2985 return ret; 2986 } 2987 2988 static int smu_read_sensor(void *handle, 2989 int sensor, 2990 void *data, 2991 int *size_arg) 2992 { 2993 struct smu_context *smu = handle; 2994 struct amdgpu_device *adev = smu->adev; 2995 struct smu_umd_pstate_table *pstate_table = 2996 &smu->pstate_table; 2997 int i, ret = 0; 2998 uint32_t *size, size_val; 2999 3000 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3001 return -EOPNOTSUPP; 3002 3003 if (!data || !size_arg) 3004 return -EINVAL; 3005 3006 size_val = *size_arg; 3007 size = &size_val; 3008 3009 if (smu->ppt_funcs->read_sensor) 3010 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3011 goto unlock; 3012 3013 switch (sensor) { 3014 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3015 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3016 *size = 4; 3017 break; 3018 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3019 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3020 *size = 4; 3021 break; 3022 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3023 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3024 *size = 4; 3025 break; 3026 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3027 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3028 *size = 4; 3029 break; 3030 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3031 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3032 *size = 8; 3033 break; 3034 case AMDGPU_PP_SENSOR_UVD_POWER: 3035 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3036 *size = 4; 3037 break; 3038 case AMDGPU_PP_SENSOR_VCE_POWER: 3039 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3040 *size = 4; 3041 break; 3042 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3043 *(uint32_t *)data = 0; 3044 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3045 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3046 *(uint32_t *)data = 1; 3047 break; 3048 } 3049 } 3050 *size = 4; 3051 break; 3052 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3053 *(uint32_t *)data = 0; 3054 *size = 4; 3055 break; 3056 default: 3057 *size = 0; 3058 ret = -EOPNOTSUPP; 3059 break; 3060 } 3061 3062 unlock: 3063 // assign uint32_t to int 3064 *size_arg = size_val; 3065 3066 return ret; 3067 } 3068 3069 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3070 { 3071 int ret = -EOPNOTSUPP; 3072 struct smu_context *smu = handle; 3073 3074 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3075 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3076 3077 return ret; 3078 } 3079 3080 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3081 { 3082 int ret = -EOPNOTSUPP; 3083 struct smu_context *smu = handle; 3084 3085 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3086 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3087 3088 return ret; 3089 } 3090 3091 static int smu_get_power_profile_mode(void *handle, char *buf) 3092 { 3093 struct smu_context *smu = handle; 3094 3095 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3096 !smu->ppt_funcs->get_power_profile_mode) 3097 return -EOPNOTSUPP; 3098 if (!buf) 3099 return -EINVAL; 3100 3101 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3102 } 3103 3104 static int smu_set_power_profile_mode(void *handle, 3105 long *param, 3106 uint32_t param_size) 3107 { 3108 struct smu_context *smu = handle; 3109 bool custom = false; 3110 int ret = 0; 3111 3112 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3113 !smu->ppt_funcs->set_power_profile_mode) 3114 return -EOPNOTSUPP; 3115 3116 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3117 custom = true; 3118 /* clear frontend mask so custom changes propogate */ 3119 smu->workload_mask = 0; 3120 } 3121 3122 if ((param[param_size] != smu->power_profile_mode) || custom) { 3123 /* clear the old user preference */ 3124 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3125 /* set the new user preference */ 3126 smu_power_profile_mode_get(smu, param[param_size]); 3127 ret = smu_bump_power_profile_mode(smu, 3128 custom ? param : NULL, 3129 custom ? param_size : 0); 3130 if (ret) 3131 smu_power_profile_mode_put(smu, param[param_size]); 3132 else 3133 /* store the user's preference */ 3134 smu->power_profile_mode = param[param_size]; 3135 } 3136 3137 return ret; 3138 } 3139 3140 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3141 { 3142 struct smu_context *smu = handle; 3143 3144 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3145 return -EOPNOTSUPP; 3146 3147 if (!smu->ppt_funcs->get_fan_control_mode) 3148 return -EOPNOTSUPP; 3149 3150 if (!fan_mode) 3151 return -EINVAL; 3152 3153 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3154 3155 return 0; 3156 } 3157 3158 static int smu_set_fan_control_mode(void *handle, u32 value) 3159 { 3160 struct smu_context *smu = handle; 3161 int ret = 0; 3162 3163 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3164 return -EOPNOTSUPP; 3165 3166 if (!smu->ppt_funcs->set_fan_control_mode) 3167 return -EOPNOTSUPP; 3168 3169 if (value == U32_MAX) 3170 return -EINVAL; 3171 3172 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3173 if (ret) 3174 goto out; 3175 3176 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3177 smu->user_dpm_profile.fan_mode = value; 3178 3179 /* reset user dpm fan speed */ 3180 if (value != AMD_FAN_CTRL_MANUAL) { 3181 smu->user_dpm_profile.fan_speed_pwm = 0; 3182 smu->user_dpm_profile.fan_speed_rpm = 0; 3183 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3184 } 3185 } 3186 3187 out: 3188 return ret; 3189 } 3190 3191 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3192 { 3193 struct smu_context *smu = handle; 3194 int ret = 0; 3195 3196 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3197 return -EOPNOTSUPP; 3198 3199 if (!smu->ppt_funcs->get_fan_speed_pwm) 3200 return -EOPNOTSUPP; 3201 3202 if (!speed) 3203 return -EINVAL; 3204 3205 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3206 3207 return ret; 3208 } 3209 3210 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3211 { 3212 struct smu_context *smu = handle; 3213 int ret = 0; 3214 3215 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3216 return -EOPNOTSUPP; 3217 3218 if (!smu->ppt_funcs->set_fan_speed_pwm) 3219 return -EOPNOTSUPP; 3220 3221 if (speed == U32_MAX) 3222 return -EINVAL; 3223 3224 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3225 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3226 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3227 smu->user_dpm_profile.fan_speed_pwm = speed; 3228 3229 /* Override custom RPM setting as they cannot co-exist */ 3230 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3231 smu->user_dpm_profile.fan_speed_rpm = 0; 3232 } 3233 3234 return ret; 3235 } 3236 3237 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3238 { 3239 struct smu_context *smu = handle; 3240 int ret = 0; 3241 3242 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3243 return -EOPNOTSUPP; 3244 3245 if (!smu->ppt_funcs->get_fan_speed_rpm) 3246 return -EOPNOTSUPP; 3247 3248 if (!speed) 3249 return -EINVAL; 3250 3251 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3252 3253 return ret; 3254 } 3255 3256 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3257 { 3258 struct smu_context *smu = handle; 3259 3260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3261 return -EOPNOTSUPP; 3262 3263 return smu_set_min_dcef_deep_sleep(smu, clk); 3264 } 3265 3266 static int smu_get_clock_by_type_with_latency(void *handle, 3267 enum amd_pp_clock_type type, 3268 struct pp_clock_levels_with_latency *clocks) 3269 { 3270 struct smu_context *smu = handle; 3271 enum smu_clk_type clk_type; 3272 int ret = 0; 3273 3274 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3275 return -EOPNOTSUPP; 3276 3277 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3278 switch (type) { 3279 case amd_pp_sys_clock: 3280 clk_type = SMU_GFXCLK; 3281 break; 3282 case amd_pp_mem_clock: 3283 clk_type = SMU_MCLK; 3284 break; 3285 case amd_pp_dcef_clock: 3286 clk_type = SMU_DCEFCLK; 3287 break; 3288 case amd_pp_disp_clock: 3289 clk_type = SMU_DISPCLK; 3290 break; 3291 default: 3292 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3293 return -EINVAL; 3294 } 3295 3296 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3297 } 3298 3299 return ret; 3300 } 3301 3302 static int smu_display_clock_voltage_request(void *handle, 3303 struct pp_display_clock_request *clock_req) 3304 { 3305 struct smu_context *smu = handle; 3306 int ret = 0; 3307 3308 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3309 return -EOPNOTSUPP; 3310 3311 if (smu->ppt_funcs->display_clock_voltage_request) 3312 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3313 3314 return ret; 3315 } 3316 3317 3318 static int smu_display_disable_memory_clock_switch(void *handle, 3319 bool disable_memory_clock_switch) 3320 { 3321 struct smu_context *smu = handle; 3322 int ret = -EINVAL; 3323 3324 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3325 return -EOPNOTSUPP; 3326 3327 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3328 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3329 3330 return ret; 3331 } 3332 3333 static int smu_set_xgmi_pstate(void *handle, 3334 uint32_t pstate) 3335 { 3336 struct smu_context *smu = handle; 3337 int ret = 0; 3338 3339 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3340 return -EOPNOTSUPP; 3341 3342 if (smu->ppt_funcs->set_xgmi_pstate) 3343 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3344 3345 if (ret) 3346 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3347 3348 return ret; 3349 } 3350 3351 static int smu_get_baco_capability(void *handle) 3352 { 3353 struct smu_context *smu = handle; 3354 3355 if (!smu->pm_enabled) 3356 return false; 3357 3358 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3359 return false; 3360 3361 return smu->ppt_funcs->get_bamaco_support(smu); 3362 } 3363 3364 static int smu_baco_set_state(void *handle, int state) 3365 { 3366 struct smu_context *smu = handle; 3367 int ret = 0; 3368 3369 if (!smu->pm_enabled) 3370 return -EOPNOTSUPP; 3371 3372 if (state == 0) { 3373 if (smu->ppt_funcs->baco_exit) 3374 ret = smu->ppt_funcs->baco_exit(smu); 3375 } else if (state == 1) { 3376 if (smu->ppt_funcs->baco_enter) 3377 ret = smu->ppt_funcs->baco_enter(smu); 3378 } else { 3379 return -EINVAL; 3380 } 3381 3382 if (ret) 3383 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3384 (state)?"enter":"exit"); 3385 3386 return ret; 3387 } 3388 3389 bool smu_mode1_reset_is_support(struct smu_context *smu) 3390 { 3391 bool ret = false; 3392 3393 if (!smu->pm_enabled) 3394 return false; 3395 3396 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3397 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3398 3399 return ret; 3400 } 3401 3402 bool smu_mode2_reset_is_support(struct smu_context *smu) 3403 { 3404 bool ret = false; 3405 3406 if (!smu->pm_enabled) 3407 return false; 3408 3409 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3410 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3411 3412 return ret; 3413 } 3414 3415 int smu_mode1_reset(struct smu_context *smu) 3416 { 3417 int ret = 0; 3418 3419 if (!smu->pm_enabled) 3420 return -EOPNOTSUPP; 3421 3422 if (smu->ppt_funcs->mode1_reset) 3423 ret = smu->ppt_funcs->mode1_reset(smu); 3424 3425 return ret; 3426 } 3427 3428 static int smu_mode2_reset(void *handle) 3429 { 3430 struct smu_context *smu = handle; 3431 int ret = 0; 3432 3433 if (!smu->pm_enabled) 3434 return -EOPNOTSUPP; 3435 3436 if (smu->ppt_funcs->mode2_reset) 3437 ret = smu->ppt_funcs->mode2_reset(smu); 3438 3439 if (ret) 3440 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3441 3442 return ret; 3443 } 3444 3445 static int smu_enable_gfx_features(void *handle) 3446 { 3447 struct smu_context *smu = handle; 3448 int ret = 0; 3449 3450 if (!smu->pm_enabled) 3451 return -EOPNOTSUPP; 3452 3453 if (smu->ppt_funcs->enable_gfx_features) 3454 ret = smu->ppt_funcs->enable_gfx_features(smu); 3455 3456 if (ret) 3457 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3458 3459 return ret; 3460 } 3461 3462 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3463 struct pp_smu_nv_clock_table *max_clocks) 3464 { 3465 struct smu_context *smu = handle; 3466 int ret = 0; 3467 3468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3469 return -EOPNOTSUPP; 3470 3471 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3472 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3473 3474 return ret; 3475 } 3476 3477 static int smu_get_uclk_dpm_states(void *handle, 3478 unsigned int *clock_values_in_khz, 3479 unsigned int *num_states) 3480 { 3481 struct smu_context *smu = handle; 3482 int ret = 0; 3483 3484 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3485 return -EOPNOTSUPP; 3486 3487 if (smu->ppt_funcs->get_uclk_dpm_states) 3488 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3489 3490 return ret; 3491 } 3492 3493 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3494 { 3495 struct smu_context *smu = handle; 3496 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3497 3498 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3499 return -EOPNOTSUPP; 3500 3501 if (smu->ppt_funcs->get_current_power_state) 3502 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3503 3504 return pm_state; 3505 } 3506 3507 static int smu_get_dpm_clock_table(void *handle, 3508 struct dpm_clocks *clock_table) 3509 { 3510 struct smu_context *smu = handle; 3511 int ret = 0; 3512 3513 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3514 return -EOPNOTSUPP; 3515 3516 if (smu->ppt_funcs->get_dpm_clock_table) 3517 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3518 3519 return ret; 3520 } 3521 3522 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3523 { 3524 struct smu_context *smu = handle; 3525 3526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3527 return -EOPNOTSUPP; 3528 3529 if (!smu->ppt_funcs->get_gpu_metrics) 3530 return -EOPNOTSUPP; 3531 3532 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3533 } 3534 3535 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3536 size_t size) 3537 { 3538 struct smu_context *smu = handle; 3539 3540 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3541 return -EOPNOTSUPP; 3542 3543 if (!smu->ppt_funcs->get_pm_metrics) 3544 return -EOPNOTSUPP; 3545 3546 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3547 } 3548 3549 static int smu_enable_mgpu_fan_boost(void *handle) 3550 { 3551 struct smu_context *smu = handle; 3552 int ret = 0; 3553 3554 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3555 return -EOPNOTSUPP; 3556 3557 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3558 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3559 3560 return ret; 3561 } 3562 3563 static int smu_gfx_state_change_set(void *handle, 3564 uint32_t state) 3565 { 3566 struct smu_context *smu = handle; 3567 int ret = 0; 3568 3569 if (smu->ppt_funcs->gfx_state_change_set) 3570 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3571 3572 return ret; 3573 } 3574 3575 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3576 { 3577 int ret = 0; 3578 3579 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3580 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3581 3582 return ret; 3583 } 3584 3585 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3586 { 3587 int ret = -EOPNOTSUPP; 3588 3589 if (smu->ppt_funcs && 3590 smu->ppt_funcs->get_ecc_info) 3591 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3592 3593 return ret; 3594 3595 } 3596 3597 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3598 { 3599 struct smu_context *smu = handle; 3600 struct smu_table_context *smu_table = &smu->smu_table; 3601 struct smu_table *memory_pool = &smu_table->memory_pool; 3602 3603 if (!addr || !size) 3604 return -EINVAL; 3605 3606 *addr = NULL; 3607 *size = 0; 3608 if (memory_pool->bo) { 3609 *addr = memory_pool->cpu_addr; 3610 *size = memory_pool->size; 3611 } 3612 3613 return 0; 3614 } 3615 3616 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3617 size_t *size) 3618 { 3619 size_t offset = *size; 3620 int level; 3621 3622 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3623 if (level == policy->current_level) 3624 offset += sysfs_emit_at(sysbuf, offset, 3625 "%d : %s*\n", level, 3626 policy->desc->get_desc(policy, level)); 3627 else 3628 offset += sysfs_emit_at(sysbuf, offset, 3629 "%d : %s\n", level, 3630 policy->desc->get_desc(policy, level)); 3631 } 3632 3633 *size = offset; 3634 } 3635 3636 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3637 enum pp_pm_policy p_type, char *sysbuf) 3638 { 3639 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3640 struct smu_dpm_policy_ctxt *policy_ctxt; 3641 struct smu_dpm_policy *dpm_policy; 3642 size_t offset = 0; 3643 3644 policy_ctxt = dpm_ctxt->dpm_policies; 3645 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3646 !policy_ctxt->policy_mask) 3647 return -EOPNOTSUPP; 3648 3649 if (p_type == PP_PM_POLICY_NONE) 3650 return -EINVAL; 3651 3652 dpm_policy = smu_get_pm_policy(smu, p_type); 3653 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3654 return -ENOENT; 3655 3656 if (!sysbuf) 3657 return -EINVAL; 3658 3659 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3660 3661 return offset; 3662 } 3663 3664 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3665 enum pp_pm_policy p_type) 3666 { 3667 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3668 struct smu_dpm_policy_ctxt *policy_ctxt; 3669 int i; 3670 3671 policy_ctxt = dpm_ctxt->dpm_policies; 3672 if (!policy_ctxt) 3673 return NULL; 3674 3675 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3676 if (policy_ctxt->policies[i].policy_type == p_type) 3677 return &policy_ctxt->policies[i]; 3678 } 3679 3680 return NULL; 3681 } 3682 3683 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3684 int level) 3685 { 3686 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3687 struct smu_dpm_policy *dpm_policy = NULL; 3688 struct smu_dpm_policy_ctxt *policy_ctxt; 3689 int ret = -EOPNOTSUPP; 3690 3691 policy_ctxt = dpm_ctxt->dpm_policies; 3692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3693 !policy_ctxt->policy_mask) 3694 return ret; 3695 3696 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3697 return -EINVAL; 3698 3699 dpm_policy = smu_get_pm_policy(smu, p_type); 3700 3701 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3702 return ret; 3703 3704 if (dpm_policy->current_level == level) 3705 return 0; 3706 3707 ret = dpm_policy->set_policy(smu, level); 3708 3709 if (!ret) 3710 dpm_policy->current_level = level; 3711 3712 return ret; 3713 } 3714 3715 static const struct amd_pm_funcs swsmu_pm_funcs = { 3716 /* export for sysfs */ 3717 .set_fan_control_mode = smu_set_fan_control_mode, 3718 .get_fan_control_mode = smu_get_fan_control_mode, 3719 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3720 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3721 .force_clock_level = smu_force_ppclk_levels, 3722 .print_clock_levels = smu_print_ppclk_levels, 3723 .emit_clock_levels = smu_emit_ppclk_levels, 3724 .force_performance_level = smu_force_performance_level, 3725 .read_sensor = smu_read_sensor, 3726 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3727 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3728 .get_performance_level = smu_get_performance_level, 3729 .get_current_power_state = smu_get_current_power_state, 3730 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3731 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3732 .get_pp_num_states = smu_get_power_num_states, 3733 .get_pp_table = smu_sys_get_pp_table, 3734 .set_pp_table = smu_sys_set_pp_table, 3735 .switch_power_profile = smu_switch_power_profile, 3736 /* export to amdgpu */ 3737 .dispatch_tasks = smu_handle_dpm_task, 3738 .load_firmware = smu_load_microcode, 3739 .set_powergating_by_smu = smu_dpm_set_power_gate, 3740 .set_power_limit = smu_set_power_limit, 3741 .get_power_limit = smu_get_power_limit, 3742 .get_power_profile_mode = smu_get_power_profile_mode, 3743 .set_power_profile_mode = smu_set_power_profile_mode, 3744 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3745 .set_mp1_state = smu_set_mp1_state, 3746 .gfx_state_change_set = smu_gfx_state_change_set, 3747 /* export to DC */ 3748 .get_sclk = smu_get_sclk, 3749 .get_mclk = smu_get_mclk, 3750 .display_configuration_change = smu_display_configuration_change, 3751 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3752 .display_clock_voltage_request = smu_display_clock_voltage_request, 3753 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3754 .set_active_display_count = smu_set_display_count, 3755 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3756 .get_asic_baco_capability = smu_get_baco_capability, 3757 .set_asic_baco_state = smu_baco_set_state, 3758 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3759 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3760 .asic_reset_mode_2 = smu_mode2_reset, 3761 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3762 .set_df_cstate = smu_set_df_cstate, 3763 .set_xgmi_pstate = smu_set_xgmi_pstate, 3764 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3765 .get_pm_metrics = smu_sys_get_pm_metrics, 3766 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3767 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3768 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3769 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3770 .get_dpm_clock_table = smu_get_dpm_clock_table, 3771 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3772 }; 3773 3774 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3775 uint64_t event_arg) 3776 { 3777 int ret = -EINVAL; 3778 3779 if (smu->ppt_funcs->wait_for_event) 3780 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3781 3782 return ret; 3783 } 3784 3785 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3786 { 3787 3788 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3789 return -EOPNOTSUPP; 3790 3791 /* Confirm the buffer allocated is of correct size */ 3792 if (size != smu->stb_context.stb_buf_size) 3793 return -EINVAL; 3794 3795 /* 3796 * No need to lock smu mutex as we access STB directly through MMIO 3797 * and not going through SMU messaging route (for now at least). 3798 * For registers access rely on implementation internal locking. 3799 */ 3800 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3801 } 3802 3803 #if defined(CONFIG_DEBUG_FS) 3804 3805 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3806 { 3807 struct amdgpu_device *adev = filp->f_inode->i_private; 3808 struct smu_context *smu = adev->powerplay.pp_handle; 3809 unsigned char *buf; 3810 int r; 3811 3812 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3813 if (!buf) 3814 return -ENOMEM; 3815 3816 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3817 if (r) 3818 goto out; 3819 3820 filp->private_data = buf; 3821 3822 return 0; 3823 3824 out: 3825 kvfree(buf); 3826 return r; 3827 } 3828 3829 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3830 loff_t *pos) 3831 { 3832 struct amdgpu_device *adev = filp->f_inode->i_private; 3833 struct smu_context *smu = adev->powerplay.pp_handle; 3834 3835 3836 if (!filp->private_data) 3837 return -EINVAL; 3838 3839 return simple_read_from_buffer(buf, 3840 size, 3841 pos, filp->private_data, 3842 smu->stb_context.stb_buf_size); 3843 } 3844 3845 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3846 { 3847 kvfree(filp->private_data); 3848 filp->private_data = NULL; 3849 3850 return 0; 3851 } 3852 3853 /* 3854 * We have to define not only read method but also 3855 * open and release because .read takes up to PAGE_SIZE 3856 * data each time so and so is invoked multiple times. 3857 * We allocate the STB buffer in .open and release it 3858 * in .release 3859 */ 3860 static const struct file_operations smu_stb_debugfs_fops = { 3861 .owner = THIS_MODULE, 3862 .open = smu_stb_debugfs_open, 3863 .read = smu_stb_debugfs_read, 3864 .release = smu_stb_debugfs_release, 3865 .llseek = default_llseek, 3866 }; 3867 3868 #endif 3869 3870 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3871 { 3872 #if defined(CONFIG_DEBUG_FS) 3873 3874 struct smu_context *smu = adev->powerplay.pp_handle; 3875 3876 if (!smu || (!smu->stb_context.stb_buf_size)) 3877 return; 3878 3879 debugfs_create_file_size("amdgpu_smu_stb_dump", 3880 S_IRUSR, 3881 adev_to_drm(adev)->primary->debugfs_root, 3882 adev, 3883 &smu_stb_debugfs_fops, 3884 smu->stb_context.stb_buf_size); 3885 #endif 3886 } 3887 3888 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3889 { 3890 int ret = 0; 3891 3892 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3893 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3894 3895 return ret; 3896 } 3897 3898 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3899 { 3900 int ret = 0; 3901 3902 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3903 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3904 3905 return ret; 3906 } 3907 3908 int smu_send_rma_reason(struct smu_context *smu) 3909 { 3910 int ret = 0; 3911 3912 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3913 ret = smu->ppt_funcs->send_rma_reason(smu); 3914 3915 return ret; 3916 } 3917 3918 /** 3919 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 3920 * @smu: smu_context pointer 3921 * 3922 * This function checks if the SMU supports resetting the SDMA engine. 3923 * It returns true if supported, false otherwise. 3924 */ 3925 bool smu_reset_sdma_is_supported(struct smu_context *smu) 3926 { 3927 bool ret = false; 3928 3929 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma_is_supported) 3930 ret = smu->ppt_funcs->reset_sdma_is_supported(smu); 3931 3932 return ret; 3933 } 3934 3935 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 3936 { 3937 int ret = 0; 3938 3939 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 3940 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 3941 3942 return ret; 3943 } 3944