1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 137 }; 138 139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 142 }; 143 144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = { 151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0), 152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = { 164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0), 165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0, 166 }; 167 168 169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 170 const struct amdgpu_video_codecs **codecs) 171 { 172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 173 return -EINVAL; 174 175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 176 case IP_VERSION(4, 0, 0): 177 case IP_VERSION(4, 0, 2): 178 case IP_VERSION(4, 0, 4): 179 case IP_VERSION(4, 0, 5): 180 if (amdgpu_sriov_vf(adev)) { 181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 182 !amdgpu_sriov_is_av1_support(adev)) { 183 if (encode) 184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } else { 194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 195 if (encode) 196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 197 else 198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 199 } else { 200 if (encode) 201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 202 else 203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 204 } 205 } 206 return 0; 207 case IP_VERSION(4, 0, 6): 208 if (encode) 209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 210 else 211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 212 return 0; 213 case IP_VERSION(5, 3, 0): 214 if (encode) 215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0; 216 else 217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0; 218 return 0; 219 default: 220 return -EINVAL; 221 } 222 } 223 224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags, address, data; 227 u32 r; 228 229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 231 232 spin_lock_irqsave(&adev->didt_idx_lock, flags); 233 WREG32(address, (reg)); 234 r = RREG32(data); 235 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 236 return r; 237 } 238 239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 240 { 241 unsigned long flags, address, data; 242 243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 245 246 spin_lock_irqsave(&adev->didt_idx_lock, flags); 247 WREG32(address, (reg)); 248 WREG32(data, (v)); 249 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 250 } 251 252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 253 { 254 return adev->nbio.funcs->get_memsize(adev); 255 } 256 257 static u32 soc21_get_xclk(struct amdgpu_device *adev) 258 { 259 u32 reference_clock = adev->clock.spll.reference_freq; 260 261 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ 262 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) 263 return 9981; 264 265 return reference_clock; 266 } 267 268 269 void soc21_grbm_select(struct amdgpu_device *adev, 270 u32 me, u32 pipe, u32 queue, u32 vmid) 271 { 272 u32 grbm_gfx_cntl = 0; 273 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 277 278 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 279 } 280 281 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 282 { 283 /* todo */ 284 return false; 285 } 286 287 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 288 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 295 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 296 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 297 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 300 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 303 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 306 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 307 }; 308 309 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 310 u32 sh_num, u32 reg_offset) 311 { 312 uint32_t val; 313 314 mutex_lock(&adev->grbm_idx_mutex); 315 if (se_num != 0xffffffff || sh_num != 0xffffffff) 316 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 317 318 val = RREG32(reg_offset); 319 320 if (se_num != 0xffffffff || sh_num != 0xffffffff) 321 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 322 mutex_unlock(&adev->grbm_idx_mutex); 323 return val; 324 } 325 326 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 327 bool indexed, u32 se_num, 328 u32 sh_num, u32 reg_offset) 329 { 330 if (indexed) { 331 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 332 } else { 333 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 334 return adev->gfx.config.gb_addr_config; 335 return RREG32(reg_offset); 336 } 337 } 338 339 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 340 u32 sh_num, u32 reg_offset, u32 *value) 341 { 342 uint32_t i; 343 struct soc15_allowed_register_entry *en; 344 345 *value = 0; 346 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 347 en = &soc21_allowed_read_registers[i]; 348 if (!adev->reg_offset[en->hwip][en->inst]) 349 continue; 350 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 351 + en->reg_offset)) 352 continue; 353 354 *value = soc21_get_register_value(adev, 355 soc21_allowed_read_registers[i].grbm_indexed, 356 se_num, sh_num, reg_offset); 357 return 0; 358 } 359 return -EINVAL; 360 } 361 362 #if 0 363 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 364 { 365 u32 i; 366 int ret = 0; 367 368 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 369 370 /* disable BM */ 371 pci_clear_master(adev->pdev); 372 373 amdgpu_device_cache_pci_state(adev->pdev); 374 375 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 376 dev_info(adev->dev, "GPU smu mode1 reset\n"); 377 ret = amdgpu_dpm_mode1_reset(adev); 378 } else { 379 dev_info(adev->dev, "GPU psp mode1 reset\n"); 380 ret = psp_gpu_reset(adev); 381 } 382 383 if (ret) 384 dev_err(adev->dev, "GPU mode1 reset failed\n"); 385 amdgpu_device_load_pci_state(adev->pdev); 386 387 /* wait for asic to come out of reset */ 388 for (i = 0; i < adev->usec_timeout; i++) { 389 u32 memsize = adev->nbio.funcs->get_memsize(adev); 390 391 if (memsize != 0xffffffff) 392 break; 393 udelay(1); 394 } 395 396 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 397 398 return ret; 399 } 400 #endif 401 402 static enum amd_reset_method 403 soc21_asic_reset_method(struct amdgpu_device *adev) 404 { 405 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 406 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 407 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 408 return amdgpu_reset_method; 409 410 if (amdgpu_reset_method != -1) 411 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 412 amdgpu_reset_method); 413 414 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 415 case IP_VERSION(13, 0, 0): 416 case IP_VERSION(13, 0, 7): 417 case IP_VERSION(13, 0, 10): 418 return AMD_RESET_METHOD_MODE1; 419 case IP_VERSION(13, 0, 4): 420 case IP_VERSION(13, 0, 11): 421 case IP_VERSION(14, 0, 0): 422 case IP_VERSION(14, 0, 1): 423 case IP_VERSION(14, 0, 4): 424 case IP_VERSION(14, 0, 5): 425 return AMD_RESET_METHOD_MODE2; 426 default: 427 if (amdgpu_dpm_is_baco_supported(adev)) 428 return AMD_RESET_METHOD_BACO; 429 else 430 return AMD_RESET_METHOD_MODE1; 431 } 432 } 433 434 static int soc21_asic_reset(struct amdgpu_device *adev) 435 { 436 int ret = 0; 437 438 switch (soc21_asic_reset_method(adev)) { 439 case AMD_RESET_METHOD_PCI: 440 dev_info(adev->dev, "PCI reset\n"); 441 ret = amdgpu_device_pci_reset(adev); 442 break; 443 case AMD_RESET_METHOD_BACO: 444 dev_info(adev->dev, "BACO reset\n"); 445 ret = amdgpu_dpm_baco_reset(adev); 446 break; 447 case AMD_RESET_METHOD_MODE2: 448 dev_info(adev->dev, "MODE2 reset\n"); 449 ret = amdgpu_dpm_mode2_reset(adev); 450 break; 451 default: 452 dev_info(adev->dev, "MODE1 reset\n"); 453 ret = amdgpu_device_mode1_reset(adev); 454 break; 455 } 456 457 return ret; 458 } 459 460 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 461 { 462 /* todo */ 463 return 0; 464 } 465 466 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 467 { 468 /* todo */ 469 return 0; 470 } 471 472 static void soc21_program_aspm(struct amdgpu_device *adev) 473 { 474 if (!amdgpu_device_should_use_aspm(adev)) 475 return; 476 477 if (adev->nbio.funcs->program_aspm) 478 adev->nbio.funcs->program_aspm(adev); 479 } 480 481 const struct amdgpu_ip_block_version soc21_common_ip_block = { 482 .type = AMD_IP_BLOCK_TYPE_COMMON, 483 .major = 1, 484 .minor = 0, 485 .rev = 0, 486 .funcs = &soc21_common_ip_funcs, 487 }; 488 489 static bool soc21_need_full_reset(struct amdgpu_device *adev) 490 { 491 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 492 case IP_VERSION(11, 0, 0): 493 case IP_VERSION(11, 0, 2): 494 case IP_VERSION(11, 0, 3): 495 default: 496 return true; 497 } 498 } 499 500 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 501 { 502 u32 sol_reg; 503 504 if (adev->flags & AMD_IS_APU) 505 return false; 506 507 /* Check sOS sign of life register to confirm sys driver and sOS 508 * are already been loaded. 509 */ 510 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 511 if (sol_reg) 512 return true; 513 514 return false; 515 } 516 517 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 518 { 519 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 520 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 521 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 522 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 523 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 524 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 525 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 526 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 527 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 528 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 529 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 530 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 531 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 532 adev->doorbell_index.gfx_userqueue_start = 533 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 534 adev->doorbell_index.gfx_userqueue_end = 535 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 536 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 537 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 538 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 539 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 540 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 541 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 542 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 543 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 544 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 545 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; 546 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 547 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 548 549 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 550 adev->doorbell_index.sdma_doorbell_range = 20; 551 } 552 553 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 554 bool enter) 555 { 556 if (enter) 557 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 558 else 559 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 560 561 if (adev->gfx.funcs->update_perfmon_mgcg) 562 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 563 564 return 0; 565 } 566 567 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 568 .read_disabled_bios = &soc21_read_disabled_bios, 569 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 570 .read_register = &soc21_read_register, 571 .reset = &soc21_asic_reset, 572 .reset_method = &soc21_asic_reset_method, 573 .get_xclk = &soc21_get_xclk, 574 .set_uvd_clocks = &soc21_set_uvd_clocks, 575 .set_vce_clocks = &soc21_set_vce_clocks, 576 .get_config_memsize = &soc21_get_config_memsize, 577 .init_doorbell_index = &soc21_init_doorbell_index, 578 .need_full_reset = &soc21_need_full_reset, 579 .need_reset_on_init = &soc21_need_reset_on_init, 580 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 581 .supports_baco = &amdgpu_dpm_is_baco_supported, 582 .query_video_codecs = &soc21_query_video_codecs, 583 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 584 }; 585 586 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) 587 { 588 struct amdgpu_device *adev = ip_block->adev; 589 590 adev->nbio.funcs->set_reg_remap(adev); 591 adev->smc_rreg = NULL; 592 adev->smc_wreg = NULL; 593 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 594 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 595 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 596 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 597 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 598 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 599 600 /* TODO: will add them during VCN v2 implementation */ 601 adev->uvd_ctx_rreg = NULL; 602 adev->uvd_ctx_wreg = NULL; 603 604 adev->didt_rreg = &soc21_didt_rreg; 605 adev->didt_wreg = &soc21_didt_wreg; 606 607 adev->asic_funcs = &soc21_asic_funcs; 608 609 adev->rev_id = amdgpu_device_get_rev_id(adev); 610 adev->external_rev_id = 0xff; 611 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 612 case IP_VERSION(11, 0, 0): 613 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 614 AMD_CG_SUPPORT_GFX_CGLS | 615 #if 0 616 AMD_CG_SUPPORT_GFX_3D_CGCG | 617 AMD_CG_SUPPORT_GFX_3D_CGLS | 618 #endif 619 AMD_CG_SUPPORT_GFX_MGCG | 620 AMD_CG_SUPPORT_REPEATER_FGCG | 621 AMD_CG_SUPPORT_GFX_FGCG | 622 AMD_CG_SUPPORT_GFX_PERF_CLK | 623 AMD_CG_SUPPORT_VCN_MGCG | 624 AMD_CG_SUPPORT_JPEG_MGCG | 625 AMD_CG_SUPPORT_ATHUB_MGCG | 626 AMD_CG_SUPPORT_ATHUB_LS | 627 AMD_CG_SUPPORT_MC_MGCG | 628 AMD_CG_SUPPORT_MC_LS | 629 AMD_CG_SUPPORT_IH_CG | 630 AMD_CG_SUPPORT_HDP_SD; 631 adev->pg_flags = AMD_PG_SUPPORT_VCN | 632 AMD_PG_SUPPORT_VCN_DPG | 633 AMD_PG_SUPPORT_JPEG | 634 AMD_PG_SUPPORT_ATHUB | 635 AMD_PG_SUPPORT_MMHUB; 636 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 637 break; 638 case IP_VERSION(11, 0, 2): 639 adev->cg_flags = 640 AMD_CG_SUPPORT_GFX_CGCG | 641 AMD_CG_SUPPORT_GFX_CGLS | 642 AMD_CG_SUPPORT_REPEATER_FGCG | 643 AMD_CG_SUPPORT_VCN_MGCG | 644 AMD_CG_SUPPORT_JPEG_MGCG | 645 AMD_CG_SUPPORT_ATHUB_MGCG | 646 AMD_CG_SUPPORT_ATHUB_LS | 647 AMD_CG_SUPPORT_IH_CG | 648 AMD_CG_SUPPORT_HDP_SD; 649 adev->pg_flags = 650 AMD_PG_SUPPORT_VCN | 651 AMD_PG_SUPPORT_VCN_DPG | 652 AMD_PG_SUPPORT_JPEG | 653 AMD_PG_SUPPORT_ATHUB | 654 AMD_PG_SUPPORT_MMHUB; 655 adev->external_rev_id = adev->rev_id + 0x10; 656 break; 657 case IP_VERSION(11, 0, 1): 658 adev->cg_flags = 659 AMD_CG_SUPPORT_GFX_CGCG | 660 AMD_CG_SUPPORT_GFX_CGLS | 661 AMD_CG_SUPPORT_GFX_MGCG | 662 AMD_CG_SUPPORT_GFX_FGCG | 663 AMD_CG_SUPPORT_REPEATER_FGCG | 664 AMD_CG_SUPPORT_GFX_PERF_CLK | 665 AMD_CG_SUPPORT_MC_MGCG | 666 AMD_CG_SUPPORT_MC_LS | 667 AMD_CG_SUPPORT_HDP_MGCG | 668 AMD_CG_SUPPORT_HDP_LS | 669 AMD_CG_SUPPORT_ATHUB_MGCG | 670 AMD_CG_SUPPORT_ATHUB_LS | 671 AMD_CG_SUPPORT_IH_CG | 672 AMD_CG_SUPPORT_BIF_MGCG | 673 AMD_CG_SUPPORT_BIF_LS | 674 AMD_CG_SUPPORT_VCN_MGCG | 675 AMD_CG_SUPPORT_JPEG_MGCG; 676 adev->pg_flags = 677 AMD_PG_SUPPORT_GFX_PG | 678 AMD_PG_SUPPORT_VCN | 679 AMD_PG_SUPPORT_VCN_DPG | 680 AMD_PG_SUPPORT_JPEG; 681 adev->external_rev_id = adev->rev_id + 0x1; 682 break; 683 case IP_VERSION(11, 0, 3): 684 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 685 AMD_CG_SUPPORT_JPEG_MGCG | 686 AMD_CG_SUPPORT_GFX_CGCG | 687 AMD_CG_SUPPORT_GFX_CGLS | 688 AMD_CG_SUPPORT_REPEATER_FGCG | 689 AMD_CG_SUPPORT_GFX_MGCG | 690 AMD_CG_SUPPORT_HDP_SD | 691 AMD_CG_SUPPORT_ATHUB_MGCG | 692 AMD_CG_SUPPORT_ATHUB_LS; 693 adev->pg_flags = AMD_PG_SUPPORT_VCN | 694 AMD_PG_SUPPORT_VCN_DPG | 695 AMD_PG_SUPPORT_JPEG; 696 adev->external_rev_id = adev->rev_id + 0x20; 697 break; 698 case IP_VERSION(11, 0, 4): 699 adev->cg_flags = 700 AMD_CG_SUPPORT_GFX_CGCG | 701 AMD_CG_SUPPORT_GFX_CGLS | 702 AMD_CG_SUPPORT_GFX_MGCG | 703 AMD_CG_SUPPORT_GFX_FGCG | 704 AMD_CG_SUPPORT_REPEATER_FGCG | 705 AMD_CG_SUPPORT_GFX_PERF_CLK | 706 AMD_CG_SUPPORT_MC_MGCG | 707 AMD_CG_SUPPORT_MC_LS | 708 AMD_CG_SUPPORT_HDP_MGCG | 709 AMD_CG_SUPPORT_HDP_LS | 710 AMD_CG_SUPPORT_ATHUB_MGCG | 711 AMD_CG_SUPPORT_ATHUB_LS | 712 AMD_CG_SUPPORT_IH_CG | 713 AMD_CG_SUPPORT_BIF_MGCG | 714 AMD_CG_SUPPORT_BIF_LS | 715 AMD_CG_SUPPORT_VCN_MGCG | 716 AMD_CG_SUPPORT_JPEG_MGCG; 717 adev->pg_flags = AMD_PG_SUPPORT_VCN | 718 AMD_PG_SUPPORT_VCN_DPG | 719 AMD_PG_SUPPORT_GFX_PG | 720 AMD_PG_SUPPORT_JPEG; 721 adev->external_rev_id = adev->rev_id + 0x80; 722 break; 723 case IP_VERSION(11, 5, 0): 724 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 725 AMD_CG_SUPPORT_JPEG_MGCG | 726 AMD_CG_SUPPORT_GFX_CGCG | 727 AMD_CG_SUPPORT_GFX_CGLS | 728 AMD_CG_SUPPORT_GFX_MGCG | 729 AMD_CG_SUPPORT_GFX_FGCG | 730 AMD_CG_SUPPORT_REPEATER_FGCG | 731 AMD_CG_SUPPORT_GFX_PERF_CLK | 732 AMD_CG_SUPPORT_GFX_3D_CGCG | 733 AMD_CG_SUPPORT_GFX_3D_CGLS | 734 AMD_CG_SUPPORT_MC_MGCG | 735 AMD_CG_SUPPORT_MC_LS | 736 AMD_CG_SUPPORT_HDP_LS | 737 AMD_CG_SUPPORT_HDP_DS | 738 AMD_CG_SUPPORT_HDP_SD | 739 AMD_CG_SUPPORT_ATHUB_MGCG | 740 AMD_CG_SUPPORT_ATHUB_LS | 741 AMD_CG_SUPPORT_IH_CG | 742 AMD_CG_SUPPORT_BIF_MGCG | 743 AMD_CG_SUPPORT_BIF_LS; 744 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 745 AMD_PG_SUPPORT_JPEG_DPG | 746 AMD_PG_SUPPORT_VCN | 747 AMD_PG_SUPPORT_JPEG | 748 AMD_PG_SUPPORT_GFX_PG; 749 if (adev->rev_id == 0) 750 adev->external_rev_id = 0x1; 751 else 752 adev->external_rev_id = adev->rev_id + 0x10; 753 break; 754 case IP_VERSION(11, 5, 1): 755 adev->cg_flags = 756 AMD_CG_SUPPORT_GFX_CGCG | 757 AMD_CG_SUPPORT_GFX_CGLS | 758 AMD_CG_SUPPORT_GFX_MGCG | 759 AMD_CG_SUPPORT_GFX_FGCG | 760 AMD_CG_SUPPORT_REPEATER_FGCG | 761 AMD_CG_SUPPORT_GFX_PERF_CLK | 762 AMD_CG_SUPPORT_GFX_3D_CGCG | 763 AMD_CG_SUPPORT_GFX_3D_CGLS | 764 AMD_CG_SUPPORT_MC_MGCG | 765 AMD_CG_SUPPORT_MC_LS | 766 AMD_CG_SUPPORT_HDP_LS | 767 AMD_CG_SUPPORT_HDP_DS | 768 AMD_CG_SUPPORT_HDP_SD | 769 AMD_CG_SUPPORT_ATHUB_MGCG | 770 AMD_CG_SUPPORT_ATHUB_LS | 771 AMD_CG_SUPPORT_IH_CG | 772 AMD_CG_SUPPORT_BIF_MGCG | 773 AMD_CG_SUPPORT_BIF_LS | 774 AMD_CG_SUPPORT_VCN_MGCG | 775 AMD_CG_SUPPORT_JPEG_MGCG; 776 adev->pg_flags = 777 AMD_PG_SUPPORT_GFX_PG | 778 AMD_PG_SUPPORT_VCN | 779 AMD_PG_SUPPORT_VCN_DPG | 780 AMD_PG_SUPPORT_JPEG; 781 adev->external_rev_id = adev->rev_id + 0xc1; 782 break; 783 case IP_VERSION(11, 5, 2): 784 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 785 AMD_CG_SUPPORT_JPEG_MGCG | 786 AMD_CG_SUPPORT_GFX_CGCG | 787 AMD_CG_SUPPORT_GFX_CGLS | 788 AMD_CG_SUPPORT_GFX_MGCG | 789 AMD_CG_SUPPORT_GFX_FGCG | 790 AMD_CG_SUPPORT_REPEATER_FGCG | 791 AMD_CG_SUPPORT_GFX_PERF_CLK | 792 AMD_CG_SUPPORT_GFX_3D_CGCG | 793 AMD_CG_SUPPORT_GFX_3D_CGLS | 794 AMD_CG_SUPPORT_MC_MGCG | 795 AMD_CG_SUPPORT_MC_LS | 796 AMD_CG_SUPPORT_HDP_LS | 797 AMD_CG_SUPPORT_HDP_DS | 798 AMD_CG_SUPPORT_HDP_SD | 799 AMD_CG_SUPPORT_ATHUB_MGCG | 800 AMD_CG_SUPPORT_ATHUB_LS | 801 AMD_CG_SUPPORT_IH_CG | 802 AMD_CG_SUPPORT_BIF_MGCG | 803 AMD_CG_SUPPORT_BIF_LS; 804 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 805 AMD_PG_SUPPORT_VCN | 806 AMD_PG_SUPPORT_JPEG_DPG | 807 AMD_PG_SUPPORT_JPEG | 808 AMD_PG_SUPPORT_GFX_PG; 809 adev->external_rev_id = adev->rev_id + 0x40; 810 break; 811 case IP_VERSION(11, 5, 3): 812 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 813 AMD_CG_SUPPORT_JPEG_MGCG | 814 AMD_CG_SUPPORT_GFX_CGCG | 815 AMD_CG_SUPPORT_GFX_CGLS | 816 AMD_CG_SUPPORT_GFX_MGCG | 817 AMD_CG_SUPPORT_GFX_FGCG | 818 AMD_CG_SUPPORT_REPEATER_FGCG | 819 AMD_CG_SUPPORT_GFX_PERF_CLK | 820 AMD_CG_SUPPORT_GFX_3D_CGCG | 821 AMD_CG_SUPPORT_GFX_3D_CGLS | 822 AMD_CG_SUPPORT_MC_MGCG | 823 AMD_CG_SUPPORT_MC_LS | 824 AMD_CG_SUPPORT_HDP_LS | 825 AMD_CG_SUPPORT_HDP_DS | 826 AMD_CG_SUPPORT_HDP_SD | 827 AMD_CG_SUPPORT_ATHUB_MGCG | 828 AMD_CG_SUPPORT_ATHUB_LS | 829 AMD_CG_SUPPORT_IH_CG | 830 AMD_CG_SUPPORT_BIF_MGCG | 831 AMD_CG_SUPPORT_BIF_LS; 832 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 833 AMD_PG_SUPPORT_VCN | 834 AMD_PG_SUPPORT_JPEG_DPG | 835 AMD_PG_SUPPORT_JPEG | 836 AMD_PG_SUPPORT_GFX_PG; 837 adev->external_rev_id = adev->rev_id + 0x50; 838 break; 839 case IP_VERSION(11, 5, 4): 840 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 841 AMD_CG_SUPPORT_JPEG_MGCG; 842 adev->pg_flags = AMD_PG_SUPPORT_VCN | 843 AMD_PG_SUPPORT_JPEG; 844 adev->external_rev_id = adev->rev_id + 0x1; 845 break; 846 default: 847 /* FIXME: not supported yet */ 848 return -EINVAL; 849 } 850 851 if (amdgpu_sriov_vf(adev)) { 852 amdgpu_virt_init_setting(adev); 853 xgpu_nv_mailbox_set_irq_funcs(adev); 854 } 855 856 return 0; 857 } 858 859 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) 860 { 861 struct amdgpu_device *adev = ip_block->adev; 862 863 if (amdgpu_sriov_vf(adev)) { 864 xgpu_nv_mailbox_get_irq(adev); 865 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 866 !amdgpu_sriov_is_av1_support(adev)) { 867 amdgpu_virt_update_sriov_video_codec(adev, 868 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 869 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 870 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 871 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 872 } else { 873 amdgpu_virt_update_sriov_video_codec(adev, 874 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 875 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 876 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 877 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 878 } 879 } else { 880 if (adev->nbio.ras && 881 adev->nbio.ras_err_event_athub_irq.funcs) 882 /* don't need to fail gpu late init 883 * if enabling athub_err_event interrupt failed 884 * nbio v4_3 only support fatal error hanlding 885 * just enable the interrupt directly */ 886 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 887 } 888 889 /* Enable selfring doorbell aperture late because doorbell BAR 890 * aperture will change if resize BAR successfully in gmc sw_init. 891 */ 892 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 893 894 return 0; 895 } 896 897 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) 898 { 899 struct amdgpu_device *adev = ip_block->adev; 900 901 if (amdgpu_sriov_vf(adev)) 902 xgpu_nv_mailbox_add_irq_id(adev); 903 904 return 0; 905 } 906 907 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) 908 { 909 struct amdgpu_device *adev = ip_block->adev; 910 911 /* enable aspm */ 912 soc21_program_aspm(adev); 913 /* setup nbio registers */ 914 adev->nbio.funcs->init_registers(adev); 915 /* remap HDP registers to a hole in mmio space, 916 * for the purpose of expose those registers 917 * to process space 918 */ 919 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 920 adev->nbio.funcs->remap_hdp_registers(adev); 921 /* enable the doorbell aperture */ 922 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 923 924 return 0; 925 } 926 927 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block) 928 { 929 struct amdgpu_device *adev = ip_block->adev; 930 931 /* Disable the doorbell aperture and selfring doorbell aperture 932 * separately in hw_fini because soc21_enable_doorbell_aperture 933 * has been removed and there is no need to delay disabling 934 * selfring doorbell. 935 */ 936 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 937 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 938 939 if (amdgpu_sriov_vf(adev)) { 940 xgpu_nv_mailbox_put_irq(adev); 941 } else { 942 if (adev->nbio.ras && 943 adev->nbio.ras_err_event_athub_irq.funcs) 944 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 945 } 946 947 return 0; 948 } 949 950 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) 951 { 952 return soc21_common_hw_fini(ip_block); 953 } 954 955 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 956 { 957 u32 sol_reg1, sol_reg2; 958 959 /* Will reset for the following suspend abort cases. 960 * 1) Only reset dGPU side. 961 * 2) S3 suspend got aborted and TOS is active. 962 * As for dGPU suspend abort cases the SOL value 963 * will be kept as zero at this resume point. 964 */ 965 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 966 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 967 msleep(100); 968 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 969 970 return (sol_reg1 != sol_reg2); 971 } 972 973 return false; 974 } 975 976 static int soc21_common_resume(struct amdgpu_ip_block *ip_block) 977 { 978 struct amdgpu_device *adev = ip_block->adev; 979 980 if (soc21_need_reset_on_resume(adev)) { 981 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 982 soc21_asic_reset(adev); 983 } 984 985 return soc21_common_hw_init(ip_block); 986 } 987 988 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block) 989 { 990 return true; 991 } 992 993 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 994 enum amd_clockgating_state state) 995 { 996 struct amdgpu_device *adev = ip_block->adev; 997 998 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 999 case IP_VERSION(4, 3, 0): 1000 case IP_VERSION(4, 3, 1): 1001 case IP_VERSION(7, 7, 0): 1002 case IP_VERSION(7, 7, 1): 1003 case IP_VERSION(7, 11, 0): 1004 case IP_VERSION(7, 11, 1): 1005 case IP_VERSION(7, 11, 2): 1006 case IP_VERSION(7, 11, 3): 1007 case IP_VERSION(7, 11, 4): 1008 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1009 state == AMD_CG_STATE_GATE); 1010 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1011 state == AMD_CG_STATE_GATE); 1012 adev->hdp.funcs->update_clock_gating(adev, 1013 state == AMD_CG_STATE_GATE); 1014 break; 1015 default: 1016 break; 1017 } 1018 return 0; 1019 } 1020 1021 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1022 enum amd_powergating_state state) 1023 { 1024 struct amdgpu_device *adev = ip_block->adev; 1025 1026 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 1027 case IP_VERSION(6, 0, 0): 1028 case IP_VERSION(6, 0, 2): 1029 adev->lsdma.funcs->update_memory_power_gating(adev, 1030 state == AMD_PG_STATE_GATE); 1031 break; 1032 default: 1033 break; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1040 { 1041 struct amdgpu_device *adev = ip_block->adev; 1042 1043 adev->nbio.funcs->get_clockgating_state(adev, flags); 1044 1045 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1046 } 1047 1048 static const struct amd_ip_funcs soc21_common_ip_funcs = { 1049 .name = "soc21_common", 1050 .early_init = soc21_common_early_init, 1051 .late_init = soc21_common_late_init, 1052 .sw_init = soc21_common_sw_init, 1053 .hw_init = soc21_common_hw_init, 1054 .hw_fini = soc21_common_hw_fini, 1055 .suspend = soc21_common_suspend, 1056 .resume = soc21_common_resume, 1057 .is_idle = soc21_common_is_idle, 1058 .set_clockgating_state = soc21_common_set_clockgating_state, 1059 .set_powergating_state = soc21_common_set_powergating_state, 1060 .get_clockgating_state = soc21_common_get_clockgating_state, 1061 }; 1062