1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright © 2018 Broadcom 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_fb_dma_helper.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 #include <drm/drm_writeback.h> 27 28 #include "vc4_drv.h" 29 #include "vc4_regs.h" 30 31 /* Base address of the output. Raster formats must be 4-byte aligned, 32 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are 33 * inconsistent, but probably utile). 34 */ 35 #define TXP_DST_PTR 0x00 36 37 /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's 38 * the width in tiles. 39 */ 40 #define TXP_DST_PITCH 0x04 41 /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide, 42 * shifted up. 43 */ 44 # define TXP_T_TILE_WIDTH_SHIFT 7 45 /* For LT-tiled images, DST_PITCH should be the number of utiles wide, 46 * shifted up. 47 */ 48 # define TXP_LT_TILE_WIDTH_SHIFT 4 49 50 /* Pre-rotation width/height of the image. Must match HVS config. 51 * 52 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit 53 * and width/height must be tile or utile-aligned as appropriate. If 54 * transposing (rotating), width is limited to 1920. 55 * 56 * Height is limited to various numbers between 4088 and 4095. I'd 57 * just use 4088 to be safe. 58 */ 59 #define TXP_DIM 0x08 60 # define TXP_HEIGHT_SHIFT 16 61 # define TXP_HEIGHT_MASK GENMASK(31, 16) 62 # define TXP_WIDTH_SHIFT 0 63 # define TXP_WIDTH_MASK GENMASK(15, 0) 64 65 #define TXP_DST_CTRL 0x0c 66 /* These bits are set to 0x54 */ 67 #define TXP_PILOT_SHIFT 24 68 #define TXP_PILOT_MASK GENMASK(31, 24) 69 /* Bits 22-23 are set to 0x01 */ 70 #define TXP_VERSION_SHIFT 22 71 #define TXP_VERSION_MASK GENMASK(23, 22) 72 73 /* Powers down the internal memory. */ 74 # define TXP_POWERDOWN BIT(21) 75 76 /* Enables storing the alpha component in 8888/4444, instead of 77 * filling with ~ALPHA_INVERT. 78 */ 79 # define TXP_ALPHA_ENABLE BIT(20) 80 81 /* 4 bits, each enables stores for a channel in each set of 4 bytes. 82 * Set to 0xf for normal operation. 83 */ 84 # define TXP_BYTE_ENABLE_SHIFT 16 85 # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16) 86 87 /* Debug: Generate VSTART again at EOF. */ 88 # define TXP_VSTART_AT_EOF BIT(15) 89 90 /* Debug: Terminate the current frame immediately. Stops AXI 91 * writes. 92 */ 93 # define TXP_ABORT BIT(14) 94 95 # define TXP_DITHER BIT(13) 96 97 /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for 98 * !TXP_ALPHA_ENABLE. 99 */ 100 # define TXP_ALPHA_INVERT BIT(12) 101 102 /* Note: I've listed the channels here in high bit (in byte 3/2/1) to 103 * low bit (in byte 0) order. 104 */ 105 # define TXP_FORMAT_SHIFT 8 106 # define TXP_FORMAT_MASK GENMASK(11, 8) 107 # define TXP_FORMAT_ABGR4444 0 108 # define TXP_FORMAT_ARGB4444 1 109 # define TXP_FORMAT_BGRA4444 2 110 # define TXP_FORMAT_RGBA4444 3 111 # define TXP_FORMAT_BGR565 6 112 # define TXP_FORMAT_RGB565 7 113 /* 888s are non-rotated, raster-only */ 114 # define TXP_FORMAT_BGR888 8 115 # define TXP_FORMAT_RGB888 9 116 # define TXP_FORMAT_ABGR8888 12 117 # define TXP_FORMAT_ARGB8888 13 118 # define TXP_FORMAT_BGRA8888 14 119 # define TXP_FORMAT_RGBA8888 15 120 121 /* If TFORMAT is set, generates LT instead of T format. */ 122 # define TXP_LINEAR_UTILE BIT(7) 123 124 /* Rotate output by 90 degrees. */ 125 # define TXP_TRANSPOSE BIT(6) 126 127 /* Generate a tiled format for V3D. */ 128 # define TXP_TFORMAT BIT(5) 129 130 /* Generates some undefined test mode output. */ 131 # define TXP_TEST_MODE BIT(4) 132 133 /* Request odd field from HVS. */ 134 # define TXP_FIELD BIT(3) 135 136 /* Raise interrupt when idle. */ 137 # define TXP_EI BIT(2) 138 139 /* Set when generating a frame, clears when idle. */ 140 # define TXP_BUSY BIT(1) 141 142 /* Starts a frame. Self-clearing. */ 143 # define TXP_GO BIT(0) 144 145 /* Number of lines received and committed to memory. */ 146 #define TXP_PROGRESS 0x10 147 148 #define TXP_DST_PTR_HIGH_MOPLET 0x1c 149 #define TXP_DST_PTR_HIGH_MOP 0x24 150 151 #define TXP_READ(offset) \ 152 ({ \ 153 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 154 readl(txp->regs + (offset)); \ 155 }) 156 157 #define TXP_WRITE(offset, val) \ 158 do { \ 159 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 160 writel(val, txp->regs + (offset)); \ 161 } while (0) 162 163 struct vc4_txp { 164 struct vc4_crtc base; 165 const struct vc4_txp_data *data; 166 167 struct platform_device *pdev; 168 169 struct vc4_encoder encoder; 170 struct drm_writeback_connector connector; 171 172 void __iomem *regs; 173 }; 174 175 #define encoder_to_vc4_txp(_encoder) \ 176 container_of_const(_encoder, struct vc4_txp, encoder.base) 177 178 #define connector_to_vc4_txp(_connector) \ 179 container_of_const(_connector, struct vc4_txp, connector.base) 180 181 static const struct debugfs_reg32 txp_regs[] = { 182 VC4_REG32(TXP_DST_PTR), 183 VC4_REG32(TXP_DST_PITCH), 184 VC4_REG32(TXP_DIM), 185 VC4_REG32(TXP_DST_CTRL), 186 VC4_REG32(TXP_PROGRESS), 187 }; 188 189 static int vc4_txp_connector_get_modes(struct drm_connector *connector) 190 { 191 struct drm_device *dev = connector->dev; 192 193 return drm_add_modes_noedid(connector, dev->mode_config.max_width, 194 dev->mode_config.max_height); 195 } 196 197 static enum drm_mode_status 198 vc4_txp_connector_mode_valid(struct drm_connector *connector, 199 const struct drm_display_mode *mode) 200 { 201 struct drm_device *dev = connector->dev; 202 struct drm_mode_config *mode_config = &dev->mode_config; 203 int w = mode->hdisplay, h = mode->vdisplay; 204 205 if (w < mode_config->min_width || w > mode_config->max_width) 206 return MODE_BAD_HVALUE; 207 208 if (h < mode_config->min_height || h > mode_config->max_height) 209 return MODE_BAD_VVALUE; 210 211 return MODE_OK; 212 } 213 214 static const u32 drm_fmts[] = { 215 DRM_FORMAT_RGB888, 216 DRM_FORMAT_BGR888, 217 DRM_FORMAT_XRGB8888, 218 DRM_FORMAT_XBGR8888, 219 DRM_FORMAT_ARGB8888, 220 DRM_FORMAT_ABGR8888, 221 DRM_FORMAT_RGBX8888, 222 DRM_FORMAT_BGRX8888, 223 DRM_FORMAT_RGBA8888, 224 DRM_FORMAT_BGRA8888, 225 }; 226 227 static const u32 txp_fmts[] = { 228 TXP_FORMAT_RGB888, 229 TXP_FORMAT_BGR888, 230 TXP_FORMAT_ARGB8888, 231 TXP_FORMAT_ABGR8888, 232 TXP_FORMAT_ARGB8888, 233 TXP_FORMAT_ABGR8888, 234 TXP_FORMAT_RGBA8888, 235 TXP_FORMAT_BGRA8888, 236 TXP_FORMAT_RGBA8888, 237 TXP_FORMAT_BGRA8888, 238 }; 239 240 static void vc4_txp_armed(struct drm_crtc_state *state) 241 { 242 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 243 244 vc4_state->txp_armed = true; 245 } 246 247 static int vc4_txp_connector_atomic_check(struct drm_connector *conn, 248 struct drm_atomic_state *state) 249 { 250 struct drm_connector_state *conn_state; 251 struct drm_crtc_state *crtc_state; 252 struct drm_framebuffer *fb; 253 int i; 254 255 conn_state = drm_atomic_get_new_connector_state(state, conn); 256 if (!conn_state->writeback_job) 257 return 0; 258 259 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 260 261 fb = conn_state->writeback_job->fb; 262 if (fb->width != crtc_state->mode.hdisplay || 263 fb->height != crtc_state->mode.vdisplay) { 264 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", 265 fb->width, fb->height); 266 return -EINVAL; 267 } 268 269 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 270 if (fb->format->format == drm_fmts[i]) 271 break; 272 } 273 274 if (i == ARRAY_SIZE(drm_fmts)) 275 return -EINVAL; 276 277 /* Pitch must be aligned on 16 bytes. */ 278 if (fb->pitches[0] & GENMASK(3, 0)) 279 return -EINVAL; 280 281 vc4_txp_armed(crtc_state); 282 283 return 0; 284 } 285 286 static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, 287 struct drm_atomic_state *state) 288 { 289 struct drm_device *drm = conn->dev; 290 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, 291 conn); 292 struct vc4_txp *txp = connector_to_vc4_txp(conn); 293 const struct vc4_txp_data *txp_data = txp->data; 294 struct drm_gem_dma_object *gem; 295 struct drm_display_mode *mode; 296 struct drm_framebuffer *fb; 297 unsigned int hdisplay; 298 unsigned int vdisplay; 299 dma_addr_t addr; 300 u32 ctrl; 301 int idx; 302 int i; 303 304 if (WARN_ON(!conn_state->writeback_job)) 305 return; 306 307 mode = &conn_state->crtc->state->adjusted_mode; 308 fb = conn_state->writeback_job->fb; 309 310 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 311 if (fb->format->format == drm_fmts[i]) 312 break; 313 } 314 315 if (WARN_ON(i == ARRAY_SIZE(drm_fmts))) 316 return; 317 318 ctrl = TXP_GO | TXP_EI | 319 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); 320 321 if (txp_data->has_byte_enable) 322 ctrl |= VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE); 323 324 if (fb->format->has_alpha) 325 ctrl |= TXP_ALPHA_ENABLE; 326 else 327 /* 328 * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the 329 * hardware will force the output padding to be 0xff. 330 */ 331 ctrl |= TXP_ALPHA_INVERT; 332 333 if (!drm_dev_enter(drm, &idx)) 334 return; 335 336 gem = drm_fb_dma_get_gem_obj(fb, 0); 337 addr = gem->dma_addr + fb->offsets[0]; 338 339 TXP_WRITE(TXP_DST_PTR, lower_32_bits(addr)); 340 341 if (txp_data->supports_40bit_addresses) 342 TXP_WRITE(txp_data->high_addr_ptr_reg, upper_32_bits(addr) & 0xff); 343 344 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]); 345 346 hdisplay = mode->hdisplay ?: 1; 347 vdisplay = mode->vdisplay ?: 1; 348 if (txp_data->size_minus_one) { 349 hdisplay -= 1; 350 vdisplay -= 1; 351 } 352 353 TXP_WRITE(TXP_DIM, 354 VC4_SET_FIELD(hdisplay, TXP_WIDTH) | 355 VC4_SET_FIELD(vdisplay, TXP_HEIGHT)); 356 357 TXP_WRITE(TXP_DST_CTRL, ctrl); 358 359 drm_writeback_queue_job(&txp->connector, conn_state); 360 361 drm_dev_exit(idx); 362 } 363 364 static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = { 365 .get_modes = vc4_txp_connector_get_modes, 366 .mode_valid = vc4_txp_connector_mode_valid, 367 .atomic_check = vc4_txp_connector_atomic_check, 368 .atomic_commit = vc4_txp_connector_atomic_commit, 369 }; 370 371 static enum drm_connector_status 372 vc4_txp_connector_detect(struct drm_connector *connector, bool force) 373 { 374 return connector_status_connected; 375 } 376 377 static const struct drm_connector_funcs vc4_txp_connector_funcs = { 378 .detect = vc4_txp_connector_detect, 379 .fill_modes = drm_helper_probe_single_connector_modes, 380 .destroy = drm_connector_cleanup, 381 .reset = drm_atomic_helper_connector_reset, 382 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 383 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 384 }; 385 386 static void vc4_txp_encoder_disable(struct drm_encoder *encoder) 387 { 388 struct drm_device *drm = encoder->dev; 389 struct vc4_dev *vc4 = to_vc4_dev(drm); 390 struct vc4_txp *txp = encoder_to_vc4_txp(encoder); 391 int idx; 392 393 if (!drm_dev_enter(drm, &idx)) 394 return; 395 396 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) { 397 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 398 399 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT); 400 401 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY && 402 time_before(jiffies, timeout)) 403 ; 404 405 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY); 406 } 407 408 if (vc4->gen < VC4_GEN_6_C) 409 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN); 410 411 drm_dev_exit(idx); 412 } 413 414 static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = { 415 .disable = vc4_txp_encoder_disable, 416 }; 417 418 static int vc4_txp_enable_vblank(struct drm_crtc *crtc) 419 { 420 return 0; 421 } 422 423 static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {} 424 425 static const struct drm_crtc_funcs vc4_txp_crtc_funcs = { 426 .set_config = drm_atomic_helper_set_config, 427 .page_flip = vc4_page_flip, 428 .reset = vc4_crtc_reset, 429 .atomic_duplicate_state = vc4_crtc_duplicate_state, 430 .atomic_destroy_state = vc4_crtc_destroy_state, 431 .enable_vblank = vc4_txp_enable_vblank, 432 .disable_vblank = vc4_txp_disable_vblank, 433 .late_register = vc4_crtc_late_register, 434 }; 435 436 static int vc4_txp_atomic_check(struct drm_crtc *crtc, 437 struct drm_atomic_state *state) 438 { 439 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 440 crtc); 441 int ret; 442 443 ret = vc4_hvs_atomic_check(crtc, state); 444 if (ret) 445 return ret; 446 447 crtc_state->no_vblank = true; 448 449 return 0; 450 } 451 452 static void vc4_txp_atomic_enable(struct drm_crtc *crtc, 453 struct drm_atomic_state *state) 454 { 455 drm_crtc_vblank_on(crtc); 456 vc4_hvs_atomic_enable(crtc, state); 457 } 458 459 static void vc4_txp_atomic_disable(struct drm_crtc *crtc, 460 struct drm_atomic_state *state) 461 { 462 struct drm_device *dev = crtc->dev; 463 464 /* Disable vblank irq handling before crtc is disabled. */ 465 drm_crtc_vblank_off(crtc); 466 467 vc4_hvs_atomic_disable(crtc, state); 468 469 /* 470 * Make sure we issue a vblank event after disabling the CRTC if 471 * someone was waiting it. 472 */ 473 if (crtc->state->event) { 474 unsigned long flags; 475 476 spin_lock_irqsave(&dev->event_lock, flags); 477 drm_crtc_send_vblank_event(crtc, crtc->state->event); 478 crtc->state->event = NULL; 479 spin_unlock_irqrestore(&dev->event_lock, flags); 480 } 481 } 482 483 static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = { 484 .atomic_check = vc4_txp_atomic_check, 485 .atomic_begin = vc4_hvs_atomic_begin, 486 .atomic_flush = vc4_hvs_atomic_flush, 487 .atomic_enable = vc4_txp_atomic_enable, 488 .atomic_disable = vc4_txp_atomic_disable, 489 }; 490 491 static irqreturn_t vc4_txp_interrupt(int irq, void *data) 492 { 493 struct vc4_txp *txp = data; 494 struct vc4_crtc *vc4_crtc = &txp->base; 495 496 /* 497 * We don't need to protect the register access using 498 * drm_dev_enter() there because the interrupt handler lifetime 499 * is tied to the device itself, and not to the DRM device. 500 * 501 * So when the device will be gone, one of the first thing we 502 * will be doing will be to unregister the interrupt handler, 503 * and then unregister the DRM device. drm_dev_enter() would 504 * thus always succeed if we are here. 505 */ 506 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI); 507 vc4_crtc_handle_vblank(vc4_crtc); 508 drm_writeback_signal_completion(&txp->connector, 0); 509 510 return IRQ_HANDLED; 511 } 512 513 static const struct vc4_txp_data bcm2712_mop_data = { 514 .base = { 515 .name = "mop", 516 .debugfs_name = "mop_regs", 517 .hvs_available_channels = BIT(2), 518 .hvs_output = 2, 519 }, 520 .encoder_type = VC4_ENCODER_TYPE_TXP0, 521 .high_addr_ptr_reg = TXP_DST_PTR_HIGH_MOP, 522 .has_byte_enable = true, 523 .size_minus_one = true, 524 .supports_40bit_addresses = true, 525 }; 526 527 static const struct vc4_txp_data bcm2712_moplet_data = { 528 .base = { 529 .name = "moplet", 530 .debugfs_name = "moplet_regs", 531 .hvs_available_channels = BIT(1), 532 .hvs_output = 4, 533 }, 534 .encoder_type = VC4_ENCODER_TYPE_TXP1, 535 .high_addr_ptr_reg = TXP_DST_PTR_HIGH_MOPLET, 536 .size_minus_one = true, 537 .supports_40bit_addresses = true, 538 }; 539 540 const struct vc4_txp_data bcm2835_txp_data = { 541 .base = { 542 .name = "txp", 543 .debugfs_name = "txp_regs", 544 .hvs_available_channels = BIT(2), 545 .hvs_output = 2, 546 }, 547 .encoder_type = VC4_ENCODER_TYPE_TXP0, 548 .has_byte_enable = true, 549 }; 550 551 static int vc4_txp_bind(struct device *dev, struct device *master, void *data) 552 { 553 struct platform_device *pdev = to_platform_device(dev); 554 struct drm_device *drm = dev_get_drvdata(master); 555 const struct vc4_txp_data *txp_data; 556 struct vc4_encoder *vc4_encoder; 557 struct drm_encoder *encoder; 558 struct vc4_crtc *vc4_crtc; 559 struct vc4_txp *txp; 560 int ret, irq; 561 562 irq = platform_get_irq(pdev, 0); 563 if (irq < 0) 564 return irq; 565 566 txp = drmm_kzalloc(drm, sizeof(*txp), GFP_KERNEL); 567 if (!txp) 568 return -ENOMEM; 569 570 txp_data = of_device_get_match_data(dev); 571 if (!txp_data) 572 return -ENODEV; 573 574 txp->data = txp_data; 575 txp->pdev = pdev; 576 txp->regs = vc4_ioremap_regs(pdev, 0); 577 if (IS_ERR(txp->regs)) 578 return PTR_ERR(txp->regs); 579 580 vc4_crtc = &txp->base; 581 vc4_crtc->regset.base = txp->regs; 582 vc4_crtc->regset.regs = txp_regs; 583 vc4_crtc->regset.nregs = ARRAY_SIZE(txp_regs); 584 585 ret = vc4_crtc_init(drm, pdev, vc4_crtc, &txp_data->base, 586 &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs, true); 587 if (ret) 588 return ret; 589 590 vc4_encoder = &txp->encoder; 591 txp->encoder.type = txp_data->encoder_type; 592 593 encoder = &vc4_encoder->base; 594 encoder->possible_crtcs = drm_crtc_mask(&vc4_crtc->base); 595 596 drm_encoder_helper_add(encoder, &vc4_txp_encoder_helper_funcs); 597 598 ret = drmm_encoder_init(drm, encoder, NULL, DRM_MODE_ENCODER_VIRTUAL, NULL); 599 if (ret) 600 return ret; 601 602 drm_connector_helper_add(&txp->connector.base, 603 &vc4_txp_connector_helper_funcs); 604 ret = drm_writeback_connector_init_with_encoder(drm, &txp->connector, 605 encoder, 606 &vc4_txp_connector_funcs, 607 drm_fmts, ARRAY_SIZE(drm_fmts)); 608 if (ret) 609 return ret; 610 611 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0, 612 dev_name(dev), txp); 613 if (ret) 614 return ret; 615 616 dev_set_drvdata(dev, txp); 617 618 return 0; 619 } 620 621 static void vc4_txp_unbind(struct device *dev, struct device *master, 622 void *data) 623 { 624 struct vc4_txp *txp = dev_get_drvdata(dev); 625 626 drm_connector_cleanup(&txp->connector.base); 627 } 628 629 static const struct component_ops vc4_txp_ops = { 630 .bind = vc4_txp_bind, 631 .unbind = vc4_txp_unbind, 632 }; 633 634 static int vc4_txp_probe(struct platform_device *pdev) 635 { 636 return component_add(&pdev->dev, &vc4_txp_ops); 637 } 638 639 static void vc4_txp_remove(struct platform_device *pdev) 640 { 641 component_del(&pdev->dev, &vc4_txp_ops); 642 } 643 644 static const struct of_device_id vc4_txp_dt_match[] = { 645 { .compatible = "brcm,bcm2712-mop", .data = &bcm2712_mop_data }, 646 { .compatible = "brcm,bcm2712-moplet", .data = &bcm2712_moplet_data }, 647 { .compatible = "brcm,bcm2835-txp", .data = &bcm2835_txp_data }, 648 { /* sentinel */ }, 649 }; 650 651 struct platform_driver vc4_txp_driver = { 652 .probe = vc4_txp_probe, 653 .remove = vc4_txp_remove, 654 .driver = { 655 .name = "vc4_txp", 656 .of_match_table = vc4_txp_dt_match, 657 }, 658 }; 659