xref: /linux/drivers/gpu/drm/amd/display/dc/inc/core_types.h (revision 5c06c1df3582102e837dc7d6e8a462323277e57b)
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef _CORE_TYPES_H_
27 #define _CORE_TYPES_H_
28 
29 #include "dc.h"
30 #include "dce_calcs.h"
31 #include "dcn_calcs.h"
32 #include "ddc_service_types.h"
33 #include "dc_bios_types.h"
34 #include "mem_input.h"
35 #include "hubp.h"
36 #include "mpc.h"
37 #include "dwb.h"
38 #include "mcif_wb.h"
39 #include "panel_cntl.h"
40 #include "dmub/inc/dmub_cmd.h"
41 #include "pg_cntl.h"
42 #include "sspl/dc_spl.h"
43 
44 #define MAX_CLOCK_SOURCES 7
45 #define MAX_SVP_PHANTOM_STREAMS 2
46 #define MAX_SVP_PHANTOM_PLANES 2
47 
48 #include "grph_object_id.h"
49 #include "link_encoder.h"
50 #include "stream_encoder.h"
51 #include "clock_source.h"
52 #include "audio.h"
53 #include "dm_pp_smu.h"
54 #include "dm_cp_psp.h"
55 #include "link_hwss.h"
56 
57 /********** DAL Core*********************/
58 #include "transform.h"
59 #include "dpp.h"
60 
61 #include "dml2/dml21/inc/dml_top_dchub_registers.h"
62 #include "dml2/dml21/inc/dml_top_types.h"
63 
64 struct resource_pool;
65 struct dc_state;
66 struct resource_context;
67 struct clk_bw_params;
68 
69 struct resource_funcs {
70 	enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index);
71 	void (*destroy)(struct resource_pool **pool);
72 	void (*link_init)(struct dc_link *link);
73 	struct panel_cntl*(*panel_cntl_create)(
74 		const struct panel_cntl_init_data *panel_cntl_init_data);
75 	struct link_encoder *(*link_enc_create)(
76 			struct dc_context *ctx,
77 			const struct encoder_init_data *init);
78 	/* Create a minimal link encoder object with no dc_link object
79 	 * associated with it. */
80 	struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);
81 
82 	bool (*validate_bandwidth)(
83 					struct dc *dc,
84 					struct dc_state *context,
85 					bool fast_validate);
86 	void (*calculate_wm_and_dlg)(
87 				struct dc *dc, struct dc_state *context,
88 				display_e2e_pipe_params_st *pipes,
89 				int pipe_cnt,
90 				int vlevel);
91 	void (*update_soc_for_wm_a)(
92 				struct dc *dc, struct dc_state *context);
93 
94 	unsigned int (*calculate_mall_ways_from_bytes)(
95 				const struct dc *dc,
96 				unsigned int total_size_in_mall_bytes);
97 	void (*prepare_mcache_programming)(
98 					struct dc *dc,
99 					struct dc_state *context);
100 	/**
101 	 * @populate_dml_pipes - Populate pipe data struct
102 	 *
103 	 * Returns:
104 	 * Total of pipes available in the specific ASIC.
105 	 */
106 	int (*populate_dml_pipes)(
107 		struct dc *dc,
108 		struct dc_state *context,
109 		display_e2e_pipe_params_st *pipes,
110 		bool fast_validate);
111 
112 	/*
113 	 * Algorithm for assigning available link encoders to links.
114 	 *
115 	 * Update link_enc_assignments table and link_enc_avail list accordingly in
116 	 * struct resource_context.
117 	 */
118 	void (*link_encs_assign)(
119 			struct dc *dc,
120 			struct dc_state *state,
121 			struct dc_stream_state *streams[],
122 			uint8_t stream_count);
123 	/*
124 	 * Unassign a link encoder from a stream.
125 	 *
126 	 * Update link_enc_assignments table and link_enc_avail list accordingly in
127 	 * struct resource_context.
128 	 */
129 	void (*link_enc_unassign)(
130 			struct dc_state *state,
131 			struct dc_stream_state *stream);
132 
133 	enum dc_status (*validate_global)(
134 		struct dc *dc,
135 		struct dc_state *context);
136 
137 	struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)(
138 			const struct dc_state *cur_ctx,
139 			struct dc_state *new_ctx,
140 			const struct resource_pool *pool,
141 			const struct pipe_ctx *opp_head_pipe);
142 
143 	struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(
144 			const struct dc_state *cur_ctx,
145 			struct dc_state *new_ctx,
146 			const struct resource_pool *pool,
147 			const struct pipe_ctx *otg_master);
148 
149 	void (*release_pipe)(struct dc_state *context,
150 			struct pipe_ctx *pipe,
151 			const struct resource_pool *pool);
152 
153 	enum dc_status (*validate_plane)(
154 			const struct dc_plane_state *plane_state,
155 			struct dc_caps *caps);
156 
157 	enum dc_status (*add_stream_to_ctx)(
158 			struct dc *dc,
159 			struct dc_state *new_ctx,
160 			struct dc_stream_state *dc_stream);
161 
162 	enum dc_status (*remove_stream_from_ctx)(
163 				struct dc *dc,
164 				struct dc_state *new_ctx,
165 				struct dc_stream_state *stream);
166 
167 	enum dc_status (*patch_unknown_plane_state)(
168 			struct dc_plane_state *plane_state);
169 
170 	struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
171 			struct resource_context *res_ctx,
172 			const struct resource_pool *pool,
173 			struct dc_stream_state *stream);
174 
175 	void (*populate_dml_writeback_from_context)(
176 			struct dc *dc,
177 			struct resource_context *res_ctx,
178 			display_e2e_pipe_params_st *pipes);
179 
180 	void (*set_mcif_arb_params)(
181 			struct dc *dc,
182 			struct dc_state *context,
183 			display_e2e_pipe_params_st *pipes,
184 			int pipe_cnt);
185 
186 	void (*update_bw_bounding_box)(
187 			struct dc *dc,
188 			struct clk_bw_params *bw_params);
189 	bool (*acquire_post_bldn_3dlut)(
190 			struct resource_context *res_ctx,
191 			const struct resource_pool *pool,
192 			int mpcc_id,
193 			struct dc_3dlut **lut,
194 			struct dc_transfer_func **shaper);
195 
196 	bool (*release_post_bldn_3dlut)(
197 			struct resource_context *res_ctx,
198 			const struct resource_pool *pool,
199 			struct dc_3dlut **lut,
200 			struct dc_transfer_func **shaper);
201 
202 	enum dc_status (*add_dsc_to_stream_resource)(
203 			struct dc *dc, struct dc_state *state,
204 			struct dc_stream_state *stream);
205 
206 	void (*add_phantom_pipes)(
207             struct dc *dc,
208             struct dc_state *context,
209             display_e2e_pipe_params_st *pipes,
210 			unsigned int pipe_cnt,
211             unsigned int index);
212 
213 	void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);
214 	void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);
215 	/*
216 	 * Get indicator of power from a context that went through full validation
217 	 */
218 	int (*get_power_profile)(const struct dc_state *context);
219 	unsigned int (*get_det_buffer_size)(const struct dc_state *context);
220 	unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx);
221 };
222 
223 struct audio_support{
224 	bool dp_audio;
225 	bool hdmi_audio_on_dongle;
226 	bool hdmi_audio_native;
227 };
228 
229 #define NO_UNDERLAY_PIPE -1
230 
231 struct resource_pool {
232 	struct mem_input *mis[MAX_PIPES];
233 	struct hubp *hubps[MAX_PIPES];
234 	struct input_pixel_processor *ipps[MAX_PIPES];
235 	struct transform *transforms[MAX_PIPES];
236 	struct dpp *dpps[MAX_PIPES];
237 	struct output_pixel_processor *opps[MAX_PIPES];
238 	struct timing_generator *timing_generators[MAX_PIPES];
239 	struct stream_encoder *stream_enc[MAX_PIPES * 2];
240 	struct hubbub *hubbub;
241 	struct mpc *mpc;
242 	struct pp_smu_funcs *pp_smu;
243 	struct dce_aux *engines[MAX_PIPES];
244 	struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
245 	struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
246 	bool i2c_hw_buffer_in_use;
247 
248 	struct dwbc *dwbc[MAX_DWB_PIPES];
249 	struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
250 	struct {
251 		unsigned int gsl_0:1;
252 		unsigned int gsl_1:1;
253 		unsigned int gsl_2:1;
254 	} gsl_groups;
255 
256 	struct display_stream_compressor *dscs[MAX_PIPES];
257 
258 	unsigned int pipe_count;
259 	unsigned int underlay_pipe_index;
260 	unsigned int stream_enc_count;
261 
262 	/* An array for accessing the link encoder objects that have been created.
263 	 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA
264 	 */
265 	struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS];
266 	/* Number of DIG link encoder objects created - i.e. number of valid
267 	 * entries in link_encoders array.
268 	 */
269 	unsigned int dig_link_enc_count;
270 	/* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/
271 	unsigned int usb4_dpia_count;
272 
273 	unsigned int hpo_dp_stream_enc_count;
274 	struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
275 	unsigned int hpo_dp_link_enc_count;
276 	struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
277 	struct dc_3dlut *mpc_lut[MAX_PIPES];
278 	struct dc_transfer_func *mpc_shaper[MAX_PIPES];
279 
280 	struct {
281 		unsigned int xtalin_clock_inKhz;
282 		unsigned int dccg_ref_clock_inKhz;
283 		unsigned int dchub_ref_clock_inKhz;
284 	} ref_clocks;
285 	unsigned int timing_generator_count;
286 	unsigned int mpcc_count;
287 
288 	unsigned int writeback_pipe_count;
289 	/*
290 	 * reserved clock source for DP
291 	 */
292 	struct clock_source *dp_clock_source;
293 
294 	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
295 	unsigned int clk_src_count;
296 
297 	struct audio *audios[MAX_AUDIOS];
298 	unsigned int audio_count;
299 	struct audio_support audio_support;
300 
301 	struct dccg *dccg;
302 	struct pg_cntl *pg_cntl;
303 	struct irq_service *irqs;
304 
305 	struct abm *abm;
306 	struct dmcu *dmcu;
307 	struct dmub_psr *psr;
308 	struct dmub_replay *replay;
309 
310 	struct abm *multiple_abms[MAX_PIPES];
311 
312 	const struct resource_funcs *funcs;
313 	const struct resource_caps *res_cap;
314 
315 	struct ddc_service *oem_device;
316 };
317 
318 struct dcn_fe_bandwidth {
319 	int dppclk_khz;
320 
321 };
322 
323 /* Parameters needed to call set_disp_pattern_generator */
324 struct test_pattern_params {
325 	enum controller_dp_test_pattern test_pattern;
326 	enum controller_dp_color_space color_space;
327 	enum dc_color_depth color_depth;
328 	int width;
329 	int height;
330 	int offset;
331 };
332 
333 struct stream_resource {
334 	struct output_pixel_processor *opp;
335 	struct display_stream_compressor *dsc;
336 	struct timing_generator *tg;
337 	struct stream_encoder *stream_enc;
338 	struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
339 	struct audio *audio;
340 
341 	struct pixel_clk_params pix_clk_params;
342 	struct encoder_info_frame encoder_info_frame;
343 
344 	struct abm *abm;
345 	/* There are only (num_pipes+1)/2 groups. 0 means unassigned,
346 	 * otherwise it's using group number 'gsl_group-1'
347 	 */
348 	uint8_t gsl_group;
349 
350 	struct test_pattern_params test_pattern_params;
351 };
352 
353 struct plane_resource {
354 	/* scl_data is scratch space required to program a plane */
355 	struct scaler_data scl_data;
356 	/* Below pointers to hw objects are required to enable the plane */
357 	/* spl_in and spl_out are the input and output structures for SPL
358 	 * which are required when using Scaler Programming Library
359 	 * these are scratch spaces needed when programming a plane
360 	 */
361 	struct spl_in spl_in;
362 	struct spl_out spl_out;
363 	/* Below pointers to hw objects are required to enable the plane */
364 	struct hubp *hubp;
365 	struct mem_input *mi;
366 	struct input_pixel_processor *ipp;
367 	struct transform *xfm;
368 	struct dpp *dpp;
369 	uint8_t mpcc_inst;
370 
371 	struct dcn_fe_bandwidth bw;
372 };
373 
374 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
375 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
376 
377 /* all mappable hardware resources used to enable a link */
378 struct link_resource {
379 	struct link_encoder *dio_link_enc;
380 	struct hpo_dp_link_encoder *hpo_dp_link_enc;
381 };
382 
383 struct link_config {
384 	struct dc_link_settings dp_link_settings;
385 };
386 union pipe_update_flags {
387 	struct {
388 		uint32_t enable : 1;
389 		uint32_t disable : 1;
390 		uint32_t odm : 1;
391 		uint32_t global_sync : 1;
392 		uint32_t opp_changed : 1;
393 		uint32_t tg_changed : 1;
394 		uint32_t mpcc : 1;
395 		uint32_t dppclk : 1;
396 		uint32_t hubp_interdependent : 1;
397 		uint32_t hubp_rq_dlg_ttu : 1;
398 		uint32_t gamut_remap : 1;
399 		uint32_t scaler : 1;
400 		uint32_t viewport : 1;
401 		uint32_t plane_changed : 1;
402 		uint32_t det_size : 1;
403 		uint32_t unbounded_req : 1;
404 		uint32_t test_pattern_changed : 1;
405 	} bits;
406 	uint32_t raw;
407 };
408 
409 struct pixel_rate_divider {
410 	uint32_t div_factor1;
411 	uint32_t div_factor2;
412 };
413 
414 enum p_state_switch_method {
415 	P_STATE_UNKNOWN						= 0,
416 	P_STATE_V_BLANK						= 1,
417 	P_STATE_FPO,
418 	P_STATE_V_ACTIVE,
419 	P_STATE_SUB_VP,
420 	P_STATE_DRR_SUB_VP,
421 	P_STATE_V_BLANK_SUB_VP
422 };
423 
424 struct pipe_ctx {
425 	struct dc_plane_state *plane_state;
426 	struct dc_stream_state *stream;
427 
428 	struct plane_resource plane_res;
429 
430 	/**
431 	 * @stream_res: Reference to DCN resource components such OPP and DSC.
432 	 */
433 	struct stream_resource stream_res;
434 	struct link_resource link_res;
435 
436 	struct clock_source *clock_source;
437 
438 	struct pll_settings pll_settings;
439 
440 	/**
441 	 * @link_config:
442 	 *
443 	 * link config records software decision for what link config should be
444 	 * enabled given current link capability and stream during hw resource
445 	 * mapping. This is to decouple the dependency on link capability during
446 	 * dc commit or update.
447 	 */
448 	struct link_config link_config;
449 
450 	uint8_t pipe_idx;
451 	uint8_t pipe_idx_syncd;
452 
453 	struct pipe_ctx *top_pipe;
454 	struct pipe_ctx *bottom_pipe;
455 	struct pipe_ctx *next_odm_pipe;
456 	struct pipe_ctx *prev_odm_pipe;
457 
458 	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
459 	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
460 	struct _vcs_dpi_display_rq_regs_st rq_regs;
461 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
462 	struct _vcs_dpi_display_rq_params_st dml_rq_param;
463 	struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param;
464 	struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
465 	int det_buffer_size_kb;
466 	bool unbounded_req;
467 	unsigned int surface_size_in_mall_bytes;
468 	struct dml2_dchub_per_pipe_register_set hubp_regs;
469 	struct dml2_hubp_pipe_mcache_regs mcache_regs;
470 	union dml2_global_sync_programming global_sync;
471 
472 	struct dwbc *dwbc;
473 	struct mcif_wb *mcif_wb;
474 	union pipe_update_flags update_flags;
475 	enum p_state_switch_method p_state_type;
476 	struct tg_color visual_confirm_color;
477 	bool has_vactive_margin;
478 	/* subvp_index: only valid if the pipe is a SUBVP_MAIN*/
479 	uint8_t subvp_index;
480 	struct pixel_rate_divider pixel_rate_divider;
481 	/* pixels borrowed from hblank to hactive */
482 	uint8_t hblank_borrow;
483 };
484 
485 /* Data used for dynamic link encoder assignment.
486  * Tracks current and future assignments; available link encoders;
487  * and mode of operation (whether to use current or future assignments).
488  */
489 struct link_enc_cfg_context {
490 	enum link_enc_cfg_mode mode;
491 	struct link_enc_assignment link_enc_assignments[MAX_PIPES];
492 	enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
493 	struct link_enc_assignment transient_assignments[MAX_PIPES];
494 };
495 
496 struct resource_context {
497 	struct pipe_ctx pipe_ctx[MAX_PIPES];
498 	bool is_stream_enc_acquired[MAX_PIPES * 2];
499 	bool is_audio_acquired[MAX_PIPES];
500 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
501 	uint8_t dp_clock_source_ref_count;
502 	bool is_dsc_acquired[MAX_PIPES];
503 	struct link_enc_cfg_context link_enc_cfg_ctx;
504 	unsigned int dio_link_enc_to_link_idx[MAX_DIG_LINK_ENCODERS];
505 	int dio_link_enc_ref_cnts[MAX_DIG_LINK_ENCODERS];
506 	bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
507 	unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
508 	int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
509 	bool is_mpc_3dlut_acquired[MAX_PIPES];
510 	/* solely used for build scalar data in dml2 */
511 	struct pipe_ctx temp_pipe;
512 };
513 
514 struct dce_bw_output {
515 	bool cpuc_state_change_enable;
516 	bool cpup_state_change_enable;
517 	bool stutter_mode_enable;
518 	bool nbp_state_change_enable;
519 	bool all_displays_in_sync;
520 	struct dce_watermarks urgent_wm_ns[MAX_PIPES];
521 	struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
522 	struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
523 	struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
524 	int sclk_khz;
525 	int sclk_deep_sleep_khz;
526 	int yclk_khz;
527 	int dispclk_khz;
528 	int blackout_recovery_time_us;
529 };
530 
531 struct dcn_bw_writeback {
532 	struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
533 };
534 
535 struct dcn_bw_output {
536 	struct dc_clocks clk;
537 	union dcn_watermark_set watermarks;
538 	struct dcn_bw_writeback bw_writeback;
539 	int compbuf_size_kb;
540 	unsigned int mall_ss_size_bytes;
541 	unsigned int mall_ss_psr_active_size_bytes;
542 	unsigned int mall_subvp_size_bytes;
543 	unsigned int legacy_svp_drr_stream_index;
544 	bool legacy_svp_drr_stream_index_valid;
545 	struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];
546 	struct dmub_cmd_fams2_global_config fams2_global_config;
547 	union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES];
548 	union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES];
549 	struct dml2_display_arb_regs arb_regs;
550 };
551 
552 union bw_output {
553 	struct dcn_bw_output dcn;
554 	struct dce_bw_output dce;
555 };
556 
557 struct bw_context {
558 	union bw_output bw;
559 	struct display_mode_lib dml;
560 	struct dml2_context *dml2;
561 	struct dml2_context *dml2_dc_power_source;
562 };
563 
564 struct dc_dmub_cmd {
565 	union dmub_rb_cmd dmub_cmd;
566 	enum dm_dmub_wait_type wait_type;
567 };
568 
569 /**
570  * struct dc_state - The full description of a state requested by users
571  */
572 struct dc_state {
573 	/**
574 	 * @streams: Stream state properties
575 	 */
576 	struct dc_stream_state *streams[MAX_PIPES];
577 
578 	/**
579 	 * @stream_status: Planes status on a given stream
580 	 */
581 	struct dc_stream_status stream_status[MAX_PIPES];
582 	/**
583 	 * @phantom_streams: Stream state properties for phantoms
584 	 */
585 	struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES];
586 	/**
587 	 * @phantom_planes: Planes state properties for phantoms
588 	 */
589 	struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES];
590 
591 	/**
592 	 * @stream_count: Total of streams in use
593 	 */
594 	uint8_t stream_count;
595 	uint8_t stream_mask;
596 
597 	/**
598 	 * @stream_count: Total phantom streams in use
599 	 */
600 	uint8_t phantom_stream_count;
601 	/**
602 	 * @stream_count: Total phantom planes in use
603 	 */
604 	uint8_t phantom_plane_count;
605 	/**
606 	 * @res_ctx: Persistent state of resources
607 	 */
608 	struct resource_context res_ctx;
609 
610 	/**
611 	 * @pp_display_cfg: PowerPlay clocks and settings
612 	 * Note: this is a big struct, do *not* put on stack!
613 	 */
614 	struct dm_pp_display_configuration pp_display_cfg;
615 
616 	/**
617 	 * @dcn_bw_vars: non-stack memory to support bandwidth calculations
618 	 * Note: this is a big struct, do *not* put on stack!
619 	 */
620 	struct dcn_bw_internal_vars dcn_bw_vars;
621 
622 	struct clk_mgr *clk_mgr;
623 
624 	/**
625 	 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
626 	 *
627 	 * Each context must have its own instance of VBA, and in order to
628 	 * initialize and obtain IP and SOC, the base DML instance from DC is
629 	 * initially copied into every context.
630 	 */
631 	struct bw_context bw_ctx;
632 
633 	struct block_sequence block_sequence[100];
634 	unsigned int block_sequence_steps;
635 	struct dc_dmub_cmd dc_dmub_cmd[10];
636 	unsigned int dmub_cmd_count;
637 
638 	/**
639 	 * @refcount: refcount reference
640 	 *
641 	 * Notice that dc_state is used around the code to capture the current
642 	 * context, so we need to pass it everywhere. That's why we want to use
643 	 * kref in this struct.
644 	 */
645 	struct kref refcount;
646 
647 	struct {
648 		unsigned int stutter_period_us;
649 	} perf_params;
650 
651 	enum dc_power_source_type power_source;
652 };
653 
654 struct replay_context {
655 	/* ddc line */
656 	enum channel_id aux_inst;
657 	/* Transmitter id */
658 	enum transmitter digbe_inst;
659 	/* Engine Id is used for Dig Be source select */
660 	enum engine_id digfe_inst;
661 	/* Controller Id used for Dig Fe source select */
662 	enum controller_id controllerId;
663 	unsigned int line_time_in_ns;
664 };
665 
666 enum dc_replay_enable {
667 	DC_REPLAY_DISABLE			= 0,
668 	DC_REPLAY_ENABLE			= 1,
669 };
670 
671 struct dc_bounding_box_max_clk {
672 	int max_dcfclk_mhz;
673 	int max_dispclk_mhz;
674 	int max_dppclk_mhz;
675 	int max_phyclk_mhz;
676 };
677 
678 #endif /* _CORE_TYPES_H_ */
679