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Searched defs:val_p (Results 1 – 19 of 19) sorted by relevance

/titanic_50/usr/src/uts/common/io/1394/targets/dcam1394/
H A Ddcam_param.c437 uint_t *val_p) in dcam1394_param_get()
658 uint_t feature_elm_inq_reg_offs, uint_t subparam, uint_t *val_p) in feature_get()
738 param_cap_power_ctrl_get(dcam_state_t *softc_p, uint_t *val_p) in param_cap_power_ctrl_get()
760 param_cap_vid_mode_get(dcam_state_t *softc_p, uint_t subparam, uint_t *val_p) in param_cap_vid_mode_get()
787 uint_t subparam, uint_t *val_p) in param_cap_frame_rate_get()
814 param_power_get(dcam_state_t *softc_p, uint_t *val_p) in param_power_get()
853 param_vid_mode_get(dcam_state_t *softc_p, uint_t *val_p) in param_vid_mode_get()
906 param_frame_rate_get(dcam_state_t *softc_p, uint_t *val_p) in param_frame_rate_get()
979 param_ring_buff_capacity_get(dcam_state_t *softc_p, uint_t *val_p) in param_ring_buff_capacity_get()
1018 param_ring_buff_num_frames_ready_get(dcam_state_t *softc_p, uint_t *val_p) in param_ring_buff_num_frames_ready_get()
[all …]
/titanic_50/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txc.h67 #define TXC_FZC_REG_READ64(handle, reg, cn, val_p) \ argument
75 #define TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p) \ argument
H A Dnpi_mac.h282 #define XMAC_REG_RD(handle, portn, reg, val_p)\ argument
288 #define BMAC_REG_RD(handle, portn, reg, val_p)\ argument
294 #define PCS_REG_RD(handle, portn, reg, val_p)\ argument
300 #define XPCS_REG_RD(handle, portn, reg, val_p)\ argument
306 #define MIF_REG_RD(handle, reg, val_p)\ argument
321 #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ argument
325 #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ argument
332 #define ESR_REG_RD(handle, reg, val_p)\ argument
H A Dnpi_espc.h38 #define EPC_WAIT_RW_COMP(handle, val_p, comp_bit) {\ argument
H A Dnpi_txdma.h134 #define TX_LOG_REG_READ64(handle, reg, channel, val_p) \ argument
/titanic_50/usr/src/uts/common/io/hxge/
H A Dhxge_common_impl.h172 #define HXGE_MEM_PIO_READ64(hpi_handle, val_p) { \ argument
184 #define HXGE_REG_RD64(handle, offset, val_p) { \ argument
189 #define HXGE_REG_RD32(handle, offset, val_p) { \ argument
203 #define HXGE_MEM_PIO_READ64(hpi_handle, val_p) { \ argument
210 #define HXGE_REG_RD64(handle, offset, val_p) { \ argument
213 #define HXGE_REG_RD32(handle, offset, val_p) { \ argument
H A Dhxge_pfc.h52 #define REG_PIO_READ64(handle, offset, val_p) \ argument
65 #define READ_TCAM_REG_CTL(handle, val_p) \ argument
77 #define READ_TCAM_REG_KEY0(handle, val_p) \ argument
79 #define READ_TCAM_REG_KEY1(handle, val_p) \ argument
81 #define READ_TCAM_REG_MASK0(handle, val_p) \ argument
83 #define READ_TCAM_REG_MASK1(handle, val_p) \ argument
H A Dhpi_txdma.h53 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ argument
/titanic_50/usr/src/uts/common/sys/nxge/
H A Dnxge_common_impl.h314 #define NXGE_REG_RD64(handle, offset, val_p) {\ argument
324 #define NXGE_REG_RD64(handle, offset, val_p) {\ argument
329 #define NXGE_REG_RD64(handle, offset, val_p) {\ argument
H A Dnxge_fflp_hw.h1097 #define REG_PIO_READ64(handle, offset, val_p) \ argument
1104 #define READ_TCAM_REG_CTL(handle, val_p) \ argument
1125 #define READ_TCAM_REG_KEY0(handle, val_p) \ argument
1127 #define READ_TCAM_REG_KEY1(handle, val_p) \ argument
1129 #define READ_TCAM_REG_KEY2(handle, val_p) \ argument
1131 #define READ_TCAM_REG_KEY3(handle, val_p) \ argument
1133 #define READ_TCAM_REG_MASK0(handle, val_p) \ argument
1135 #define READ_TCAM_REG_MASK1(handle, val_p) \ argument
1137 #define READ_TCAM_REG_MASK2(handle, val_p) \ argument
1139 #define READ_TCAM_REG_MASK3(handle, val_p) \ argument
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/
H A Dmm_ndismono.h198 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
H A Dmm_solaris.h198 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
H A Dmm_vbd.h69 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
H A Dmm_user_mode_debug.h212 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
H A Dmm_dos.h254 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
H A Dmm_uefi.h260 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
H A Dmm.h551 #define mm_get_bar_size(/* struct _lm_device_t* */pdev, /* u8_t */bar_num, /* u32_t* */val_p) \ argument
/titanic_50/usr/src/uts/common/os/
H A Dsunddi.c409 ddi_peek8(dev_info_t *dip, int8_t *addr, int8_t *val_p) in ddi_peek8()
416 ddi_peek16(dev_info_t *dip, int16_t *addr, int16_t *val_p) in ddi_peek16()
423 ddi_peek32(dev_info_t *dip, int32_t *addr, int32_t *val_p) in ddi_peek32()
430 ddi_peek64(dev_info_t *dip, int64_t *addr, int64_t *val_p) in ddi_peek64()
447 ddi_peekc(dev_info_t *dip, int8_t *addr, int8_t *val_p) in ddi_peekc()
454 ddi_peeks(dev_info_t *dip, int16_t *addr, int16_t *val_p) in ddi_peeks()
461 ddi_peekl(dev_info_t *dip, int32_t *addr, int32_t *val_p) in ddi_peekl()
468 ddi_peekd(dev_info_t *dip, int64_t *addr, int64_t *val_p) in ddi_peekd()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_devinfo.c422 OUT u32_t * val_p) in lm_get_bar_size_direct()