1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
3
4 /**
5 * DOC: Interrupt management for the V3D engine
6 *
7 * When we take a bin, render, TFU done, or CSD done interrupt, we
8 * need to signal the fence for that job so that the scheduler can
9 * queue up the next one and unblock any waiters.
10 *
11 * When we take the binner out of memory interrupt, we need to
12 * allocate some new memory and pass it to the binner so that the
13 * current job can make progress.
14 */
15
16 #include <linux/platform_device.h>
17 #include <linux/sched/clock.h>
18
19 #include "v3d_drv.h"
20 #include "v3d_regs.h"
21 #include "v3d_trace.h"
22
23 #define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \
24 V3D_INT_FLDONE | \
25 V3D_INT_FRDONE | \
26 V3D_INT_CSDDONE(ver) | \
27 (ver < 71 ? V3D_INT_GMPV : 0)))
28
29 #define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \
30 V3D_HUB_INT_MMU_PTI | \
31 V3D_HUB_INT_MMU_CAP | \
32 V3D_HUB_INT_TFUC | \
33 (ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0)))
34
35 static irqreturn_t
36 v3d_hub_irq(int irq, void *arg);
37
38 static void
v3d_overflow_mem_work(struct work_struct * work)39 v3d_overflow_mem_work(struct work_struct *work)
40 {
41 struct v3d_dev *v3d =
42 container_of(work, struct v3d_dev, overflow_mem_work);
43 struct drm_device *dev = &v3d->drm;
44 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
45 struct drm_gem_object *obj;
46 unsigned long irqflags;
47
48 if (IS_ERR(bo)) {
49 DRM_ERROR("Couldn't allocate binner overflow mem\n");
50 return;
51 }
52 obj = &bo->base.base;
53
54 /* We lost a race, and our work task came in after the bin job
55 * completed and exited. This can happen because the HW
56 * signals OOM before it's fully OOM, so the binner might just
57 * barely complete.
58 *
59 * If we lose the race and our work task comes in after a new
60 * bin job got scheduled, that's fine. We'll just give them
61 * some binner pool anyway.
62 */
63 spin_lock_irqsave(&v3d->job_lock, irqflags);
64 if (!v3d->bin_job) {
65 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
66 goto out;
67 }
68
69 drm_gem_object_get(obj);
70 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
71 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
72
73 v3d_mmu_flush_all(v3d);
74
75 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT);
76 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
77
78 out:
79 drm_gem_object_put(obj);
80 }
81
82 static irqreturn_t
v3d_irq(int irq,void * arg)83 v3d_irq(int irq, void *arg)
84 {
85 struct v3d_dev *v3d = arg;
86 u32 intsts;
87 irqreturn_t status = IRQ_NONE;
88
89 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
90
91 /* Acknowledge the interrupts we're handling here. */
92 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
93
94 if (intsts & V3D_INT_OUTOMEM) {
95 /* Note that the OOM status is edge signaled, so the
96 * interrupt won't happen again until the we actually
97 * add more memory. Also, as of V3D 4.1, FLDONE won't
98 * be reported until any OOM state has been cleared.
99 */
100 schedule_work(&v3d->overflow_mem_work);
101 status = IRQ_HANDLED;
102 }
103
104 if (intsts & V3D_INT_FLDONE) {
105 struct v3d_fence *fence =
106 to_v3d_fence(v3d->bin_job->base.irq_fence);
107
108 v3d_job_update_stats(&v3d->bin_job->base, V3D_BIN);
109 trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
110
111 v3d->bin_job = NULL;
112 dma_fence_signal(&fence->base);
113
114 status = IRQ_HANDLED;
115 }
116
117 if (intsts & V3D_INT_FRDONE) {
118 struct v3d_fence *fence =
119 to_v3d_fence(v3d->render_job->base.irq_fence);
120
121 v3d_job_update_stats(&v3d->render_job->base, V3D_RENDER);
122 trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
123
124 v3d->render_job = NULL;
125 dma_fence_signal(&fence->base);
126
127 status = IRQ_HANDLED;
128 }
129
130 if (intsts & V3D_INT_CSDDONE(v3d->ver)) {
131 struct v3d_fence *fence =
132 to_v3d_fence(v3d->csd_job->base.irq_fence);
133
134 v3d_job_update_stats(&v3d->csd_job->base, V3D_CSD);
135 trace_v3d_csd_irq(&v3d->drm, fence->seqno);
136
137 v3d->csd_job = NULL;
138 dma_fence_signal(&fence->base);
139
140 status = IRQ_HANDLED;
141 }
142
143 /* We shouldn't be triggering these if we have GMP in
144 * always-allowed mode.
145 */
146 if (v3d->ver < V3D_GEN_71 && (intsts & V3D_INT_GMPV))
147 dev_err(v3d->drm.dev, "GMP violation\n");
148
149 /* V3D 4.2 wires the hub and core IRQs together, so if we &
150 * didn't see the common one then check hub for MMU IRQs.
151 */
152 if (v3d->single_irq_line && status == IRQ_NONE)
153 return v3d_hub_irq(irq, arg);
154
155 return status;
156 }
157
158 static irqreturn_t
v3d_hub_irq(int irq,void * arg)159 v3d_hub_irq(int irq, void *arg)
160 {
161 struct v3d_dev *v3d = arg;
162 u32 intsts;
163 irqreturn_t status = IRQ_NONE;
164
165 intsts = V3D_READ(V3D_HUB_INT_STS);
166
167 /* Acknowledge the interrupts we're handling here. */
168 V3D_WRITE(V3D_HUB_INT_CLR, intsts);
169
170 if (intsts & V3D_HUB_INT_TFUC) {
171 struct v3d_fence *fence =
172 to_v3d_fence(v3d->tfu_job->base.irq_fence);
173
174 v3d_job_update_stats(&v3d->tfu_job->base, V3D_TFU);
175 trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
176
177 v3d->tfu_job = NULL;
178 dma_fence_signal(&fence->base);
179
180 status = IRQ_HANDLED;
181 }
182
183 if (intsts & (V3D_HUB_INT_MMU_WRV |
184 V3D_HUB_INT_MMU_PTI |
185 V3D_HUB_INT_MMU_CAP)) {
186 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
187 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
188 (v3d->va_width - 32));
189 static const struct {
190 u32 begin;
191 u32 end;
192 const char *client;
193 } v3d41_axi_ids[] = {
194 {0x00, 0x20, "L2T"},
195 {0x20, 0x21, "PTB"},
196 {0x40, 0x41, "PSE"},
197 {0x60, 0x80, "TLB"},
198 {0x80, 0x88, "CLE"},
199 {0xA0, 0xA1, "TFU"},
200 {0xC0, 0xE0, "MMU"},
201 {0xE0, 0xE1, "GMP"},
202 }, v3d71_axi_ids[] = {
203 {0x00, 0x30, "L2T"},
204 {0x30, 0x38, "CLE"},
205 {0x38, 0x39, "PTB"},
206 {0x39, 0x3A, "PSE"},
207 {0x3A, 0x3B, "CSD"},
208 {0x40, 0x60, "TLB"},
209 {0x60, 0x70, "MMU"},
210 {0x7C, 0x7E, "TFU"},
211 {0x7F, 0x80, "GMP"},
212 };
213 const char *client = "?";
214
215 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
216
217 if (v3d->ver >= V3D_GEN_71) {
218 size_t i;
219
220 axi_id = axi_id & 0x7F;
221 for (i = 0; i < ARRAY_SIZE(v3d71_axi_ids); i++) {
222 if (axi_id >= v3d71_axi_ids[i].begin &&
223 axi_id < v3d71_axi_ids[i].end) {
224 client = v3d71_axi_ids[i].client;
225 break;
226 }
227 }
228 } else if (v3d->ver >= V3D_GEN_41) {
229 size_t i;
230
231 axi_id = axi_id & 0xFF;
232 for (i = 0; i < ARRAY_SIZE(v3d41_axi_ids); i++) {
233 if (axi_id >= v3d41_axi_ids[i].begin &&
234 axi_id < v3d41_axi_ids[i].end) {
235 client = v3d41_axi_ids[i].client;
236 break;
237 }
238 }
239 }
240
241 dev_err(v3d->drm.dev, "MMU error from client %s (0x%x) at 0x%llx%s%s%s\n",
242 client, axi_id, (long long)vio_addr,
243 ((intsts & V3D_HUB_INT_MMU_WRV) ?
244 ", write violation" : ""),
245 ((intsts & V3D_HUB_INT_MMU_PTI) ?
246 ", pte invalid" : ""),
247 ((intsts & V3D_HUB_INT_MMU_CAP) ?
248 ", cap exceeded" : ""));
249 status = IRQ_HANDLED;
250 }
251
252 if (v3d->ver >= V3D_GEN_71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
253 dev_err(v3d->drm.dev, "GMP Violation\n");
254 status = IRQ_HANDLED;
255 }
256
257 return status;
258 }
259
260 int
v3d_irq_init(struct v3d_dev * v3d)261 v3d_irq_init(struct v3d_dev *v3d)
262 {
263 int irq, ret, core;
264
265 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
266
267 /* Clear any pending interrupts someone might have left around
268 * for us.
269 */
270 for (core = 0; core < v3d->cores; core++)
271 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
272 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
273
274 irq = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
275 if (irq == -EPROBE_DEFER)
276 return irq;
277 if (irq > 0) {
278 v3d->irq[V3D_CORE_IRQ] = irq;
279
280 ret = devm_request_irq(v3d->drm.dev, v3d->irq[V3D_CORE_IRQ],
281 v3d_irq, IRQF_SHARED,
282 "v3d_core0", v3d);
283 if (ret)
284 goto fail;
285
286 irq = platform_get_irq(v3d_to_pdev(v3d), 0);
287 if (irq < 0)
288 return irq;
289 v3d->irq[V3D_HUB_IRQ] = irq;
290
291 ret = devm_request_irq(v3d->drm.dev, v3d->irq[V3D_HUB_IRQ],
292 v3d_hub_irq, IRQF_SHARED,
293 "v3d_hub", v3d);
294 if (ret)
295 goto fail;
296 } else {
297 v3d->single_irq_line = true;
298
299 irq = platform_get_irq(v3d_to_pdev(v3d), 0);
300 if (irq < 0)
301 return irq;
302 v3d->irq[V3D_CORE_IRQ] = irq;
303
304 ret = devm_request_irq(v3d->drm.dev, v3d->irq[V3D_CORE_IRQ],
305 v3d_irq, IRQF_SHARED,
306 "v3d", v3d);
307 if (ret)
308 goto fail;
309 }
310
311 v3d_irq_enable(v3d);
312 return 0;
313
314 fail:
315 if (ret != -EPROBE_DEFER)
316 dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
317 return ret;
318 }
319
320 void
v3d_irq_enable(struct v3d_dev * v3d)321 v3d_irq_enable(struct v3d_dev *v3d)
322 {
323 int core;
324
325 /* Enable our set of interrupts, masking out any others. */
326 for (core = 0; core < v3d->cores; core++) {
327 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver));
328 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver));
329 }
330
331 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver));
332 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver));
333 }
334
335 void
v3d_irq_disable(struct v3d_dev * v3d)336 v3d_irq_disable(struct v3d_dev *v3d)
337 {
338 int core;
339
340 /* Disable all interrupts. */
341 for (core = 0; core < v3d->cores; core++)
342 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
343 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
344
345 /* Finish any interrupt handler still in flight. */
346 for (int i = 0; i < V3D_MAX_IRQS; i++) {
347 if (v3d->irq[i])
348 synchronize_irq(v3d->irq[i]);
349 }
350
351 /* Clear any pending interrupts we might have left. */
352 for (core = 0; core < v3d->cores; core++)
353 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
354 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
355
356 cancel_work_sync(&v3d->overflow_mem_work);
357 }
358
359 /** Reinitializes interrupt registers when a GPU reset is performed. */
v3d_irq_reset(struct v3d_dev * v3d)360 void v3d_irq_reset(struct v3d_dev *v3d)
361 {
362 v3d_irq_enable(v3d);
363 }
364