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/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
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H A Dhantro_g1_mpeg2_dec.c25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
[all …]
H A Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x01_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
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H A Dhw_host1x07_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
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H A Dhw_host1x08_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
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H A Dhw_host1x06_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
[all …]
H A Dhw_host1x02_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
[all …]
H A Dhw_host1x05_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
[all …]
H A Dhw_host1x04_uclass.h48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f()
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ argument
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) in host1x_uclass_wait_syncpt_thresh_f()
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ argument
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) in host1x_uclass_wait_syncpt_base_indx_f()
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ argument
[all …]
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h19 #define BF_PXP_CTRL_SFTRST(v) \ argument
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ argument
34 #define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ argument
37 #define BF_PXP_CTRL_ENABLE_LUT(v) \ argument
40 #define BF_PXP_CTRL_ENABLE_CSC2(v) \ argument
43 #define BF_PXP_CTRL_BLOCK_SIZE(v) \ argument
48 #define BF_PXP_CTRL_RSVD1(v) \ argument
[all …]
/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) argument
105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3)) argument
106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) argument
107 #define SUN6I_ISP_MODE_SHARP(v) (((v) << 17) & BIT(17)) argument
108 #define SUN6I_ISP_MODE_HIST(v) (((v) << 20) & GENMASK(21, 20)) argument
123 #define SUN6I_ISP_IN_CFG_STRIDE_DIV16(v) ((v) & GENMASK(10, 0)) argument
133 #define SUN6I_ISP_AE_CFG_LOW_BRI_TH(v) ((v) & GENMASK(11, 0)) argument
[all …]
/linux/drivers/iio/adc/
H A Dstm32-dfsdm.h52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) argument
54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) argument
56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) argument
58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) argument
60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) argument
62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) argument
64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) argument
66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) argument
68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) argument
70 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v) argument
[all …]
/linux/sound/soc/qcom/
H A Dlpass-lpaif-reg.h11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ argument
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ argument
73 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) argument
74 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) argument
75 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) argument
78 #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \ argument
81 #define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port) argument
82 #define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port) argument
83 #define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port) argument
[all …]
/linux/arch/x86/lib/
H A Datomic64_386_32.S35 #define v %ecx macro
43 #define v %esi macro
51 #define v %esi macro
61 #define v %ecx macro
69 #define v %ecx macro
79 #define v %ecx macro
87 #define v %ecx macro
100 #define v %esi macro
108 #define v %esi macro
120 #define v %esi macro
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/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v2.c26 #define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v) argument
27 #define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v) argument
28 #define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v) argument
29 #define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v) argument
30 #define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v) argument
31 #define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v) argument
32 #define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v) argument
33 #define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v) argument
34 #define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MASK( 79, 72), v) argument
35 #define CMD_U2_IDB0(v) FIELD_PREP(W2_MASK( 71, 64), v) argument
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H A Dcmd_v1.c27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) argument
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) argument
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) argument
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) argument
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) argument
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) argument
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) argument
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v) argument
42 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v) argument
46 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v) argument
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/linux/tools/testing/selftests/bpf/progs/
H A Dmap_kptr_fail.c27 struct map_value *v; in size_not_bpf_dw() local
42 struct map_value *v; in non_const_var_off() local
61 struct map_value *v; in non_const_var_off_kptr_xchg() local
80 struct map_value *v; in misaligned_access_write() local
96 struct map_value *v; in misaligned_access_read() local
111 struct map_value *v; in reject_var_off_store() local
135 struct map_value *v; in reject_bad_type_match() local
155 struct map_value *v; in marked_as_untrusted_or_null() local
171 struct map_value *v; in correct_btf_id_check_size() local
189 struct map_value *v; in inherit_untrusted_on_walk() local
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/linux/drivers/vhost/
H A Dvdpa.c80 static struct vhost_vdpa_as *asid_to_as(struct vhost_vdpa *v, u32 asid) in asid_to_as()
92 static struct vhost_iotlb *asid_to_iotlb(struct vhost_vdpa *v, u32 asid) in asid_to_iotlb()
102 static struct vhost_vdpa_as *vhost_vdpa_alloc_as(struct vhost_vdpa *v, u32 asid) in vhost_vdpa_alloc_as()
124 static struct vhost_vdpa_as *vhost_vdpa_find_alloc_as(struct vhost_vdpa *v, in vhost_vdpa_find_alloc_as()
135 static void vhost_vdpa_reset_map(struct vhost_vdpa *v, u32 asid) in vhost_vdpa_reset_map()
144 static int vhost_vdpa_remove_as(struct vhost_vdpa *v, u32 asid) in vhost_vdpa_remove_as()
170 struct vhost_vdpa *v = container_of(vq->dev, struct vhost_vdpa, vdev); in handle_vq_kick() local
189 struct vhost_vdpa *v = private; in vhost_vdpa_config_cb() local
198 static void vhost_vdpa_setup_vq_irq(struct vhost_vdpa *v, u16 qid) in vhost_vdpa_setup_vq_irq()
222 static void vhost_vdpa_unsetup_vq_irq(struct vhost_vdpa *v, u16 qid) in vhost_vdpa_unsetup_vq_irq()
[all …]
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
112 #define VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(v) \ argument
114 #define VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(v) \ argument
116 #define VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(v) \ argument
118 #define VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(v) \ argument
250 #define VE_DEC_MPEG_IQMINPUT_WEIGHT(i, v) \ argument
[all …]
/linux/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h20 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
28 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
30 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
35 #define SET_FIELD(addr, mask, shift, v) \ argument
84 #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) argument
85 #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) argument
86 #define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v)) argument
87 #define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v)) argument
88 #define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v)) argument
89 #define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v)) argument
[all …]
/linux/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_io.h58 #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) argument
59 #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) argument
60 #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) argument
61 #define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v)) argument
69 #define bcm_rset_writeb(s, v, o) bcm_writeb((v), \ argument
71 #define bcm_rset_writew(s, v, o) bcm_writew((v), \ argument
73 #define bcm_rset_writel(s, v, o) bcm_writel((v), \ argument
80 #define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o)) argument
82 #define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o)) argument
84 #define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o)) argument
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
250 #define SCALER_SRC_C_POS_SET_CH_POS(v) SCALER_SET(v, 31, 16) argument
252 #define SCALER_SRC_C_POS_SET_CV_POS(v) SCALER_SET(v, 15, 0) argument
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/linux/arch/riscv/kernel/
H A Dmodule.c80 static int apply_r_riscv_32_rela(struct module *me, void *location, Elf_Addr v) in apply_r_riscv_32_rela()
91 static int apply_r_riscv_64_rela(struct module *me, void *location, Elf_Addr v) in apply_r_riscv_64_rela()
98 Elf_Addr v) in apply_r_riscv_branch_rela()
110 Elf_Addr v) in apply_r_riscv_jal_rela()
122 Elf_Addr v) in apply_r_riscv_rvc_branch_rela()
136 Elf_Addr v) in apply_r_riscv_rvc_jump_rela()
153 Elf_Addr v) in apply_r_riscv_pcrel_hi20_rela()
168 Elf_Addr v) in apply_r_riscv_pcrel_lo12_i_rela()
178 Elf_Addr v) in apply_r_riscv_pcrel_lo12_s_rela()
191 Elf_Addr v) in apply_r_riscv_hi20_rela()
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/linux/drivers/media/i2c/
H A Dov8865.c35 #define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0)) argument
37 #define OV8865_PLL_CTRL1_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8) argument
39 #define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0)) argument
41 #define OV8865_PLL_CTRL3_M_DIV(v) (((v) - 1) & GENMASK(3, 0)) argument
43 #define OV8865_PLL_CTRL4_MIPI_DIV(v) ((v) & GENMASK(1, 0)) argument
45 #define OV8865_PLL_CTRL5_SYS_PRE_DIV(v) ((v) & GENMASK(1, 0)) argument
47 #define OV8865_PLL_CTRL6_SYS_DIV(v) (((v) - 1) & BIT(0)) argument
52 #define OV8865_PLL_CTRLA_PRE_DIV_HALF(v) (((v) - 1) & BIT(0)) argument
54 #define OV8865_PLL_CTRLB_PRE_DIV(v) ((v) & GENMASK(2, 0)) argument
56 #define OV8865_PLL_CTRLC_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8) argument
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