1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/drm_gem.h> 31 #include <drm/drm_print.h> 32 33 #include "intel_color_regs.h" 34 #include "intel_de.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_types.h" 37 #include "intel_frontbuffer.h" 38 #include "intel_overlay.h" 39 #include "intel_parent.h" 40 #include "intel_pfit_regs.h" 41 42 /* Limits for overlay size. According to intel doc, the real limits are: 43 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 44 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 45 * the minimum of both. 46 */ 47 #define IMAGE_MAX_WIDTH 2048 48 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 49 /* on 830 and 845 these large limits result in the card hanging */ 50 #define IMAGE_MAX_WIDTH_LEGACY 1024 51 #define IMAGE_MAX_HEIGHT_LEGACY 1088 52 53 /* overlay register definitions */ 54 /* OCMD register */ 55 #define OCMD_TILED_SURFACE (0x1<<19) 56 #define OCMD_MIRROR_MASK (0x3<<17) 57 #define OCMD_MIRROR_MODE (0x3<<17) 58 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 59 #define OCMD_MIRROR_VERTICAL (0x2<<17) 60 #define OCMD_MIRROR_BOTH (0x3<<17) 61 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 62 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 63 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 64 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 65 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 66 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 67 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 68 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_422_PACKED (0x8<<10) 70 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 71 #define OCMD_YUV_420_PLANAR (0xc<<10) 72 #define OCMD_YUV_422_PLANAR (0xd<<10) 73 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 74 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 75 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 76 #define OCMD_BUF_TYPE_MASK (0x1<<5) 77 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 78 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 79 #define OCMD_TEST_MODE (0x1<<4) 80 #define OCMD_BUFFER_SELECT (0x3<<2) 81 #define OCMD_BUFFER0 (0x0<<2) 82 #define OCMD_BUFFER1 (0x1<<2) 83 #define OCMD_FIELD_SELECT (0x1<<2) 84 #define OCMD_FIELD0 (0x0<<1) 85 #define OCMD_FIELD1 (0x1<<1) 86 #define OCMD_ENABLE (0x1<<0) 87 88 /* OCONFIG register */ 89 #define OCONF_PIPE_MASK (0x1<<18) 90 #define OCONF_PIPE_A (0x0<<18) 91 #define OCONF_PIPE_B (0x1<<18) 92 #define OCONF_GAMMA2_ENABLE (0x1<<16) 93 #define OCONF_CSC_MODE_BT601 (0x0<<5) 94 #define OCONF_CSC_MODE_BT709 (0x1<<5) 95 #define OCONF_CSC_BYPASS (0x1<<4) 96 #define OCONF_CC_OUT_8BIT (0x1<<3) 97 #define OCONF_TEST_MODE (0x1<<2) 98 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 99 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 100 101 /* DCLRKM (dst-key) register */ 102 #define DST_KEY_ENABLE (0x1<<31) 103 #define CLK_RGB24_MASK 0x0 104 #define CLK_RGB16_MASK 0x070307 105 #define CLK_RGB15_MASK 0x070707 106 107 #define RGB30_TO_COLORKEY(c) \ 108 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 109 #define RGB16_TO_COLORKEY(c) \ 110 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 111 #define RGB15_TO_COLORKEY(c) \ 112 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 113 #define RGB8I_TO_COLORKEY(c) \ 114 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 115 116 /* polyphase filter coefficients */ 117 #define N_HORIZ_Y_TAPS 5 118 #define N_VERT_Y_TAPS 3 119 #define N_HORIZ_UV_TAPS 3 120 #define N_VERT_UV_TAPS 3 121 #define N_PHASES 17 122 #define MAX_TAPS 5 123 124 /* memory bufferd overlay registers */ 125 struct overlay_registers { 126 u32 OBUF_0Y; 127 u32 OBUF_1Y; 128 u32 OBUF_0U; 129 u32 OBUF_0V; 130 u32 OBUF_1U; 131 u32 OBUF_1V; 132 u32 OSTRIDE; 133 u32 YRGB_VPH; 134 u32 UV_VPH; 135 u32 HORZ_PH; 136 u32 INIT_PHS; 137 u32 DWINPOS; 138 u32 DWINSZ; 139 u32 SWIDTH; 140 u32 SWIDTHSW; 141 u32 SHEIGHT; 142 u32 YRGBSCALE; 143 u32 UVSCALE; 144 u32 OCLRC0; 145 u32 OCLRC1; 146 u32 DCLRKV; 147 u32 DCLRKM; 148 u32 SCLRKVH; 149 u32 SCLRKVL; 150 u32 SCLRKEN; 151 u32 OCONFIG; 152 u32 OCMD; 153 u32 RESERVED1; /* 0x6C */ 154 u32 OSTART_0Y; 155 u32 OSTART_1Y; 156 u32 OSTART_0U; 157 u32 OSTART_0V; 158 u32 OSTART_1U; 159 u32 OSTART_1V; 160 u32 OTILEOFF_0Y; 161 u32 OTILEOFF_1Y; 162 u32 OTILEOFF_0U; 163 u32 OTILEOFF_0V; 164 u32 OTILEOFF_1U; 165 u32 OTILEOFF_1V; 166 u32 FASTHSCALE; /* 0xA0 */ 167 u32 UVSCALEV; /* 0xA4 */ 168 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 169 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 170 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 171 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 172 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 173 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 174 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 175 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 176 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 177 }; 178 179 struct intel_overlay { 180 struct intel_display *display; 181 struct intel_crtc *crtc; 182 bool pfit_active; 183 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 184 u32 color_key:24; 185 u32 color_key_enabled:1; 186 u32 brightness, contrast, saturation; 187 u32 old_xscale, old_yscale; 188 struct overlay_registers __iomem *regs; 189 }; 190 191 void intel_overlay_reset(struct intel_display *display) 192 { 193 struct intel_overlay *overlay = display->overlay; 194 195 if (!overlay) 196 return; 197 198 overlay->old_xscale = 0; 199 overlay->old_yscale = 0; 200 overlay->crtc = NULL; 201 202 intel_parent_overlay_reset(display); 203 } 204 205 static int packed_depth_bytes(u32 format) 206 { 207 switch (format & I915_OVERLAY_DEPTH_MASK) { 208 case I915_OVERLAY_YUV422: 209 return 4; 210 case I915_OVERLAY_YUV411: 211 /* return 6; not implemented */ 212 default: 213 return -EINVAL; 214 } 215 } 216 217 static int packed_width_bytes(u32 format, short width) 218 { 219 switch (format & I915_OVERLAY_DEPTH_MASK) { 220 case I915_OVERLAY_YUV422: 221 return width << 1; 222 default: 223 return -EINVAL; 224 } 225 } 226 227 static int uv_hsubsampling(u32 format) 228 { 229 switch (format & I915_OVERLAY_DEPTH_MASK) { 230 case I915_OVERLAY_YUV422: 231 case I915_OVERLAY_YUV420: 232 return 2; 233 case I915_OVERLAY_YUV411: 234 case I915_OVERLAY_YUV410: 235 return 4; 236 default: 237 return -EINVAL; 238 } 239 } 240 241 static int uv_vsubsampling(u32 format) 242 { 243 switch (format & I915_OVERLAY_DEPTH_MASK) { 244 case I915_OVERLAY_YUV420: 245 case I915_OVERLAY_YUV410: 246 return 2; 247 case I915_OVERLAY_YUV422: 248 case I915_OVERLAY_YUV411: 249 return 1; 250 default: 251 return -EINVAL; 252 } 253 } 254 255 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 256 { 257 u32 sw; 258 259 if (DISPLAY_VER(display) == 2) 260 sw = ALIGN((offset & 31) + width, 32); 261 else 262 sw = ALIGN((offset & 63) + width, 64); 263 264 if (sw == 0) 265 return 0; 266 267 return (sw - 32) >> 3; 268 } 269 270 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 271 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 272 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 273 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 274 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 275 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 276 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 277 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 278 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 279 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 280 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 281 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 282 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 283 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 284 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 285 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 286 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 287 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 288 }; 289 290 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 291 [ 0] = { 0x3000, 0x1800, 0x1800, }, 292 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 293 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 294 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 295 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 296 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 297 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 298 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 299 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 300 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 301 [10] = { 0xb100, 0x1eb8, 0x3620, }, 302 [11] = { 0xb100, 0x1f18, 0x34a0, }, 303 [12] = { 0xb100, 0x1f68, 0x3360, }, 304 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 305 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 306 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 307 [16] = { 0x3000, 0x0800, 0x3000, }, 308 }; 309 310 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 311 { 312 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 313 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 314 sizeof(uv_static_hcoeffs)); 315 } 316 317 static bool update_scaling_factors(struct intel_overlay *overlay, 318 struct overlay_registers __iomem *regs, 319 struct drm_intel_overlay_put_image *params) 320 { 321 /* fixed point with a 12 bit shift */ 322 u32 xscale, yscale, xscale_UV, yscale_UV; 323 #define FP_SHIFT 12 324 #define FRACT_MASK 0xfff 325 bool scale_changed = false; 326 int uv_hscale = uv_hsubsampling(params->flags); 327 int uv_vscale = uv_vsubsampling(params->flags); 328 329 if (params->dst_width > 1) 330 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 331 params->dst_width; 332 else 333 xscale = 1 << FP_SHIFT; 334 335 if (params->dst_height > 1) 336 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 337 params->dst_height; 338 else 339 yscale = 1 << FP_SHIFT; 340 341 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 342 xscale_UV = xscale/uv_hscale; 343 yscale_UV = yscale/uv_vscale; 344 /* make the Y scale to UV scale ratio an exact multiply */ 345 xscale = xscale_UV * uv_hscale; 346 yscale = yscale_UV * uv_vscale; 347 /*} else { 348 xscale_UV = 0; 349 yscale_UV = 0; 350 }*/ 351 352 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 353 scale_changed = true; 354 overlay->old_xscale = xscale; 355 overlay->old_yscale = yscale; 356 357 iowrite32(((yscale & FRACT_MASK) << 20) | 358 ((xscale >> FP_SHIFT) << 16) | 359 ((xscale & FRACT_MASK) << 3), 360 ®s->YRGBSCALE); 361 362 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 363 ((xscale_UV >> FP_SHIFT) << 16) | 364 ((xscale_UV & FRACT_MASK) << 3), 365 ®s->UVSCALE); 366 367 iowrite32((((yscale >> FP_SHIFT) << 16) | 368 ((yscale_UV >> FP_SHIFT) << 0)), 369 ®s->UVSCALEV); 370 371 if (scale_changed) 372 update_polyphase_filter(regs); 373 374 return scale_changed; 375 } 376 377 static void update_colorkey(struct intel_overlay *overlay, 378 struct overlay_registers __iomem *regs) 379 { 380 const struct intel_plane_state *state = 381 to_intel_plane_state(overlay->crtc->base.primary->state); 382 u32 key = overlay->color_key; 383 u32 format = 0; 384 u32 flags = 0; 385 386 if (overlay->color_key_enabled) 387 flags |= DST_KEY_ENABLE; 388 389 if (state->uapi.visible) 390 format = state->hw.fb->format->format; 391 392 switch (format) { 393 case DRM_FORMAT_C8: 394 key = RGB8I_TO_COLORKEY(key); 395 flags |= CLK_RGB24_MASK; 396 break; 397 case DRM_FORMAT_XRGB1555: 398 key = RGB15_TO_COLORKEY(key); 399 flags |= CLK_RGB15_MASK; 400 break; 401 case DRM_FORMAT_RGB565: 402 key = RGB16_TO_COLORKEY(key); 403 flags |= CLK_RGB16_MASK; 404 break; 405 case DRM_FORMAT_XRGB2101010: 406 case DRM_FORMAT_XBGR2101010: 407 key = RGB30_TO_COLORKEY(key); 408 flags |= CLK_RGB24_MASK; 409 break; 410 default: 411 flags |= CLK_RGB24_MASK; 412 break; 413 } 414 415 iowrite32(key, ®s->DCLRKV); 416 iowrite32(flags, ®s->DCLRKM); 417 } 418 419 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 420 { 421 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 422 423 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 424 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 425 case I915_OVERLAY_YUV422: 426 cmd |= OCMD_YUV_422_PLANAR; 427 break; 428 case I915_OVERLAY_YUV420: 429 cmd |= OCMD_YUV_420_PLANAR; 430 break; 431 case I915_OVERLAY_YUV411: 432 case I915_OVERLAY_YUV410: 433 cmd |= OCMD_YUV_410_PLANAR; 434 break; 435 } 436 } else { /* YUV packed */ 437 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 438 case I915_OVERLAY_YUV422: 439 cmd |= OCMD_YUV_422_PACKED; 440 break; 441 case I915_OVERLAY_YUV411: 442 cmd |= OCMD_YUV_411_PACKED; 443 break; 444 } 445 446 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 447 case I915_OVERLAY_NO_SWAP: 448 break; 449 case I915_OVERLAY_UV_SWAP: 450 cmd |= OCMD_UV_SWAP; 451 break; 452 case I915_OVERLAY_Y_SWAP: 453 cmd |= OCMD_Y_SWAP; 454 break; 455 case I915_OVERLAY_Y_AND_UV_SWAP: 456 cmd |= OCMD_Y_AND_UV_SWAP; 457 break; 458 } 459 } 460 461 return cmd; 462 } 463 464 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 465 struct drm_gem_object *obj, 466 struct drm_intel_overlay_put_image *params) 467 { 468 struct intel_display *display = overlay->display; 469 struct overlay_registers __iomem *regs = overlay->regs; 470 u32 swidth, swidthsw, sheight, ostride; 471 enum pipe pipe = overlay->crtc->pipe; 472 bool scale_changed = false; 473 struct i915_vma *vma; 474 int ret, tmp_width; 475 u32 tmp, offset; 476 477 drm_WARN_ON(display->drm, 478 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 479 480 ret = intel_parent_overlay_release_old_vid(display); 481 if (ret != 0) 482 return ret; 483 484 atomic_inc(&display->restore.pending_fb_pin); 485 486 vma = intel_parent_overlay_pin_fb(display, obj, &offset); 487 if (IS_ERR(vma)) { 488 ret = PTR_ERR(vma); 489 goto out_pin_section; 490 } 491 492 if (!intel_parent_overlay_is_active(display)) { 493 const struct intel_crtc_state *crtc_state = 494 overlay->crtc->config; 495 u32 oconfig = 0; 496 497 if (crtc_state->gamma_enable && 498 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 499 oconfig |= OCONF_CC_OUT_8BIT; 500 if (crtc_state->gamma_enable) 501 oconfig |= OCONF_GAMMA2_ENABLE; 502 if (DISPLAY_VER(display) == 4) 503 oconfig |= OCONF_CSC_MODE_BT709; 504 oconfig |= pipe == 0 ? 505 OCONF_PIPE_A : OCONF_PIPE_B; 506 iowrite32(oconfig, ®s->OCONFIG); 507 508 ret = intel_parent_overlay_on(display, INTEL_FRONTBUFFER_OVERLAY(pipe)); 509 if (ret != 0) 510 goto out_unpin; 511 } 512 513 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 514 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 515 516 if (params->flags & I915_OVERLAY_YUV_PACKED) 517 tmp_width = packed_width_bytes(params->flags, 518 params->src_width); 519 else 520 tmp_width = params->src_width; 521 522 swidth = params->src_width; 523 swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 524 sheight = params->src_height; 525 iowrite32(offset + params->offset_Y, ®s->OBUF_0Y); 526 ostride = params->stride_Y; 527 528 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 529 int uv_hscale = uv_hsubsampling(params->flags); 530 int uv_vscale = uv_vsubsampling(params->flags); 531 u32 tmp_U, tmp_V; 532 533 swidth |= (params->src_width / uv_hscale) << 16; 534 sheight |= (params->src_height / uv_vscale) << 16; 535 536 tmp_U = calc_swidthsw(display, params->offset_U, 537 params->src_width / uv_hscale); 538 tmp_V = calc_swidthsw(display, params->offset_V, 539 params->src_width / uv_hscale); 540 swidthsw |= max(tmp_U, tmp_V) << 16; 541 542 iowrite32(offset + params->offset_U, 543 ®s->OBUF_0U); 544 iowrite32(offset + params->offset_V, 545 ®s->OBUF_0V); 546 547 ostride |= params->stride_UV << 16; 548 } 549 550 iowrite32(swidth, ®s->SWIDTH); 551 iowrite32(swidthsw, ®s->SWIDTHSW); 552 iowrite32(sheight, ®s->SHEIGHT); 553 iowrite32(ostride, ®s->OSTRIDE); 554 555 scale_changed = update_scaling_factors(overlay, regs, params); 556 557 update_colorkey(overlay, regs); 558 559 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 560 561 /* check for underruns */ 562 tmp = intel_de_read(display, DOVSTA); 563 if (tmp & (1 << 17)) 564 drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 565 566 ret = intel_parent_overlay_continue(display, vma, scale_changed); 567 if (ret) 568 goto out_unpin; 569 570 return 0; 571 572 out_unpin: 573 intel_parent_overlay_unpin_fb(display, vma); 574 out_pin_section: 575 atomic_dec(&display->restore.pending_fb_pin); 576 577 return ret; 578 } 579 580 int intel_overlay_switch_off(struct intel_overlay *overlay) 581 { 582 struct intel_display *display = overlay->display; 583 int ret; 584 585 drm_WARN_ON(display->drm, 586 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 587 588 ret = intel_parent_overlay_recover_from_interrupt(display); 589 if (ret != 0) 590 return ret; 591 592 if (!intel_parent_overlay_is_active(display)) 593 return 0; 594 595 ret = intel_parent_overlay_release_old_vid(display); 596 if (ret != 0) 597 return ret; 598 599 iowrite32(0, &overlay->regs->OCMD); 600 601 overlay->crtc->overlay = NULL; 602 overlay->crtc = NULL; 603 604 return intel_parent_overlay_off(display); 605 } 606 607 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 608 struct intel_crtc *crtc) 609 { 610 if (!crtc->active) 611 return -EINVAL; 612 613 /* can't use the overlay with double wide pipe */ 614 if (crtc->config->double_wide) 615 return -EINVAL; 616 617 return 0; 618 } 619 620 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 621 { 622 struct intel_display *display = overlay->display; 623 u32 ratio; 624 625 /* XXX: This is not the same logic as in the xorg driver, but more in 626 * line with the intel documentation for the i965 627 */ 628 if (DISPLAY_VER(display) >= 4) { 629 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 630 631 /* on i965 use the PGM reg to read out the autoscaler values */ 632 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 633 } else { 634 u32 tmp; 635 636 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 637 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 638 else 639 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 640 641 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 642 } 643 644 overlay->pfit_vscale_ratio = ratio; 645 } 646 647 static int check_overlay_dst(struct intel_overlay *overlay, 648 struct drm_intel_overlay_put_image *rec) 649 { 650 const struct intel_crtc_state *crtc_state = 651 overlay->crtc->config; 652 struct drm_rect req, clipped; 653 654 drm_rect_init(&req, rec->dst_x, rec->dst_y, 655 rec->dst_width, rec->dst_height); 656 657 clipped = req; 658 659 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src)) 660 return -EINVAL; 661 662 if (!drm_rect_equals(&clipped, &req)) 663 return -EINVAL; 664 665 return 0; 666 } 667 668 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 669 { 670 u32 tmp; 671 672 /* downscaling limit is 8.0 */ 673 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 674 if (tmp > 7) 675 return -EINVAL; 676 677 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 678 if (tmp > 7) 679 return -EINVAL; 680 681 return 0; 682 } 683 684 static int check_overlay_src(struct intel_display *display, 685 struct drm_intel_overlay_put_image *rec, 686 struct drm_gem_object *obj) 687 { 688 int uv_hscale = uv_hsubsampling(rec->flags); 689 int uv_vscale = uv_vsubsampling(rec->flags); 690 u32 stride_mask; 691 int depth; 692 u32 tmp; 693 694 /* check src dimensions */ 695 if (display->platform.i845g || display->platform.i830) { 696 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 697 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 698 return -EINVAL; 699 } else { 700 if (rec->src_height > IMAGE_MAX_HEIGHT || 701 rec->src_width > IMAGE_MAX_WIDTH) 702 return -EINVAL; 703 } 704 705 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 706 if (rec->src_height < N_VERT_Y_TAPS*4 || 707 rec->src_width < N_HORIZ_Y_TAPS*4) 708 return -EINVAL; 709 710 /* check alignment constraints */ 711 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 712 case I915_OVERLAY_RGB: 713 /* not implemented */ 714 return -EINVAL; 715 716 case I915_OVERLAY_YUV_PACKED: 717 if (uv_vscale != 1) 718 return -EINVAL; 719 720 depth = packed_depth_bytes(rec->flags); 721 if (depth < 0) 722 return depth; 723 724 /* ignore UV planes */ 725 rec->stride_UV = 0; 726 rec->offset_U = 0; 727 rec->offset_V = 0; 728 /* check pixel alignment */ 729 if (rec->offset_Y % depth) 730 return -EINVAL; 731 break; 732 733 case I915_OVERLAY_YUV_PLANAR: 734 if (uv_vscale < 0 || uv_hscale < 0) 735 return -EINVAL; 736 /* no offset restrictions for planar formats */ 737 break; 738 739 default: 740 return -EINVAL; 741 } 742 743 if (rec->src_width % uv_hscale) 744 return -EINVAL; 745 746 /* stride checking */ 747 if (display->platform.i830 || display->platform.i845g) 748 stride_mask = 255; 749 else 750 stride_mask = 63; 751 752 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 753 return -EINVAL; 754 if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 755 return -EINVAL; 756 757 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 758 4096 : 8192; 759 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 760 return -EINVAL; 761 762 /* check buffer dimensions */ 763 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 764 case I915_OVERLAY_RGB: 765 case I915_OVERLAY_YUV_PACKED: 766 /* always 4 Y values per depth pixels */ 767 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 768 return -EINVAL; 769 770 tmp = rec->stride_Y*rec->src_height; 771 if (rec->offset_Y + tmp > obj->size) 772 return -EINVAL; 773 break; 774 775 case I915_OVERLAY_YUV_PLANAR: 776 if (rec->src_width > rec->stride_Y) 777 return -EINVAL; 778 if (rec->src_width/uv_hscale > rec->stride_UV) 779 return -EINVAL; 780 781 tmp = rec->stride_Y * rec->src_height; 782 if (rec->offset_Y + tmp > obj->size) 783 return -EINVAL; 784 785 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 786 if (rec->offset_U + tmp > obj->size || 787 rec->offset_V + tmp > obj->size) 788 return -EINVAL; 789 break; 790 } 791 792 return 0; 793 } 794 795 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 796 struct drm_file *file_priv) 797 { 798 struct intel_display *display = to_intel_display(dev); 799 struct drm_intel_overlay_put_image *params = data; 800 struct intel_overlay *overlay; 801 struct drm_crtc *drmmode_crtc; 802 struct drm_gem_object *obj; 803 struct intel_crtc *crtc; 804 int ret; 805 806 overlay = display->overlay; 807 if (!overlay) { 808 drm_dbg(display->drm, "userspace bug: no overlay\n"); 809 return -ENODEV; 810 } 811 812 if (!(params->flags & I915_OVERLAY_ENABLE)) { 813 drm_modeset_lock_all(dev); 814 ret = intel_overlay_switch_off(overlay); 815 drm_modeset_unlock_all(dev); 816 817 return ret; 818 } 819 820 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 821 if (!drmmode_crtc) 822 return -ENOENT; 823 crtc = to_intel_crtc(drmmode_crtc); 824 825 obj = intel_parent_overlay_obj_lookup(display, file_priv, params->bo_handle); 826 if (IS_ERR(obj)) 827 return PTR_ERR(obj); 828 829 drm_modeset_lock_all(dev); 830 831 ret = intel_parent_overlay_recover_from_interrupt(display); 832 if (ret != 0) 833 goto out_unlock; 834 835 if (overlay->crtc != crtc) { 836 ret = intel_overlay_switch_off(overlay); 837 if (ret != 0) 838 goto out_unlock; 839 840 ret = check_overlay_possible_on_crtc(overlay, crtc); 841 if (ret != 0) 842 goto out_unlock; 843 844 overlay->crtc = crtc; 845 crtc->overlay = overlay; 846 847 /* line too wide, i.e. one-line-mode */ 848 if (drm_rect_width(&crtc->config->pipe_src) > 1024 && 849 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 850 overlay->pfit_active = true; 851 update_pfit_vscale_ratio(overlay); 852 } else 853 overlay->pfit_active = false; 854 } 855 856 ret = check_overlay_dst(overlay, params); 857 if (ret != 0) 858 goto out_unlock; 859 860 if (overlay->pfit_active) { 861 params->dst_y = (((u32)params->dst_y << 12) / 862 overlay->pfit_vscale_ratio); 863 /* shifting right rounds downwards, so add 1 */ 864 params->dst_height = (((u32)params->dst_height << 12) / 865 overlay->pfit_vscale_ratio) + 1; 866 } 867 868 if (params->src_scan_height > params->src_height || 869 params->src_scan_width > params->src_width) { 870 ret = -EINVAL; 871 goto out_unlock; 872 } 873 874 ret = check_overlay_src(display, params, obj); 875 if (ret != 0) 876 goto out_unlock; 877 878 /* Check scaling after src size to prevent a divide-by-zero. */ 879 ret = check_overlay_scaling(params); 880 if (ret != 0) 881 goto out_unlock; 882 883 ret = intel_overlay_do_put_image(overlay, obj, params); 884 if (ret != 0) 885 goto out_unlock; 886 887 drm_modeset_unlock_all(dev); 888 drm_gem_object_put(obj); 889 890 return 0; 891 892 out_unlock: 893 drm_modeset_unlock_all(dev); 894 drm_gem_object_put(obj); 895 896 return ret; 897 } 898 899 static void update_reg_attrs(struct intel_overlay *overlay, 900 struct overlay_registers __iomem *regs) 901 { 902 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 903 ®s->OCLRC0); 904 iowrite32(overlay->saturation, ®s->OCLRC1); 905 } 906 907 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 908 { 909 int i; 910 911 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 912 return false; 913 914 for (i = 0; i < 3; i++) { 915 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 916 return false; 917 } 918 919 return true; 920 } 921 922 static bool check_gamma5_errata(u32 gamma5) 923 { 924 int i; 925 926 for (i = 0; i < 3; i++) { 927 if (((gamma5 >> i*8) & 0xff) == 0x80) 928 return false; 929 } 930 931 return true; 932 } 933 934 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 935 { 936 if (!check_gamma_bounds(0, attrs->gamma0) || 937 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 938 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 939 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 940 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 941 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 942 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 943 return -EINVAL; 944 945 if (!check_gamma5_errata(attrs->gamma5)) 946 return -EINVAL; 947 948 return 0; 949 } 950 951 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 952 struct drm_file *file_priv) 953 { 954 struct intel_display *display = to_intel_display(dev); 955 struct drm_intel_overlay_attrs *attrs = data; 956 struct intel_overlay *overlay; 957 int ret; 958 959 overlay = display->overlay; 960 if (!overlay) { 961 drm_dbg(display->drm, "userspace bug: no overlay\n"); 962 return -ENODEV; 963 } 964 965 drm_modeset_lock_all(dev); 966 967 ret = -EINVAL; 968 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 969 attrs->color_key = overlay->color_key; 970 attrs->brightness = overlay->brightness; 971 attrs->contrast = overlay->contrast; 972 attrs->saturation = overlay->saturation; 973 974 if (DISPLAY_VER(display) != 2) { 975 attrs->gamma0 = intel_de_read(display, OGAMC0); 976 attrs->gamma1 = intel_de_read(display, OGAMC1); 977 attrs->gamma2 = intel_de_read(display, OGAMC2); 978 attrs->gamma3 = intel_de_read(display, OGAMC3); 979 attrs->gamma4 = intel_de_read(display, OGAMC4); 980 attrs->gamma5 = intel_de_read(display, OGAMC5); 981 } 982 } else { 983 if (attrs->brightness < -128 || attrs->brightness > 127) 984 goto out_unlock; 985 if (attrs->contrast > 255) 986 goto out_unlock; 987 if (attrs->saturation > 1023) 988 goto out_unlock; 989 990 overlay->color_key = attrs->color_key; 991 overlay->brightness = attrs->brightness; 992 overlay->contrast = attrs->contrast; 993 overlay->saturation = attrs->saturation; 994 995 update_reg_attrs(overlay, overlay->regs); 996 997 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 998 if (DISPLAY_VER(display) == 2) 999 goto out_unlock; 1000 1001 if (intel_parent_overlay_is_active(display)) { 1002 ret = -EBUSY; 1003 goto out_unlock; 1004 } 1005 1006 ret = check_gamma(attrs); 1007 if (ret) 1008 goto out_unlock; 1009 1010 intel_de_write(display, OGAMC0, attrs->gamma0); 1011 intel_de_write(display, OGAMC1, attrs->gamma1); 1012 intel_de_write(display, OGAMC2, attrs->gamma2); 1013 intel_de_write(display, OGAMC3, attrs->gamma3); 1014 intel_de_write(display, OGAMC4, attrs->gamma4); 1015 intel_de_write(display, OGAMC5, attrs->gamma5); 1016 } 1017 } 1018 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1019 1020 ret = 0; 1021 out_unlock: 1022 drm_modeset_unlock_all(dev); 1023 1024 return ret; 1025 } 1026 1027 void intel_overlay_setup(struct intel_display *display) 1028 { 1029 struct intel_overlay *overlay; 1030 void __iomem *regs; 1031 1032 if (!HAS_OVERLAY(display)) 1033 return; 1034 1035 overlay = kzalloc_obj(*overlay); 1036 if (!overlay) 1037 return; 1038 1039 regs = intel_parent_overlay_setup(display, 1040 OVERLAY_NEEDS_PHYSICAL(display)); 1041 if (IS_ERR(regs)) 1042 goto out_free; 1043 1044 overlay->display = display; 1045 overlay->regs = regs; 1046 overlay->color_key = 0x0101fe; 1047 overlay->color_key_enabled = true; 1048 overlay->brightness = -19; 1049 overlay->contrast = 75; 1050 overlay->saturation = 146; 1051 1052 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1053 update_polyphase_filter(overlay->regs); 1054 update_reg_attrs(overlay, overlay->regs); 1055 1056 display->overlay = overlay; 1057 drm_info(display->drm, "Initialized overlay support.\n"); 1058 return; 1059 1060 out_free: 1061 kfree(overlay); 1062 } 1063 1064 bool intel_overlay_available(struct intel_display *display) 1065 { 1066 return display->overlay; 1067 } 1068 1069 void intel_overlay_cleanup(struct intel_display *display) 1070 { 1071 if (!display->overlay) 1072 return; 1073 1074 intel_parent_overlay_cleanup(display); 1075 1076 kfree(display->overlay); 1077 display->overlay = NULL; 1078 } 1079