1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12 #include <linux/units.h>
13
14 #include "sb_regs.h"
15 #include "tb.h"
16
17 #define USB4_DATA_RETRIES 3
18 #define USB4_DATA_DWORDS 16
19
20 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
21 #define USB4_NVM_READ_OFFSET_SHIFT 2
22 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
23 #define USB4_NVM_READ_LENGTH_SHIFT 24
24
25 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
26 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
27
28 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
29 #define USB4_DROM_ADDRESS_SHIFT 2
30 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
31 #define USB4_DROM_SIZE_SHIFT 15
32
33 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
34
35 #define USB4_BA_LENGTH_MASK GENMASK(7, 0)
36 #define USB4_BA_INDEX_MASK GENMASK(15, 0)
37
38 enum usb4_ba_index {
39 USB4_BA_MAX_USB3 = 0x1,
40 USB4_BA_MIN_DP_AUX = 0x2,
41 USB4_BA_MIN_DP_MAIN = 0x3,
42 USB4_BA_MAX_PCIE = 0x4,
43 USB4_BA_MAX_HI = 0x5,
44 };
45
46 #define USB4_BA_VALUE_MASK GENMASK(31, 16)
47 #define USB4_BA_VALUE_SHIFT 16
48
49 /* Delays in us used with usb4_port_wait_for_bit() */
50 #define USB4_PORT_DELAY 50
51 #define USB4_PORT_SB_DELAY 5000
52
usb4_native_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)53 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
54 u32 *metadata, u8 *status,
55 const void *tx_data, size_t tx_dwords,
56 void *rx_data, size_t rx_dwords)
57 {
58 u32 val;
59 int ret;
60
61 if (metadata) {
62 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
63 if (ret)
64 return ret;
65 }
66 if (tx_dwords) {
67 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
68 tx_dwords);
69 if (ret)
70 return ret;
71 }
72
73 val = opcode | ROUTER_CS_26_OV;
74 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
75 if (ret)
76 return ret;
77
78 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
79 if (ret)
80 return ret;
81
82 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
83 if (ret)
84 return ret;
85
86 if (val & ROUTER_CS_26_ONS)
87 return -EOPNOTSUPP;
88
89 if (status)
90 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
91 ROUTER_CS_26_STATUS_SHIFT;
92
93 if (metadata) {
94 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
95 if (ret)
96 return ret;
97 }
98 if (rx_dwords) {
99 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
100 rx_dwords);
101 if (ret)
102 return ret;
103 }
104
105 return 0;
106 }
107
__usb4_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)108 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
109 u8 *status, const void *tx_data, size_t tx_dwords,
110 void *rx_data, size_t rx_dwords)
111 {
112 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
113
114 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
115 return -EINVAL;
116
117 /*
118 * If the connection manager implementation provides USB4 router
119 * operation proxy callback, call it here instead of running the
120 * operation natively.
121 */
122 if (cm_ops->usb4_switch_op) {
123 int ret;
124
125 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
126 tx_data, tx_dwords, rx_data,
127 rx_dwords);
128 if (ret != -EOPNOTSUPP)
129 return ret;
130
131 /*
132 * If the proxy was not supported then run the native
133 * router operation instead.
134 */
135 }
136
137 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
138 tx_dwords, rx_data, rx_dwords);
139 }
140
usb4_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status)141 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
142 u32 *metadata, u8 *status)
143 {
144 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
145 }
146
usb4_switch_op_data(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)147 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
148 u32 *metadata, u8 *status,
149 const void *tx_data, size_t tx_dwords,
150 void *rx_data, size_t rx_dwords)
151 {
152 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
153 tx_dwords, rx_data, rx_dwords);
154 }
155
156 /**
157 * usb4_switch_check_wakes() - Check for wakes and notify PM core about them
158 * @sw: Router whose wakes to check
159 *
160 * Checks wakes occurred during suspend and notify the PM core about them.
161 */
usb4_switch_check_wakes(struct tb_switch * sw)162 void usb4_switch_check_wakes(struct tb_switch *sw)
163 {
164 bool wakeup_usb4 = false;
165 struct usb4_port *usb4;
166 struct tb_port *port;
167 bool wakeup = false;
168 u32 val;
169
170 if (tb_route(sw)) {
171 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
172 return;
173
174 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
175 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
176 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
177
178 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
179 }
180
181 /*
182 * Check for any downstream ports for USB4 wake,
183 * connection wake and disconnection wake.
184 */
185 tb_switch_for_each_port(sw, port) {
186 if (!port->cap_usb4)
187 continue;
188
189 if (tb_port_read(port, &val, TB_CFG_PORT,
190 port->cap_usb4 + PORT_CS_18, 1))
191 break;
192
193 tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
194 (val & PORT_CS_18_WOU4S) ? "yes" : "no",
195 (val & PORT_CS_18_WOCS) ? "yes" : "no",
196 (val & PORT_CS_18_WODS) ? "yes" : "no");
197
198 wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
199 PORT_CS_18_WODS);
200
201 usb4 = port->usb4;
202 if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
203 pm_wakeup_event(&usb4->dev, 0);
204
205 wakeup |= wakeup_usb4;
206 }
207
208 if (wakeup)
209 pm_wakeup_event(&sw->dev, 0);
210 }
211
link_is_usb4(struct tb_port * port)212 static bool link_is_usb4(struct tb_port *port)
213 {
214 u32 val;
215
216 if (!port->cap_usb4)
217 return false;
218
219 if (tb_port_read(port, &val, TB_CFG_PORT,
220 port->cap_usb4 + PORT_CS_18, 1))
221 return false;
222
223 return !(val & PORT_CS_18_TCM);
224 }
225
226 /**
227 * usb4_switch_setup() - Additional setup for USB4 device
228 * @sw: USB4 router to setup
229 *
230 * USB4 routers need additional settings in order to enable all the
231 * tunneling. This function enables USB and PCIe tunneling if it can be
232 * enabled (e.g the parent switch also supports them). If USB tunneling
233 * is not available for some reason (like that there is Thunderbolt 3
234 * switch upstream) then the internal xHCI controller is enabled
235 * instead.
236 *
237 * This does not set the configuration valid bit of the router. To do
238 * that call usb4_switch_configuration_valid().
239 */
usb4_switch_setup(struct tb_switch * sw)240 int usb4_switch_setup(struct tb_switch *sw)
241 {
242 struct tb_switch *parent = tb_switch_parent(sw);
243 struct tb_port *down;
244 bool tbt3, xhci;
245 u32 val = 0;
246 int ret;
247
248 if (!tb_route(sw))
249 return 0;
250
251 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
252 if (ret)
253 return ret;
254
255 down = tb_switch_downstream_port(sw);
256 sw->link_usb4 = link_is_usb4(down);
257 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
258
259 xhci = val & ROUTER_CS_6_HCI;
260 tbt3 = !(val & ROUTER_CS_6_TNS);
261
262 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
263 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
264
265 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
266 if (ret)
267 return ret;
268
269 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
270 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
271 val |= ROUTER_CS_5_UTO;
272 xhci = false;
273 }
274
275 /*
276 * Only enable PCIe tunneling if the parent router supports it
277 * and it is not disabled.
278 */
279 if (tb_acpi_may_tunnel_pcie() &&
280 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
281 val |= ROUTER_CS_5_PTO;
282 /*
283 * xHCI can be enabled if PCIe tunneling is supported
284 * and the parent does not have any USB3 dowstream
285 * adapters (so we cannot do USB 3.x tunneling).
286 */
287 if (xhci)
288 val |= ROUTER_CS_5_HCO;
289 }
290
291 /* TBT3 supported by the CM */
292 val &= ~ROUTER_CS_5_CNS;
293
294 return tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
295 }
296
297 /**
298 * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
299 * @sw: USB4 router
300 *
301 * Sets configuration valid bit for the router. Must be called before
302 * any tunnels can be set through the router and after
303 * usb4_switch_setup() has been called. Can be called to host and device
304 * routers (does nothing for the latter).
305 *
306 * Returns %0 in success and negative errno otherwise.
307 */
usb4_switch_configuration_valid(struct tb_switch * sw)308 int usb4_switch_configuration_valid(struct tb_switch *sw)
309 {
310 u32 val;
311 int ret;
312
313 if (!tb_route(sw))
314 return 0;
315
316 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
317 if (ret)
318 return ret;
319
320 val |= ROUTER_CS_5_CV;
321
322 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
323 if (ret)
324 return ret;
325
326 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
327 ROUTER_CS_6_CR, 50);
328 }
329
330 /**
331 * usb4_switch_read_uid() - Read UID from USB4 router
332 * @sw: USB4 router
333 * @uid: UID is stored here
334 *
335 * Reads 64-bit UID from USB4 router config space.
336 */
usb4_switch_read_uid(struct tb_switch * sw,u64 * uid)337 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
338 {
339 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
340 }
341
usb4_switch_drom_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)342 static int usb4_switch_drom_read_block(void *data,
343 unsigned int dwaddress, void *buf,
344 size_t dwords)
345 {
346 struct tb_switch *sw = data;
347 u8 status = 0;
348 u32 metadata;
349 int ret;
350
351 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
352 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
353 USB4_DROM_ADDRESS_MASK;
354
355 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
356 &status, NULL, 0, buf, dwords);
357 if (ret)
358 return ret;
359
360 return status ? -EIO : 0;
361 }
362
363 /**
364 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
365 * @sw: USB4 router
366 * @address: Byte address inside DROM to start reading
367 * @buf: Buffer where the DROM content is stored
368 * @size: Number of bytes to read from DROM
369 *
370 * Uses USB4 router operations to read router DROM. For devices this
371 * should always work but for hosts it may return %-EOPNOTSUPP in which
372 * case the host router does not have DROM.
373 */
usb4_switch_drom_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)374 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
375 size_t size)
376 {
377 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
378 usb4_switch_drom_read_block, sw);
379 }
380
381 /**
382 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
383 * @sw: USB4 router
384 *
385 * Checks whether conditions are met so that lane bonding can be
386 * established with the upstream router. Call only for device routers.
387 */
usb4_switch_lane_bonding_possible(struct tb_switch * sw)388 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
389 {
390 struct tb_port *up;
391 int ret;
392 u32 val;
393
394 up = tb_upstream_port(sw);
395 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
396 if (ret)
397 return false;
398
399 return !!(val & PORT_CS_18_BE);
400 }
401
402 /**
403 * usb4_switch_set_wake() - Enabled/disable wake
404 * @sw: USB4 router
405 * @flags: Wakeup flags (%0 to disable)
406 *
407 * Enables/disables router to wake up from sleep.
408 */
usb4_switch_set_wake(struct tb_switch * sw,unsigned int flags)409 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
410 {
411 struct usb4_port *usb4;
412 struct tb_port *port;
413 u64 route = tb_route(sw);
414 u32 val;
415 int ret;
416
417 /*
418 * Enable wakes coming from all USB4 downstream ports (from
419 * child routers). For device routers do this also for the
420 * upstream USB4 port.
421 */
422 tb_switch_for_each_port(sw, port) {
423 if (!tb_port_is_null(port))
424 continue;
425 if (!route && tb_is_upstream_port(port))
426 continue;
427 if (!port->cap_usb4)
428 continue;
429
430 ret = tb_port_read(port, &val, TB_CFG_PORT,
431 port->cap_usb4 + PORT_CS_19, 1);
432 if (ret)
433 return ret;
434
435 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
436
437 if (tb_is_upstream_port(port)) {
438 val |= PORT_CS_19_WOU4;
439 } else {
440 bool configured = val & PORT_CS_19_PC;
441 usb4 = port->usb4;
442
443 if (((flags & TB_WAKE_ON_CONNECT) |
444 device_may_wakeup(&usb4->dev)) && !configured)
445 val |= PORT_CS_19_WOC;
446 if (((flags & TB_WAKE_ON_DISCONNECT) |
447 device_may_wakeup(&usb4->dev)) && configured)
448 val |= PORT_CS_19_WOD;
449 if ((flags & TB_WAKE_ON_USB4) && configured)
450 val |= PORT_CS_19_WOU4;
451 }
452
453 ret = tb_port_write(port, &val, TB_CFG_PORT,
454 port->cap_usb4 + PORT_CS_19, 1);
455 if (ret)
456 return ret;
457 }
458
459 /*
460 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
461 * needed for device routers.
462 */
463 if (route) {
464 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
465 if (ret)
466 return ret;
467
468 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
469 if (flags & TB_WAKE_ON_USB3)
470 val |= ROUTER_CS_5_WOU;
471 if (flags & TB_WAKE_ON_PCIE)
472 val |= ROUTER_CS_5_WOP;
473 if (flags & TB_WAKE_ON_DP)
474 val |= ROUTER_CS_5_WOD;
475
476 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
477 if (ret)
478 return ret;
479 }
480
481 return 0;
482 }
483
484 /**
485 * usb4_switch_set_sleep() - Prepare the router to enter sleep
486 * @sw: USB4 router
487 *
488 * Sets sleep bit for the router. Returns when the router sleep ready
489 * bit has been asserted.
490 */
usb4_switch_set_sleep(struct tb_switch * sw)491 int usb4_switch_set_sleep(struct tb_switch *sw)
492 {
493 int ret;
494 u32 val;
495
496 /* Set sleep bit and wait for sleep ready to be asserted */
497 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
498 if (ret)
499 return ret;
500
501 val |= ROUTER_CS_5_SLP;
502
503 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
504 if (ret)
505 return ret;
506
507 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
508 ROUTER_CS_6_SLPR, 500);
509 }
510
511 /**
512 * usb4_switch_nvm_sector_size() - Return router NVM sector size
513 * @sw: USB4 router
514 *
515 * If the router supports NVM operations this function returns the NVM
516 * sector size in bytes. If NVM operations are not supported returns
517 * %-EOPNOTSUPP.
518 */
usb4_switch_nvm_sector_size(struct tb_switch * sw)519 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
520 {
521 u32 metadata;
522 u8 status;
523 int ret;
524
525 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
526 &status);
527 if (ret)
528 return ret;
529
530 if (status)
531 return status == 0x2 ? -EOPNOTSUPP : -EIO;
532
533 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
534 }
535
usb4_switch_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)536 static int usb4_switch_nvm_read_block(void *data,
537 unsigned int dwaddress, void *buf, size_t dwords)
538 {
539 struct tb_switch *sw = data;
540 u8 status = 0;
541 u32 metadata;
542 int ret;
543
544 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
545 USB4_NVM_READ_LENGTH_MASK;
546 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
547 USB4_NVM_READ_OFFSET_MASK;
548
549 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
550 &status, NULL, 0, buf, dwords);
551 if (ret)
552 return ret;
553
554 return status ? -EIO : 0;
555 }
556
557 /**
558 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
559 * @sw: USB4 router
560 * @address: Starting address in bytes
561 * @buf: Read data is placed here
562 * @size: How many bytes to read
563 *
564 * Reads NVM contents of the router. If NVM is not supported returns
565 * %-EOPNOTSUPP.
566 */
usb4_switch_nvm_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)567 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
568 size_t size)
569 {
570 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
571 usb4_switch_nvm_read_block, sw);
572 }
573
574 /**
575 * usb4_switch_nvm_set_offset() - Set NVM write offset
576 * @sw: USB4 router
577 * @address: Start offset
578 *
579 * Explicitly sets NVM write offset. Normally when writing to NVM this
580 * is done automatically by usb4_switch_nvm_write().
581 *
582 * Returns %0 in success and negative errno if there was a failure.
583 */
usb4_switch_nvm_set_offset(struct tb_switch * sw,unsigned int address)584 int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
585 {
586 u32 metadata, dwaddress;
587 u8 status = 0;
588 int ret;
589
590 dwaddress = address / 4;
591 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
592 USB4_NVM_SET_OFFSET_MASK;
593
594 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
595 &status);
596 if (ret)
597 return ret;
598
599 return status ? -EIO : 0;
600 }
601
usb4_switch_nvm_write_next_block(void * data,unsigned int dwaddress,const void * buf,size_t dwords)602 static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
603 const void *buf, size_t dwords)
604 {
605 struct tb_switch *sw = data;
606 u8 status;
607 int ret;
608
609 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
610 buf, dwords, NULL, 0);
611 if (ret)
612 return ret;
613
614 return status ? -EIO : 0;
615 }
616
617 /**
618 * usb4_switch_nvm_write() - Write to the router NVM
619 * @sw: USB4 router
620 * @address: Start address where to write in bytes
621 * @buf: Pointer to the data to write
622 * @size: Size of @buf in bytes
623 *
624 * Writes @buf to the router NVM using USB4 router operations. If NVM
625 * write is not supported returns %-EOPNOTSUPP.
626 */
usb4_switch_nvm_write(struct tb_switch * sw,unsigned int address,const void * buf,size_t size)627 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
628 const void *buf, size_t size)
629 {
630 int ret;
631
632 ret = usb4_switch_nvm_set_offset(sw, address);
633 if (ret)
634 return ret;
635
636 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
637 usb4_switch_nvm_write_next_block, sw);
638 }
639
640 /**
641 * usb4_switch_nvm_authenticate() - Authenticate new NVM
642 * @sw: USB4 router
643 *
644 * After the new NVM has been written via usb4_switch_nvm_write(), this
645 * function triggers NVM authentication process. The router gets power
646 * cycled and if the authentication is successful the new NVM starts
647 * running. In case of failure returns negative errno.
648 *
649 * The caller should call usb4_switch_nvm_authenticate_status() to read
650 * the status of the authentication after power cycle. It should be the
651 * first router operation to avoid the status being lost.
652 */
usb4_switch_nvm_authenticate(struct tb_switch * sw)653 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
654 {
655 int ret;
656
657 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
658 switch (ret) {
659 /*
660 * The router is power cycled once NVM_AUTH is started so it is
661 * expected to get any of the following errors back.
662 */
663 case -EACCES:
664 case -ENOTCONN:
665 case -ETIMEDOUT:
666 return 0;
667
668 default:
669 return ret;
670 }
671 }
672
673 /**
674 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
675 * @sw: USB4 router
676 * @status: Status code of the operation
677 *
678 * The function checks if there is status available from the last NVM
679 * authenticate router operation. If there is status then %0 is returned
680 * and the status code is placed in @status. Returns negative errno in case
681 * of failure.
682 *
683 * Must be called before any other router operation.
684 */
usb4_switch_nvm_authenticate_status(struct tb_switch * sw,u32 * status)685 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
686 {
687 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
688 u16 opcode;
689 u32 val;
690 int ret;
691
692 if (cm_ops->usb4_switch_nvm_authenticate_status) {
693 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
694 if (ret != -EOPNOTSUPP)
695 return ret;
696 }
697
698 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
699 if (ret)
700 return ret;
701
702 /* Check that the opcode is correct */
703 opcode = val & ROUTER_CS_26_OPCODE_MASK;
704 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
705 if (val & ROUTER_CS_26_OV)
706 return -EBUSY;
707 if (val & ROUTER_CS_26_ONS)
708 return -EOPNOTSUPP;
709
710 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
711 ROUTER_CS_26_STATUS_SHIFT;
712 } else {
713 *status = 0;
714 }
715
716 return 0;
717 }
718
719 /**
720 * usb4_switch_credits_init() - Read buffer allocation parameters
721 * @sw: USB4 router
722 *
723 * Reads @sw buffer allocation parameters and initializes @sw buffer
724 * allocation fields accordingly. Specifically @sw->credits_allocation
725 * is set to %true if these parameters can be used in tunneling.
726 *
727 * Returns %0 on success and negative errno otherwise.
728 */
usb4_switch_credits_init(struct tb_switch * sw)729 int usb4_switch_credits_init(struct tb_switch *sw)
730 {
731 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
732 int ret, length, i, nports;
733 const struct tb_port *port;
734 u32 data[USB4_DATA_DWORDS];
735 u32 metadata = 0;
736 u8 status = 0;
737
738 memset(data, 0, sizeof(data));
739 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
740 &status, NULL, 0, data, ARRAY_SIZE(data));
741 if (ret)
742 return ret;
743 if (status)
744 return -EIO;
745
746 length = metadata & USB4_BA_LENGTH_MASK;
747 if (WARN_ON(length > ARRAY_SIZE(data)))
748 return -EMSGSIZE;
749
750 max_usb3 = -1;
751 min_dp_aux = -1;
752 min_dp_main = -1;
753 max_pcie = -1;
754 max_dma = -1;
755
756 tb_sw_dbg(sw, "credit allocation parameters:\n");
757
758 for (i = 0; i < length; i++) {
759 u16 index, value;
760
761 index = data[i] & USB4_BA_INDEX_MASK;
762 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
763
764 switch (index) {
765 case USB4_BA_MAX_USB3:
766 tb_sw_dbg(sw, " USB3: %u\n", value);
767 max_usb3 = value;
768 break;
769 case USB4_BA_MIN_DP_AUX:
770 tb_sw_dbg(sw, " DP AUX: %u\n", value);
771 min_dp_aux = value;
772 break;
773 case USB4_BA_MIN_DP_MAIN:
774 tb_sw_dbg(sw, " DP main: %u\n", value);
775 min_dp_main = value;
776 break;
777 case USB4_BA_MAX_PCIE:
778 tb_sw_dbg(sw, " PCIe: %u\n", value);
779 max_pcie = value;
780 break;
781 case USB4_BA_MAX_HI:
782 tb_sw_dbg(sw, " DMA: %u\n", value);
783 max_dma = value;
784 break;
785 default:
786 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
787 index);
788 break;
789 }
790 }
791
792 /*
793 * Validate the buffer allocation preferences. If we find
794 * issues, log a warning and fall back using the hard-coded
795 * values.
796 */
797
798 /* Host router must report baMaxHI */
799 if (!tb_route(sw) && max_dma < 0) {
800 tb_sw_warn(sw, "host router is missing baMaxHI\n");
801 goto err_invalid;
802 }
803
804 nports = 0;
805 tb_switch_for_each_port(sw, port) {
806 if (tb_port_is_null(port))
807 nports++;
808 }
809
810 /* Must have DP buffer allocation (multiple USB4 ports) */
811 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
812 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
813 goto err_invalid;
814 }
815
816 tb_switch_for_each_port(sw, port) {
817 if (tb_port_is_dpout(port) && min_dp_main < 0) {
818 tb_sw_warn(sw, "missing baMinDPmain");
819 goto err_invalid;
820 }
821 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
822 min_dp_aux < 0) {
823 tb_sw_warn(sw, "missing baMinDPaux");
824 goto err_invalid;
825 }
826 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
827 max_usb3 < 0) {
828 tb_sw_warn(sw, "missing baMaxUSB3");
829 goto err_invalid;
830 }
831 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
832 max_pcie < 0) {
833 tb_sw_warn(sw, "missing baMaxPCIe");
834 goto err_invalid;
835 }
836 }
837
838 /*
839 * Buffer allocation passed the validation so we can use it in
840 * path creation.
841 */
842 sw->credit_allocation = true;
843 if (max_usb3 > 0)
844 sw->max_usb3_credits = max_usb3;
845 if (min_dp_aux > 0)
846 sw->min_dp_aux_credits = min_dp_aux;
847 if (min_dp_main > 0)
848 sw->min_dp_main_credits = min_dp_main;
849 if (max_pcie > 0)
850 sw->max_pcie_credits = max_pcie;
851 if (max_dma > 0)
852 sw->max_dma_credits = max_dma;
853
854 return 0;
855
856 err_invalid:
857 return -EINVAL;
858 }
859
860 /**
861 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
862 * @sw: USB4 router
863 * @in: DP IN adapter
864 *
865 * For DP tunneling this function can be used to query availability of
866 * DP IN resource. Returns true if the resource is available for DP
867 * tunneling, false otherwise.
868 */
usb4_switch_query_dp_resource(struct tb_switch * sw,struct tb_port * in)869 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
870 {
871 u32 metadata = in->port;
872 u8 status;
873 int ret;
874
875 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
876 &status);
877 /*
878 * If DP resource allocation is not supported assume it is
879 * always available.
880 */
881 if (ret == -EOPNOTSUPP)
882 return true;
883 if (ret)
884 return false;
885
886 return !status;
887 }
888
889 /**
890 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
891 * @sw: USB4 router
892 * @in: DP IN adapter
893 *
894 * Allocates DP IN resource for DP tunneling using USB4 router
895 * operations. If the resource was allocated returns %0. Otherwise
896 * returns negative errno, in particular %-EBUSY if the resource is
897 * already allocated.
898 */
usb4_switch_alloc_dp_resource(struct tb_switch * sw,struct tb_port * in)899 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
900 {
901 u32 metadata = in->port;
902 u8 status;
903 int ret;
904
905 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
906 &status);
907 if (ret == -EOPNOTSUPP)
908 return 0;
909 if (ret)
910 return ret;
911
912 return status ? -EBUSY : 0;
913 }
914
915 /**
916 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
917 * @sw: USB4 router
918 * @in: DP IN adapter
919 *
920 * Releases the previously allocated DP IN resource.
921 */
usb4_switch_dealloc_dp_resource(struct tb_switch * sw,struct tb_port * in)922 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
923 {
924 u32 metadata = in->port;
925 u8 status;
926 int ret;
927
928 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
929 &status);
930 if (ret == -EOPNOTSUPP)
931 return 0;
932 if (ret)
933 return ret;
934
935 return status ? -EIO : 0;
936 }
937
usb4_port_idx(const struct tb_switch * sw,const struct tb_port * port)938 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
939 {
940 struct tb_port *p;
941 int usb4_idx = 0;
942
943 /* Assume port is primary */
944 tb_switch_for_each_port(sw, p) {
945 if (!tb_port_is_null(p))
946 continue;
947 if (tb_is_upstream_port(p))
948 continue;
949 if (!p->link_nr) {
950 if (p == port)
951 break;
952 usb4_idx++;
953 }
954 }
955
956 return usb4_idx;
957 }
958
959 /**
960 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
961 * @sw: USB4 router
962 * @port: USB4 port
963 *
964 * USB4 routers have direct mapping between USB4 ports and PCIe
965 * downstream adapters where the PCIe topology is extended. This
966 * function returns the corresponding downstream PCIe adapter or %NULL
967 * if no such mapping was possible.
968 */
usb4_switch_map_pcie_down(struct tb_switch * sw,const struct tb_port * port)969 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
970 const struct tb_port *port)
971 {
972 int usb4_idx = usb4_port_idx(sw, port);
973 struct tb_port *p;
974 int pcie_idx = 0;
975
976 /* Find PCIe down port matching usb4_port */
977 tb_switch_for_each_port(sw, p) {
978 if (!tb_port_is_pcie_down(p))
979 continue;
980
981 if (pcie_idx == usb4_idx)
982 return p;
983
984 pcie_idx++;
985 }
986
987 return NULL;
988 }
989
990 /**
991 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
992 * @sw: USB4 router
993 * @port: USB4 port
994 *
995 * USB4 routers have direct mapping between USB4 ports and USB 3.x
996 * downstream adapters where the USB 3.x topology is extended. This
997 * function returns the corresponding downstream USB 3.x adapter or
998 * %NULL if no such mapping was possible.
999 */
usb4_switch_map_usb3_down(struct tb_switch * sw,const struct tb_port * port)1000 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1001 const struct tb_port *port)
1002 {
1003 int usb4_idx = usb4_port_idx(sw, port);
1004 struct tb_port *p;
1005 int usb_idx = 0;
1006
1007 /* Find USB3 down port matching usb4_port */
1008 tb_switch_for_each_port(sw, p) {
1009 if (!tb_port_is_usb3_down(p))
1010 continue;
1011
1012 if (usb_idx == usb4_idx)
1013 return p;
1014
1015 usb_idx++;
1016 }
1017
1018 return NULL;
1019 }
1020
1021 /**
1022 * usb4_switch_add_ports() - Add USB4 ports for this router
1023 * @sw: USB4 router
1024 *
1025 * For USB4 router finds all USB4 ports and registers devices for each.
1026 * Can be called to any router.
1027 *
1028 * Return %0 in case of success and negative errno in case of failure.
1029 */
usb4_switch_add_ports(struct tb_switch * sw)1030 int usb4_switch_add_ports(struct tb_switch *sw)
1031 {
1032 struct tb_port *port;
1033
1034 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1035 return 0;
1036
1037 tb_switch_for_each_port(sw, port) {
1038 struct usb4_port *usb4;
1039
1040 if (!tb_port_is_null(port))
1041 continue;
1042 if (!port->cap_usb4)
1043 continue;
1044
1045 usb4 = usb4_port_device_add(port);
1046 if (IS_ERR(usb4)) {
1047 usb4_switch_remove_ports(sw);
1048 return PTR_ERR(usb4);
1049 }
1050
1051 port->usb4 = usb4;
1052 }
1053
1054 return 0;
1055 }
1056
1057 /**
1058 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1059 * @sw: USB4 router
1060 *
1061 * Unregisters previously registered USB4 ports.
1062 */
usb4_switch_remove_ports(struct tb_switch * sw)1063 void usb4_switch_remove_ports(struct tb_switch *sw)
1064 {
1065 struct tb_port *port;
1066
1067 tb_switch_for_each_port(sw, port) {
1068 if (port->usb4) {
1069 usb4_port_device_remove(port->usb4);
1070 port->usb4 = NULL;
1071 }
1072 }
1073 }
1074
1075 /**
1076 * usb4_port_unlock() - Unlock USB4 downstream port
1077 * @port: USB4 port to unlock
1078 *
1079 * Unlocks USB4 downstream port so that the connection manager can
1080 * access the router below this port.
1081 */
usb4_port_unlock(struct tb_port * port)1082 int usb4_port_unlock(struct tb_port *port)
1083 {
1084 int ret;
1085 u32 val;
1086
1087 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1088 if (ret)
1089 return ret;
1090
1091 val &= ~ADP_CS_4_LCK;
1092 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1093 }
1094
1095 /**
1096 * usb4_port_hotplug_enable() - Enables hotplug for a port
1097 * @port: USB4 port to operate on
1098 *
1099 * Enables hot plug events on a given port. This is only intended
1100 * to be used on lane, DP-IN, and DP-OUT adapters.
1101 */
usb4_port_hotplug_enable(struct tb_port * port)1102 int usb4_port_hotplug_enable(struct tb_port *port)
1103 {
1104 int ret;
1105 u32 val;
1106
1107 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1108 if (ret)
1109 return ret;
1110
1111 val &= ~ADP_CS_5_DHP;
1112 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1113 }
1114
1115 /**
1116 * usb4_port_reset() - Issue downstream port reset
1117 * @port: USB4 port to reset
1118 *
1119 * Issues downstream port reset to @port.
1120 */
usb4_port_reset(struct tb_port * port)1121 int usb4_port_reset(struct tb_port *port)
1122 {
1123 int ret;
1124 u32 val;
1125
1126 if (!port->cap_usb4)
1127 return -EINVAL;
1128
1129 ret = tb_port_read(port, &val, TB_CFG_PORT,
1130 port->cap_usb4 + PORT_CS_19, 1);
1131 if (ret)
1132 return ret;
1133
1134 val |= PORT_CS_19_DPR;
1135
1136 ret = tb_port_write(port, &val, TB_CFG_PORT,
1137 port->cap_usb4 + PORT_CS_19, 1);
1138 if (ret)
1139 return ret;
1140
1141 fsleep(10000);
1142
1143 ret = tb_port_read(port, &val, TB_CFG_PORT,
1144 port->cap_usb4 + PORT_CS_19, 1);
1145 if (ret)
1146 return ret;
1147
1148 val &= ~PORT_CS_19_DPR;
1149
1150 return tb_port_write(port, &val, TB_CFG_PORT,
1151 port->cap_usb4 + PORT_CS_19, 1);
1152 }
1153
usb4_port_set_configured(struct tb_port * port,bool configured)1154 static int usb4_port_set_configured(struct tb_port *port, bool configured)
1155 {
1156 int ret;
1157 u32 val;
1158
1159 if (!port->cap_usb4)
1160 return -EINVAL;
1161
1162 ret = tb_port_read(port, &val, TB_CFG_PORT,
1163 port->cap_usb4 + PORT_CS_19, 1);
1164 if (ret)
1165 return ret;
1166
1167 if (configured)
1168 val |= PORT_CS_19_PC;
1169 else
1170 val &= ~PORT_CS_19_PC;
1171
1172 return tb_port_write(port, &val, TB_CFG_PORT,
1173 port->cap_usb4 + PORT_CS_19, 1);
1174 }
1175
1176 /**
1177 * usb4_port_configure() - Set USB4 port configured
1178 * @port: USB4 router
1179 *
1180 * Sets the USB4 link to be configured for power management purposes.
1181 */
usb4_port_configure(struct tb_port * port)1182 int usb4_port_configure(struct tb_port *port)
1183 {
1184 return usb4_port_set_configured(port, true);
1185 }
1186
1187 /**
1188 * usb4_port_unconfigure() - Set USB4 port unconfigured
1189 * @port: USB4 router
1190 *
1191 * Sets the USB4 link to be unconfigured for power management purposes.
1192 */
usb4_port_unconfigure(struct tb_port * port)1193 void usb4_port_unconfigure(struct tb_port *port)
1194 {
1195 usb4_port_set_configured(port, false);
1196 }
1197
usb4_set_xdomain_configured(struct tb_port * port,bool configured)1198 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1199 {
1200 int ret;
1201 u32 val;
1202
1203 if (!port->cap_usb4)
1204 return -EINVAL;
1205
1206 ret = tb_port_read(port, &val, TB_CFG_PORT,
1207 port->cap_usb4 + PORT_CS_19, 1);
1208 if (ret)
1209 return ret;
1210
1211 if (configured)
1212 val |= PORT_CS_19_PID;
1213 else
1214 val &= ~PORT_CS_19_PID;
1215
1216 return tb_port_write(port, &val, TB_CFG_PORT,
1217 port->cap_usb4 + PORT_CS_19, 1);
1218 }
1219
1220 /**
1221 * usb4_port_configure_xdomain() - Configure port for XDomain
1222 * @port: USB4 port connected to another host
1223 * @xd: XDomain that is connected to the port
1224 *
1225 * Marks the USB4 port as being connected to another host and updates
1226 * the link type. Returns %0 in success and negative errno in failure.
1227 */
usb4_port_configure_xdomain(struct tb_port * port,struct tb_xdomain * xd)1228 int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1229 {
1230 xd->link_usb4 = link_is_usb4(port);
1231 return usb4_set_xdomain_configured(port, true);
1232 }
1233
1234 /**
1235 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1236 * @port: USB4 port that was connected to another host
1237 *
1238 * Clears USB4 port from being marked as XDomain.
1239 */
usb4_port_unconfigure_xdomain(struct tb_port * port)1240 void usb4_port_unconfigure_xdomain(struct tb_port *port)
1241 {
1242 usb4_set_xdomain_configured(port, false);
1243 }
1244
usb4_port_wait_for_bit(struct tb_port * port,u32 offset,u32 bit,u32 value,int timeout_msec,unsigned long delay_usec)1245 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1246 u32 value, int timeout_msec, unsigned long delay_usec)
1247 {
1248 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1249
1250 do {
1251 u32 val;
1252 int ret;
1253
1254 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1255 if (ret)
1256 return ret;
1257
1258 if ((val & bit) == value)
1259 return 0;
1260
1261 fsleep(delay_usec);
1262 } while (ktime_before(ktime_get(), timeout));
1263
1264 return -ETIMEDOUT;
1265 }
1266
usb4_port_read_data(struct tb_port * port,void * data,size_t dwords)1267 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1268 {
1269 if (dwords > USB4_DATA_DWORDS)
1270 return -EINVAL;
1271
1272 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1273 dwords);
1274 }
1275
usb4_port_write_data(struct tb_port * port,const void * data,size_t dwords)1276 static int usb4_port_write_data(struct tb_port *port, const void *data,
1277 size_t dwords)
1278 {
1279 if (dwords > USB4_DATA_DWORDS)
1280 return -EINVAL;
1281
1282 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1283 dwords);
1284 }
1285
1286 /**
1287 * usb4_port_sb_read() - Read from sideband register
1288 * @port: USB4 port to read
1289 * @target: Sideband target
1290 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1291 * @reg: Sideband register index
1292 * @buf: Buffer where the sideband data is copied
1293 * @size: Size of @buf
1294 *
1295 * Reads data from sideband register @reg and copies it into @buf.
1296 * Returns %0 in case of success and negative errno in case of failure.
1297 */
usb4_port_sb_read(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,void * buf,u8 size)1298 int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, u8 index,
1299 u8 reg, void *buf, u8 size)
1300 {
1301 size_t dwords = DIV_ROUND_UP(size, 4);
1302 int ret;
1303 u32 val;
1304
1305 if (!port->cap_usb4)
1306 return -EINVAL;
1307
1308 val = reg;
1309 val |= size << PORT_CS_1_LENGTH_SHIFT;
1310 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1311 if (target == USB4_SB_TARGET_RETIMER)
1312 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1313 val |= PORT_CS_1_PND;
1314
1315 ret = tb_port_write(port, &val, TB_CFG_PORT,
1316 port->cap_usb4 + PORT_CS_1, 1);
1317 if (ret)
1318 return ret;
1319
1320 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1321 PORT_CS_1_PND, 0, 500, USB4_PORT_SB_DELAY);
1322 if (ret)
1323 return ret;
1324
1325 ret = tb_port_read(port, &val, TB_CFG_PORT,
1326 port->cap_usb4 + PORT_CS_1, 1);
1327 if (ret)
1328 return ret;
1329
1330 if (val & PORT_CS_1_NR)
1331 return -ENODEV;
1332 if (val & PORT_CS_1_RC)
1333 return -EIO;
1334
1335 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1336 }
1337
1338 /**
1339 * usb4_port_sb_write() - Write to sideband register
1340 * @port: USB4 port to write
1341 * @target: Sideband target
1342 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1343 * @reg: Sideband register index
1344 * @buf: Data to write
1345 * @size: Size of @buf
1346 *
1347 * Writes @buf to sideband register @reg. Returns %0 in case of success
1348 * and negative errno in case of failure.
1349 */
usb4_port_sb_write(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,const void * buf,u8 size)1350 int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1351 u8 index, u8 reg, const void *buf, u8 size)
1352 {
1353 size_t dwords = DIV_ROUND_UP(size, 4);
1354 int ret;
1355 u32 val;
1356
1357 if (!port->cap_usb4)
1358 return -EINVAL;
1359
1360 if (buf) {
1361 ret = usb4_port_write_data(port, buf, dwords);
1362 if (ret)
1363 return ret;
1364 }
1365
1366 val = reg;
1367 val |= size << PORT_CS_1_LENGTH_SHIFT;
1368 val |= PORT_CS_1_WNR_WRITE;
1369 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1370 if (target == USB4_SB_TARGET_RETIMER)
1371 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1372 val |= PORT_CS_1_PND;
1373
1374 ret = tb_port_write(port, &val, TB_CFG_PORT,
1375 port->cap_usb4 + PORT_CS_1, 1);
1376 if (ret)
1377 return ret;
1378
1379 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1380 PORT_CS_1_PND, 0, 500, USB4_PORT_SB_DELAY);
1381 if (ret)
1382 return ret;
1383
1384 ret = tb_port_read(port, &val, TB_CFG_PORT,
1385 port->cap_usb4 + PORT_CS_1, 1);
1386 if (ret)
1387 return ret;
1388
1389 if (val & PORT_CS_1_NR)
1390 return -ENODEV;
1391 if (val & PORT_CS_1_RC)
1392 return -EIO;
1393
1394 return 0;
1395 }
1396
usb4_port_sb_opcode_err_to_errno(u32 val)1397 static int usb4_port_sb_opcode_err_to_errno(u32 val)
1398 {
1399 switch (val) {
1400 case 0:
1401 return 0;
1402 case USB4_SB_OPCODE_ERR:
1403 return -EAGAIN;
1404 case USB4_SB_OPCODE_ONS:
1405 return -EOPNOTSUPP;
1406 default:
1407 return -EIO;
1408 }
1409 }
1410
usb4_port_sb_op(struct tb_port * port,enum usb4_sb_target target,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1411 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1412 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1413 {
1414 ktime_t timeout;
1415 u32 val;
1416 int ret;
1417
1418 val = opcode;
1419 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1420 sizeof(val));
1421 if (ret)
1422 return ret;
1423
1424 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1425
1426 do {
1427 /* Check results */
1428 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1429 &val, sizeof(val));
1430 if (ret)
1431 return ret;
1432
1433 if (val != opcode)
1434 return usb4_port_sb_opcode_err_to_errno(val);
1435
1436 fsleep(USB4_PORT_SB_DELAY);
1437 } while (ktime_before(ktime_get(), timeout));
1438
1439 return -ETIMEDOUT;
1440 }
1441
usb4_port_set_router_offline(struct tb_port * port,bool offline)1442 static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1443 {
1444 u32 val = !offline;
1445 int ret;
1446
1447 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1448 USB4_SB_METADATA, &val, sizeof(val));
1449 if (ret)
1450 return ret;
1451
1452 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1453 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1454 USB4_SB_OPCODE, &val, sizeof(val));
1455 }
1456
1457 /**
1458 * usb4_port_router_offline() - Put the USB4 port to offline mode
1459 * @port: USB4 port
1460 *
1461 * This function puts the USB4 port into offline mode. In this mode the
1462 * port does not react on hotplug events anymore. This needs to be
1463 * called before retimer access is done when the USB4 links is not up.
1464 *
1465 * Returns %0 in case of success and negative errno if there was an
1466 * error.
1467 */
usb4_port_router_offline(struct tb_port * port)1468 int usb4_port_router_offline(struct tb_port *port)
1469 {
1470 return usb4_port_set_router_offline(port, true);
1471 }
1472
1473 /**
1474 * usb4_port_router_online() - Put the USB4 port back to online
1475 * @port: USB4 port
1476 *
1477 * Makes the USB4 port functional again.
1478 */
usb4_port_router_online(struct tb_port * port)1479 int usb4_port_router_online(struct tb_port *port)
1480 {
1481 return usb4_port_set_router_offline(port, false);
1482 }
1483
1484 /**
1485 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1486 * @port: USB4 port
1487 *
1488 * This forces the USB4 port to send broadcast RT transaction which
1489 * makes the retimers on the link to assign index to themselves. Returns
1490 * %0 in case of success and negative errno if there was an error.
1491 */
usb4_port_enumerate_retimers(struct tb_port * port)1492 int usb4_port_enumerate_retimers(struct tb_port *port)
1493 {
1494 u32 val;
1495
1496 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1497 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1498 USB4_SB_OPCODE, &val, sizeof(val));
1499 }
1500
1501 /**
1502 * usb4_port_clx_supported() - Check if CLx is supported by the link
1503 * @port: Port to check for CLx support for
1504 *
1505 * PORT_CS_18_CPS bit reflects if the link supports CLx including
1506 * active cables (if connected on the link).
1507 */
usb4_port_clx_supported(struct tb_port * port)1508 bool usb4_port_clx_supported(struct tb_port *port)
1509 {
1510 int ret;
1511 u32 val;
1512
1513 ret = tb_port_read(port, &val, TB_CFG_PORT,
1514 port->cap_usb4 + PORT_CS_18, 1);
1515 if (ret)
1516 return false;
1517
1518 return !!(val & PORT_CS_18_CPS);
1519 }
1520
1521 /**
1522 * usb4_port_asym_supported() - If the port supports asymmetric link
1523 * @port: USB4 port
1524 *
1525 * Checks if the port and the cable supports asymmetric link and returns
1526 * %true in that case.
1527 */
usb4_port_asym_supported(struct tb_port * port)1528 bool usb4_port_asym_supported(struct tb_port *port)
1529 {
1530 u32 val;
1531
1532 if (!port->cap_usb4)
1533 return false;
1534
1535 if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
1536 return false;
1537
1538 return !!(val & PORT_CS_18_CSA);
1539 }
1540
1541 /**
1542 * usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1543 * @port: USB4 port
1544 * @width: Asymmetric width to configure
1545 *
1546 * Sets USB4 port link width to @width. Can be called for widths where
1547 * usb4_port_asym_width_supported() returned @true.
1548 */
usb4_port_asym_set_link_width(struct tb_port * port,enum tb_link_width width)1549 int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1550 {
1551 u32 val;
1552 int ret;
1553
1554 if (!port->cap_phy)
1555 return -EINVAL;
1556
1557 ret = tb_port_read(port, &val, TB_CFG_PORT,
1558 port->cap_phy + LANE_ADP_CS_1, 1);
1559 if (ret)
1560 return ret;
1561
1562 val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1563 switch (width) {
1564 case TB_LINK_WIDTH_DUAL:
1565 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1566 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1567 break;
1568 case TB_LINK_WIDTH_ASYM_TX:
1569 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1570 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1571 break;
1572 case TB_LINK_WIDTH_ASYM_RX:
1573 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1574 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1575 break;
1576 default:
1577 return -EINVAL;
1578 }
1579
1580 return tb_port_write(port, &val, TB_CFG_PORT,
1581 port->cap_phy + LANE_ADP_CS_1, 1);
1582 }
1583
1584 /**
1585 * usb4_port_asym_start() - Start symmetry change and wait for completion
1586 * @port: USB4 port
1587 *
1588 * Start symmetry change of the link to asymmetric or symmetric
1589 * (according to what was previously set in tb_port_set_link_width().
1590 * Wait for completion of the change.
1591 *
1592 * Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
1593 * a negative errno in case of a failure.
1594 */
usb4_port_asym_start(struct tb_port * port)1595 int usb4_port_asym_start(struct tb_port *port)
1596 {
1597 int ret;
1598 u32 val;
1599
1600 ret = tb_port_read(port, &val, TB_CFG_PORT,
1601 port->cap_usb4 + PORT_CS_19, 1);
1602 if (ret)
1603 return ret;
1604
1605 val &= ~PORT_CS_19_START_ASYM;
1606 val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1607
1608 ret = tb_port_write(port, &val, TB_CFG_PORT,
1609 port->cap_usb4 + PORT_CS_19, 1);
1610 if (ret)
1611 return ret;
1612
1613 /*
1614 * Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1615 * port started the symmetry transition.
1616 */
1617 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
1618 PORT_CS_19_START_ASYM, 0, 1000,
1619 USB4_PORT_DELAY);
1620 if (ret)
1621 return ret;
1622
1623 /* Then wait for the transtion to be completed */
1624 return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
1625 PORT_CS_18_TIP, 0, 5000, USB4_PORT_DELAY);
1626 }
1627
1628 /**
1629 * usb4_port_margining_caps() - Read USB4 port marginig capabilities
1630 * @port: USB4 port
1631 * @target: Sideband target
1632 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1633 * @caps: Array with at least two elements to hold the results
1634 *
1635 * Reads the USB4 port lane margining capabilities into @caps.
1636 */
usb4_port_margining_caps(struct tb_port * port,enum usb4_sb_target target,u8 index,u32 * caps)1637 int usb4_port_margining_caps(struct tb_port *port, enum usb4_sb_target target,
1638 u8 index, u32 *caps)
1639 {
1640 int ret;
1641
1642 ret = usb4_port_sb_op(port, target, index,
1643 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1644 if (ret)
1645 return ret;
1646
1647 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, caps,
1648 sizeof(*caps) * 2);
1649 }
1650
1651 /**
1652 * usb4_port_hw_margin() - Run hardware lane margining on port
1653 * @port: USB4 port
1654 * @target: Sideband target
1655 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1656 * @lanes: Which lanes to run (must match the port capabilities). Can be
1657 * %0, %1 or %7.
1658 * @ber_level: BER level contour value
1659 * @timing: Perform timing margining instead of voltage
1660 * @right_high: Use Right/high margin instead of left/low
1661 * @results: Array with at least two elements to hold the results
1662 *
1663 * Runs hardware lane margining on USB4 port and returns the result in
1664 * @results.
1665 */
usb4_port_hw_margin(struct tb_port * port,enum usb4_sb_target target,u8 index,unsigned int lanes,unsigned int ber_level,bool timing,bool right_high,u32 * results)1666 int usb4_port_hw_margin(struct tb_port *port, enum usb4_sb_target target,
1667 u8 index, unsigned int lanes, unsigned int ber_level,
1668 bool timing, bool right_high, u32 *results)
1669 {
1670 u32 val;
1671 int ret;
1672
1673 val = lanes;
1674 if (timing)
1675 val |= USB4_MARGIN_HW_TIME;
1676 if (right_high)
1677 val |= USB4_MARGIN_HW_RH;
1678 if (ber_level)
1679 val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
1680 USB4_MARGIN_HW_BER_MASK;
1681
1682 ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
1683 sizeof(val));
1684 if (ret)
1685 return ret;
1686
1687 ret = usb4_port_sb_op(port, target, index,
1688 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1689 if (ret)
1690 return ret;
1691
1692 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, results,
1693 sizeof(*results) * 2);
1694 }
1695
1696 /**
1697 * usb4_port_sw_margin() - Run software lane margining on port
1698 * @port: USB4 port
1699 * @target: Sideband target
1700 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1701 * @lanes: Which lanes to run (must match the port capabilities). Can be
1702 * %0, %1 or %7.
1703 * @timing: Perform timing margining instead of voltage
1704 * @right_high: Use Right/high margin instead of left/low
1705 * @counter: What to do with the error counter
1706 *
1707 * Runs software lane margining on USB4 port. Read back the error
1708 * counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1709 * success and negative errno otherwise.
1710 */
usb4_port_sw_margin(struct tb_port * port,enum usb4_sb_target target,u8 index,unsigned int lanes,bool timing,bool right_high,u32 counter)1711 int usb4_port_sw_margin(struct tb_port *port, enum usb4_sb_target target,
1712 u8 index, unsigned int lanes, bool timing,
1713 bool right_high, u32 counter)
1714 {
1715 u32 val;
1716 int ret;
1717
1718 val = lanes;
1719 if (timing)
1720 val |= USB4_MARGIN_SW_TIME;
1721 if (right_high)
1722 val |= USB4_MARGIN_SW_RH;
1723 val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
1724 USB4_MARGIN_SW_COUNTER_MASK;
1725
1726 ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
1727 sizeof(val));
1728 if (ret)
1729 return ret;
1730
1731 return usb4_port_sb_op(port, target, index,
1732 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1733 }
1734
1735 /**
1736 * usb4_port_sw_margin_errors() - Read the software margining error counters
1737 * @port: USB4 port
1738 * @target: Sideband target
1739 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1740 * @errors: Error metadata is copied here.
1741 *
1742 * This reads back the software margining error counters from the port.
1743 * Returns %0 in success and negative errno otherwise.
1744 */
usb4_port_sw_margin_errors(struct tb_port * port,enum usb4_sb_target target,u8 index,u32 * errors)1745 int usb4_port_sw_margin_errors(struct tb_port *port, enum usb4_sb_target target,
1746 u8 index, u32 *errors)
1747 {
1748 int ret;
1749
1750 ret = usb4_port_sb_op(port, target, index,
1751 USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1752 if (ret)
1753 return ret;
1754
1755 return usb4_port_sb_read(port, target, index, USB4_SB_METADATA, errors,
1756 sizeof(*errors));
1757 }
1758
usb4_port_retimer_op(struct tb_port * port,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1759 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1760 enum usb4_sb_opcode opcode,
1761 int timeout_msec)
1762 {
1763 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1764 timeout_msec);
1765 }
1766
1767 /**
1768 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1769 * @port: USB4 port
1770 * @index: Retimer index
1771 *
1772 * Enables sideband channel transations on SBTX. Can be used when USB4
1773 * link does not go up, for example if there is no device connected.
1774 */
usb4_port_retimer_set_inbound_sbtx(struct tb_port * port,u8 index)1775 int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1776 {
1777 int ret;
1778
1779 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1780 500);
1781
1782 if (ret != -ENODEV)
1783 return ret;
1784
1785 /*
1786 * Per the USB4 retimer spec, the retimer is not required to
1787 * send an RT (Retimer Transaction) response for the first
1788 * SET_INBOUND_SBTX command
1789 */
1790 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1791 500);
1792 }
1793
1794 /**
1795 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1796 * @port: USB4 port
1797 * @index: Retimer index
1798 *
1799 * Disables sideband channel transations on SBTX. The reverse of
1800 * usb4_port_retimer_set_inbound_sbtx().
1801 */
usb4_port_retimer_unset_inbound_sbtx(struct tb_port * port,u8 index)1802 int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1803 {
1804 return usb4_port_retimer_op(port, index,
1805 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1806 }
1807
1808 /**
1809 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1810 * @port: USB4 port
1811 * @index: Retimer index
1812 *
1813 * If the retimer at @index is last one (connected directly to the
1814 * Type-C port) this function returns %1. If it is not returns %0. If
1815 * the retimer is not present returns %-ENODEV. Otherwise returns
1816 * negative errno.
1817 */
usb4_port_retimer_is_last(struct tb_port * port,u8 index)1818 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1819 {
1820 u32 metadata;
1821 int ret;
1822
1823 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1824 500);
1825 if (ret)
1826 return ret;
1827
1828 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1829 USB4_SB_METADATA, &metadata, sizeof(metadata));
1830 return ret ? ret : metadata & 1;
1831 }
1832
1833 /**
1834 * usb4_port_retimer_is_cable() - Is the retimer cable retimer
1835 * @port: USB4 port
1836 * @index: Retimer index
1837 *
1838 * If the retimer at @index is last cable retimer this function returns
1839 * %1 and %0 if it is on-board retimer. In case a retimer is not present
1840 * at @index returns %-ENODEV. Otherwise returns negative errno.
1841 */
usb4_port_retimer_is_cable(struct tb_port * port,u8 index)1842 int usb4_port_retimer_is_cable(struct tb_port *port, u8 index)
1843 {
1844 u32 metadata;
1845 int ret;
1846
1847 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_CABLE_RETIMER,
1848 500);
1849 if (ret)
1850 return ret;
1851
1852 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1853 USB4_SB_METADATA, &metadata, sizeof(metadata));
1854 return ret ? ret : metadata & 1;
1855 }
1856
1857 /**
1858 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1859 * @port: USB4 port
1860 * @index: Retimer index
1861 *
1862 * Reads NVM sector size (in bytes) of a retimer at @index. This
1863 * operation can be used to determine whether the retimer supports NVM
1864 * upgrade for example. Returns sector size in bytes or negative errno
1865 * in case of error. Specifically returns %-ENODEV if there is no
1866 * retimer at @index.
1867 */
usb4_port_retimer_nvm_sector_size(struct tb_port * port,u8 index)1868 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1869 {
1870 u32 metadata;
1871 int ret;
1872
1873 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1874 500);
1875 if (ret)
1876 return ret;
1877
1878 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1879 USB4_SB_METADATA, &metadata, sizeof(metadata));
1880 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1881 }
1882
1883 /**
1884 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1885 * @port: USB4 port
1886 * @index: Retimer index
1887 * @address: Start offset
1888 *
1889 * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1890 * done automatically by usb4_port_retimer_nvm_write().
1891 *
1892 * Returns %0 in success and negative errno if there was a failure.
1893 */
usb4_port_retimer_nvm_set_offset(struct tb_port * port,u8 index,unsigned int address)1894 int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1895 unsigned int address)
1896 {
1897 u32 metadata, dwaddress;
1898 int ret;
1899
1900 dwaddress = address / 4;
1901 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1902 USB4_NVM_SET_OFFSET_MASK;
1903
1904 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1905 USB4_SB_METADATA, &metadata, sizeof(metadata));
1906 if (ret)
1907 return ret;
1908
1909 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1910 500);
1911 }
1912
1913 struct retimer_info {
1914 struct tb_port *port;
1915 u8 index;
1916 };
1917
usb4_port_retimer_nvm_write_next_block(void * data,unsigned int dwaddress,const void * buf,size_t dwords)1918 static int usb4_port_retimer_nvm_write_next_block(void *data,
1919 unsigned int dwaddress, const void *buf, size_t dwords)
1920
1921 {
1922 const struct retimer_info *info = data;
1923 struct tb_port *port = info->port;
1924 u8 index = info->index;
1925 int ret;
1926
1927 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1928 USB4_SB_DATA, buf, dwords * 4);
1929 if (ret)
1930 return ret;
1931
1932 return usb4_port_retimer_op(port, index,
1933 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1934 }
1935
1936 /**
1937 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1938 * @port: USB4 port
1939 * @index: Retimer index
1940 * @address: Byte address where to start the write
1941 * @buf: Data to write
1942 * @size: Size in bytes how much to write
1943 *
1944 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1945 * upgrade. Returns %0 if the data was written successfully and negative
1946 * errno in case of failure. Specifically returns %-ENODEV if there is
1947 * no retimer at @index.
1948 */
usb4_port_retimer_nvm_write(struct tb_port * port,u8 index,unsigned int address,const void * buf,size_t size)1949 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1950 const void *buf, size_t size)
1951 {
1952 struct retimer_info info = { .port = port, .index = index };
1953 int ret;
1954
1955 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1956 if (ret)
1957 return ret;
1958
1959 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1960 usb4_port_retimer_nvm_write_next_block, &info);
1961 }
1962
1963 /**
1964 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1965 * @port: USB4 port
1966 * @index: Retimer index
1967 *
1968 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1969 * this function can be used to trigger the NVM upgrade process. If
1970 * successful the retimer restarts with the new NVM and may not have the
1971 * index set so one needs to call usb4_port_enumerate_retimers() to
1972 * force index to be assigned.
1973 */
usb4_port_retimer_nvm_authenticate(struct tb_port * port,u8 index)1974 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1975 {
1976 u32 val;
1977
1978 /*
1979 * We need to use the raw operation here because once the
1980 * authentication completes the retimer index is not set anymore
1981 * so we do not get back the status now.
1982 */
1983 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1984 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1985 USB4_SB_OPCODE, &val, sizeof(val));
1986 }
1987
1988 /**
1989 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1990 * @port: USB4 port
1991 * @index: Retimer index
1992 * @status: Raw status code read from metadata
1993 *
1994 * This can be called after usb4_port_retimer_nvm_authenticate() and
1995 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1996 *
1997 * Returns %0 if the authentication status was successfully read. The
1998 * completion metadata (the result) is then stored into @status. If
1999 * reading the status fails, returns negative errno.
2000 */
usb4_port_retimer_nvm_authenticate_status(struct tb_port * port,u8 index,u32 * status)2001 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
2002 u32 *status)
2003 {
2004 u32 metadata, val;
2005 int ret;
2006
2007 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2008 USB4_SB_OPCODE, &val, sizeof(val));
2009 if (ret)
2010 return ret;
2011
2012 ret = usb4_port_sb_opcode_err_to_errno(val);
2013 switch (ret) {
2014 case 0:
2015 *status = 0;
2016 return 0;
2017
2018 case -EAGAIN:
2019 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2020 USB4_SB_METADATA, &metadata,
2021 sizeof(metadata));
2022 if (ret)
2023 return ret;
2024
2025 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
2026 return 0;
2027
2028 default:
2029 return ret;
2030 }
2031 }
2032
usb4_port_retimer_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)2033 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
2034 void *buf, size_t dwords)
2035 {
2036 const struct retimer_info *info = data;
2037 struct tb_port *port = info->port;
2038 u8 index = info->index;
2039 u32 metadata;
2040 int ret;
2041
2042 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
2043 if (dwords < USB4_DATA_DWORDS)
2044 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
2045
2046 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
2047 USB4_SB_METADATA, &metadata, sizeof(metadata));
2048 if (ret)
2049 return ret;
2050
2051 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
2052 if (ret)
2053 return ret;
2054
2055 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2056 USB4_SB_DATA, buf, dwords * 4);
2057 }
2058
2059 /**
2060 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2061 * @port: USB4 port
2062 * @index: Retimer index
2063 * @address: NVM address (in bytes) to start reading
2064 * @buf: Data read from NVM is stored here
2065 * @size: Number of bytes to read
2066 *
2067 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
2068 * read was successful and negative errno in case of failure.
2069 * Specifically returns %-ENODEV if there is no retimer at @index.
2070 */
usb4_port_retimer_nvm_read(struct tb_port * port,u8 index,unsigned int address,void * buf,size_t size)2071 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2072 unsigned int address, void *buf, size_t size)
2073 {
2074 struct retimer_info info = { .port = port, .index = index };
2075
2076 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2077 usb4_port_retimer_nvm_read_block, &info);
2078 }
2079
2080 static inline unsigned int
usb4_usb3_port_max_bandwidth(const struct tb_port * port,unsigned int bw)2081 usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2082 {
2083 /* Take the possible bandwidth limitation into account */
2084 if (port->max_bw)
2085 return min(bw, port->max_bw);
2086 return bw;
2087 }
2088
2089 /**
2090 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
2091 * @port: USB3 adapter port
2092 *
2093 * Return maximum supported link rate of a USB3 adapter in Mb/s.
2094 * Negative errno in case of error.
2095 */
usb4_usb3_port_max_link_rate(struct tb_port * port)2096 int usb4_usb3_port_max_link_rate(struct tb_port *port)
2097 {
2098 int ret, lr;
2099 u32 val;
2100
2101 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2102 return -EINVAL;
2103
2104 ret = tb_port_read(port, &val, TB_CFG_PORT,
2105 port->cap_adap + ADP_USB3_CS_4, 1);
2106 if (ret)
2107 return ret;
2108
2109 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2110 ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2111
2112 return usb4_usb3_port_max_bandwidth(port, ret);
2113 }
2114
usb4_usb3_port_cm_request(struct tb_port * port,bool request)2115 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2116 {
2117 int ret;
2118 u32 val;
2119
2120 if (!tb_port_is_usb3_down(port))
2121 return -EINVAL;
2122 if (tb_route(port->sw))
2123 return -EINVAL;
2124
2125 ret = tb_port_read(port, &val, TB_CFG_PORT,
2126 port->cap_adap + ADP_USB3_CS_2, 1);
2127 if (ret)
2128 return ret;
2129
2130 if (request)
2131 val |= ADP_USB3_CS_2_CMR;
2132 else
2133 val &= ~ADP_USB3_CS_2_CMR;
2134
2135 ret = tb_port_write(port, &val, TB_CFG_PORT,
2136 port->cap_adap + ADP_USB3_CS_2, 1);
2137 if (ret)
2138 return ret;
2139
2140 /*
2141 * We can use val here directly as the CMR bit is in the same place
2142 * as HCA. Just mask out others.
2143 */
2144 val &= ADP_USB3_CS_2_CMR;
2145 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2146 ADP_USB3_CS_1_HCA, val, 1500,
2147 USB4_PORT_DELAY);
2148 }
2149
usb4_usb3_port_set_cm_request(struct tb_port * port)2150 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2151 {
2152 return usb4_usb3_port_cm_request(port, true);
2153 }
2154
usb4_usb3_port_clear_cm_request(struct tb_port * port)2155 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2156 {
2157 return usb4_usb3_port_cm_request(port, false);
2158 }
2159
usb3_bw_to_mbps(u32 bw,u8 scale)2160 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2161 {
2162 unsigned long uframes;
2163
2164 uframes = bw * 512UL << scale;
2165 return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2166 }
2167
mbps_to_usb3_bw(unsigned int mbps,u8 scale)2168 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2169 {
2170 unsigned long uframes;
2171
2172 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2173 uframes = ((unsigned long)mbps * MEGA) / 8000;
2174 return DIV_ROUND_UP(uframes, 512UL << scale);
2175 }
2176
usb4_usb3_port_read_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2177 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2178 int *upstream_bw,
2179 int *downstream_bw)
2180 {
2181 u32 val, bw, scale;
2182 int ret;
2183
2184 ret = tb_port_read(port, &val, TB_CFG_PORT,
2185 port->cap_adap + ADP_USB3_CS_2, 1);
2186 if (ret)
2187 return ret;
2188
2189 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2190 port->cap_adap + ADP_USB3_CS_3, 1);
2191 if (ret)
2192 return ret;
2193
2194 scale &= ADP_USB3_CS_3_SCALE_MASK;
2195
2196 bw = val & ADP_USB3_CS_2_AUBW_MASK;
2197 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2198
2199 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2200 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2201
2202 return 0;
2203 }
2204
2205 /**
2206 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2207 * @port: USB3 adapter port
2208 * @upstream_bw: Allocated upstream bandwidth is stored here
2209 * @downstream_bw: Allocated downstream bandwidth is stored here
2210 *
2211 * Stores currently allocated USB3 bandwidth into @upstream_bw and
2212 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
2213 * errno in failure.
2214 */
usb4_usb3_port_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2215 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2216 int *downstream_bw)
2217 {
2218 int ret;
2219
2220 ret = usb4_usb3_port_set_cm_request(port);
2221 if (ret)
2222 return ret;
2223
2224 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2225 downstream_bw);
2226 usb4_usb3_port_clear_cm_request(port);
2227
2228 return ret;
2229 }
2230
usb4_usb3_port_read_consumed_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2231 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2232 int *upstream_bw,
2233 int *downstream_bw)
2234 {
2235 u32 val, bw, scale;
2236 int ret;
2237
2238 ret = tb_port_read(port, &val, TB_CFG_PORT,
2239 port->cap_adap + ADP_USB3_CS_1, 1);
2240 if (ret)
2241 return ret;
2242
2243 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2244 port->cap_adap + ADP_USB3_CS_3, 1);
2245 if (ret)
2246 return ret;
2247
2248 scale &= ADP_USB3_CS_3_SCALE_MASK;
2249
2250 bw = val & ADP_USB3_CS_1_CUBW_MASK;
2251 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2252
2253 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2254 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2255
2256 return 0;
2257 }
2258
usb4_usb3_port_write_allocated_bandwidth(struct tb_port * port,int upstream_bw,int downstream_bw)2259 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2260 int upstream_bw,
2261 int downstream_bw)
2262 {
2263 u32 val, ubw, dbw, scale;
2264 int ret, max_bw;
2265
2266 /* Figure out suitable scale */
2267 scale = 0;
2268 max_bw = max(upstream_bw, downstream_bw);
2269 while (scale < 64) {
2270 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2271 break;
2272 scale++;
2273 }
2274
2275 if (WARN_ON(scale >= 64))
2276 return -EINVAL;
2277
2278 ret = tb_port_write(port, &scale, TB_CFG_PORT,
2279 port->cap_adap + ADP_USB3_CS_3, 1);
2280 if (ret)
2281 return ret;
2282
2283 ubw = mbps_to_usb3_bw(upstream_bw, scale);
2284 dbw = mbps_to_usb3_bw(downstream_bw, scale);
2285
2286 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2287
2288 ret = tb_port_read(port, &val, TB_CFG_PORT,
2289 port->cap_adap + ADP_USB3_CS_2, 1);
2290 if (ret)
2291 return ret;
2292
2293 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2294 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2295 val |= ubw;
2296
2297 return tb_port_write(port, &val, TB_CFG_PORT,
2298 port->cap_adap + ADP_USB3_CS_2, 1);
2299 }
2300
2301 /**
2302 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2303 * @port: USB3 adapter port
2304 * @upstream_bw: New upstream bandwidth
2305 * @downstream_bw: New downstream bandwidth
2306 *
2307 * This can be used to set how much bandwidth is allocated for the USB3
2308 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2309 * new values programmed to the USB3 adapter allocation registers. If
2310 * the values are lower than what is currently consumed the allocation
2311 * is set to what is currently consumed instead (consumed bandwidth
2312 * cannot be taken away by CM). The actual new values are returned in
2313 * @upstream_bw and @downstream_bw.
2314 *
2315 * Returns %0 in case of success and negative errno if there was a
2316 * failure.
2317 */
usb4_usb3_port_allocate_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2318 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2319 int *downstream_bw)
2320 {
2321 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2322
2323 ret = usb4_usb3_port_set_cm_request(port);
2324 if (ret)
2325 return ret;
2326
2327 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2328 &consumed_down);
2329 if (ret)
2330 goto err_request;
2331
2332 /* Don't allow it go lower than what is consumed */
2333 allocate_up = max(*upstream_bw, consumed_up);
2334 allocate_down = max(*downstream_bw, consumed_down);
2335
2336 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2337 allocate_down);
2338 if (ret)
2339 goto err_request;
2340
2341 *upstream_bw = allocate_up;
2342 *downstream_bw = allocate_down;
2343
2344 err_request:
2345 usb4_usb3_port_clear_cm_request(port);
2346 return ret;
2347 }
2348
2349 /**
2350 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2351 * @port: USB3 adapter port
2352 * @upstream_bw: New allocated upstream bandwidth
2353 * @downstream_bw: New allocated downstream bandwidth
2354 *
2355 * Releases USB3 allocated bandwidth down to what is actually consumed.
2356 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2357 *
2358 * Returns 0% in success and negative errno in case of failure.
2359 */
usb4_usb3_port_release_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2360 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2361 int *downstream_bw)
2362 {
2363 int ret, consumed_up, consumed_down;
2364
2365 ret = usb4_usb3_port_set_cm_request(port);
2366 if (ret)
2367 return ret;
2368
2369 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2370 &consumed_down);
2371 if (ret)
2372 goto err_request;
2373
2374 /*
2375 * Always keep 900 Mb/s to make sure xHCI has at least some
2376 * bandwidth available for isochronous traffic.
2377 */
2378 if (consumed_up < 900)
2379 consumed_up = 900;
2380 if (consumed_down < 900)
2381 consumed_down = 900;
2382
2383 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2384 consumed_down);
2385 if (ret)
2386 goto err_request;
2387
2388 *upstream_bw = consumed_up;
2389 *downstream_bw = consumed_down;
2390
2391 err_request:
2392 usb4_usb3_port_clear_cm_request(port);
2393 return ret;
2394 }
2395
is_usb4_dpin(const struct tb_port * port)2396 static bool is_usb4_dpin(const struct tb_port *port)
2397 {
2398 if (!tb_port_is_dpin(port))
2399 return false;
2400 if (!tb_switch_is_usb4(port->sw))
2401 return false;
2402 return true;
2403 }
2404
2405 /**
2406 * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2407 * @port: DP IN adapter
2408 * @cm_id: CM ID to assign
2409 *
2410 * Sets CM ID for the @port. Returns %0 on success and negative errno
2411 * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2412 * support this.
2413 */
usb4_dp_port_set_cm_id(struct tb_port * port,int cm_id)2414 int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2415 {
2416 u32 val;
2417 int ret;
2418
2419 if (!is_usb4_dpin(port))
2420 return -EOPNOTSUPP;
2421
2422 ret = tb_port_read(port, &val, TB_CFG_PORT,
2423 port->cap_adap + ADP_DP_CS_2, 1);
2424 if (ret)
2425 return ret;
2426
2427 val &= ~ADP_DP_CS_2_CM_ID_MASK;
2428 val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2429
2430 return tb_port_write(port, &val, TB_CFG_PORT,
2431 port->cap_adap + ADP_DP_CS_2, 1);
2432 }
2433
2434 /**
2435 * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2436 * supported
2437 * @port: DP IN adapter to check
2438 *
2439 * Can be called to any DP IN adapter. Returns true if the adapter
2440 * supports USB4 bandwidth allocation mode, false otherwise.
2441 */
usb4_dp_port_bandwidth_mode_supported(struct tb_port * port)2442 bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2443 {
2444 int ret;
2445 u32 val;
2446
2447 if (!is_usb4_dpin(port))
2448 return false;
2449
2450 ret = tb_port_read(port, &val, TB_CFG_PORT,
2451 port->cap_adap + DP_LOCAL_CAP, 1);
2452 if (ret)
2453 return false;
2454
2455 return !!(val & DP_COMMON_CAP_BW_MODE);
2456 }
2457
2458 /**
2459 * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2460 * enabled
2461 * @port: DP IN adapter to check
2462 *
2463 * Can be called to any DP IN adapter. Returns true if the bandwidth
2464 * allocation mode has been enabled, false otherwise.
2465 */
usb4_dp_port_bandwidth_mode_enabled(struct tb_port * port)2466 bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2467 {
2468 int ret;
2469 u32 val;
2470
2471 if (!is_usb4_dpin(port))
2472 return false;
2473
2474 ret = tb_port_read(port, &val, TB_CFG_PORT,
2475 port->cap_adap + ADP_DP_CS_8, 1);
2476 if (ret)
2477 return false;
2478
2479 return !!(val & ADP_DP_CS_8_DPME);
2480 }
2481
2482 /**
2483 * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2484 * bandwidth allocation mode
2485 * @port: DP IN adapter
2486 * @supported: Does the CM support bandwidth allocation mode
2487 *
2488 * Can be called to any DP IN adapter. Sets or clears the CM support bit
2489 * of the DP IN adapter. Returns %0 in success and negative errno
2490 * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2491 * does not support this.
2492 */
usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port * port,bool supported)2493 int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2494 bool supported)
2495 {
2496 u32 val;
2497 int ret;
2498
2499 if (!is_usb4_dpin(port))
2500 return -EOPNOTSUPP;
2501
2502 ret = tb_port_read(port, &val, TB_CFG_PORT,
2503 port->cap_adap + ADP_DP_CS_2, 1);
2504 if (ret)
2505 return ret;
2506
2507 if (supported)
2508 val |= ADP_DP_CS_2_CMMS;
2509 else
2510 val &= ~ADP_DP_CS_2_CMMS;
2511
2512 return tb_port_write(port, &val, TB_CFG_PORT,
2513 port->cap_adap + ADP_DP_CS_2, 1);
2514 }
2515
2516 /**
2517 * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2518 * @port: DP IN adapter
2519 *
2520 * Reads bandwidth allocation Group ID from the DP IN adapter and
2521 * returns it. If the adapter does not support setting Group_ID
2522 * %-EOPNOTSUPP is returned.
2523 */
usb4_dp_port_group_id(struct tb_port * port)2524 int usb4_dp_port_group_id(struct tb_port *port)
2525 {
2526 u32 val;
2527 int ret;
2528
2529 if (!is_usb4_dpin(port))
2530 return -EOPNOTSUPP;
2531
2532 ret = tb_port_read(port, &val, TB_CFG_PORT,
2533 port->cap_adap + ADP_DP_CS_2, 1);
2534 if (ret)
2535 return ret;
2536
2537 return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2538 }
2539
2540 /**
2541 * usb4_dp_port_set_group_id() - Set adapter Group ID
2542 * @port: DP IN adapter
2543 * @group_id: Group ID for the adapter
2544 *
2545 * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2546 * Returns %0 in case of success and negative errno otherwise.
2547 * Specifically returns %-EOPNOTSUPP if the adapter does not support
2548 * this.
2549 */
usb4_dp_port_set_group_id(struct tb_port * port,int group_id)2550 int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2551 {
2552 u32 val;
2553 int ret;
2554
2555 if (!is_usb4_dpin(port))
2556 return -EOPNOTSUPP;
2557
2558 ret = tb_port_read(port, &val, TB_CFG_PORT,
2559 port->cap_adap + ADP_DP_CS_2, 1);
2560 if (ret)
2561 return ret;
2562
2563 val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2564 val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2565
2566 return tb_port_write(port, &val, TB_CFG_PORT,
2567 port->cap_adap + ADP_DP_CS_2, 1);
2568 }
2569
2570 /**
2571 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2572 * @port: DP IN adapter
2573 * @rate: Non-reduced rate in Mb/s is placed here
2574 * @lanes: Non-reduced lanes are placed here
2575 *
2576 * Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2577 * %0 in success and negative errno otherwise. Specifically returns
2578 * %-EOPNOTSUPP if the adapter does not support this.
2579 */
usb4_dp_port_nrd(struct tb_port * port,int * rate,int * lanes)2580 int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2581 {
2582 u32 val, tmp;
2583 int ret;
2584
2585 if (!is_usb4_dpin(port))
2586 return -EOPNOTSUPP;
2587
2588 ret = tb_port_read(port, &val, TB_CFG_PORT,
2589 port->cap_adap + ADP_DP_CS_2, 1);
2590 if (ret)
2591 return ret;
2592
2593 tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2594 switch (tmp) {
2595 case DP_COMMON_CAP_RATE_RBR:
2596 *rate = 1620;
2597 break;
2598 case DP_COMMON_CAP_RATE_HBR:
2599 *rate = 2700;
2600 break;
2601 case DP_COMMON_CAP_RATE_HBR2:
2602 *rate = 5400;
2603 break;
2604 case DP_COMMON_CAP_RATE_HBR3:
2605 *rate = 8100;
2606 break;
2607 }
2608
2609 tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2610 switch (tmp) {
2611 case DP_COMMON_CAP_1_LANE:
2612 *lanes = 1;
2613 break;
2614 case DP_COMMON_CAP_2_LANES:
2615 *lanes = 2;
2616 break;
2617 case DP_COMMON_CAP_4_LANES:
2618 *lanes = 4;
2619 break;
2620 }
2621
2622 return 0;
2623 }
2624
2625 /**
2626 * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2627 * @port: DP IN adapter
2628 * @rate: Non-reduced rate in Mb/s
2629 * @lanes: Non-reduced lanes
2630 *
2631 * Before the capabilities reduction this function can be used to set
2632 * the non-reduced values for the DP IN adapter. Returns %0 in success
2633 * and negative errno otherwise. If the adapter does not support this
2634 * %-EOPNOTSUPP is returned.
2635 */
usb4_dp_port_set_nrd(struct tb_port * port,int rate,int lanes)2636 int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2637 {
2638 u32 val;
2639 int ret;
2640
2641 if (!is_usb4_dpin(port))
2642 return -EOPNOTSUPP;
2643
2644 ret = tb_port_read(port, &val, TB_CFG_PORT,
2645 port->cap_adap + ADP_DP_CS_2, 1);
2646 if (ret)
2647 return ret;
2648
2649 val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2650
2651 switch (rate) {
2652 case 1620:
2653 break;
2654 case 2700:
2655 val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2656 & ADP_DP_CS_2_NRD_MLR_MASK;
2657 break;
2658 case 5400:
2659 val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2660 & ADP_DP_CS_2_NRD_MLR_MASK;
2661 break;
2662 case 8100:
2663 val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2664 & ADP_DP_CS_2_NRD_MLR_MASK;
2665 break;
2666 default:
2667 return -EINVAL;
2668 }
2669
2670 val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2671
2672 switch (lanes) {
2673 case 1:
2674 break;
2675 case 2:
2676 val |= DP_COMMON_CAP_2_LANES;
2677 break;
2678 case 4:
2679 val |= DP_COMMON_CAP_4_LANES;
2680 break;
2681 default:
2682 return -EINVAL;
2683 }
2684
2685 return tb_port_write(port, &val, TB_CFG_PORT,
2686 port->cap_adap + ADP_DP_CS_2, 1);
2687 }
2688
2689 /**
2690 * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2691 * @port: DP IN adapter
2692 *
2693 * Reads the programmed granularity from @port. If the DP IN adapter does
2694 * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2695 * errno in other error cases.
2696 */
usb4_dp_port_granularity(struct tb_port * port)2697 int usb4_dp_port_granularity(struct tb_port *port)
2698 {
2699 u32 val;
2700 int ret;
2701
2702 if (!is_usb4_dpin(port))
2703 return -EOPNOTSUPP;
2704
2705 ret = tb_port_read(port, &val, TB_CFG_PORT,
2706 port->cap_adap + ADP_DP_CS_2, 1);
2707 if (ret)
2708 return ret;
2709
2710 val &= ADP_DP_CS_2_GR_MASK;
2711 val >>= ADP_DP_CS_2_GR_SHIFT;
2712
2713 switch (val) {
2714 case ADP_DP_CS_2_GR_0_25G:
2715 return 250;
2716 case ADP_DP_CS_2_GR_0_5G:
2717 return 500;
2718 case ADP_DP_CS_2_GR_1G:
2719 return 1000;
2720 }
2721
2722 return -EINVAL;
2723 }
2724
2725 /**
2726 * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2727 * @port: DP IN adapter
2728 * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2729 *
2730 * Sets the granularity used with the estimated, allocated and requested
2731 * bandwidth. Returns %0 in success and negative errno otherwise. If the
2732 * adapter does not support this %-EOPNOTSUPP is returned.
2733 */
usb4_dp_port_set_granularity(struct tb_port * port,int granularity)2734 int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2735 {
2736 u32 val;
2737 int ret;
2738
2739 if (!is_usb4_dpin(port))
2740 return -EOPNOTSUPP;
2741
2742 ret = tb_port_read(port, &val, TB_CFG_PORT,
2743 port->cap_adap + ADP_DP_CS_2, 1);
2744 if (ret)
2745 return ret;
2746
2747 val &= ~ADP_DP_CS_2_GR_MASK;
2748
2749 switch (granularity) {
2750 case 250:
2751 val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2752 break;
2753 case 500:
2754 val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2755 break;
2756 case 1000:
2757 val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2758 break;
2759 default:
2760 return -EINVAL;
2761 }
2762
2763 return tb_port_write(port, &val, TB_CFG_PORT,
2764 port->cap_adap + ADP_DP_CS_2, 1);
2765 }
2766
2767 /**
2768 * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2769 * @port: DP IN adapter
2770 * @bw: Estimated bandwidth in Mb/s.
2771 *
2772 * Sets the estimated bandwidth to @bw. Set the granularity by calling
2773 * usb4_dp_port_set_granularity() before calling this. The @bw is round
2774 * down to the closest granularity multiplier. Returns %0 in success
2775 * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2776 * the adapter does not support this.
2777 */
usb4_dp_port_set_estimated_bandwidth(struct tb_port * port,int bw)2778 int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2779 {
2780 u32 val, granularity;
2781 int ret;
2782
2783 if (!is_usb4_dpin(port))
2784 return -EOPNOTSUPP;
2785
2786 ret = usb4_dp_port_granularity(port);
2787 if (ret < 0)
2788 return ret;
2789 granularity = ret;
2790
2791 ret = tb_port_read(port, &val, TB_CFG_PORT,
2792 port->cap_adap + ADP_DP_CS_2, 1);
2793 if (ret)
2794 return ret;
2795
2796 val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2797 val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2798
2799 return tb_port_write(port, &val, TB_CFG_PORT,
2800 port->cap_adap + ADP_DP_CS_2, 1);
2801 }
2802
2803 /**
2804 * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2805 * @port: DP IN adapter
2806 *
2807 * Reads and returns allocated bandwidth for @port in Mb/s (taking into
2808 * account the programmed granularity). Returns negative errno in case
2809 * of error.
2810 */
usb4_dp_port_allocated_bandwidth(struct tb_port * port)2811 int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2812 {
2813 u32 val, granularity;
2814 int ret;
2815
2816 if (!is_usb4_dpin(port))
2817 return -EOPNOTSUPP;
2818
2819 ret = usb4_dp_port_granularity(port);
2820 if (ret < 0)
2821 return ret;
2822 granularity = ret;
2823
2824 ret = tb_port_read(port, &val, TB_CFG_PORT,
2825 port->cap_adap + DP_STATUS, 1);
2826 if (ret)
2827 return ret;
2828
2829 val &= DP_STATUS_ALLOCATED_BW_MASK;
2830 val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2831
2832 return val * granularity;
2833 }
2834
__usb4_dp_port_set_cm_ack(struct tb_port * port,bool ack)2835 static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2836 {
2837 u32 val;
2838 int ret;
2839
2840 ret = tb_port_read(port, &val, TB_CFG_PORT,
2841 port->cap_adap + ADP_DP_CS_2, 1);
2842 if (ret)
2843 return ret;
2844
2845 if (ack)
2846 val |= ADP_DP_CS_2_CA;
2847 else
2848 val &= ~ADP_DP_CS_2_CA;
2849
2850 return tb_port_write(port, &val, TB_CFG_PORT,
2851 port->cap_adap + ADP_DP_CS_2, 1);
2852 }
2853
usb4_dp_port_set_cm_ack(struct tb_port * port)2854 static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2855 {
2856 return __usb4_dp_port_set_cm_ack(port, true);
2857 }
2858
usb4_dp_port_wait_and_clear_cm_ack(struct tb_port * port,int timeout_msec)2859 static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2860 int timeout_msec)
2861 {
2862 ktime_t end;
2863 u32 val;
2864 int ret;
2865
2866 ret = __usb4_dp_port_set_cm_ack(port, false);
2867 if (ret)
2868 return ret;
2869
2870 end = ktime_add_ms(ktime_get(), timeout_msec);
2871 do {
2872 ret = tb_port_read(port, &val, TB_CFG_PORT,
2873 port->cap_adap + ADP_DP_CS_8, 1);
2874 if (ret)
2875 return ret;
2876
2877 if (!(val & ADP_DP_CS_8_DR))
2878 break;
2879
2880 usleep_range(50, 100);
2881 } while (ktime_before(ktime_get(), end));
2882
2883 if (val & ADP_DP_CS_8_DR) {
2884 tb_port_warn(port, "timeout waiting for DPTX request to clear\n");
2885 return -ETIMEDOUT;
2886 }
2887
2888 ret = tb_port_read(port, &val, TB_CFG_PORT,
2889 port->cap_adap + ADP_DP_CS_2, 1);
2890 if (ret)
2891 return ret;
2892
2893 val &= ~ADP_DP_CS_2_CA;
2894 return tb_port_write(port, &val, TB_CFG_PORT,
2895 port->cap_adap + ADP_DP_CS_2, 1);
2896 }
2897
2898 /**
2899 * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2900 * @port: DP IN adapter
2901 * @bw: New allocated bandwidth in Mb/s
2902 *
2903 * Communicates the new allocated bandwidth with the DPCD (graphics
2904 * driver). Takes into account the programmed granularity. Returns %0 in
2905 * success and negative errno in case of error.
2906 */
usb4_dp_port_allocate_bandwidth(struct tb_port * port,int bw)2907 int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2908 {
2909 u32 val, granularity;
2910 int ret;
2911
2912 if (!is_usb4_dpin(port))
2913 return -EOPNOTSUPP;
2914
2915 ret = usb4_dp_port_granularity(port);
2916 if (ret < 0)
2917 return ret;
2918 granularity = ret;
2919
2920 ret = tb_port_read(port, &val, TB_CFG_PORT,
2921 port->cap_adap + DP_STATUS, 1);
2922 if (ret)
2923 return ret;
2924
2925 val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2926 val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2927
2928 ret = tb_port_write(port, &val, TB_CFG_PORT,
2929 port->cap_adap + DP_STATUS, 1);
2930 if (ret)
2931 return ret;
2932
2933 ret = usb4_dp_port_set_cm_ack(port);
2934 if (ret)
2935 return ret;
2936
2937 return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
2938 }
2939
2940 /**
2941 * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2942 * @port: DP IN adapter
2943 *
2944 * Reads the DPCD (graphics driver) requested bandwidth and returns it
2945 * in Mb/s. Takes the programmed granularity into account. In case of
2946 * error returns negative errno. Specifically returns %-EOPNOTSUPP if
2947 * the adapter does not support bandwidth allocation mode, and %ENODATA
2948 * if there is no active bandwidth request from the graphics driver.
2949 */
usb4_dp_port_requested_bandwidth(struct tb_port * port)2950 int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2951 {
2952 u32 val, granularity;
2953 int ret;
2954
2955 if (!is_usb4_dpin(port))
2956 return -EOPNOTSUPP;
2957
2958 ret = usb4_dp_port_granularity(port);
2959 if (ret < 0)
2960 return ret;
2961 granularity = ret;
2962
2963 ret = tb_port_read(port, &val, TB_CFG_PORT,
2964 port->cap_adap + ADP_DP_CS_8, 1);
2965 if (ret)
2966 return ret;
2967
2968 if (!(val & ADP_DP_CS_8_DR))
2969 return -ENODATA;
2970
2971 return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2972 }
2973
2974 /**
2975 * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2976 * @port: PCIe adapter
2977 * @enable: Enable/disable extended encapsulation
2978 *
2979 * Enables or disables extended encapsulation used in PCIe tunneling. Caller
2980 * needs to make sure both adapters support this before enabling. Returns %0 on
2981 * success and negative errno otherwise.
2982 */
usb4_pci_port_set_ext_encapsulation(struct tb_port * port,bool enable)2983 int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2984 {
2985 u32 val;
2986 int ret;
2987
2988 if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2989 return -EINVAL;
2990
2991 ret = tb_port_read(port, &val, TB_CFG_PORT,
2992 port->cap_adap + ADP_PCIE_CS_1, 1);
2993 if (ret)
2994 return ret;
2995
2996 if (enable)
2997 val |= ADP_PCIE_CS_1_EE;
2998 else
2999 val &= ~ADP_PCIE_CS_1_EE;
3000
3001 return tb_port_write(port, &val, TB_CFG_PORT,
3002 port->cap_adap + ADP_PCIE_CS_1, 1);
3003 }
3004