1 /*-
2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <sys/cdefs.h>
18 #include "opt_wlan.h"
19
20 #include <sys/param.h>
21 #include <sys/sockio.h>
22 #include <sys/sysctl.h>
23 #include <sys/lock.h>
24 #include <sys/mutex.h>
25 #include <sys/mbuf.h>
26 #include <sys/kernel.h>
27 #include <sys/socket.h>
28 #include <sys/systm.h>
29 #include <sys/malloc.h>
30 #include <sys/module.h>
31 #include <sys/bus.h>
32 #include <sys/endian.h>
33 #include <sys/kdb.h>
34
35 #include <net/if.h>
36 #include <net/if_var.h>
37 #include <net/if_arp.h>
38 #include <net/ethernet.h>
39 #include <net/if_dl.h>
40 #include <net/if_media.h>
41 #include <net/if_types.h>
42
43 #ifdef INET
44 #include <netinet/in.h>
45 #include <netinet/in_systm.h>
46 #include <netinet/in_var.h>
47 #include <netinet/if_ether.h>
48 #include <netinet/ip.h>
49 #endif
50
51 #include <net80211/ieee80211_var.h>
52 #include <net80211/ieee80211_regdomain.h>
53 #include <net80211/ieee80211_radiotap.h>
54
55 #include <dev/usb/usb.h>
56 #include <dev/usb/usbdi.h>
57 #include "usbdevs.h"
58
59 #include <dev/usb/wlan/if_urtwreg.h>
60 #include <dev/usb/wlan/if_urtwvar.h>
61
62 /* copy some rate indices from if_rtwn_ridx.h */
63 #define URTW_RIDX_CCK5 2
64 #define URTW_RIDX_CCK11 3
65 #define URTW_RIDX_OFDM6 4
66 #define URTW_RIDX_OFDM24 8
67
68 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
69 "USB Realtek 8187L");
70 #ifdef URTW_DEBUG
71 int urtw_debug = 0;
72 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0,
73 "control debugging printfs");
74 enum {
75 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
76 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
77 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
78 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
79 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
80 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
81 URTW_DEBUG_STAT = 0x00000040, /* statistic */
82 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
83 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
84 URTW_DEBUG_ANY = 0xffffffff
85 };
86 #define DPRINTF(sc, m, fmt, ...) do { \
87 if (sc->sc_debug & (m)) \
88 printf(fmt, __VA_ARGS__); \
89 } while (0)
90 #else
91 #define DPRINTF(sc, m, fmt, ...) do { \
92 (void) sc; \
93 } while (0)
94 #endif
95 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
96 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN,
97 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
98
99 /* recognized device vendors/products */
100 #define urtw_lookup(v, p) \
101 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
102 #define URTW_DEV_B(v,p) \
103 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
104 #define URTW_DEV_L(v,p) \
105 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
106 #define URTW_REV_RTL8187B 0
107 #define URTW_REV_RTL8187L 1
108 static const STRUCT_USB_HOST_ID urtw_devs[] = {
109 URTW_DEV_B(NETGEAR, WG111V3),
110 URTW_DEV_B(REALTEK, RTL8187B_0),
111 URTW_DEV_B(REALTEK, RTL8187B_1),
112 URTW_DEV_B(REALTEK, RTL8187B_2),
113 URTW_DEV_B(SITECOMEU, WL168V4),
114 URTW_DEV_L(ASUS, P5B_WIFI),
115 URTW_DEV_L(BELKIN, F5D7050E),
116 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
117 URTW_DEV_L(NETGEAR, WG111V2),
118 URTW_DEV_L(REALTEK, RTL8187),
119 URTW_DEV_L(SITECOMEU, WL168V1),
120 URTW_DEV_L(SURECOM, EP9001G2A),
121 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
125 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
126 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
127 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
128 #undef URTW_DEV_L
129 #undef URTW_DEV_B
130 };
131
132 #define urtw_read8_m(sc, val, data) do { \
133 error = urtw_read8_c(sc, val, data); \
134 if (error != 0) \
135 goto fail; \
136 } while (0)
137 #define urtw_write8_m(sc, val, data) do { \
138 error = urtw_write8_c(sc, val, data); \
139 if (error != 0) \
140 goto fail; \
141 } while (0)
142 #define urtw_read16_m(sc, val, data) do { \
143 error = urtw_read16_c(sc, val, data); \
144 if (error != 0) \
145 goto fail; \
146 } while (0)
147 #define urtw_write16_m(sc, val, data) do { \
148 error = urtw_write16_c(sc, val, data); \
149 if (error != 0) \
150 goto fail; \
151 } while (0)
152 #define urtw_read32_m(sc, val, data) do { \
153 error = urtw_read32_c(sc, val, data); \
154 if (error != 0) \
155 goto fail; \
156 } while (0)
157 #define urtw_write32_m(sc, val, data) do { \
158 error = urtw_write32_c(sc, val, data); \
159 if (error != 0) \
160 goto fail; \
161 } while (0)
162 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
163 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
164 if (error != 0) \
165 goto fail; \
166 } while (0)
167 #define urtw_8187_write_phy_cck(sc, val, data) do { \
168 error = urtw_8187_write_phy_cck_c(sc, val, data); \
169 if (error != 0) \
170 goto fail; \
171 } while (0)
172 #define urtw_8225_write(sc, val, data) do { \
173 error = urtw_8225_write_c(sc, val, data); \
174 if (error != 0) \
175 goto fail; \
176 } while (0)
177
178 struct urtw_pair {
179 uint32_t reg;
180 uint32_t val;
181 };
182
183 static uint8_t urtw_8225_agc[] = {
184 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
185 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
186 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
187 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
188 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
189 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
190 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
191 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
192 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
193 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
194 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
195 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
196 };
197
198 static uint8_t urtw_8225z2_agc[] = {
199 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
200 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
201 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
202 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
203 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
204 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
205 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
206 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
207 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
208 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
209 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
210 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
211 };
212
213 static uint32_t urtw_8225_channel[] = {
214 0x0000, /* dummy channel 0 */
215 0x085c, /* 1 */
216 0x08dc, /* 2 */
217 0x095c, /* 3 */
218 0x09dc, /* 4 */
219 0x0a5c, /* 5 */
220 0x0adc, /* 6 */
221 0x0b5c, /* 7 */
222 0x0bdc, /* 8 */
223 0x0c5c, /* 9 */
224 0x0cdc, /* 10 */
225 0x0d5c, /* 11 */
226 0x0ddc, /* 12 */
227 0x0e5c, /* 13 */
228 0x0f72, /* 14 */
229 };
230
231 static uint8_t urtw_8225_gain[] = {
232 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
233 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
234 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
235 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
236 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
237 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
238 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
239 };
240
241 static struct urtw_pair urtw_8225_rf_part1[] = {
242 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
243 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
244 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
245 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
246 };
247
248 static struct urtw_pair urtw_8225_rf_part2[] = {
249 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
250 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
251 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
252 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
253 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
254 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
255 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
256 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
257 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
258 { 0x27, 0x88 }
259 };
260
261 static struct urtw_pair urtw_8225_rf_part3[] = {
262 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
263 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
264 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
265 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
266 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
267 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
268 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
269 };
270
271 static uint16_t urtw_8225_rxgain[] = {
272 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
273 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
274 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
275 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
276 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
277 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
278 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
279 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
280 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
281 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
282 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
283 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
284 };
285
286 static uint8_t urtw_8225_threshold[] = {
287 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
288 };
289
290 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
291 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
292 };
293
294 static uint8_t urtw_8225_txpwr_cck[] = {
295 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
296 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
297 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
298 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
299 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
300 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
301 };
302
303 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
304 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
305 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
306 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
307 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
308 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
309 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
310 };
311
312 static uint8_t urtw_8225_txpwr_ofdm[]={
313 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
314 };
315
316 static uint8_t urtw_8225v2_gain_bg[]={
317 0x23, 0x15, 0xa5, /* -82-1dbm */
318 0x23, 0x15, 0xb5, /* -82-2dbm */
319 0x23, 0x15, 0xc5, /* -82-3dbm */
320 0x33, 0x15, 0xc5, /* -78dbm */
321 0x43, 0x15, 0xc5, /* -74dbm */
322 0x53, 0x15, 0xc5, /* -70dbm */
323 0x63, 0x15, 0xc5, /* -66dbm */
324 };
325
326 static struct urtw_pair urtw_8225v2_rf_part1[] = {
327 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
328 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
329 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
330 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
331 };
332
333 static struct urtw_pair urtw_8225v2b_rf_part0[] = {
334 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
335 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
336 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
337 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
338 };
339
340 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
341 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
342 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
343 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
344 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
345 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
346 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
347 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
348 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
349 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
350 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
351 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
352 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
353 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
354 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
355 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
356 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
357 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
358 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
359 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
360 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
361 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
362 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
363 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
364 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
365 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
366 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
367 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
368 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
369 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
370 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
371 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
372 };
373
374 static struct urtw_pair urtw_8225v2_rf_part2[] = {
375 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
376 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
377 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
378 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
379 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
380 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
381 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
382 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
383 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
384 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
385 };
386
387 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
388 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
389 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
390 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
391 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
392 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
393 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
394 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
395 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
396 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
397 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
398 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
399 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
400 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
401 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
402 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
403 };
404
405 static struct urtw_pair urtw_8225v2_rf_part3[] = {
406 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
407 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
408 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
409 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
410 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
411 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
412 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
413 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
414 };
415
416 static uint16_t urtw_8225v2_rxgain[] = {
417 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
418 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
419 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
420 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
421 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
422 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
423 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
424 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
425 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
426 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
427 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
428 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
429 };
430
431 static uint16_t urtw_8225v2b_rxgain[] = {
432 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
433 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
434 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
435 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
436 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
437 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
438 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
439 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
440 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
441 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
442 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
443 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
444 };
445
446 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
447 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
448 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
449 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
450 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
451 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
452 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
453 };
454
455 static uint8_t urtw_8225v2_txpwr_cck[] = {
456 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
457 };
458
459 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
460 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
461 };
462
463 static uint8_t urtw_8225v2b_txpwr_cck[] = {
464 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
465 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
466 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
467 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
468 };
469
470 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
471 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
472 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
474 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
475 };
476
477 static struct urtw_pair urtw_ratetable[] = {
478 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
479 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
480 { 96, 10 }, { 108, 11 }
481 };
482
483 #if 0
484 static const uint8_t urtw_8187b_reg_table[][3] = {
485 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
486 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
487 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
488 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
489 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
490 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
491 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
492 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
493 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
494 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
495 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
496 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
497 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
498 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
499 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
500 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
501 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
502 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
503 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
504 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
505 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
506 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
507 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
508 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
509 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
510 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
511 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
512 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
513 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
514 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
515 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
516 };
517 #endif
518
519 static usb_callback_t urtw_bulk_rx_callback;
520 static usb_callback_t urtw_bulk_tx_callback;
521 static usb_callback_t urtw_bulk_tx_status_callback;
522
523 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
524 [URTW_8187B_BULK_RX] = {
525 .type = UE_BULK,
526 .endpoint = 0x83,
527 .direction = UE_DIR_IN,
528 .bufsize = MCLBYTES,
529 .flags = {
530 .ext_buffer = 1,
531 .pipe_bof = 1,
532 .short_xfer_ok = 1
533 },
534 .callback = urtw_bulk_rx_callback
535 },
536 [URTW_8187B_BULK_TX_STATUS] = {
537 .type = UE_BULK,
538 .endpoint = 0x89,
539 .direction = UE_DIR_IN,
540 .bufsize = sizeof(uint64_t),
541 .flags = {
542 .pipe_bof = 1,
543 .short_xfer_ok = 1
544 },
545 .callback = urtw_bulk_tx_status_callback
546 },
547 [URTW_8187B_BULK_TX_BE] = {
548 .type = UE_BULK,
549 .endpoint = URTW_8187B_TXPIPE_BE,
550 .direction = UE_DIR_OUT,
551 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
552 .flags = {
553 .force_short_xfer = 1,
554 .pipe_bof = 1,
555 },
556 .callback = urtw_bulk_tx_callback,
557 .timeout = URTW_DATA_TIMEOUT
558 },
559 [URTW_8187B_BULK_TX_BK] = {
560 .type = UE_BULK,
561 .endpoint = URTW_8187B_TXPIPE_BK,
562 .direction = UE_DIR_OUT,
563 .bufsize = URTW_TX_MAXSIZE,
564 .flags = {
565 .ext_buffer = 1,
566 .force_short_xfer = 1,
567 .pipe_bof = 1,
568 },
569 .callback = urtw_bulk_tx_callback,
570 .timeout = URTW_DATA_TIMEOUT
571 },
572 [URTW_8187B_BULK_TX_VI] = {
573 .type = UE_BULK,
574 .endpoint = URTW_8187B_TXPIPE_VI,
575 .direction = UE_DIR_OUT,
576 .bufsize = URTW_TX_MAXSIZE,
577 .flags = {
578 .ext_buffer = 1,
579 .force_short_xfer = 1,
580 .pipe_bof = 1,
581 },
582 .callback = urtw_bulk_tx_callback,
583 .timeout = URTW_DATA_TIMEOUT
584 },
585 [URTW_8187B_BULK_TX_VO] = {
586 .type = UE_BULK,
587 .endpoint = URTW_8187B_TXPIPE_VO,
588 .direction = UE_DIR_OUT,
589 .bufsize = URTW_TX_MAXSIZE,
590 .flags = {
591 .ext_buffer = 1,
592 .force_short_xfer = 1,
593 .pipe_bof = 1,
594 },
595 .callback = urtw_bulk_tx_callback,
596 .timeout = URTW_DATA_TIMEOUT
597 },
598 [URTW_8187B_BULK_TX_EP12] = {
599 .type = UE_BULK,
600 .endpoint = 0xc,
601 .direction = UE_DIR_OUT,
602 .bufsize = URTW_TX_MAXSIZE,
603 .flags = {
604 .ext_buffer = 1,
605 .force_short_xfer = 1,
606 .pipe_bof = 1,
607 },
608 .callback = urtw_bulk_tx_callback,
609 .timeout = URTW_DATA_TIMEOUT
610 }
611 };
612
613 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
614 [URTW_8187L_BULK_RX] = {
615 .type = UE_BULK,
616 .endpoint = 0x81,
617 .direction = UE_DIR_IN,
618 .bufsize = MCLBYTES,
619 .flags = {
620 .ext_buffer = 1,
621 .pipe_bof = 1,
622 .short_xfer_ok = 1
623 },
624 .callback = urtw_bulk_rx_callback
625 },
626 [URTW_8187L_BULK_TX_LOW] = {
627 .type = UE_BULK,
628 .endpoint = 0x2,
629 .direction = UE_DIR_OUT,
630 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
631 .flags = {
632 .force_short_xfer = 1,
633 .pipe_bof = 1,
634 },
635 .callback = urtw_bulk_tx_callback,
636 .timeout = URTW_DATA_TIMEOUT
637 },
638 [URTW_8187L_BULK_TX_NORMAL] = {
639 .type = UE_BULK,
640 .endpoint = 0x3,
641 .direction = UE_DIR_OUT,
642 .bufsize = URTW_TX_MAXSIZE,
643 .flags = {
644 .ext_buffer = 1,
645 .force_short_xfer = 1,
646 .pipe_bof = 1,
647 },
648 .callback = urtw_bulk_tx_callback,
649 .timeout = URTW_DATA_TIMEOUT
650 },
651 };
652
653 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
654 const char [IFNAMSIZ], int, enum ieee80211_opmode,
655 int, const uint8_t [IEEE80211_ADDR_LEN],
656 const uint8_t [IEEE80211_ADDR_LEN]);
657 static void urtw_vap_delete(struct ieee80211vap *);
658 static void urtw_init(struct urtw_softc *);
659 static void urtw_stop(struct urtw_softc *);
660 static void urtw_parent(struct ieee80211com *);
661 static int urtw_transmit(struct ieee80211com *, struct mbuf *);
662 static void urtw_start(struct urtw_softc *);
663 static int urtw_alloc_rx_data_list(struct urtw_softc *);
664 static int urtw_alloc_tx_data_list(struct urtw_softc *);
665 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
666 const struct ieee80211_bpf_params *);
667 static void urtw_scan_start(struct ieee80211com *);
668 static void urtw_scan_end(struct ieee80211com *);
669 static void urtw_getradiocaps(struct ieee80211com *, int, int *,
670 struct ieee80211_channel[]);
671 static void urtw_set_channel(struct ieee80211com *);
672 static void urtw_update_promisc(struct ieee80211com *);
673 static void urtw_update_mcast(struct ieee80211com *);
674 static int urtw_tx_start(struct urtw_softc *,
675 struct ieee80211_node *, struct mbuf *,
676 struct urtw_data *, int);
677 static int urtw_newstate(struct ieee80211vap *,
678 enum ieee80211_state, int);
679 static void urtw_led_ch(void *);
680 static void urtw_ledtask(void *, int);
681 static void urtw_watchdog(void *);
682 static void urtw_set_multi(void *);
683 static int urtw_isbmode(uint16_t);
684 static uint16_t urtw_rtl2rate(uint32_t);
685 static usb_error_t urtw_set_rate(struct urtw_softc *);
686 static usb_error_t urtw_update_msr(struct urtw_softc *);
687 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
688 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
689 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
690 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
691 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
692 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
693 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
694 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
695 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
696 int);
697 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
698 uint32_t *);
699 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
700 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
701 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
702 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
703 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
704 static usb_error_t urtw_led_init(struct urtw_softc *);
705 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
706 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
707 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
708 uint32_t);
709 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
710 uint8_t, uint32_t);
711 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
712 uint32_t);
713 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
714 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
715 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
716 uint16_t);
717 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
718 uint16_t *);
719 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
720 uint32_t *);
721 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
722 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
723 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
724 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
725 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
726 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
727 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
728 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
729 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
730 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
731 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
732 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
733 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
734 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
735 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
736 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
737 static usb_error_t urtw_intr_enable(struct urtw_softc *);
738 static usb_error_t urtw_intr_disable(struct urtw_softc *);
739 static usb_error_t urtw_reset(struct urtw_softc *);
740 static usb_error_t urtw_led_on(struct urtw_softc *, int);
741 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
742 static usb_error_t urtw_led_blink(struct urtw_softc *);
743 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
744 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
745 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
746 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
747 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
748 static usb_error_t urtw_rx_enable(struct urtw_softc *);
749 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
750 static void urtw_free_tx_data_list(struct urtw_softc *);
751 static void urtw_free_rx_data_list(struct urtw_softc *);
752 static void urtw_free_data_list(struct urtw_softc *,
753 struct urtw_data data[], int, int);
754 static usb_error_t urtw_set_macaddr(struct urtw_softc *, const uint8_t *);
755 static usb_error_t urtw_adapter_start(struct urtw_softc *);
756 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
757 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
758 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
759 static usb_error_t urtw_do_request(struct urtw_softc *,
760 struct usb_device_request *, void *);
761 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
762 static usb_error_t urtw_led_off(struct urtw_softc *, int);
763 static void urtw_abort_xfers(struct urtw_softc *);
764 static struct urtw_data *
765 urtw_getbuf(struct urtw_softc *sc);
766 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t,
767 uint8_t);
768 static void urtw_updateslot(struct ieee80211com *);
769 static void urtw_updateslottask(void *, int);
770 static void urtw_sysctl_node(struct urtw_softc *);
771
772 static int
urtw_match(device_t dev)773 urtw_match(device_t dev)
774 {
775 struct usb_attach_arg *uaa = device_get_ivars(dev);
776
777 if (uaa->usb_mode != USB_MODE_HOST)
778 return (ENXIO);
779 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
780 return (ENXIO);
781 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
782 return (ENXIO);
783
784 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
785 }
786
787 static int
urtw_attach(device_t dev)788 urtw_attach(device_t dev)
789 {
790 const struct usb_config *setup_start;
791 int ret = ENXIO;
792 struct urtw_softc *sc = device_get_softc(dev);
793 struct usb_attach_arg *uaa = device_get_ivars(dev);
794 struct ieee80211com *ic = &sc->sc_ic;
795 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */
796 uint16_t n_setup;
797 uint32_t data;
798 usb_error_t error;
799
800 device_set_usb_desc(dev);
801
802 sc->sc_dev = dev;
803 sc->sc_udev = uaa->device;
804 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
805 sc->sc_flags |= URTW_RTL8187B;
806 #ifdef URTW_DEBUG
807 sc->sc_debug = urtw_debug;
808 #endif
809
810 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
811 MTX_DEF);
812 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
813 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
814 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc);
815 callout_init(&sc->sc_watchdog_ch, 0);
816 mbufq_init(&sc->sc_snd, ifqmaxlen);
817
818 if (sc->sc_flags & URTW_RTL8187B) {
819 setup_start = urtw_8187b_usbconfig;
820 n_setup = URTW_8187B_N_XFERS;
821 } else {
822 setup_start = urtw_8187l_usbconfig;
823 n_setup = URTW_8187L_N_XFERS;
824 }
825
826 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
827 setup_start, n_setup, sc, &sc->sc_mtx);
828 if (error) {
829 device_printf(dev, "could not allocate USB transfers, "
830 "err=%s\n", usbd_errstr(error));
831 ret = ENXIO;
832 goto fail0;
833 }
834
835 if (sc->sc_flags & URTW_RTL8187B) {
836 sc->sc_tx_dma_buf =
837 usbd_xfer_get_frame_buffer(sc->sc_xfer[
838 URTW_8187B_BULK_TX_BE], 0);
839 } else {
840 sc->sc_tx_dma_buf =
841 usbd_xfer_get_frame_buffer(sc->sc_xfer[
842 URTW_8187L_BULK_TX_LOW], 0);
843 }
844
845 URTW_LOCK(sc);
846
847 urtw_read32_m(sc, URTW_RX, &data);
848 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
849 URTW_EEPROM_93C46;
850
851 error = urtw_get_rfchip(sc);
852 if (error != 0)
853 goto fail;
854 error = urtw_get_macaddr(sc);
855 if (error != 0)
856 goto fail;
857 error = urtw_get_txpwr(sc);
858 if (error != 0)
859 goto fail;
860 error = urtw_led_init(sc);
861 if (error != 0)
862 goto fail;
863
864 URTW_UNLOCK(sc);
865
866 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
867 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
868 sc->sc_currate = URTW_RIDX_CCK11;
869 sc->sc_preamble_mode = urtw_preamble_mode;
870
871 ic->ic_softc = sc;
872 ic->ic_name = device_get_nameunit(dev);
873 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
874 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
875
876 /* set device capabilities */
877 ic->ic_caps =
878 IEEE80211_C_STA | /* station mode */
879 IEEE80211_C_MONITOR | /* monitor mode supported */
880 IEEE80211_C_TXPMGT | /* tx power management */
881 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
882 IEEE80211_C_SHSLOT | /* short slot time supported */
883 IEEE80211_C_BGSCAN | /* capable of bg scanning */
884 IEEE80211_C_WPA; /* 802.11i */
885
886 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/
887
888 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
889 ic->ic_channels);
890
891 ieee80211_ifattach(ic);
892 ic->ic_raw_xmit = urtw_raw_xmit;
893 ic->ic_scan_start = urtw_scan_start;
894 ic->ic_scan_end = urtw_scan_end;
895 ic->ic_getradiocaps = urtw_getradiocaps;
896 ic->ic_set_channel = urtw_set_channel;
897 ic->ic_updateslot = urtw_updateslot;
898 ic->ic_vap_create = urtw_vap_create;
899 ic->ic_vap_delete = urtw_vap_delete;
900 ic->ic_update_promisc = urtw_update_promisc;
901 ic->ic_update_mcast = urtw_update_mcast;
902 ic->ic_parent = urtw_parent;
903 ic->ic_transmit = urtw_transmit;
904
905 ieee80211_radiotap_attach(ic,
906 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
907 URTW_TX_RADIOTAP_PRESENT,
908 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
909 URTW_RX_RADIOTAP_PRESENT);
910
911 urtw_sysctl_node(sc);
912
913 if (bootverbose)
914 ieee80211_announce(ic);
915 return (0);
916
917 fail:
918 URTW_UNLOCK(sc);
919 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
920 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
921 fail0:
922 return (ret);
923 }
924
925 static int
urtw_detach(device_t dev)926 urtw_detach(device_t dev)
927 {
928 struct urtw_softc *sc = device_get_softc(dev);
929 struct ieee80211com *ic = &sc->sc_ic;
930 unsigned x;
931 unsigned n_xfers;
932
933 /* Prevent further ioctls */
934 URTW_LOCK(sc);
935 sc->sc_flags |= URTW_DETACHED;
936 urtw_stop(sc);
937 URTW_UNLOCK(sc);
938
939 ieee80211_draintask(ic, &sc->sc_updateslot_task);
940 ieee80211_draintask(ic, &sc->sc_led_task);
941
942 usb_callout_drain(&sc->sc_led_ch);
943 callout_drain(&sc->sc_watchdog_ch);
944
945 n_xfers = (sc->sc_flags & URTW_RTL8187B) ?
946 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS;
947
948 /* prevent further allocations from RX/TX data lists */
949 URTW_LOCK(sc);
950 STAILQ_INIT(&sc->sc_tx_active);
951 STAILQ_INIT(&sc->sc_tx_inactive);
952 STAILQ_INIT(&sc->sc_tx_pending);
953
954 STAILQ_INIT(&sc->sc_rx_active);
955 STAILQ_INIT(&sc->sc_rx_inactive);
956 URTW_UNLOCK(sc);
957
958 /* drain USB transfers */
959 for (x = 0; x != n_xfers; x++)
960 usbd_transfer_drain(sc->sc_xfer[x]);
961
962 /* free data buffers */
963 URTW_LOCK(sc);
964 urtw_free_tx_data_list(sc);
965 urtw_free_rx_data_list(sc);
966 URTW_UNLOCK(sc);
967
968 /* free USB transfers and some data buffers */
969 usbd_transfer_unsetup(sc->sc_xfer, n_xfers);
970
971 ieee80211_ifdetach(ic);
972 mbufq_drain(&sc->sc_snd);
973 mtx_destroy(&sc->sc_mtx);
974 return (0);
975 }
976
977 static void
urtw_free_tx_data_list(struct urtw_softc * sc)978 urtw_free_tx_data_list(struct urtw_softc *sc)
979 {
980 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
981 }
982
983 static void
urtw_free_rx_data_list(struct urtw_softc * sc)984 urtw_free_rx_data_list(struct urtw_softc *sc)
985 {
986 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
987 }
988
989 static void
urtw_free_data_list(struct urtw_softc * sc,struct urtw_data data[],int ndata,int fillmbuf)990 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
991 int fillmbuf)
992 {
993 int i;
994
995 for (i = 0; i < ndata; i++) {
996 struct urtw_data *dp = &data[i];
997
998 if (fillmbuf == 1) {
999 if (dp->m != NULL) {
1000 m_freem(dp->m);
1001 dp->m = NULL;
1002 dp->buf = NULL;
1003 }
1004 } else {
1005 dp->buf = NULL;
1006 }
1007 if (dp->ni != NULL) {
1008 ieee80211_free_node(dp->ni);
1009 dp->ni = NULL;
1010 }
1011 }
1012 }
1013
1014 static struct ieee80211vap *
urtw_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])1015 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1016 enum ieee80211_opmode opmode, int flags,
1017 const uint8_t bssid[IEEE80211_ADDR_LEN],
1018 const uint8_t mac[IEEE80211_ADDR_LEN])
1019 {
1020 struct urtw_vap *uvp;
1021 struct ieee80211vap *vap;
1022
1023 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1024 return (NULL);
1025 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1026 vap = &uvp->vap;
1027 /* enable s/w bmiss handling for sta mode */
1028
1029 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
1030 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
1031 /* out of memory */
1032 free(uvp, M_80211_VAP);
1033 return (NULL);
1034 }
1035
1036 /* override state transition machine */
1037 uvp->newstate = vap->iv_newstate;
1038 vap->iv_newstate = urtw_newstate;
1039
1040 /* complete setup */
1041 ieee80211_vap_attach(vap, ieee80211_media_change,
1042 ieee80211_media_status, mac);
1043 ic->ic_opmode = opmode;
1044 return (vap);
1045 }
1046
1047 static void
urtw_vap_delete(struct ieee80211vap * vap)1048 urtw_vap_delete(struct ieee80211vap *vap)
1049 {
1050 struct urtw_vap *uvp = URTW_VAP(vap);
1051
1052 ieee80211_vap_detach(vap);
1053 free(uvp, M_80211_VAP);
1054 }
1055
1056 static void
urtw_init(struct urtw_softc * sc)1057 urtw_init(struct urtw_softc *sc)
1058 {
1059 usb_error_t error;
1060 int ret;
1061
1062 URTW_ASSERT_LOCKED(sc);
1063
1064 if (sc->sc_flags & URTW_RUNNING)
1065 urtw_stop(sc);
1066
1067 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
1068 urtw_adapter_start(sc);
1069 if (error != 0)
1070 goto fail;
1071
1072 /* reset softc variables */
1073 sc->sc_txtimer = 0;
1074
1075 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1076 ret = urtw_alloc_rx_data_list(sc);
1077 if (ret != 0)
1078 goto fail;
1079 ret = urtw_alloc_tx_data_list(sc);
1080 if (ret != 0)
1081 goto fail;
1082 sc->sc_flags |= URTW_INIT_ONCE;
1083 }
1084
1085 error = urtw_rx_enable(sc);
1086 if (error != 0)
1087 goto fail;
1088 error = urtw_tx_enable(sc);
1089 if (error != 0)
1090 goto fail;
1091
1092 if (sc->sc_flags & URTW_RTL8187B)
1093 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]);
1094
1095 sc->sc_flags |= URTW_RUNNING;
1096
1097 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1098 fail:
1099 return;
1100 }
1101
1102 static usb_error_t
urtw_adapter_start_b(struct urtw_softc * sc)1103 urtw_adapter_start_b(struct urtw_softc *sc)
1104 {
1105 uint8_t data8;
1106 usb_error_t error;
1107
1108 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1109 if (error)
1110 goto fail;
1111
1112 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1113 urtw_write8_m(sc, URTW_CONFIG3,
1114 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1115 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1116 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1117 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1118
1119 urtw_write8_m(sc, 0x61, 0x10);
1120 urtw_read8_m(sc, 0x62, &data8);
1121 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1122 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1123
1124 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1125 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1126 urtw_write8_m(sc, URTW_CONFIG3, data8);
1127
1128 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1129 if (error)
1130 goto fail;
1131
1132 error = urtw_8187b_cmd_reset(sc);
1133 if (error)
1134 goto fail;
1135
1136 error = sc->sc_rf_init(sc);
1137 if (error != 0)
1138 goto fail;
1139 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1140
1141 /* fix RTL8187B RX stall */
1142 error = urtw_intr_enable(sc);
1143 if (error)
1144 goto fail;
1145
1146 error = urtw_write8e(sc, 0x41, 0xf4);
1147 if (error)
1148 goto fail;
1149 error = urtw_write8e(sc, 0x40, 0x00);
1150 if (error)
1151 goto fail;
1152 error = urtw_write8e(sc, 0x42, 0x00);
1153 if (error)
1154 goto fail;
1155 error = urtw_write8e(sc, 0x42, 0x01);
1156 if (error)
1157 goto fail;
1158 error = urtw_write8e(sc, 0x40, 0x0f);
1159 if (error)
1160 goto fail;
1161 error = urtw_write8e(sc, 0x42, 0x00);
1162 if (error)
1163 goto fail;
1164 error = urtw_write8e(sc, 0x42, 0x01);
1165 if (error)
1166 goto fail;
1167
1168 urtw_read8_m(sc, 0xdb, &data8);
1169 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1170 urtw_write16_m(sc, 0x372, 0x59fa);
1171 urtw_write16_m(sc, 0x374, 0x59d2);
1172 urtw_write16_m(sc, 0x376, 0x59d2);
1173 urtw_write16_m(sc, 0x378, 0x19fa);
1174 urtw_write16_m(sc, 0x37a, 0x19fa);
1175 urtw_write16_m(sc, 0x37c, 0x00d0);
1176 urtw_write8_m(sc, 0x61, 0);
1177
1178 urtw_write8_m(sc, 0x180, 0x0f);
1179 urtw_write8_m(sc, 0x183, 0x03);
1180 urtw_write8_m(sc, 0xda, 0x10);
1181 urtw_write8_m(sc, 0x24d, 0x08);
1182 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
1183
1184 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */
1185 fail:
1186 return (error);
1187 }
1188
1189 static usb_error_t
urtw_set_macaddr(struct urtw_softc * sc,const uint8_t * macaddr)1190 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *macaddr)
1191 {
1192 usb_error_t error;
1193
1194 urtw_write32_m(sc, URTW_MAC0, ((const uint32_t *)macaddr)[0]);
1195 urtw_write16_m(sc, URTW_MAC4, ((const uint32_t *)macaddr)[1] & 0xffff);
1196
1197 fail:
1198 return (error);
1199 }
1200
1201 static usb_error_t
urtw_adapter_start(struct urtw_softc * sc)1202 urtw_adapter_start(struct urtw_softc *sc)
1203 {
1204 struct ieee80211com *ic = &sc->sc_ic;
1205 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1206 const uint8_t *macaddr;
1207 usb_error_t error;
1208
1209 error = urtw_reset(sc);
1210 if (error)
1211 goto fail;
1212
1213 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1214 urtw_write8_m(sc, URTW_GPIO, 0);
1215
1216 /* for led */
1217 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1218 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1219 if (error != 0)
1220 goto fail;
1221
1222 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1223 if (error)
1224 goto fail;
1225 /* applying MAC address again. */
1226 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
1227 urtw_set_macaddr(sc, macaddr);
1228 if (error)
1229 goto fail;
1230
1231 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1232 if (error)
1233 goto fail;
1234
1235 error = urtw_update_msr(sc);
1236 if (error)
1237 goto fail;
1238
1239 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1240 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1241 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1242 error = urtw_set_rate(sc);
1243 if (error != 0)
1244 goto fail;
1245
1246 error = sc->sc_rf_init(sc);
1247 if (error != 0)
1248 goto fail;
1249 if (sc->sc_rf_set_sens != NULL)
1250 sc->sc_rf_set_sens(sc, sc->sc_sens);
1251
1252 /* XXX correct? to call write16 */
1253 urtw_write16_m(sc, URTW_PSR, 1);
1254 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1255 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1256 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1257 /* XXX correct? to call write16 */
1258 urtw_write16_m(sc, URTW_PSR, 0);
1259 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1260
1261 error = urtw_intr_enable(sc);
1262 if (error != 0)
1263 goto fail;
1264
1265 fail:
1266 return (error);
1267 }
1268
1269 static usb_error_t
urtw_set_mode(struct urtw_softc * sc,uint32_t mode)1270 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1271 {
1272 uint8_t data;
1273 usb_error_t error;
1274
1275 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1276 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1277 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1278 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1279 fail:
1280 return (error);
1281 }
1282
1283 static void
urtw_pause_ms(struct urtw_softc * sc,int delay)1284 urtw_pause_ms(struct urtw_softc *sc, int delay)
1285 {
1286 usb_pause_mtx(&sc->sc_mtx, USB_MS_TO_TICKS(delay));
1287 }
1288
1289 static usb_error_t
urtw_8187b_cmd_reset(struct urtw_softc * sc)1290 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1291 {
1292 int i;
1293 uint8_t data8;
1294 usb_error_t error;
1295
1296 /* XXX the code can be duplicate with urtw_reset(). */
1297 urtw_read8_m(sc, URTW_CMD, &data8);
1298 data8 = (data8 & 0x2) | URTW_CMD_RST;
1299 urtw_write8_m(sc, URTW_CMD, data8);
1300
1301 for (i = 0; i < 20; i++) {
1302 urtw_pause_ms(sc, 2);
1303 urtw_read8_m(sc, URTW_CMD, &data8);
1304 if (!(data8 & URTW_CMD_RST))
1305 break;
1306 }
1307 if (i >= 20) {
1308 device_printf(sc->sc_dev, "reset timeout\n");
1309 goto fail;
1310 }
1311 fail:
1312 return (error);
1313 }
1314
1315 static usb_error_t
urtw_do_request(struct urtw_softc * sc,struct usb_device_request * req,void * data)1316 urtw_do_request(struct urtw_softc *sc,
1317 struct usb_device_request *req, void *data)
1318 {
1319 usb_error_t err;
1320 int ntries = 10;
1321
1322 URTW_ASSERT_LOCKED(sc);
1323
1324 while (ntries--) {
1325 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1326 req, data, 0, NULL, 250 /* ms */);
1327 if (err == 0)
1328 break;
1329
1330 DPRINTF(sc, URTW_DEBUG_INIT,
1331 "Control request failed, %s (retrying)\n",
1332 usbd_errstr(err));
1333 urtw_pause_ms(sc, 10);
1334 }
1335 return (err);
1336 }
1337
1338 static void
urtw_stop(struct urtw_softc * sc)1339 urtw_stop(struct urtw_softc *sc)
1340 {
1341 uint8_t data8;
1342 usb_error_t error;
1343
1344 URTW_ASSERT_LOCKED(sc);
1345
1346 sc->sc_flags &= ~URTW_RUNNING;
1347
1348 error = urtw_intr_disable(sc);
1349 if (error)
1350 goto fail;
1351 urtw_read8_m(sc, URTW_CMD, &data8);
1352 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1353 urtw_write8_m(sc, URTW_CMD, data8);
1354
1355 error = sc->sc_rf_stop(sc);
1356 if (error != 0)
1357 goto fail;
1358
1359 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1360 if (error)
1361 goto fail;
1362 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1363 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1364 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1365 if (error)
1366 goto fail;
1367 fail:
1368 if (error)
1369 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1370 usbd_errstr(error));
1371
1372 usb_callout_stop(&sc->sc_led_ch);
1373 callout_stop(&sc->sc_watchdog_ch);
1374
1375 urtw_abort_xfers(sc);
1376 }
1377
1378 static void
urtw_abort_xfers(struct urtw_softc * sc)1379 urtw_abort_xfers(struct urtw_softc *sc)
1380 {
1381 int i, max;
1382
1383 URTW_ASSERT_LOCKED(sc);
1384
1385 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1386 URTW_8187L_N_XFERS;
1387
1388 /* abort any pending transfers */
1389 for (i = 0; i < max; i++)
1390 usbd_transfer_stop(sc->sc_xfer[i]);
1391 }
1392
1393 static void
urtw_parent(struct ieee80211com * ic)1394 urtw_parent(struct ieee80211com *ic)
1395 {
1396 struct urtw_softc *sc = ic->ic_softc;
1397 int startall = 0;
1398
1399 URTW_LOCK(sc);
1400 if (sc->sc_flags & URTW_DETACHED) {
1401 URTW_UNLOCK(sc);
1402 return;
1403 }
1404
1405 if (ic->ic_nrunning > 0) {
1406 if (sc->sc_flags & URTW_RUNNING) {
1407 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0)
1408 urtw_set_multi(sc);
1409 } else {
1410 urtw_init(sc);
1411 startall = 1;
1412 }
1413 } else if (sc->sc_flags & URTW_RUNNING)
1414 urtw_stop(sc);
1415 URTW_UNLOCK(sc);
1416 if (startall)
1417 ieee80211_start_all(ic);
1418 }
1419
1420 static int
urtw_transmit(struct ieee80211com * ic,struct mbuf * m)1421 urtw_transmit(struct ieee80211com *ic, struct mbuf *m)
1422 {
1423 struct urtw_softc *sc = ic->ic_softc;
1424 int error;
1425
1426 URTW_LOCK(sc);
1427 if ((sc->sc_flags & URTW_RUNNING) == 0) {
1428 URTW_UNLOCK(sc);
1429 return (ENXIO);
1430 }
1431 error = mbufq_enqueue(&sc->sc_snd, m);
1432 if (error) {
1433 URTW_UNLOCK(sc);
1434 return (error);
1435 }
1436 urtw_start(sc);
1437 URTW_UNLOCK(sc);
1438
1439 return (0);
1440 }
1441
1442 static void
urtw_start(struct urtw_softc * sc)1443 urtw_start(struct urtw_softc *sc)
1444 {
1445 struct urtw_data *bf;
1446 struct ieee80211_node *ni;
1447 struct mbuf *m;
1448
1449 URTW_ASSERT_LOCKED(sc);
1450
1451 if ((sc->sc_flags & URTW_RUNNING) == 0)
1452 return;
1453
1454 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1455 bf = urtw_getbuf(sc);
1456 if (bf == NULL) {
1457 mbufq_prepend(&sc->sc_snd, m);
1458 break;
1459 }
1460
1461 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1462 m->m_pkthdr.rcvif = NULL;
1463
1464 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1465 if_inc_counter(ni->ni_vap->iv_ifp,
1466 IFCOUNTER_OERRORS, 1);
1467 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1468 ieee80211_free_node(ni);
1469 break;
1470 }
1471
1472 sc->sc_txtimer = 5;
1473 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1474 }
1475 }
1476
1477 static int
urtw_alloc_data_list(struct urtw_softc * sc,struct urtw_data data[],int ndata,int maxsz,void * dma_buf)1478 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1479 int ndata, int maxsz, void *dma_buf)
1480 {
1481 int i, error;
1482
1483 for (i = 0; i < ndata; i++) {
1484 struct urtw_data *dp = &data[i];
1485
1486 dp->sc = sc;
1487 if (dma_buf == NULL) {
1488 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1489 if (dp->m == NULL) {
1490 device_printf(sc->sc_dev,
1491 "could not allocate rx mbuf\n");
1492 error = ENOMEM;
1493 goto fail;
1494 }
1495 dp->buf = mtod(dp->m, uint8_t *);
1496 } else {
1497 dp->m = NULL;
1498 dp->buf = ((uint8_t *)dma_buf) +
1499 (i * maxsz);
1500 }
1501 dp->ni = NULL;
1502 }
1503 return (0);
1504
1505 fail: urtw_free_data_list(sc, data, ndata, 1);
1506 return (error);
1507 }
1508
1509 static int
urtw_alloc_rx_data_list(struct urtw_softc * sc)1510 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1511 {
1512 int error, i;
1513
1514 error = urtw_alloc_data_list(sc,
1515 sc->sc_rx, URTW_RX_DATA_LIST_COUNT,
1516 MCLBYTES, NULL /* mbufs */);
1517 if (error != 0)
1518 return (error);
1519
1520 STAILQ_INIT(&sc->sc_rx_active);
1521 STAILQ_INIT(&sc->sc_rx_inactive);
1522
1523 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1524 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1525
1526 return (0);
1527 }
1528
1529 static int
urtw_alloc_tx_data_list(struct urtw_softc * sc)1530 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1531 {
1532 int error, i;
1533
1534 error = urtw_alloc_data_list(sc,
1535 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1536 sc->sc_tx_dma_buf /* no mbufs */);
1537 if (error != 0)
1538 return (error);
1539
1540 STAILQ_INIT(&sc->sc_tx_active);
1541 STAILQ_INIT(&sc->sc_tx_inactive);
1542 STAILQ_INIT(&sc->sc_tx_pending);
1543
1544 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1545 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1546 next);
1547
1548 return (0);
1549 }
1550
1551 static int
urtw_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1552 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1553 const struct ieee80211_bpf_params *params)
1554 {
1555 struct ieee80211com *ic = ni->ni_ic;
1556 struct urtw_softc *sc = ic->ic_softc;
1557 struct urtw_data *bf;
1558
1559 /* prevent management frames from being sent if we're not ready */
1560 if (!(sc->sc_flags & URTW_RUNNING)) {
1561 m_freem(m);
1562 return ENETDOWN;
1563 }
1564 URTW_LOCK(sc);
1565 bf = urtw_getbuf(sc);
1566 if (bf == NULL) {
1567 m_freem(m);
1568 URTW_UNLOCK(sc);
1569 return (ENOBUFS); /* XXX */
1570 }
1571
1572 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1573 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1574 URTW_UNLOCK(sc);
1575 return (EIO);
1576 }
1577 URTW_UNLOCK(sc);
1578
1579 sc->sc_txtimer = 5;
1580 return (0);
1581 }
1582
1583 static void
urtw_scan_start(struct ieee80211com * ic)1584 urtw_scan_start(struct ieee80211com *ic)
1585 {
1586
1587 /* XXX do nothing? */
1588 }
1589
1590 static void
urtw_scan_end(struct ieee80211com * ic)1591 urtw_scan_end(struct ieee80211com *ic)
1592 {
1593
1594 /* XXX do nothing? */
1595 }
1596
1597 static void
urtw_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1598 urtw_getradiocaps(struct ieee80211com *ic,
1599 int maxchans, int *nchans, struct ieee80211_channel chans[])
1600 {
1601 uint8_t bands[IEEE80211_MODE_BYTES];
1602
1603 memset(bands, 0, sizeof(bands));
1604 setbit(bands, IEEE80211_MODE_11B);
1605 setbit(bands, IEEE80211_MODE_11G);
1606 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1607 }
1608
1609 static void
urtw_set_channel(struct ieee80211com * ic)1610 urtw_set_channel(struct ieee80211com *ic)
1611 {
1612 struct urtw_softc *sc = ic->ic_softc;
1613 uint32_t data, orig;
1614 usb_error_t error;
1615
1616 /*
1617 * if the user set a channel explicitly using ifconfig(8) this function
1618 * can be called earlier than we're expected that in some cases the
1619 * initialization would be failed if setting a channel is called before
1620 * the init have done.
1621 */
1622 if (!(sc->sc_flags & URTW_RUNNING))
1623 return;
1624
1625 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1626 return;
1627
1628 URTW_LOCK(sc);
1629
1630 /*
1631 * during changing th channel we need to temporarily be disable
1632 * TX.
1633 */
1634 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1635 data = orig & ~URTW_TX_LOOPBACK_MASK;
1636 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1637
1638 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1639 if (error != 0)
1640 goto fail;
1641 urtw_pause_ms(sc, 10);
1642 urtw_write32_m(sc, URTW_TX_CONF, orig);
1643
1644 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1645 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1646 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1647 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1648
1649 fail:
1650 URTW_UNLOCK(sc);
1651
1652 sc->sc_curchan = ic->ic_curchan;
1653
1654 if (error != 0)
1655 device_printf(sc->sc_dev, "could not change the channel\n");
1656 }
1657
1658 static void
urtw_update_promisc(struct ieee80211com * ic)1659 urtw_update_promisc(struct ieee80211com *ic)
1660 {
1661 struct urtw_softc *sc = ic->ic_softc;
1662
1663 URTW_LOCK(sc);
1664 if (sc->sc_flags & URTW_RUNNING)
1665 urtw_rx_setconf(sc);
1666 URTW_UNLOCK(sc);
1667 }
1668
1669 static void
urtw_update_mcast(struct ieee80211com * ic)1670 urtw_update_mcast(struct ieee80211com *ic)
1671 {
1672
1673 /* XXX do nothing? */
1674 }
1675
1676 static int
urtw_tx_start(struct urtw_softc * sc,struct ieee80211_node * ni,struct mbuf * m0,struct urtw_data * data,int prior)1677 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1678 struct urtw_data *data, int prior)
1679 {
1680 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1681 struct ieee80211_key *k;
1682 const struct ieee80211_txparam *tp = ni->ni_txparms;
1683 struct ieee80211com *ic = &sc->sc_ic;
1684 struct ieee80211vap *vap = ni->ni_vap;
1685 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1686 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1687 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1688 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1689 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1690 };
1691 struct usb_xfer *xfer;
1692 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type,
1693 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast;
1694 uint16_t acktime, rtstime, ctstime;
1695 uint32_t flags;
1696 usb_error_t error;
1697
1698 URTW_ASSERT_LOCKED(sc);
1699
1700 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1701 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1702
1703 /*
1704 * Software crypto.
1705 */
1706 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1707 k = ieee80211_crypto_encap(ni, m0);
1708 if (k == NULL) {
1709 device_printf(sc->sc_dev,
1710 "ieee80211_crypto_encap returns NULL.\n");
1711 /* XXX we don't expect the fragmented frames */
1712 m_freem(m0);
1713 return (ENOBUFS);
1714 }
1715
1716 /* in case packet header moved, reset pointer */
1717 wh = mtod(m0, struct ieee80211_frame *);
1718 }
1719
1720 if (ieee80211_radiotap_active_vap(vap)) {
1721 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1722
1723 tap->wt_flags = 0;
1724 ieee80211_radiotap_tx(vap, m0);
1725 }
1726
1727 if (IEEE80211_IS_MGMT(wh) || IEEE80211_IS_CTL(wh) ||
1728 (m0->m_flags & M_EAPOL) != 0) {
1729 rate = tp->mgmtrate;
1730 } else {
1731 /* for data frames */
1732 if (ismcast)
1733 rate = tp->mcastrate;
1734 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1735 rate = tp->ucastrate;
1736 else
1737 rate = urtw_rtl2rate(sc->sc_currate);
1738 }
1739
1740 sc->sc_stats.txrates[sc->sc_currate]++;
1741
1742 if (ismcast)
1743 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1744 IEEE80211_CRC_LEN, rate, 0, 0);
1745 else {
1746 acktime = urtw_compute_txtime(14, 2,0, 0);
1747 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1748 rtsenable = 1;
1749 ctsenable = 0;
1750 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1751 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1752 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1753 IEEE80211_CRC_LEN, rate, 0, isshort);
1754 rtsdur = ctstime + pkttime + acktime +
1755 3 * URTW_ASIFS_TIME;
1756 txdur = rtstime + rtsdur;
1757 } else {
1758 rtsenable = ctsenable = rtsdur = 0;
1759 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1760 IEEE80211_CRC_LEN, rate, 0, isshort);
1761 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1762 }
1763
1764 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1765 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1766 IEEE80211_CRC_LEN, rate, 0, isshort) +
1767 3 * URTW_ASIFS_TIME +
1768 2 * acktime;
1769 else
1770 dur = URTW_ASIFS_TIME + acktime;
1771 }
1772 USETW(wh->i_dur, dur);
1773
1774 xferlen = m0->m_pkthdr.len;
1775 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1776 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1777 xferlen += 1;
1778
1779 memset(data->buf, 0, URTW_TX_MAXSIZE);
1780 flags = m0->m_pkthdr.len & 0xfff;
1781 flags |= URTW_TX_FLAG_NO_ENC;
1782 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1783 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1784 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1785 (sc->sc_currate != 0))
1786 flags |= URTW_TX_FLAG_SPLCP;
1787 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1788 flags |= URTW_TX_FLAG_MOREFRAG;
1789
1790 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1791
1792 if (sc->sc_flags & URTW_RTL8187B) {
1793 struct urtw_8187b_txhdr *tx;
1794
1795 tx = (struct urtw_8187b_txhdr *)data->buf;
1796 if (ctsenable)
1797 flags |= URTW_TX_FLAG_CTS;
1798 if (rtsenable) {
1799 flags |= URTW_TX_FLAG_RTS;
1800 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT;
1801 tx->rtsdur = rtsdur;
1802 }
1803 tx->flag = htole32(flags);
1804 tx->txdur = txdur;
1805 if (IEEE80211_IS_MGMT_PROBE_RESP(wh))
1806 tx->retry = 1;
1807 else
1808 tx->retry = URTW_TX_MAXRETRY;
1809 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1810 } else {
1811 struct urtw_8187l_txhdr *tx;
1812
1813 tx = (struct urtw_8187l_txhdr *)data->buf;
1814 if (rtsenable) {
1815 flags |= URTW_TX_FLAG_RTS;
1816 tx->rtsdur = rtsdur;
1817 }
1818 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT;
1819 tx->flag = htole32(flags);
1820 tx->retry = 3; /* CW minimum */
1821 tx->retry |= 7 << 4; /* CW maximum */
1822 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */
1823 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1824 }
1825
1826 data->buflen = xferlen;
1827 data->ni = ni;
1828 data->m = m0;
1829
1830 if (sc->sc_flags & URTW_RTL8187B) {
1831 switch (type) {
1832 case IEEE80211_FC0_TYPE_CTL:
1833 case IEEE80211_FC0_TYPE_MGT:
1834 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1835 break;
1836 default:
1837 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1838 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1839 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1840 break;
1841 }
1842 } else
1843 xfer = (prior == URTW_PRIORITY_LOW) ?
1844 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1845 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1846
1847 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1848 usbd_transfer_start(xfer);
1849
1850 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1851 if (error != 0)
1852 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1853 error);
1854 return (0);
1855 }
1856
1857 static int
urtw_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1858 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1859 {
1860 struct ieee80211com *ic = vap->iv_ic;
1861 struct urtw_softc *sc = ic->ic_softc;
1862 struct urtw_vap *uvp = URTW_VAP(vap);
1863 struct ieee80211_node *ni;
1864 usb_error_t error = 0;
1865
1866 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1867 ieee80211_state_name[vap->iv_state],
1868 ieee80211_state_name[nstate]);
1869
1870 sc->sc_state = nstate;
1871
1872 IEEE80211_UNLOCK(ic);
1873 URTW_LOCK(sc);
1874 usb_callout_stop(&sc->sc_led_ch);
1875 callout_stop(&sc->sc_watchdog_ch);
1876
1877 switch (nstate) {
1878 case IEEE80211_S_INIT:
1879 case IEEE80211_S_SCAN:
1880 case IEEE80211_S_AUTH:
1881 case IEEE80211_S_ASSOC:
1882 break;
1883 case IEEE80211_S_RUN:
1884 ni = ieee80211_ref_node(vap->iv_bss);
1885 /* setting bssid. */
1886 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1887 urtw_write16_m(sc, URTW_BSSID + 4,
1888 ((uint16_t *)ni->ni_bssid)[2]);
1889 urtw_update_msr(sc);
1890 /* XXX maybe the below would be incorrect. */
1891 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1892 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1893 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1894 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1895 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1896 if (error != 0)
1897 device_printf(sc->sc_dev,
1898 "could not control LED (%d)\n", error);
1899 ieee80211_free_node(ni);
1900 break;
1901 default:
1902 break;
1903 }
1904 fail:
1905 URTW_UNLOCK(sc);
1906 IEEE80211_LOCK(ic);
1907 return (uvp->newstate(vap, nstate, arg));
1908 }
1909
1910 static void
urtw_watchdog(void * arg)1911 urtw_watchdog(void *arg)
1912 {
1913 struct urtw_softc *sc = arg;
1914 struct ieee80211com *ic = &sc->sc_ic;
1915
1916 if (sc->sc_txtimer > 0) {
1917 if (--sc->sc_txtimer == 0) {
1918 device_printf(sc->sc_dev, "device timeout\n");
1919 counter_u64_add(ic->ic_oerrors, 1);
1920 ieee80211_restart_all(ic);
1921 return;
1922 }
1923 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1924 }
1925 }
1926
1927 static void
urtw_set_multi(void * arg)1928 urtw_set_multi(void *arg)
1929 {
1930 /* XXX don't know how to set a device. Lack of docs. */
1931 }
1932
1933 static usb_error_t
urtw_set_rate(struct urtw_softc * sc)1934 urtw_set_rate(struct urtw_softc *sc)
1935 {
1936 int i, basic_rate, min_rr_rate, max_rr_rate;
1937 uint16_t data;
1938 usb_error_t error;
1939
1940 basic_rate = URTW_RIDX_OFDM24;
1941 min_rr_rate = URTW_RIDX_OFDM6;
1942 max_rr_rate = URTW_RIDX_OFDM24;
1943
1944 urtw_write8_m(sc, URTW_RESP_RATE,
1945 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1946 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1947
1948 urtw_read16_m(sc, URTW_BRSR, &data);
1949 data &= ~URTW_BRSR_MBR_8185;
1950
1951 for (i = 0; i <= basic_rate; i++)
1952 data |= (1 << i);
1953
1954 urtw_write16_m(sc, URTW_BRSR, data);
1955 fail:
1956 return (error);
1957 }
1958
1959 static uint16_t
urtw_rtl2rate(uint32_t rate)1960 urtw_rtl2rate(uint32_t rate)
1961 {
1962 unsigned i;
1963
1964 for (i = 0; i < nitems(urtw_ratetable); i++) {
1965 if (rate == urtw_ratetable[i].val)
1966 return urtw_ratetable[i].reg;
1967 }
1968
1969 return (0);
1970 }
1971
1972 static usb_error_t
urtw_update_msr(struct urtw_softc * sc)1973 urtw_update_msr(struct urtw_softc *sc)
1974 {
1975 struct ieee80211com *ic = &sc->sc_ic;
1976 uint8_t data;
1977 usb_error_t error;
1978
1979 urtw_read8_m(sc, URTW_MSR, &data);
1980 data &= ~URTW_MSR_LINK_MASK;
1981
1982 if (sc->sc_state == IEEE80211_S_RUN) {
1983 switch (ic->ic_opmode) {
1984 case IEEE80211_M_STA:
1985 case IEEE80211_M_MONITOR:
1986 data |= URTW_MSR_LINK_STA;
1987 if (sc->sc_flags & URTW_RTL8187B)
1988 data |= URTW_MSR_LINK_ENEDCA;
1989 break;
1990 case IEEE80211_M_IBSS:
1991 data |= URTW_MSR_LINK_ADHOC;
1992 break;
1993 case IEEE80211_M_HOSTAP:
1994 data |= URTW_MSR_LINK_HOSTAP;
1995 break;
1996 default:
1997 DPRINTF(sc, URTW_DEBUG_STATE,
1998 "unsupported operation mode 0x%x\n",
1999 ic->ic_opmode);
2000 error = USB_ERR_INVAL;
2001 goto fail;
2002 }
2003 } else
2004 data |= URTW_MSR_LINK_NONE;
2005
2006 urtw_write8_m(sc, URTW_MSR, data);
2007 fail:
2008 return (error);
2009 }
2010
2011 static usb_error_t
urtw_read8_c(struct urtw_softc * sc,int val,uint8_t * data)2012 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2013 {
2014 struct usb_device_request req;
2015 usb_error_t error;
2016
2017 URTW_ASSERT_LOCKED(sc);
2018
2019 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2020 req.bRequest = URTW_8187_GETREGS_REQ;
2021 USETW(req.wValue, (val & 0xff) | 0xff00);
2022 USETW(req.wIndex, (val >> 8) & 0x3);
2023 USETW(req.wLength, sizeof(uint8_t));
2024
2025 error = urtw_do_request(sc, &req, data);
2026 return (error);
2027 }
2028
2029 static usb_error_t
urtw_read16_c(struct urtw_softc * sc,int val,uint16_t * data)2030 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2031 {
2032 struct usb_device_request req;
2033 usb_error_t error;
2034
2035 URTW_ASSERT_LOCKED(sc);
2036
2037 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2038 req.bRequest = URTW_8187_GETREGS_REQ;
2039 USETW(req.wValue, (val & 0xff) | 0xff00);
2040 USETW(req.wIndex, (val >> 8) & 0x3);
2041 USETW(req.wLength, sizeof(uint16_t));
2042
2043 error = urtw_do_request(sc, &req, data);
2044 return (error);
2045 }
2046
2047 static usb_error_t
urtw_read32_c(struct urtw_softc * sc,int val,uint32_t * data)2048 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2049 {
2050 struct usb_device_request req;
2051 usb_error_t error;
2052
2053 URTW_ASSERT_LOCKED(sc);
2054
2055 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2056 req.bRequest = URTW_8187_GETREGS_REQ;
2057 USETW(req.wValue, (val & 0xff) | 0xff00);
2058 USETW(req.wIndex, (val >> 8) & 0x3);
2059 USETW(req.wLength, sizeof(uint32_t));
2060
2061 error = urtw_do_request(sc, &req, data);
2062 return (error);
2063 }
2064
2065 static usb_error_t
urtw_write8_c(struct urtw_softc * sc,int val,uint8_t data)2066 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2067 {
2068 struct usb_device_request req;
2069
2070 URTW_ASSERT_LOCKED(sc);
2071
2072 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2073 req.bRequest = URTW_8187_SETREGS_REQ;
2074 USETW(req.wValue, (val & 0xff) | 0xff00);
2075 USETW(req.wIndex, (val >> 8) & 0x3);
2076 USETW(req.wLength, sizeof(uint8_t));
2077
2078 return (urtw_do_request(sc, &req, &data));
2079 }
2080
2081 static usb_error_t
urtw_write16_c(struct urtw_softc * sc,int val,uint16_t data)2082 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2083 {
2084 struct usb_device_request req;
2085
2086 URTW_ASSERT_LOCKED(sc);
2087
2088 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2089 req.bRequest = URTW_8187_SETREGS_REQ;
2090 USETW(req.wValue, (val & 0xff) | 0xff00);
2091 USETW(req.wIndex, (val >> 8) & 0x3);
2092 USETW(req.wLength, sizeof(uint16_t));
2093
2094 return (urtw_do_request(sc, &req, &data));
2095 }
2096
2097 static usb_error_t
urtw_write32_c(struct urtw_softc * sc,int val,uint32_t data)2098 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2099 {
2100 struct usb_device_request req;
2101
2102 URTW_ASSERT_LOCKED(sc);
2103
2104 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2105 req.bRequest = URTW_8187_SETREGS_REQ;
2106 USETW(req.wValue, (val & 0xff) | 0xff00);
2107 USETW(req.wIndex, (val >> 8) & 0x3);
2108 USETW(req.wLength, sizeof(uint32_t));
2109
2110 return (urtw_do_request(sc, &req, &data));
2111 }
2112
2113 static usb_error_t
urtw_get_macaddr(struct urtw_softc * sc)2114 urtw_get_macaddr(struct urtw_softc *sc)
2115 {
2116 struct ieee80211com *ic = &sc->sc_ic;
2117 uint32_t data;
2118 usb_error_t error;
2119
2120 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2121 if (error != 0)
2122 goto fail;
2123 ic->ic_macaddr[0] = data & 0xff;
2124 ic->ic_macaddr[1] = (data & 0xff00) >> 8;
2125 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2126 if (error != 0)
2127 goto fail;
2128 ic->ic_macaddr[2] = data & 0xff;
2129 ic->ic_macaddr[3] = (data & 0xff00) >> 8;
2130 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2131 if (error != 0)
2132 goto fail;
2133 ic->ic_macaddr[4] = data & 0xff;
2134 ic->ic_macaddr[5] = (data & 0xff00) >> 8;
2135 fail:
2136 return (error);
2137 }
2138
2139 static usb_error_t
urtw_eprom_read32(struct urtw_softc * sc,uint32_t addr,uint32_t * data)2140 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2141 {
2142 #define URTW_READCMD_LEN 3
2143 int addrlen, i;
2144 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2145 usb_error_t error;
2146
2147 /* NB: make sure the buffer is initialized */
2148 *data = 0;
2149
2150 /* enable EPROM programming */
2151 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2152 DELAY(URTW_EPROM_DELAY);
2153
2154 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2155 if (error != 0)
2156 goto fail;
2157 error = urtw_eprom_ck(sc);
2158 if (error != 0)
2159 goto fail;
2160 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2161 if (error != 0)
2162 goto fail;
2163 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2164 addrlen = 8;
2165 addrstr[0] = addr & (1 << 7);
2166 addrstr[1] = addr & (1 << 6);
2167 addrstr[2] = addr & (1 << 5);
2168 addrstr[3] = addr & (1 << 4);
2169 addrstr[4] = addr & (1 << 3);
2170 addrstr[5] = addr & (1 << 2);
2171 addrstr[6] = addr & (1 << 1);
2172 addrstr[7] = addr & (1 << 0);
2173 } else {
2174 addrlen=6;
2175 addrstr[0] = addr & (1 << 5);
2176 addrstr[1] = addr & (1 << 4);
2177 addrstr[2] = addr & (1 << 3);
2178 addrstr[3] = addr & (1 << 2);
2179 addrstr[4] = addr & (1 << 1);
2180 addrstr[5] = addr & (1 << 0);
2181 }
2182 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2183 if (error != 0)
2184 goto fail;
2185
2186 error = urtw_eprom_writebit(sc, 0);
2187 if (error != 0)
2188 goto fail;
2189
2190 for (i = 0; i < 16; i++) {
2191 error = urtw_eprom_ck(sc);
2192 if (error != 0)
2193 goto fail;
2194 error = urtw_eprom_readbit(sc, &data16);
2195 if (error != 0)
2196 goto fail;
2197
2198 (*data) |= (data16 << (15 - i));
2199 }
2200
2201 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2202 if (error != 0)
2203 goto fail;
2204 error = urtw_eprom_ck(sc);
2205 if (error != 0)
2206 goto fail;
2207
2208 /* now disable EPROM programming */
2209 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2210 fail:
2211 return (error);
2212 #undef URTW_READCMD_LEN
2213 }
2214
2215 static usb_error_t
urtw_eprom_cs(struct urtw_softc * sc,int able)2216 urtw_eprom_cs(struct urtw_softc *sc, int able)
2217 {
2218 uint8_t data;
2219 usb_error_t error;
2220
2221 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2222 if (able == URTW_EPROM_ENABLE)
2223 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2224 else
2225 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2226 DELAY(URTW_EPROM_DELAY);
2227 fail:
2228 return (error);
2229 }
2230
2231 static usb_error_t
urtw_eprom_ck(struct urtw_softc * sc)2232 urtw_eprom_ck(struct urtw_softc *sc)
2233 {
2234 uint8_t data;
2235 usb_error_t error;
2236
2237 /* masking */
2238 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2239 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2240 DELAY(URTW_EPROM_DELAY);
2241 /* unmasking */
2242 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2243 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2244 DELAY(URTW_EPROM_DELAY);
2245 fail:
2246 return (error);
2247 }
2248
2249 static usb_error_t
urtw_eprom_readbit(struct urtw_softc * sc,int16_t * data)2250 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2251 {
2252 uint8_t data8;
2253 usb_error_t error;
2254
2255 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2256 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2257 DELAY(URTW_EPROM_DELAY);
2258
2259 fail:
2260 return (error);
2261 }
2262
2263 static usb_error_t
urtw_eprom_writebit(struct urtw_softc * sc,int16_t bit)2264 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2265 {
2266 uint8_t data;
2267 usb_error_t error;
2268
2269 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2270 if (bit != 0)
2271 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2272 else
2273 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2274 DELAY(URTW_EPROM_DELAY);
2275 fail:
2276 return (error);
2277 }
2278
2279 static usb_error_t
urtw_eprom_sendbits(struct urtw_softc * sc,int16_t * buf,int buflen)2280 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2281 {
2282 int i = 0;
2283 usb_error_t error = 0;
2284
2285 for (i = 0; i < buflen; i++) {
2286 error = urtw_eprom_writebit(sc, buf[i]);
2287 if (error != 0)
2288 goto fail;
2289 error = urtw_eprom_ck(sc);
2290 if (error != 0)
2291 goto fail;
2292 }
2293 fail:
2294 return (error);
2295 }
2296
2297 static usb_error_t
urtw_get_txpwr(struct urtw_softc * sc)2298 urtw_get_txpwr(struct urtw_softc *sc)
2299 {
2300 int i, j;
2301 uint32_t data;
2302 usb_error_t error;
2303
2304 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2305 if (error != 0)
2306 goto fail;
2307 sc->sc_txpwr_cck_base = data & 0xf;
2308 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2309
2310 for (i = 1, j = 0; i < 6; i += 2, j++) {
2311 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2312 if (error != 0)
2313 goto fail;
2314 sc->sc_txpwr_cck[i] = data & 0xf;
2315 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2316 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2317 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2318 }
2319 for (i = 1, j = 0; i < 4; i += 2, j++) {
2320 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2321 if (error != 0)
2322 goto fail;
2323 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2324 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2325 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2326 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2327 }
2328 if (sc->sc_flags & URTW_RTL8187B) {
2329 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2330 if (error != 0)
2331 goto fail;
2332 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2333 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2334 error = urtw_eprom_read32(sc, 0x0a, &data);
2335 if (error != 0)
2336 goto fail;
2337 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2338 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2339 error = urtw_eprom_read32(sc, 0x1c, &data);
2340 if (error != 0)
2341 goto fail;
2342 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2343 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2344 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2345 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2346 } else {
2347 for (i = 1, j = 0; i < 4; i += 2, j++) {
2348 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2349 &data);
2350 if (error != 0)
2351 goto fail;
2352 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2353 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2354 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2355 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2356 }
2357 }
2358 fail:
2359 return (error);
2360 }
2361
2362 static usb_error_t
urtw_get_rfchip(struct urtw_softc * sc)2363 urtw_get_rfchip(struct urtw_softc *sc)
2364 {
2365 int ret;
2366 uint8_t data8;
2367 uint32_t data;
2368 usb_error_t error;
2369
2370 if (sc->sc_flags & URTW_RTL8187B) {
2371 urtw_read8_m(sc, 0xe1, &data8);
2372 switch (data8) {
2373 case 0:
2374 sc->sc_flags |= URTW_RTL8187B_REV_B;
2375 break;
2376 case 1:
2377 sc->sc_flags |= URTW_RTL8187B_REV_D;
2378 break;
2379 case 2:
2380 sc->sc_flags |= URTW_RTL8187B_REV_E;
2381 break;
2382 default:
2383 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2384 sc->sc_flags |= URTW_RTL8187B_REV_B;
2385 break;
2386 }
2387 } else {
2388 urtw_read32_m(sc, URTW_TX_CONF, &data);
2389 switch (data & URTW_TX_HWMASK) {
2390 case URTW_TX_R8187vD_B:
2391 sc->sc_flags |= URTW_RTL8187B;
2392 break;
2393 case URTW_TX_R8187vD:
2394 break;
2395 default:
2396 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2397 data & URTW_TX_HWMASK);
2398 break;
2399 }
2400 }
2401
2402 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2403 if (error != 0)
2404 goto fail;
2405 switch (data & 0xff) {
2406 case URTW_EPROM_RFCHIPID_RTL8225U:
2407 error = urtw_8225_isv2(sc, &ret);
2408 if (error != 0)
2409 goto fail;
2410 if (ret == 0) {
2411 sc->sc_rf_init = urtw_8225_rf_init;
2412 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2413 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2414 sc->sc_rf_stop = urtw_8225_rf_stop;
2415 } else {
2416 sc->sc_rf_init = urtw_8225v2_rf_init;
2417 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2418 sc->sc_rf_stop = urtw_8225_rf_stop;
2419 }
2420 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2421 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2422 break;
2423 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2424 sc->sc_rf_init = urtw_8225v2b_rf_init;
2425 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2426 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2427 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2428 sc->sc_rf_stop = urtw_8225_rf_stop;
2429 break;
2430 default:
2431 DPRINTF(sc, URTW_DEBUG_STATE,
2432 "unsupported RF chip %d\n", data & 0xff);
2433 error = USB_ERR_INVAL;
2434 goto fail;
2435 }
2436
2437 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2438 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2439 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2440 "rtl8225z2",
2441 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2442 (data8 == 1) ? "d" : "e") : "none");
2443
2444 fail:
2445 return (error);
2446 }
2447
2448 static usb_error_t
urtw_led_init(struct urtw_softc * sc)2449 urtw_led_init(struct urtw_softc *sc)
2450 {
2451 uint32_t rev;
2452 usb_error_t error;
2453
2454 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2455 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2456 if (error != 0)
2457 goto fail;
2458
2459 switch (rev & URTW_EPROM_CID_MASK) {
2460 case URTW_EPROM_CID_ALPHA0:
2461 sc->sc_strategy = URTW_SW_LED_MODE1;
2462 break;
2463 case URTW_EPROM_CID_SERCOMM_PS:
2464 sc->sc_strategy = URTW_SW_LED_MODE3;
2465 break;
2466 case URTW_EPROM_CID_HW_LED:
2467 sc->sc_strategy = URTW_HW_LED;
2468 break;
2469 case URTW_EPROM_CID_RSVD0:
2470 case URTW_EPROM_CID_RSVD1:
2471 default:
2472 sc->sc_strategy = URTW_SW_LED_MODE0;
2473 break;
2474 }
2475
2476 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2477
2478 fail:
2479 return (error);
2480 }
2481
2482 static usb_error_t
urtw_8225_rf_init(struct urtw_softc * sc)2483 urtw_8225_rf_init(struct urtw_softc *sc)
2484 {
2485 unsigned i;
2486 uint16_t data;
2487 usb_error_t error;
2488
2489 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2490 if (error)
2491 goto fail;
2492
2493 error = urtw_8225_usb_init(sc);
2494 if (error)
2495 goto fail;
2496
2497 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2498 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2499 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2500 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2501
2502 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2503 if (error)
2504 goto fail;
2505 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2506 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2507 if (error)
2508 goto fail;
2509
2510 error = urtw_8185_rf_pins_enable(sc);
2511 if (error)
2512 goto fail;
2513 urtw_pause_ms(sc, 1000);
2514
2515 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) {
2516 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2517 urtw_8225_rf_part1[i].val);
2518 urtw_pause_ms(sc, 1);
2519 }
2520 urtw_pause_ms(sc, 100);
2521 urtw_8225_write(sc,
2522 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2523 urtw_pause_ms(sc, 200);
2524 urtw_8225_write(sc,
2525 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2526 urtw_pause_ms(sc, 200);
2527 urtw_8225_write(sc,
2528 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2529
2530 for (i = 0; i < 95; i++) {
2531 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2532 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2533 }
2534
2535 urtw_8225_write(sc,
2536 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2537 urtw_8225_write(sc,
2538 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2539
2540 for (i = 0; i < 128; i++) {
2541 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2542 urtw_pause_ms(sc, 1);
2543 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2544 urtw_pause_ms(sc, 1);
2545 }
2546
2547 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) {
2548 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2549 urtw_8225_rf_part2[i].val);
2550 urtw_pause_ms(sc, 1);
2551 }
2552
2553 error = urtw_8225_setgain(sc, 4);
2554 if (error)
2555 goto fail;
2556
2557 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) {
2558 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2559 urtw_8225_rf_part3[i].val);
2560 urtw_pause_ms(sc, 1);
2561 }
2562
2563 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2564
2565 error = urtw_8225_set_txpwrlvl(sc, 1);
2566 if (error)
2567 goto fail;
2568
2569 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2570 urtw_pause_ms(sc, 1);
2571 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2572 urtw_pause_ms(sc, 1);
2573
2574 /* TX ant A, 0x0 for B */
2575 error = urtw_8185_tx_antenna(sc, 0x3);
2576 if (error)
2577 goto fail;
2578 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2579
2580 error = urtw_8225_rf_set_chan(sc, 1);
2581 fail:
2582 return (error);
2583 }
2584
2585 static usb_error_t
urtw_8185_rf_pins_enable(struct urtw_softc * sc)2586 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2587 {
2588 usb_error_t error = 0;
2589
2590 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2591 fail:
2592 return (error);
2593 }
2594
2595 static usb_error_t
urtw_8185_tx_antenna(struct urtw_softc * sc,uint8_t ant)2596 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2597 {
2598 usb_error_t error;
2599
2600 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2601 urtw_pause_ms(sc, 1);
2602 fail:
2603 return (error);
2604 }
2605
2606 static usb_error_t
urtw_8187_write_phy_ofdm_c(struct urtw_softc * sc,uint8_t addr,uint32_t data)2607 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2608 {
2609
2610 data = data & 0xff;
2611 return urtw_8187_write_phy(sc, addr, data);
2612 }
2613
2614 static usb_error_t
urtw_8187_write_phy_cck_c(struct urtw_softc * sc,uint8_t addr,uint32_t data)2615 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2616 {
2617
2618 data = data & 0xff;
2619 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2620 }
2621
2622 static usb_error_t
urtw_8187_write_phy(struct urtw_softc * sc,uint8_t addr,uint32_t data)2623 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2624 {
2625 uint32_t phyw;
2626 usb_error_t error;
2627
2628 phyw = ((data << 8) | (addr | 0x80));
2629 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2630 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2631 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2632 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2633 urtw_pause_ms(sc, 1);
2634 fail:
2635 return (error);
2636 }
2637
2638 static usb_error_t
urtw_8225_setgain(struct urtw_softc * sc,int16_t gain)2639 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2640 {
2641 usb_error_t error;
2642
2643 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2644 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2645 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2646 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2647 fail:
2648 return (error);
2649 }
2650
2651 static usb_error_t
urtw_8225_usb_init(struct urtw_softc * sc)2652 urtw_8225_usb_init(struct urtw_softc *sc)
2653 {
2654 uint8_t data;
2655 usb_error_t error;
2656
2657 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2658 urtw_write8_m(sc, URTW_GPIO, 0);
2659 error = urtw_read8e(sc, 0x53, &data);
2660 if (error)
2661 goto fail;
2662 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2663 if (error)
2664 goto fail;
2665 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2666 urtw_write8_m(sc, URTW_GPIO, 0x20);
2667 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2668
2669 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2670 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2671 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2672
2673 urtw_pause_ms(sc, 500);
2674 fail:
2675 return (error);
2676 }
2677
2678 static usb_error_t
urtw_8225_write_c(struct urtw_softc * sc,uint8_t addr,uint16_t data)2679 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2680 {
2681 uint16_t d80, d82, d84;
2682 usb_error_t error;
2683
2684 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2685 d80 &= URTW_RF_PINS_MAGIC1;
2686 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2687 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2688 d84 &= URTW_RF_PINS_MAGIC2;
2689 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2690 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2691 DELAY(10);
2692
2693 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2694 DELAY(2);
2695 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2696 DELAY(10);
2697
2698 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2699 if (error != 0)
2700 goto fail;
2701
2702 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2703 DELAY(10);
2704 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2705 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2706 urtw_pause_ms(sc, 2);
2707 fail:
2708 return (error);
2709 }
2710
2711 static usb_error_t
urtw_8225_write_s16(struct urtw_softc * sc,uint8_t addr,int index,uint16_t * data)2712 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2713 uint16_t *data)
2714 {
2715 uint8_t buf[2];
2716 uint16_t data16;
2717 struct usb_device_request req;
2718 usb_error_t error = 0;
2719
2720 data16 = *data;
2721
2722 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2723 req.bRequest = URTW_8187_SETREGS_REQ;
2724 USETW(req.wValue, addr);
2725 USETW(req.wIndex, index);
2726 USETW(req.wLength, sizeof(uint16_t));
2727 buf[0] = (data16 & 0x00ff);
2728 buf[1] = (data16 & 0xff00) >> 8;
2729
2730 error = urtw_do_request(sc, &req, buf);
2731
2732 return (error);
2733 }
2734
2735 static usb_error_t
urtw_8225_rf_set_chan(struct urtw_softc * sc,int chan)2736 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2737 {
2738 usb_error_t error;
2739
2740 error = urtw_8225_set_txpwrlvl(sc, chan);
2741 if (error)
2742 goto fail;
2743 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2744 urtw_pause_ms(sc, 10);
2745 fail:
2746 return (error);
2747 }
2748
2749 static usb_error_t
urtw_8225_rf_set_sens(struct urtw_softc * sc,int sens)2750 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2751 {
2752 usb_error_t error;
2753
2754 if (sens < 0 || sens > 6)
2755 return -1;
2756
2757 if (sens > 4)
2758 urtw_8225_write(sc,
2759 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2760 else
2761 urtw_8225_write(sc,
2762 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2763
2764 sens = 6 - sens;
2765 error = urtw_8225_setgain(sc, sens);
2766 if (error)
2767 goto fail;
2768
2769 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2770
2771 fail:
2772 return (error);
2773 }
2774
2775 static usb_error_t
urtw_8225_set_txpwrlvl(struct urtw_softc * sc,int chan)2776 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2777 {
2778 int i, idx, set;
2779 uint8_t *cck_pwltable;
2780 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2781 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2782 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2783 usb_error_t error;
2784
2785 cck_pwrlvl_max = 11;
2786 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2787 ofdm_pwrlvl_min = 10;
2788
2789 /* CCK power setting */
2790 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2791 idx = cck_pwrlvl % 6;
2792 set = cck_pwrlvl / 6;
2793 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2794 urtw_8225_txpwr_cck;
2795
2796 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2797 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2798 for (i = 0; i < 8; i++) {
2799 urtw_8187_write_phy_cck(sc, 0x44 + i,
2800 cck_pwltable[idx * 8 + i]);
2801 }
2802 urtw_pause_ms(sc, 1);
2803
2804 /* OFDM power setting */
2805 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2806 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2807 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2808
2809 idx = ofdm_pwrlvl % 6;
2810 set = ofdm_pwrlvl / 6;
2811
2812 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2813 if (error)
2814 goto fail;
2815 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2816 urtw_8187_write_phy_ofdm(sc, 6, 0);
2817 urtw_8187_write_phy_ofdm(sc, 8, 0);
2818
2819 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2820 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2821 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2822 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2823 urtw_pause_ms(sc, 1);
2824 fail:
2825 return (error);
2826 }
2827
2828 static usb_error_t
urtw_8225_rf_stop(struct urtw_softc * sc)2829 urtw_8225_rf_stop(struct urtw_softc *sc)
2830 {
2831 uint8_t data;
2832 usb_error_t error;
2833
2834 urtw_8225_write(sc, 0x4, 0x1f);
2835
2836 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2837 if (error)
2838 goto fail;
2839
2840 urtw_read8_m(sc, URTW_CONFIG3, &data);
2841 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2842 if (sc->sc_flags & URTW_RTL8187B) {
2843 urtw_write32_m(sc, URTW_ANAPARAM2,
2844 URTW_8187B_8225_ANAPARAM2_OFF);
2845 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2846 urtw_write32_m(sc, URTW_ANAPARAM3,
2847 URTW_8187B_8225_ANAPARAM3_OFF);
2848 } else {
2849 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2850 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2851 }
2852
2853 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2854 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2855 if (error)
2856 goto fail;
2857
2858 fail:
2859 return (error);
2860 }
2861
2862 static usb_error_t
urtw_8225v2_rf_init(struct urtw_softc * sc)2863 urtw_8225v2_rf_init(struct urtw_softc *sc)
2864 {
2865 unsigned i;
2866 uint16_t data;
2867 uint32_t data32;
2868 usb_error_t error;
2869
2870 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2871 if (error)
2872 goto fail;
2873
2874 error = urtw_8225_usb_init(sc);
2875 if (error)
2876 goto fail;
2877
2878 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2879 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2880 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2881 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2882
2883 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2884 if (error)
2885 goto fail;
2886 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2887 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2888 if (error)
2889 goto fail;
2890
2891 error = urtw_8185_rf_pins_enable(sc);
2892 if (error)
2893 goto fail;
2894
2895 urtw_pause_ms(sc, 500);
2896
2897 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) {
2898 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2899 urtw_8225v2_rf_part1[i].val);
2900 }
2901 urtw_pause_ms(sc, 50);
2902
2903 urtw_8225_write(sc,
2904 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2905
2906 for (i = 0; i < 95; i++) {
2907 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2908 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2909 urtw_8225v2_rxgain[i]);
2910 }
2911
2912 urtw_8225_write(sc,
2913 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2914 urtw_8225_write(sc,
2915 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2916 urtw_8225_write(sc,
2917 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2918 urtw_8225_write(sc,
2919 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2920 urtw_pause_ms(sc, 100);
2921 urtw_8225_write(sc,
2922 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2923 urtw_pause_ms(sc, 100);
2924
2925 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2926 if (error != 0)
2927 goto fail;
2928 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2929 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2930 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2931 urtw_8225_write(sc,
2932 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2933 urtw_pause_ms(sc, 100);
2934 urtw_8225_write(sc,
2935 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2936 urtw_pause_ms(sc, 50);
2937 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2938 if (error != 0)
2939 goto fail;
2940 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2941 device_printf(sc->sc_dev, "RF calibration failed\n");
2942 }
2943 urtw_pause_ms(sc, 100);
2944
2945 urtw_8225_write(sc,
2946 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2947 for (i = 0; i < 128; i++) {
2948 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2949 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2950 }
2951
2952 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) {
2953 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2954 urtw_8225v2_rf_part2[i].val);
2955 }
2956
2957 error = urtw_8225v2_setgain(sc, 4);
2958 if (error)
2959 goto fail;
2960
2961 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) {
2962 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2963 urtw_8225v2_rf_part3[i].val);
2964 }
2965
2966 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2967
2968 error = urtw_8225v2_set_txpwrlvl(sc, 1);
2969 if (error)
2970 goto fail;
2971
2972 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2973 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2974
2975 /* TX ant A, 0x0 for B */
2976 error = urtw_8185_tx_antenna(sc, 0x3);
2977 if (error)
2978 goto fail;
2979 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2980
2981 error = urtw_8225_rf_set_chan(sc, 1);
2982 fail:
2983 return (error);
2984 }
2985
2986 static usb_error_t
urtw_8225v2_rf_set_chan(struct urtw_softc * sc,int chan)2987 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
2988 {
2989 usb_error_t error;
2990
2991 error = urtw_8225v2_set_txpwrlvl(sc, chan);
2992 if (error)
2993 goto fail;
2994
2995 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2996 urtw_pause_ms(sc, 10);
2997 fail:
2998 return (error);
2999 }
3000
3001 static usb_error_t
urtw_8225_read(struct urtw_softc * sc,uint8_t addr,uint32_t * data)3002 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3003 {
3004 int i;
3005 int16_t bit;
3006 uint8_t rlen = 12, wlen = 6;
3007 uint16_t o1, o2, o3, tmp;
3008 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3009 uint32_t mask = 0x80000000, value = 0;
3010 usb_error_t error;
3011
3012 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3013 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3014 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3015 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3016 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3017 o1 &= ~URTW_RF_PINS_MAGIC4;
3018 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3019 DELAY(5);
3020 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3021 DELAY(5);
3022
3023 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3024 bit = ((d2w & mask) != 0) ? 1 : 0;
3025
3026 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3027 DELAY(2);
3028 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3029 URTW_BB_HOST_BANG_CLK);
3030 DELAY(2);
3031 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3032 URTW_BB_HOST_BANG_CLK);
3033 DELAY(2);
3034 mask = mask >> 1;
3035 if (i == 2)
3036 break;
3037 bit = ((d2w & mask) != 0) ? 1 : 0;
3038 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3039 URTW_BB_HOST_BANG_CLK);
3040 DELAY(2);
3041 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3042 URTW_BB_HOST_BANG_CLK);
3043 DELAY(2);
3044 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3045 DELAY(1);
3046 }
3047 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3048 URTW_BB_HOST_BANG_CLK);
3049 DELAY(2);
3050 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3051 DELAY(2);
3052 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3053 DELAY(2);
3054
3055 mask = 0x800;
3056 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3057 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3058 o1 | URTW_BB_HOST_BANG_RW);
3059 DELAY(2);
3060 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3061 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3062 DELAY(2);
3063 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3064 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3065 DELAY(2);
3066 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3067 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3068 DELAY(2);
3069
3070 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3071 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3072 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3073 o1 | URTW_BB_HOST_BANG_RW);
3074 DELAY(2);
3075 }
3076
3077 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3078 URTW_BB_HOST_BANG_RW);
3079 DELAY(2);
3080
3081 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3082 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3083 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3084
3085 if (data != NULL)
3086 *data = value;
3087 fail:
3088 return (error);
3089 }
3090
3091 static usb_error_t
urtw_8225v2_set_txpwrlvl(struct urtw_softc * sc,int chan)3092 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3093 {
3094 int i;
3095 uint8_t *cck_pwrtable;
3096 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3097 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3098 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3099 usb_error_t error;
3100
3101 /* CCK power setting */
3102 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3103 cck_pwrlvl += sc->sc_txpwr_cck_base;
3104 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3105 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3106 urtw_8225v2_txpwr_cck;
3107
3108 for (i = 0; i < 8; i++)
3109 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3110
3111 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3112 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3113 urtw_pause_ms(sc, 1);
3114
3115 /* OFDM power setting */
3116 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3117 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3118 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3119 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3120
3121 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3122 if (error)
3123 goto fail;
3124
3125 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3126 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3127 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3128 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3129 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3130
3131 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3132 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3133 urtw_pause_ms(sc, 1);
3134 fail:
3135 return (error);
3136 }
3137
3138 static usb_error_t
urtw_8225v2_setgain(struct urtw_softc * sc,int16_t gain)3139 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3140 {
3141 uint8_t *gainp;
3142 usb_error_t error;
3143
3144 /* XXX for A? */
3145 gainp = urtw_8225v2_gain_bg;
3146 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3147 urtw_pause_ms(sc, 1);
3148 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3149 urtw_pause_ms(sc, 1);
3150 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3151 urtw_pause_ms(sc, 1);
3152 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3153 urtw_pause_ms(sc, 1);
3154 fail:
3155 return (error);
3156 }
3157
3158 static usb_error_t
urtw_8225_isv2(struct urtw_softc * sc,int * ret)3159 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3160 {
3161 uint32_t data;
3162 usb_error_t error;
3163
3164 *ret = 1;
3165
3166 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3167 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3168 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3169 urtw_pause_ms(sc, 500);
3170
3171 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3172 URTW_8225_ADDR_0_DATA_MAGIC1);
3173
3174 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3175 if (error != 0)
3176 goto fail;
3177 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3178 *ret = 0;
3179 else {
3180 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3181 if (error != 0)
3182 goto fail;
3183 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3184 *ret = 0;
3185 }
3186
3187 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3188 URTW_8225_ADDR_0_DATA_MAGIC2);
3189 fail:
3190 return (error);
3191 }
3192
3193 static usb_error_t
urtw_8225v2b_rf_init(struct urtw_softc * sc)3194 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3195 {
3196 struct ieee80211com *ic = &sc->sc_ic;
3197 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3198 const uint8_t *macaddr;
3199 unsigned i;
3200 uint8_t data8;
3201 usb_error_t error;
3202
3203 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3204 if (error)
3205 goto fail;
3206
3207 /*
3208 * initialize extra registers on 8187
3209 */
3210 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3211
3212 /* retry limit */
3213 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3214 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3215 urtw_write8_m(sc, URTW_CW_CONF, data8);
3216
3217 /* TX AGC */
3218 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3219 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3220 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3221
3222 /* Auto Rate Fallback Control */
3223 #define URTW_ARFR 0x1e0
3224 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3225 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3226 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3227 data8 | URTW_RATE_FALLBACK_ENABLE);
3228
3229 urtw_read8_m(sc, URTW_MSR, &data8);
3230 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3231 urtw_read8_m(sc, URTW_MSR, &data8);
3232 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3233 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3234
3235 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3236 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3237 #define URTW_FEMR_FOR_8187B 0x1d4
3238 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3239
3240 /* led type */
3241 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3242 data8 = (data8 & 0x3f) | 0x80;
3243 urtw_write8_m(sc, URTW_CONFIG1, data8);
3244
3245 /* applying MAC address again. */
3246 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
3247 error = urtw_set_macaddr(sc, macaddr);
3248 if (error)
3249 goto fail;
3250
3251 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3252 if (error)
3253 goto fail;
3254
3255 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3256
3257 /*
3258 * MAC configuration
3259 */
3260 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++)
3261 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3262 urtw_8225v2b_rf_part1[i].val);
3263 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3264 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3265 urtw_write32_m(sc, 0x1f0, 0);
3266 urtw_write32_m(sc, 0x1f4, 0);
3267 urtw_write8_m(sc, 0x1f8, 0);
3268 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3269
3270 #define URTW_RFSW_CTRL 0x272
3271 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3272
3273 /*
3274 * initialize PHY
3275 */
3276 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3277 if (error)
3278 goto fail;
3279 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3280 urtw_write8_m(sc, URTW_CONFIG3,
3281 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3282
3283 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3284 if (error)
3285 goto fail;
3286
3287 /* setup RFE initial timing */
3288 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3289 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3290 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3291 urtw_pause_ms(sc, 1100);
3292
3293 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) {
3294 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3295 urtw_8225v2b_rf_part0[i].val);
3296 urtw_pause_ms(sc, 1);
3297 }
3298 urtw_8225_write(sc, 0x00, 0x01b7);
3299
3300 for (i = 0; i < 95; i++) {
3301 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3302 urtw_pause_ms(sc, 1);
3303 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3304 urtw_8225v2b_rxgain[i]);
3305 urtw_pause_ms(sc, 1);
3306 }
3307
3308 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3309 urtw_pause_ms(sc, 1);
3310 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3311 urtw_pause_ms(sc, 1);
3312 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3313 urtw_pause_ms(sc, 1);
3314 urtw_pause_ms(sc, 3000);
3315 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3316 urtw_pause_ms(sc, 2000);
3317 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3318 urtw_pause_ms(sc, 1);
3319 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3320 urtw_pause_ms(sc, 1);
3321
3322 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3323 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3324 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3325
3326 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3327 for (i = 0; i < 128; i++) {
3328 uint32_t addr, data;
3329
3330 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3331 addr = ((i + 0x80) << 8) | 0x0000008e;
3332
3333 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3334 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3335 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3336 }
3337 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3338
3339 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++)
3340 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3341
3342 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3343 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3344 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3345 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3346
3347 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3348 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3349 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3350 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3351
3352 fail:
3353 return (error);
3354 }
3355
3356 static usb_error_t
urtw_8225v2b_rf_set_chan(struct urtw_softc * sc,int chan)3357 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3358 {
3359 usb_error_t error;
3360
3361 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3362 if (error)
3363 goto fail;
3364
3365 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3366 urtw_pause_ms(sc, 10);
3367 fail:
3368 return (error);
3369 }
3370
3371 static usb_error_t
urtw_8225v2b_set_txpwrlvl(struct urtw_softc * sc,int chan)3372 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3373 {
3374 int i;
3375 uint8_t *cck_pwrtable;
3376 uint8_t cck_pwrlvl_max = 15;
3377 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3378 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3379 usb_error_t error;
3380
3381 /* CCK power setting */
3382 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3383 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3384 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3385 cck_pwrlvl += sc->sc_txpwr_cck_base;
3386 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3387 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3388 urtw_8225v2b_txpwr_cck;
3389
3390 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3391 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3392 ((cck_pwrlvl <= 11) ? 8 : 16);
3393 else
3394 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3395 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3396
3397 for (i = 0; i < 8; i++)
3398 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3399
3400 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3401 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3402 urtw_pause_ms(sc, 1);
3403
3404 /* OFDM power setting */
3405 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3406 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3407 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3408 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3409 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3410
3411 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3412 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3413
3414 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3415 if (ofdm_pwrlvl <= 11) {
3416 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3417 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3418 } else {
3419 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3420 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3421 }
3422 } else {
3423 if (ofdm_pwrlvl <= 11) {
3424 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3425 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3426 } else if (ofdm_pwrlvl <= 17) {
3427 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3428 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3429 } else {
3430 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3431 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3432 }
3433 }
3434 urtw_pause_ms(sc, 1);
3435 fail:
3436 return (error);
3437 }
3438
3439 static usb_error_t
urtw_read8e(struct urtw_softc * sc,int val,uint8_t * data)3440 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3441 {
3442 struct usb_device_request req;
3443 usb_error_t error;
3444
3445 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3446 req.bRequest = URTW_8187_GETREGS_REQ;
3447 USETW(req.wValue, val | 0xfe00);
3448 USETW(req.wIndex, 0);
3449 USETW(req.wLength, sizeof(uint8_t));
3450
3451 error = urtw_do_request(sc, &req, data);
3452 return (error);
3453 }
3454
3455 static usb_error_t
urtw_write8e(struct urtw_softc * sc,int val,uint8_t data)3456 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3457 {
3458 struct usb_device_request req;
3459
3460 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3461 req.bRequest = URTW_8187_SETREGS_REQ;
3462 USETW(req.wValue, val | 0xfe00);
3463 USETW(req.wIndex, 0);
3464 USETW(req.wLength, sizeof(uint8_t));
3465
3466 return (urtw_do_request(sc, &req, &data));
3467 }
3468
3469 static usb_error_t
urtw_8180_set_anaparam(struct urtw_softc * sc,uint32_t val)3470 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3471 {
3472 uint8_t data;
3473 usb_error_t error;
3474
3475 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3476 if (error)
3477 goto fail;
3478
3479 urtw_read8_m(sc, URTW_CONFIG3, &data);
3480 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3481 urtw_write32_m(sc, URTW_ANAPARAM, val);
3482 urtw_read8_m(sc, URTW_CONFIG3, &data);
3483 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3484
3485 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3486 if (error)
3487 goto fail;
3488 fail:
3489 return (error);
3490 }
3491
3492 static usb_error_t
urtw_8185_set_anaparam2(struct urtw_softc * sc,uint32_t val)3493 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3494 {
3495 uint8_t data;
3496 usb_error_t error;
3497
3498 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3499 if (error)
3500 goto fail;
3501
3502 urtw_read8_m(sc, URTW_CONFIG3, &data);
3503 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3504 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3505 urtw_read8_m(sc, URTW_CONFIG3, &data);
3506 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3507
3508 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3509 if (error)
3510 goto fail;
3511 fail:
3512 return (error);
3513 }
3514
3515 static usb_error_t
urtw_intr_enable(struct urtw_softc * sc)3516 urtw_intr_enable(struct urtw_softc *sc)
3517 {
3518 usb_error_t error;
3519
3520 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3521 fail:
3522 return (error);
3523 }
3524
3525 static usb_error_t
urtw_intr_disable(struct urtw_softc * sc)3526 urtw_intr_disable(struct urtw_softc *sc)
3527 {
3528 usb_error_t error;
3529
3530 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3531 fail:
3532 return (error);
3533 }
3534
3535 static usb_error_t
urtw_reset(struct urtw_softc * sc)3536 urtw_reset(struct urtw_softc *sc)
3537 {
3538 uint8_t data;
3539 usb_error_t error;
3540
3541 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3542 if (error)
3543 goto fail;
3544 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3545 if (error)
3546 goto fail;
3547
3548 error = urtw_intr_disable(sc);
3549 if (error)
3550 goto fail;
3551 urtw_pause_ms(sc, 100);
3552
3553 error = urtw_write8e(sc, 0x18, 0x10);
3554 if (error != 0)
3555 goto fail;
3556 error = urtw_write8e(sc, 0x18, 0x11);
3557 if (error != 0)
3558 goto fail;
3559 error = urtw_write8e(sc, 0x18, 0x00);
3560 if (error != 0)
3561 goto fail;
3562 urtw_pause_ms(sc, 100);
3563
3564 urtw_read8_m(sc, URTW_CMD, &data);
3565 data = (data & 0x2) | URTW_CMD_RST;
3566 urtw_write8_m(sc, URTW_CMD, data);
3567 urtw_pause_ms(sc, 100);
3568
3569 urtw_read8_m(sc, URTW_CMD, &data);
3570 if (data & URTW_CMD_RST) {
3571 device_printf(sc->sc_dev, "reset timeout\n");
3572 goto fail;
3573 }
3574
3575 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3576 if (error)
3577 goto fail;
3578 urtw_pause_ms(sc, 100);
3579
3580 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3581 if (error)
3582 goto fail;
3583 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3584 if (error)
3585 goto fail;
3586 fail:
3587 return (error);
3588 }
3589
3590 static usb_error_t
urtw_led_ctl(struct urtw_softc * sc,int mode)3591 urtw_led_ctl(struct urtw_softc *sc, int mode)
3592 {
3593 usb_error_t error = 0;
3594
3595 switch (sc->sc_strategy) {
3596 case URTW_SW_LED_MODE0:
3597 error = urtw_led_mode0(sc, mode);
3598 break;
3599 case URTW_SW_LED_MODE1:
3600 error = urtw_led_mode1(sc, mode);
3601 break;
3602 case URTW_SW_LED_MODE2:
3603 error = urtw_led_mode2(sc, mode);
3604 break;
3605 case URTW_SW_LED_MODE3:
3606 error = urtw_led_mode3(sc, mode);
3607 break;
3608 default:
3609 DPRINTF(sc, URTW_DEBUG_STATE,
3610 "unsupported LED mode %d\n", sc->sc_strategy);
3611 error = USB_ERR_INVAL;
3612 break;
3613 }
3614
3615 return (error);
3616 }
3617
3618 static usb_error_t
urtw_led_mode0(struct urtw_softc * sc,int mode)3619 urtw_led_mode0(struct urtw_softc *sc, int mode)
3620 {
3621
3622 switch (mode) {
3623 case URTW_LED_CTL_POWER_ON:
3624 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3625 break;
3626 case URTW_LED_CTL_TX:
3627 if (sc->sc_gpio_ledinprogress == 1)
3628 return (0);
3629
3630 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3631 sc->sc_gpio_blinktime = 2;
3632 break;
3633 case URTW_LED_CTL_LINK:
3634 sc->sc_gpio_ledstate = URTW_LED_ON;
3635 break;
3636 default:
3637 DPRINTF(sc, URTW_DEBUG_STATE,
3638 "unsupported LED mode 0x%x", mode);
3639 return (USB_ERR_INVAL);
3640 }
3641
3642 switch (sc->sc_gpio_ledstate) {
3643 case URTW_LED_ON:
3644 if (sc->sc_gpio_ledinprogress != 0)
3645 break;
3646 urtw_led_on(sc, URTW_LED_GPIO);
3647 break;
3648 case URTW_LED_BLINK_NORMAL:
3649 if (sc->sc_gpio_ledinprogress != 0)
3650 break;
3651 sc->sc_gpio_ledinprogress = 1;
3652 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3653 URTW_LED_OFF : URTW_LED_ON;
3654 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3655 break;
3656 case URTW_LED_POWER_ON_BLINK:
3657 urtw_led_on(sc, URTW_LED_GPIO);
3658 urtw_pause_ms(sc, 100);
3659 urtw_led_off(sc, URTW_LED_GPIO);
3660 break;
3661 default:
3662 DPRINTF(sc, URTW_DEBUG_STATE,
3663 "unknown LED status 0x%x", sc->sc_gpio_ledstate);
3664 return (USB_ERR_INVAL);
3665 }
3666 return (0);
3667 }
3668
3669 static usb_error_t
urtw_led_mode1(struct urtw_softc * sc,int mode)3670 urtw_led_mode1(struct urtw_softc *sc, int mode)
3671 {
3672 return (USB_ERR_INVAL);
3673 }
3674
3675 static usb_error_t
urtw_led_mode2(struct urtw_softc * sc,int mode)3676 urtw_led_mode2(struct urtw_softc *sc, int mode)
3677 {
3678 return (USB_ERR_INVAL);
3679 }
3680
3681 static usb_error_t
urtw_led_mode3(struct urtw_softc * sc,int mode)3682 urtw_led_mode3(struct urtw_softc *sc, int mode)
3683 {
3684 return (USB_ERR_INVAL);
3685 }
3686
3687 static usb_error_t
urtw_led_on(struct urtw_softc * sc,int type)3688 urtw_led_on(struct urtw_softc *sc, int type)
3689 {
3690 usb_error_t error;
3691
3692 if (type == URTW_LED_GPIO) {
3693 switch (sc->sc_gpio_ledpin) {
3694 case URTW_LED_PIN_GPIO0:
3695 urtw_write8_m(sc, URTW_GPIO, 0x01);
3696 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3697 break;
3698 default:
3699 DPRINTF(sc, URTW_DEBUG_STATE,
3700 "unsupported LED PIN type 0x%x",
3701 sc->sc_gpio_ledpin);
3702 error = USB_ERR_INVAL;
3703 goto fail;
3704 }
3705 } else {
3706 DPRINTF(sc, URTW_DEBUG_STATE,
3707 "unsupported LED type 0x%x", type);
3708 error = USB_ERR_INVAL;
3709 goto fail;
3710 }
3711
3712 sc->sc_gpio_ledon = 1;
3713 fail:
3714 return (error);
3715 }
3716
3717 static usb_error_t
urtw_led_off(struct urtw_softc * sc,int type)3718 urtw_led_off(struct urtw_softc *sc, int type)
3719 {
3720 usb_error_t error;
3721
3722 if (type == URTW_LED_GPIO) {
3723 switch (sc->sc_gpio_ledpin) {
3724 case URTW_LED_PIN_GPIO0:
3725 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3726 urtw_write8_m(sc,
3727 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3728 break;
3729 default:
3730 DPRINTF(sc, URTW_DEBUG_STATE,
3731 "unsupported LED PIN type 0x%x",
3732 sc->sc_gpio_ledpin);
3733 error = USB_ERR_INVAL;
3734 goto fail;
3735 }
3736 } else {
3737 DPRINTF(sc, URTW_DEBUG_STATE,
3738 "unsupported LED type 0x%x", type);
3739 error = USB_ERR_INVAL;
3740 goto fail;
3741 }
3742
3743 sc->sc_gpio_ledon = 0;
3744
3745 fail:
3746 return (error);
3747 }
3748
3749 static void
urtw_led_ch(void * arg)3750 urtw_led_ch(void *arg)
3751 {
3752 struct urtw_softc *sc = arg;
3753 struct ieee80211com *ic = &sc->sc_ic;
3754
3755 ieee80211_runtask(ic, &sc->sc_led_task);
3756 }
3757
3758 static void
urtw_ledtask(void * arg,int pending)3759 urtw_ledtask(void *arg, int pending)
3760 {
3761 struct urtw_softc *sc = arg;
3762
3763 if (sc->sc_strategy != URTW_SW_LED_MODE0) {
3764 DPRINTF(sc, URTW_DEBUG_STATE,
3765 "could not process a LED strategy 0x%x",
3766 sc->sc_strategy);
3767 return;
3768 }
3769
3770 URTW_LOCK(sc);
3771 urtw_led_blink(sc);
3772 URTW_UNLOCK(sc);
3773 }
3774
3775 static usb_error_t
urtw_led_blink(struct urtw_softc * sc)3776 urtw_led_blink(struct urtw_softc *sc)
3777 {
3778 uint8_t ing = 0;
3779
3780 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3781 urtw_led_on(sc, URTW_LED_GPIO);
3782 else
3783 urtw_led_off(sc, URTW_LED_GPIO);
3784 sc->sc_gpio_blinktime--;
3785 if (sc->sc_gpio_blinktime == 0)
3786 ing = 1;
3787 else {
3788 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3789 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3790 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3791 ing = 1;
3792 }
3793 if (ing == 1) {
3794 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3795 sc->sc_gpio_ledon == 0)
3796 urtw_led_on(sc, URTW_LED_GPIO);
3797 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3798 sc->sc_gpio_ledon == 1)
3799 urtw_led_off(sc, URTW_LED_GPIO);
3800
3801 sc->sc_gpio_blinktime = 0;
3802 sc->sc_gpio_ledinprogress = 0;
3803 return (0);
3804 }
3805
3806 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3807 URTW_LED_ON : URTW_LED_OFF;
3808
3809 switch (sc->sc_gpio_ledstate) {
3810 case URTW_LED_BLINK_NORMAL:
3811 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3812 break;
3813 default:
3814 DPRINTF(sc, URTW_DEBUG_STATE,
3815 "unknown LED status 0x%x",
3816 sc->sc_gpio_ledstate);
3817 return (USB_ERR_INVAL);
3818 }
3819 return (0);
3820 }
3821
3822 static usb_error_t
urtw_rx_enable(struct urtw_softc * sc)3823 urtw_rx_enable(struct urtw_softc *sc)
3824 {
3825 uint8_t data;
3826 usb_error_t error;
3827
3828 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3829 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3830
3831 error = urtw_rx_setconf(sc);
3832 if (error != 0)
3833 goto fail;
3834
3835 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3836 urtw_read8_m(sc, URTW_CMD, &data);
3837 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3838 }
3839 fail:
3840 return (error);
3841 }
3842
3843 static usb_error_t
urtw_tx_enable(struct urtw_softc * sc)3844 urtw_tx_enable(struct urtw_softc *sc)
3845 {
3846 uint8_t data8;
3847 uint32_t data;
3848 usb_error_t error;
3849
3850 if (sc->sc_flags & URTW_RTL8187B) {
3851 urtw_read32_m(sc, URTW_TX_CONF, &data);
3852 data &= ~URTW_TX_LOOPBACK_MASK;
3853 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3854 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3855 data &= ~URTW_TX_SWPLCPLEN;
3856 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3857 (7 << 8) | /* short retry limit */
3858 (7 << 0) | /* long retry limit */
3859 (7 << 21); /* MAX TX DMA */
3860 urtw_write32_m(sc, URTW_TX_CONF, data);
3861
3862 urtw_read8_m(sc, URTW_MSR, &data8);
3863 data8 |= URTW_MSR_LINK_ENEDCA;
3864 urtw_write8_m(sc, URTW_MSR, data8);
3865 return (error);
3866 }
3867
3868 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3869 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3870 urtw_write8_m(sc, URTW_CW_CONF, data8);
3871
3872 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3873 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3874 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3875 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3876 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3877
3878 urtw_read32_m(sc, URTW_TX_CONF, &data);
3879 data &= ~URTW_TX_LOOPBACK_MASK;
3880 data |= URTW_TX_LOOPBACK_NONE;
3881 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3882 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3883 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3884 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3885 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3886 data &= ~URTW_TX_SWPLCPLEN;
3887 data |= URTW_TX_NOICV;
3888 urtw_write32_m(sc, URTW_TX_CONF, data);
3889
3890 urtw_read8_m(sc, URTW_CMD, &data8);
3891 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3892 fail:
3893 return (error);
3894 }
3895
3896 static usb_error_t
urtw_rx_setconf(struct urtw_softc * sc)3897 urtw_rx_setconf(struct urtw_softc *sc)
3898 {
3899 struct ieee80211com *ic = &sc->sc_ic;
3900 uint32_t data;
3901 usb_error_t error;
3902
3903 urtw_read32_m(sc, URTW_RX, &data);
3904 data = data &~ URTW_RX_FILTER_MASK;
3905 if (sc->sc_flags & URTW_RTL8187B) {
3906 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3907 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3908 URTW_RX_FIFO_THRESHOLD_NONE |
3909 URTW_MAX_RX_DMA_2048 |
3910 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3911 } else {
3912 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3913 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3914
3915 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3916 data = data | URTW_RX_FILTER_ICVERR;
3917 data = data | URTW_RX_FILTER_PWR;
3918 }
3919 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3920 data = data | URTW_RX_FILTER_CRCERR;
3921
3922 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3923 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3924 URTW_RX_AUTORESETPHY;
3925 data = data &~ URTW_MAX_RX_DMA_MASK;
3926 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3927 }
3928
3929 /* XXX allmulti should not be checked here... */
3930 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3931 ic->ic_promisc > 0 || ic->ic_allmulti > 0) {
3932 data = data | URTW_RX_FILTER_CTL;
3933 data = data | URTW_RX_FILTER_ALLMAC;
3934 } else {
3935 data = data | URTW_RX_FILTER_NICMAC;
3936 data = data | URTW_RX_CHECK_BSSID;
3937 }
3938
3939 urtw_write32_m(sc, URTW_RX, data);
3940 fail:
3941 return (error);
3942 }
3943
3944 static struct mbuf *
urtw_rxeof(struct usb_xfer * xfer,struct urtw_data * data,int * rssi_p,int8_t * nf_p)3945 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3946 int8_t *nf_p)
3947 {
3948 int actlen, flen, rssi;
3949 struct ieee80211_frame *wh;
3950 struct mbuf *m, *mnew;
3951 struct urtw_softc *sc = data->sc;
3952 struct ieee80211com *ic = &sc->sc_ic;
3953 uint8_t noise = 0, rate;
3954 uint64_t mactime;
3955
3956 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3957
3958 if (sc->sc_flags & URTW_RTL8187B) {
3959 struct urtw_8187b_rxhdr *rx;
3960
3961 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN)
3962 goto fail;
3963
3964 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3965 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3966 flen = le32toh(rx->flag) & 0xfff;
3967 if (flen > actlen - sizeof(*rx))
3968 goto fail;
3969
3970 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3971 /* XXX correct? */
3972 rssi = rx->rssi & URTW_RX_RSSI_MASK;
3973 noise = rx->noise;
3974
3975 if (ieee80211_radiotap_active(ic))
3976 mactime = rx->mactime;
3977 } else {
3978 struct urtw_8187l_rxhdr *rx;
3979
3980 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN)
3981 goto fail;
3982
3983 rx = (struct urtw_8187l_rxhdr *)(data->buf +
3984 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
3985 flen = le32toh(rx->flag) & 0xfff;
3986 if (flen > actlen - sizeof(*rx))
3987 goto fail;
3988
3989 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3990 /* XXX correct? */
3991 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
3992 noise = rx->noise;
3993
3994 if (ieee80211_radiotap_active(ic))
3995 mactime = rx->mactime;
3996 }
3997
3998 if (flen < IEEE80211_ACK_LEN)
3999 goto fail;
4000
4001 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
4002 if (mnew == NULL)
4003 goto fail;
4004
4005 m = data->m;
4006 data->m = mnew;
4007 data->buf = mtod(mnew, uint8_t *);
4008
4009 /* finalize mbuf */
4010 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4011
4012 if (ieee80211_radiotap_active(ic)) {
4013 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4014
4015 tap->wr_tsf = mactime;
4016 tap->wr_flags = 0;
4017 tap->wr_dbm_antsignal = (int8_t)rssi;
4018 }
4019
4020 wh = mtod(m, struct ieee80211_frame *);
4021 if (IEEE80211_IS_DATA(wh))
4022 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4023
4024 *rssi_p = rssi;
4025 *nf_p = noise; /* XXX correct? */
4026
4027 return (m);
4028
4029 fail:
4030 counter_u64_add(ic->ic_ierrors, 1);
4031 return (NULL);
4032 }
4033
4034 static void
urtw_bulk_rx_callback(struct usb_xfer * xfer,usb_error_t error)4035 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4036 {
4037 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4038 struct ieee80211com *ic = &sc->sc_ic;
4039 struct ieee80211_node *ni;
4040 struct mbuf *m = NULL;
4041 struct urtw_data *data;
4042 int8_t nf = -95;
4043 int rssi = 1;
4044
4045 URTW_ASSERT_LOCKED(sc);
4046
4047 switch (USB_GET_STATE(xfer)) {
4048 case USB_ST_TRANSFERRED:
4049 data = STAILQ_FIRST(&sc->sc_rx_active);
4050 if (data == NULL)
4051 goto setup;
4052 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4053 m = urtw_rxeof(xfer, data, &rssi, &nf);
4054 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4055 /* FALLTHROUGH */
4056 case USB_ST_SETUP:
4057 setup:
4058 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4059 if (data == NULL) {
4060 KASSERT(m == NULL, ("mbuf isn't NULL"));
4061 return;
4062 }
4063 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4064 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4065 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4066 usbd_xfer_max_len(xfer));
4067 usbd_transfer_submit(xfer);
4068
4069 /*
4070 * To avoid LOR we should unlock our private mutex here to call
4071 * ieee80211_input() because here is at the end of a USB
4072 * callback and safe to unlock.
4073 */
4074 URTW_UNLOCK(sc);
4075 if (m != NULL) {
4076 if (m->m_pkthdr.len >=
4077 sizeof(struct ieee80211_frame_min)) {
4078 ni = ieee80211_find_rxnode(ic,
4079 mtod(m, struct ieee80211_frame_min *));
4080 } else
4081 ni = NULL;
4082
4083 if (ni != NULL) {
4084 (void) ieee80211_input(ni, m, rssi, nf);
4085 /* node is no longer needed */
4086 ieee80211_free_node(ni);
4087 } else
4088 (void) ieee80211_input_all(ic, m, rssi, nf);
4089 m = NULL;
4090 }
4091 URTW_LOCK(sc);
4092 break;
4093 default:
4094 /* needs it to the inactive queue due to a error. */
4095 data = STAILQ_FIRST(&sc->sc_rx_active);
4096 if (data != NULL) {
4097 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4098 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4099 }
4100 if (error != USB_ERR_CANCELLED) {
4101 usbd_xfer_set_stall(xfer);
4102 counter_u64_add(ic->ic_ierrors, 1);
4103 goto setup;
4104 }
4105 break;
4106 }
4107 }
4108
4109 #define URTW_STATUS_TYPE_TXCLOSE 1
4110 #define URTW_STATUS_TYPE_BEACON_INTR 0
4111
4112 static void
urtw_txstatus_eof(struct usb_xfer * xfer)4113 urtw_txstatus_eof(struct usb_xfer *xfer)
4114 {
4115 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4116 struct ieee80211com *ic = &sc->sc_ic;
4117 int actlen, type, pktretry;
4118 uint64_t val;
4119
4120 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4121
4122 if (actlen != sizeof(uint64_t))
4123 return;
4124
4125 val = le64toh(sc->sc_txstatus);
4126 type = (val >> 30) & 0x3;
4127 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4128 pktretry = val & 0xff;
4129 if (pktretry == URTW_TX_MAXRETRY)
4130 counter_u64_add(ic->ic_oerrors, 1);
4131 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4132 pktretry, (val >> 16) & 0xff);
4133 }
4134 }
4135
4136 static void
urtw_bulk_tx_status_callback(struct usb_xfer * xfer,usb_error_t error)4137 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4138 {
4139 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4140 struct ieee80211com *ic = &sc->sc_ic;
4141 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0);
4142
4143 URTW_ASSERT_LOCKED(sc);
4144
4145 switch (USB_GET_STATE(xfer)) {
4146 case USB_ST_TRANSFERRED:
4147 urtw_txstatus_eof(xfer);
4148 /* FALLTHROUGH */
4149 case USB_ST_SETUP:
4150 setup:
4151 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t));
4152 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t));
4153 usbd_transfer_submit(xfer);
4154 break;
4155 default:
4156 if (error != USB_ERR_CANCELLED) {
4157 usbd_xfer_set_stall(xfer);
4158 counter_u64_add(ic->ic_ierrors, 1);
4159 goto setup;
4160 }
4161 break;
4162 }
4163 }
4164
4165 static void
urtw_txeof(struct usb_xfer * xfer,struct urtw_data * data)4166 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4167 {
4168 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4169
4170 URTW_ASSERT_LOCKED(sc);
4171
4172 if (data->m) {
4173 /* XXX status? */
4174 ieee80211_tx_complete(data->ni, data->m, 0);
4175 data->m = NULL;
4176 data->ni = NULL;
4177 }
4178 sc->sc_txtimer = 0;
4179 }
4180
4181 static void
urtw_bulk_tx_callback(struct usb_xfer * xfer,usb_error_t error)4182 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4183 {
4184 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4185 struct urtw_data *data;
4186
4187 URTW_ASSERT_LOCKED(sc);
4188
4189 switch (USB_GET_STATE(xfer)) {
4190 case USB_ST_TRANSFERRED:
4191 data = STAILQ_FIRST(&sc->sc_tx_active);
4192 if (data == NULL)
4193 goto setup;
4194 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4195 urtw_txeof(xfer, data);
4196 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4197 /* FALLTHROUGH */
4198 case USB_ST_SETUP:
4199 setup:
4200 data = STAILQ_FIRST(&sc->sc_tx_pending);
4201 if (data == NULL) {
4202 DPRINTF(sc, URTW_DEBUG_XMIT,
4203 "%s: empty pending queue\n", __func__);
4204 return;
4205 }
4206 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4207 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4208
4209 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4210 usbd_transfer_submit(xfer);
4211
4212 urtw_start(sc);
4213 break;
4214 default:
4215 data = STAILQ_FIRST(&sc->sc_tx_active);
4216 if (data == NULL)
4217 goto setup;
4218 if (data->ni != NULL) {
4219 if_inc_counter(data->ni->ni_vap->iv_ifp,
4220 IFCOUNTER_OERRORS, 1);
4221 ieee80211_free_node(data->ni);
4222 data->ni = NULL;
4223 }
4224 if (error != USB_ERR_CANCELLED) {
4225 usbd_xfer_set_stall(xfer);
4226 goto setup;
4227 }
4228 break;
4229 }
4230 }
4231
4232 static struct urtw_data *
_urtw_getbuf(struct urtw_softc * sc)4233 _urtw_getbuf(struct urtw_softc *sc)
4234 {
4235 struct urtw_data *bf;
4236
4237 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4238 if (bf != NULL)
4239 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4240 else
4241 bf = NULL;
4242 if (bf == NULL)
4243 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4244 "out of xmit buffers");
4245 return (bf);
4246 }
4247
4248 static struct urtw_data *
urtw_getbuf(struct urtw_softc * sc)4249 urtw_getbuf(struct urtw_softc *sc)
4250 {
4251 struct urtw_data *bf;
4252
4253 URTW_ASSERT_LOCKED(sc);
4254
4255 bf = _urtw_getbuf(sc);
4256 if (bf == NULL)
4257 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4258 return (bf);
4259 }
4260
4261 static int
urtw_isbmode(uint16_t rate)4262 urtw_isbmode(uint16_t rate)
4263 {
4264
4265 return ((rate <= 22 && rate != 12 && rate != 18) ||
4266 rate == 44) ? (1) : (0);
4267 }
4268
4269 static uint16_t
urtw_rate2dbps(uint16_t rate)4270 urtw_rate2dbps(uint16_t rate)
4271 {
4272
4273 switch(rate) {
4274 case 12:
4275 case 18:
4276 case 24:
4277 case 36:
4278 case 48:
4279 case 72:
4280 case 96:
4281 case 108:
4282 return (rate * 2);
4283 default:
4284 break;
4285 }
4286 return (24);
4287 }
4288
4289 static int
urtw_compute_txtime(uint16_t framelen,uint16_t rate,uint8_t ismgt,uint8_t isshort)4290 urtw_compute_txtime(uint16_t framelen, uint16_t rate,
4291 uint8_t ismgt, uint8_t isshort)
4292 {
4293 uint16_t ceiling, frametime, n_dbps;
4294
4295 if (urtw_isbmode(rate)) {
4296 if (ismgt || !isshort || rate == 2)
4297 frametime = (uint16_t)(144 + 48 +
4298 (framelen * 8 / (rate / 2)));
4299 else
4300 frametime = (uint16_t)(72 + 24 +
4301 (framelen * 8 / (rate / 2)));
4302 if ((framelen * 8 % (rate / 2)) != 0)
4303 frametime++;
4304 } else {
4305 n_dbps = urtw_rate2dbps(rate);
4306 ceiling = (16 + 8 * framelen + 6) / n_dbps
4307 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0);
4308 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6);
4309 }
4310 return (frametime);
4311 }
4312
4313 /*
4314 * Callback from the 802.11 layer to update the
4315 * slot time based on the current setting.
4316 */
4317 static void
urtw_updateslot(struct ieee80211com * ic)4318 urtw_updateslot(struct ieee80211com *ic)
4319 {
4320 struct urtw_softc *sc = ic->ic_softc;
4321
4322 ieee80211_runtask(ic, &sc->sc_updateslot_task);
4323 }
4324
4325 static void
urtw_updateslottask(void * arg,int pending)4326 urtw_updateslottask(void *arg, int pending)
4327 {
4328 struct urtw_softc *sc = arg;
4329 struct ieee80211com *ic = &sc->sc_ic;
4330 int error;
4331
4332 URTW_LOCK(sc);
4333 if ((sc->sc_flags & URTW_RUNNING) == 0) {
4334 URTW_UNLOCK(sc);
4335 return;
4336 }
4337 if (sc->sc_flags & URTW_RTL8187B) {
4338 urtw_write8_m(sc, URTW_SIFS, 0x22);
4339 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
4340 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT);
4341 else
4342 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT);
4343 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b);
4344 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b);
4345 } else {
4346 urtw_write8_m(sc, URTW_SIFS, 0x22);
4347 if (sc->sc_state == IEEE80211_S_ASSOC &&
4348 ic->ic_flags & IEEE80211_F_SHSLOT)
4349 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT);
4350 else
4351 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT);
4352 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
4353 urtw_write8_m(sc, URTW_DIFS, 0x14);
4354 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
4355 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
4356 } else {
4357 urtw_write8_m(sc, URTW_DIFS, 0x24);
4358 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
4359 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
4360 }
4361 }
4362 fail:
4363 URTW_UNLOCK(sc);
4364 }
4365
4366 static void
urtw_sysctl_node(struct urtw_softc * sc)4367 urtw_sysctl_node(struct urtw_softc *sc)
4368 {
4369 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \
4370 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
4371 struct sysctl_ctx_list *ctx;
4372 struct sysctl_oid_list *child, *parent;
4373 struct sysctl_oid *tree;
4374 struct urtw_stats *stats = &sc->sc_stats;
4375
4376 ctx = device_get_sysctl_ctx(sc->sc_dev);
4377 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
4378
4379 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
4380 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "URTW statistics");
4381 parent = SYSCTL_CHILDREN(tree);
4382
4383 /* Tx statistics. */
4384 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
4385 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
4386 child = SYSCTL_CHILDREN(tree);
4387 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0],
4388 "1 Mbit/s");
4389 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1],
4390 "2 Mbit/s");
4391 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2],
4392 "5.5 Mbit/s");
4393 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4],
4394 "6 Mbit/s");
4395 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5],
4396 "9 Mbit/s");
4397 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3],
4398 "11 Mbit/s");
4399 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6],
4400 "12 Mbit/s");
4401 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7],
4402 "18 Mbit/s");
4403 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8],
4404 "24 Mbit/s");
4405 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9],
4406 "36 Mbit/s");
4407 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10],
4408 "48 Mbit/s");
4409 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11],
4410 "54 Mbit/s");
4411 #undef URTW_SYSCTL_STAT_ADD32
4412 }
4413
4414 static device_method_t urtw_methods[] = {
4415 DEVMETHOD(device_probe, urtw_match),
4416 DEVMETHOD(device_attach, urtw_attach),
4417 DEVMETHOD(device_detach, urtw_detach),
4418 DEVMETHOD_END
4419 };
4420
4421 static driver_t urtw_driver = {
4422 .name = "urtw",
4423 .methods = urtw_methods,
4424 .size = sizeof(struct urtw_softc)
4425 };
4426
4427 DRIVER_MODULE(urtw, uhub, urtw_driver, NULL, NULL);
4428 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4429 MODULE_DEPEND(urtw, usb, 1, 1, 1);
4430 MODULE_VERSION(urtw, 1);
4431 USB_PNP_HOST_INFO(urtw_devs);
4432