1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_inet6.h" 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/condvar.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/sbuf.h> 38 #include <sys/socket.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 42 #include <net/if.h> 43 #include <net/if_var.h> 44 #include <net/if_media.h> 45 46 /* needed for checksum offload */ 47 #include <netinet/in.h> 48 #include <netinet/ip.h> 49 #ifdef INET6 50 #include <netinet/ip6.h> 51 #include <netinet6/ip6_var.h> 52 #endif 53 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include <dev/usb/usbdi_util.h> 60 #include "usbdevs.h" 61 62 #define USB_DEBUG_VAR ure_debug 63 #include <dev/usb/usb_debug.h> 64 #include <dev/usb/usb_process.h> 65 66 #include <dev/usb/net/usb_ethernet.h> 67 #include <dev/usb/net/if_urereg.h> 68 69 #include "miibus_if.h" 70 71 #ifdef USB_DEBUG 72 static int ure_debug = 0; 73 74 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 75 "USB ure"); 76 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 77 "Debug level"); 78 #endif 79 80 #ifdef USB_DEBUG_VAR 81 #ifdef USB_DEBUG 82 #define DEVPRINTFN(n,dev,fmt,...) do { \ 83 if ((USB_DEBUG_VAR) >= (n)) { \ 84 device_printf((dev), "%s: " fmt, \ 85 __FUNCTION__ ,##__VA_ARGS__); \ 86 } \ 87 } while (0) 88 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__) 89 #else 90 #define DEVPRINTF(...) do { } while (0) 91 #define DEVPRINTFN(...) do { } while (0) 92 #endif 93 #endif 94 95 /* 96 * Various supported device vendors/products. 97 */ 98 static const STRUCT_USB_HOST_ID ure_devs[] = { 99 #define URE_DEV(v,p,i) { \ 100 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \ 101 USB_IFACE_CLASS(UICLASS_VENDOR), \ 102 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) } 103 URE_DEV(ELECOM, EDCQUA3C, 0), 104 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153), 105 URE_DEV(LENOVO, TBT3LANGEN2, 0), 106 URE_DEV(LENOVO, ONELINK, 0), 107 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153), 108 URE_DEV(LENOVO, ONELINKPLUS, URE_FLAG_8153), 109 URE_DEV(LENOVO, USBCLAN, 0), 110 URE_DEV(LENOVO, USBCLANGEN2, 0), 111 URE_DEV(LENOVO, USBCLANHYBRID, 0), 112 URE_DEV(MICROSOFT, WINDEVETH, 0), 113 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153), 114 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 115 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153), 116 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153), 117 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156), 118 #undef URE_DEV 119 }; 120 121 static device_probe_t ure_probe; 122 static device_attach_t ure_attach; 123 static device_detach_t ure_detach; 124 125 static usb_callback_t ure_bulk_read_callback; 126 static usb_callback_t ure_bulk_write_callback; 127 128 static miibus_readreg_t ure_miibus_readreg; 129 static miibus_writereg_t ure_miibus_writereg; 130 static miibus_statchg_t ure_miibus_statchg; 131 132 static uether_fn_t ure_attach_post; 133 static uether_fn_t ure_init; 134 static uether_fn_t ure_stop; 135 static uether_fn_t ure_start; 136 static uether_fn_t ure_tick; 137 static uether_fn_t ure_rxfilter; 138 139 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 140 void *, int); 141 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 142 int); 143 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 144 int); 145 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 146 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 147 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 148 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 149 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 150 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 151 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 152 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 153 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t); 154 155 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS); 156 157 static void ure_read_chipver(struct ure_softc *); 158 static int ure_attach_post_sub(struct usb_ether *); 159 static void ure_reset(struct ure_softc *); 160 static int ure_ifmedia_upd(if_t); 161 static void ure_ifmedia_sts(if_t, struct ifmediareq *); 162 static void ure_add_media_types(struct ure_softc *); 163 static void ure_link_state(struct ure_softc *sc); 164 static int ure_get_link_status(struct ure_softc *); 165 static int ure_ioctl(if_t, u_long, caddr_t); 166 static void ure_rtl8152_init(struct ure_softc *); 167 static void ure_rtl8152_nic_reset(struct ure_softc *); 168 static void ure_rtl8153_init(struct ure_softc *); 169 static void ure_rtl8153b_init(struct ure_softc *); 170 static void ure_rtl8153b_nic_reset(struct ure_softc *); 171 static void ure_disable_teredo(struct ure_softc *); 172 static void ure_enable_aldps(struct ure_softc *, bool); 173 static uint16_t ure_phy_status(struct ure_softc *, uint16_t); 174 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m); 175 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout); 176 177 static device_method_t ure_methods[] = { 178 /* Device interface. */ 179 DEVMETHOD(device_probe, ure_probe), 180 DEVMETHOD(device_attach, ure_attach), 181 DEVMETHOD(device_detach, ure_detach), 182 183 /* MII interface. */ 184 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 185 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 186 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 187 188 DEVMETHOD_END 189 }; 190 191 static driver_t ure_driver = { 192 .name = "ure", 193 .methods = ure_methods, 194 .size = sizeof(struct ure_softc), 195 }; 196 197 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL); 198 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL); 199 MODULE_DEPEND(ure, uether, 1, 1, 1); 200 MODULE_DEPEND(ure, usb, 1, 1, 1); 201 MODULE_DEPEND(ure, ether, 1, 1, 1); 202 MODULE_DEPEND(ure, miibus, 1, 1, 1); 203 MODULE_VERSION(ure, 1); 204 USB_PNP_HOST_INFO(ure_devs); 205 206 static const struct usb_ether_methods ure_ue_methods = { 207 .ue_attach_post = ure_attach_post, 208 .ue_attach_post_sub = ure_attach_post_sub, 209 .ue_start = ure_start, 210 .ue_init = ure_init, 211 .ue_stop = ure_stop, 212 .ue_tick = ure_tick, 213 .ue_setmulti = ure_rxfilter, 214 .ue_setpromisc = ure_rxfilter, 215 .ue_mii_upd = ure_ifmedia_upd, 216 .ue_mii_sts = ure_ifmedia_sts, 217 }; 218 219 #define URE_SETBIT_1(sc, reg, index, x) \ 220 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 221 #define URE_SETBIT_2(sc, reg, index, x) \ 222 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 223 #define URE_SETBIT_4(sc, reg, index, x) \ 224 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 225 226 #define URE_CLRBIT_1(sc, reg, index, x) \ 227 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 228 #define URE_CLRBIT_2(sc, reg, index, x) \ 229 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 230 #define URE_CLRBIT_4(sc, reg, index, x) \ 231 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 232 233 static int 234 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 235 void *buf, int len) 236 { 237 struct usb_device_request req; 238 239 URE_LOCK_ASSERT(sc, MA_OWNED); 240 241 if (rw == URE_CTL_WRITE) 242 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 243 else 244 req.bmRequestType = UT_READ_VENDOR_DEVICE; 245 req.bRequest = UR_SET_ADDRESS; 246 USETW(req.wValue, val); 247 USETW(req.wIndex, index); 248 USETW(req.wLength, len); 249 250 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 251 } 252 253 static int 254 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 255 void *buf, int len) 256 { 257 258 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 259 } 260 261 static int 262 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 263 void *buf, int len) 264 { 265 266 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 267 } 268 269 static uint8_t 270 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 271 { 272 uint32_t val; 273 uint8_t temp[4]; 274 uint8_t shift; 275 276 shift = (reg & 3) << 3; 277 reg &= ~3; 278 279 ure_read_mem(sc, reg, index, &temp, 4); 280 val = UGETDW(temp); 281 val >>= shift; 282 283 return (val & 0xff); 284 } 285 286 static uint16_t 287 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 288 { 289 uint32_t val; 290 uint8_t temp[4]; 291 uint8_t shift; 292 293 shift = (reg & 2) << 3; 294 reg &= ~3; 295 296 ure_read_mem(sc, reg, index, &temp, 4); 297 val = UGETDW(temp); 298 val >>= shift; 299 300 return (val & 0xffff); 301 } 302 303 static uint32_t 304 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 305 { 306 uint8_t temp[4]; 307 308 ure_read_mem(sc, reg, index, &temp, 4); 309 return (UGETDW(temp)); 310 } 311 312 static int 313 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 314 { 315 uint16_t byen; 316 uint8_t temp[4]; 317 uint8_t shift; 318 319 byen = URE_BYTE_EN_BYTE; 320 shift = reg & 3; 321 val &= 0xff; 322 323 if (reg & 3) { 324 byen <<= shift; 325 val <<= (shift << 3); 326 reg &= ~3; 327 } 328 329 USETDW(temp, val); 330 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 331 } 332 333 static int 334 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 335 { 336 uint16_t byen; 337 uint8_t temp[4]; 338 uint8_t shift; 339 340 byen = URE_BYTE_EN_WORD; 341 shift = reg & 2; 342 val &= 0xffff; 343 344 if (reg & 2) { 345 byen <<= shift; 346 val <<= (shift << 3); 347 reg &= ~3; 348 } 349 350 USETDW(temp, val); 351 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 352 } 353 354 static int 355 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 356 { 357 uint8_t temp[4]; 358 359 USETDW(temp, val); 360 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 361 } 362 363 static uint16_t 364 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 365 { 366 uint16_t reg; 367 368 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 369 reg = (addr & 0x0fff) | 0xb000; 370 371 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 372 } 373 374 static void 375 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 376 { 377 uint16_t reg; 378 379 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 380 reg = (addr & 0x0fff) | 0xb000; 381 382 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 383 } 384 385 static void 386 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 387 { 388 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr); 389 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data); 390 } 391 392 static int 393 ure_miibus_readreg(device_t dev, int phy, int reg) 394 { 395 struct ure_softc *sc; 396 uint16_t val; 397 int locked; 398 399 sc = device_get_softc(dev); 400 locked = mtx_owned(&sc->sc_mtx); 401 if (!locked) 402 URE_LOCK(sc); 403 404 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 405 if (reg == URE_GMEDIASTAT) { 406 if (!locked) 407 URE_UNLOCK(sc); 408 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 409 } 410 411 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 412 413 if (!locked) 414 URE_UNLOCK(sc); 415 return (val); 416 } 417 418 static int 419 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 420 { 421 struct ure_softc *sc; 422 int locked; 423 424 sc = device_get_softc(dev); 425 if (sc->sc_phyno != phy) 426 return (0); 427 428 locked = mtx_owned(&sc->sc_mtx); 429 if (!locked) 430 URE_LOCK(sc); 431 432 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 433 434 if (!locked) 435 URE_UNLOCK(sc); 436 return (0); 437 } 438 439 static void 440 ure_miibus_statchg(device_t dev) 441 { 442 struct ure_softc *sc; 443 struct mii_data *mii; 444 if_t ifp; 445 int locked; 446 447 sc = device_get_softc(dev); 448 mii = GET_MII(sc); 449 locked = mtx_owned(&sc->sc_mtx); 450 if (!locked) 451 URE_LOCK(sc); 452 453 ifp = uether_getifp(&sc->sc_ue); 454 if (mii == NULL || ifp == NULL || 455 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 456 goto done; 457 458 sc->sc_flags &= ~URE_FLAG_LINK; 459 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 460 (IFM_ACTIVE | IFM_AVALID)) { 461 switch (IFM_SUBTYPE(mii->mii_media_active)) { 462 case IFM_10_T: 463 case IFM_100_TX: 464 sc->sc_flags |= URE_FLAG_LINK; 465 sc->sc_rxstarted = 0; 466 break; 467 case IFM_1000_T: 468 if ((sc->sc_flags & URE_FLAG_8152) != 0) 469 break; 470 sc->sc_flags |= URE_FLAG_LINK; 471 sc->sc_rxstarted = 0; 472 break; 473 default: 474 break; 475 } 476 } 477 478 /* Lost link, do nothing. */ 479 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 480 goto done; 481 done: 482 if (!locked) 483 URE_UNLOCK(sc); 484 } 485 486 /* 487 * Probe for a RTL8152/RTL8153/RTL8156 chip. 488 */ 489 static int 490 ure_probe(device_t dev) 491 { 492 struct usb_attach_arg *uaa; 493 494 uaa = device_get_ivars(dev); 495 if (uaa->usb_mode != USB_MODE_HOST) 496 return (ENXIO); 497 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 498 return (ENXIO); 499 500 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 501 } 502 503 /* 504 * Attach the interface. Allocate softc structures, do ifmedia 505 * setup and ethernet/BPF attach. 506 */ 507 static int 508 ure_attach(device_t dev) 509 { 510 struct usb_attach_arg *uaa = device_get_ivars(dev); 511 struct ure_softc *sc = device_get_softc(dev); 512 struct usb_ether *ue = &sc->sc_ue; 513 struct usb_config ure_config_rx[URE_MAX_RX]; 514 struct usb_config ure_config_tx[URE_MAX_TX]; 515 uint8_t iface_index; 516 int error; 517 int i; 518 519 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 520 device_set_usb_desc(dev); 521 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 522 523 iface_index = URE_IFACE_IDX; 524 525 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B)) 526 sc->sc_rxbufsz = URE_8153_RX_BUFSZ; 527 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 528 sc->sc_rxbufsz = URE_8156_RX_BUFSZ; 529 else 530 sc->sc_rxbufsz = URE_8152_RX_BUFSZ; 531 532 for (i = 0; i < URE_MAX_RX; i++) { 533 ure_config_rx[i] = (struct usb_config) { 534 .type = UE_BULK, 535 .endpoint = UE_ADDR_ANY, 536 .direction = UE_DIR_IN, 537 .bufsize = sc->sc_rxbufsz, 538 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 539 .callback = ure_bulk_read_callback, 540 .timeout = 0, /* no timeout */ 541 }; 542 } 543 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer, 544 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx); 545 if (error != 0) { 546 device_printf(dev, "allocating USB RX transfers failed\n"); 547 goto detach; 548 } 549 550 for (i = 0; i < URE_MAX_TX; i++) { 551 ure_config_tx[i] = (struct usb_config) { 552 .type = UE_BULK, 553 .endpoint = UE_ADDR_ANY, 554 .direction = UE_DIR_OUT, 555 .bufsize = URE_TX_BUFSZ, 556 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 557 .callback = ure_bulk_write_callback, 558 .timeout = 10000, /* 10 seconds */ 559 }; 560 } 561 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer, 562 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx); 563 if (error != 0) { 564 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 565 device_printf(dev, "allocating USB TX transfers failed\n"); 566 goto detach; 567 } 568 569 ue->ue_sc = sc; 570 ue->ue_dev = dev; 571 ue->ue_udev = uaa->device; 572 ue->ue_mtx = &sc->sc_mtx; 573 ue->ue_methods = &ure_ue_methods; 574 575 error = uether_ifattach(ue); 576 if (error != 0) { 577 device_printf(dev, "could not attach interface\n"); 578 goto detach; 579 } 580 return (0); /* success */ 581 582 detach: 583 ure_detach(dev); 584 return (ENXIO); /* failure */ 585 } 586 587 static int 588 ure_detach(device_t dev) 589 { 590 struct ure_softc *sc = device_get_softc(dev); 591 struct usb_ether *ue = &sc->sc_ue; 592 593 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX); 594 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 595 uether_ifdetach(ue); 596 mtx_destroy(&sc->sc_mtx); 597 598 return (0); 599 } 600 601 /* 602 * Copy from USB buffers to a new mbuf chain with pkt header. 603 * 604 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf 605 * clusters as necessary. 606 */ 607 static struct mbuf * 608 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, 609 usb_frlength_t len) 610 { 611 struct usb_page_search_res; 612 struct mbuf *m, *mb; 613 usb_frlength_t tlen; 614 615 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR); 616 if (m == NULL) 617 return (m); 618 619 /* uether_newbuf does this. */ 620 m_adj(m, ETHER_ALIGN); 621 622 m->m_pkthdr.len = len; 623 624 for (mb = m; len > 0; mb = mb->m_next) { 625 tlen = MIN(len, M_TRAILINGSPACE(mb)); 626 627 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen); 628 mb->m_len = tlen; 629 630 offset += tlen; 631 len -= tlen; 632 } 633 634 return (m); 635 } 636 637 static void 638 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 639 { 640 struct ure_softc *sc = usbd_xfer_softc(xfer); 641 struct usb_ether *ue = &sc->sc_ue; 642 if_t ifp = uether_getifp(ue); 643 struct usb_page_cache *pc; 644 struct mbuf *m; 645 struct ure_rxpkt pkt; 646 int actlen, off, len; 647 int caps; 648 uint32_t pktcsum; 649 650 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 651 652 switch (USB_GET_STATE(xfer)) { 653 case USB_ST_TRANSFERRED: 654 off = 0; 655 pc = usbd_xfer_get_frame(xfer, 0); 656 caps = if_getcapenable(ifp); 657 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n"); 658 while (actlen > 0) { 659 if (actlen < (int)(sizeof(pkt))) { 660 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 661 goto tr_setup; 662 } 663 usbd_copy_out(pc, off, &pkt, sizeof(pkt)); 664 665 off += sizeof(pkt); 666 actlen -= sizeof(pkt); 667 668 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 669 670 DEVPRINTFN(13, sc->sc_ue.ue_dev, 671 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n", 672 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc, 673 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4); 674 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len); 675 676 if (len >= URE_RXPKT_LEN_MASK) { 677 /* 678 * drop the rest of this segment. With out 679 * more information, we cannot know where next 680 * packet starts. Blindly continuing would 681 * cause a packet in packet attack, allowing 682 * one VLAN to inject packets w/o a VLAN tag, 683 * or injecting packets into other VLANs. 684 */ 685 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 686 goto tr_setup; 687 } 688 689 if (actlen < len) { 690 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 691 goto tr_setup; 692 } 693 694 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN)) 695 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN); 696 else 697 m = NULL; 698 if (m == NULL) { 699 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 700 } else { 701 /* make mbuf and queue */ 702 pktcsum = le32toh(pkt.ure_csum); 703 if (caps & IFCAP_VLAN_HWTAGGING && 704 pktcsum & URE_RXPKT_RX_VLAN_TAG) { 705 m->m_pkthdr.ether_vtag = 706 bswap16(pktcsum & 707 URE_RXPKT_VLAN_MASK); 708 m->m_flags |= M_VLANTAG; 709 } 710 711 /* set the necessary flags for rx checksum */ 712 ure_rxcsum(caps, &pkt, m); 713 714 /* 715 * len has been known to be bogus at times, 716 * which leads to problems when passed to 717 * uether_rxmbuf(). Better understanding why we 718 * can get there make for good future work. 719 */ 720 uether_rxmbuf(ue, m, 0); 721 } 722 723 off += roundup(len, URE_RXPKT_ALIGN); 724 actlen -= roundup(len, URE_RXPKT_ALIGN); 725 } 726 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n"); 727 728 /* FALLTHROUGH */ 729 case USB_ST_SETUP: 730 tr_setup: 731 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 732 usbd_transfer_submit(xfer); 733 uether_rxflush(ue); 734 return; 735 736 default: /* Error */ 737 DPRINTF("bulk read error, %s\n", 738 usbd_errstr(error)); 739 740 if (error != USB_ERR_CANCELLED) { 741 /* try to clear stall first */ 742 usbd_xfer_set_stall(xfer); 743 goto tr_setup; 744 } 745 return; 746 } 747 } 748 749 static void 750 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 751 { 752 struct ure_softc *sc = usbd_xfer_softc(xfer); 753 if_t ifp = uether_getifp(&sc->sc_ue); 754 struct usb_page_cache *pc; 755 struct mbuf *m; 756 struct ure_txpkt txpkt; 757 uint32_t regtmp; 758 int len, pos; 759 int rem; 760 int caps; 761 762 switch (USB_GET_STATE(xfer)) { 763 case USB_ST_TRANSFERRED: 764 DPRINTFN(11, "transfer complete\n"); 765 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 766 767 /* FALLTHROUGH */ 768 case USB_ST_SETUP: 769 tr_setup: 770 if ((sc->sc_flags & URE_FLAG_LINK) == 0) { 771 /* don't send anything if there is no link! */ 772 break; 773 } 774 775 pc = usbd_xfer_get_frame(xfer, 0); 776 caps = if_getcapenable(ifp); 777 778 pos = 0; 779 rem = URE_TX_BUFSZ; 780 while (rem > sizeof(txpkt)) { 781 m = if_dequeue(ifp); 782 if (m == NULL) 783 break; 784 785 /* 786 * make sure we don't ever send too large of a 787 * packet 788 */ 789 len = m->m_pkthdr.len; 790 if ((len & URE_TXPKT_LEN_MASK) != len) { 791 device_printf(sc->sc_ue.ue_dev, 792 "pkt len too large: %#x", len); 793 pkterror: 794 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 795 m_freem(m); 796 continue; 797 } 798 799 if (sizeof(txpkt) + 800 roundup(len, URE_TXPKT_ALIGN) > rem) { 801 /* out of space */ 802 if_sendq_prepend(ifp, m); 803 m = NULL; 804 break; 805 } 806 807 txpkt = (struct ure_txpkt){}; 808 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 809 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 810 if (m->m_flags & M_VLANTAG) { 811 txpkt.ure_csum = htole32( 812 bswap16(m->m_pkthdr.ether_vtag & 813 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN); 814 } 815 if (ure_txcsum(m, caps, ®tmp)) { 816 device_printf(sc->sc_ue.ue_dev, 817 "pkt l4 off too large"); 818 goto pkterror; 819 } 820 txpkt.ure_csum |= htole32(regtmp); 821 822 DEVPRINTFN(13, sc->sc_ue.ue_dev, 823 "txpkt: mbflg: %#x, %#x, %#x\n", 824 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen), 825 le32toh(txpkt.ure_csum)); 826 827 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 828 829 pos += sizeof(txpkt); 830 rem -= sizeof(txpkt); 831 832 usbd_m_copy_in(pc, pos, m, 0, len); 833 834 pos += roundup(len, URE_TXPKT_ALIGN); 835 rem -= roundup(len, URE_TXPKT_ALIGN); 836 837 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 838 839 /* 840 * If there's a BPF listener, bounce a copy 841 * of this frame to him. 842 */ 843 BPF_MTAP(ifp, m); 844 845 m_freem(m); 846 } 847 848 /* no packets to send */ 849 if (pos == 0) 850 break; 851 852 /* Set frame length. */ 853 usbd_xfer_set_frame_len(xfer, 0, pos); 854 855 usbd_transfer_submit(xfer); 856 857 return; 858 859 default: /* Error */ 860 DPRINTFN(11, "transfer error, %s\n", 861 usbd_errstr(error)); 862 863 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 864 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 865 866 if (error == USB_ERR_TIMEOUT) { 867 DEVPRINTFN(12, sc->sc_ue.ue_dev, 868 "pkt tx timeout\n"); 869 } 870 871 if (error != USB_ERR_CANCELLED) { 872 /* try to clear stall first */ 873 usbd_xfer_set_stall(xfer); 874 goto tr_setup; 875 } 876 } 877 } 878 879 static void 880 ure_read_chipver(struct ure_softc *sc) 881 { 882 uint16_t ver; 883 884 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 885 sc->sc_ver = ver; 886 switch (ver) { 887 case 0x4c00: 888 sc->sc_chip |= URE_CHIP_VER_4C00; 889 sc->sc_flags = URE_FLAG_8152; 890 break; 891 case 0x4c10: 892 sc->sc_chip |= URE_CHIP_VER_4C10; 893 sc->sc_flags = URE_FLAG_8152; 894 break; 895 case 0x5c00: 896 sc->sc_chip |= URE_CHIP_VER_5C00; 897 sc->sc_flags = URE_FLAG_8153; 898 break; 899 case 0x5c10: 900 sc->sc_chip |= URE_CHIP_VER_5C10; 901 sc->sc_flags = URE_FLAG_8153; 902 break; 903 case 0x5c20: 904 sc->sc_chip |= URE_CHIP_VER_5C20; 905 sc->sc_flags = URE_FLAG_8153; 906 break; 907 case 0x5c30: 908 sc->sc_chip |= URE_CHIP_VER_5C30; 909 sc->sc_flags = URE_FLAG_8153; 910 break; 911 case 0x6000: 912 sc->sc_flags = URE_FLAG_8153B; 913 sc->sc_chip |= URE_CHIP_VER_6000; 914 break; 915 case 0x6010: 916 sc->sc_flags = URE_FLAG_8153B; 917 sc->sc_chip |= URE_CHIP_VER_6010; 918 break; 919 case 0x7020: 920 sc->sc_flags = URE_FLAG_8156; 921 sc->sc_chip |= URE_CHIP_VER_7020; 922 break; 923 case 0x7030: 924 sc->sc_flags = URE_FLAG_8156; 925 sc->sc_chip |= URE_CHIP_VER_7030; 926 break; 927 case 0x7400: 928 sc->sc_flags = URE_FLAG_8156B; 929 sc->sc_chip |= URE_CHIP_VER_7400; 930 break; 931 case 0x7410: 932 sc->sc_flags = URE_FLAG_8156B; 933 sc->sc_chip |= URE_CHIP_VER_7410; 934 break; 935 default: 936 device_printf(sc->sc_ue.ue_dev, 937 "unknown version 0x%04x\n", ver); 938 break; 939 } 940 } 941 942 static int 943 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS) 944 { 945 struct sbuf sb; 946 struct ure_softc *sc = arg1; 947 int error; 948 949 sbuf_new_for_sysctl(&sb, NULL, 0, req); 950 951 sbuf_printf(&sb, "%04x", sc->sc_ver); 952 953 error = sbuf_finish(&sb); 954 sbuf_delete(&sb); 955 956 return (error); 957 } 958 959 static void 960 ure_attach_post(struct usb_ether *ue) 961 { 962 struct ure_softc *sc = uether_getsc(ue); 963 964 sc->sc_rxstarted = 0; 965 sc->sc_phyno = 0; 966 967 /* Determine the chip version. */ 968 ure_read_chipver(sc); 969 970 /* Initialize controller and get station address. */ 971 if (sc->sc_flags & URE_FLAG_8152) 972 ure_rtl8152_init(sc); 973 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 974 ure_rtl8153b_init(sc); 975 else 976 ure_rtl8153_init(sc); 977 978 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 979 (sc->sc_chip & URE_CHIP_VER_4C10)) 980 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 981 ue->ue_eaddr, 8); 982 else 983 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 984 ue->ue_eaddr, 8); 985 986 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 987 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 988 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 989 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 990 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 991 } 992 } 993 994 static int 995 ure_attach_post_sub(struct usb_ether *ue) 996 { 997 struct sysctl_ctx_list *sctx; 998 struct sysctl_oid *soid; 999 struct ure_softc *sc; 1000 if_t ifp; 1001 int error; 1002 1003 sc = uether_getsc(ue); 1004 ifp = ue->ue_ifp; 1005 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1006 if_setstartfn(ifp, uether_start); 1007 if_setioctlfn(ifp, ure_ioctl); 1008 if_setinitfn(ifp, uether_init); 1009 /* 1010 * Try to keep two transfers full at a time. 1011 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight) 1012 */ 1013 if_setsendqlen(ifp, 512); 1014 if_setsendqready(ifp); 1015 1016 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1017 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 1018 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0); 1019 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 1020 #ifdef INET6 1021 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0); 1022 if_sethwassistbits(ifp, CSUM_IP6_UDP|CSUM_IP6_TCP, 0); 1023 #endif 1024 if_setcapenable(ifp, if_getcapabilities(ifp)); 1025 1026 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1027 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1028 ure_ifmedia_sts); 1029 ure_add_media_types(sc); 1030 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1031 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 1032 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 1033 error = 0; 1034 } else { 1035 bus_topo_lock(); 1036 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1037 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1038 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1039 bus_topo_unlock(); 1040 } 1041 1042 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev); 1043 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev); 1044 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver", 1045 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1046 ure_sysctl_chipver, "A", 1047 "Return string with chip version."); 1048 1049 return (error); 1050 } 1051 1052 static void 1053 ure_init(struct usb_ether *ue) 1054 { 1055 struct ure_softc *sc = uether_getsc(ue); 1056 if_t ifp = uether_getifp(ue); 1057 uint16_t cpcr; 1058 uint32_t reg; 1059 1060 URE_LOCK_ASSERT(sc, MA_OWNED); 1061 1062 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1063 return; 1064 1065 /* Cancel pending I/O. */ 1066 ure_stop(ue); 1067 1068 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1069 ure_rtl8153b_nic_reset(sc); 1070 else 1071 ure_reset(sc); 1072 1073 /* Set MAC address. */ 1074 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1075 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 1076 if_getlladdr(ifp), 8); 1077 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1078 1079 /* Set RX EARLY timeout and size */ 1080 if (sc->sc_flags & URE_FLAG_8153) { 1081 switch (usbd_get_speed(sc->sc_ue.ue_udev)) { 1082 case USB_SPEED_SUPER: 1083 reg = URE_COALESCE_SUPER / 8; 1084 break; 1085 case USB_SPEED_HIGH: 1086 reg = URE_COALESCE_HIGH / 8; 1087 break; 1088 default: 1089 reg = URE_COALESCE_SLOW / 8; 1090 break; 1091 } 1092 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg); 1093 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1094 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1095 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4); 1096 } else if (sc->sc_flags & URE_FLAG_8153B) { 1097 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158); 1098 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1099 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1100 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1101 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1102 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1103 URE_OWN_UPDATE | URE_OWN_CLEAR); 1104 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1105 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80); 1106 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1107 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1108 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1109 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1110 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1111 URE_OWN_UPDATE | URE_OWN_CLEAR); 1112 } 1113 1114 if (sc->sc_flags & URE_FLAG_8156B) { 1115 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1116 uether_pause(&sc->sc_ue, hz / 500); 1117 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1118 } 1119 1120 /* Reset the packet filter. */ 1121 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1122 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1123 1124 /* Enable RX VLANs if enabled */ 1125 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 1126 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1127 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n"); 1128 cpcr |= URE_CPCR_RX_VLAN; 1129 } else { 1130 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n"); 1131 cpcr &= ~URE_CPCR_RX_VLAN; 1132 } 1133 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr); 1134 1135 /* Enable transmit and receive. */ 1136 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1137 1138 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1139 1140 /* Configure RX filters. */ 1141 ure_rxfilter(ue); 1142 1143 usbd_xfer_set_stall(sc->sc_tx_xfer[0]); 1144 1145 /* Indicate we are up and running. */ 1146 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1147 1148 /* Switch to selected media. */ 1149 ure_ifmedia_upd(ifp); 1150 } 1151 1152 static void 1153 ure_tick(struct usb_ether *ue) 1154 { 1155 struct ure_softc *sc = uether_getsc(ue); 1156 if_t ifp = uether_getifp(ue); 1157 struct mii_data *mii; 1158 1159 URE_LOCK_ASSERT(sc, MA_OWNED); 1160 1161 (void)ifp; 1162 for (int i = 0; i < URE_MAX_RX; i++) 1163 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1164 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i])); 1165 1166 for (int i = 0; i < URE_MAX_TX; i++) 1167 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1168 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i])); 1169 1170 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1171 ure_link_state(sc); 1172 } else { 1173 mii = GET_MII(sc); 1174 mii_tick(mii); 1175 if ((sc->sc_flags & URE_FLAG_LINK) == 0 1176 && mii->mii_media_status & IFM_ACTIVE && 1177 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1178 sc->sc_flags |= URE_FLAG_LINK; 1179 sc->sc_rxstarted = 0; 1180 ure_start(ue); 1181 } 1182 } 1183 } 1184 1185 static u_int 1186 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1187 { 1188 uint32_t h, *hashes = arg; 1189 1190 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 1191 if (h < 32) 1192 hashes[0] |= (1 << h); 1193 else 1194 hashes[1] |= (1 << (h - 32)); 1195 return (1); 1196 } 1197 1198 /* 1199 * Program the 64-bit multicast hash filter. 1200 */ 1201 static void 1202 ure_rxfilter(struct usb_ether *ue) 1203 { 1204 struct ure_softc *sc = uether_getsc(ue); 1205 if_t ifp = uether_getifp(ue); 1206 uint32_t rxmode; 1207 uint32_t h, hashes[2] = { 0, 0 }; 1208 1209 URE_LOCK_ASSERT(sc, MA_OWNED); 1210 1211 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 1212 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 1213 rxmode |= URE_RCR_APM; /* accept physical match packets */ 1214 rxmode |= URE_RCR_AB; /* always accept broadcasts */ 1215 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 1216 if (if_getflags(ifp) & IFF_PROMISC) 1217 rxmode |= URE_RCR_AAP; 1218 rxmode |= URE_RCR_AM; 1219 hashes[0] = hashes[1] = 0xffffffff; 1220 goto done; 1221 } 1222 1223 /* calculate multicast masks */ 1224 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 1225 1226 h = bswap32(hashes[0]); 1227 hashes[0] = bswap32(hashes[1]); 1228 hashes[1] = h; 1229 rxmode |= URE_RCR_AM; /* accept multicast packets */ 1230 1231 done: 1232 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n", 1233 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1234 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 1235 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 1236 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 1237 } 1238 1239 static void 1240 ure_start(struct usb_ether *ue) 1241 { 1242 struct ure_softc *sc = uether_getsc(ue); 1243 unsigned i; 1244 1245 URE_LOCK_ASSERT(sc, MA_OWNED); 1246 1247 if (!sc->sc_rxstarted) { 1248 sc->sc_rxstarted = 1; 1249 for (i = 0; i != URE_MAX_RX; i++) 1250 usbd_transfer_start(sc->sc_rx_xfer[i]); 1251 } 1252 1253 for (i = 0; i != URE_MAX_TX; i++) 1254 usbd_transfer_start(sc->sc_tx_xfer[i]); 1255 } 1256 1257 static void 1258 ure_reset(struct ure_softc *sc) 1259 { 1260 int i; 1261 1262 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 1263 1264 for (i = 0; i < URE_TIMEOUT; i++) { 1265 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 1266 URE_CR_RST)) 1267 break; 1268 uether_pause(&sc->sc_ue, hz / 100); 1269 } 1270 if (i == URE_TIMEOUT) 1271 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 1272 } 1273 1274 /* 1275 * Set media options. 1276 */ 1277 static int 1278 ure_ifmedia_upd(if_t ifp) 1279 { 1280 struct ure_softc *sc = if_getsoftc(ifp); 1281 struct ifmedia *ifm; 1282 struct mii_data *mii; 1283 struct mii_softc *miisc; 1284 int gig; 1285 int reg; 1286 int anar; 1287 int locked; 1288 int error; 1289 1290 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1291 ifm = &sc->sc_ifmedia; 1292 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1293 return (EINVAL); 1294 1295 locked = mtx_owned(&sc->sc_mtx); 1296 if (!locked) 1297 URE_LOCK(sc); 1298 reg = ure_ocp_reg_read(sc, 0xa5d4); 1299 reg &= ~URE_ADV_2500TFDX; 1300 1301 anar = gig = 0; 1302 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1303 case IFM_AUTO: 1304 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1305 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1306 reg |= URE_ADV_2500TFDX; 1307 break; 1308 case IFM_2500_T: 1309 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1310 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1311 reg |= URE_ADV_2500TFDX; 1312 if_setbaudrate(ifp, IF_Mbps(2500)); 1313 break; 1314 case IFM_1000_T: 1315 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1316 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1317 if_setbaudrate(ifp, IF_Gbps(1)); 1318 break; 1319 case IFM_100_TX: 1320 anar |= ANAR_TX | ANAR_TX_FD; 1321 if_setbaudrate(ifp, IF_Mbps(100)); 1322 break; 1323 case IFM_10_T: 1324 anar |= ANAR_10 | ANAR_10_FD; 1325 if_setbaudrate(ifp, IF_Mbps(10)); 1326 break; 1327 default: 1328 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n"); 1329 if (!locked) 1330 URE_UNLOCK(sc); 1331 return (EINVAL); 1332 } 1333 1334 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 1335 anar | ANAR_PAUSE_ASYM | ANAR_FC); 1336 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 1337 ure_ocp_reg_write(sc, 0xa5d4, reg); 1338 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 1339 BMCR_AUTOEN | BMCR_STARTNEG); 1340 if (!locked) 1341 URE_UNLOCK(sc); 1342 return (0); 1343 } 1344 1345 mii = GET_MII(sc); 1346 1347 URE_LOCK_ASSERT(sc, MA_OWNED); 1348 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1349 PHY_RESET(miisc); 1350 error = mii_mediachg(mii); 1351 return (error); 1352 } 1353 1354 /* 1355 * Report current media status. 1356 */ 1357 static void 1358 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1359 { 1360 struct ure_softc *sc; 1361 struct mii_data *mii; 1362 uint16_t status; 1363 1364 sc = if_getsoftc(ifp); 1365 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1366 URE_LOCK(sc); 1367 ifmr->ifm_status = IFM_AVALID; 1368 if (ure_get_link_status(sc)) { 1369 ifmr->ifm_status |= IFM_ACTIVE; 1370 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 1371 URE_MCU_TYPE_PLA); 1372 if ((status & URE_PHYSTATUS_FDX) || 1373 (status & URE_PHYSTATUS_2500MBPS)) 1374 ifmr->ifm_active |= IFM_FDX; 1375 else 1376 ifmr->ifm_active |= IFM_HDX; 1377 if (status & URE_PHYSTATUS_10MBPS) 1378 ifmr->ifm_active |= IFM_10_T; 1379 else if (status & URE_PHYSTATUS_100MBPS) 1380 ifmr->ifm_active |= IFM_100_TX; 1381 else if (status & URE_PHYSTATUS_1000MBPS) 1382 ifmr->ifm_active |= IFM_1000_T; 1383 else if (status & URE_PHYSTATUS_2500MBPS) 1384 ifmr->ifm_active |= IFM_2500_T; 1385 } 1386 URE_UNLOCK(sc); 1387 return; 1388 } 1389 1390 mii = GET_MII(sc); 1391 1392 URE_LOCK(sc); 1393 mii_pollstat(mii); 1394 ifmr->ifm_active = mii->mii_media_active; 1395 ifmr->ifm_status = mii->mii_media_status; 1396 URE_UNLOCK(sc); 1397 } 1398 1399 static void 1400 ure_add_media_types(struct ure_softc *sc) 1401 { 1402 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1403 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1404 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1405 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1406 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1407 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); 1408 } 1409 1410 static void 1411 ure_link_state(struct ure_softc *sc) 1412 { 1413 if_t ifp = uether_getifp(&sc->sc_ue); 1414 1415 if (ure_get_link_status(sc)) { 1416 if (if_getlinkstate(ifp) != LINK_STATE_UP) { 1417 if_link_state_change(ifp, LINK_STATE_UP); 1418 /* Enable transmit and receive. */ 1419 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1420 1421 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1422 URE_PHYSTATUS_2500MBPS) 1423 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1424 else 1425 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1426 } 1427 } else { 1428 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) { 1429 if_link_state_change(ifp, LINK_STATE_DOWN); 1430 } 1431 } 1432 } 1433 1434 static int 1435 ure_get_link_status(struct ure_softc *sc) 1436 { 1437 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1438 URE_PHYSTATUS_LINK) { 1439 sc->sc_flags |= URE_FLAG_LINK; 1440 return (1); 1441 } else { 1442 sc->sc_flags &= ~URE_FLAG_LINK; 1443 return (0); 1444 } 1445 } 1446 1447 static int 1448 ure_ioctl(if_t ifp, u_long cmd, caddr_t data) 1449 { 1450 struct usb_ether *ue = if_getsoftc(ifp); 1451 struct ure_softc *sc; 1452 struct ifreq *ifr; 1453 int error, mask, reinit; 1454 1455 sc = uether_getsc(ue); 1456 ifr = (struct ifreq *)data; 1457 error = 0; 1458 reinit = 0; 1459 switch (cmd) { 1460 case SIOCSIFCAP: 1461 URE_LOCK(sc); 1462 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1463 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1464 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1465 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1466 reinit++; 1467 } 1468 if ((mask & IFCAP_TXCSUM) != 0 && 1469 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1470 if_togglecapenable(ifp, IFCAP_TXCSUM); 1471 if_togglehwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 1472 } 1473 if ((mask & IFCAP_RXCSUM) != 0 && 1474 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1475 if_togglecapenable(ifp, IFCAP_RXCSUM); 1476 } 1477 if ((mask & IFCAP_TXCSUM_IPV6) != 0 && 1478 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) { 1479 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 1480 if_togglehwassist(ifp, CSUM_IP6_UDP|CSUM_IP6_TCP); 1481 } 1482 if ((mask & IFCAP_RXCSUM_IPV6) != 0 && 1483 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) { 1484 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 1485 } 1486 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1487 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1488 else 1489 reinit = 0; 1490 URE_UNLOCK(sc); 1491 if (reinit > 0) 1492 uether_init(ue); 1493 break; 1494 1495 case SIOCSIFMTU: 1496 /* 1497 * in testing large MTUs "crashes" the device, it 1498 * leaves the device w/ a broken state where link 1499 * is in a bad state. 1500 */ 1501 if (ifr->ifr_mtu < ETHERMIN || 1502 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN - 1503 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) { 1504 error = EINVAL; 1505 break; 1506 } 1507 URE_LOCK(sc); 1508 if (if_getmtu(ifp) != ifr->ifr_mtu) 1509 if_setmtu(ifp, ifr->ifr_mtu); 1510 URE_UNLOCK(sc); 1511 break; 1512 1513 case SIOCGIFMEDIA: 1514 case SIOCSIFMEDIA: 1515 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1516 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1517 else 1518 error = uether_ioctl(ifp, cmd, data); 1519 break; 1520 1521 default: 1522 error = uether_ioctl(ifp, cmd, data); 1523 break; 1524 } 1525 1526 return (error); 1527 } 1528 1529 static void 1530 ure_rtl8152_init(struct ure_softc *sc) 1531 { 1532 uint32_t pwrctrl; 1533 1534 ure_enable_aldps(sc, false); 1535 1536 if (sc->sc_chip & URE_CHIP_VER_4C00) { 1537 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1538 } 1539 1540 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1541 1542 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE); 1543 1544 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1545 1546 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1547 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1548 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1549 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1550 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1551 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1552 URE_SPDWN_LINKCHG_MSK); 1553 1554 /* Enable Rx aggregation. */ 1555 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1556 1557 ure_enable_aldps(sc, false); 1558 1559 ure_rtl8152_nic_reset(sc); 1560 1561 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1562 URE_TX_AGG_MAX_THRESHOLD); 1563 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1564 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1565 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1566 } 1567 1568 static void 1569 ure_rtl8153_init(struct ure_softc *sc) 1570 { 1571 uint16_t val; 1572 uint8_t u1u2[8]; 1573 int i; 1574 1575 ure_enable_aldps(sc, false); 1576 1577 memset(u1u2, 0x00, sizeof(u1u2)); 1578 ure_write_mem(sc, URE_USB_TOLERANCE, 1579 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1580 1581 for (i = 0; i < URE_TIMEOUT; i++) { 1582 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1583 URE_AUTOLOAD_DONE) 1584 break; 1585 uether_pause(&sc->sc_ue, hz / 100); 1586 } 1587 if (i == URE_TIMEOUT) 1588 device_printf(sc->sc_ue.ue_dev, 1589 "timeout waiting for chip autoload\n"); 1590 1591 for (i = 0; i < URE_TIMEOUT; i++) { 1592 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1593 URE_PHY_STAT_MASK; 1594 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1595 break; 1596 uether_pause(&sc->sc_ue, hz / 100); 1597 } 1598 if (i == URE_TIMEOUT) 1599 device_printf(sc->sc_ue.ue_dev, 1600 "timeout waiting for phy to stabilize\n"); 1601 1602 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1603 1604 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1605 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1606 val &= ~URE_PWD_DN_SCALE_MASK; 1607 val |= URE_PWD_DN_SCALE(96); 1608 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1609 1610 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1611 } else if (sc->sc_chip & URE_CHIP_VER_5C20) 1612 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS); 1613 1614 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1615 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1616 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1617 0) 1618 val &= ~URE_DYNAMIC_BURST; 1619 else 1620 val |= URE_DYNAMIC_BURST; 1621 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1622 } 1623 1624 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1625 1626 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1627 1628 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1629 1630 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1631 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1632 val = URE_LPM_TIMER_500MS; 1633 else 1634 val = URE_LPM_TIMER_500US; 1635 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1636 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1637 1638 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1639 val &= ~URE_SEN_VAL_MASK; 1640 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1641 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1642 1643 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1644 1645 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN); 1646 1647 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1648 1649 memset(u1u2, 0xff, sizeof(u1u2)); 1650 ure_write_mem(sc, URE_USB_TOLERANCE, 1651 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1652 1653 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1654 URE_ALDPS_SPDWN_RATIO); 1655 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1656 URE_EEE_SPDWN_RATIO); 1657 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1658 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1659 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1660 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1661 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1662 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1663 URE_EEE_SPDWN_EN); 1664 1665 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1666 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1667 val |= URE_U2P3_ENABLE; 1668 else 1669 val &= ~URE_U2P3_ENABLE; 1670 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1671 1672 memset(u1u2, 0x00, sizeof(u1u2)); 1673 ure_write_mem(sc, URE_USB_TOLERANCE, 1674 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1675 1676 ure_enable_aldps(sc, false); 1677 1678 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1679 URE_CHIP_VER_5C20)) { 1680 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1681 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1682 } 1683 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1684 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1685 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1686 ~URE_CTAP_SHORT_EN); 1687 } 1688 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1689 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1690 URE_EEE_CLKDIV_EN); 1691 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1692 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1693 URE_EN_10M_BGOFF); 1694 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1695 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1696 URE_EN_10M_PLLOFF); 1697 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13); 1698 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH); 1699 1700 /* Enable LPF corner auto tune. */ 1701 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f); 1702 1703 /* Adjust 10M amplitude. */ 1704 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af); 1705 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208); 1706 1707 ure_rtl8152_nic_reset(sc); 1708 1709 /* Enable Rx aggregation. */ 1710 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1711 1712 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1713 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1714 val |= URE_U2P3_ENABLE; 1715 else 1716 val &= ~URE_U2P3_ENABLE; 1717 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1718 1719 memset(u1u2, 0xff, sizeof(u1u2)); 1720 ure_write_mem(sc, URE_USB_TOLERANCE, 1721 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1722 } 1723 1724 static void 1725 ure_rtl8153b_init(struct ure_softc *sc) 1726 { 1727 uint16_t val; 1728 int i; 1729 1730 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1731 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); 1732 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); 1733 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); 1734 } 1735 1736 if (sc->sc_flags & URE_FLAG_8156B) { 1737 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08); 1738 } 1739 1740 ure_enable_aldps(sc, false); 1741 1742 /* Disable U1U2 */ 1743 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1744 1745 /* Wait loading flash */ 1746 if (sc->sc_chip == URE_CHIP_VER_7410) { 1747 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) && 1748 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) { 1749 for (i=0; i < 100; i++) { 1750 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004) 1751 break; 1752 uether_pause(&sc->sc_ue, hz / 1000); 1753 } 1754 } 1755 } 1756 1757 for (i = 0; i < URE_TIMEOUT; i++) { 1758 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1759 URE_AUTOLOAD_DONE) 1760 break; 1761 uether_pause(&sc->sc_ue, hz / 100); 1762 } 1763 if (i == URE_TIMEOUT) 1764 device_printf(sc->sc_ue.ue_dev, 1765 "timeout waiting for chip autoload\n"); 1766 1767 val = ure_phy_status(sc, 0); 1768 if ((val == URE_PHY_STAT_EXT_INIT) & 1769 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1770 ure_ocp_reg_write(sc, 0xa468, 1771 ure_ocp_reg_read(sc, 0xa468) & ~0x0a); 1772 if (sc->sc_flags & URE_FLAG_8156B) 1773 ure_ocp_reg_write(sc, 0xa466, 1774 ure_ocp_reg_read(sc, 0xa466) & ~0x01); 1775 } 1776 1777 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR); 1778 if (val & BMCR_PDOWN) { 1779 val &= ~BMCR_PDOWN; 1780 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val); 1781 } 1782 1783 ure_phy_status(sc, URE_PHY_STAT_LAN_ON); 1784 1785 /* Disable U2P3 */ 1786 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1787 1788 /* MSC timer, 32760 ms. */ 1789 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); 1790 1791 /* U1/U2/L1 idle timer, 500 us. */ 1792 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1793 1794 /* Disable power cut */ 1795 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1796 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1797 1798 /* Disable ups */ 1799 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE); 1800 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); 1801 1802 /* Disable queue wake */ 1803 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3); 1804 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT); 1805 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG); 1806 1807 /* Disable runtime suspend */ 1808 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1809 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN); 1810 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1811 1812 /* Enable U1U2 */ 1813 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1814 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1815 1816 if (sc->sc_flags & URE_FLAG_8156B) { 1817 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800); 1818 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001); 1819 1820 /* enable fc timer and set timer to 600 ms. */ 1821 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8)); 1822 1823 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) { 1824 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1825 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100; 1826 val &= ~0x08; 1827 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val); 1828 } 1829 1830 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1831 } 1832 1833 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1834 if (ure_get_link_status(sc)) 1835 val |= URE_CUR_LINK_OK; 1836 else 1837 val &= ~URE_CUR_LINK_OK; 1838 val |= URE_POLL_LINK_CHG; 1839 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val); 1840 1841 /* MAC clock speed down */ 1842 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1843 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1844 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1845 val &= ~0xff; 1846 val |= URE_MAC_CLK_SPDWN_EN | 0x03; 1847 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val); 1848 } else { 1849 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN); 1850 } 1851 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1852 1853 /* Enable Rx aggregation. */ 1854 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1855 1856 if (sc->sc_flags & URE_FLAG_8156) 1857 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02); 1858 1859 /* Reset tally */ 1860 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET); 1861 } 1862 1863 static void 1864 ure_rtl8153b_nic_reset(struct ure_softc *sc) 1865 { 1866 if_t ifp = uether_getifp(&sc->sc_ue); 1867 uint16_t val; 1868 int i; 1869 1870 /* Disable U1U2 */ 1871 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1872 1873 /* Disable U2P3 */ 1874 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1875 1876 ure_enable_aldps(sc, false); 1877 1878 /* Enable rxdy_gated */ 1879 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1880 1881 /* Disable teredo */ 1882 ure_disable_teredo(sc); 1883 1884 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1885 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1886 1887 ure_reset(sc); 1888 1889 /* Reset BMU */ 1890 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1891 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1892 1893 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1894 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1895 if (sc->sc_flags & URE_FLAG_8153B) { 1896 for (i = 0; i < URE_TIMEOUT; i++) { 1897 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1898 URE_LINK_LIST_READY) 1899 break; 1900 uether_pause(&sc->sc_ue, hz / 100); 1901 } 1902 if (i == URE_TIMEOUT) 1903 device_printf(sc->sc_ue.ue_dev, 1904 "timeout waiting for OOB control\n"); 1905 1906 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1907 for (i = 0; i < URE_TIMEOUT; i++) { 1908 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1909 URE_LINK_LIST_READY) 1910 break; 1911 uether_pause(&sc->sc_ue, hz / 100); 1912 } 1913 if (i == URE_TIMEOUT) 1914 device_printf(sc->sc_ue.ue_dev, 1915 "timeout waiting for OOB control\n"); 1916 } 1917 1918 /* Configure rxvlan */ 1919 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); 1920 val &= ~0x00c0; 1921 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) 1922 val |= 0x00c0; 1923 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val); 1924 1925 val = if_getmtu(ifp); 1926 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val)); 1927 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO); 1928 1929 if (sc->sc_flags & URE_FLAG_8153B) { 1930 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1931 ure_reset(sc); 1932 } 1933 1934 /* Configure fc parameter */ 1935 if (sc->sc_flags & URE_FLAG_8156) { 1936 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400); 1937 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800); 1938 } else if (sc->sc_flags & URE_FLAG_8156B) { 1939 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200); 1940 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400); 1941 } 1942 1943 /* Configure Rx FIFO threshold. */ 1944 if (sc->sc_flags & URE_FLAG_8153B) { 1945 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL); 1946 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL); 1947 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL); 1948 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B); 1949 } else { 1950 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA, 1951 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08); 1952 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400); 1953 } 1954 1955 /* Configure Tx FIFO threshold. */ 1956 if (sc->sc_flags & URE_FLAG_8153B) { 1957 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1958 } else if (sc->sc_flags & URE_FLAG_8156) { 1959 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1960 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002); 1961 } else if (sc->sc_flags & URE_FLAG_8156B) { 1962 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008); 1963 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA, 1964 (URE_FRAMELEN(val) + 0x100) / 16 ); 1965 } 1966 1967 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1968 1969 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1970 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300); 1971 1972 ure_enable_aldps(sc, true); 1973 1974 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1975 /* Enable U2P3 */ 1976 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1977 } 1978 1979 /* Enable U1U2 */ 1980 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1981 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1982 } 1983 1984 static void 1985 ure_stop(struct usb_ether *ue) 1986 { 1987 struct ure_softc *sc = uether_getsc(ue); 1988 if_t ifp = uether_getifp(ue); 1989 1990 URE_LOCK_ASSERT(sc, MA_OWNED); 1991 1992 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1993 sc->sc_flags &= ~URE_FLAG_LINK; 1994 sc->sc_rxstarted = 0; 1995 1996 /* 1997 * stop all the transfers, if not already stopped: 1998 */ 1999 for (int i = 0; i < URE_MAX_RX; i++) 2000 usbd_transfer_stop(sc->sc_rx_xfer[i]); 2001 for (int i = 0; i < URE_MAX_TX; i++) 2002 usbd_transfer_stop(sc->sc_tx_xfer[i]); 2003 } 2004 2005 static void 2006 ure_disable_teredo(struct ure_softc *sc) 2007 { 2008 2009 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 2010 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 2011 else { 2012 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 2013 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 2014 } 2015 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 2016 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 2017 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 2018 } 2019 2020 static void 2021 ure_enable_aldps(struct ure_softc *sc, bool enable) 2022 { 2023 int i; 2024 2025 if (enable) { 2026 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 2027 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 2028 } else { 2029 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 2030 URE_DIS_SDSAVE); 2031 for (i = 0; i < 20; i++) { 2032 uether_pause(&sc->sc_ue, hz / 1000); 2033 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100) 2034 break; 2035 } 2036 } 2037 } 2038 2039 static uint16_t 2040 ure_phy_status(struct ure_softc *sc, uint16_t desired) 2041 { 2042 uint16_t val; 2043 int i; 2044 2045 for (i = 0; i < URE_TIMEOUT; i++) { 2046 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 2047 URE_PHY_STAT_MASK; 2048 if (desired) { 2049 if (val == desired) 2050 break; 2051 } else { 2052 if (val == URE_PHY_STAT_LAN_ON || 2053 val == URE_PHY_STAT_PWRDN || 2054 val == URE_PHY_STAT_EXT_INIT) 2055 break; 2056 } 2057 uether_pause(&sc->sc_ue, hz / 100); 2058 } 2059 if (i == URE_TIMEOUT) 2060 device_printf(sc->sc_ue.ue_dev, 2061 "timeout waiting for phy to stabilize\n"); 2062 2063 return (val); 2064 } 2065 2066 static void 2067 ure_rtl8152_nic_reset(struct ure_softc *sc) 2068 { 2069 uint32_t rx_fifo1, rx_fifo2; 2070 int i; 2071 2072 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 2073 2074 ure_disable_teredo(sc); 2075 2076 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 2077 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 2078 2079 ure_reset(sc); 2080 2081 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 2082 2083 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 2084 2085 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 2086 for (i = 0; i < URE_TIMEOUT; i++) { 2087 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2088 URE_LINK_LIST_READY) 2089 break; 2090 uether_pause(&sc->sc_ue, hz / 100); 2091 } 2092 if (i == URE_TIMEOUT) 2093 device_printf(sc->sc_ue.ue_dev, 2094 "timeout waiting for OOB control\n"); 2095 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 2096 for (i = 0; i < URE_TIMEOUT; i++) { 2097 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2098 URE_LINK_LIST_READY) 2099 break; 2100 uether_pause(&sc->sc_ue, hz / 100); 2101 } 2102 if (i == URE_TIMEOUT) 2103 device_printf(sc->sc_ue.ue_dev, 2104 "timeout waiting for OOB control\n"); 2105 2106 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN); 2107 2108 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 2109 2110 /* Configure Rx FIFO threshold. */ 2111 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 2112 URE_RXFIFO_THR1_NORMAL); 2113 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 2114 rx_fifo1 = URE_RXFIFO_THR2_FULL; 2115 rx_fifo2 = URE_RXFIFO_THR3_FULL; 2116 } else { 2117 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 2118 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 2119 } 2120 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 2121 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 2122 2123 /* Configure Tx FIFO threshold. */ 2124 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 2125 URE_TXFIFO_THR_NORMAL); 2126 } 2127 2128 /* 2129 * Update mbuf for rx checksum from hardware 2130 */ 2131 static void 2132 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m) 2133 { 2134 int flags; 2135 uint32_t csum, misc; 2136 int tcp, udp; 2137 2138 m->m_pkthdr.csum_flags = 0; 2139 2140 if (!(capenb & IFCAP_RXCSUM)) 2141 return; 2142 2143 csum = le32toh(rp->ure_csum); 2144 misc = le32toh(rp->ure_misc); 2145 2146 tcp = udp = 0; 2147 2148 flags = 0; 2149 if (csum & URE_RXPKT_IPV4_CS) 2150 flags |= CSUM_IP_CHECKED; 2151 else if (csum & URE_RXPKT_IPV6_CS) 2152 flags = 0; 2153 2154 tcp = rp->ure_csum & URE_RXPKT_TCP_CS; 2155 udp = rp->ure_csum & URE_RXPKT_UDP_CS; 2156 2157 if (__predict_true((flags & CSUM_IP_CHECKED) && 2158 !(misc & URE_RXPKT_IP_F))) { 2159 flags |= CSUM_IP_VALID; 2160 } 2161 if (__predict_true( 2162 (tcp && !(misc & URE_RXPKT_TCP_F)) || 2163 (udp && !(misc & URE_RXPKT_UDP_F)))) { 2164 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2165 m->m_pkthdr.csum_data = 0xFFFF; 2166 } 2167 2168 m->m_pkthdr.csum_flags = flags; 2169 } 2170 2171 /* 2172 * If the L4 checksum offset is larger than 0x7ff (2047), return failure. 2173 * We currently restrict MTU such that it can't happen, and even if we 2174 * did have a large enough MTU, only a very specially crafted IPv6 packet 2175 * with MANY headers could possibly come close. 2176 * 2177 * Returns 0 for success, and 1 if the packet cannot be checksummed and 2178 * should be dropped. 2179 */ 2180 static int 2181 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout) 2182 { 2183 struct ip ip; 2184 struct ether_header *eh; 2185 int flags; 2186 uint32_t reg; 2187 int l3off, l4off; 2188 uint16_t type; 2189 2190 *regout = 0; 2191 flags = m->m_pkthdr.csum_flags; 2192 if (flags == 0) 2193 return (0); 2194 2195 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 2196 eh = mtod(m, struct ether_header *); 2197 type = eh->ether_type; 2198 } else 2199 m_copydata(m, offsetof(struct ether_header, ether_type), 2200 sizeof(type), (caddr_t)&type); 2201 2202 switch (type = htons(type)) { 2203 case ETHERTYPE_IP: 2204 case ETHERTYPE_IPV6: 2205 l3off = ETHER_HDR_LEN; 2206 break; 2207 case ETHERTYPE_VLAN: 2208 /* XXX - what about QinQ? */ 2209 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2210 break; 2211 default: 2212 return (0); 2213 } 2214 2215 reg = 0; 2216 2217 if (flags & CSUM_IP) 2218 reg |= URE_TXPKT_IPV4_CS; 2219 2220 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) { 2221 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip); 2222 l4off = l3off + (ip.ip_hl << 2); 2223 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2224 return (1); 2225 2226 reg |= URE_TXPKT_IPV4_CS; 2227 if (flags & CSUM_IP_TCP) 2228 reg |= URE_TXPKT_TCP_CS; 2229 else if (flags & CSUM_IP_UDP) 2230 reg |= URE_TXPKT_UDP_CS; 2231 reg |= l4off << URE_L4_OFFSET_SHIFT; 2232 } 2233 #ifdef INET6 2234 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) { 2235 l4off = ip6_lasthdr(m, l3off, IPPROTO_IPV6, NULL); 2236 if (__predict_false(l4off < 0)) 2237 return (1); 2238 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2239 return (1); 2240 2241 reg |= URE_TXPKT_IPV6_CS; 2242 if (flags & CSUM_IP6_TCP) 2243 reg |= URE_TXPKT_TCP_CS; 2244 else if (flags & CSUM_IP6_UDP) 2245 reg |= URE_TXPKT_UDP_CS; 2246 reg |= l4off << URE_L4_OFFSET_SHIFT; 2247 } 2248 #endif 2249 *regout = reg; 2250 return 0; 2251 } 2252