1 /*-
2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_inet6.h"
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/condvar.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/sbuf.h>
38 #include <sys/socket.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
41
42 #include <net/if.h>
43 #include <net/if_var.h>
44 #include <net/if_media.h>
45
46 /* needed for checksum offload */
47 #include <netinet/in.h>
48 #include <netinet/ip.h>
49 #ifdef INET6
50 #include <netinet/ip6.h>
51 #include <netinet6/ip6_var.h>
52 #endif
53
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
56
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usbdi.h>
59 #include <dev/usb/usbdi_util.h>
60 #include "usbdevs.h"
61
62 #define USB_DEBUG_VAR ure_debug
63 #include <dev/usb/usb_debug.h>
64 #include <dev/usb/usb_process.h>
65
66 #include <dev/usb/net/usb_ethernet.h>
67 #include <dev/usb/net/if_urereg.h>
68
69 #include "miibus_if.h"
70
71 #ifdef USB_DEBUG
72 static int ure_debug = 0;
73
74 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
75 "USB ure");
76 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
77 "Debug level");
78 #endif
79
80 #ifdef USB_DEBUG_VAR
81 #ifdef USB_DEBUG
82 #define DEVPRINTFN(n,dev,fmt,...) do { \
83 if ((USB_DEBUG_VAR) >= (n)) { \
84 device_printf((dev), "%s: " fmt, \
85 __FUNCTION__ ,##__VA_ARGS__); \
86 } \
87 } while (0)
88 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__)
89 #else
90 #define DEVPRINTF(...) do { } while (0)
91 #define DEVPRINTFN(...) do { } while (0)
92 #endif
93 #endif
94
95 /*
96 * Various supported device vendors/products.
97 */
98 static const STRUCT_USB_HOST_ID ure_devs[] = {
99 #define URE_DEV(v,p,i) { \
100 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \
101 USB_IFACE_CLASS(UICLASS_VENDOR), \
102 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) }
103 URE_DEV(CISCOLINKSYS, USB3GIGV1, 0),
104 URE_DEV(DLINK, DUBE1312, 0),
105 URE_DEV(ELECOM, EDCQUA3C, 0),
106 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153),
107 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153),
108 URE_DEV(LENOVO, TBT3LAN, 0),
109 URE_DEV(LENOVO, TBT3LANGEN2, 0),
110 URE_DEV(LENOVO, ONELINK, 0),
111 URE_DEV(LENOVO, ONELINKPLUS, URE_FLAG_8153),
112 URE_DEV(LENOVO, USBCLAN, 0),
113 URE_DEV(LENOVO, USBCLANGEN2, 0),
114 URE_DEV(LENOVO, USBCLANHYBRID, 0),
115 URE_DEV(MICROSOFT, SURFETH1, 0),
116 URE_DEV(MICROSOFT, SURFETH2, 0),
117 URE_DEV(MICROSOFT, WINDEVETH, 0),
118 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153),
119 URE_DEV(REALTEK, RTL8050, URE_FLAG_8152),
120 URE_DEV(REALTEK, RTL8053, URE_FLAG_8153),
121 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
122 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153),
123 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156),
124 URE_DEV(SAMSUNG, RTL8153, 0),
125 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153),
126 URE_DEV(TPLINK, RTL8153_2, 0),
127 #undef URE_DEV
128 };
129
130 static device_probe_t ure_probe;
131 static device_attach_t ure_attach;
132 static device_detach_t ure_detach;
133
134 static usb_callback_t ure_bulk_read_callback;
135 static usb_callback_t ure_bulk_write_callback;
136
137 static miibus_readreg_t ure_miibus_readreg;
138 static miibus_writereg_t ure_miibus_writereg;
139 static miibus_statchg_t ure_miibus_statchg;
140 static miibus_linkchg_t ure_miibus_linkchg;
141
142 static uether_fn_t ure_attach_post;
143 static uether_fn_t ure_init;
144 static uether_fn_t ure_stop;
145 static uether_fn_t ure_start;
146 static uether_fn_t ure_tick;
147 static uether_fn_t ure_rxfilter;
148
149 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
150 void *, int);
151 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
152 int);
153 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
154 int);
155 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
156 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
157 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
158 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
159 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
160 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
161 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
162 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
163 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t);
164
165 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS);
166
167 static void ure_read_chipver(struct ure_softc *);
168 static int ure_attach_post_sub(struct usb_ether *);
169 static void ure_reset(struct ure_softc *);
170 static int ure_ifmedia_upd(if_t);
171 static void ure_ifmedia_sts(if_t, struct ifmediareq *);
172 static void ure_add_media_types(struct ure_softc *);
173 static void ure_link_state(struct ure_softc *sc);
174 static int ure_get_link_status(struct ure_softc *);
175 static int ure_ioctl(if_t, u_long, caddr_t);
176 static void ure_rtl8152_init(struct ure_softc *);
177 static void ure_rtl8152_nic_reset(struct ure_softc *);
178 static void ure_rtl8153_init(struct ure_softc *);
179 static void ure_rtl8153b_init(struct ure_softc *);
180 static void ure_rtl8153b_nic_reset(struct ure_softc *);
181 static void ure_disable_teredo(struct ure_softc *);
182 static void ure_enable_aldps(struct ure_softc *, bool);
183 static uint16_t ure_phy_status(struct ure_softc *, uint16_t);
184 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m);
185 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout);
186
187 static device_method_t ure_methods[] = {
188 /* Device interface. */
189 DEVMETHOD(device_probe, ure_probe),
190 DEVMETHOD(device_attach, ure_attach),
191 DEVMETHOD(device_detach, ure_detach),
192
193 /* MII interface. */
194 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
195 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
196 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
197 DEVMETHOD(miibus_linkchg, ure_miibus_linkchg),
198
199 DEVMETHOD_END
200 };
201
202 static driver_t ure_driver = {
203 .name = "ure",
204 .methods = ure_methods,
205 .size = sizeof(struct ure_softc),
206 };
207
208 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL);
209 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL);
210 MODULE_DEPEND(ure, uether, 1, 1, 1);
211 MODULE_DEPEND(ure, usb, 1, 1, 1);
212 MODULE_DEPEND(ure, ether, 1, 1, 1);
213 MODULE_DEPEND(ure, miibus, 1, 1, 1);
214 MODULE_VERSION(ure, 1);
215 USB_PNP_HOST_INFO(ure_devs);
216
217 static const struct usb_ether_methods ure_ue_methods = {
218 .ue_attach_post = ure_attach_post,
219 .ue_attach_post_sub = ure_attach_post_sub,
220 .ue_start = ure_start,
221 .ue_init = ure_init,
222 .ue_stop = ure_stop,
223 .ue_tick = ure_tick,
224 .ue_setmulti = ure_rxfilter,
225 .ue_setpromisc = ure_rxfilter,
226 .ue_mii_upd = ure_ifmedia_upd,
227 .ue_mii_sts = ure_ifmedia_sts,
228 };
229
230 #define URE_SETBIT_1(sc, reg, index, x) \
231 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
232 #define URE_SETBIT_2(sc, reg, index, x) \
233 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
234 #define URE_SETBIT_4(sc, reg, index, x) \
235 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
236
237 #define URE_CLRBIT_1(sc, reg, index, x) \
238 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
239 #define URE_CLRBIT_2(sc, reg, index, x) \
240 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
241 #define URE_CLRBIT_4(sc, reg, index, x) \
242 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
243
244 static int
ure_ctl(struct ure_softc * sc,uint8_t rw,uint16_t val,uint16_t index,void * buf,int len)245 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
246 void *buf, int len)
247 {
248 struct usb_device_request req;
249
250 URE_LOCK_ASSERT(sc, MA_OWNED);
251
252 if (rw == URE_CTL_WRITE)
253 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
254 else
255 req.bmRequestType = UT_READ_VENDOR_DEVICE;
256 req.bRequest = UR_SET_ADDRESS;
257 USETW(req.wValue, val);
258 USETW(req.wIndex, index);
259 USETW(req.wLength, len);
260
261 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
262 }
263
264 static int
ure_read_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)265 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
266 void *buf, int len)
267 {
268
269 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
270 }
271
272 static int
ure_write_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)273 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
274 void *buf, int len)
275 {
276
277 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
278 }
279
280 static uint8_t
ure_read_1(struct ure_softc * sc,uint16_t reg,uint16_t index)281 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
282 {
283 uint32_t val;
284 uint8_t temp[4];
285 uint8_t shift;
286
287 shift = (reg & 3) << 3;
288 reg &= ~3;
289
290 ure_read_mem(sc, reg, index, &temp, 4);
291 val = UGETDW(temp);
292 val >>= shift;
293
294 return (val & 0xff);
295 }
296
297 static uint16_t
ure_read_2(struct ure_softc * sc,uint16_t reg,uint16_t index)298 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
299 {
300 uint32_t val;
301 uint8_t temp[4];
302 uint8_t shift;
303
304 shift = (reg & 2) << 3;
305 reg &= ~3;
306
307 ure_read_mem(sc, reg, index, &temp, 4);
308 val = UGETDW(temp);
309 val >>= shift;
310
311 return (val & 0xffff);
312 }
313
314 static uint32_t
ure_read_4(struct ure_softc * sc,uint16_t reg,uint16_t index)315 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
316 {
317 uint8_t temp[4];
318
319 ure_read_mem(sc, reg, index, &temp, 4);
320 return (UGETDW(temp));
321 }
322
323 static int
ure_write_1(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)324 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
325 {
326 uint16_t byen;
327 uint8_t temp[4];
328 uint8_t shift;
329
330 byen = URE_BYTE_EN_BYTE;
331 shift = reg & 3;
332 val &= 0xff;
333
334 if (reg & 3) {
335 byen <<= shift;
336 val <<= (shift << 3);
337 reg &= ~3;
338 }
339
340 USETDW(temp, val);
341 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
342 }
343
344 static int
ure_write_2(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)345 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
346 {
347 uint16_t byen;
348 uint8_t temp[4];
349 uint8_t shift;
350
351 byen = URE_BYTE_EN_WORD;
352 shift = reg & 2;
353 val &= 0xffff;
354
355 if (reg & 2) {
356 byen <<= shift;
357 val <<= (shift << 3);
358 reg &= ~3;
359 }
360
361 USETDW(temp, val);
362 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
363 }
364
365 static int
ure_write_4(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)366 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
367 {
368 uint8_t temp[4];
369
370 USETDW(temp, val);
371 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
372 }
373
374 static uint16_t
ure_ocp_reg_read(struct ure_softc * sc,uint16_t addr)375 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
376 {
377 uint16_t reg;
378
379 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
380 reg = (addr & 0x0fff) | 0xb000;
381
382 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
383 }
384
385 static void
ure_ocp_reg_write(struct ure_softc * sc,uint16_t addr,uint16_t data)386 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
387 {
388 uint16_t reg;
389
390 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
391 reg = (addr & 0x0fff) | 0xb000;
392
393 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
394 }
395
396 static void
ure_sram_write(struct ure_softc * sc,uint16_t addr,uint16_t data)397 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
398 {
399 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr);
400 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data);
401 }
402
403 static int
ure_miibus_readreg(device_t dev,int phy,int reg)404 ure_miibus_readreg(device_t dev, int phy, int reg)
405 {
406 struct ure_softc *sc;
407 uint16_t val;
408 int locked;
409
410 sc = device_get_softc(dev);
411 locked = mtx_owned(&sc->sc_mtx);
412 if (!locked)
413 URE_LOCK(sc);
414
415 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
416 if (reg == URE_GMEDIASTAT) {
417 if (!locked)
418 URE_UNLOCK(sc);
419 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
420 }
421
422 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
423
424 if (!locked)
425 URE_UNLOCK(sc);
426 return (val);
427 }
428
429 static int
ure_miibus_writereg(device_t dev,int phy,int reg,int val)430 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
431 {
432 struct ure_softc *sc;
433 int locked;
434
435 sc = device_get_softc(dev);
436 if (sc->sc_phyno != phy)
437 return (0);
438
439 locked = mtx_owned(&sc->sc_mtx);
440 if (!locked)
441 URE_LOCK(sc);
442
443 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
444
445 if (!locked)
446 URE_UNLOCK(sc);
447 return (0);
448 }
449
450 static void
ure_miibus_statchg(device_t dev)451 ure_miibus_statchg(device_t dev)
452 {
453 struct ure_softc *sc;
454 struct mii_data *mii;
455 if_t ifp;
456 int locked;
457 uint16_t bmsr;
458 bool new_link, old_link;
459
460 sc = device_get_softc(dev);
461 mii = GET_MII(sc);
462 locked = mtx_owned(&sc->sc_mtx);
463 if (!locked)
464 URE_LOCK(sc);
465
466 ifp = uether_getifp(&sc->sc_ue);
467 if (mii == NULL || ifp == NULL ||
468 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
469 goto done;
470
471 old_link = (sc->sc_flags & URE_FLAG_LINK) ? true : false;
472 sc->sc_flags &= ~URE_FLAG_LINK;
473 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
474 (IFM_ACTIVE | IFM_AVALID)) {
475 switch (IFM_SUBTYPE(mii->mii_media_active)) {
476 case IFM_10_T:
477 case IFM_100_TX:
478 sc->sc_flags |= URE_FLAG_LINK;
479 sc->sc_rxstarted = 0;
480 break;
481 case IFM_1000_T:
482 if ((sc->sc_flags & URE_FLAG_8152) != 0)
483 break;
484 sc->sc_flags |= URE_FLAG_LINK;
485 sc->sc_rxstarted = 0;
486 break;
487 default:
488 break;
489 }
490 }
491
492 new_link = (sc->sc_flags & URE_FLAG_LINK) ? true : false;
493 if (old_link && !new_link) {
494 /*
495 * MII layer reports link down. Verify by reading
496 * the PHY BMSR register directly. BMSR link status
497 * is latched-low, so read twice: first clears any
498 * stale latch, second gives current state.
499 */
500 (void)ure_ocp_reg_read(sc,
501 URE_OCP_BASE_MII + MII_BMSR * 2);
502 bmsr = ure_ocp_reg_read(sc,
503 URE_OCP_BASE_MII + MII_BMSR * 2);
504
505 if (bmsr & BMSR_LINK) {
506 /*
507 * PHY still has link. This is a spurious
508 * link-down from the MII polling race (see
509 * PR 252165). Restore IFM_ACTIVE so the
510 * subsequent MIIBUS_LINKCHG check in
511 * mii_phy_update sees no change.
512 */
513 device_printf(dev,
514 "spurious link down (PHY link up), overriding\n");
515 sc->sc_flags |= URE_FLAG_LINK;
516 mii->mii_media_status |= IFM_ACTIVE;
517 }
518 }
519 done:
520 if (!locked)
521 URE_UNLOCK(sc);
522 }
523
524 static void
ure_miibus_linkchg(device_t dev)525 ure_miibus_linkchg(device_t dev)
526 {
527 struct ure_softc *sc;
528 struct mii_data *mii;
529 int locked;
530 uint16_t bmsr;
531
532 sc = device_get_softc(dev);
533 mii = GET_MII(sc);
534 locked = mtx_owned(&sc->sc_mtx);
535 if (locked == 0)
536 URE_LOCK(sc);
537
538 /*
539 * This is called by the default miibus linkchg handler
540 * before it calls if_link_state_change(). If the PHY
541 * still has link but the MII layer lost IFM_ACTIVE due
542 * to the polling race (see PR 252165), restore it so the
543 * notification goes out as LINK_STATE_UP rather than DOWN.
544 */
545 if (mii != NULL && (mii->mii_media_status & IFM_ACTIVE) == 0) {
546 (void)ure_ocp_reg_read(sc,
547 URE_OCP_BASE_MII + MII_BMSR * 2);
548 bmsr = ure_ocp_reg_read(sc,
549 URE_OCP_BASE_MII + MII_BMSR * 2);
550 if (bmsr & BMSR_LINK)
551 mii->mii_media_status |= IFM_ACTIVE;
552 }
553
554 if (locked == 0)
555 URE_UNLOCK(sc);
556 }
557
558 /*
559 * Probe for a RTL8152/RTL8153/RTL8156 chip.
560 */
561 static int
ure_probe(device_t dev)562 ure_probe(device_t dev)
563 {
564 struct usb_attach_arg *uaa;
565
566 uaa = device_get_ivars(dev);
567 if (uaa->usb_mode != USB_MODE_HOST)
568 return (ENXIO);
569 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
570 return (ENXIO);
571
572 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
573 }
574
575 /*
576 * Attach the interface. Allocate softc structures, do ifmedia
577 * setup and ethernet/BPF attach.
578 */
579 static int
ure_attach(device_t dev)580 ure_attach(device_t dev)
581 {
582 struct usb_attach_arg *uaa = device_get_ivars(dev);
583 struct ure_softc *sc = device_get_softc(dev);
584 struct usb_ether *ue = &sc->sc_ue;
585 struct usb_config ure_config_rx[URE_MAX_RX];
586 struct usb_config ure_config_tx[URE_MAX_TX];
587 uint8_t iface_index;
588 int error;
589 int i;
590
591 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
592 device_set_usb_desc(dev);
593 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
594
595 iface_index = URE_IFACE_IDX;
596
597 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B))
598 sc->sc_rxbufsz = URE_8153_RX_BUFSZ;
599 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
600 sc->sc_rxbufsz = URE_8156_RX_BUFSZ;
601 else
602 sc->sc_rxbufsz = URE_8152_RX_BUFSZ;
603
604 for (i = 0; i < URE_MAX_RX; i++) {
605 ure_config_rx[i] = (struct usb_config) {
606 .type = UE_BULK,
607 .endpoint = UE_ADDR_ANY,
608 .direction = UE_DIR_IN,
609 .bufsize = sc->sc_rxbufsz,
610 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
611 .callback = ure_bulk_read_callback,
612 .timeout = 0, /* no timeout */
613 };
614 }
615 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer,
616 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx);
617 if (error != 0) {
618 device_printf(dev, "allocating USB RX transfers failed\n");
619 goto detach;
620 }
621
622 for (i = 0; i < URE_MAX_TX; i++) {
623 ure_config_tx[i] = (struct usb_config) {
624 .type = UE_BULK,
625 .endpoint = UE_ADDR_ANY,
626 .direction = UE_DIR_OUT,
627 .bufsize = URE_TX_BUFSZ,
628 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
629 .callback = ure_bulk_write_callback,
630 .timeout = 10000, /* 10 seconds */
631 };
632 }
633 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer,
634 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx);
635 if (error != 0) {
636 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
637 device_printf(dev, "allocating USB TX transfers failed\n");
638 goto detach;
639 }
640
641 ue->ue_sc = sc;
642 ue->ue_dev = dev;
643 ue->ue_udev = uaa->device;
644 ue->ue_mtx = &sc->sc_mtx;
645 ue->ue_methods = &ure_ue_methods;
646
647 error = uether_ifattach(ue);
648 if (error != 0) {
649 device_printf(dev, "could not attach interface\n");
650 goto detach;
651 }
652 return (0); /* success */
653
654 detach:
655 ure_detach(dev);
656 return (ENXIO); /* failure */
657 }
658
659 static int
ure_detach(device_t dev)660 ure_detach(device_t dev)
661 {
662 struct ure_softc *sc = device_get_softc(dev);
663 struct usb_ether *ue = &sc->sc_ue;
664
665 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX);
666 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
667 uether_ifdetach(ue);
668 mtx_destroy(&sc->sc_mtx);
669
670 return (0);
671 }
672
673 /*
674 * Copy from USB buffers to a new mbuf chain with pkt header.
675 *
676 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf
677 * clusters as necessary.
678 */
679 static struct mbuf *
ure_makembuf(struct usb_page_cache * pc,usb_frlength_t offset,usb_frlength_t len)680 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset,
681 usb_frlength_t len)
682 {
683 struct usb_page_search_res;
684 struct mbuf *m, *mb;
685 usb_frlength_t tlen;
686
687 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR);
688 if (m == NULL)
689 return (m);
690
691 /* uether_newbuf does this. */
692 m_adj(m, ETHER_ALIGN);
693
694 m->m_pkthdr.len = len;
695
696 for (mb = m; len > 0; mb = mb->m_next) {
697 tlen = MIN(len, M_TRAILINGSPACE(mb));
698
699 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen);
700 mb->m_len = tlen;
701
702 offset += tlen;
703 len -= tlen;
704 }
705
706 return (m);
707 }
708
709 static void
ure_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)710 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
711 {
712 struct ure_softc *sc = usbd_xfer_softc(xfer);
713 struct usb_ether *ue = &sc->sc_ue;
714 if_t ifp = uether_getifp(ue);
715 struct usb_page_cache *pc;
716 struct mbuf *m;
717 struct ure_rxpkt pkt;
718 int actlen, off, len;
719 int caps;
720 uint32_t pktcsum;
721
722 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
723
724 switch (USB_GET_STATE(xfer)) {
725 case USB_ST_TRANSFERRED:
726 off = 0;
727 pc = usbd_xfer_get_frame(xfer, 0);
728 caps = if_getcapenable(ifp);
729 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n");
730 while (actlen > 0) {
731 if (actlen < (int)(sizeof(pkt))) {
732 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
733 goto tr_setup;
734 }
735 usbd_copy_out(pc, off, &pkt, sizeof(pkt));
736
737 off += sizeof(pkt);
738 actlen -= sizeof(pkt);
739
740 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
741
742 DEVPRINTFN(13, sc->sc_ue.ue_dev,
743 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n",
744 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc,
745 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4);
746 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len);
747
748 if (len >= URE_RXPKT_LEN_MASK) {
749 /*
750 * drop the rest of this segment. With out
751 * more information, we cannot know where next
752 * packet starts. Blindly continuing would
753 * cause a packet in packet attack, allowing
754 * one VLAN to inject packets w/o a VLAN tag,
755 * or injecting packets into other VLANs.
756 */
757 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
758 goto tr_setup;
759 }
760
761 if (actlen < len) {
762 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
763 goto tr_setup;
764 }
765
766 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN))
767 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN);
768 else
769 m = NULL;
770 if (m == NULL) {
771 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
772 } else {
773 /* make mbuf and queue */
774 pktcsum = le32toh(pkt.ure_csum);
775 if (caps & IFCAP_VLAN_HWTAGGING &&
776 pktcsum & URE_RXPKT_RX_VLAN_TAG) {
777 m->m_pkthdr.ether_vtag =
778 bswap16(pktcsum &
779 URE_RXPKT_VLAN_MASK);
780 m->m_flags |= M_VLANTAG;
781 }
782
783 /* set the necessary flags for rx checksum */
784 ure_rxcsum(caps, &pkt, m);
785
786 /*
787 * len has been known to be bogus at times,
788 * which leads to problems when passed to
789 * uether_rxmbuf(). Better understanding why we
790 * can get there make for good future work.
791 */
792 uether_rxmbuf(ue, m, 0);
793 }
794
795 off += roundup(len, URE_RXPKT_ALIGN);
796 actlen -= roundup(len, URE_RXPKT_ALIGN);
797 }
798 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n");
799
800 /* FALLTHROUGH */
801 case USB_ST_SETUP:
802 tr_setup:
803 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
804 usbd_transfer_submit(xfer);
805 uether_rxflush(ue);
806 return;
807
808 default: /* Error */
809 DPRINTF("bulk read error, %s\n",
810 usbd_errstr(error));
811
812 if (error != USB_ERR_CANCELLED) {
813 /* try to clear stall first */
814 usbd_xfer_set_stall(xfer);
815 goto tr_setup;
816 }
817 return;
818 }
819 }
820
821 static void
ure_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)822 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
823 {
824 struct ure_softc *sc = usbd_xfer_softc(xfer);
825 if_t ifp = uether_getifp(&sc->sc_ue);
826 struct usb_page_cache *pc;
827 struct mbuf *m;
828 struct ure_txpkt txpkt;
829 uint32_t regtmp;
830 int len, pos;
831 int rem;
832 int caps;
833
834 switch (USB_GET_STATE(xfer)) {
835 case USB_ST_TRANSFERRED:
836 DPRINTFN(11, "transfer complete\n");
837 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
838
839 /* FALLTHROUGH */
840 case USB_ST_SETUP:
841 tr_setup:
842 if ((sc->sc_flags & URE_FLAG_LINK) == 0) {
843 /* don't send anything if there is no link! */
844 break;
845 }
846
847 pc = usbd_xfer_get_frame(xfer, 0);
848 caps = if_getcapenable(ifp);
849
850 pos = 0;
851 rem = URE_TX_BUFSZ;
852 while (rem > sizeof(txpkt)) {
853 m = if_dequeue(ifp);
854 if (m == NULL)
855 break;
856
857 /*
858 * make sure we don't ever send too large of a
859 * packet
860 */
861 len = m->m_pkthdr.len;
862 if ((len & URE_TXPKT_LEN_MASK) != len) {
863 device_printf(sc->sc_ue.ue_dev,
864 "pkt len too large: %#x", len);
865 pkterror:
866 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
867 m_freem(m);
868 continue;
869 }
870
871 if (sizeof(txpkt) +
872 roundup(len, URE_TXPKT_ALIGN) > rem) {
873 /* out of space */
874 if_sendq_prepend(ifp, m);
875 m = NULL;
876 break;
877 }
878
879 txpkt = (struct ure_txpkt){};
880 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
881 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
882 if (m->m_flags & M_VLANTAG) {
883 txpkt.ure_csum = htole32(
884 bswap16(m->m_pkthdr.ether_vtag &
885 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN);
886 }
887 if (ure_txcsum(m, caps, ®tmp)) {
888 device_printf(sc->sc_ue.ue_dev,
889 "pkt l4 off too large");
890 goto pkterror;
891 }
892 txpkt.ure_csum |= htole32(regtmp);
893
894 DEVPRINTFN(13, sc->sc_ue.ue_dev,
895 "txpkt: mbflg: %#x, %#x, %#x\n",
896 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen),
897 le32toh(txpkt.ure_csum));
898
899 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
900
901 pos += sizeof(txpkt);
902 rem -= sizeof(txpkt);
903
904 usbd_m_copy_in(pc, pos, m, 0, len);
905
906 pos += roundup(len, URE_TXPKT_ALIGN);
907 rem -= roundup(len, URE_TXPKT_ALIGN);
908
909 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
910
911 /*
912 * If there's a BPF listener, bounce a copy
913 * of this frame to him.
914 */
915 BPF_MTAP(ifp, m);
916
917 m_freem(m);
918 }
919
920 /* no packets to send */
921 if (pos == 0)
922 break;
923
924 /* Set frame length. */
925 usbd_xfer_set_frame_len(xfer, 0, pos);
926
927 usbd_transfer_submit(xfer);
928
929 return;
930
931 default: /* Error */
932 DPRINTFN(11, "transfer error, %s\n",
933 usbd_errstr(error));
934
935 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
936 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
937
938 if (error == USB_ERR_TIMEOUT) {
939 DEVPRINTFN(12, sc->sc_ue.ue_dev,
940 "pkt tx timeout\n");
941 }
942
943 if (error != USB_ERR_CANCELLED) {
944 /* try to clear stall first */
945 usbd_xfer_set_stall(xfer);
946 goto tr_setup;
947 }
948 }
949 }
950
951 static void
ure_read_chipver(struct ure_softc * sc)952 ure_read_chipver(struct ure_softc *sc)
953 {
954 uint16_t ver;
955
956 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
957 sc->sc_ver = ver;
958 switch (ver) {
959 case 0x4c00:
960 sc->sc_chip |= URE_CHIP_VER_4C00;
961 sc->sc_flags = URE_FLAG_8152;
962 break;
963 case 0x4c10:
964 sc->sc_chip |= URE_CHIP_VER_4C10;
965 sc->sc_flags = URE_FLAG_8152;
966 break;
967 case 0x5c00:
968 sc->sc_chip |= URE_CHIP_VER_5C00;
969 sc->sc_flags = URE_FLAG_8153;
970 break;
971 case 0x5c10:
972 sc->sc_chip |= URE_CHIP_VER_5C10;
973 sc->sc_flags = URE_FLAG_8153;
974 break;
975 case 0x5c20:
976 sc->sc_chip |= URE_CHIP_VER_5C20;
977 sc->sc_flags = URE_FLAG_8153;
978 break;
979 case 0x5c30:
980 sc->sc_chip |= URE_CHIP_VER_5C30;
981 sc->sc_flags = URE_FLAG_8153;
982 break;
983 case 0x6000:
984 sc->sc_flags = URE_FLAG_8153B;
985 sc->sc_chip |= URE_CHIP_VER_6000;
986 break;
987 case 0x6010:
988 sc->sc_flags = URE_FLAG_8153B;
989 sc->sc_chip |= URE_CHIP_VER_6010;
990 break;
991 case 0x7020:
992 sc->sc_flags = URE_FLAG_8156;
993 sc->sc_chip |= URE_CHIP_VER_7020;
994 break;
995 case 0x7030:
996 sc->sc_flags = URE_FLAG_8156;
997 sc->sc_chip |= URE_CHIP_VER_7030;
998 break;
999 case 0x7400:
1000 sc->sc_flags = URE_FLAG_8156B;
1001 sc->sc_chip |= URE_CHIP_VER_7400;
1002 break;
1003 case 0x7410:
1004 sc->sc_flags = URE_FLAG_8156B;
1005 sc->sc_chip |= URE_CHIP_VER_7410;
1006 break;
1007 default:
1008 device_printf(sc->sc_ue.ue_dev,
1009 "unknown version 0x%04x\n", ver);
1010 break;
1011 }
1012 }
1013
1014 static int
ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)1015 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)
1016 {
1017 struct sbuf sb;
1018 struct ure_softc *sc = arg1;
1019 int error;
1020
1021 sbuf_new_for_sysctl(&sb, NULL, 0, req);
1022
1023 sbuf_printf(&sb, "%04x", sc->sc_ver);
1024
1025 error = sbuf_finish(&sb);
1026 sbuf_delete(&sb);
1027
1028 return (error);
1029 }
1030
1031 static void
ure_attach_post(struct usb_ether * ue)1032 ure_attach_post(struct usb_ether *ue)
1033 {
1034 struct ure_softc *sc = uether_getsc(ue);
1035
1036 sc->sc_rxstarted = 0;
1037 sc->sc_phyno = 0;
1038
1039 /* Determine the chip version. */
1040 ure_read_chipver(sc);
1041
1042 /* Initialize controller and get station address. */
1043 if (sc->sc_flags & URE_FLAG_8152)
1044 ure_rtl8152_init(sc);
1045 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1046 ure_rtl8153b_init(sc);
1047 else
1048 ure_rtl8153_init(sc);
1049
1050 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
1051 (sc->sc_chip & URE_CHIP_VER_4C10))
1052 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
1053 ue->ue_eaddr, 8);
1054 else
1055 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
1056 ue->ue_eaddr, 8);
1057
1058 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
1059 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
1060 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
1061 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
1062 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
1063 }
1064 }
1065
1066 static int
ure_attach_post_sub(struct usb_ether * ue)1067 ure_attach_post_sub(struct usb_ether *ue)
1068 {
1069 struct sysctl_ctx_list *sctx;
1070 struct sysctl_oid *soid;
1071 struct ure_softc *sc;
1072 if_t ifp;
1073 int error;
1074
1075 sc = uether_getsc(ue);
1076 ifp = ue->ue_ifp;
1077 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1078 if_setstartfn(ifp, uether_start);
1079 if_setioctlfn(ifp, ure_ioctl);
1080 if_setinitfn(ifp, uether_init);
1081 /*
1082 * Try to keep two transfers full at a time.
1083 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight)
1084 */
1085 if_setsendqlen(ifp, 512);
1086 if_setsendqready(ifp);
1087
1088 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1089 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
1090 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);
1091 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1092 #ifdef INET6
1093 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);
1094 if_sethwassistbits(ifp, CSUM_IP6_UDP|CSUM_IP6_TCP, 0);
1095 #endif
1096 if_setcapenable(ifp, if_getcapabilities(ifp));
1097
1098 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1099 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd,
1100 ure_ifmedia_sts);
1101 ure_add_media_types(sc);
1102 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1103 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
1104 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
1105 error = 0;
1106 } else {
1107 bus_topo_lock();
1108 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
1109 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
1110 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
1111 bus_topo_unlock();
1112 }
1113
1114 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev);
1115 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev);
1116 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver",
1117 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1118 ure_sysctl_chipver, "A",
1119 "Return string with chip version.");
1120
1121 return (error);
1122 }
1123
1124 static void
ure_init(struct usb_ether * ue)1125 ure_init(struct usb_ether *ue)
1126 {
1127 struct ure_softc *sc = uether_getsc(ue);
1128 if_t ifp = uether_getifp(ue);
1129 uint16_t cpcr;
1130 uint32_t reg;
1131
1132 URE_LOCK_ASSERT(sc, MA_OWNED);
1133
1134 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1135 return;
1136
1137 /* Cancel pending I/O. */
1138 ure_stop(ue);
1139
1140 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1141 ure_rtl8153b_nic_reset(sc);
1142 else
1143 ure_reset(sc);
1144
1145 /* Set MAC address. */
1146 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1147 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
1148 if_getlladdr(ifp), 8);
1149 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1150
1151 /* Set RX EARLY timeout and size */
1152 if (sc->sc_flags & URE_FLAG_8153) {
1153 switch (usbd_get_speed(sc->sc_ue.ue_udev)) {
1154 case USB_SPEED_SUPER:
1155 reg = URE_COALESCE_SUPER / 8;
1156 break;
1157 case USB_SPEED_HIGH:
1158 reg = URE_COALESCE_HIGH / 8;
1159 break;
1160 default:
1161 reg = URE_COALESCE_SLOW / 8;
1162 break;
1163 }
1164 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg);
1165 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1166 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1167 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4);
1168 } else if (sc->sc_flags & URE_FLAG_8153B) {
1169 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158);
1170 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1171 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1172 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1173 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1174 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1175 URE_OWN_UPDATE | URE_OWN_CLEAR);
1176 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1177 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80);
1178 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1179 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1180 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1181 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1182 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1183 URE_OWN_UPDATE | URE_OWN_CLEAR);
1184 }
1185
1186 if (sc->sc_flags & URE_FLAG_8156B) {
1187 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1188 uether_pause(&sc->sc_ue, hz / 500);
1189 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1190 }
1191
1192 /* Reset the packet filter. */
1193 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1194 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1195
1196 /* Enable RX VLANs if enabled */
1197 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
1198 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1199 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n");
1200 cpcr |= URE_CPCR_RX_VLAN;
1201 } else {
1202 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n");
1203 cpcr &= ~URE_CPCR_RX_VLAN;
1204 }
1205 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr);
1206
1207 /* Enable transmit and receive. */
1208 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1209
1210 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1211
1212 /* Configure RX filters. */
1213 ure_rxfilter(ue);
1214
1215 usbd_xfer_set_stall(sc->sc_tx_xfer[0]);
1216
1217 /* Indicate we are up and running. */
1218 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1219
1220 /* Switch to selected media. */
1221 ure_ifmedia_upd(ifp);
1222 }
1223
1224 static void
ure_tick(struct usb_ether * ue)1225 ure_tick(struct usb_ether *ue)
1226 {
1227 struct ure_softc *sc = uether_getsc(ue);
1228 if_t ifp = uether_getifp(ue);
1229 struct mii_data *mii;
1230
1231 URE_LOCK_ASSERT(sc, MA_OWNED);
1232
1233 (void)ifp;
1234 for (int i = 0; i < URE_MAX_RX; i++)
1235 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1236 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i]));
1237
1238 for (int i = 0; i < URE_MAX_TX; i++)
1239 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1240 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i]));
1241
1242 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1243 ure_link_state(sc);
1244 } else {
1245 mii = GET_MII(sc);
1246 mii_tick(mii);
1247 if ((sc->sc_flags & URE_FLAG_LINK) == 0
1248 && mii->mii_media_status & IFM_ACTIVE &&
1249 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1250 sc->sc_flags |= URE_FLAG_LINK;
1251 sc->sc_rxstarted = 0;
1252 ure_start(ue);
1253 }
1254 }
1255 }
1256
1257 static u_int
ure_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1258 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1259 {
1260 uint32_t h, *hashes = arg;
1261
1262 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
1263 if (h < 32)
1264 hashes[0] |= (1 << h);
1265 else
1266 hashes[1] |= (1 << (h - 32));
1267 return (1);
1268 }
1269
1270 /*
1271 * Program the 64-bit multicast hash filter.
1272 */
1273 static void
ure_rxfilter(struct usb_ether * ue)1274 ure_rxfilter(struct usb_ether *ue)
1275 {
1276 struct ure_softc *sc = uether_getsc(ue);
1277 if_t ifp = uether_getifp(ue);
1278 uint32_t rxmode;
1279 uint32_t h, hashes[2] = { 0, 0 };
1280
1281 URE_LOCK_ASSERT(sc, MA_OWNED);
1282
1283 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
1284 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM);
1285 rxmode |= URE_RCR_APM; /* accept physical match packets */
1286 rxmode |= URE_RCR_AB; /* always accept broadcasts */
1287 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
1288 if (if_getflags(ifp) & IFF_PROMISC)
1289 rxmode |= URE_RCR_AAP;
1290 rxmode |= URE_RCR_AM;
1291 hashes[0] = hashes[1] = 0xffffffff;
1292 goto done;
1293 }
1294
1295 /* calculate multicast masks */
1296 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
1297
1298 h = bswap32(hashes[0]);
1299 hashes[0] = bswap32(hashes[1]);
1300 hashes[1] = h;
1301 rxmode |= URE_RCR_AM; /* accept multicast packets */
1302
1303 done:
1304 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n",
1305 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1306 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
1307 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
1308 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
1309 }
1310
1311 static void
ure_start(struct usb_ether * ue)1312 ure_start(struct usb_ether *ue)
1313 {
1314 struct ure_softc *sc = uether_getsc(ue);
1315 unsigned i;
1316
1317 URE_LOCK_ASSERT(sc, MA_OWNED);
1318
1319 if (!sc->sc_rxstarted) {
1320 sc->sc_rxstarted = 1;
1321 for (i = 0; i != URE_MAX_RX; i++)
1322 usbd_transfer_start(sc->sc_rx_xfer[i]);
1323 }
1324
1325 for (i = 0; i != URE_MAX_TX; i++)
1326 usbd_transfer_start(sc->sc_tx_xfer[i]);
1327 }
1328
1329 static void
ure_reset(struct ure_softc * sc)1330 ure_reset(struct ure_softc *sc)
1331 {
1332 int i;
1333
1334 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
1335
1336 for (i = 0; i < URE_TIMEOUT; i++) {
1337 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
1338 URE_CR_RST))
1339 break;
1340 uether_pause(&sc->sc_ue, hz / 100);
1341 }
1342 if (i == URE_TIMEOUT)
1343 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
1344 }
1345
1346 /*
1347 * Set media options.
1348 */
1349 static int
ure_ifmedia_upd(if_t ifp)1350 ure_ifmedia_upd(if_t ifp)
1351 {
1352 struct ure_softc *sc = if_getsoftc(ifp);
1353 struct ifmedia *ifm;
1354 struct mii_data *mii;
1355 struct mii_softc *miisc;
1356 int gig;
1357 int reg;
1358 int anar;
1359 int locked;
1360 int error;
1361
1362 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1363 ifm = &sc->sc_ifmedia;
1364 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1365 return (EINVAL);
1366
1367 locked = mtx_owned(&sc->sc_mtx);
1368 if (!locked)
1369 URE_LOCK(sc);
1370 reg = ure_ocp_reg_read(sc, 0xa5d4);
1371 reg &= ~URE_ADV_2500TFDX;
1372
1373 anar = gig = 0;
1374 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1375 case IFM_AUTO:
1376 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1377 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1378 reg |= URE_ADV_2500TFDX;
1379 break;
1380 case IFM_2500_T:
1381 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1382 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1383 reg |= URE_ADV_2500TFDX;
1384 if_setbaudrate(ifp, IF_Mbps(2500));
1385 break;
1386 case IFM_1000_T:
1387 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1388 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1389 if_setbaudrate(ifp, IF_Gbps(1));
1390 break;
1391 case IFM_100_TX:
1392 anar |= ANAR_TX | ANAR_TX_FD;
1393 if_setbaudrate(ifp, IF_Mbps(100));
1394 break;
1395 case IFM_10_T:
1396 anar |= ANAR_10 | ANAR_10_FD;
1397 if_setbaudrate(ifp, IF_Mbps(10));
1398 break;
1399 default:
1400 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n");
1401 if (!locked)
1402 URE_UNLOCK(sc);
1403 return (EINVAL);
1404 }
1405
1406 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
1407 anar | ANAR_PAUSE_ASYM | ANAR_FC);
1408 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
1409 ure_ocp_reg_write(sc, 0xa5d4, reg);
1410 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR,
1411 BMCR_AUTOEN | BMCR_STARTNEG);
1412 if (!locked)
1413 URE_UNLOCK(sc);
1414 return (0);
1415 }
1416
1417 mii = GET_MII(sc);
1418
1419 URE_LOCK_ASSERT(sc, MA_OWNED);
1420 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1421 PHY_RESET(miisc);
1422 error = mii_mediachg(mii);
1423 return (error);
1424 }
1425
1426 /*
1427 * Report current media status.
1428 */
1429 static void
ure_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1430 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1431 {
1432 struct ure_softc *sc;
1433 struct mii_data *mii;
1434 uint16_t status;
1435
1436 sc = if_getsoftc(ifp);
1437 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1438 URE_LOCK(sc);
1439 ifmr->ifm_status = IFM_AVALID;
1440 if (ure_get_link_status(sc)) {
1441 ifmr->ifm_status |= IFM_ACTIVE;
1442 status = ure_read_2(sc, URE_PLA_PHYSTATUS,
1443 URE_MCU_TYPE_PLA);
1444 if ((status & URE_PHYSTATUS_FDX) ||
1445 (status & URE_PHYSTATUS_2500MBPS))
1446 ifmr->ifm_active |= IFM_FDX;
1447 else
1448 ifmr->ifm_active |= IFM_HDX;
1449 if (status & URE_PHYSTATUS_10MBPS)
1450 ifmr->ifm_active |= IFM_10_T;
1451 else if (status & URE_PHYSTATUS_100MBPS)
1452 ifmr->ifm_active |= IFM_100_TX;
1453 else if (status & URE_PHYSTATUS_1000MBPS)
1454 ifmr->ifm_active |= IFM_1000_T;
1455 else if (status & URE_PHYSTATUS_2500MBPS)
1456 ifmr->ifm_active |= IFM_2500_T;
1457 }
1458 URE_UNLOCK(sc);
1459 return;
1460 }
1461
1462 mii = GET_MII(sc);
1463
1464 URE_LOCK(sc);
1465 mii_pollstat(mii);
1466 ifmr->ifm_active = mii->mii_media_active;
1467 ifmr->ifm_status = mii->mii_media_status;
1468 URE_UNLOCK(sc);
1469 }
1470
1471 static void
ure_add_media_types(struct ure_softc * sc)1472 ure_add_media_types(struct ure_softc *sc)
1473 {
1474 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1475 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1476 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1477 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1478 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1479 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
1480 }
1481
1482 static void
ure_link_state(struct ure_softc * sc)1483 ure_link_state(struct ure_softc *sc)
1484 {
1485 if_t ifp = uether_getifp(&sc->sc_ue);
1486
1487 if (ure_get_link_status(sc)) {
1488 if (if_getlinkstate(ifp) != LINK_STATE_UP) {
1489 if_link_state_change(ifp, LINK_STATE_UP);
1490 /* Enable transmit and receive. */
1491 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1492
1493 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1494 URE_PHYSTATUS_2500MBPS)
1495 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1496 else
1497 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1498 }
1499 } else {
1500 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) {
1501 if_link_state_change(ifp, LINK_STATE_DOWN);
1502 }
1503 }
1504 }
1505
1506 static int
ure_get_link_status(struct ure_softc * sc)1507 ure_get_link_status(struct ure_softc *sc)
1508 {
1509 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1510 URE_PHYSTATUS_LINK) {
1511 sc->sc_flags |= URE_FLAG_LINK;
1512 return (1);
1513 } else {
1514 sc->sc_flags &= ~URE_FLAG_LINK;
1515 return (0);
1516 }
1517 }
1518
1519 static int
ure_ioctl(if_t ifp,u_long cmd,caddr_t data)1520 ure_ioctl(if_t ifp, u_long cmd, caddr_t data)
1521 {
1522 struct usb_ether *ue = if_getsoftc(ifp);
1523 struct ure_softc *sc;
1524 struct ifreq *ifr;
1525 int error, mask, reinit;
1526
1527 sc = uether_getsc(ue);
1528 ifr = (struct ifreq *)data;
1529 error = 0;
1530 reinit = 0;
1531 switch (cmd) {
1532 case SIOCSIFCAP:
1533 URE_LOCK(sc);
1534 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1535 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1536 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1537 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1538 reinit++;
1539 }
1540 if ((mask & IFCAP_TXCSUM) != 0 &&
1541 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1542 if_togglecapenable(ifp, IFCAP_TXCSUM);
1543 if_togglehwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1544 }
1545 if ((mask & IFCAP_RXCSUM) != 0 &&
1546 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1547 if_togglecapenable(ifp, IFCAP_RXCSUM);
1548 }
1549 if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&
1550 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {
1551 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
1552 if_togglehwassist(ifp, CSUM_IP6_UDP|CSUM_IP6_TCP);
1553 }
1554 if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&
1555 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {
1556 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
1557 }
1558 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1559 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1560 else
1561 reinit = 0;
1562 URE_UNLOCK(sc);
1563 if (reinit > 0)
1564 uether_init(ue);
1565 break;
1566
1567 case SIOCSIFMTU:
1568 /*
1569 * in testing large MTUs "crashes" the device, it
1570 * leaves the device w/ a broken state where link
1571 * is in a bad state.
1572 */
1573 if (ifr->ifr_mtu < ETHERMIN ||
1574 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN -
1575 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) {
1576 error = EINVAL;
1577 break;
1578 }
1579 URE_LOCK(sc);
1580 if (if_getmtu(ifp) != ifr->ifr_mtu)
1581 if_setmtu(ifp, ifr->ifr_mtu);
1582 URE_UNLOCK(sc);
1583 break;
1584
1585 case SIOCGIFMEDIA:
1586 case SIOCSIFMEDIA:
1587 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1588 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
1589 else
1590 error = uether_ioctl(ifp, cmd, data);
1591 break;
1592
1593 default:
1594 error = uether_ioctl(ifp, cmd, data);
1595 break;
1596 }
1597
1598 return (error);
1599 }
1600
1601 static void
ure_rtl8152_init(struct ure_softc * sc)1602 ure_rtl8152_init(struct ure_softc *sc)
1603 {
1604 uint32_t pwrctrl;
1605
1606 ure_enable_aldps(sc, false);
1607
1608 if (sc->sc_chip & URE_CHIP_VER_4C00) {
1609 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1610 }
1611
1612 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT);
1613
1614 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE);
1615
1616 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
1617
1618 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
1619 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1620 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
1621 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
1622 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
1623 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
1624 URE_SPDWN_LINKCHG_MSK);
1625
1626 /* Enable Rx aggregation. */
1627 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1628
1629 ure_enable_aldps(sc, false);
1630
1631 ure_rtl8152_nic_reset(sc);
1632
1633 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
1634 URE_TX_AGG_MAX_THRESHOLD);
1635 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
1636 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
1637 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
1638 }
1639
1640 static void
ure_rtl8153_init(struct ure_softc * sc)1641 ure_rtl8153_init(struct ure_softc *sc)
1642 {
1643 uint16_t val;
1644 uint8_t u1u2[8];
1645 int i;
1646
1647 ure_enable_aldps(sc, false);
1648
1649 memset(u1u2, 0x00, sizeof(u1u2));
1650 ure_write_mem(sc, URE_USB_TOLERANCE,
1651 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1652
1653 for (i = 0; i < URE_TIMEOUT; i++) {
1654 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1655 URE_AUTOLOAD_DONE)
1656 break;
1657 uether_pause(&sc->sc_ue, hz / 100);
1658 }
1659 if (i == URE_TIMEOUT)
1660 device_printf(sc->sc_ue.ue_dev,
1661 "timeout waiting for chip autoload\n");
1662
1663 for (i = 0; i < URE_TIMEOUT; i++) {
1664 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1665 URE_PHY_STAT_MASK;
1666 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1667 break;
1668 uether_pause(&sc->sc_ue, hz / 100);
1669 }
1670 if (i == URE_TIMEOUT)
1671 device_printf(sc->sc_ue.ue_dev,
1672 "timeout waiting for phy to stabilize\n");
1673
1674 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1675
1676 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1677 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1678 val &= ~URE_PWD_DN_SCALE_MASK;
1679 val |= URE_PWD_DN_SCALE(96);
1680 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1681
1682 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1683 } else if (sc->sc_chip & URE_CHIP_VER_5C20)
1684 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS);
1685
1686 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1687 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1688 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1689 0)
1690 val &= ~URE_DYNAMIC_BURST;
1691 else
1692 val |= URE_DYNAMIC_BURST;
1693 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1694 }
1695
1696 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
1697
1698 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
1699
1700 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1701
1702 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1703 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1704 val = URE_LPM_TIMER_500MS;
1705 else
1706 val = URE_LPM_TIMER_500US;
1707 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1708 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1709
1710 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1711 val &= ~URE_SEN_VAL_MASK;
1712 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1713 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1714
1715 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1716
1717 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN);
1718
1719 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1720
1721 memset(u1u2, 0xff, sizeof(u1u2));
1722 ure_write_mem(sc, URE_USB_TOLERANCE,
1723 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1724
1725 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1726 URE_ALDPS_SPDWN_RATIO);
1727 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1728 URE_EEE_SPDWN_RATIO);
1729 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1730 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1731 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1732 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1733 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1734 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1735 URE_EEE_SPDWN_EN);
1736
1737 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1738 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1739 val |= URE_U2P3_ENABLE;
1740 else
1741 val &= ~URE_U2P3_ENABLE;
1742 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1743
1744 memset(u1u2, 0x00, sizeof(u1u2));
1745 ure_write_mem(sc, URE_USB_TOLERANCE,
1746 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1747
1748 ure_enable_aldps(sc, false);
1749
1750 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1751 URE_CHIP_VER_5C20)) {
1752 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1753 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1754 }
1755 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1756 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1757 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1758 ~URE_CTAP_SHORT_EN);
1759 }
1760 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1761 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1762 URE_EEE_CLKDIV_EN);
1763 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1764 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1765 URE_EN_10M_BGOFF);
1766 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1767 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1768 URE_EN_10M_PLLOFF);
1769 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);
1770 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH);
1771
1772 /* Enable LPF corner auto tune. */
1773 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);
1774
1775 /* Adjust 10M amplitude. */
1776 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);
1777 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);
1778
1779 ure_rtl8152_nic_reset(sc);
1780
1781 /* Enable Rx aggregation. */
1782 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1783
1784 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1785 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1786 val |= URE_U2P3_ENABLE;
1787 else
1788 val &= ~URE_U2P3_ENABLE;
1789 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1790
1791 memset(u1u2, 0xff, sizeof(u1u2));
1792 ure_write_mem(sc, URE_USB_TOLERANCE,
1793 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1794 }
1795
1796 static void
ure_rtl8153b_init(struct ure_softc * sc)1797 ure_rtl8153b_init(struct ure_softc *sc)
1798 {
1799 uint16_t val;
1800 int i;
1801
1802 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1803 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);
1804 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);
1805 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);
1806 }
1807
1808 if (sc->sc_flags & URE_FLAG_8156B) {
1809 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);
1810 }
1811
1812 ure_enable_aldps(sc, false);
1813
1814 /* Disable U1U2 */
1815 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1816
1817 /* Wait loading flash */
1818 if (sc->sc_chip == URE_CHIP_VER_7410) {
1819 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&
1820 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {
1821 for (i=0; i < 100; i++) {
1822 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)
1823 break;
1824 uether_pause(&sc->sc_ue, hz / 1000);
1825 }
1826 }
1827 }
1828
1829 for (i = 0; i < URE_TIMEOUT; i++) {
1830 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1831 URE_AUTOLOAD_DONE)
1832 break;
1833 uether_pause(&sc->sc_ue, hz / 100);
1834 }
1835 if (i == URE_TIMEOUT)
1836 device_printf(sc->sc_ue.ue_dev,
1837 "timeout waiting for chip autoload\n");
1838
1839 val = ure_phy_status(sc, 0);
1840 if ((val == URE_PHY_STAT_EXT_INIT) &
1841 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) {
1842 ure_ocp_reg_write(sc, 0xa468,
1843 ure_ocp_reg_read(sc, 0xa468) & ~0x0a);
1844 if (sc->sc_flags & URE_FLAG_8156B)
1845 ure_ocp_reg_write(sc, 0xa466,
1846 ure_ocp_reg_read(sc, 0xa466) & ~0x01);
1847 }
1848
1849 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR);
1850 if (val & BMCR_PDOWN) {
1851 val &= ~BMCR_PDOWN;
1852 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val);
1853 }
1854
1855 ure_phy_status(sc, URE_PHY_STAT_LAN_ON);
1856
1857 /* Disable U2P3 */
1858 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1859
1860 /* MSC timer, 32760 ms. */
1861 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);
1862
1863 /* U1/U2/L1 idle timer, 500 us. */
1864 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1865
1866 /* Disable power cut */
1867 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1868 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1869
1870 /* Disable ups */
1871 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE);
1872 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);
1873
1874 /* Disable queue wake */
1875 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3);
1876 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT);
1877 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG);
1878
1879 /* Disable runtime suspend */
1880 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1881 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN);
1882 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1883
1884 /* Enable U1U2 */
1885 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1886 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1887
1888 if (sc->sc_flags & URE_FLAG_8156B) {
1889 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);
1890 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);
1891
1892 /* enable fc timer and set timer to 600 ms. */
1893 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8));
1894
1895 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {
1896 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1897 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;
1898 val &= ~0x08;
1899 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val);
1900 }
1901
1902 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1903 }
1904
1905 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1906 if (ure_get_link_status(sc))
1907 val |= URE_CUR_LINK_OK;
1908 else
1909 val &= ~URE_CUR_LINK_OK;
1910 val |= URE_POLL_LINK_CHG;
1911 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val);
1912
1913 /* MAC clock speed down */
1914 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1915 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);
1916 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA);
1917 val &= ~0xff;
1918 val |= URE_MAC_CLK_SPDWN_EN | 0x03;
1919 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val);
1920 } else {
1921 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN);
1922 }
1923 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1924
1925 /* Enable Rx aggregation. */
1926 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1927
1928 if (sc->sc_flags & URE_FLAG_8156)
1929 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);
1930
1931 /* Reset tally */
1932 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET);
1933 }
1934
1935 static void
ure_rtl8153b_nic_reset(struct ure_softc * sc)1936 ure_rtl8153b_nic_reset(struct ure_softc *sc)
1937 {
1938 if_t ifp = uether_getifp(&sc->sc_ue);
1939 uint16_t val;
1940 int i;
1941
1942 /* Disable U1U2 */
1943 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1944
1945 /* Disable U2P3 */
1946 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1947
1948 ure_enable_aldps(sc, false);
1949
1950 /* Enable rxdy_gated */
1951 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1952
1953 /* Disable teredo */
1954 ure_disable_teredo(sc);
1955
1956 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1957 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1958
1959 ure_reset(sc);
1960
1961 /* Reset BMU */
1962 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1963 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1964
1965 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1966 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1967 if (sc->sc_flags & URE_FLAG_8153B) {
1968 for (i = 0; i < URE_TIMEOUT; i++) {
1969 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1970 URE_LINK_LIST_READY)
1971 break;
1972 uether_pause(&sc->sc_ue, hz / 100);
1973 }
1974 if (i == URE_TIMEOUT)
1975 device_printf(sc->sc_ue.ue_dev,
1976 "timeout waiting for OOB control\n");
1977
1978 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
1979 for (i = 0; i < URE_TIMEOUT; i++) {
1980 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1981 URE_LINK_LIST_READY)
1982 break;
1983 uether_pause(&sc->sc_ue, hz / 100);
1984 }
1985 if (i == URE_TIMEOUT)
1986 device_printf(sc->sc_ue.ue_dev,
1987 "timeout waiting for OOB control\n");
1988 }
1989
1990 /* Configure rxvlan */
1991 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);
1992 val &= ~0x00c0;
1993 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)
1994 val |= 0x00c0;
1995 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);
1996
1997 val = if_getmtu(ifp);
1998 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val));
1999 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO);
2000
2001 if (sc->sc_flags & URE_FLAG_8153B) {
2002 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
2003 ure_reset(sc);
2004 }
2005
2006 /* Configure fc parameter */
2007 if (sc->sc_flags & URE_FLAG_8156) {
2008 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);
2009 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);
2010 } else if (sc->sc_flags & URE_FLAG_8156B) {
2011 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);
2012 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);
2013 }
2014
2015 /* Configure Rx FIFO threshold. */
2016 if (sc->sc_flags & URE_FLAG_8153B) {
2017 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL);
2018 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL);
2019 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL);
2020 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B);
2021 } else {
2022 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,
2023 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);
2024 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);
2025 }
2026
2027 /* Configure Tx FIFO threshold. */
2028 if (sc->sc_flags & URE_FLAG_8153B) {
2029 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
2030 } else if (sc->sc_flags & URE_FLAG_8156) {
2031 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
2032 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);
2033 } else if (sc->sc_flags & URE_FLAG_8156B) {
2034 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);
2035 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,
2036 (URE_FRAMELEN(val) + 0x100) / 16 );
2037 }
2038
2039 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
2040
2041 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
2042 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);
2043
2044 ure_enable_aldps(sc, true);
2045
2046 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
2047 /* Enable U2P3 */
2048 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
2049 }
2050
2051 /* Enable U1U2 */
2052 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
2053 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
2054 }
2055
2056 static void
ure_stop(struct usb_ether * ue)2057 ure_stop(struct usb_ether *ue)
2058 {
2059 struct ure_softc *sc = uether_getsc(ue);
2060 if_t ifp = uether_getifp(ue);
2061
2062 URE_LOCK_ASSERT(sc, MA_OWNED);
2063
2064 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2065 sc->sc_flags &= ~URE_FLAG_LINK;
2066 sc->sc_rxstarted = 0;
2067
2068 /*
2069 * stop all the transfers, if not already stopped:
2070 */
2071 for (int i = 0; i < URE_MAX_RX; i++)
2072 usbd_transfer_stop(sc->sc_rx_xfer[i]);
2073 for (int i = 0; i < URE_MAX_TX; i++)
2074 usbd_transfer_stop(sc->sc_tx_xfer[i]);
2075 }
2076
2077 static void
ure_disable_teredo(struct ure_softc * sc)2078 ure_disable_teredo(struct ure_softc *sc)
2079 {
2080
2081 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
2082 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);
2083 else {
2084 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
2085 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
2086 }
2087 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE);
2088 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
2089 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
2090 }
2091
2092 static void
ure_enable_aldps(struct ure_softc * sc,bool enable)2093 ure_enable_aldps(struct ure_softc *sc, bool enable)
2094 {
2095 int i;
2096
2097 if (enable) {
2098 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
2099 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
2100 } else {
2101 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
2102 URE_DIS_SDSAVE);
2103 for (i = 0; i < 20; i++) {
2104 uether_pause(&sc->sc_ue, hz / 1000);
2105 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)
2106 break;
2107 }
2108 }
2109 }
2110
2111 static uint16_t
ure_phy_status(struct ure_softc * sc,uint16_t desired)2112 ure_phy_status(struct ure_softc *sc, uint16_t desired)
2113 {
2114 uint16_t val;
2115 int i;
2116
2117 for (i = 0; i < URE_TIMEOUT; i++) {
2118 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
2119 URE_PHY_STAT_MASK;
2120 if (desired) {
2121 if (val == desired)
2122 break;
2123 } else {
2124 if (val == URE_PHY_STAT_LAN_ON ||
2125 val == URE_PHY_STAT_PWRDN ||
2126 val == URE_PHY_STAT_EXT_INIT)
2127 break;
2128 }
2129 uether_pause(&sc->sc_ue, hz / 100);
2130 }
2131 if (i == URE_TIMEOUT)
2132 device_printf(sc->sc_ue.ue_dev,
2133 "timeout waiting for phy to stabilize\n");
2134
2135 return (val);
2136 }
2137
2138 static void
ure_rtl8152_nic_reset(struct ure_softc * sc)2139 ure_rtl8152_nic_reset(struct ure_softc *sc)
2140 {
2141 uint32_t rx_fifo1, rx_fifo2;
2142 int i;
2143
2144 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
2145
2146 ure_disable_teredo(sc);
2147
2148 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
2149 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
2150
2151 ure_reset(sc);
2152
2153 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
2154
2155 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
2156
2157 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
2158 for (i = 0; i < URE_TIMEOUT; i++) {
2159 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2160 URE_LINK_LIST_READY)
2161 break;
2162 uether_pause(&sc->sc_ue, hz / 100);
2163 }
2164 if (i == URE_TIMEOUT)
2165 device_printf(sc->sc_ue.ue_dev,
2166 "timeout waiting for OOB control\n");
2167 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
2168 for (i = 0; i < URE_TIMEOUT; i++) {
2169 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2170 URE_LINK_LIST_READY)
2171 break;
2172 uether_pause(&sc->sc_ue, hz / 100);
2173 }
2174 if (i == URE_TIMEOUT)
2175 device_printf(sc->sc_ue.ue_dev,
2176 "timeout waiting for OOB control\n");
2177
2178 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN);
2179
2180 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
2181
2182 /* Configure Rx FIFO threshold. */
2183 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
2184 URE_RXFIFO_THR1_NORMAL);
2185 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
2186 rx_fifo1 = URE_RXFIFO_THR2_FULL;
2187 rx_fifo2 = URE_RXFIFO_THR3_FULL;
2188 } else {
2189 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
2190 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
2191 }
2192 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
2193 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
2194
2195 /* Configure Tx FIFO threshold. */
2196 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
2197 URE_TXFIFO_THR_NORMAL);
2198 }
2199
2200 /*
2201 * Update mbuf for rx checksum from hardware
2202 */
2203 static void
ure_rxcsum(int capenb,struct ure_rxpkt * rp,struct mbuf * m)2204 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m)
2205 {
2206 uint32_t csum, misc;
2207
2208 m->m_pkthdr.csum_flags = 0;
2209
2210 csum = le32toh(rp->ure_csum);
2211 misc = le32toh(rp->ure_misc);
2212
2213 if ((capenb & IFCAP_RXCSUM) == 0 &&
2214 (csum & URE_RXPKT_IPV4_CS) != 0)
2215 return;
2216 if ((capenb & IFCAP_RXCSUM_IPV6) == 0 &&
2217 (csum & URE_RXPKT_IPV6_CS) != 0)
2218 return;
2219
2220 if ((csum & URE_RXPKT_IPV4_CS) != 0) {
2221 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2222 if (__predict_true((misc & URE_RXPKT_IP_F) == 0))
2223 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2224 }
2225 if (__predict_true(
2226 ((rp->ure_csum & URE_RXPKT_TCP_CS) != 0 &&
2227 (misc & URE_RXPKT_TCP_F) == 0) ||
2228 ((rp->ure_csum & URE_RXPKT_UDP_CS) != 0 &&
2229 (misc & URE_RXPKT_UDP_F) == 0))) {
2230 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2231 m->m_pkthdr.csum_data = 0xFFFF;
2232 }
2233 }
2234
2235 /*
2236 * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2237 * We currently restrict MTU such that it can't happen, and even if we
2238 * did have a large enough MTU, only a very specially crafted IPv6 packet
2239 * with MANY headers could possibly come close.
2240 *
2241 * Returns 0 for success, and 1 if the packet cannot be checksummed and
2242 * should be dropped.
2243 */
2244 static int
ure_txcsum(struct mbuf * m,int caps,uint32_t * regout)2245 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout)
2246 {
2247 struct ip ip;
2248 struct ether_header *eh;
2249 int flags;
2250 uint32_t reg;
2251 int l3off, l4off;
2252 uint16_t type;
2253
2254 *regout = 0;
2255 flags = m->m_pkthdr.csum_flags;
2256 if (flags == 0)
2257 return (0);
2258
2259 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
2260 eh = mtod(m, struct ether_header *);
2261 type = eh->ether_type;
2262 } else
2263 m_copydata(m, offsetof(struct ether_header, ether_type),
2264 sizeof(type), (caddr_t)&type);
2265
2266 switch (type = htons(type)) {
2267 case ETHERTYPE_IP:
2268 case ETHERTYPE_IPV6:
2269 l3off = ETHER_HDR_LEN;
2270 break;
2271 case ETHERTYPE_VLAN:
2272 /* XXX - what about QinQ? */
2273 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2274 break;
2275 default:
2276 return (0);
2277 }
2278
2279 reg = 0;
2280
2281 if (flags & CSUM_IP)
2282 reg |= URE_TXPKT_IPV4_CS;
2283
2284 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) {
2285 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip);
2286 l4off = l3off + (ip.ip_hl << 2);
2287 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2288 return (1);
2289
2290 reg |= URE_TXPKT_IPV4_CS;
2291 if (flags & CSUM_IP_TCP)
2292 reg |= URE_TXPKT_TCP_CS;
2293 else if (flags & CSUM_IP_UDP)
2294 reg |= URE_TXPKT_UDP_CS;
2295 reg |= l4off << URE_L4_OFFSET_SHIFT;
2296 }
2297 #ifdef INET6
2298 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
2299 l4off = ip6_lasthdr(m, l3off, IPPROTO_IPV6, NULL);
2300 if (__predict_false(l4off < 0))
2301 return (1);
2302 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2303 return (1);
2304
2305 reg |= URE_TXPKT_IPV6_CS;
2306 if (flags & CSUM_IP6_TCP)
2307 reg |= URE_TXPKT_TCP_CS;
2308 else if (flags & CSUM_IP6_UDP)
2309 reg |= URE_TXPKT_UDP_CS;
2310 reg |= l4off << URE_L4_OFFSET_SHIFT;
2311 }
2312 #endif
2313 *regout = reg;
2314 return 0;
2315 }
2316