xref: /freebsd/sys/dev/cxgbe/t4_main.c (revision c029d04671e904ce7e194fb441704b6a814f40f5) 
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2011, 2025 Chelsio Communications.
5  * Written by: Navdeep Parhar <np@FreeBSD.org>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #include "opt_ddb.h"
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_kern_tls.h"
34 #include "opt_ratelimit.h"
35 #include "opt_rss.h"
36 
37 #include <sys/param.h>
38 #include <sys/conf.h>
39 #include <sys/priv.h>
40 #include <sys/kernel.h>
41 #include <sys/bus.h>
42 #include <sys/eventhandler.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
46 #include <sys/taskqueue.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <sys/firmware.h>
50 #include <sys/sbuf.h>
51 #include <sys/smp.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55 #include <net/ethernet.h>
56 #include <net/if.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
59 #include <net/if_vlan_var.h>
60 #include <net/rss_config.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
63 #ifdef KERN_TLS
64 #include <netinet/tcp_seq.h>
65 #endif
66 #if defined(__i386__) || defined(__amd64__)
67 #include <machine/md_var.h>
68 #include <machine/cputypes.h>
69 #include <vm/vm.h>
70 #include <vm/pmap.h>
71 #endif
72 #ifdef DDB
73 #include <ddb/ddb.h>
74 #include <ddb/db_lex.h>
75 #endif
76 
77 #include "common/common.h"
78 #include "common/t4_msg.h"
79 #include "common/t4_regs.h"
80 #include "common/t4_regs_values.h"
81 #include "cudbg/cudbg.h"
82 #include "t4_clip.h"
83 #include "t4_ioctl.h"
84 #include "t4_l2t.h"
85 #include "t4_mp_ring.h"
86 #include "t4_if.h"
87 #include "t4_smt.h"
88 
89 /* T4 bus driver interface */
90 static int t4_probe(device_t);
91 static int t4_attach(device_t);
92 static int t4_detach(device_t);
93 static int t4_child_location(device_t, device_t, struct sbuf *);
94 static int t4_ready(device_t);
95 static int t4_read_port_device(device_t, int, device_t *);
96 static int t4_suspend(device_t);
97 static int t4_resume(device_t);
98 static int t4_reset_prepare(device_t, device_t);
99 static int t4_reset_post(device_t, device_t);
100 static device_method_t t4_methods[] = {
101 	DEVMETHOD(device_probe,		t4_probe),
102 	DEVMETHOD(device_attach,	t4_attach),
103 	DEVMETHOD(device_detach,	t4_detach),
104 	DEVMETHOD(device_suspend,	t4_suspend),
105 	DEVMETHOD(device_resume,	t4_resume),
106 
107 	DEVMETHOD(bus_child_location,	t4_child_location),
108 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
109 	DEVMETHOD(bus_reset_post,	t4_reset_post),
110 
111 	DEVMETHOD(t4_is_main_ready,	t4_ready),
112 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
113 
114 	DEVMETHOD_END
115 };
116 static driver_t t4_driver = {
117 	"t4nex",
118 	t4_methods,
119 	sizeof(struct adapter)
120 };
121 
122 
123 /* T4 port (cxgbe) interface */
124 static int cxgbe_probe(device_t);
125 static int cxgbe_attach(device_t);
126 static int cxgbe_detach(device_t);
127 device_method_t cxgbe_methods[] = {
128 	DEVMETHOD(device_probe,		cxgbe_probe),
129 	DEVMETHOD(device_attach,	cxgbe_attach),
130 	DEVMETHOD(device_detach,	cxgbe_detach),
131 	DEVMETHOD_END
132 };
133 static driver_t cxgbe_driver = {
134 	"cxgbe",
135 	cxgbe_methods,
136 	sizeof(struct port_info)
137 };
138 
139 /* T4 VI (vcxgbe) interface */
140 static int vcxgbe_probe(device_t);
141 static int vcxgbe_attach(device_t);
142 static int vcxgbe_detach(device_t);
143 static device_method_t vcxgbe_methods[] = {
144 	DEVMETHOD(device_probe,		vcxgbe_probe),
145 	DEVMETHOD(device_attach,	vcxgbe_attach),
146 	DEVMETHOD(device_detach,	vcxgbe_detach),
147 	DEVMETHOD_END
148 };
149 static driver_t vcxgbe_driver = {
150 	"vcxgbe",
151 	vcxgbe_methods,
152 	sizeof(struct vi_info)
153 };
154 
155 static d_ioctl_t t4_ioctl;
156 
157 static struct cdevsw t4_cdevsw = {
158        .d_version = D_VERSION,
159        .d_ioctl = t4_ioctl,
160        .d_name = "t4nex",
161 };
162 
163 /* T5 bus driver interface */
164 static int t5_probe(device_t);
165 static device_method_t t5_methods[] = {
166 	DEVMETHOD(device_probe,		t5_probe),
167 	DEVMETHOD(device_attach,	t4_attach),
168 	DEVMETHOD(device_detach,	t4_detach),
169 	DEVMETHOD(device_suspend,	t4_suspend),
170 	DEVMETHOD(device_resume,	t4_resume),
171 
172 	DEVMETHOD(bus_child_location,	t4_child_location),
173 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
174 	DEVMETHOD(bus_reset_post,	t4_reset_post),
175 
176 	DEVMETHOD(t4_is_main_ready,	t4_ready),
177 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
178 
179 	DEVMETHOD_END
180 };
181 static driver_t t5_driver = {
182 	"t5nex",
183 	t5_methods,
184 	sizeof(struct adapter)
185 };
186 
187 
188 /* T5 port (cxl) interface */
189 static driver_t cxl_driver = {
190 	"cxl",
191 	cxgbe_methods,
192 	sizeof(struct port_info)
193 };
194 
195 /* T5 VI (vcxl) interface */
196 static driver_t vcxl_driver = {
197 	"vcxl",
198 	vcxgbe_methods,
199 	sizeof(struct vi_info)
200 };
201 
202 /* T6 bus driver interface */
203 static int t6_probe(device_t);
204 static device_method_t t6_methods[] = {
205 	DEVMETHOD(device_probe,		t6_probe),
206 	DEVMETHOD(device_attach,	t4_attach),
207 	DEVMETHOD(device_detach,	t4_detach),
208 	DEVMETHOD(device_suspend,	t4_suspend),
209 	DEVMETHOD(device_resume,	t4_resume),
210 
211 	DEVMETHOD(bus_child_location,	t4_child_location),
212 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
213 	DEVMETHOD(bus_reset_post,	t4_reset_post),
214 
215 	DEVMETHOD(t4_is_main_ready,	t4_ready),
216 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
217 
218 	DEVMETHOD_END
219 };
220 static driver_t t6_driver = {
221 	"t6nex",
222 	t6_methods,
223 	sizeof(struct adapter)
224 };
225 
226 
227 /* T6 port (cc) interface */
228 static driver_t cc_driver = {
229 	"cc",
230 	cxgbe_methods,
231 	sizeof(struct port_info)
232 };
233 
234 /* T6 VI (vcc) interface */
235 static driver_t vcc_driver = {
236 	"vcc",
237 	vcxgbe_methods,
238 	sizeof(struct vi_info)
239 };
240 
241 /* T7+ bus driver interface */
242 static int ch_probe(device_t);
243 static device_method_t ch_methods[] = {
244 	DEVMETHOD(device_probe,		ch_probe),
245 	DEVMETHOD(device_attach,	t4_attach),
246 	DEVMETHOD(device_detach,	t4_detach),
247 	DEVMETHOD(device_suspend,	t4_suspend),
248 	DEVMETHOD(device_resume,	t4_resume),
249 
250 	DEVMETHOD(bus_child_location,	t4_child_location),
251 	DEVMETHOD(bus_reset_prepare, 	t4_reset_prepare),
252 	DEVMETHOD(bus_reset_post, 	t4_reset_post),
253 
254 	DEVMETHOD(t4_is_main_ready,	t4_ready),
255 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
256 
257 	DEVMETHOD_END
258 };
259 static driver_t ch_driver = {
260 	"chnex",
261 	ch_methods,
262 	sizeof(struct adapter)
263 };
264 
265 
266 /* T7+ port (che) interface */
267 static driver_t che_driver = {
268 	"che",
269 	cxgbe_methods,
270 	sizeof(struct port_info)
271 };
272 
273 /* T7+ VI (vche) interface */
274 static driver_t vche_driver = {
275 	"vche",
276 	vcxgbe_methods,
277 	sizeof(struct vi_info)
278 };
279 
280 /* ifnet interface */
281 static void cxgbe_init(void *);
282 static int cxgbe_ioctl(if_t, unsigned long, caddr_t);
283 static int cxgbe_transmit(if_t, struct mbuf *);
284 static void cxgbe_qflush(if_t);
285 #if defined(KERN_TLS) || defined(RATELIMIT)
286 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *,
287     struct m_snd_tag **);
288 #endif
289 
290 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
291 
292 /*
293  * Correct lock order when you need to acquire multiple locks is t4_list_lock,
294  * then ADAPTER_LOCK, then t4_uld_list_lock.
295  */
296 static struct sx t4_list_lock;
297 SLIST_HEAD(, adapter) t4_list;
298 #ifdef TCP_OFFLOAD
299 static struct sx t4_uld_list_lock;
300 struct uld_info *t4_uld_list[ULD_MAX + 1];
301 #endif
302 
303 /*
304  * Tunables.  See tweak_tunables() too.
305  *
306  * Each tunable is set to a default value here if it's known at compile-time.
307  * Otherwise it is set to -n as an indication to tweak_tunables() that it should
308  * provide a reasonable default (upto n) when the driver is loaded.
309  *
310  * Tunables applicable to both T4 and T5 are under hw.cxgbe.  Those specific to
311  * T5 are under hw.cxl.
312  */
313 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
314     "cxgbe(4) parameters");
315 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
316     "cxgbe(4) T5+ parameters");
317 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
318     "cxgbe(4) TOE parameters");
319 
320 /*
321  * Number of queues for tx and rx, NIC and offload.
322  */
323 #define NTXQ 16
324 int t4_ntxq = -NTXQ;
325 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
326     "Number of TX queues per port");
327 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq);	/* Old name, undocumented */
328 
329 #define NRXQ 8
330 int t4_nrxq = -NRXQ;
331 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
332     "Number of RX queues per port");
333 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq);	/* Old name, undocumented */
334 
335 #define NTXQ_VI 1
336 static int t4_ntxq_vi = -NTXQ_VI;
337 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
338     "Number of TX queues per VI");
339 
340 #define NRXQ_VI 1
341 static int t4_nrxq_vi = -NRXQ_VI;
342 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
343     "Number of RX queues per VI");
344 
345 static int t4_rsrv_noflowq = 0;
346 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
347     0, "Reserve TX queue 0 of each VI for non-flowid packets");
348 
349 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
350 #define NOFLDTXQ 8
351 static int t4_nofldtxq = -NOFLDTXQ;
352 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
353     "Number of offload TX queues per port");
354 
355 #define NOFLDTXQ_VI 1
356 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
357 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
358     "Number of offload TX queues per VI");
359 #endif
360 
361 #if defined(TCP_OFFLOAD)
362 #define NOFLDRXQ 2
363 static int t4_nofldrxq = -NOFLDRXQ;
364 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
365     "Number of offload RX queues per port");
366 
367 #define NOFLDRXQ_VI 1
368 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
369 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
370     "Number of offload RX queues per VI");
371 
372 #define TMR_IDX_OFLD 1
373 static int t4_tmr_idx_ofld = TMR_IDX_OFLD;
374 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
375     &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
376 
377 #define PKTC_IDX_OFLD (-1)
378 static int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
379 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
380     &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
381 
382 /* 0 means chip/fw default, non-zero number is value in microseconds */
383 static u_long t4_toe_keepalive_idle = 0;
384 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
385     &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
386 
387 /* 0 means chip/fw default, non-zero number is value in microseconds */
388 static u_long t4_toe_keepalive_interval = 0;
389 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
390     &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
391 
392 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
393 static int t4_toe_keepalive_count = 0;
394 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
395     &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
396 
397 /* 0 means chip/fw default, non-zero number is value in microseconds */
398 static u_long t4_toe_rexmt_min = 0;
399 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
400     &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
401 
402 /* 0 means chip/fw default, non-zero number is value in microseconds */
403 static u_long t4_toe_rexmt_max = 0;
404 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
405     &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
406 
407 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
408 static int t4_toe_rexmt_count = 0;
409 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
410     &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
411 
412 /* -1 means chip/fw default, other values are raw backoff values to use */
413 static int t4_toe_rexmt_backoff[16] = {
414 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
415 };
416 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff,
417     CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
418     "cxgbe(4) TOE retransmit backoff values");
419 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
420     &t4_toe_rexmt_backoff[0], 0, "");
421 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
422     &t4_toe_rexmt_backoff[1], 0, "");
423 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
424     &t4_toe_rexmt_backoff[2], 0, "");
425 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
426     &t4_toe_rexmt_backoff[3], 0, "");
427 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
428     &t4_toe_rexmt_backoff[4], 0, "");
429 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
430     &t4_toe_rexmt_backoff[5], 0, "");
431 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
432     &t4_toe_rexmt_backoff[6], 0, "");
433 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
434     &t4_toe_rexmt_backoff[7], 0, "");
435 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
436     &t4_toe_rexmt_backoff[8], 0, "");
437 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
438     &t4_toe_rexmt_backoff[9], 0, "");
439 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
440     &t4_toe_rexmt_backoff[10], 0, "");
441 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
442     &t4_toe_rexmt_backoff[11], 0, "");
443 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
444     &t4_toe_rexmt_backoff[12], 0, "");
445 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
446     &t4_toe_rexmt_backoff[13], 0, "");
447 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
448     &t4_toe_rexmt_backoff[14], 0, "");
449 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
450     &t4_toe_rexmt_backoff[15], 0, "");
451 
452 int t4_ddp_rcvbuf_len = 256 * 1024;
453 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN,
454     &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer");
455 
456 unsigned int t4_ddp_rcvbuf_cache = 4;
457 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN,
458     &t4_ddp_rcvbuf_cache, 0,
459     "maximum number of free DDP RX buffers to cache per connection");
460 #endif
461 
462 #ifdef DEV_NETMAP
463 #define NN_MAIN_VI	(1 << 0)	/* Native netmap on the main VI */
464 #define NN_EXTRA_VI	(1 << 1)	/* Native netmap on the extra VI(s) */
465 static int t4_native_netmap = NN_EXTRA_VI;
466 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
467     0, "Native netmap support.  bit 0 = main VI, bit 1 = extra VIs");
468 
469 #define NNMTXQ 8
470 static int t4_nnmtxq = -NNMTXQ;
471 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
472     "Number of netmap TX queues");
473 
474 #define NNMRXQ 8
475 static int t4_nnmrxq = -NNMRXQ;
476 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
477     "Number of netmap RX queues");
478 
479 #define NNMTXQ_VI 2
480 static int t4_nnmtxq_vi = -NNMTXQ_VI;
481 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
482     "Number of netmap TX queues per VI");
483 
484 #define NNMRXQ_VI 2
485 static int t4_nnmrxq_vi = -NNMRXQ_VI;
486 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
487     "Number of netmap RX queues per VI");
488 #endif
489 
490 /*
491  * Holdoff parameters for ports.
492  */
493 #define TMR_IDX 1
494 int t4_tmr_idx = TMR_IDX;
495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
496     0, "Holdoff timer index");
497 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx);	/* Old name */
498 
499 #define PKTC_IDX (-1)
500 int t4_pktc_idx = PKTC_IDX;
501 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
502     0, "Holdoff packet counter index");
503 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx);	/* Old name */
504 
505 /*
506  * Size (# of entries) of each tx and rx queue.
507  */
508 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
510     "Number of descriptors in each TX queue");
511 
512 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
513 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
514     "Number of descriptors in each RX queue");
515 
516 /*
517  * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
518  */
519 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
520 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
521     0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
522 
523 /*
524  * Configuration file.  All the _CF names here are special.
525  */
526 #define DEFAULT_CF	"default"
527 #define BUILTIN_CF	"built-in"
528 #define FLASH_CF	"flash"
529 #define UWIRE_CF	"uwire"
530 #define FPGA_CF		"fpga"
531 static char t4_cfg_file[32] = DEFAULT_CF;
532 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
533     sizeof(t4_cfg_file), "Firmware configuration file");
534 
535 /*
536  * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
537  * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
538  * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
539  *            mark or when signalled to do so, 0 to never emit PAUSE.
540  * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
541  *                 negotiated settings will override rx_pause/tx_pause.
542  *                 Otherwise rx_pause/tx_pause are applied forcibly.
543  */
544 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
545 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
546     &t4_pause_settings, 0,
547     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
548 
549 /*
550  * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
551  * -1 to run with the firmware default.  Same as FEC_AUTO (bit 5)
552  *  0 to disable FEC.
553  */
554 static int t4_fec = -1;
555 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
556     "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
557 
558 static const char *
559 t4_fec_bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2\6auto\7module";
560 
561 /*
562  * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it
563  * issues to the firmware.  If the firmware doesn't support FORCE_FEC then the
564  * driver runs as if this is set to 0.
565  * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay.
566  *  0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the
567  *    transceiver. Multiple FEC bits may not be okay but will be passed on to
568  *    the firmware anyway (may result in l1cfg errors with old firmwares).
569  *  1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO
570  *    means set all FEC bits that are valid for the speed.
571  */
572 static int t4_force_fec = -1;
573 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0,
574     "Controls the use of FORCE_FEC bit in L1 configuration.");
575 
576 /*
577  * Link autonegotiation.
578  * -1 to run with the firmware default.
579  *  0 to disable.
580  *  1 to enable.
581  */
582 static int t4_autoneg = -1;
583 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
584     "Link autonegotiation");
585 
586 /*
587  * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
588  * encouraged respectively).  '-n' is the same as 'n' except the firmware
589  * version used in the checks is read from the firmware bundled with the driver.
590  */
591 static int t4_fw_install = 1;
592 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
593     "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
594 
595 /*
596  * ASIC features that will be used.  Disable the ones you don't want so that the
597  * chip resources aren't wasted on features that will not be used.
598  */
599 static int t4_nbmcaps_allowed = 0;
600 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
601     &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
602 
603 static int t4_linkcaps_allowed = 0;	/* No DCBX, PPP, etc. by default */
604 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
605     &t4_linkcaps_allowed, 0, "Default link capabilities");
606 
607 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
608     FW_CAPS_CONFIG_SWITCH_EGRESS;
609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
610     &t4_switchcaps_allowed, 0, "Default switch capabilities");
611 
612 static int t4_nvmecaps_allowed = -1;
613 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nvmecaps_allowed, CTLFLAG_RDTUN,
614     &t4_nvmecaps_allowed, 0, "Default NVMe capabilities");
615 
616 #ifdef RATELIMIT
617 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
618 	FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
619 #else
620 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
621 	FW_CAPS_CONFIG_NIC_HASHFILTER;
622 #endif
623 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
624     &t4_niccaps_allowed, 0, "Default NIC capabilities");
625 
626 static int t4_toecaps_allowed = -1;
627 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
628     &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
629 
630 static int t4_rdmacaps_allowed = -1;
631 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
632     &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
633 
634 static int t4_cryptocaps_allowed = -1;
635 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
636     &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
637 
638 static int t4_iscsicaps_allowed = -1;
639 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
640     &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
641 
642 static int t4_fcoecaps_allowed = 0;
643 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
644     &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
645 
646 static int t5_write_combine = 0;
647 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
648     0, "Use WC instead of UC for BAR2");
649 
650 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */
651 static int t4_doorbells_allowed = 0xf;
652 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN,
653 	   &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells");
654 
655 static int t4_num_vis = 1;
656 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
657     "Number of VIs per port");
658 
659 /*
660  * PCIe Relaxed Ordering.
661  * -1: driver should figure out a good value.
662  * 0: disable RO.
663  * 1: enable RO.
664  * 2: leave RO alone.
665  */
666 static int pcie_relaxed_ordering = -1;
667 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
668     &pcie_relaxed_ordering, 0,
669     "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
670 
671 static int t4_panic_on_fatal_err = 0;
672 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN,
673     &t4_panic_on_fatal_err, 0, "panic on fatal errors");
674 
675 static int t4_reset_on_fatal_err = 0;
676 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN,
677     &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors");
678 
679 static int t4_reset_method = 1;
680 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_method, CTLFLAG_RWTUN, &t4_reset_method,
681     0, "reset method: 0 = PL_RST, 1 = PCIe secondary bus reset, 2 = PCIe link bounce");
682 
683 static int t4_clock_gate_on_suspend = 0;
684 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN,
685     &t4_clock_gate_on_suspend, 0, "gate the clock on suspend");
686 
687 static int t4_tx_vm_wr = 0;
688 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0,
689     "Use VM work requests to transmit packets.");
690 
691 /*
692  * Set to non-zero to enable the attack filter.  A packet that matches any of
693  * these conditions will get dropped on ingress:
694  * 1) IP && source address == destination address.
695  * 2) TCP/IP && source address is not a unicast address.
696  * 3) TCP/IP && destination address is not a unicast address.
697  * 4) IP && source address is loopback (127.x.y.z).
698  * 5) IP && destination address is loopback (127.x.y.z).
699  * 6) IPv6 && source address == destination address.
700  * 7) IPv6 && source address is not a unicast address.
701  * 8) IPv6 && source address is loopback (::1/128).
702  * 9) IPv6 && destination address is loopback (::1/128).
703  * 10) IPv6 && source address is unspecified (::/128).
704  * 11) IPv6 && destination address is unspecified (::/128).
705  * 12) TCP/IPv6 && source address is multicast (ff00::/8).
706  * 13) TCP/IPv6 && destination address is multicast (ff00::/8).
707  */
708 static int t4_attack_filter = 0;
709 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN,
710     &t4_attack_filter, 0, "Drop suspicious traffic");
711 
712 static int t4_drop_ip_fragments = 0;
713 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN,
714     &t4_drop_ip_fragments, 0, "Drop IP fragments");
715 
716 static int t4_drop_pkts_with_l2_errors = 1;
717 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN,
718     &t4_drop_pkts_with_l2_errors, 0,
719     "Drop all frames with Layer 2 length or checksum errors");
720 
721 static int t4_drop_pkts_with_l3_errors = 0;
722 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN,
723     &t4_drop_pkts_with_l3_errors, 0,
724     "Drop all frames with IP version, length, or checksum errors");
725 
726 static int t4_drop_pkts_with_l4_errors = 0;
727 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN,
728     &t4_drop_pkts_with_l4_errors, 0,
729     "Drop all frames with Layer 4 length, checksum, or other errors");
730 
731 #ifdef TCP_OFFLOAD
732 /*
733  * TOE tunables.
734  */
735 static int t4_cop_managed_offloading = 0;
736 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
737     &t4_cop_managed_offloading, 0,
738     "COP (Connection Offload Policy) controls all TOE offload");
739 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading);
740 #endif
741 
742 #ifdef KERN_TLS
743 /*
744  * This enables KERN_TLS for all adapters if set.
745  */
746 static int t4_kern_tls = 0;
747 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
748     "Enable KERN_TLS mode for T6 adapters");
749 
750 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
751     "cxgbe(4) KERN_TLS parameters");
752 
753 static int t4_tls_inline_keys = 0;
754 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
755     &t4_tls_inline_keys, 0,
756     "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
757     "in card memory.");
758 
759 static int t4_tls_combo_wrs = 0;
760 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
761     0, "Attempt to combine TCB field updates with TLS record work requests.");
762 
763 static int t4_tls_short_records = 1;
764 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, short_records, CTLFLAG_RDTUN,
765     &t4_tls_short_records, 0, "Use cipher-only mode for short records.");
766 
767 static int t4_tls_partial_ghash = 1;
768 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, partial_ghash, CTLFLAG_RDTUN,
769     &t4_tls_partial_ghash, 0, "Use partial GHASH for AES-GCM records.");
770 #endif
771 
772 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
773 static int vi_mac_funcs[] = {
774 	FW_VI_FUNC_ETH,
775 	FW_VI_FUNC_OFLD,
776 	FW_VI_FUNC_IWARP,
777 	FW_VI_FUNC_OPENISCSI,
778 	FW_VI_FUNC_OPENFCOE,
779 	FW_VI_FUNC_FOISCSI,
780 	FW_VI_FUNC_FOFCOE,
781 };
782 
783 struct intrs_and_queues {
784 	uint16_t intr_type;	/* INTx, MSI, or MSI-X */
785 	uint16_t num_vis;	/* number of VIs for each port */
786 	uint16_t nirq;		/* Total # of vectors */
787 	uint16_t ntxq;		/* # of NIC txq's for each port */
788 	uint16_t nrxq;		/* # of NIC rxq's for each port */
789 	uint16_t nofldtxq;	/* # of TOE/ETHOFLD txq's for each port */
790 	uint16_t nofldrxq;	/* # of TOE rxq's for each port */
791 	uint16_t nnmtxq;	/* # of netmap txq's */
792 	uint16_t nnmrxq;	/* # of netmap rxq's */
793 
794 	/* The vcxgbe/vcxl interfaces use these and not the ones above. */
795 	uint16_t ntxq_vi;	/* # of NIC txq's */
796 	uint16_t nrxq_vi;	/* # of NIC rxq's */
797 	uint16_t nofldtxq_vi;	/* # of TOE txq's */
798 	uint16_t nofldrxq_vi;	/* # of TOE rxq's */
799 	uint16_t nnmtxq_vi;	/* # of netmap txq's */
800 	uint16_t nnmrxq_vi;	/* # of netmap rxq's */
801 };
802 
803 static void setup_memwin(struct adapter *);
804 static void position_memwin(struct adapter *, int, uint32_t);
805 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
806 static int fwmtype_to_hwmtype(int);
807 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
808     uint32_t *);
809 static int fixup_devlog_ncores_params(struct adapter *);
810 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
811 static int contact_firmware(struct adapter *);
812 static int partition_resources(struct adapter *);
813 static int get_params__pre_init(struct adapter *);
814 static int set_params__pre_init(struct adapter *);
815 static int get_params__post_init(struct adapter *);
816 static int set_params__post_init(struct adapter *);
817 static void t4_set_desc(struct adapter *);
818 static bool fixed_ifmedia(struct port_info *);
819 static void build_medialist(struct port_info *);
820 static void init_link_config(struct port_info *);
821 static int fixup_link_config(struct port_info *);
822 static int apply_link_config(struct port_info *);
823 static int cxgbe_init_synchronized(struct vi_info *);
824 static int cxgbe_uninit_synchronized(struct vi_info *);
825 static int adapter_full_init(struct adapter *);
826 static void adapter_full_uninit(struct adapter *);
827 static int vi_full_init(struct vi_info *);
828 static void vi_full_uninit(struct vi_info *);
829 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *);
830 static void quiesce_txq(struct sge_txq *);
831 static void quiesce_wrq(struct sge_wrq *);
832 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
833 static void quiesce_vi(struct vi_info *);
834 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
835     driver_intr_t *, void *, char *);
836 static int t4_free_irq(struct adapter *, struct irq *);
837 static void t4_init_atid_table(struct adapter *);
838 static void t4_free_atid_table(struct adapter *);
839 static void stop_atid_allocator(struct adapter *);
840 static void restart_atid_allocator(struct adapter *);
841 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
842 static void vi_refresh_stats(struct vi_info *);
843 static void cxgbe_refresh_stats(struct vi_info *);
844 static void cxgbe_tick(void *);
845 static void vi_tick(void *);
846 static void cxgbe_sysctls(struct port_info *);
847 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
848 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
849 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
850 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
851 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
852 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS);
853 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
854 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
855 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
856 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
857 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
858 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS);
859 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS);
860 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
861 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
862 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS);
863 static int sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS);
864 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
865 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
866 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
867 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
868 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
869 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
870 static int sysctl_cim_ibq(SYSCTL_HANDLER_ARGS);
871 static int sysctl_cim_obq(SYSCTL_HANDLER_ARGS);
872 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
873 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
874 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
875 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
876 static int sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS);
877 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
878 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
879 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS);
880 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
881 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
882 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
883 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
884 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
885 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
886 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
887 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
888 static int sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS);
889 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
890 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
891 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
892 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
893 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
894 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
895 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS);
896 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
897 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
898 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
899 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
900 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
901 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
902 static int sysctl_reset(SYSCTL_HANDLER_ARGS);
903 static int sysctl_tcb_cache(SYSCTL_HANDLER_ARGS);
904 #ifdef TCP_OFFLOAD
905 static int sysctl_tls(SYSCTL_HANDLER_ARGS);
906 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
907 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
908 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
909 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
910 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
911 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
912 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
913 #endif
914 static int get_sge_context(struct adapter *, int, uint32_t, int, uint32_t *);
915 static int load_fw(struct adapter *, struct t4_data *);
916 static int load_cfg(struct adapter *, struct t4_data *);
917 static int load_boot(struct adapter *, struct t4_bootrom *);
918 static int load_bootcfg(struct adapter *, struct t4_data *);
919 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
920 static void free_offload_policy(struct t4_offload_policy *);
921 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
922 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
923 static int read_i2c(struct adapter *, struct t4_i2c_data *);
924 static int clear_stats(struct adapter *, u_int);
925 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *);
926 static int release_clip_addr(struct adapter *, struct t4_clip_addr *);
927 static inline int stop_adapter(struct adapter *);
928 static inline void set_adapter_hwstatus(struct adapter *, const bool);
929 static int stop_lld(struct adapter *);
930 static inline int restart_adapter(struct adapter *);
931 static int restart_lld(struct adapter *);
932 #ifdef TCP_OFFLOAD
933 static int deactivate_all_uld(struct adapter *);
934 static void stop_all_uld(struct adapter *);
935 static void restart_all_uld(struct adapter *);
936 #endif
937 #ifdef KERN_TLS
938 static int ktls_capability(struct adapter *, bool);
939 #endif
940 static int mod_event(module_t, int, void *);
941 static int notify_siblings(device_t, int);
942 static uint64_t vi_get_counter(if_t, ift_counter);
943 static uint64_t cxgbe_get_counter(if_t, ift_counter);
944 static void enable_vxlan_rx(struct adapter *);
945 static void reset_adapter_task(void *, int);
946 static void fatal_error_task(void *, int);
947 static void dump_devlog(struct adapter *);
948 static void dump_cim_regs(struct adapter *);
949 static void dump_cimla(struct adapter *);
950 
951 struct {
952 	uint16_t device;
953 	char *desc;
954 } t4_pciids[] = {
955 	{0xa000, "Chelsio Terminator 4 FPGA"},
956 	{0x4400, "Chelsio T440-dbg"},
957 	{0x4401, "Chelsio T420-CR"},
958 	{0x4402, "Chelsio T422-CR"},
959 	{0x4403, "Chelsio T440-CR"},
960 	{0x4404, "Chelsio T420-BCH"},
961 	{0x4405, "Chelsio T440-BCH"},
962 	{0x4406, "Chelsio T440-CH"},
963 	{0x4407, "Chelsio T420-SO"},
964 	{0x4408, "Chelsio T420-CX"},
965 	{0x4409, "Chelsio T420-BT"},
966 	{0x440a, "Chelsio T404-BT"},
967 	{0x440e, "Chelsio T440-LP-CR"},
968 }, t5_pciids[] = {
969 	{0xb000, "Chelsio Terminator 5 FPGA"},
970 	{0x5400, "Chelsio T580-dbg"},
971 	{0x5401,  "Chelsio T520-CR"},		/* 2 x 10G */
972 	{0x5402,  "Chelsio T522-CR"},		/* 2 x 10G, 2 X 1G */
973 	{0x5403,  "Chelsio T540-CR"},		/* 4 x 10G */
974 	{0x5407,  "Chelsio T520-SO"},		/* 2 x 10G, nomem */
975 	{0x5409,  "Chelsio T520-BT"},		/* 2 x 10GBaseT */
976 	{0x540a,  "Chelsio T504-BT"},		/* 4 x 1G */
977 	{0x540d,  "Chelsio T580-CR"},		/* 2 x 40G */
978 	{0x540e,  "Chelsio T540-LP-CR"},	/* 4 x 10G */
979 	{0x5410,  "Chelsio T580-LP-CR"},	/* 2 x 40G */
980 	{0x5411,  "Chelsio T520-LL-CR"},	/* 2 x 10G */
981 	{0x5412,  "Chelsio T560-CR"},		/* 1 x 40G, 2 x 10G */
982 	{0x5414,  "Chelsio T580-LP-SO-CR"},	/* 2 x 40G, nomem */
983 	{0x5415,  "Chelsio T502-BT"},		/* 2 x 1G */
984 	{0x5418,  "Chelsio T540-BT"},		/* 4 x 10GBaseT */
985 	{0x5419,  "Chelsio T540-LP-BT"},	/* 4 x 10GBaseT */
986 	{0x541a,  "Chelsio T540-SO-BT"},	/* 4 x 10GBaseT, nomem */
987 	{0x541b,  "Chelsio T540-SO-CR"},	/* 4 x 10G, nomem */
988 
989 	/* Custom */
990 	{0x5483, "Custom T540-CR"},
991 	{0x5484, "Custom T540-BT"},
992 }, t6_pciids[] = {
993 	{0xc006, "Chelsio Terminator 6 FPGA"},	/* T6 PE10K6 FPGA (PF0) */
994 	{0x6400, "Chelsio T6-DBG-25"},		/* 2 x 10/25G, debug */
995 	{0x6401, "Chelsio T6225-CR"},		/* 2 x 10/25G */
996 	{0x6402, "Chelsio T6225-SO-CR"},	/* 2 x 10/25G, nomem */
997 	{0x6403, "Chelsio T6425-CR"},		/* 4 x 10/25G */
998 	{0x6404, "Chelsio T6425-SO-CR"},	/* 4 x 10/25G, nomem */
999 	{0x6405, "Chelsio T6225-SO-OCP3"},	/* 2 x 10/25G, nomem */
1000 	{0x6406, "Chelsio T6225-OCP3"},		/* 2 x 10/25G */
1001 	{0x6407, "Chelsio T62100-LP-CR"},	/* 2 x 40/50/100G */
1002 	{0x6408, "Chelsio T62100-SO-CR"},	/* 2 x 40/50/100G, nomem */
1003 	{0x6409, "Chelsio T6210-BT"},		/* 2 x 10GBASE-T */
1004 	{0x640d, "Chelsio T62100-CR"},		/* 2 x 40/50/100G */
1005 	{0x6410, "Chelsio T6-DBG-100"},		/* 2 x 40/50/100G, debug */
1006 	{0x6411, "Chelsio T6225-LL-CR"},	/* 2 x 10/25G */
1007 	{0x6414, "Chelsio T62100-SO-OCP3"},	/* 2 x 40/50/100G, nomem */
1008 	{0x6415, "Chelsio T6201-BT"},		/* 2 x 1000BASE-T */
1009 
1010 	/* Custom */
1011 	{0x6480, "Custom T6225-CR"},
1012 	{0x6481, "Custom T62100-CR"},
1013 	{0x6482, "Custom T6225-CR"},
1014 	{0x6483, "Custom T62100-CR"},
1015 	{0x6484, "Custom T64100-CR"},
1016 	{0x6485, "Custom T6240-SO"},
1017 	{0x6486, "Custom T6225-SO-CR"},
1018 	{0x6487, "Custom T6225-CR"},
1019 }, t7_pciids[] = {
1020 	{0xd000, "Chelsio Terminator 7 FPGA"},	/* T7 PE12K FPGA */
1021 	{0x7400, "Chelsio T72200-DBG"},		/* 2 x 200G, debug */
1022 	{0x7401, "Chelsio T7250"},		/* 2 x 10/25/50G, 1 mem */
1023 	{0x7402, "Chelsio S7250"},		/* 2 x 10/25/50G, nomem */
1024 	{0x7403, "Chelsio T7450"},		/* 4 x 10/25/50G, 1 mem */
1025 	{0x7404, "Chelsio S7450"},		/* 4 x 10/25/50G, nomem */
1026 	{0x7405, "Chelsio T72200"},		/* 2 x 40/100/200G, 1 mem */
1027 	{0x7406, "Chelsio S72200"},		/* 2 x 40/100/200G, nomem */
1028 	{0x7407, "Chelsio T72200-FH"},		/* 2 x 40/100/200G, 2 mem */
1029 	{0x7408, "Chelsio S71400"},		/* 1 x 400G, nomem */
1030 	{0x7409, "Chelsio S7210-BT"},		/* 2 x 10GBASE-T, nomem */
1031 	{0x740a, "Chelsio T7450-RC"},		/* 4 x 10/25/50G, 1 mem, RC */
1032 	{0x740b, "Chelsio T72200-RC"},		/* 2 x 40/100/200G, 1 mem, RC */
1033 	{0x740c, "Chelsio T72200-FH-RC"},	/* 2 x 40/100/200G, 2 mem, RC */
1034 	{0x740d, "Chelsio S72200-OCP3"},	/* 2 x 40/100/200G OCP3 */
1035 	{0x740e, "Chelsio S7450-OCP3"},		/* 4 x 1/20/25/50G OCP3 */
1036 	{0x740f, "Chelsio S7410-BT-OCP3"},	/* 4 x 10GBASE-T OCP3 */
1037 	{0x7410, "Chelsio S7210-BT-A"},		/* 2 x 10GBASE-T */
1038 	{0x7411, "Chelsio T7_MAYRA_7"},		/* Motherboard */
1039 
1040 	/* Custom */
1041 	{0x7480, "Custom T7"},
1042 };
1043 
1044 #ifdef TCP_OFFLOAD
1045 /*
1046  * service_iq_fl() has an iq and needs the fl.  Offset of fl from the iq should
1047  * be exactly the same for both rxq and ofld_rxq.
1048  */
1049 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
1050 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
1051 #endif
1052 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
1053 
1054 static int
1055 t4_probe(device_t dev)
1056 {
1057 	int i;
1058 	uint16_t v = pci_get_vendor(dev);
1059 	uint16_t d = pci_get_device(dev);
1060 	uint8_t f = pci_get_function(dev);
1061 
1062 	if (v != PCI_VENDOR_ID_CHELSIO)
1063 		return (ENXIO);
1064 
1065 	/* Attach only to PF0 of the FPGA */
1066 	if (d == 0xa000 && f != 0)
1067 		return (ENXIO);
1068 
1069 	for (i = 0; i < nitems(t4_pciids); i++) {
1070 		if (d == t4_pciids[i].device) {
1071 			device_set_desc(dev, t4_pciids[i].desc);
1072 			return (BUS_PROBE_DEFAULT);
1073 		}
1074 	}
1075 
1076 	return (ENXIO);
1077 }
1078 
1079 static int
1080 t5_probe(device_t dev)
1081 {
1082 	int i;
1083 	uint16_t v = pci_get_vendor(dev);
1084 	uint16_t d = pci_get_device(dev);
1085 	uint8_t f = pci_get_function(dev);
1086 
1087 	if (v != PCI_VENDOR_ID_CHELSIO)
1088 		return (ENXIO);
1089 
1090 	/* Attach only to PF0 of the FPGA */
1091 	if (d == 0xb000 && f != 0)
1092 		return (ENXIO);
1093 
1094 	for (i = 0; i < nitems(t5_pciids); i++) {
1095 		if (d == t5_pciids[i].device) {
1096 			device_set_desc(dev, t5_pciids[i].desc);
1097 			return (BUS_PROBE_DEFAULT);
1098 		}
1099 	}
1100 
1101 	return (ENXIO);
1102 }
1103 
1104 static int
1105 t6_probe(device_t dev)
1106 {
1107 	int i;
1108 	uint16_t v = pci_get_vendor(dev);
1109 	uint16_t d = pci_get_device(dev);
1110 
1111 	if (v != PCI_VENDOR_ID_CHELSIO)
1112 		return (ENXIO);
1113 
1114 	for (i = 0; i < nitems(t6_pciids); i++) {
1115 		if (d == t6_pciids[i].device) {
1116 			device_set_desc(dev, t6_pciids[i].desc);
1117 			return (BUS_PROBE_DEFAULT);
1118 		}
1119 	}
1120 
1121 	return (ENXIO);
1122 }
1123 
1124 static int
1125 ch_probe(device_t dev)
1126 {
1127 	int i;
1128 	uint16_t v = pci_get_vendor(dev);
1129 	uint16_t d = pci_get_device(dev);
1130 	uint8_t f = pci_get_function(dev);
1131 
1132 	if (v != PCI_VENDOR_ID_CHELSIO)
1133 		return (ENXIO);
1134 
1135 	/* Attach only to PF0 of the FPGA */
1136 	if (d == 0xd000 && f != 0)
1137 		return (ENXIO);
1138 
1139 	for (i = 0; i < nitems(t7_pciids); i++) {
1140 		if (d == t7_pciids[i].device) {
1141 			device_set_desc(dev, t7_pciids[i].desc);
1142 			return (BUS_PROBE_DEFAULT);
1143 		}
1144 	}
1145 
1146 	return (ENXIO);
1147 }
1148 
1149 static void
1150 t5_attribute_workaround(device_t dev)
1151 {
1152 	device_t root_port;
1153 	uint32_t v;
1154 
1155 	/*
1156 	 * The T5 chips do not properly echo the No Snoop and Relaxed
1157 	 * Ordering attributes when replying to a TLP from a Root
1158 	 * Port.  As a workaround, find the parent Root Port and
1159 	 * disable No Snoop and Relaxed Ordering.  Note that this
1160 	 * affects all devices under this root port.
1161 	 */
1162 	root_port = pci_find_pcie_root_port(dev);
1163 	if (root_port == NULL) {
1164 		device_printf(dev, "Unable to find parent root port\n");
1165 		return;
1166 	}
1167 
1168 	v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
1169 	    PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
1170 	if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
1171 	    0)
1172 		device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
1173 		    device_get_nameunit(root_port));
1174 }
1175 
1176 static const struct devnames devnames[] = {
1177 	{
1178 		.nexus_name = "t4nex",
1179 		.ifnet_name = "cxgbe",
1180 		.vi_ifnet_name = "vcxgbe",
1181 		.pf03_drv_name = "t4iov",
1182 		.vf_nexus_name = "t4vf",
1183 		.vf_ifnet_name = "cxgbev"
1184 	}, {
1185 		.nexus_name = "t5nex",
1186 		.ifnet_name = "cxl",
1187 		.vi_ifnet_name = "vcxl",
1188 		.pf03_drv_name = "t5iov",
1189 		.vf_nexus_name = "t5vf",
1190 		.vf_ifnet_name = "cxlv"
1191 	}, {
1192 		.nexus_name = "t6nex",
1193 		.ifnet_name = "cc",
1194 		.vi_ifnet_name = "vcc",
1195 		.pf03_drv_name = "t6iov",
1196 		.vf_nexus_name = "t6vf",
1197 		.vf_ifnet_name = "ccv"
1198 	}, {
1199 		.nexus_name = "chnex",
1200 		.ifnet_name = "che",
1201 		.vi_ifnet_name = "vche",
1202 		.pf03_drv_name = "chiov",
1203 		.vf_nexus_name = "chvf",
1204 		.vf_ifnet_name = "chev"
1205 	}
1206 };
1207 
1208 void
1209 t4_init_devnames(struct adapter *sc)
1210 {
1211 	int id;
1212 
1213 	id = chip_id(sc);
1214 	if (id < CHELSIO_T4) {
1215 		device_printf(sc->dev, "chip id %d is not supported.\n", id);
1216 		sc->names = NULL;
1217 	} else if (id - CHELSIO_T4 < nitems(devnames))
1218 		sc->names = &devnames[id - CHELSIO_T4];
1219 	else
1220 		sc->names = &devnames[nitems(devnames) - 1];
1221 }
1222 
1223 static int
1224 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
1225 {
1226 	const char *parent, *name;
1227 	long value;
1228 	int line, unit;
1229 
1230 	line = 0;
1231 	parent = device_get_nameunit(sc->dev);
1232 	name = sc->names->ifnet_name;
1233 	while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
1234 		if (resource_long_value(name, unit, "port", &value) == 0 &&
1235 		    value == pi->port_id)
1236 			return (unit);
1237 	}
1238 	return (-1);
1239 }
1240 
1241 static void
1242 t4_calibration(void *arg)
1243 {
1244 	struct adapter *sc;
1245 	struct clock_sync *cur, *nex;
1246 	uint64_t hw;
1247 	sbintime_t sbt;
1248 	int next_up;
1249 
1250 	sc = (struct adapter *)arg;
1251 
1252 	KASSERT(!hw_off_limits(sc), ("hw_off_limits at t4_calibration"));
1253 	hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO);
1254 	sbt = sbinuptime();
1255 
1256 	cur = &sc->cal_info[sc->cal_current];
1257 	next_up = (sc->cal_current + 1) % CNT_CAL_INFO;
1258 	nex = &sc->cal_info[next_up];
1259 	if (__predict_false(sc->cal_count == 0)) {
1260 		/* First time in, just get the values in */
1261 		cur->hw_cur = hw;
1262 		cur->sbt_cur = sbt;
1263 		sc->cal_count++;
1264 		goto done;
1265 	}
1266 
1267 	if (cur->hw_cur == hw) {
1268 		/* The clock is not advancing? */
1269 		sc->cal_count = 0;
1270 		atomic_store_rel_int(&cur->gen, 0);
1271 		goto done;
1272 	}
1273 
1274 	seqc_write_begin(&nex->gen);
1275 	nex->hw_prev = cur->hw_cur;
1276 	nex->sbt_prev = cur->sbt_cur;
1277 	nex->hw_cur = hw;
1278 	nex->sbt_cur = sbt;
1279 	seqc_write_end(&nex->gen);
1280 	sc->cal_current = next_up;
1281 done:
1282 	callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration,
1283 	    sc, C_DIRECT_EXEC);
1284 }
1285 
1286 static void
1287 t4_calibration_start(struct adapter *sc)
1288 {
1289 	/*
1290 	 * Here if we have not done a calibration
1291 	 * then do so otherwise start the appropriate
1292 	 * timer.
1293 	 */
1294 	int i;
1295 
1296 	for (i = 0; i < CNT_CAL_INFO; i++) {
1297 		sc->cal_info[i].gen = 0;
1298 	}
1299 	sc->cal_current = 0;
1300 	sc->cal_count = 0;
1301 	sc->cal_gen = 0;
1302 	t4_calibration(sc);
1303 }
1304 
1305 static int
1306 t4_attach(device_t dev)
1307 {
1308 	struct adapter *sc;
1309 	int rc = 0, i, j, rqidx, tqidx, nports;
1310 	struct make_dev_args mda;
1311 	struct intrs_and_queues iaq;
1312 	struct sge *s;
1313 	uint32_t *buf;
1314 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1315 	int ofld_tqidx;
1316 #endif
1317 #ifdef TCP_OFFLOAD
1318 	int ofld_rqidx;
1319 #endif
1320 #ifdef DEV_NETMAP
1321 	int nm_rqidx, nm_tqidx;
1322 #endif
1323 	int num_vis;
1324 
1325 	sc = device_get_softc(dev);
1326 	sc->dev = dev;
1327 	sysctl_ctx_init(&sc->ctx);
1328 	TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1329 	if (TUNABLE_INT_FETCH("hw.cxgbe.iflags", &sc->intr_flags) == 0)
1330 		sc->intr_flags = IHF_INTR_CLEAR_ON_INIT | IHF_CLR_ALL_UNIGNORED;
1331 
1332 	if ((pci_get_device(dev) & 0xff00) == 0x5400)
1333 		t5_attribute_workaround(dev);
1334 	pci_enable_busmaster(dev);
1335 	if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1336 		uint32_t v;
1337 
1338 		pci_set_max_read_req(dev, 4096);
1339 		v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1340 		sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1341 		if (pcie_relaxed_ordering == 0 &&
1342 		    (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1343 			v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1344 			pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1345 		} else if (pcie_relaxed_ordering == 1 &&
1346 		    (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1347 			v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1348 			pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1349 		}
1350 	}
1351 
1352 	sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1353 	sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1354 	sc->traceq = -1;
1355 	mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1356 	snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1357 	    device_get_nameunit(dev));
1358 
1359 	snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1360 	    device_get_nameunit(dev));
1361 	mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1362 	t4_add_adapter(sc);
1363 
1364 	mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1365 	TAILQ_INIT(&sc->sfl);
1366 	callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1367 
1368 	mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1369 
1370 	sc->policy = NULL;
1371 	rw_init(&sc->policy_lock, "connection offload policy");
1372 
1373 	callout_init(&sc->ktls_tick, 1);
1374 
1375 	callout_init(&sc->cal_callout, 1);
1376 
1377 	refcount_init(&sc->vxlan_refcount, 0);
1378 
1379 	TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc);
1380 	TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc);
1381 
1382 	sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1383 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq",
1384 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1385 	sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1386 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq",
1387 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
1388 
1389 	rc = t4_map_bars_0_and_4(sc);
1390 	if (rc != 0)
1391 		goto done; /* error message displayed already */
1392 
1393 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1394 	memset(sc->port_map, 0xff, sizeof(sc->port_map));
1395 
1396 	/* Prepare the adapter for operation. */
1397 	buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1398 	rc = -t4_prep_adapter(sc, buf);
1399 	free(buf, M_CXGBE);
1400 	if (rc != 0) {
1401 		device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1402 		goto done;
1403 	}
1404 
1405 	/*
1406 	 * This is the real PF# to which we're attaching.  Works from within PCI
1407 	 * passthrough environments too, where pci_get_function() could return a
1408 	 * different PF# depending on the passthrough configuration.  We need to
1409 	 * use the real PF# in all our communication with the firmware.
1410 	 */
1411 	j = t4_read_reg(sc, A_PL_WHOAMI);
1412 	sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1413 	sc->mbox = sc->pf;
1414 
1415 	t4_init_devnames(sc);
1416 	if (sc->names == NULL) {
1417 		rc = ENOTSUP;
1418 		goto done; /* error message displayed already */
1419 	}
1420 
1421 	/*
1422 	 * Do this really early, with the memory windows set up even before the
1423 	 * character device.  The userland tool's register i/o and mem read
1424 	 * will work even in "recovery mode".
1425 	 */
1426 	setup_memwin(sc);
1427 	if (t4_init_devlog_ncores_params(sc, 0) == 0)
1428 		fixup_devlog_ncores_params(sc);
1429 	make_dev_args_init(&mda);
1430 	mda.mda_devsw = &t4_cdevsw;
1431 	mda.mda_uid = UID_ROOT;
1432 	mda.mda_gid = GID_WHEEL;
1433 	mda.mda_mode = 0600;
1434 	mda.mda_si_drv1 = sc;
1435 	rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1436 	if (rc != 0)
1437 		device_printf(dev, "failed to create nexus char device: %d.\n",
1438 		    rc);
1439 
1440 	/* Go no further if recovery mode has been requested. */
1441 	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1442 		device_printf(dev, "recovery mode.\n");
1443 		goto done;
1444 	}
1445 
1446 #if defined(__i386__)
1447 	if ((cpu_feature & CPUID_CX8) == 0) {
1448 		device_printf(dev, "64 bit atomics not available.\n");
1449 		rc = ENOTSUP;
1450 		goto done;
1451 	}
1452 #endif
1453 
1454 	/* Contact the firmware and try to become the master driver. */
1455 	rc = contact_firmware(sc);
1456 	if (rc != 0)
1457 		goto done; /* error message displayed already */
1458 	MPASS(sc->flags & FW_OK);
1459 
1460 	rc = get_params__pre_init(sc);
1461 	if (rc != 0)
1462 		goto done; /* error message displayed already */
1463 
1464 	if (sc->flags & MASTER_PF) {
1465 		rc = partition_resources(sc);
1466 		if (rc != 0)
1467 			goto done; /* error message displayed already */
1468 	}
1469 
1470 	rc = get_params__post_init(sc);
1471 	if (rc != 0)
1472 		goto done; /* error message displayed already */
1473 
1474 	rc = set_params__post_init(sc);
1475 	if (rc != 0)
1476 		goto done; /* error message displayed already */
1477 
1478 	rc = t4_map_bar_2(sc);
1479 	if (rc != 0)
1480 		goto done; /* error message displayed already */
1481 
1482 	rc = t4_adj_doorbells(sc);
1483 	if (rc != 0)
1484 		goto done; /* error message displayed already */
1485 
1486 	rc = t4_create_dma_tag(sc);
1487 	if (rc != 0)
1488 		goto done; /* error message displayed already */
1489 
1490 	/*
1491 	 * First pass over all the ports - allocate VIs and initialize some
1492 	 * basic parameters like mac address, port type, etc.
1493 	 */
1494 	for_each_port(sc, i) {
1495 		struct port_info *pi;
1496 
1497 		pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1498 		sc->port[i] = pi;
1499 
1500 		/* These must be set before t4_port_init */
1501 		pi->adapter = sc;
1502 		pi->port_id = i;
1503 		/*
1504 		 * XXX: vi[0] is special so we can't delay this allocation until
1505 		 * pi->nvi's final value is known.
1506 		 */
1507 		pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1508 		    M_ZERO | M_WAITOK);
1509 
1510 		/*
1511 		 * Allocate the "main" VI and initialize parameters
1512 		 * like mac addr.
1513 		 */
1514 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1515 		if (rc != 0) {
1516 			device_printf(dev, "unable to initialize port %d: %d\n",
1517 			    i, rc);
1518 			free(pi->vi, M_CXGBE);
1519 			free(pi, M_CXGBE);
1520 			sc->port[i] = NULL;
1521 			goto done;
1522 		}
1523 
1524 		if (is_bt(pi->port_type))
1525 			setbit(&sc->bt_map, pi->hw_port);
1526 		else
1527 			MPASS(!isset(&sc->bt_map, pi->hw_port));
1528 
1529 		snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1530 		    device_get_nameunit(dev), i);
1531 		mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1532 		for (j = 0; j < sc->params.tp.lb_nchan; j++)
1533 			sc->chan_map[pi->tx_chan + j] = i;
1534 		sc->port_map[pi->hw_port] = i;
1535 
1536 		/*
1537 		 * The MPS counter for FCS errors doesn't work correctly on the
1538 		 * T6 so we use the MAC counter here.  Which MAC is in use
1539 		 * depends on the link settings which will be known when the
1540 		 * link comes up.
1541 		 */
1542 		if (is_t6(sc))
1543 			pi->fcs_reg = -1;
1544 		else
1545 			pi->fcs_reg = A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L;
1546 		pi->fcs_base = 0;
1547 
1548 		/* All VIs on this port share this media. */
1549 		ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1550 		    cxgbe_media_status);
1551 
1552 		PORT_LOCK(pi);
1553 		init_link_config(pi);
1554 		fixup_link_config(pi);
1555 		build_medialist(pi);
1556 		if (fixed_ifmedia(pi))
1557 			pi->flags |= FIXED_IFMEDIA;
1558 		PORT_UNLOCK(pi);
1559 
1560 		pi->dev = device_add_child(dev, sc->names->ifnet_name,
1561 		    t4_ifnet_unit(sc, pi));
1562 		if (pi->dev == NULL) {
1563 			device_printf(dev,
1564 			    "failed to add device for port %d.\n", i);
1565 			rc = ENXIO;
1566 			goto done;
1567 		}
1568 		pi->vi[0].dev = pi->dev;
1569 		device_set_softc(pi->dev, pi);
1570 	}
1571 
1572 	/*
1573 	 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1574 	 */
1575 	nports = sc->params.nports;
1576 	rc = cfg_itype_and_nqueues(sc, &iaq);
1577 	if (rc != 0)
1578 		goto done; /* error message displayed already */
1579 
1580 	num_vis = iaq.num_vis;
1581 	sc->intr_type = iaq.intr_type;
1582 	sc->intr_count = iaq.nirq;
1583 
1584 	s = &sc->sge;
1585 	s->nctrlq = max(sc->params.nports, sc->params.ncores);
1586 	s->nrxq = nports * iaq.nrxq;
1587 	s->ntxq = nports * iaq.ntxq;
1588 	if (num_vis > 1) {
1589 		s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1590 		s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1591 	}
1592 	s->neq = s->ntxq + s->nrxq;	/* the free list in an rxq is an eq */
1593 	s->neq += nports;		/* ctrl queues: 1 per port */
1594 	s->niq = s->nrxq + 1;		/* 1 extra for firmware event queue */
1595 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1596 	if (is_offload(sc) || is_ethoffload(sc)) {
1597 		s->nofldtxq = nports * iaq.nofldtxq;
1598 		if (num_vis > 1)
1599 			s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1600 		s->neq += s->nofldtxq;
1601 
1602 		s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq),
1603 		    M_CXGBE, M_ZERO | M_WAITOK);
1604 	}
1605 #endif
1606 #ifdef TCP_OFFLOAD
1607 	if (is_offload(sc)) {
1608 		s->nofldrxq = nports * iaq.nofldrxq;
1609 		if (num_vis > 1)
1610 			s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1611 		s->neq += s->nofldrxq;	/* free list */
1612 		s->niq += s->nofldrxq;
1613 
1614 		s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1615 		    M_CXGBE, M_ZERO | M_WAITOK);
1616 	}
1617 #endif
1618 #ifdef DEV_NETMAP
1619 	s->nnmrxq = 0;
1620 	s->nnmtxq = 0;
1621 	if (t4_native_netmap & NN_MAIN_VI) {
1622 		s->nnmrxq += nports * iaq.nnmrxq;
1623 		s->nnmtxq += nports * iaq.nnmtxq;
1624 	}
1625 	if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1626 		s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1627 		s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1628 	}
1629 	s->neq += s->nnmtxq + s->nnmrxq;
1630 	s->niq += s->nnmrxq;
1631 
1632 	s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1633 	    M_CXGBE, M_ZERO | M_WAITOK);
1634 	s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1635 	    M_CXGBE, M_ZERO | M_WAITOK);
1636 #endif
1637 	MPASS(s->niq <= s->iqmap_sz);
1638 	MPASS(s->neq <= s->eqmap_sz);
1639 
1640 	s->ctrlq = malloc(s->nctrlq * sizeof(struct sge_wrq), M_CXGBE,
1641 	    M_ZERO | M_WAITOK);
1642 	s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1643 	    M_ZERO | M_WAITOK);
1644 	s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1645 	    M_ZERO | M_WAITOK);
1646 	s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
1647 	    M_ZERO | M_WAITOK);
1648 	s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
1649 	    M_ZERO | M_WAITOK);
1650 
1651 	sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1652 	    M_ZERO | M_WAITOK);
1653 
1654 	t4_init_l2t(sc, M_WAITOK);
1655 	t4_init_smt(sc, M_WAITOK);
1656 	t4_init_tx_sched(sc);
1657 	t4_init_atid_table(sc);
1658 #ifdef RATELIMIT
1659 	t4_init_etid_table(sc);
1660 #endif
1661 #ifdef INET6
1662 	t4_init_clip_table(sc);
1663 #endif
1664 	if (sc->vres.key.size != 0)
1665 		sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1666 		    sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1667 	t4_init_tpt(sc);
1668 
1669 	/*
1670 	 * Second pass over the ports.  This time we know the number of rx and
1671 	 * tx queues that each port should get.
1672 	 */
1673 	rqidx = tqidx = 0;
1674 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1675 	ofld_tqidx = 0;
1676 #endif
1677 #ifdef TCP_OFFLOAD
1678 	ofld_rqidx = 0;
1679 #endif
1680 #ifdef DEV_NETMAP
1681 	nm_rqidx = nm_tqidx = 0;
1682 #endif
1683 	for_each_port(sc, i) {
1684 		struct port_info *pi = sc->port[i];
1685 		struct vi_info *vi;
1686 
1687 		if (pi == NULL)
1688 			continue;
1689 
1690 		pi->nvi = num_vis;
1691 		for_each_vi(pi, j, vi) {
1692 			vi->pi = pi;
1693 			vi->adapter = sc;
1694 			vi->first_intr = -1;
1695 			vi->qsize_rxq = t4_qsize_rxq;
1696 			vi->qsize_txq = t4_qsize_txq;
1697 
1698 			vi->first_rxq = rqidx;
1699 			vi->first_txq = tqidx;
1700 			vi->tmr_idx = t4_tmr_idx;
1701 			vi->pktc_idx = t4_pktc_idx;
1702 			vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1703 			vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1704 
1705 			rqidx += vi->nrxq;
1706 			tqidx += vi->ntxq;
1707 
1708 			if (j == 0 && vi->ntxq > 1)
1709 				vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1710 			else
1711 				vi->rsrv_noflowq = 0;
1712 
1713 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1714 			vi->first_ofld_txq = ofld_tqidx;
1715 			vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1716 			ofld_tqidx += vi->nofldtxq;
1717 #endif
1718 #ifdef TCP_OFFLOAD
1719 			vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1720 			vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1721 			vi->first_ofld_rxq = ofld_rqidx;
1722 			vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1723 
1724 			ofld_rqidx += vi->nofldrxq;
1725 #endif
1726 #ifdef DEV_NETMAP
1727 			vi->first_nm_rxq = nm_rqidx;
1728 			vi->first_nm_txq = nm_tqidx;
1729 			if (j == 0) {
1730 				vi->nnmrxq = iaq.nnmrxq;
1731 				vi->nnmtxq = iaq.nnmtxq;
1732 			} else {
1733 				vi->nnmrxq = iaq.nnmrxq_vi;
1734 				vi->nnmtxq = iaq.nnmtxq_vi;
1735 			}
1736 			nm_rqidx += vi->nnmrxq;
1737 			nm_tqidx += vi->nnmtxq;
1738 #endif
1739 		}
1740 	}
1741 
1742 	rc = t4_setup_intr_handlers(sc);
1743 	if (rc != 0) {
1744 		device_printf(dev,
1745 		    "failed to setup interrupt handlers: %d\n", rc);
1746 		goto done;
1747 	}
1748 
1749 	bus_identify_children(dev);
1750 
1751 	/*
1752 	 * Ensure thread-safe mailbox access (in debug builds).
1753 	 *
1754 	 * So far this was the only thread accessing the mailbox but various
1755 	 * ifnets and sysctls are about to be created and their handlers/ioctls
1756 	 * will access the mailbox from different threads.
1757 	 */
1758 	sc->flags |= CHK_MBOX_ACCESS;
1759 
1760 	bus_attach_children(dev);
1761 	t4_calibration_start(sc);
1762 
1763 	device_printf(dev,
1764 	    "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1765 	    sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1766 	    sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1767 	    (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1768 	    sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1769 
1770 	t4_set_desc(sc);
1771 
1772 	notify_siblings(dev, 0);
1773 
1774 done:
1775 	if (rc != 0 && sc->cdev) {
1776 		/* cdev was created and so cxgbetool works; recover that way. */
1777 		device_printf(dev,
1778 		    "error during attach, adapter is now in recovery mode.\n");
1779 		rc = 0;
1780 	}
1781 
1782 	if (rc != 0)
1783 		t4_detach_common(dev);
1784 	else
1785 		t4_sysctls(sc);
1786 
1787 	return (rc);
1788 }
1789 
1790 static int
1791 t4_child_location(device_t bus, device_t dev, struct sbuf *sb)
1792 {
1793 	struct adapter *sc;
1794 	struct port_info *pi;
1795 	int i;
1796 
1797 	sc = device_get_softc(bus);
1798 	for_each_port(sc, i) {
1799 		pi = sc->port[i];
1800 		if (pi != NULL && pi->dev == dev) {
1801 			sbuf_printf(sb, "port=%d", pi->port_id);
1802 			break;
1803 		}
1804 	}
1805 	return (0);
1806 }
1807 
1808 static int
1809 t4_ready(device_t dev)
1810 {
1811 	struct adapter *sc;
1812 
1813 	sc = device_get_softc(dev);
1814 	if (sc->flags & FW_OK)
1815 		return (0);
1816 	return (ENXIO);
1817 }
1818 
1819 static int
1820 t4_read_port_device(device_t dev, int port, device_t *child)
1821 {
1822 	struct adapter *sc;
1823 	struct port_info *pi;
1824 
1825 	sc = device_get_softc(dev);
1826 	if (port < 0 || port >= MAX_NPORTS)
1827 		return (EINVAL);
1828 	pi = sc->port[port];
1829 	if (pi == NULL || pi->dev == NULL)
1830 		return (ENXIO);
1831 	*child = pi->dev;
1832 	return (0);
1833 }
1834 
1835 static int
1836 notify_siblings(device_t dev, int detaching)
1837 {
1838 	device_t sibling;
1839 	int error, i;
1840 
1841 	error = 0;
1842 	for (i = 0; i < PCI_FUNCMAX; i++) {
1843 		if (i == pci_get_function(dev))
1844 			continue;
1845 		sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1846 		    pci_get_slot(dev), i);
1847 		if (sibling == NULL || !device_is_attached(sibling))
1848 			continue;
1849 		if (detaching)
1850 			error = T4_DETACH_CHILD(sibling);
1851 		else
1852 			(void)T4_ATTACH_CHILD(sibling);
1853 		if (error)
1854 			break;
1855 	}
1856 	return (error);
1857 }
1858 
1859 /*
1860  * Idempotent
1861  */
1862 static int
1863 t4_detach(device_t dev)
1864 {
1865 	int rc;
1866 
1867 	rc = notify_siblings(dev, 1);
1868 	if (rc) {
1869 		device_printf(dev,
1870 		    "failed to detach sibling devices: %d\n", rc);
1871 		return (rc);
1872 	}
1873 
1874 	return (t4_detach_common(dev));
1875 }
1876 
1877 int
1878 t4_detach_common(device_t dev)
1879 {
1880 	struct adapter *sc;
1881 	struct port_info *pi;
1882 	int i, rc;
1883 
1884 	sc = device_get_softc(dev);
1885 
1886 #ifdef TCP_OFFLOAD
1887 	rc = deactivate_all_uld(sc);
1888 	if (rc) {
1889 		device_printf(dev,
1890 		    "failed to detach upper layer drivers: %d\n", rc);
1891 		return (rc);
1892 	}
1893 #endif
1894 
1895 	if (sc->cdev) {
1896 		destroy_dev(sc->cdev);
1897 		sc->cdev = NULL;
1898 	}
1899 
1900 	sx_xlock(&t4_list_lock);
1901 	SLIST_REMOVE(&t4_list, sc, adapter, link);
1902 	sx_xunlock(&t4_list_lock);
1903 
1904 	sc->flags &= ~CHK_MBOX_ACCESS;
1905 	if (sc->flags & FULL_INIT_DONE) {
1906 		if (!(sc->flags & IS_VF))
1907 			t4_intr_disable(sc);
1908 	}
1909 
1910 	if (device_is_attached(dev)) {
1911 		rc = bus_detach_children(dev);
1912 		if (rc) {
1913 			device_printf(dev,
1914 			    "failed to detach child devices: %d\n", rc);
1915 			return (rc);
1916 		}
1917 	}
1918 
1919 	for (i = 0; i < sc->intr_count; i++)
1920 		t4_free_irq(sc, &sc->irq[i]);
1921 
1922 	if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1923 		t4_free_tx_sched(sc);
1924 
1925 	for (i = 0; i < MAX_NPORTS; i++) {
1926 		pi = sc->port[i];
1927 		if (pi) {
1928 			t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1929 
1930 			mtx_destroy(&pi->pi_lock);
1931 			free(pi->vi, M_CXGBE);
1932 			free(pi, M_CXGBE);
1933 		}
1934 	}
1935 	callout_stop(&sc->cal_callout);
1936 	callout_drain(&sc->cal_callout);
1937 	device_delete_children(dev);
1938 	sysctl_ctx_free(&sc->ctx);
1939 	adapter_full_uninit(sc);
1940 
1941 	if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1942 		t4_fw_bye(sc, sc->mbox);
1943 
1944 	if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1945 		pci_release_msi(dev);
1946 
1947 	if (sc->regs_res)
1948 		bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1949 		    sc->regs_res);
1950 
1951 	if (sc->udbs_res)
1952 		bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1953 		    sc->udbs_res);
1954 
1955 	if (sc->msix_res)
1956 		bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1957 		    sc->msix_res);
1958 
1959 	if (sc->l2t)
1960 		t4_free_l2t(sc);
1961 	if (sc->smt)
1962 		t4_free_smt(sc->smt);
1963 	t4_free_atid_table(sc);
1964 #ifdef RATELIMIT
1965 	t4_free_etid_table(sc);
1966 #endif
1967 	if (sc->key_map)
1968 		vmem_destroy(sc->key_map);
1969 	t4_free_tpt(sc);
1970 #ifdef INET6
1971 	t4_destroy_clip_table(sc);
1972 #endif
1973 
1974 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1975 	free(sc->sge.ofld_txq, M_CXGBE);
1976 #endif
1977 #ifdef TCP_OFFLOAD
1978 	free(sc->sge.ofld_rxq, M_CXGBE);
1979 #endif
1980 #ifdef DEV_NETMAP
1981 	free(sc->sge.nm_rxq, M_CXGBE);
1982 	free(sc->sge.nm_txq, M_CXGBE);
1983 #endif
1984 	free(sc->irq, M_CXGBE);
1985 	free(sc->sge.rxq, M_CXGBE);
1986 	free(sc->sge.txq, M_CXGBE);
1987 	free(sc->sge.ctrlq, M_CXGBE);
1988 	free(sc->sge.iqmap, M_CXGBE);
1989 	free(sc->sge.eqmap, M_CXGBE);
1990 	free(sc->tids.ftid_tab, M_CXGBE);
1991 	free(sc->tids.hpftid_tab, M_CXGBE);
1992 	free_hftid_hash(&sc->tids);
1993 	free(sc->tids.tid_tab, M_CXGBE);
1994 	t4_destroy_dma_tag(sc);
1995 
1996 	callout_drain(&sc->ktls_tick);
1997 	callout_drain(&sc->sfl_callout);
1998 	if (mtx_initialized(&sc->tids.ftid_lock)) {
1999 		mtx_destroy(&sc->tids.ftid_lock);
2000 		cv_destroy(&sc->tids.ftid_cv);
2001 	}
2002 	if (mtx_initialized(&sc->tids.atid_lock))
2003 		mtx_destroy(&sc->tids.atid_lock);
2004 	if (mtx_initialized(&sc->ifp_lock))
2005 		mtx_destroy(&sc->ifp_lock);
2006 
2007 	if (rw_initialized(&sc->policy_lock)) {
2008 		rw_destroy(&sc->policy_lock);
2009 #ifdef TCP_OFFLOAD
2010 		if (sc->policy != NULL)
2011 			free_offload_policy(sc->policy);
2012 #endif
2013 	}
2014 
2015 	for (i = 0; i < NUM_MEMWIN; i++) {
2016 		struct memwin *mw = &sc->memwin[i];
2017 
2018 		if (rw_initialized(&mw->mw_lock))
2019 			rw_destroy(&mw->mw_lock);
2020 	}
2021 
2022 	mtx_destroy(&sc->sfl_lock);
2023 	mtx_destroy(&sc->reg_lock);
2024 	mtx_destroy(&sc->sc_lock);
2025 
2026 	bzero(sc, sizeof(*sc));
2027 
2028 	return (0);
2029 }
2030 
2031 static inline int
2032 stop_adapter(struct adapter *sc)
2033 {
2034 	struct port_info *pi;
2035 	int i;
2036 
2037 	if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) {
2038 		CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n",
2039 			 __func__, curthread, sc->flags, sc->error_flags);
2040 		return (EALREADY);
2041 	}
2042 	CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread,
2043 		 sc->flags, sc->error_flags);
2044 	t4_shutdown_adapter(sc);
2045 	for_each_port(sc, i) {
2046 		pi = sc->port[i];
2047 		if (pi == NULL)
2048 			continue;
2049 		PORT_LOCK(pi);
2050 		if (pi->up_vis > 0 && pi->link_cfg.link_ok) {
2051 			/*
2052 			 * t4_shutdown_adapter has already shut down all the
2053 			 * PHYs but it also disables interrupts and DMA so there
2054 			 * won't be a link interrupt.  Update the state manually
2055 			 * if the link was up previously and inform the kernel.
2056 			 */
2057 			pi->link_cfg.link_ok = false;
2058 			t4_os_link_changed(pi);
2059 		}
2060 		PORT_UNLOCK(pi);
2061 	}
2062 
2063 	return (0);
2064 }
2065 
2066 static inline int
2067 restart_adapter(struct adapter *sc)
2068 {
2069 	uint32_t val;
2070 
2071 	if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) {
2072 		CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n",
2073 			 __func__, curthread, sc->flags, sc->error_flags);
2074 		return (EALREADY);
2075 	}
2076 	CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread,
2077 		 sc->flags, sc->error_flags);
2078 
2079 	MPASS(hw_off_limits(sc));
2080 	MPASS((sc->flags & FW_OK) == 0);
2081 	MPASS((sc->flags & MASTER_PF) == 0);
2082 	MPASS(sc->reset_thread == NULL);
2083 
2084 	/*
2085 	 * The adapter is supposed to be back on PCIE with its config space and
2086 	 * BARs restored to their state before reset.  Register access via
2087 	 * t4_read_reg BAR0 should just work.
2088 	 */
2089 	sc->reset_thread = curthread;
2090 	val = t4_read_reg(sc, A_PL_WHOAMI);
2091 	if (val == 0xffffffff || val == 0xeeeeeeee) {
2092 		CH_ERR(sc, "%s: device registers not readable.\n", __func__);
2093 		sc->reset_thread = NULL;
2094 		atomic_set_int(&sc->error_flags, ADAP_STOPPED);
2095 		return (ENXIO);
2096 	}
2097 	atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR);
2098 	atomic_add_int(&sc->incarnation, 1);
2099 	atomic_add_int(&sc->num_resets, 1);
2100 
2101 	return (0);
2102 }
2103 
2104 static inline void
2105 set_adapter_hwstatus(struct adapter *sc, const bool usable)
2106 {
2107 	if (usable) {
2108 		/* Must be marked reusable by the designated thread. */
2109 		ASSERT_SYNCHRONIZED_OP(sc);
2110 		MPASS(sc->reset_thread == curthread);
2111 		mtx_lock(&sc->reg_lock);
2112 		atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2113 		mtx_unlock(&sc->reg_lock);
2114 	} else {
2115 		/* Mark the adapter totally off limits. */
2116 		begin_synchronized_op(sc, NULL, SLEEP_OK, "t4hwsts");
2117 		mtx_lock(&sc->reg_lock);
2118 		atomic_set_int(&sc->error_flags, HW_OFF_LIMITS);
2119 		mtx_unlock(&sc->reg_lock);
2120 		sc->flags &= ~(FW_OK | MASTER_PF);
2121 		sc->reset_thread = NULL;
2122 		end_synchronized_op(sc, 0);
2123 	}
2124 }
2125 
2126 static int
2127 stop_lld(struct adapter *sc)
2128 {
2129 	struct port_info *pi;
2130 	struct vi_info *vi;
2131 	if_t ifp;
2132 	struct sge_rxq *rxq;
2133 	struct sge_txq *txq;
2134 	struct sge_wrq *wrq;
2135 #ifdef TCP_OFFLOAD
2136 	struct sge_ofld_rxq *ofld_rxq;
2137 #endif
2138 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2139 	struct sge_ofld_txq *ofld_txq;
2140 #endif
2141 	int rc, i, j, k;
2142 
2143 	/*
2144 	 * XXX: Can there be a synch_op in progress that will hang because
2145 	 * hardware has been stopped?  We'll hang too and the solution will be
2146 	 * to use a version of begin_synch_op that wakes up existing synch_op
2147 	 * with errors.  Maybe stop_adapter should do this wakeup?
2148 	 *
2149 	 * I don't think any synch_op could get stranded waiting for DMA or
2150 	 * interrupt so I think we're okay here.  Remove this comment block
2151 	 * after testing.
2152 	 */
2153 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld");
2154 	if (rc != 0)
2155 		return (ENXIO);
2156 
2157 	/* Quiesce all activity. */
2158 	for_each_port(sc, i) {
2159 		pi = sc->port[i];
2160 		if (pi == NULL)
2161 			continue;
2162 		pi->vxlan_tcam_entry = false;
2163 		for_each_vi(pi, j, vi) {
2164 			vi->xact_addr_filt = -1;
2165 			mtx_lock(&vi->tick_mtx);
2166 			vi->flags |= VI_SKIP_STATS;
2167 			mtx_unlock(&vi->tick_mtx);
2168 			if (!(vi->flags & VI_INIT_DONE))
2169 				continue;
2170 
2171 			ifp = vi->ifp;
2172 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2173 				mtx_lock(&vi->tick_mtx);
2174 				callout_stop(&vi->tick);
2175 				mtx_unlock(&vi->tick_mtx);
2176 				callout_drain(&vi->tick);
2177 			}
2178 
2179 			/*
2180 			 * Note that the HW is not available.
2181 			 */
2182 			for_each_txq(vi, k, txq) {
2183 				TXQ_LOCK(txq);
2184 				txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED);
2185 				TXQ_UNLOCK(txq);
2186 			}
2187 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2188 			for_each_ofld_txq(vi, k, ofld_txq) {
2189 				TXQ_LOCK(&ofld_txq->wrq);
2190 				ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED;
2191 				TXQ_UNLOCK(&ofld_txq->wrq);
2192 			}
2193 #endif
2194 			for_each_rxq(vi, k, rxq) {
2195 				rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2196 			}
2197 #if defined(TCP_OFFLOAD)
2198 			for_each_ofld_rxq(vi, k, ofld_rxq) {
2199 				ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2200 			}
2201 #endif
2202 
2203 			quiesce_vi(vi);
2204 		}
2205 
2206 		if (sc->flags & FULL_INIT_DONE) {
2207 			/* Control queue */
2208 			wrq = &sc->sge.ctrlq[i];
2209 			TXQ_LOCK(wrq);
2210 			wrq->eq.flags &= ~EQ_HW_ALLOCATED;
2211 			TXQ_UNLOCK(wrq);
2212 			quiesce_wrq(wrq);
2213 		}
2214 
2215 		if (pi->flags & HAS_TRACEQ) {
2216 			pi->flags &= ~HAS_TRACEQ;
2217 			sc->traceq = -1;
2218 			sc->tracer_valid = 0;
2219 			sc->tracer_enabled = 0;
2220 		}
2221 	}
2222 	if (sc->flags & FULL_INIT_DONE) {
2223 		/* Firmware event queue */
2224 		sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED;
2225 		quiesce_iq_fl(sc, &sc->sge.fwq, NULL);
2226 	}
2227 
2228 	/* Stop calibration */
2229 	callout_stop(&sc->cal_callout);
2230 	callout_drain(&sc->cal_callout);
2231 
2232 	if (t4_clock_gate_on_suspend) {
2233 		t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN |
2234 		    F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN |
2235 		    F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0);
2236 	}
2237 
2238 	end_synchronized_op(sc, 0);
2239 
2240 	stop_atid_allocator(sc);
2241 	t4_stop_l2t(sc);
2242 
2243 	return (rc);
2244 }
2245 
2246 int
2247 suspend_adapter(struct adapter *sc)
2248 {
2249 	stop_adapter(sc);
2250 	stop_lld(sc);
2251 #ifdef TCP_OFFLOAD
2252 	stop_all_uld(sc);
2253 #endif
2254 	set_adapter_hwstatus(sc, false);
2255 
2256 	return (0);
2257 }
2258 
2259 static int
2260 t4_suspend(device_t dev)
2261 {
2262 	struct adapter *sc = device_get_softc(dev);
2263 	int rc;
2264 
2265 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2266 	rc = suspend_adapter(sc);
2267 	CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread);
2268 
2269 	return (rc);
2270 }
2271 
2272 struct adapter_pre_reset_state {
2273 	u_int flags;
2274 	uint16_t nbmcaps;
2275 	uint16_t linkcaps;
2276 	uint16_t switchcaps;
2277 	uint16_t nvmecaps;
2278 	uint16_t niccaps;
2279 	uint16_t toecaps;
2280 	uint16_t rdmacaps;
2281 	uint16_t cryptocaps;
2282 	uint16_t iscsicaps;
2283 	uint16_t fcoecaps;
2284 
2285 	u_int cfcsum;
2286 	char cfg_file[32];
2287 
2288 	struct adapter_params params;
2289 	struct t4_virt_res vres;
2290 	struct tid_info tids;
2291 	struct sge sge;
2292 
2293 	int rawf_base;
2294 	int nrawf;
2295 
2296 };
2297 
2298 static void
2299 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2300 {
2301 
2302 	ASSERT_SYNCHRONIZED_OP(sc);
2303 
2304 	o->flags = sc->flags;
2305 
2306 	o->nbmcaps =  sc->nbmcaps;
2307 	o->linkcaps = sc->linkcaps;
2308 	o->switchcaps = sc->switchcaps;
2309 	o->nvmecaps = sc->nvmecaps;
2310 	o->niccaps = sc->niccaps;
2311 	o->toecaps = sc->toecaps;
2312 	o->rdmacaps = sc->rdmacaps;
2313 	o->cryptocaps = sc->cryptocaps;
2314 	o->iscsicaps = sc->iscsicaps;
2315 	o->fcoecaps = sc->fcoecaps;
2316 
2317 	o->cfcsum = sc->cfcsum;
2318 	MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file));
2319 	memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file));
2320 
2321 	o->params = sc->params;
2322 	o->vres = sc->vres;
2323 	o->tids = sc->tids;
2324 	o->sge = sc->sge;
2325 
2326 	o->rawf_base = sc->rawf_base;
2327 	o->nrawf = sc->nrawf;
2328 }
2329 
2330 static int
2331 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2332 {
2333 	int rc = 0;
2334 
2335 	ASSERT_SYNCHRONIZED_OP(sc);
2336 
2337 	/* Capabilities */
2338 #define COMPARE_CAPS(c) do { \
2339 	if (o->c##caps != sc->c##caps) { \
2340 		CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \
2341 		    sc->c##caps); \
2342 		rc = EINVAL; \
2343 	} \
2344 } while (0)
2345 	COMPARE_CAPS(nbm);
2346 	COMPARE_CAPS(link);
2347 	COMPARE_CAPS(switch);
2348 	COMPARE_CAPS(nvme);
2349 	COMPARE_CAPS(nic);
2350 	COMPARE_CAPS(toe);
2351 	COMPARE_CAPS(rdma);
2352 	COMPARE_CAPS(crypto);
2353 	COMPARE_CAPS(iscsi);
2354 	COMPARE_CAPS(fcoe);
2355 #undef COMPARE_CAPS
2356 
2357 	/* Firmware config file */
2358 	if (o->cfcsum != sc->cfcsum) {
2359 		CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file,
2360 		    o->cfcsum, sc->cfg_file, sc->cfcsum);
2361 		rc = EINVAL;
2362 	}
2363 
2364 #define COMPARE_PARAM(p, name) do { \
2365 	if (o->p != sc->p) { \
2366 		CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \
2367 		rc = EINVAL; \
2368 	} \
2369 } while (0)
2370 	COMPARE_PARAM(sge.iq_start, iq_start);
2371 	COMPARE_PARAM(sge.eq_start, eq_start);
2372 	COMPARE_PARAM(tids.ftid_base, ftid_base);
2373 	COMPARE_PARAM(tids.ftid_end, ftid_end);
2374 	COMPARE_PARAM(tids.nftids, nftids);
2375 	COMPARE_PARAM(vres.l2t.start, l2t_start);
2376 	COMPARE_PARAM(vres.l2t.size, l2t_size);
2377 	COMPARE_PARAM(sge.iqmap_sz, iqmap_sz);
2378 	COMPARE_PARAM(sge.eqmap_sz, eqmap_sz);
2379 	COMPARE_PARAM(tids.tid_base, tid_base);
2380 	COMPARE_PARAM(tids.hpftid_base, hpftid_base);
2381 	COMPARE_PARAM(tids.hpftid_end, hpftid_end);
2382 	COMPARE_PARAM(tids.nhpftids, nhpftids);
2383 	COMPARE_PARAM(rawf_base, rawf_base);
2384 	COMPARE_PARAM(nrawf, nrawf);
2385 	COMPARE_PARAM(params.mps_bg_map, mps_bg_map);
2386 	COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support);
2387 	COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl);
2388 	COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support);
2389 	COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr);
2390 	COMPARE_PARAM(tids.ntids, ntids);
2391 	COMPARE_PARAM(tids.etid_base, etid_base);
2392 	COMPARE_PARAM(tids.etid_end, etid_end);
2393 	COMPARE_PARAM(tids.netids, netids);
2394 	COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred);
2395 	COMPARE_PARAM(params.ethoffload, ethoffload);
2396 	COMPARE_PARAM(tids.natids, natids);
2397 	COMPARE_PARAM(tids.stid_base, stid_base);
2398 	COMPARE_PARAM(vres.ddp.start, ddp_start);
2399 	COMPARE_PARAM(vres.ddp.size, ddp_size);
2400 	COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred);
2401 	COMPARE_PARAM(vres.stag.start, stag_start);
2402 	COMPARE_PARAM(vres.stag.size, stag_size);
2403 	COMPARE_PARAM(vres.rq.start, rq_start);
2404 	COMPARE_PARAM(vres.rq.size, rq_size);
2405 	COMPARE_PARAM(vres.pbl.start, pbl_start);
2406 	COMPARE_PARAM(vres.pbl.size, pbl_size);
2407 	COMPARE_PARAM(vres.qp.start, qp_start);
2408 	COMPARE_PARAM(vres.qp.size, qp_size);
2409 	COMPARE_PARAM(vres.cq.start, cq_start);
2410 	COMPARE_PARAM(vres.cq.size, cq_size);
2411 	COMPARE_PARAM(vres.ocq.start, ocq_start);
2412 	COMPARE_PARAM(vres.ocq.size, ocq_size);
2413 	COMPARE_PARAM(vres.srq.start, srq_start);
2414 	COMPARE_PARAM(vres.srq.size, srq_size);
2415 	COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp);
2416 	COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter);
2417 	COMPARE_PARAM(vres.iscsi.start, iscsi_start);
2418 	COMPARE_PARAM(vres.iscsi.size, iscsi_size);
2419 	COMPARE_PARAM(vres.key.start, key_start);
2420 	COMPARE_PARAM(vres.key.size, key_size);
2421 #undef COMPARE_PARAM
2422 
2423 	return (rc);
2424 }
2425 
2426 static int
2427 restart_lld(struct adapter *sc)
2428 {
2429 	struct adapter_pre_reset_state *old_state = NULL;
2430 	struct port_info *pi;
2431 	struct vi_info *vi;
2432 	if_t ifp;
2433 	struct sge_txq *txq;
2434 	int rc, i, j, k;
2435 
2436 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld");
2437 	if (rc != 0)
2438 		return (ENXIO);
2439 
2440 	/* Restore memory window. */
2441 	setup_memwin(sc);
2442 
2443 	/* Go no further if recovery mode has been requested. */
2444 	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
2445 		CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__);
2446 		rc = 0;
2447 		set_adapter_hwstatus(sc, true);
2448 		goto done;
2449 	}
2450 
2451 	old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK);
2452 	save_caps_and_params(sc, old_state);
2453 
2454 	/* Reestablish contact with firmware and become the primary PF. */
2455 	rc = contact_firmware(sc);
2456 	if (rc != 0)
2457 		goto done; /* error message displayed already */
2458 	MPASS(sc->flags & FW_OK);
2459 
2460 	if (sc->flags & MASTER_PF) {
2461 		rc = partition_resources(sc);
2462 		if (rc != 0)
2463 			goto done; /* error message displayed already */
2464 	}
2465 
2466 	rc = get_params__post_init(sc);
2467 	if (rc != 0)
2468 		goto done; /* error message displayed already */
2469 
2470 	rc = set_params__post_init(sc);
2471 	if (rc != 0)
2472 		goto done; /* error message displayed already */
2473 
2474 	rc = compare_caps_and_params(sc, old_state);
2475 	if (rc != 0)
2476 		goto done; /* error message displayed already */
2477 
2478 	for_each_port(sc, i) {
2479 		pi = sc->port[i];
2480 		MPASS(pi != NULL);
2481 		MPASS(pi->vi != NULL);
2482 		MPASS(pi->vi[0].dev == pi->dev);
2483 
2484 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
2485 		if (rc != 0) {
2486 			CH_ERR(sc,
2487 			    "failed to re-initialize port %d: %d\n", i, rc);
2488 			goto done;
2489 		}
2490 		MPASS(sc->chan_map[pi->tx_chan] == i);
2491 
2492 		PORT_LOCK(pi);
2493 		fixup_link_config(pi);
2494 		build_medialist(pi);
2495 		PORT_UNLOCK(pi);
2496 		for_each_vi(pi, j, vi) {
2497 			if (IS_MAIN_VI(vi))
2498 				continue;
2499 			rc = alloc_extra_vi(sc, pi, vi);
2500 			if (rc != 0) {
2501 				CH_ERR(vi,
2502 				    "failed to re-allocate extra VI: %d\n", rc);
2503 				goto done;
2504 			}
2505 		}
2506 	}
2507 
2508 	/*
2509 	 * Interrupts and queues are about to be enabled and other threads will
2510 	 * want to access the hardware too.  It is safe to do so.  Note that
2511 	 * this thread is still in the middle of a synchronized_op.
2512 	 */
2513 	set_adapter_hwstatus(sc, true);
2514 
2515 	if (sc->flags & FULL_INIT_DONE) {
2516 		rc = adapter_full_init(sc);
2517 		if (rc != 0) {
2518 			CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc);
2519 			goto done;
2520 		}
2521 
2522 		if (sc->vxlan_refcount > 0)
2523 			enable_vxlan_rx(sc);
2524 
2525 		for_each_port(sc, i) {
2526 			pi = sc->port[i];
2527 			for_each_vi(pi, j, vi) {
2528 				mtx_lock(&vi->tick_mtx);
2529 				vi->flags &= ~VI_SKIP_STATS;
2530 				mtx_unlock(&vi->tick_mtx);
2531 				if (!(vi->flags & VI_INIT_DONE))
2532 					continue;
2533 				rc = vi_full_init(vi);
2534 				if (rc != 0) {
2535 					CH_ERR(vi, "failed to re-initialize "
2536 					    "interface: %d\n", rc);
2537 					goto done;
2538 				}
2539 				if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
2540 					sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
2541 					t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
2542 					pi->flags |= HAS_TRACEQ;
2543 				}
2544 
2545 				ifp = vi->ifp;
2546 				if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2547 					continue;
2548 				/*
2549 				 * Note that we do not setup multicast addresses
2550 				 * in the first pass.  This ensures that the
2551 				 * unicast DMACs for all VIs on all ports get an
2552 				 * MPS TCAM entry.
2553 				 */
2554 				rc = update_mac_settings(ifp, XGMAC_ALL &
2555 				    ~XGMAC_MCADDRS);
2556 				if (rc != 0) {
2557 					CH_ERR(vi, "failed to re-configure MAC: %d\n", rc);
2558 					goto done;
2559 				}
2560 				rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true,
2561 				    true);
2562 				if (rc != 0) {
2563 					CH_ERR(vi, "failed to re-enable VI: %d\n", rc);
2564 					goto done;
2565 				}
2566 				for_each_txq(vi, k, txq) {
2567 					TXQ_LOCK(txq);
2568 					txq->eq.flags |= EQ_ENABLED;
2569 					TXQ_UNLOCK(txq);
2570 				}
2571 				mtx_lock(&vi->tick_mtx);
2572 				callout_schedule(&vi->tick, hz);
2573 				mtx_unlock(&vi->tick_mtx);
2574 			}
2575 			PORT_LOCK(pi);
2576 			if (pi->up_vis > 0) {
2577 				t4_update_port_info(pi);
2578 				fixup_link_config(pi);
2579 				build_medialist(pi);
2580 				apply_link_config(pi);
2581 				if (pi->link_cfg.link_ok)
2582 					t4_os_link_changed(pi);
2583 			}
2584 			PORT_UNLOCK(pi);
2585 		}
2586 
2587 		/* Now reprogram the L2 multicast addresses. */
2588 		for_each_port(sc, i) {
2589 			pi = sc->port[i];
2590 			for_each_vi(pi, j, vi) {
2591 				if (!(vi->flags & VI_INIT_DONE))
2592 					continue;
2593 				ifp = vi->ifp;
2594 				if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2595 					continue;
2596 				rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2597 				if (rc != 0) {
2598 					CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc);
2599 					rc = 0;	/* carry on */
2600 				}
2601 			}
2602 		}
2603 	}
2604 
2605 	/* Reset all calibration */
2606 	t4_calibration_start(sc);
2607 done:
2608 	end_synchronized_op(sc, 0);
2609 	free(old_state, M_CXGBE);
2610 
2611 	restart_atid_allocator(sc);
2612 	t4_restart_l2t(sc);
2613 
2614 	return (rc);
2615 }
2616 
2617 int
2618 resume_adapter(struct adapter *sc)
2619 {
2620 	restart_adapter(sc);
2621 	restart_lld(sc);
2622 #ifdef TCP_OFFLOAD
2623 	restart_all_uld(sc);
2624 #endif
2625 	return (0);
2626 }
2627 
2628 static int
2629 t4_resume(device_t dev)
2630 {
2631 	struct adapter *sc = device_get_softc(dev);
2632 	int rc;
2633 
2634 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2635 	rc = resume_adapter(sc);
2636 	CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread);
2637 
2638 	return (rc);
2639 }
2640 
2641 static int
2642 t4_reset_prepare(device_t dev, device_t child)
2643 {
2644 	struct adapter *sc = device_get_softc(dev);
2645 
2646 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2647 	return (0);
2648 }
2649 
2650 static int
2651 t4_reset_post(device_t dev, device_t child)
2652 {
2653 	struct adapter *sc = device_get_softc(dev);
2654 
2655 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2656 	return (0);
2657 }
2658 
2659 static int
2660 reset_adapter_with_pl_rst(struct adapter *sc)
2661 {
2662 	/* This is a t4_write_reg without the hw_off_limits check. */
2663 	MPASS(sc->error_flags & HW_OFF_LIMITS);
2664 	bus_write_4(sc->regs_res, A_PL_RST,
2665 	    F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE);
2666 	pause("pl_rst", 1 * hz);		/* Wait 1s for reset */
2667 	return (0);
2668 }
2669 
2670 static int
2671 reset_adapter_with_pcie_sbr(struct adapter *sc)
2672 {
2673 	device_t pdev = device_get_parent(sc->dev);
2674 	device_t gpdev = device_get_parent(pdev);
2675 	device_t *children;
2676 	int rc, i, lcap, lsta, nchildren;
2677 	uint32_t v;
2678 
2679 	rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v);
2680 	if (rc != 0) {
2681 		CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__,
2682 		    device_get_nameunit(gpdev), rc);
2683 		return (ENOTSUP);
2684 	}
2685 	lcap = v + PCIER_LINK_CAP;
2686 	lsta = v + PCIER_LINK_STA;
2687 
2688 	nchildren = 0;
2689 	device_get_children(pdev, &children, &nchildren);
2690 	for (i = 0; i < nchildren; i++)
2691 		pci_save_state(children[i]);
2692 	v = pci_read_config(gpdev, PCIR_BRIDGECTL_1, 2);
2693 	pci_write_config(gpdev, PCIR_BRIDGECTL_1, v | PCIB_BCR_SECBUS_RESET, 2);
2694 	pause("pcie_sbr1", hz / 10);	/* 100ms */
2695 	pci_write_config(gpdev, PCIR_BRIDGECTL_1, v, 2);
2696 	pause("pcie_sbr2", hz);		/* Wait 1s before restore_state. */
2697 	v = pci_read_config(gpdev, lsta, 2);
2698 	if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE)
2699 		rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT;
2700 	else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING))
2701 		rc = ETIMEDOUT;
2702 	else
2703 		rc = 0;
2704 	if (rc != 0)
2705 		CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n",
2706 		    __func__, v);
2707 	else {
2708 		for (i = 0; i < nchildren; i++)
2709 			pci_restore_state(children[i]);
2710 	}
2711 	free(children, M_TEMP);
2712 
2713 	return (rc);
2714 }
2715 
2716 static int
2717 reset_adapter_with_pcie_link_bounce(struct adapter *sc)
2718 {
2719 	device_t pdev = device_get_parent(sc->dev);
2720 	device_t gpdev = device_get_parent(pdev);
2721 	device_t *children;
2722 	int rc, i, lcap, lctl, lsta, nchildren;
2723 	uint32_t v;
2724 
2725 	rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v);
2726 	if (rc != 0) {
2727 		CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__,
2728 		    device_get_nameunit(gpdev), rc);
2729 		return (ENOTSUP);
2730 	}
2731 	lcap = v + PCIER_LINK_CAP;
2732 	lctl = v + PCIER_LINK_CTL;
2733 	lsta = v + PCIER_LINK_STA;
2734 
2735 	nchildren = 0;
2736 	device_get_children(pdev, &children, &nchildren);
2737 	for (i = 0; i < nchildren; i++)
2738 		pci_save_state(children[i]);
2739 	v = pci_read_config(gpdev, lctl, 2);
2740 	pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_LINK_DIS, 2);
2741 	pause("pcie_lnk1", 100 * hz / 1000);	/* 100ms */
2742 	pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_RETRAIN_LINK, 2);
2743 	pause("pcie_lnk2", hz);		/* Wait 1s before restore_state. */
2744 	v = pci_read_config(gpdev, lsta, 2);
2745 	if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE)
2746 		rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT;
2747 	else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING))
2748 		rc = ETIMEDOUT;
2749 	else
2750 		rc = 0;
2751 	if (rc != 0)
2752 		CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n",
2753 		    __func__, v);
2754 	else {
2755 		for (i = 0; i < nchildren; i++)
2756 			pci_restore_state(children[i]);
2757 	}
2758 	free(children, M_TEMP);
2759 
2760 	return (rc);
2761 }
2762 
2763 static inline int
2764 reset_adapter(struct adapter *sc)
2765 {
2766 	int rc;
2767 	const int reset_method = vm_guest == VM_GUEST_NO ? t4_reset_method : 0;
2768 
2769 	rc = suspend_adapter(sc);
2770 	if (rc != 0)
2771 		return (rc);
2772 
2773 	switch (reset_method) {
2774 	case 1:
2775 		rc = reset_adapter_with_pcie_sbr(sc);
2776 		break;
2777 	case 2:
2778 		rc = reset_adapter_with_pcie_link_bounce(sc);
2779 		break;
2780 	case 0:
2781 	default:
2782 		rc = reset_adapter_with_pl_rst(sc);
2783 		break;
2784 	}
2785 	if (rc == 0)
2786 		rc = resume_adapter(sc);
2787 	return (rc);
2788 }
2789 
2790 static void
2791 reset_adapter_task(void *arg, int pending)
2792 {
2793 	struct adapter *sc = arg;
2794 	const int flags = sc->flags;
2795 	const int eflags = sc->error_flags;
2796 	int rc;
2797 
2798 	if (pending > 1)
2799 		CH_ALERT(sc, "%s: pending %d\n", __func__, pending);
2800 	rc = reset_adapter(sc);
2801 	if (rc != 0) {
2802 		CH_ERR(sc, "adapter did not reset properly, rc = %d, "
2803 		       "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n",
2804 		       rc, flags, sc->flags, eflags, sc->error_flags);
2805 	}
2806 }
2807 
2808 static int
2809 cxgbe_probe(device_t dev)
2810 {
2811 	struct port_info *pi = device_get_softc(dev);
2812 
2813 	device_set_descf(dev, "port %d", pi->port_id);
2814 
2815 	return (BUS_PROBE_DEFAULT);
2816 }
2817 
2818 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
2819     IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
2820     IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
2821     IFCAP_HWRXTSTMP | IFCAP_MEXTPG | IFCAP_NV)
2822 #define T4_CAP_ENABLE (T4_CAP)
2823 
2824 static void
2825 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
2826 {
2827 	if_t ifp;
2828 	struct sbuf *sb;
2829 	struct sysctl_ctx_list *ctx = &vi->ctx;
2830 	struct sysctl_oid_list *children;
2831 	struct pfil_head_args pa;
2832 	struct adapter *sc = vi->adapter;
2833 
2834 	sysctl_ctx_init(ctx);
2835 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev));
2836 	vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq",
2837 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues");
2838 	vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq",
2839 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues");
2840 #ifdef DEV_NETMAP
2841 	vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq",
2842 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues");
2843 	vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq",
2844 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues");
2845 #endif
2846 #ifdef TCP_OFFLOAD
2847 	vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq",
2848 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues");
2849 #endif
2850 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2851 	vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq",
2852 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues");
2853 #endif
2854 
2855 	vi->xact_addr_filt = -1;
2856 	mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF);
2857 	callout_init_mtx(&vi->tick, &vi->tick_mtx, 0);
2858 	if (sc->flags & IS_VF || t4_tx_vm_wr != 0)
2859 		vi->flags |= TX_USES_VM_WR;
2860 
2861 	/* Allocate an ifnet and set it up */
2862 	ifp = if_alloc_dev(IFT_ETHER, dev);
2863 	vi->ifp = ifp;
2864 	if_setsoftc(ifp, vi);
2865 
2866 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2867 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
2868 
2869 	if_setinitfn(ifp, cxgbe_init);
2870 	if_setioctlfn(ifp, cxgbe_ioctl);
2871 	if_settransmitfn(ifp, cxgbe_transmit);
2872 	if_setqflushfn(ifp, cxgbe_qflush);
2873 	if (vi->pi->nvi > 1 || sc->flags & IS_VF)
2874 		if_setgetcounterfn(ifp, vi_get_counter);
2875 	else
2876 		if_setgetcounterfn(ifp, cxgbe_get_counter);
2877 #if defined(KERN_TLS) || defined(RATELIMIT)
2878 	if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc);
2879 #endif
2880 #ifdef RATELIMIT
2881 	if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query);
2882 #endif
2883 
2884 	if_setcapabilities(ifp, T4_CAP);
2885 	if_setcapenable(ifp, T4_CAP_ENABLE);
2886 	if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
2887 	    CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2888 	if (chip_id(sc) >= CHELSIO_T6) {
2889 		if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2890 		if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2891 		if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
2892 		    CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2893 		    CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0);
2894 	}
2895 
2896 #ifdef TCP_OFFLOAD
2897 	if (vi->nofldrxq != 0)
2898 		if_setcapabilitiesbit(ifp, IFCAP_TOE, 0);
2899 #endif
2900 #ifdef RATELIMIT
2901 	if (is_ethoffload(sc) && vi->nofldtxq != 0) {
2902 		if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0);
2903 		if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0);
2904 	}
2905 #endif
2906 
2907 	if_sethwtsomax(ifp, IP_MAXPACKET);
2908 	if (vi->flags & TX_USES_VM_WR)
2909 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO);
2910 	else
2911 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO);
2912 #ifdef RATELIMIT
2913 	if (is_ethoffload(sc) && vi->nofldtxq != 0)
2914 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO);
2915 #endif
2916 	if_sethwtsomaxsegsize(ifp, 65536);
2917 #ifdef KERN_TLS
2918 	if (is_ktls(sc)) {
2919 		if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0);
2920 		if (sc->flags & KERN_TLS_ON || !is_t6(sc))
2921 			if_setcapenablebit(ifp, IFCAP_TXTLS, 0);
2922 	}
2923 #endif
2924 
2925 	ether_ifattach(ifp, vi->hw_addr);
2926 #ifdef DEV_NETMAP
2927 	if (vi->nnmrxq != 0)
2928 		cxgbe_nm_attach(vi);
2929 #endif
2930 	sb = sbuf_new_auto();
2931 	sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
2932 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2933 	switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) {
2934 	case IFCAP_TOE:
2935 		sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
2936 		break;
2937 	case IFCAP_TOE | IFCAP_TXRTLMT:
2938 		sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
2939 		break;
2940 	case IFCAP_TXRTLMT:
2941 		sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
2942 		break;
2943 	}
2944 #endif
2945 #ifdef TCP_OFFLOAD
2946 	if (if_getcapabilities(ifp) & IFCAP_TOE)
2947 		sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
2948 #endif
2949 #ifdef DEV_NETMAP
2950 	if (if_getcapabilities(ifp) & IFCAP_NETMAP)
2951 		sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
2952 		    vi->nnmtxq, vi->nnmrxq);
2953 #endif
2954 	sbuf_finish(sb);
2955 	device_printf(dev, "%s\n", sbuf_data(sb));
2956 	sbuf_delete(sb);
2957 
2958 	vi_sysctls(vi);
2959 
2960 	pa.pa_version = PFIL_VERSION;
2961 	pa.pa_flags = PFIL_IN;
2962 	pa.pa_type = PFIL_TYPE_ETHERNET;
2963 	pa.pa_headname = if_name(ifp);
2964 	vi->pfil = pfil_head_register(&pa);
2965 }
2966 
2967 static int
2968 cxgbe_attach(device_t dev)
2969 {
2970 	struct port_info *pi = device_get_softc(dev);
2971 	struct adapter *sc = pi->adapter;
2972 	struct vi_info *vi;
2973 	int i;
2974 
2975 	sysctl_ctx_init(&pi->ctx);
2976 
2977 	cxgbe_vi_attach(dev, &pi->vi[0]);
2978 
2979 	for_each_vi(pi, i, vi) {
2980 		if (i == 0)
2981 			continue;
2982 		vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY);
2983 		if (vi->dev == NULL) {
2984 			device_printf(dev, "failed to add VI %d\n", i);
2985 			continue;
2986 		}
2987 		device_set_softc(vi->dev, vi);
2988 	}
2989 
2990 	cxgbe_sysctls(pi);
2991 
2992 	bus_attach_children(dev);
2993 
2994 	return (0);
2995 }
2996 
2997 static void
2998 cxgbe_vi_detach(struct vi_info *vi)
2999 {
3000 	if_t ifp = vi->ifp;
3001 
3002 	if (vi->pfil != NULL) {
3003 		pfil_head_unregister(vi->pfil);
3004 		vi->pfil = NULL;
3005 	}
3006 
3007 	ether_ifdetach(ifp);
3008 
3009 	/* Let detach proceed even if these fail. */
3010 #ifdef DEV_NETMAP
3011 	if (if_getcapabilities(ifp) & IFCAP_NETMAP)
3012 		cxgbe_nm_detach(vi);
3013 #endif
3014 	cxgbe_uninit_synchronized(vi);
3015 	callout_drain(&vi->tick);
3016 	mtx_destroy(&vi->tick_mtx);
3017 	sysctl_ctx_free(&vi->ctx);
3018 	vi_full_uninit(vi);
3019 
3020 	if_free(vi->ifp);
3021 	vi->ifp = NULL;
3022 }
3023 
3024 static int
3025 cxgbe_detach(device_t dev)
3026 {
3027 	struct port_info *pi = device_get_softc(dev);
3028 	struct adapter *sc = pi->adapter;
3029 	int rc;
3030 
3031 	/* Detach the extra VIs first. */
3032 	rc = bus_generic_detach(dev);
3033 	if (rc)
3034 		return (rc);
3035 
3036 	sysctl_ctx_free(&pi->ctx);
3037 	begin_vi_detach(sc, &pi->vi[0]);
3038 	if (pi->flags & HAS_TRACEQ) {
3039 		sc->traceq = -1;	/* cloner should not create ifnet */
3040 		t4_tracer_port_detach(sc);
3041 	}
3042 	cxgbe_vi_detach(&pi->vi[0]);
3043 	ifmedia_removeall(&pi->media);
3044 	end_vi_detach(sc, &pi->vi[0]);
3045 
3046 	return (0);
3047 }
3048 
3049 static void
3050 cxgbe_init(void *arg)
3051 {
3052 	struct vi_info *vi = arg;
3053 	struct adapter *sc = vi->adapter;
3054 
3055 	if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
3056 		return;
3057 	cxgbe_init_synchronized(vi);
3058 	end_synchronized_op(sc, 0);
3059 }
3060 
3061 static int
3062 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data)
3063 {
3064 	int rc = 0, mtu, flags;
3065 	struct vi_info *vi = if_getsoftc(ifp);
3066 	struct port_info *pi = vi->pi;
3067 	struct adapter *sc = pi->adapter;
3068 	struct ifreq *ifr = (struct ifreq *)data;
3069 	uint32_t mask, mask2;
3070 
3071 	switch (cmd) {
3072 	case SIOCSIFMTU:
3073 		mtu = ifr->ifr_mtu;
3074 		if (mtu < ETHERMIN || mtu > MAX_MTU)
3075 			return (EINVAL);
3076 
3077 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
3078 		if (rc)
3079 			return (rc);
3080 		if_setmtu(ifp, mtu);
3081 		if (vi->flags & VI_INIT_DONE) {
3082 			t4_update_fl_bufsize(ifp);
3083 			if (hw_all_ok(sc) &&
3084 			    if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3085 				rc = update_mac_settings(ifp, XGMAC_MTU);
3086 		}
3087 		end_synchronized_op(sc, 0);
3088 		break;
3089 
3090 	case SIOCSIFFLAGS:
3091 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
3092 		if (rc)
3093 			return (rc);
3094 
3095 		if (!hw_all_ok(sc)) {
3096 			rc = ENXIO;
3097 			goto fail;
3098 		}
3099 
3100 		if (if_getflags(ifp) & IFF_UP) {
3101 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3102 				flags = vi->if_flags;
3103 				if ((if_getflags(ifp) ^ flags) &
3104 				    (IFF_PROMISC | IFF_ALLMULTI)) {
3105 					rc = update_mac_settings(ifp,
3106 					    XGMAC_PROMISC | XGMAC_ALLMULTI);
3107 				}
3108 			} else {
3109 				rc = cxgbe_init_synchronized(vi);
3110 			}
3111 			vi->if_flags = if_getflags(ifp);
3112 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3113 			rc = cxgbe_uninit_synchronized(vi);
3114 		}
3115 		end_synchronized_op(sc, 0);
3116 		break;
3117 
3118 	case SIOCADDMULTI:
3119 	case SIOCDELMULTI:
3120 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
3121 		if (rc)
3122 			return (rc);
3123 		if (hw_all_ok(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3124 			rc = update_mac_settings(ifp, XGMAC_MCADDRS);
3125 		end_synchronized_op(sc, 0);
3126 		break;
3127 
3128 	case SIOCGIFCAPNV:
3129 		break;
3130 	case SIOCSIFCAPNV:
3131 	case SIOCSIFCAP:
3132 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
3133 		if (rc)
3134 			return (rc);
3135 
3136 		if (cmd == SIOCSIFCAPNV) {
3137 			const struct siocsifcapnv_driver_data *ifr_nv =
3138 			    (struct siocsifcapnv_driver_data *)data;
3139 
3140 			mask = ifr_nv->reqcap ^ if_getcapenable(ifp);
3141 			mask2 = ifr_nv->reqcap2 ^ if_getcapenable2(ifp);
3142 		} else {
3143 			mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3144 			mask2 = 0;
3145 		}
3146 		if (mask & IFCAP_TXCSUM) {
3147 			if_togglecapenable(ifp, IFCAP_TXCSUM);
3148 			if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP);
3149 
3150 			if (IFCAP_TSO4 & if_getcapenable(ifp) &&
3151 			    !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3152 				mask &= ~IFCAP_TSO4;
3153 				if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3154 				if_printf(ifp,
3155 				    "tso4 disabled due to -txcsum.\n");
3156 			}
3157 		}
3158 		if (mask & IFCAP_TXCSUM_IPV6) {
3159 			if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
3160 			if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3161 
3162 			if (IFCAP_TSO6 & if_getcapenable(ifp) &&
3163 			    !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3164 				mask &= ~IFCAP_TSO6;
3165 				if_setcapenablebit(ifp, 0, IFCAP_TSO6);
3166 				if_printf(ifp,
3167 				    "tso6 disabled due to -txcsum6.\n");
3168 			}
3169 		}
3170 		if (mask & IFCAP_RXCSUM)
3171 			if_togglecapenable(ifp, IFCAP_RXCSUM);
3172 		if (mask & IFCAP_RXCSUM_IPV6)
3173 			if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
3174 
3175 		/*
3176 		 * Note that we leave CSUM_TSO alone (it is always set).  The
3177 		 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
3178 		 * sending a TSO request our way, so it's sufficient to toggle
3179 		 * IFCAP_TSOx only.
3180 		 */
3181 		if (mask & IFCAP_TSO4) {
3182 			if (!(IFCAP_TSO4 & if_getcapenable(ifp)) &&
3183 			    !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3184 				if_printf(ifp, "enable txcsum first.\n");
3185 				rc = EAGAIN;
3186 				goto fail;
3187 			}
3188 			if_togglecapenable(ifp, IFCAP_TSO4);
3189 		}
3190 		if (mask & IFCAP_TSO6) {
3191 			if (!(IFCAP_TSO6 & if_getcapenable(ifp)) &&
3192 			    !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3193 				if_printf(ifp, "enable txcsum6 first.\n");
3194 				rc = EAGAIN;
3195 				goto fail;
3196 			}
3197 			if_togglecapenable(ifp, IFCAP_TSO6);
3198 		}
3199 		if (mask & IFCAP_LRO) {
3200 #if defined(INET) || defined(INET6)
3201 			int i;
3202 			struct sge_rxq *rxq;
3203 
3204 			if_togglecapenable(ifp, IFCAP_LRO);
3205 			for_each_rxq(vi, i, rxq) {
3206 				if (if_getcapenable(ifp) & IFCAP_LRO)
3207 					rxq->iq.flags |= IQ_LRO_ENABLED;
3208 				else
3209 					rxq->iq.flags &= ~IQ_LRO_ENABLED;
3210 			}
3211 #endif
3212 		}
3213 #ifdef TCP_OFFLOAD
3214 		if (mask & IFCAP_TOE) {
3215 			int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE;
3216 
3217 			rc = toe_capability(vi, enable);
3218 			if (rc != 0)
3219 				goto fail;
3220 
3221 			if_togglecapenable(ifp, mask);
3222 		}
3223 #endif
3224 		if (mask & IFCAP_VLAN_HWTAGGING) {
3225 			if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3226 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3227 				rc = update_mac_settings(ifp, XGMAC_VLANEX);
3228 		}
3229 		if (mask & IFCAP_VLAN_MTU) {
3230 			if_togglecapenable(ifp, IFCAP_VLAN_MTU);
3231 
3232 			/* Need to find out how to disable auto-mtu-inflation */
3233 		}
3234 		if (mask & IFCAP_VLAN_HWTSO)
3235 			if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
3236 		if (mask & IFCAP_VLAN_HWCSUM)
3237 			if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
3238 #ifdef RATELIMIT
3239 		if (mask & IFCAP_TXRTLMT)
3240 			if_togglecapenable(ifp, IFCAP_TXRTLMT);
3241 #endif
3242 		if (mask & IFCAP_HWRXTSTMP) {
3243 			int i;
3244 			struct sge_rxq *rxq;
3245 
3246 			if_togglecapenable(ifp, IFCAP_HWRXTSTMP);
3247 			for_each_rxq(vi, i, rxq) {
3248 				if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP)
3249 					rxq->iq.flags |= IQ_RX_TIMESTAMP;
3250 				else
3251 					rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
3252 			}
3253 		}
3254 		if (mask & IFCAP_MEXTPG)
3255 			if_togglecapenable(ifp, IFCAP_MEXTPG);
3256 
3257 #ifdef KERN_TLS
3258 		if (mask & IFCAP_TXTLS) {
3259 			int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS;
3260 
3261 			rc = ktls_capability(sc, enable);
3262 			if (rc != 0)
3263 				goto fail;
3264 
3265 			if_togglecapenable(ifp, mask & IFCAP_TXTLS);
3266 		}
3267 #endif
3268 		if (mask & IFCAP_VXLAN_HWCSUM) {
3269 			if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM);
3270 			if_togglehwassist(ifp, CSUM_INNER_IP6_UDP |
3271 			    CSUM_INNER_IP6_TCP | CSUM_INNER_IP |
3272 			    CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP);
3273 		}
3274 		if (mask & IFCAP_VXLAN_HWTSO) {
3275 			if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO);
3276 			if_togglehwassist(ifp, CSUM_INNER_IP6_TSO |
3277 			    CSUM_INNER_IP_TSO);
3278 		}
3279 
3280 		MPASS(mask2 == 0);
3281 		(void)mask2;
3282 
3283 #ifdef VLAN_CAPABILITIES
3284 		VLAN_CAPABILITIES(ifp);
3285 #endif
3286 fail:
3287 		end_synchronized_op(sc, 0);
3288 		break;
3289 
3290 	case SIOCSIFMEDIA:
3291 	case SIOCGIFMEDIA:
3292 	case SIOCGIFXMEDIA:
3293 		rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
3294 		break;
3295 
3296 	case SIOCGI2C: {
3297 		struct ifi2creq i2c;
3298 
3299 		rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3300 		if (rc != 0)
3301 			break;
3302 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3303 			rc = EPERM;
3304 			break;
3305 		}
3306 		if (i2c.len > sizeof(i2c.data)) {
3307 			rc = EINVAL;
3308 			break;
3309 		}
3310 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
3311 		if (rc)
3312 			return (rc);
3313 		if (!hw_all_ok(sc))
3314 			rc = ENXIO;
3315 		else
3316 			rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
3317 			    i2c.offset, i2c.len, &i2c.data[0]);
3318 		end_synchronized_op(sc, 0);
3319 		if (rc == 0)
3320 			rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3321 		break;
3322 	}
3323 
3324 	default:
3325 		rc = ether_ioctl(ifp, cmd, data);
3326 	}
3327 
3328 	return (rc);
3329 }
3330 
3331 static int
3332 cxgbe_transmit(if_t ifp, struct mbuf *m)
3333 {
3334 	struct vi_info *vi = if_getsoftc(ifp);
3335 	struct port_info *pi = vi->pi;
3336 	struct adapter *sc;
3337 	struct sge_txq *txq;
3338 	void *items[1];
3339 	int rc;
3340 
3341 	M_ASSERTPKTHDR(m);
3342 	MPASS(m->m_nextpkt == NULL);	/* not quite ready for this yet */
3343 #if defined(KERN_TLS) || defined(RATELIMIT)
3344 	if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
3345 		MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
3346 #endif
3347 
3348 	if (__predict_false(pi->link_cfg.link_ok == false)) {
3349 		m_freem(m);
3350 		return (ENETDOWN);
3351 	}
3352 
3353 	rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR);
3354 	if (__predict_false(rc != 0)) {
3355 		if (__predict_true(rc == EINPROGRESS)) {
3356 			/* queued by parse_pkt */
3357 			MPASS(m != NULL);
3358 			return (0);
3359 		}
3360 
3361 		MPASS(m == NULL);			/* was freed already */
3362 		atomic_add_int(&pi->tx_parse_error, 1);	/* rare, atomic is ok */
3363 		return (rc);
3364 	}
3365 
3366 	/* Select a txq. */
3367 	sc = vi->adapter;
3368 	txq = &sc->sge.txq[vi->first_txq];
3369 	if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
3370 		txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
3371 		    vi->rsrv_noflowq);
3372 
3373 	items[0] = m;
3374 	rc = mp_ring_enqueue(txq->r, items, 1, 256);
3375 	if (__predict_false(rc != 0))
3376 		m_freem(m);
3377 
3378 	return (rc);
3379 }
3380 
3381 static void
3382 cxgbe_qflush(if_t ifp)
3383 {
3384 	struct vi_info *vi = if_getsoftc(ifp);
3385 	struct sge_txq *txq;
3386 	int i;
3387 
3388 	/* queues do not exist if !VI_INIT_DONE. */
3389 	if (vi->flags & VI_INIT_DONE) {
3390 		for_each_txq(vi, i, txq) {
3391 			TXQ_LOCK(txq);
3392 			txq->eq.flags |= EQ_QFLUSH;
3393 			TXQ_UNLOCK(txq);
3394 			while (!mp_ring_is_idle(txq->r)) {
3395 				mp_ring_check_drainage(txq->r, 4096);
3396 				pause("qflush", 1);
3397 			}
3398 			TXQ_LOCK(txq);
3399 			txq->eq.flags &= ~EQ_QFLUSH;
3400 			TXQ_UNLOCK(txq);
3401 		}
3402 	}
3403 	if_qflush(ifp);
3404 }
3405 
3406 static uint64_t
3407 vi_get_counter(if_t ifp, ift_counter c)
3408 {
3409 	struct vi_info *vi = if_getsoftc(ifp);
3410 	struct fw_vi_stats_vf *s = &vi->stats;
3411 
3412 	mtx_lock(&vi->tick_mtx);
3413 	vi_refresh_stats(vi);
3414 	mtx_unlock(&vi->tick_mtx);
3415 
3416 	switch (c) {
3417 	case IFCOUNTER_IPACKETS:
3418 		return (s->rx_bcast_frames + s->rx_mcast_frames +
3419 		    s->rx_ucast_frames);
3420 	case IFCOUNTER_IERRORS:
3421 		return (s->rx_err_frames);
3422 	case IFCOUNTER_OPACKETS:
3423 		return (s->tx_bcast_frames + s->tx_mcast_frames +
3424 		    s->tx_ucast_frames + s->tx_offload_frames);
3425 	case IFCOUNTER_OERRORS:
3426 		return (s->tx_drop_frames);
3427 	case IFCOUNTER_IBYTES:
3428 		return (s->rx_bcast_bytes + s->rx_mcast_bytes +
3429 		    s->rx_ucast_bytes);
3430 	case IFCOUNTER_OBYTES:
3431 		return (s->tx_bcast_bytes + s->tx_mcast_bytes +
3432 		    s->tx_ucast_bytes + s->tx_offload_bytes);
3433 	case IFCOUNTER_IMCASTS:
3434 		return (s->rx_mcast_frames);
3435 	case IFCOUNTER_OMCASTS:
3436 		return (s->tx_mcast_frames);
3437 	case IFCOUNTER_OQDROPS: {
3438 		uint64_t drops;
3439 
3440 		drops = 0;
3441 		if (vi->flags & VI_INIT_DONE) {
3442 			int i;
3443 			struct sge_txq *txq;
3444 
3445 			for_each_txq(vi, i, txq)
3446 				drops += counter_u64_fetch(txq->r->dropped);
3447 		}
3448 
3449 		return (drops);
3450 
3451 	}
3452 
3453 	default:
3454 		return (if_get_counter_default(ifp, c));
3455 	}
3456 }
3457 
3458 static uint64_t
3459 cxgbe_get_counter(if_t ifp, ift_counter c)
3460 {
3461 	struct vi_info *vi = if_getsoftc(ifp);
3462 	struct port_info *pi = vi->pi;
3463 	struct port_stats *s = &pi->stats;
3464 
3465 	mtx_lock(&vi->tick_mtx);
3466 	cxgbe_refresh_stats(vi);
3467 	mtx_unlock(&vi->tick_mtx);
3468 
3469 	switch (c) {
3470 	case IFCOUNTER_IPACKETS:
3471 		return (s->rx_frames);
3472 
3473 	case IFCOUNTER_IERRORS:
3474 		return (s->rx_jabber + s->rx_runt + s->rx_too_long +
3475 		    s->rx_fcs_err + s->rx_len_err);
3476 
3477 	case IFCOUNTER_OPACKETS:
3478 		return (s->tx_frames);
3479 
3480 	case IFCOUNTER_OERRORS:
3481 		return (s->tx_error_frames);
3482 
3483 	case IFCOUNTER_IBYTES:
3484 		return (s->rx_octets);
3485 
3486 	case IFCOUNTER_OBYTES:
3487 		return (s->tx_octets);
3488 
3489 	case IFCOUNTER_IMCASTS:
3490 		return (s->rx_mcast_frames);
3491 
3492 	case IFCOUNTER_OMCASTS:
3493 		return (s->tx_mcast_frames);
3494 
3495 	case IFCOUNTER_IQDROPS:
3496 		return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
3497 		    s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
3498 		    s->rx_trunc3 + pi->tnl_cong_drops);
3499 
3500 	case IFCOUNTER_OQDROPS: {
3501 		uint64_t drops;
3502 
3503 		drops = s->tx_drop;
3504 		if (vi->flags & VI_INIT_DONE) {
3505 			int i;
3506 			struct sge_txq *txq;
3507 
3508 			for_each_txq(vi, i, txq)
3509 				drops += counter_u64_fetch(txq->r->dropped);
3510 		}
3511 
3512 		return (drops);
3513 
3514 	}
3515 
3516 	default:
3517 		return (if_get_counter_default(ifp, c));
3518 	}
3519 }
3520 
3521 #if defined(KERN_TLS) || defined(RATELIMIT)
3522 static int
3523 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params,
3524     struct m_snd_tag **pt)
3525 {
3526 	int error;
3527 
3528 	switch (params->hdr.type) {
3529 #ifdef RATELIMIT
3530 	case IF_SND_TAG_TYPE_RATE_LIMIT:
3531 		error = cxgbe_rate_tag_alloc(ifp, params, pt);
3532 		break;
3533 #endif
3534 #ifdef KERN_TLS
3535 	case IF_SND_TAG_TYPE_TLS:
3536 	{
3537 		struct vi_info *vi = if_getsoftc(ifp);
3538 
3539 		if (is_t6(vi->pi->adapter))
3540 			error = t6_tls_tag_alloc(ifp, params, pt);
3541 		else
3542 			error = t7_tls_tag_alloc(ifp, params, pt);
3543 		break;
3544 	}
3545 #endif
3546 	default:
3547 		error = EOPNOTSUPP;
3548 	}
3549 	return (error);
3550 }
3551 #endif
3552 
3553 /*
3554  * The kernel picks a media from the list we had provided but we still validate
3555  * the requeste.
3556  */
3557 int
3558 cxgbe_media_change(if_t ifp)
3559 {
3560 	struct vi_info *vi = if_getsoftc(ifp);
3561 	struct port_info *pi = vi->pi;
3562 	struct ifmedia *ifm = &pi->media;
3563 	struct link_config *lc = &pi->link_cfg;
3564 	struct adapter *sc = pi->adapter;
3565 	int rc;
3566 
3567 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
3568 	if (rc != 0)
3569 		return (rc);
3570 	PORT_LOCK(pi);
3571 	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
3572 		/* ifconfig .. media autoselect */
3573 		if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
3574 			rc = ENOTSUP; /* AN not supported by transceiver */
3575 			goto done;
3576 		}
3577 		lc->requested_aneg = AUTONEG_ENABLE;
3578 		lc->requested_speed = 0;
3579 		lc->requested_fc |= PAUSE_AUTONEG;
3580 	} else {
3581 		lc->requested_aneg = AUTONEG_DISABLE;
3582 		lc->requested_speed =
3583 		    ifmedia_baudrate(ifm->ifm_media) / 1000000;
3584 		lc->requested_fc = 0;
3585 		if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
3586 			lc->requested_fc |= PAUSE_RX;
3587 		if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
3588 			lc->requested_fc |= PAUSE_TX;
3589 	}
3590 	if (pi->up_vis > 0 && hw_all_ok(sc)) {
3591 		fixup_link_config(pi);
3592 		rc = apply_link_config(pi);
3593 	}
3594 done:
3595 	PORT_UNLOCK(pi);
3596 	end_synchronized_op(sc, 0);
3597 	return (rc);
3598 }
3599 
3600 /*
3601  * Base media word (without ETHER, pause, link active, etc.) for the port at the
3602  * given speed.
3603  */
3604 static int
3605 port_mword(struct port_info *pi, uint32_t speed)
3606 {
3607 
3608 	MPASS(speed & M_FW_PORT_CAP32_SPEED);
3609 	MPASS(powerof2(speed));
3610 
3611 	switch(pi->port_type) {
3612 	case FW_PORT_TYPE_BT_SGMII:
3613 	case FW_PORT_TYPE_BT_XFI:
3614 	case FW_PORT_TYPE_BT_XAUI:
3615 		/* BaseT */
3616 		switch (speed) {
3617 		case FW_PORT_CAP32_SPEED_100M:
3618 			return (IFM_100_T);
3619 		case FW_PORT_CAP32_SPEED_1G:
3620 			return (IFM_1000_T);
3621 		case FW_PORT_CAP32_SPEED_10G:
3622 			return (IFM_10G_T);
3623 		}
3624 		break;
3625 	case FW_PORT_TYPE_KX4:
3626 		if (speed == FW_PORT_CAP32_SPEED_10G)
3627 			return (IFM_10G_KX4);
3628 		break;
3629 	case FW_PORT_TYPE_CX4:
3630 		if (speed == FW_PORT_CAP32_SPEED_10G)
3631 			return (IFM_10G_CX4);
3632 		break;
3633 	case FW_PORT_TYPE_KX:
3634 		if (speed == FW_PORT_CAP32_SPEED_1G)
3635 			return (IFM_1000_KX);
3636 		break;
3637 	case FW_PORT_TYPE_KR:
3638 	case FW_PORT_TYPE_BP_AP:
3639 	case FW_PORT_TYPE_BP4_AP:
3640 	case FW_PORT_TYPE_BP40_BA:
3641 	case FW_PORT_TYPE_KR4_100G:
3642 	case FW_PORT_TYPE_KR_SFP28:
3643 	case FW_PORT_TYPE_KR_XLAUI:
3644 		switch (speed) {
3645 		case FW_PORT_CAP32_SPEED_1G:
3646 			return (IFM_1000_KX);
3647 		case FW_PORT_CAP32_SPEED_10G:
3648 			return (IFM_10G_KR);
3649 		case FW_PORT_CAP32_SPEED_25G:
3650 			return (IFM_25G_KR);
3651 		case FW_PORT_CAP32_SPEED_40G:
3652 			return (IFM_40G_KR4);
3653 		case FW_PORT_CAP32_SPEED_50G:
3654 			return (IFM_50G_KR2);
3655 		case FW_PORT_CAP32_SPEED_100G:
3656 			return (IFM_100G_KR4);
3657 		}
3658 		break;
3659 	case FW_PORT_TYPE_FIBER_XFI:
3660 	case FW_PORT_TYPE_FIBER_XAUI:
3661 	case FW_PORT_TYPE_SFP:
3662 	case FW_PORT_TYPE_QSFP_10G:
3663 	case FW_PORT_TYPE_QSA:
3664 	case FW_PORT_TYPE_QSFP:
3665 	case FW_PORT_TYPE_CR4_QSFP:
3666 	case FW_PORT_TYPE_CR_QSFP:
3667 	case FW_PORT_TYPE_CR2_QSFP:
3668 	case FW_PORT_TYPE_SFP28:
3669 	case FW_PORT_TYPE_SFP56:
3670 	case FW_PORT_TYPE_QSFP56:
3671 	case FW_PORT_TYPE_QSFPDD:
3672 		/* Pluggable transceiver */
3673 		switch (pi->mod_type) {
3674 		case FW_PORT_MOD_TYPE_LR:
3675 		case FW_PORT_MOD_TYPE_LR_SIMPLEX:
3676 			switch (speed) {
3677 			case FW_PORT_CAP32_SPEED_1G:
3678 				return (IFM_1000_LX);
3679 			case FW_PORT_CAP32_SPEED_10G:
3680 				return (IFM_10G_LR);
3681 			case FW_PORT_CAP32_SPEED_25G:
3682 				return (IFM_25G_LR);
3683 			case FW_PORT_CAP32_SPEED_40G:
3684 				return (IFM_40G_LR4);
3685 			case FW_PORT_CAP32_SPEED_50G:
3686 				return (IFM_50G_LR2);
3687 			case FW_PORT_CAP32_SPEED_100G:
3688 				return (IFM_100G_LR4);
3689 			case FW_PORT_CAP32_SPEED_200G:
3690 				return (IFM_200G_LR4);
3691 			case FW_PORT_CAP32_SPEED_400G:
3692 				return (IFM_400G_LR8);
3693 			}
3694 			break;
3695 		case FW_PORT_MOD_TYPE_SR:
3696 			switch (speed) {
3697 			case FW_PORT_CAP32_SPEED_1G:
3698 				return (IFM_1000_SX);
3699 			case FW_PORT_CAP32_SPEED_10G:
3700 				return (IFM_10G_SR);
3701 			case FW_PORT_CAP32_SPEED_25G:
3702 				return (IFM_25G_SR);
3703 			case FW_PORT_CAP32_SPEED_40G:
3704 				return (IFM_40G_SR4);
3705 			case FW_PORT_CAP32_SPEED_50G:
3706 				return (IFM_50G_SR2);
3707 			case FW_PORT_CAP32_SPEED_100G:
3708 				return (IFM_100G_SR4);
3709 			case FW_PORT_CAP32_SPEED_200G:
3710 				return (IFM_200G_SR4);
3711 			case FW_PORT_CAP32_SPEED_400G:
3712 				return (IFM_400G_SR8);
3713 			}
3714 			break;
3715 		case FW_PORT_MOD_TYPE_ER:
3716 			if (speed == FW_PORT_CAP32_SPEED_10G)
3717 				return (IFM_10G_ER);
3718 			break;
3719 		case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3720 		case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3721 			switch (speed) {
3722 			case FW_PORT_CAP32_SPEED_1G:
3723 				return (IFM_1000_CX);
3724 			case FW_PORT_CAP32_SPEED_10G:
3725 				return (IFM_10G_TWINAX);
3726 			case FW_PORT_CAP32_SPEED_25G:
3727 				return (IFM_25G_CR);
3728 			case FW_PORT_CAP32_SPEED_40G:
3729 				return (IFM_40G_CR4);
3730 			case FW_PORT_CAP32_SPEED_50G:
3731 				return (IFM_50G_CR2);
3732 			case FW_PORT_CAP32_SPEED_100G:
3733 				return (IFM_100G_CR4);
3734 			case FW_PORT_CAP32_SPEED_200G:
3735 				return (IFM_200G_CR4_PAM4);
3736 			case FW_PORT_CAP32_SPEED_400G:
3737 				return (IFM_400G_CR8);
3738 			}
3739 			break;
3740 		case FW_PORT_MOD_TYPE_LRM:
3741 			if (speed == FW_PORT_CAP32_SPEED_10G)
3742 				return (IFM_10G_LRM);
3743 			break;
3744 		case FW_PORT_MOD_TYPE_DR:
3745 			if (speed == FW_PORT_CAP32_SPEED_100G)
3746 				return (IFM_100G_DR);
3747 			if (speed == FW_PORT_CAP32_SPEED_200G)
3748 				return (IFM_200G_DR4);
3749 			if (speed == FW_PORT_CAP32_SPEED_400G)
3750 				return (IFM_400G_DR4);
3751 			break;
3752 		case FW_PORT_MOD_TYPE_NA:
3753 			MPASS(0);	/* Not pluggable? */
3754 			/* fall through */
3755 		case FW_PORT_MOD_TYPE_ERROR:
3756 		case FW_PORT_MOD_TYPE_UNKNOWN:
3757 		case FW_PORT_MOD_TYPE_NOTSUPPORTED:
3758 			break;
3759 		case FW_PORT_MOD_TYPE_NONE:
3760 			return (IFM_NONE);
3761 		}
3762 		break;
3763 	case FW_PORT_TYPE_KR4_200G: {
3764 		/*
3765 		 * Pre-T7 firmware used M_FW_PORT_CMD_PTYPE for PORT_TYPE_NONE
3766 		 * and driver needs to deal with both.
3767 		 */
3768 		_Static_assert(M_FW_PORT_CMD_PTYPE == FW_PORT_TYPE_KR4_200G,
3769 		    "driver/firmware mismatch");
3770 		if (chip_id(pi->adapter) < CHELSIO_T7)
3771 			return (IFM_NONE);
3772 		return (IFM_200G_KR4_PAM4);
3773 	}
3774 	case FW_PORT_TYPE_NONE:
3775 		return (IFM_NONE);
3776 	}
3777 
3778 	return (IFM_UNKNOWN);
3779 }
3780 
3781 void
3782 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr)
3783 {
3784 	struct vi_info *vi = if_getsoftc(ifp);
3785 	struct port_info *pi = vi->pi;
3786 	struct adapter *sc = pi->adapter;
3787 	struct link_config *lc = &pi->link_cfg;
3788 
3789 	if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0)
3790 		return;
3791 	PORT_LOCK(pi);
3792 
3793 	if (pi->up_vis == 0 && hw_all_ok(sc)) {
3794 		/*
3795 		 * If all the interfaces are administratively down the firmware
3796 		 * does not report transceiver changes.  Refresh port info here
3797 		 * so that ifconfig displays accurate ifmedia at all times.
3798 		 * This is the only reason we have a synchronized op in this
3799 		 * function.  Just PORT_LOCK would have been enough otherwise.
3800 		 */
3801 		t4_update_port_info(pi);
3802 		build_medialist(pi);
3803 	}
3804 
3805 	/* ifm_status */
3806 	ifmr->ifm_status = IFM_AVALID;
3807 	if (lc->link_ok == false)
3808 		goto done;
3809 	ifmr->ifm_status |= IFM_ACTIVE;
3810 
3811 	/* ifm_active */
3812 	ifmr->ifm_active = IFM_ETHER | IFM_FDX;
3813 	ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
3814 	if (lc->fc & PAUSE_RX)
3815 		ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3816 	if (lc->fc & PAUSE_TX)
3817 		ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3818 	ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
3819 done:
3820 	PORT_UNLOCK(pi);
3821 	end_synchronized_op(sc, 0);
3822 }
3823 
3824 static int
3825 vcxgbe_probe(device_t dev)
3826 {
3827 	struct vi_info *vi = device_get_softc(dev);
3828 
3829 	device_set_descf(dev, "port %d vi %td", vi->pi->port_id,
3830 	    vi - vi->pi->vi);
3831 
3832 	return (BUS_PROBE_DEFAULT);
3833 }
3834 
3835 static int
3836 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
3837 {
3838 	int func, index, rc;
3839 	uint32_t param, val;
3840 
3841 	ASSERT_SYNCHRONIZED_OP(sc);
3842 
3843 	index = vi - pi->vi;
3844 	MPASS(index > 0);	/* This function deals with _extra_ VIs only */
3845 	KASSERT(index < nitems(vi_mac_funcs),
3846 	    ("%s: VI %s doesn't have a MAC func", __func__,
3847 	    device_get_nameunit(vi->dev)));
3848 	func = vi_mac_funcs[index];
3849 	rc = t4_alloc_vi_func(sc, sc->mbox, pi->hw_port, sc->pf, 0, 1,
3850 	    vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
3851 	if (rc < 0) {
3852 		CH_ERR(vi, "failed to allocate virtual interface %d"
3853 		    "for port %d: %d\n", index, pi->port_id, -rc);
3854 		return (-rc);
3855 	}
3856 	vi->viid = rc;
3857 
3858 	if (vi->rss_size == 1) {
3859 		/*
3860 		 * This VI didn't get a slice of the RSS table.  Reduce the
3861 		 * number of VIs being created (hw.cxgbe.num_vis) or modify the
3862 		 * configuration file (nvi, rssnvi for this PF) if this is a
3863 		 * problem.
3864 		 */
3865 		device_printf(vi->dev, "RSS table not available.\n");
3866 		vi->rss_base = 0xffff;
3867 
3868 		return (0);
3869 	}
3870 
3871 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3872 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
3873 	    V_FW_PARAMS_PARAM_YZ(vi->viid);
3874 	rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3875 	if (rc)
3876 		vi->rss_base = 0xffff;
3877 	else {
3878 		MPASS((val >> 16) == vi->rss_size);
3879 		vi->rss_base = val & 0xffff;
3880 	}
3881 
3882 	return (0);
3883 }
3884 
3885 static int
3886 vcxgbe_attach(device_t dev)
3887 {
3888 	struct vi_info *vi;
3889 	struct port_info *pi;
3890 	struct adapter *sc;
3891 	int rc;
3892 
3893 	vi = device_get_softc(dev);
3894 	pi = vi->pi;
3895 	sc = pi->adapter;
3896 
3897 	rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
3898 	if (rc)
3899 		return (rc);
3900 	rc = alloc_extra_vi(sc, pi, vi);
3901 	end_synchronized_op(sc, 0);
3902 	if (rc)
3903 		return (rc);
3904 
3905 	cxgbe_vi_attach(dev, vi);
3906 
3907 	return (0);
3908 }
3909 
3910 static int
3911 vcxgbe_detach(device_t dev)
3912 {
3913 	struct vi_info *vi;
3914 	struct adapter *sc;
3915 
3916 	vi = device_get_softc(dev);
3917 	sc = vi->adapter;
3918 
3919 	begin_vi_detach(sc, vi);
3920 	cxgbe_vi_detach(vi);
3921 	t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3922 	end_vi_detach(sc, vi);
3923 
3924 	return (0);
3925 }
3926 
3927 static struct callout fatal_callout;
3928 static struct taskqueue *reset_tq;
3929 
3930 static void
3931 delayed_panic(void *arg)
3932 {
3933 	struct adapter *sc = arg;
3934 
3935 	panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
3936 }
3937 
3938 static void
3939 fatal_error_task(void *arg, int pending)
3940 {
3941 	struct adapter *sc = arg;
3942 	int rc;
3943 
3944 	if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) {
3945 		dump_cim_regs(sc);
3946 		dump_cimla(sc);
3947 		dump_devlog(sc);
3948 	}
3949 
3950 	if (t4_reset_on_fatal_err) {
3951 		CH_ALERT(sc, "resetting adapter after fatal error.\n");
3952 		rc = reset_adapter(sc);
3953 		if (rc == 0 && t4_panic_on_fatal_err) {
3954 			CH_ALERT(sc, "reset was successful, "
3955 			    "system will NOT panic.\n");
3956 			return;
3957 		}
3958 	}
3959 
3960 	if (t4_panic_on_fatal_err) {
3961 		CH_ALERT(sc, "panicking on fatal error (after 30s).\n");
3962 		callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
3963 	}
3964 }
3965 
3966 void
3967 t4_fatal_err(struct adapter *sc, bool fw_error)
3968 {
3969 	stop_adapter(sc);
3970 	if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR)))
3971 		return;
3972 	if (fw_error) {
3973 		/*
3974 		 * We are here because of a firmware error/timeout and not
3975 		 * because of a hardware interrupt.  It is possible (although
3976 		 * not very likely) that an error interrupt was also raised but
3977 		 * this thread ran first and inhibited t4_intr_err.  We walk the
3978 		 * main INT_CAUSE registers here to make sure we haven't missed
3979 		 * anything interesting.
3980 		 */
3981 		t4_slow_intr_handler(sc, sc->intr_flags);
3982 		atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
3983 	}
3984 	t4_report_fw_error(sc);
3985 	log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n",
3986 	    device_get_nameunit(sc->dev), fw_error);
3987 	taskqueue_enqueue(reset_tq, &sc->fatal_error_task);
3988 }
3989 
3990 void
3991 t4_add_adapter(struct adapter *sc)
3992 {
3993 	sx_xlock(&t4_list_lock);
3994 	SLIST_INSERT_HEAD(&t4_list, sc, link);
3995 	sx_xunlock(&t4_list_lock);
3996 }
3997 
3998 int
3999 t4_map_bars_0_and_4(struct adapter *sc)
4000 {
4001 	sc->regs_rid = PCIR_BAR(0);
4002 	sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4003 	    &sc->regs_rid, RF_ACTIVE);
4004 	if (sc->regs_res == NULL) {
4005 		device_printf(sc->dev, "cannot map registers.\n");
4006 		return (ENXIO);
4007 	}
4008 	sc->mmio_len = rman_get_size(sc->regs_res);
4009 	setbit(&sc->doorbells, DOORBELL_KDB);
4010 
4011 	sc->msix_rid = PCIR_BAR(4);
4012 	sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4013 	    &sc->msix_rid, RF_ACTIVE);
4014 	if (sc->msix_res == NULL) {
4015 		device_printf(sc->dev, "cannot map MSI-X BAR.\n");
4016 		return (ENXIO);
4017 	}
4018 
4019 	return (0);
4020 }
4021 
4022 int
4023 t4_map_bar_2(struct adapter *sc)
4024 {
4025 
4026 	/*
4027 	 * T4: only iWARP driver uses the userspace doorbells.  There is no need
4028 	 * to map it if RDMA is disabled.
4029 	 */
4030 	if (is_t4(sc) && sc->rdmacaps == 0)
4031 		return (0);
4032 
4033 	sc->udbs_rid = PCIR_BAR(2);
4034 	sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4035 	    &sc->udbs_rid, RF_ACTIVE);
4036 	if (sc->udbs_res == NULL) {
4037 		device_printf(sc->dev, "cannot map doorbell BAR.\n");
4038 		return (ENXIO);
4039 	}
4040 	sc->udbs_base = rman_get_virtual(sc->udbs_res);
4041 
4042 	if (chip_id(sc) >= CHELSIO_T5) {
4043 		setbit(&sc->doorbells, DOORBELL_UDB);
4044 #if defined(__i386__) || defined(__amd64__)
4045 		if (t5_write_combine) {
4046 			int rc, mode;
4047 
4048 			/*
4049 			 * Enable write combining on BAR2.  This is the
4050 			 * userspace doorbell BAR and is split into 128B
4051 			 * (UDBS_SEG_SIZE) doorbell regions, each associated
4052 			 * with an egress queue.  The first 64B has the doorbell
4053 			 * and the second 64B can be used to submit a tx work
4054 			 * request with an implicit doorbell.
4055 			 */
4056 
4057 			rc = pmap_change_attr(__DEVOLATILE(void *, sc->udbs_base),
4058 			    rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
4059 			if (rc == 0) {
4060 				clrbit(&sc->doorbells, DOORBELL_UDB);
4061 				setbit(&sc->doorbells, DOORBELL_WCWR);
4062 				setbit(&sc->doorbells, DOORBELL_UDBWC);
4063 			} else {
4064 				device_printf(sc->dev,
4065 				    "couldn't enable write combining: %d\n",
4066 				    rc);
4067 			}
4068 
4069 			mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
4070 			t4_write_reg(sc, A_SGE_STAT_CFG,
4071 			    V_STATSOURCE_T5(7) | mode);
4072 		}
4073 #endif
4074 	}
4075 	sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
4076 
4077 	return (0);
4078 }
4079 
4080 int
4081 t4_adj_doorbells(struct adapter *sc)
4082 {
4083 	if ((sc->doorbells & t4_doorbells_allowed) != 0) {
4084 		sc->doorbells &= t4_doorbells_allowed;
4085 		return (0);
4086 	}
4087 	CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n",
4088 	       sc->doorbells, t4_doorbells_allowed);
4089 	return (EINVAL);
4090 }
4091 
4092 struct memwin_init {
4093 	uint32_t base;
4094 	uint32_t aperture;
4095 };
4096 
4097 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
4098 	{ MEMWIN0_BASE, MEMWIN0_APERTURE },
4099 	{ MEMWIN1_BASE, MEMWIN1_APERTURE },
4100 	{ MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
4101 };
4102 
4103 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
4104 	{ MEMWIN0_BASE, MEMWIN0_APERTURE },
4105 	{ MEMWIN1_BASE, MEMWIN1_APERTURE },
4106 	{ MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
4107 };
4108 
4109 static void
4110 setup_memwin(struct adapter *sc)
4111 {
4112 	const struct memwin_init *mw_init;
4113 	struct memwin *mw;
4114 	int i;
4115 	uint32_t bar0, reg;
4116 
4117 	if (is_t4(sc)) {
4118 		/*
4119 		 * Read low 32b of bar0 indirectly via the hardware backdoor
4120 		 * mechanism.  Works from within PCI passthrough environments
4121 		 * too, where rman_get_start() can return a different value.  We
4122 		 * need to program the T4 memory window decoders with the actual
4123 		 * addresses that will be coming across the PCIe link.
4124 		 */
4125 		bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
4126 		bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
4127 
4128 		mw_init = &t4_memwin[0];
4129 	} else {
4130 		/* T5+ use the relative offset inside the PCIe BAR */
4131 		bar0 = 0;
4132 
4133 		mw_init = &t5_memwin[0];
4134 	}
4135 
4136 	for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
4137 		if (!rw_initialized(&mw->mw_lock)) {
4138 			rw_init(&mw->mw_lock, "memory window access");
4139 			mw->mw_base = mw_init->base;
4140 			mw->mw_aperture = mw_init->aperture;
4141 			mw->mw_curpos = 0;
4142 		}
4143 		reg = chip_id(sc) > CHELSIO_T6 ?
4144 		    PCIE_MEM_ACCESS_T7_REG(A_T7_PCIE_MEM_ACCESS_BASE_WIN, i) :
4145 		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i);
4146 		t4_write_reg(sc, reg, (mw->mw_base + bar0) | V_BIR(0) |
4147 		    V_WINDOW(ilog2(mw->mw_aperture) - 10));
4148 		rw_wlock(&mw->mw_lock);
4149 		position_memwin(sc, i, mw->mw_curpos);
4150 		rw_wunlock(&mw->mw_lock);
4151 	}
4152 
4153 	/* flush */
4154 	t4_read_reg(sc, reg);
4155 }
4156 
4157 /*
4158  * Positions the memory window at the given address in the card's address space.
4159  * There are some alignment requirements and the actual position may be at an
4160  * address prior to the requested address.  mw->mw_curpos always has the actual
4161  * position of the window.
4162  */
4163 static void
4164 position_memwin(struct adapter *sc, int idx, uint32_t addr)
4165 {
4166 	struct memwin *mw;
4167 	uint32_t pf, reg, val;
4168 
4169 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
4170 	mw = &sc->memwin[idx];
4171 	rw_assert(&mw->mw_lock, RA_WLOCKED);
4172 
4173 	if (is_t4(sc)) {
4174 		pf = 0;
4175 		mw->mw_curpos = addr & ~0xf;	/* start must be 16B aligned */
4176 	} else {
4177 		pf = V_PFNUM(sc->pf);
4178 		mw->mw_curpos = addr & ~0x7f;	/* start must be 128B aligned */
4179 	}
4180 	if (chip_id(sc) > CHELSIO_T6) {
4181 		reg = PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, idx);
4182 		val = (mw->mw_curpos >> X_T7_MEMOFST_SHIFT) | pf;
4183 	} else {
4184 		reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
4185 		val = mw->mw_curpos | pf;
4186 	}
4187 	t4_write_reg(sc, reg, val);
4188 	t4_read_reg(sc, reg);	/* flush */
4189 }
4190 
4191 int
4192 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
4193     int len, int rw)
4194 {
4195 	struct memwin *mw;
4196 	uint32_t mw_end, v;
4197 
4198 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
4199 
4200 	/* Memory can only be accessed in naturally aligned 4 byte units */
4201 	if (addr & 3 || len & 3 || len <= 0)
4202 		return (EINVAL);
4203 
4204 	mw = &sc->memwin[idx];
4205 	while (len > 0) {
4206 		rw_rlock(&mw->mw_lock);
4207 		mw_end = mw->mw_curpos + mw->mw_aperture;
4208 		if (addr >= mw_end || addr < mw->mw_curpos) {
4209 			/* Will need to reposition the window */
4210 			if (!rw_try_upgrade(&mw->mw_lock)) {
4211 				rw_runlock(&mw->mw_lock);
4212 				rw_wlock(&mw->mw_lock);
4213 			}
4214 			rw_assert(&mw->mw_lock, RA_WLOCKED);
4215 			position_memwin(sc, idx, addr);
4216 			rw_downgrade(&mw->mw_lock);
4217 			mw_end = mw->mw_curpos + mw->mw_aperture;
4218 		}
4219 		rw_assert(&mw->mw_lock, RA_RLOCKED);
4220 		while (addr < mw_end && len > 0) {
4221 			if (rw == 0) {
4222 				v = t4_read_reg(sc, mw->mw_base + addr -
4223 				    mw->mw_curpos);
4224 				*val++ = le32toh(v);
4225 			} else {
4226 				v = *val++;
4227 				t4_write_reg(sc, mw->mw_base + addr -
4228 				    mw->mw_curpos, htole32(v));
4229 			}
4230 			addr += 4;
4231 			len -= 4;
4232 		}
4233 		rw_runlock(&mw->mw_lock);
4234 	}
4235 
4236 	return (0);
4237 }
4238 
4239 CTASSERT(M_TID_COOKIE == M_COOKIE);
4240 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1));
4241 
4242 static void
4243 t4_init_atid_table(struct adapter *sc)
4244 {
4245 	struct tid_info *t;
4246 	int i;
4247 
4248 	t = &sc->tids;
4249 	if (t->natids == 0)
4250 		return;
4251 
4252 	MPASS(t->atid_tab == NULL);
4253 
4254 	t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
4255 	    M_ZERO | M_WAITOK);
4256 	mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
4257 	t->afree = t->atid_tab;
4258 	t->atids_in_use = 0;
4259 	t->atid_alloc_stopped = false;
4260 	for (i = 1; i < t->natids; i++)
4261 		t->atid_tab[i - 1].next = &t->atid_tab[i];
4262 	t->atid_tab[t->natids - 1].next = NULL;
4263 }
4264 
4265 static void
4266 t4_free_atid_table(struct adapter *sc)
4267 {
4268 	struct tid_info *t;
4269 
4270 	t = &sc->tids;
4271 
4272 	KASSERT(t->atids_in_use == 0,
4273 	    ("%s: %d atids still in use.", __func__, t->atids_in_use));
4274 
4275 	if (mtx_initialized(&t->atid_lock))
4276 		mtx_destroy(&t->atid_lock);
4277 	free(t->atid_tab, M_CXGBE);
4278 	t->atid_tab = NULL;
4279 }
4280 
4281 static void
4282 stop_atid_allocator(struct adapter *sc)
4283 {
4284 	struct tid_info *t = &sc->tids;
4285 
4286 	if (t->natids == 0)
4287 		return;
4288 	mtx_lock(&t->atid_lock);
4289 	t->atid_alloc_stopped = true;
4290 	mtx_unlock(&t->atid_lock);
4291 }
4292 
4293 static void
4294 restart_atid_allocator(struct adapter *sc)
4295 {
4296 	struct tid_info *t = &sc->tids;
4297 
4298 	if (t->natids == 0)
4299 		return;
4300 	mtx_lock(&t->atid_lock);
4301 	KASSERT(t->atids_in_use == 0,
4302 	    ("%s: %d atids still in use.", __func__, t->atids_in_use));
4303 	t->atid_alloc_stopped = false;
4304 	mtx_unlock(&t->atid_lock);
4305 }
4306 
4307 int
4308 alloc_atid(struct adapter *sc, void *ctx)
4309 {
4310 	struct tid_info *t = &sc->tids;
4311 	int atid = -1;
4312 
4313 	mtx_lock(&t->atid_lock);
4314 	if (t->afree && !t->atid_alloc_stopped) {
4315 		union aopen_entry *p = t->afree;
4316 
4317 		atid = p - t->atid_tab;
4318 		MPASS(atid <= M_TID_TID);
4319 		t->afree = p->next;
4320 		p->data = ctx;
4321 		t->atids_in_use++;
4322 	}
4323 	mtx_unlock(&t->atid_lock);
4324 	return (atid);
4325 }
4326 
4327 void *
4328 lookup_atid(struct adapter *sc, int atid)
4329 {
4330 	struct tid_info *t = &sc->tids;
4331 
4332 	return (t->atid_tab[atid].data);
4333 }
4334 
4335 void
4336 free_atid(struct adapter *sc, int atid)
4337 {
4338 	struct tid_info *t = &sc->tids;
4339 	union aopen_entry *p = &t->atid_tab[atid];
4340 
4341 	mtx_lock(&t->atid_lock);
4342 	p->next = t->afree;
4343 	t->afree = p;
4344 	t->atids_in_use--;
4345 	mtx_unlock(&t->atid_lock);
4346 }
4347 
4348 static void
4349 queue_tid_release(struct adapter *sc, int tid)
4350 {
4351 
4352 	CXGBE_UNIMPLEMENTED("deferred tid release");
4353 }
4354 
4355 void
4356 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
4357 {
4358 	struct wrqe *wr;
4359 	struct cpl_tid_release *req;
4360 
4361 	wr = alloc_wrqe(sizeof(*req), ctrlq);
4362 	if (wr == NULL) {
4363 		queue_tid_release(sc, tid);	/* defer */
4364 		return;
4365 	}
4366 	req = wrtod(wr);
4367 
4368 	INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
4369 
4370 	t4_wrq_tx(sc, wr);
4371 }
4372 
4373 static int
4374 t4_range_cmp(const void *a, const void *b)
4375 {
4376 	return ((const struct t4_range *)a)->start -
4377 	       ((const struct t4_range *)b)->start;
4378 }
4379 
4380 /*
4381  * Verify that the memory range specified by the addr/len pair is valid within
4382  * the card's address space.
4383  */
4384 static int
4385 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
4386 {
4387 	struct t4_range mem_ranges[4], *r, *next;
4388 	uint32_t em, addr_len;
4389 	int i, n, remaining;
4390 
4391 	/* Memory can only be accessed in naturally aligned 4 byte units */
4392 	if (addr & 3 || len & 3 || len == 0)
4393 		return (EINVAL);
4394 
4395 	/* Enabled memories */
4396 	em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4397 
4398 	r = &mem_ranges[0];
4399 	n = 0;
4400 	bzero(r, sizeof(mem_ranges));
4401 	if (em & F_EDRAM0_ENABLE) {
4402 		addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4403 		r->size = G_EDRAM0_SIZE(addr_len) << 20;
4404 		if (r->size > 0) {
4405 			r->start = G_EDRAM0_BASE(addr_len) << 20;
4406 			if (addr >= r->start &&
4407 			    addr + len <= r->start + r->size)
4408 				return (0);
4409 			r++;
4410 			n++;
4411 		}
4412 	}
4413 	if (em & F_EDRAM1_ENABLE) {
4414 		addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4415 		r->size = G_EDRAM1_SIZE(addr_len) << 20;
4416 		if (r->size > 0) {
4417 			r->start = G_EDRAM1_BASE(addr_len) << 20;
4418 			if (addr >= r->start &&
4419 			    addr + len <= r->start + r->size)
4420 				return (0);
4421 			r++;
4422 			n++;
4423 		}
4424 	}
4425 	if (em & F_EXT_MEM_ENABLE) {
4426 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4427 		r->size = G_EXT_MEM_SIZE(addr_len) << 20;
4428 		if (r->size > 0) {
4429 			r->start = G_EXT_MEM_BASE(addr_len) << 20;
4430 			if (addr >= r->start &&
4431 			    addr + len <= r->start + r->size)
4432 				return (0);
4433 			r++;
4434 			n++;
4435 		}
4436 	}
4437 	if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
4438 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4439 		r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
4440 		if (r->size > 0) {
4441 			r->start = G_EXT_MEM1_BASE(addr_len) << 20;
4442 			if (addr >= r->start &&
4443 			    addr + len <= r->start + r->size)
4444 				return (0);
4445 			r++;
4446 			n++;
4447 		}
4448 	}
4449 	MPASS(n <= nitems(mem_ranges));
4450 
4451 	if (n > 1) {
4452 		/* Sort and merge the ranges. */
4453 		qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
4454 
4455 		/* Start from index 0 and examine the next n - 1 entries. */
4456 		r = &mem_ranges[0];
4457 		for (remaining = n - 1; remaining > 0; remaining--, r++) {
4458 
4459 			MPASS(r->size > 0);	/* r is a valid entry. */
4460 			next = r + 1;
4461 			MPASS(next->size > 0);	/* and so is the next one. */
4462 
4463 			while (r->start + r->size >= next->start) {
4464 				/* Merge the next one into the current entry. */
4465 				r->size = max(r->start + r->size,
4466 				    next->start + next->size) - r->start;
4467 				n--;	/* One fewer entry in total. */
4468 				if (--remaining == 0)
4469 					goto done;	/* short circuit */
4470 				next++;
4471 			}
4472 			if (next != r + 1) {
4473 				/*
4474 				 * Some entries were merged into r and next
4475 				 * points to the first valid entry that couldn't
4476 				 * be merged.
4477 				 */
4478 				MPASS(next->size > 0);	/* must be valid */
4479 				memcpy(r + 1, next, remaining * sizeof(*r));
4480 #ifdef INVARIANTS
4481 				/*
4482 				 * This so that the foo->size assertion in the
4483 				 * next iteration of the loop do the right
4484 				 * thing for entries that were pulled up and are
4485 				 * no longer valid.
4486 				 */
4487 				MPASS(n < nitems(mem_ranges));
4488 				bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
4489 				    sizeof(struct t4_range));
4490 #endif
4491 			}
4492 		}
4493 done:
4494 		/* Done merging the ranges. */
4495 		MPASS(n > 0);
4496 		r = &mem_ranges[0];
4497 		for (i = 0; i < n; i++, r++) {
4498 			if (addr >= r->start &&
4499 			    addr + len <= r->start + r->size)
4500 				return (0);
4501 		}
4502 	}
4503 
4504 	return (EFAULT);
4505 }
4506 
4507 static int
4508 fwmtype_to_hwmtype(int mtype)
4509 {
4510 
4511 	switch (mtype) {
4512 	case FW_MEMTYPE_EDC0:
4513 		return (MEM_EDC0);
4514 	case FW_MEMTYPE_EDC1:
4515 		return (MEM_EDC1);
4516 	case FW_MEMTYPE_EXTMEM:
4517 		return (MEM_MC0);
4518 	case FW_MEMTYPE_EXTMEM1:
4519 		return (MEM_MC1);
4520 	default:
4521 		panic("%s: cannot translate fw mtype %d.", __func__, mtype);
4522 	}
4523 }
4524 
4525 /*
4526  * Verify that the memory range specified by the memtype/offset/len pair is
4527  * valid and lies entirely within the memtype specified.  The global address of
4528  * the start of the range is returned in addr.
4529  */
4530 static int
4531 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
4532     uint32_t *addr)
4533 {
4534 	uint32_t em, addr_len, maddr;
4535 
4536 	/* Memory can only be accessed in naturally aligned 4 byte units */
4537 	if (off & 3 || len & 3 || len == 0)
4538 		return (EINVAL);
4539 
4540 	em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4541 	switch (fwmtype_to_hwmtype(mtype)) {
4542 	case MEM_EDC0:
4543 		if (!(em & F_EDRAM0_ENABLE))
4544 			return (EINVAL);
4545 		addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4546 		maddr = G_EDRAM0_BASE(addr_len) << 20;
4547 		break;
4548 	case MEM_EDC1:
4549 		if (!(em & F_EDRAM1_ENABLE))
4550 			return (EINVAL);
4551 		addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4552 		maddr = G_EDRAM1_BASE(addr_len) << 20;
4553 		break;
4554 	case MEM_MC:
4555 		if (!(em & F_EXT_MEM_ENABLE))
4556 			return (EINVAL);
4557 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4558 		maddr = G_EXT_MEM_BASE(addr_len) << 20;
4559 		break;
4560 	case MEM_MC1:
4561 		if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
4562 			return (EINVAL);
4563 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4564 		maddr = G_EXT_MEM1_BASE(addr_len) << 20;
4565 		break;
4566 	default:
4567 		return (EINVAL);
4568 	}
4569 
4570 	*addr = maddr + off;	/* global address */
4571 	return (validate_mem_range(sc, *addr, len));
4572 }
4573 
4574 static int
4575 fixup_devlog_ncores_params(struct adapter *sc)
4576 {
4577 	struct devlog_params *dparams = &sc->params.devlog;
4578 	int rc;
4579 
4580 #ifdef INVARIANTS
4581 	if (sc->params.ncores > 1)
4582 		MPASS(chip_id(sc) >= CHELSIO_T7);
4583 #endif
4584 	rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
4585 	    dparams->size, &dparams->addr);
4586 
4587 	return (rc);
4588 }
4589 
4590 static void
4591 update_nirq(struct intrs_and_queues *iaq, int nports)
4592 {
4593 
4594 	iaq->nirq = T4_EXTRA_INTR;
4595 	iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
4596 	iaq->nirq += nports * iaq->nofldrxq;
4597 	iaq->nirq += nports * (iaq->num_vis - 1) *
4598 	    max(iaq->nrxq_vi, iaq->nnmrxq_vi);
4599 	iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
4600 }
4601 
4602 /*
4603  * Adjust requirements to fit the number of interrupts available.
4604  */
4605 static void
4606 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
4607     int navail)
4608 {
4609 	int old_nirq;
4610 	const int nports = sc->params.nports;
4611 
4612 	MPASS(nports > 0);
4613 	MPASS(navail > 0);
4614 
4615 	bzero(iaq, sizeof(*iaq));
4616 	iaq->intr_type = itype;
4617 	iaq->num_vis = t4_num_vis;
4618 	iaq->ntxq = t4_ntxq;
4619 	iaq->ntxq_vi = t4_ntxq_vi;
4620 	iaq->nrxq = t4_nrxq;
4621 	iaq->nrxq_vi = t4_nrxq_vi;
4622 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4623 	if (is_offload(sc) || is_ethoffload(sc)) {
4624 		if (sc->params.tid_qid_sel_mask == 0) {
4625 			iaq->nofldtxq = t4_nofldtxq;
4626 			iaq->nofldtxq_vi = t4_nofldtxq_vi;
4627 		} else {
4628 			iaq->nofldtxq = roundup(t4_nofldtxq, sc->params.ncores);
4629 			iaq->nofldtxq_vi = roundup(t4_nofldtxq_vi,
4630 			    sc->params.ncores);
4631 			if (iaq->nofldtxq != t4_nofldtxq)
4632 				device_printf(sc->dev,
4633 				    "nofldtxq updated (%d -> %d) for correct"
4634 				    " operation with %d firmware cores.\n",
4635 				    t4_nofldtxq, iaq->nofldtxq,
4636 				    sc->params.ncores);
4637 			if (iaq->num_vis > 1 &&
4638 			    iaq->nofldtxq_vi != t4_nofldtxq_vi)
4639 				device_printf(sc->dev,
4640 				    "nofldtxq_vi updated (%d -> %d) for correct"
4641 				    " operation with %d firmware cores.\n",
4642 				    t4_nofldtxq_vi, iaq->nofldtxq_vi,
4643 				    sc->params.ncores);
4644 		}
4645 	}
4646 #endif
4647 #ifdef TCP_OFFLOAD
4648 	if (is_offload(sc)) {
4649 		iaq->nofldrxq = t4_nofldrxq;
4650 		iaq->nofldrxq_vi = t4_nofldrxq_vi;
4651 	}
4652 #endif
4653 #ifdef DEV_NETMAP
4654 	if (t4_native_netmap & NN_MAIN_VI) {
4655 		iaq->nnmtxq = t4_nnmtxq;
4656 		iaq->nnmrxq = t4_nnmrxq;
4657 	}
4658 	if (t4_native_netmap & NN_EXTRA_VI) {
4659 		iaq->nnmtxq_vi = t4_nnmtxq_vi;
4660 		iaq->nnmrxq_vi = t4_nnmrxq_vi;
4661 	}
4662 #endif
4663 
4664 	update_nirq(iaq, nports);
4665 	if (iaq->nirq <= navail &&
4666 	    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4667 		/*
4668 		 * This is the normal case -- there are enough interrupts for
4669 		 * everything.
4670 		 */
4671 		goto done;
4672 	}
4673 
4674 	/*
4675 	 * If extra VIs have been configured try reducing their count and see if
4676 	 * that works.
4677 	 */
4678 	while (iaq->num_vis > 1) {
4679 		iaq->num_vis--;
4680 		update_nirq(iaq, nports);
4681 		if (iaq->nirq <= navail &&
4682 		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4683 			device_printf(sc->dev, "virtual interfaces per port "
4684 			    "reduced to %d from %d.  nrxq=%u, nofldrxq=%u, "
4685 			    "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u.  "
4686 			    "itype %d, navail %u, nirq %d.\n",
4687 			    iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
4688 			    iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
4689 			    itype, navail, iaq->nirq);
4690 			goto done;
4691 		}
4692 	}
4693 
4694 	/*
4695 	 * Extra VIs will not be created.  Log a message if they were requested.
4696 	 */
4697 	MPASS(iaq->num_vis == 1);
4698 	iaq->ntxq_vi = iaq->nrxq_vi = 0;
4699 	iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
4700 	iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
4701 	if (iaq->num_vis != t4_num_vis) {
4702 		device_printf(sc->dev, "extra virtual interfaces disabled.  "
4703 		    "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
4704 		    "nnmrxq_vi=%u.  itype %d, navail %u, nirq %d.\n",
4705 		    iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
4706 		    iaq->nnmrxq_vi, itype, navail, iaq->nirq);
4707 	}
4708 
4709 	/*
4710 	 * Keep reducing the number of NIC rx queues to the next lower power of
4711 	 * 2 (for even RSS distribution) and halving the TOE rx queues and see
4712 	 * if that works.
4713 	 */
4714 	do {
4715 		if (iaq->nrxq > 1) {
4716 			iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1);
4717 			if (iaq->nnmrxq > iaq->nrxq)
4718 				iaq->nnmrxq = iaq->nrxq;
4719 		}
4720 		if (iaq->nofldrxq > 1)
4721 			iaq->nofldrxq >>= 1;
4722 
4723 		old_nirq = iaq->nirq;
4724 		update_nirq(iaq, nports);
4725 		if (iaq->nirq <= navail &&
4726 		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4727 			device_printf(sc->dev, "running with reduced number of "
4728 			    "rx queues because of shortage of interrupts.  "
4729 			    "nrxq=%u, nofldrxq=%u.  "
4730 			    "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
4731 			    iaq->nofldrxq, itype, navail, iaq->nirq);
4732 			goto done;
4733 		}
4734 	} while (old_nirq != iaq->nirq);
4735 
4736 	/* One interrupt for everything.  Ugh. */
4737 	device_printf(sc->dev, "running with minimal number of queues.  "
4738 	    "itype %d, navail %u.\n", itype, navail);
4739 	iaq->nirq = 1;
4740 	iaq->nrxq = 1;
4741 	iaq->ntxq = 1;
4742 	if (iaq->nofldrxq > 0) {
4743 		iaq->nofldrxq = 1;
4744 		iaq->nofldtxq = 1;
4745 		if (sc->params.tid_qid_sel_mask == 0)
4746 			iaq->nofldtxq = 1;
4747 		else
4748 			iaq->nofldtxq = sc->params.ncores;
4749 	}
4750 	iaq->nnmtxq = 0;
4751 	iaq->nnmrxq = 0;
4752 done:
4753 	MPASS(iaq->num_vis > 0);
4754 	if (iaq->num_vis > 1) {
4755 		MPASS(iaq->nrxq_vi > 0);
4756 		MPASS(iaq->ntxq_vi > 0);
4757 	}
4758 	MPASS(iaq->nirq > 0);
4759 	MPASS(iaq->nrxq > 0);
4760 	MPASS(iaq->ntxq > 0);
4761 	if (itype == INTR_MSI)
4762 		MPASS(powerof2(iaq->nirq));
4763 	if (sc->params.tid_qid_sel_mask != 0)
4764 		MPASS(iaq->nofldtxq % sc->params.ncores == 0);
4765 }
4766 
4767 static int
4768 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
4769 {
4770 	int rc, itype, navail, nalloc;
4771 
4772 	for (itype = INTR_MSIX; itype; itype >>= 1) {
4773 
4774 		if ((itype & t4_intr_types) == 0)
4775 			continue;	/* not allowed */
4776 
4777 		if (itype == INTR_MSIX)
4778 			navail = pci_msix_count(sc->dev);
4779 		else if (itype == INTR_MSI)
4780 			navail = pci_msi_count(sc->dev);
4781 		else
4782 			navail = 1;
4783 restart:
4784 		if (navail == 0)
4785 			continue;
4786 
4787 		calculate_iaq(sc, iaq, itype, navail);
4788 		nalloc = iaq->nirq;
4789 		rc = 0;
4790 		if (itype == INTR_MSIX)
4791 			rc = pci_alloc_msix(sc->dev, &nalloc);
4792 		else if (itype == INTR_MSI)
4793 			rc = pci_alloc_msi(sc->dev, &nalloc);
4794 
4795 		if (rc == 0 && nalloc > 0) {
4796 			if (nalloc == iaq->nirq)
4797 				return (0);
4798 
4799 			/*
4800 			 * Didn't get the number requested.  Use whatever number
4801 			 * the kernel is willing to allocate.
4802 			 */
4803 			device_printf(sc->dev, "fewer vectors than requested, "
4804 			    "type=%d, req=%d, rcvd=%d; will downshift req.\n",
4805 			    itype, iaq->nirq, nalloc);
4806 			pci_release_msi(sc->dev);
4807 			navail = nalloc;
4808 			goto restart;
4809 		}
4810 
4811 		device_printf(sc->dev,
4812 		    "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
4813 		    itype, rc, iaq->nirq, nalloc);
4814 	}
4815 
4816 	device_printf(sc->dev,
4817 	    "failed to find a usable interrupt type.  "
4818 	    "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
4819 	    pci_msix_count(sc->dev), pci_msi_count(sc->dev));
4820 
4821 	return (ENXIO);
4822 }
4823 
4824 #define FW_VERSION(chip) ( \
4825     V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
4826     V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
4827     V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
4828     V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
4829 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
4830 
4831 /* Just enough of fw_hdr to cover all version info. */
4832 struct fw_h {
4833 	__u8	ver;
4834 	__u8	chip;
4835 	__be16	len512;
4836 	__be32	fw_ver;
4837 	__be32	tp_microcode_ver;
4838 	__u8	intfver_nic;
4839 	__u8	intfver_vnic;
4840 	__u8	intfver_ofld;
4841 	__u8	intfver_ri;
4842 	__u8	intfver_iscsipdu;
4843 	__u8	intfver_iscsi;
4844 	__u8	intfver_fcoepdu;
4845 	__u8	intfver_fcoe;
4846 };
4847 /* Spot check a couple of fields. */
4848 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
4849 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
4850 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
4851 
4852 struct fw_info {
4853 	uint8_t chip;
4854 	char *kld_name;
4855 	char *fw_mod_name;
4856 	struct fw_h fw_h;
4857 } fw_info[] = {
4858 	{
4859 		.chip = CHELSIO_T4,
4860 		.kld_name = "t4fw_cfg",
4861 		.fw_mod_name = "t4fw",
4862 		.fw_h = {
4863 			.chip = FW_HDR_CHIP_T4,
4864 			.fw_ver = htobe32(FW_VERSION(T4)),
4865 			.intfver_nic = FW_INTFVER(T4, NIC),
4866 			.intfver_vnic = FW_INTFVER(T4, VNIC),
4867 			.intfver_ofld = FW_INTFVER(T4, OFLD),
4868 			.intfver_ri = FW_INTFVER(T4, RI),
4869 			.intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
4870 			.intfver_iscsi = FW_INTFVER(T4, ISCSI),
4871 			.intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
4872 			.intfver_fcoe = FW_INTFVER(T4, FCOE),
4873 		},
4874 	}, {
4875 		.chip = CHELSIO_T5,
4876 		.kld_name = "t5fw_cfg",
4877 		.fw_mod_name = "t5fw",
4878 		.fw_h = {
4879 			.chip = FW_HDR_CHIP_T5,
4880 			.fw_ver = htobe32(FW_VERSION(T5)),
4881 			.intfver_nic = FW_INTFVER(T5, NIC),
4882 			.intfver_vnic = FW_INTFVER(T5, VNIC),
4883 			.intfver_ofld = FW_INTFVER(T5, OFLD),
4884 			.intfver_ri = FW_INTFVER(T5, RI),
4885 			.intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
4886 			.intfver_iscsi = FW_INTFVER(T5, ISCSI),
4887 			.intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
4888 			.intfver_fcoe = FW_INTFVER(T5, FCOE),
4889 		},
4890 	}, {
4891 		.chip = CHELSIO_T6,
4892 		.kld_name = "t6fw_cfg",
4893 		.fw_mod_name = "t6fw",
4894 		.fw_h = {
4895 			.chip = FW_HDR_CHIP_T6,
4896 			.fw_ver = htobe32(FW_VERSION(T6)),
4897 			.intfver_nic = FW_INTFVER(T6, NIC),
4898 			.intfver_vnic = FW_INTFVER(T6, VNIC),
4899 			.intfver_ofld = FW_INTFVER(T6, OFLD),
4900 			.intfver_ri = FW_INTFVER(T6, RI),
4901 			.intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4902 			.intfver_iscsi = FW_INTFVER(T6, ISCSI),
4903 			.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4904 			.intfver_fcoe = FW_INTFVER(T6, FCOE),
4905 		},
4906 	}, {
4907 		.chip = CHELSIO_T7,
4908 		.kld_name = "t7fw_cfg",
4909 		.fw_mod_name = "t7fw",
4910 		.fw_h = {
4911 			.chip = FW_HDR_CHIP_T7,
4912 			.fw_ver = htobe32(FW_VERSION(T7)),
4913 			.intfver_nic = FW_INTFVER(T7, NIC),
4914 			.intfver_vnic = FW_INTFVER(T7, VNIC),
4915 			.intfver_ofld = FW_INTFVER(T7, OFLD),
4916 			.intfver_ri = FW_INTFVER(T7, RI),
4917 			.intfver_iscsipdu = FW_INTFVER(T7, ISCSIPDU),
4918 			.intfver_iscsi = FW_INTFVER(T7, ISCSI),
4919 			.intfver_fcoepdu = FW_INTFVER(T7, FCOEPDU),
4920 			.intfver_fcoe = FW_INTFVER(T7, FCOE),
4921 		},
4922 	}
4923 };
4924 
4925 static struct fw_info *
4926 find_fw_info(int chip)
4927 {
4928 	int i;
4929 
4930 	for (i = 0; i < nitems(fw_info); i++) {
4931 		if (fw_info[i].chip == chip)
4932 			return (&fw_info[i]);
4933 	}
4934 	return (NULL);
4935 }
4936 
4937 /*
4938  * Is the given firmware API compatible with the one the driver was compiled
4939  * with?
4940  */
4941 static int
4942 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
4943 {
4944 
4945 	/* short circuit if it's the exact same firmware version */
4946 	if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
4947 		return (1);
4948 
4949 	/*
4950 	 * XXX: Is this too conservative?  Perhaps I should limit this to the
4951 	 * features that are supported in the driver.
4952 	 */
4953 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
4954 	if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
4955 	    SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
4956 	    SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
4957 		return (1);
4958 #undef SAME_INTF
4959 
4960 	return (0);
4961 }
4962 
4963 static int
4964 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
4965     const struct firmware **fw)
4966 {
4967 	struct fw_info *fw_info;
4968 
4969 	*dcfg = NULL;
4970 	if (fw != NULL)
4971 		*fw = NULL;
4972 
4973 	fw_info = find_fw_info(chip_id(sc));
4974 	if (fw_info == NULL) {
4975 		device_printf(sc->dev,
4976 		    "unable to look up firmware information for chip %d.\n",
4977 		    chip_id(sc));
4978 		return (EINVAL);
4979 	}
4980 
4981 	*dcfg = firmware_get(fw_info->kld_name);
4982 	if (*dcfg != NULL) {
4983 		if (fw != NULL)
4984 			*fw = firmware_get(fw_info->fw_mod_name);
4985 		return (0);
4986 	}
4987 
4988 	return (ENOENT);
4989 }
4990 
4991 static void
4992 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
4993     const struct firmware *fw)
4994 {
4995 
4996 	if (fw != NULL)
4997 		firmware_put(fw, FIRMWARE_UNLOAD);
4998 	if (dcfg != NULL)
4999 		firmware_put(dcfg, FIRMWARE_UNLOAD);
5000 }
5001 
5002 /*
5003  * Return values:
5004  * 0 means no firmware install attempted.
5005  * ERESTART means a firmware install was attempted and was successful.
5006  * +ve errno means a firmware install was attempted but failed.
5007  */
5008 static int
5009 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
5010     const struct fw_h *drv_fw, const char *reason, int *already)
5011 {
5012 	const struct firmware *cfg, *fw;
5013 	const uint32_t c = be32toh(card_fw->fw_ver);
5014 	uint32_t d, k;
5015 	int rc, fw_install;
5016 	struct fw_h bundled_fw;
5017 	bool load_attempted;
5018 
5019 	cfg = fw = NULL;
5020 	load_attempted = false;
5021 	fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
5022 
5023 	memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
5024 	if (t4_fw_install < 0) {
5025 		rc = load_fw_module(sc, &cfg, &fw);
5026 		if (rc != 0 || fw == NULL) {
5027 			device_printf(sc->dev,
5028 			    "failed to load firmware module: %d. cfg %p, fw %p;"
5029 			    " will use compiled-in firmware version for"
5030 			    "hw.cxgbe.fw_install checks.\n",
5031 			    rc, cfg, fw);
5032 		} else {
5033 			memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
5034 		}
5035 		load_attempted = true;
5036 	}
5037 	d = be32toh(bundled_fw.fw_ver);
5038 
5039 	if (reason != NULL)
5040 		goto install;
5041 
5042 	if ((sc->flags & FW_OK) == 0) {
5043 
5044 		if (c == 0xffffffff) {
5045 			reason = "missing";
5046 			goto install;
5047 		}
5048 
5049 		rc = 0;
5050 		goto done;
5051 	}
5052 
5053 	if (!fw_compatible(card_fw, &bundled_fw)) {
5054 		reason = "incompatible or unusable";
5055 		goto install;
5056 	}
5057 
5058 	if (d > c) {
5059 		reason = "older than the version bundled with this driver";
5060 		goto install;
5061 	}
5062 
5063 	if (fw_install == 2 && d != c) {
5064 		reason = "different than the version bundled with this driver";
5065 		goto install;
5066 	}
5067 
5068 	/* No reason to do anything to the firmware already on the card. */
5069 	rc = 0;
5070 	goto done;
5071 
5072 install:
5073 	rc = 0;
5074 	if ((*already)++)
5075 		goto done;
5076 
5077 	if (fw_install == 0) {
5078 		device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5079 		    "but the driver is prohibited from installing a firmware "
5080 		    "on the card.\n",
5081 		    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5082 		    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
5083 
5084 		goto done;
5085 	}
5086 
5087 	/*
5088 	 * We'll attempt to install a firmware.  Load the module first (if it
5089 	 * hasn't been loaded already).
5090 	 */
5091 	if (!load_attempted) {
5092 		rc = load_fw_module(sc, &cfg, &fw);
5093 		if (rc != 0 || fw == NULL) {
5094 			device_printf(sc->dev,
5095 			    "failed to load firmware module: %d. cfg %p, fw %p\n",
5096 			    rc, cfg, fw);
5097 			/* carry on */
5098 		}
5099 	}
5100 	if (fw == NULL) {
5101 		device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5102 		    "but the driver cannot take corrective action because it "
5103 		    "is unable to load the firmware module.\n",
5104 		    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5105 		    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
5106 		rc = sc->flags & FW_OK ? 0 : ENOENT;
5107 		goto done;
5108 	}
5109 	k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
5110 	if (k != d) {
5111 		MPASS(t4_fw_install > 0);
5112 		device_printf(sc->dev,
5113 		    "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
5114 		    "expecting (%u.%u.%u.%u) and will not be used.\n",
5115 		    G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
5116 		    G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
5117 		    G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
5118 		    G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
5119 		rc = sc->flags & FW_OK ? 0 : EINVAL;
5120 		goto done;
5121 	}
5122 
5123 	device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5124 	    "installing firmware %u.%u.%u.%u on card.\n",
5125 	    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5126 	    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
5127 	    G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
5128 	    G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
5129 
5130 	rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
5131 	if (rc != 0) {
5132 		device_printf(sc->dev, "failed to install firmware: %d\n", rc);
5133 	} else {
5134 		/* Installed successfully, update the cached header too. */
5135 		rc = ERESTART;
5136 		memcpy(card_fw, fw->data, sizeof(*card_fw));
5137 	}
5138 done:
5139 	unload_fw_module(sc, cfg, fw);
5140 
5141 	return (rc);
5142 }
5143 
5144 /*
5145  * Establish contact with the firmware and attempt to become the master driver.
5146  *
5147  * A firmware will be installed to the card if needed (if the driver is allowed
5148  * to do so).
5149  */
5150 static int
5151 contact_firmware(struct adapter *sc)
5152 {
5153 	int rc, already = 0;
5154 	enum dev_state state;
5155 	struct fw_info *fw_info;
5156 	struct fw_hdr *card_fw;		/* fw on the card */
5157 	const struct fw_h *drv_fw;
5158 
5159 	fw_info = find_fw_info(chip_id(sc));
5160 	if (fw_info == NULL) {
5161 		device_printf(sc->dev,
5162 		    "unable to look up firmware information for chip %d.\n",
5163 		    chip_id(sc));
5164 		return (EINVAL);
5165 	}
5166 	drv_fw = &fw_info->fw_h;
5167 
5168 	/* Read the header of the firmware on the card */
5169 	card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
5170 restart:
5171 	rc = -t4_get_fw_hdr(sc, card_fw);
5172 	if (rc != 0) {
5173 		device_printf(sc->dev,
5174 		    "unable to read firmware header from card's flash: %d\n",
5175 		    rc);
5176 		goto done;
5177 	}
5178 
5179 	rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
5180 	    &already);
5181 	if (rc == ERESTART)
5182 		goto restart;
5183 	if (rc != 0)
5184 		goto done;
5185 
5186 	rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
5187 	if (rc < 0 || state == DEV_STATE_ERR) {
5188 		rc = -rc;
5189 		device_printf(sc->dev,
5190 		    "failed to connect to the firmware: %d, %d.  "
5191 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5192 #if 0
5193 		if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
5194 		    "not responding properly to HELLO", &already) == ERESTART)
5195 			goto restart;
5196 #endif
5197 		goto done;
5198 	}
5199 	MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
5200 	sc->flags |= FW_OK;	/* The firmware responded to the FW_HELLO. */
5201 
5202 	if (rc == sc->pf) {
5203 		sc->flags |= MASTER_PF;
5204 		rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
5205 		    NULL, &already);
5206 		if (rc == ERESTART)
5207 			rc = 0;
5208 		else if (rc != 0)
5209 			goto done;
5210 	} else if (state == DEV_STATE_UNINIT) {
5211 		/*
5212 		 * We didn't get to be the master so we definitely won't be
5213 		 * configuring the chip.  It's a bug if someone else hasn't
5214 		 * configured it already.
5215 		 */
5216 		device_printf(sc->dev, "couldn't be master(%d), "
5217 		    "device not already initialized either(%d).  "
5218 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5219 		rc = EPROTO;
5220 		goto done;
5221 	} else {
5222 		/*
5223 		 * Some other PF is the master and has configured the chip.
5224 		 * This is allowed but untested.
5225 		 */
5226 		device_printf(sc->dev, "PF%d is master, device state %d.  "
5227 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5228 		snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
5229 		sc->cfcsum = 0;
5230 		rc = 0;
5231 	}
5232 done:
5233 	if (rc != 0 && sc->flags & FW_OK) {
5234 		t4_fw_bye(sc, sc->mbox);
5235 		sc->flags &= ~FW_OK;
5236 	}
5237 	free(card_fw, M_CXGBE);
5238 	return (rc);
5239 }
5240 
5241 static int
5242 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
5243     uint32_t mtype, uint32_t moff, u_int maxlen)
5244 {
5245 	struct fw_info *fw_info;
5246 	const struct firmware *dcfg, *rcfg = NULL;
5247 	const uint32_t *cfdata;
5248 	uint32_t cflen, addr;
5249 	int rc;
5250 
5251 	load_fw_module(sc, &dcfg, NULL);
5252 
5253 	/* Card specific interpretation of "default". */
5254 	if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
5255 		if (pci_get_device(sc->dev) == 0x440a)
5256 			snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
5257 		if (is_fpga(sc))
5258 			snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
5259 	}
5260 
5261 	if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
5262 		if (dcfg == NULL) {
5263 			device_printf(sc->dev,
5264 			    "KLD with default config is not available.\n");
5265 			rc = ENOENT;
5266 			goto done;
5267 		}
5268 		cfdata = dcfg->data;
5269 		cflen = dcfg->datasize & ~3;
5270 	} else {
5271 		char s[32];
5272 
5273 		fw_info = find_fw_info(chip_id(sc));
5274 		if (fw_info == NULL) {
5275 			device_printf(sc->dev,
5276 			    "unable to look up firmware information for chip %d.\n",
5277 			    chip_id(sc));
5278 			rc = EINVAL;
5279 			goto done;
5280 		}
5281 		snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
5282 
5283 		rcfg = firmware_get(s);
5284 		if (rcfg == NULL) {
5285 			device_printf(sc->dev,
5286 			    "unable to load module \"%s\" for configuration "
5287 			    "profile \"%s\".\n", s, cfg_file);
5288 			rc = ENOENT;
5289 			goto done;
5290 		}
5291 		cfdata = rcfg->data;
5292 		cflen = rcfg->datasize & ~3;
5293 	}
5294 
5295 	if (cflen > maxlen) {
5296 		device_printf(sc->dev,
5297 		    "config file too long (%d, max allowed is %d).\n",
5298 		    cflen, maxlen);
5299 		rc = EINVAL;
5300 		goto done;
5301 	}
5302 
5303 	rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
5304 	if (rc != 0) {
5305 		device_printf(sc->dev,
5306 		    "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
5307 		    __func__, mtype, moff, cflen, rc);
5308 		rc = EINVAL;
5309 		goto done;
5310 	}
5311 	write_via_memwin(sc, 2, addr, cfdata, cflen);
5312 done:
5313 	if (rcfg != NULL)
5314 		firmware_put(rcfg, FIRMWARE_UNLOAD);
5315 	unload_fw_module(sc, dcfg, NULL);
5316 	return (rc);
5317 }
5318 
5319 struct caps_allowed {
5320 	uint16_t nbmcaps;
5321 	uint16_t linkcaps;
5322 	uint16_t switchcaps;
5323 	uint16_t nvmecaps;
5324 	uint16_t niccaps;
5325 	uint16_t toecaps;
5326 	uint16_t rdmacaps;
5327 	uint16_t cryptocaps;
5328 	uint16_t iscsicaps;
5329 	uint16_t fcoecaps;
5330 };
5331 
5332 #define FW_PARAM_DEV(param) \
5333 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5334 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5335 #define FW_PARAM_PFVF(param) \
5336 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5337 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
5338 
5339 /*
5340  * Provide a configuration profile to the firmware and have it initialize the
5341  * chip accordingly.  This may involve uploading a configuration file to the
5342  * card.
5343  */
5344 static int
5345 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
5346     const struct caps_allowed *caps_allowed)
5347 {
5348 	int rc;
5349 	struct fw_caps_config_cmd caps;
5350 	uint32_t mtype, moff, finicsum, cfcsum, param, val;
5351 	unsigned int maxlen = 0;
5352 	const int cfg_addr = t4_flash_cfg_addr(sc, &maxlen);
5353 
5354 	rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
5355 	if (rc != 0) {
5356 		device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
5357 		return (rc);
5358 	}
5359 
5360 	bzero(&caps, sizeof(caps));
5361 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5362 	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
5363 	if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
5364 		mtype = 0;
5365 		moff = 0;
5366 		caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5367 	} else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
5368 		mtype = FW_MEMTYPE_FLASH;
5369 		moff = cfg_addr;
5370 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5371 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5372 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5373 		    FW_LEN16(caps));
5374 	} else {
5375 		/*
5376 		 * Ask the firmware where it wants us to upload the config file.
5377 		 */
5378 		param = FW_PARAM_DEV(CF);
5379 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5380 		if (rc != 0) {
5381 			/* No support for config file?  Shouldn't happen. */
5382 			device_printf(sc->dev,
5383 			    "failed to query config file location: %d.\n", rc);
5384 			goto done;
5385 		}
5386 		mtype = G_FW_PARAMS_PARAM_Y(val);
5387 		moff = G_FW_PARAMS_PARAM_Z(val) << 16;
5388 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5389 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5390 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5391 		    FW_LEN16(caps));
5392 
5393 		rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff, maxlen);
5394 		if (rc != 0) {
5395 			device_printf(sc->dev,
5396 			    "failed to upload config file to card: %d.\n", rc);
5397 			goto done;
5398 		}
5399 	}
5400 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5401 	if (rc != 0) {
5402 		device_printf(sc->dev, "failed to pre-process config file: %d "
5403 		    "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
5404 		goto done;
5405 	}
5406 
5407 	finicsum = be32toh(caps.finicsum);
5408 	cfcsum = be32toh(caps.cfcsum);	/* actual */
5409 	if (finicsum != cfcsum) {
5410 		device_printf(sc->dev,
5411 		    "WARNING: config file checksum mismatch: %08x %08x\n",
5412 		    finicsum, cfcsum);
5413 	}
5414 	sc->cfcsum = cfcsum;
5415 	snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
5416 
5417 	/*
5418 	 * Let the firmware know what features will (not) be used so it can tune
5419 	 * things accordingly.
5420 	 */
5421 #define LIMIT_CAPS(x) do { \
5422 	caps.x##caps &= htobe16(caps_allowed->x##caps); \
5423 } while (0)
5424 	LIMIT_CAPS(nbm);
5425 	LIMIT_CAPS(link);
5426 	LIMIT_CAPS(switch);
5427 	LIMIT_CAPS(nvme);
5428 	LIMIT_CAPS(nic);
5429 	LIMIT_CAPS(toe);
5430 	LIMIT_CAPS(rdma);
5431 	LIMIT_CAPS(crypto);
5432 	LIMIT_CAPS(iscsi);
5433 	LIMIT_CAPS(fcoe);
5434 #undef LIMIT_CAPS
5435 	if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
5436 		/*
5437 		 * TOE and hashfilters are mutually exclusive.  It is a config
5438 		 * file or firmware bug if both are reported as available.  Try
5439 		 * to cope with the situation in non-debug builds by disabling
5440 		 * TOE.
5441 		 */
5442 		MPASS(caps.toecaps == 0);
5443 
5444 		caps.toecaps = 0;
5445 		caps.rdmacaps = 0;
5446 		caps.iscsicaps = 0;
5447 		caps.nvmecaps = 0;
5448 	}
5449 
5450 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5451 	    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5452 	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5453 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
5454 	if (rc != 0) {
5455 		device_printf(sc->dev,
5456 		    "failed to process config file: %d.\n", rc);
5457 		goto done;
5458 	}
5459 
5460 	t4_tweak_chip_settings(sc);
5461 	set_params__pre_init(sc);
5462 
5463 	/* get basic stuff going */
5464 	rc = -t4_fw_initialize(sc, sc->mbox);
5465 	if (rc != 0) {
5466 		device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
5467 		goto done;
5468 	}
5469 done:
5470 	return (rc);
5471 }
5472 
5473 /*
5474  * Partition chip resources for use between various PFs, VFs, etc.
5475  */
5476 static int
5477 partition_resources(struct adapter *sc)
5478 {
5479 	char cfg_file[sizeof(t4_cfg_file)];
5480 	struct caps_allowed caps_allowed;
5481 	int rc;
5482 	bool fallback;
5483 
5484 	/* Only the master driver gets to configure the chip resources. */
5485 	MPASS(sc->flags & MASTER_PF);
5486 
5487 #define COPY_CAPS(x) do { \
5488 	caps_allowed.x##caps = t4_##x##caps_allowed; \
5489 } while (0)
5490 	bzero(&caps_allowed, sizeof(caps_allowed));
5491 	COPY_CAPS(nbm);
5492 	COPY_CAPS(link);
5493 	COPY_CAPS(switch);
5494 	COPY_CAPS(nvme);
5495 	COPY_CAPS(nic);
5496 	COPY_CAPS(toe);
5497 	COPY_CAPS(rdma);
5498 	COPY_CAPS(crypto);
5499 	COPY_CAPS(iscsi);
5500 	COPY_CAPS(fcoe);
5501 	fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
5502 	snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
5503 retry:
5504 	rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
5505 	if (rc != 0 && fallback) {
5506 		dump_devlog(sc);
5507 		device_printf(sc->dev,
5508 		    "failed (%d) to configure card with \"%s\" profile, "
5509 		    "will fall back to a basic configuration and retry.\n",
5510 		    rc, cfg_file);
5511 		snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
5512 		bzero(&caps_allowed, sizeof(caps_allowed));
5513 		COPY_CAPS(switch);
5514 		caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
5515 		fallback = false;
5516 		goto retry;
5517 	}
5518 #undef COPY_CAPS
5519 	return (rc);
5520 }
5521 
5522 /*
5523  * Retrieve parameters that are needed (or nice to have) very early.
5524  */
5525 static int
5526 get_params__pre_init(struct adapter *sc)
5527 {
5528 	int rc;
5529 	uint32_t param[2], val[2];
5530 
5531 	t4_get_version_info(sc);
5532 
5533 	snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
5534 	    G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
5535 	    G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
5536 	    G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
5537 	    G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
5538 
5539 	snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
5540 	    G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
5541 	    G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
5542 	    G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
5543 	    G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
5544 
5545 	snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
5546 	    G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
5547 	    G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
5548 	    G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
5549 	    G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
5550 
5551 	snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
5552 	    G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
5553 	    G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
5554 	    G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
5555 	    G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
5556 
5557 	param[0] = FW_PARAM_DEV(PORTVEC);
5558 	param[1] = FW_PARAM_DEV(CCLK);
5559 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5560 	if (rc != 0) {
5561 		device_printf(sc->dev,
5562 		    "failed to query parameters (pre_init): %d.\n", rc);
5563 		return (rc);
5564 	}
5565 
5566 	sc->params.portvec = val[0];
5567 	sc->params.nports = bitcount32(val[0]);
5568 	sc->params.vpd.cclk = val[1];
5569 
5570 	/* Read device log parameters. */
5571 	rc = -t4_init_devlog_ncores_params(sc, 1);
5572 	if (rc == 0)
5573 		fixup_devlog_ncores_params(sc);
5574 	else {
5575 		device_printf(sc->dev,
5576 		    "failed to get devlog parameters: %d.\n", rc);
5577 		rc = 0;	/* devlog isn't critical for device operation */
5578 	}
5579 
5580 	return (rc);
5581 }
5582 
5583 /*
5584  * Any params that need to be set before FW_INITIALIZE.
5585  */
5586 static int
5587 set_params__pre_init(struct adapter *sc)
5588 {
5589 	int rc = 0;
5590 	uint32_t param, val;
5591 
5592 	if (chip_id(sc) >= CHELSIO_T6) {
5593 		param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
5594 		val = 1;
5595 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5596 		/* firmwares < 1.20.1.0 do not have this param. */
5597 		if (rc == FW_EINVAL &&
5598 		    sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
5599 			rc = 0;
5600 		}
5601 		if (rc != 0) {
5602 			device_printf(sc->dev,
5603 			    "failed to enable high priority filters :%d.\n",
5604 			    rc);
5605 		}
5606 
5607 		param = FW_PARAM_DEV(PPOD_EDRAM);
5608 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5609 		if (rc == 0 && val == 1) {
5610 			rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param,
5611 			    &val);
5612 			if (rc != 0) {
5613 				device_printf(sc->dev,
5614 				    "failed to set PPOD_EDRAM: %d.\n", rc);
5615 			}
5616 		}
5617 	}
5618 
5619 	/* Enable opaque VIIDs with firmwares that support it. */
5620 	param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
5621 	val = 1;
5622 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5623 	if (rc == 0 && val == 1)
5624 		sc->params.viid_smt_extn_support = true;
5625 	else
5626 		sc->params.viid_smt_extn_support = false;
5627 
5628 	return (rc);
5629 }
5630 
5631 /*
5632  * Retrieve various parameters that are of interest to the driver.  The device
5633  * has been initialized by the firmware at this point.
5634  */
5635 static int
5636 get_params__post_init(struct adapter *sc)
5637 {
5638 	int rc;
5639 	uint32_t param[7], val[7];
5640 	struct fw_caps_config_cmd caps;
5641 
5642 	param[0] = FW_PARAM_PFVF(IQFLINT_START);
5643 	param[1] = FW_PARAM_PFVF(EQ_START);
5644 	param[2] = FW_PARAM_PFVF(FILTER_START);
5645 	param[3] = FW_PARAM_PFVF(FILTER_END);
5646 	param[4] = FW_PARAM_PFVF(L2T_START);
5647 	param[5] = FW_PARAM_PFVF(L2T_END);
5648 	param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5649 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5650 	    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
5651 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
5652 	if (rc != 0) {
5653 		device_printf(sc->dev,
5654 		    "failed to query parameters (post_init): %d.\n", rc);
5655 		return (rc);
5656 	}
5657 
5658 	sc->sge.iq_start = val[0];
5659 	sc->sge.eq_start = val[1];
5660 	if ((int)val[3] > (int)val[2]) {
5661 		sc->tids.ftid_base = val[2];
5662 		sc->tids.ftid_end = val[3];
5663 		sc->tids.nftids = val[3] - val[2] + 1;
5664 	}
5665 	sc->vres.l2t.start = val[4];
5666 	sc->vres.l2t.size = val[5] - val[4] + 1;
5667 	/* val[5] is the last hwidx and it must not collide with F_SYNC_WR */
5668 	if (sc->vres.l2t.size > 0)
5669 		MPASS(fls(val[5]) <= S_SYNC_WR);
5670 	sc->params.core_vdd = val[6];
5671 
5672 	param[0] = FW_PARAM_PFVF(IQFLINT_END);
5673 	param[1] = FW_PARAM_PFVF(EQ_END);
5674 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5675 	if (rc != 0) {
5676 		device_printf(sc->dev,
5677 		    "failed to query parameters (post_init2): %d.\n", rc);
5678 		return (rc);
5679 	}
5680 	MPASS((int)val[0] >= sc->sge.iq_start);
5681 	sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1;
5682 	MPASS((int)val[1] >= sc->sge.eq_start);
5683 	sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1;
5684 
5685 	if (chip_id(sc) >= CHELSIO_T6) {
5686 
5687 		sc->tids.tid_base = t4_read_reg(sc,
5688 		    A_LE_DB_ACTIVE_TABLE_START_INDEX);
5689 
5690 		param[0] = FW_PARAM_PFVF(HPFILTER_START);
5691 		param[1] = FW_PARAM_PFVF(HPFILTER_END);
5692 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5693 		if (rc != 0) {
5694 			device_printf(sc->dev,
5695 			   "failed to query hpfilter parameters: %d.\n", rc);
5696 			return (rc);
5697 		}
5698 		if ((int)val[1] > (int)val[0]) {
5699 			sc->tids.hpftid_base = val[0];
5700 			sc->tids.hpftid_end = val[1];
5701 			sc->tids.nhpftids = val[1] - val[0] + 1;
5702 
5703 			/*
5704 			 * These should go off if the layout changes and the
5705 			 * driver needs to catch up.
5706 			 */
5707 			MPASS(sc->tids.hpftid_base == 0);
5708 			MPASS(sc->tids.tid_base == sc->tids.nhpftids);
5709 		}
5710 
5711 		param[0] = FW_PARAM_PFVF(RAWF_START);
5712 		param[1] = FW_PARAM_PFVF(RAWF_END);
5713 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5714 		if (rc != 0) {
5715 			device_printf(sc->dev,
5716 			   "failed to query rawf parameters: %d.\n", rc);
5717 			return (rc);
5718 		}
5719 		if ((int)val[1] > (int)val[0]) {
5720 			sc->rawf_base = val[0];
5721 			sc->nrawf = val[1] - val[0] + 1;
5722 		}
5723 	}
5724 
5725 	if (sc->params.ncores > 1) {
5726 		param[0] = FW_PARAM_DEV(TID_QID_SEL_MASK);
5727 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5728 		sc->params.tid_qid_sel_mask = rc == 0 ? val[0] : 0;
5729 	}
5730 
5731 	/*
5732 	 * The parameters that follow may not be available on all firmwares.  We
5733 	 * query them individually rather than in a compound query because old
5734 	 * firmwares fail the entire query if an unknown parameter is queried.
5735 	 */
5736 
5737 	/*
5738 	 * MPS buffer group configuration.
5739 	 */
5740 	param[0] = FW_PARAM_DEV(MPSBGMAP);
5741 	val[0] = 0;
5742 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5743 	if (rc == 0)
5744 		sc->params.mps_bg_map = val[0];
5745 	else
5746 		sc->params.mps_bg_map = UINT32_MAX;	/* Not a legal value. */
5747 
5748 	param[0] = FW_PARAM_DEV(TPCHMAP);
5749 	val[0] = 0;
5750 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5751 	if (rc == 0)
5752 		sc->params.tp_ch_map = val[0];
5753 	else
5754 		sc->params.tp_ch_map = UINT32_MAX;	/* Not a legal value. */
5755 
5756 	param[0] = FW_PARAM_DEV(TX_TPCHMAP);
5757 	val[0] = 0;
5758 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5759 	if (rc == 0)
5760 		sc->params.tx_tp_ch_map = val[0];
5761 	else
5762 		sc->params.tx_tp_ch_map = UINT32_MAX;	/* Not a legal value. */
5763 
5764 	/*
5765 	 * Determine whether the firmware supports the filter2 work request.
5766 	 */
5767 	param[0] = FW_PARAM_DEV(FILTER2_WR);
5768 	val[0] = 0;
5769 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5770 	if (rc == 0)
5771 		sc->params.filter2_wr_support = val[0] != 0;
5772 	else
5773 		sc->params.filter2_wr_support = 0;
5774 
5775 	/*
5776 	 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
5777 	 */
5778 	param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5779 	val[0] = 0;
5780 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5781 	if (rc == 0)
5782 		sc->params.ulptx_memwrite_dsgl = val[0] != 0;
5783 	else
5784 		sc->params.ulptx_memwrite_dsgl = false;
5785 
5786 	/* FW_RI_FR_NSMR_TPTE_WR support */
5787 	param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
5788 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5789 	if (rc == 0)
5790 		sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
5791 	else
5792 		sc->params.fr_nsmr_tpte_wr_support = false;
5793 
5794 	/* Support for 512 SGL entries per FR MR. */
5795 	param[0] = FW_PARAM_DEV(DEV_512SGL_MR);
5796 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5797 	if (rc == 0)
5798 		sc->params.dev_512sgl_mr = val[0] != 0;
5799 	else
5800 		sc->params.dev_512sgl_mr = false;
5801 
5802 	param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
5803 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5804 	if (rc == 0)
5805 		sc->params.max_pkts_per_eth_tx_pkts_wr = val[0];
5806 	else
5807 		sc->params.max_pkts_per_eth_tx_pkts_wr = 15;
5808 
5809 	param[0] = FW_PARAM_DEV(NUM_TM_CLASS);
5810 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5811 	if (rc == 0) {
5812 		MPASS(val[0] > 0 && val[0] < 256);	/* nsched_cls is 8b */
5813 		sc->params.nsched_cls = val[0];
5814 	} else
5815 		sc->params.nsched_cls = sc->chip_params->nsched_cls;
5816 
5817 	/* get capabilites */
5818 	bzero(&caps, sizeof(caps));
5819 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5820 	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
5821 	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5822 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5823 	if (rc != 0) {
5824 		device_printf(sc->dev,
5825 		    "failed to get card capabilities: %d.\n", rc);
5826 		return (rc);
5827 	}
5828 
5829 #define READ_CAPS(x) do { \
5830 	sc->x = htobe16(caps.x); \
5831 } while (0)
5832 	READ_CAPS(nbmcaps);
5833 	READ_CAPS(linkcaps);
5834 	READ_CAPS(switchcaps);
5835 	READ_CAPS(nvmecaps);
5836 	READ_CAPS(niccaps);
5837 	READ_CAPS(toecaps);
5838 	READ_CAPS(rdmacaps);
5839 	READ_CAPS(cryptocaps);
5840 	READ_CAPS(iscsicaps);
5841 	READ_CAPS(fcoecaps);
5842 
5843 	if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
5844 		MPASS(chip_id(sc) > CHELSIO_T4);
5845 		MPASS(sc->toecaps == 0);
5846 		sc->toecaps = 0;
5847 
5848 		param[0] = FW_PARAM_DEV(NTID);
5849 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5850 		if (rc != 0) {
5851 			device_printf(sc->dev,
5852 			    "failed to query HASHFILTER parameters: %d.\n", rc);
5853 			return (rc);
5854 		}
5855 		sc->tids.ntids = val[0];
5856 		if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5857 			MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5858 			sc->tids.ntids -= sc->tids.nhpftids;
5859 		}
5860 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5861 		sc->params.hash_filter = 1;
5862 	}
5863 	if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
5864 		param[0] = FW_PARAM_PFVF(ETHOFLD_START);
5865 		param[1] = FW_PARAM_PFVF(ETHOFLD_END);
5866 		param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5867 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
5868 		if (rc != 0) {
5869 			device_printf(sc->dev,
5870 			    "failed to query NIC parameters: %d.\n", rc);
5871 			return (rc);
5872 		}
5873 		if ((int)val[1] > (int)val[0]) {
5874 			sc->tids.etid_base = val[0];
5875 			sc->tids.etid_end = val[1];
5876 			sc->tids.netids = val[1] - val[0] + 1;
5877 			sc->params.eo_wr_cred = val[2];
5878 			sc->params.ethoffload = 1;
5879 		}
5880 	}
5881 	if (sc->toecaps) {
5882 		/* query offload-related parameters */
5883 		param[0] = FW_PARAM_DEV(NTID);
5884 		param[1] = FW_PARAM_PFVF(SERVER_START);
5885 		param[2] = FW_PARAM_PFVF(SERVER_END);
5886 		param[3] = FW_PARAM_PFVF(TDDP_START);
5887 		param[4] = FW_PARAM_PFVF(TDDP_END);
5888 		param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5889 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5890 		if (rc != 0) {
5891 			device_printf(sc->dev,
5892 			    "failed to query TOE parameters: %d.\n", rc);
5893 			return (rc);
5894 		}
5895 		sc->tids.ntids = val[0];
5896 		if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5897 			MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5898 			sc->tids.ntids -= sc->tids.nhpftids;
5899 		}
5900 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5901 		if ((int)val[2] > (int)val[1]) {
5902 			sc->tids.stid_base = val[1];
5903 			sc->tids.nstids = val[2] - val[1] + 1;
5904 		}
5905 		sc->vres.ddp.start = val[3];
5906 		sc->vres.ddp.size = val[4] - val[3] + 1;
5907 		sc->params.ofldq_wr_cred = val[5];
5908 		sc->params.offload = 1;
5909 	} else {
5910 		/*
5911 		 * The firmware attempts memfree TOE configuration for -SO cards
5912 		 * and will report toecaps=0 if it runs out of resources (this
5913 		 * depends on the config file).  It may not report 0 for other
5914 		 * capabilities dependent on the TOE in this case.  Set them to
5915 		 * 0 here so that the driver doesn't bother tracking resources
5916 		 * that will never be used.
5917 		 */
5918 		sc->iscsicaps = 0;
5919 		sc->nvmecaps = 0;
5920 		sc->rdmacaps = 0;
5921 	}
5922 	if (sc->nvmecaps || sc->rdmacaps) {
5923 		param[0] = FW_PARAM_PFVF(STAG_START);
5924 		param[1] = FW_PARAM_PFVF(STAG_END);
5925 		param[2] = FW_PARAM_PFVF(PBL_START);
5926 		param[3] = FW_PARAM_PFVF(PBL_END);
5927 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
5928 		if (rc != 0) {
5929 			device_printf(sc->dev,
5930 			    "failed to query NVMe/RDMA parameters: %d.\n", rc);
5931 			return (rc);
5932 		}
5933 		sc->vres.stag.start = val[0];
5934 		sc->vres.stag.size = val[1] - val[0] + 1;
5935 		sc->vres.pbl.start = val[2];
5936 		sc->vres.pbl.size = val[3] - val[2] + 1;
5937 	}
5938 	if (sc->rdmacaps) {
5939 		param[0] = FW_PARAM_PFVF(RQ_START);
5940 		param[1] = FW_PARAM_PFVF(RQ_END);
5941 		param[2] = FW_PARAM_PFVF(SQRQ_START);
5942 		param[3] = FW_PARAM_PFVF(SQRQ_END);
5943 		param[4] = FW_PARAM_PFVF(CQ_START);
5944 		param[5] = FW_PARAM_PFVF(CQ_END);
5945 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5946 		if (rc != 0) {
5947 			device_printf(sc->dev,
5948 			    "failed to query RDMA parameters(1): %d.\n", rc);
5949 			return (rc);
5950 		}
5951 		sc->vres.rq.start = val[0];
5952 		sc->vres.rq.size = val[1] - val[0] + 1;
5953 		sc->vres.qp.start = val[2];
5954 		sc->vres.qp.size = val[3] - val[2] + 1;
5955 		sc->vres.cq.start = val[4];
5956 		sc->vres.cq.size = val[5] - val[4] + 1;
5957 
5958 		param[0] = FW_PARAM_PFVF(OCQ_START);
5959 		param[1] = FW_PARAM_PFVF(OCQ_END);
5960 		param[2] = FW_PARAM_PFVF(SRQ_START);
5961 		param[3] = FW_PARAM_PFVF(SRQ_END);
5962 		param[4] = FW_PARAM_DEV(MAXORDIRD_QP);
5963 		param[5] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5964 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5965 		if (rc != 0) {
5966 			device_printf(sc->dev,
5967 			    "failed to query RDMA parameters(2): %d.\n", rc);
5968 			return (rc);
5969 		}
5970 		sc->vres.ocq.start = val[0];
5971 		sc->vres.ocq.size = val[1] - val[0] + 1;
5972 		sc->vres.srq.start = val[2];
5973 		sc->vres.srq.size = val[3] - val[2] + 1;
5974 		sc->params.max_ordird_qp = val[4];
5975 		sc->params.max_ird_adapter = val[5];
5976 	}
5977 	if (sc->iscsicaps) {
5978 		param[0] = FW_PARAM_PFVF(ISCSI_START);
5979 		param[1] = FW_PARAM_PFVF(ISCSI_END);
5980 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5981 		if (rc != 0) {
5982 			device_printf(sc->dev,
5983 			    "failed to query iSCSI parameters: %d.\n", rc);
5984 			return (rc);
5985 		}
5986 		sc->vres.iscsi.start = val[0];
5987 		sc->vres.iscsi.size = val[1] - val[0] + 1;
5988 	}
5989 	if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
5990 		param[0] = FW_PARAM_PFVF(TLS_START);
5991 		param[1] = FW_PARAM_PFVF(TLS_END);
5992 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5993 		if (rc != 0) {
5994 			device_printf(sc->dev,
5995 			    "failed to query TLS parameters: %d.\n", rc);
5996 			return (rc);
5997 		}
5998 		sc->vres.key.start = val[0];
5999 		sc->vres.key.size = val[1] - val[0] + 1;
6000 	}
6001 	if (sc->cryptocaps & FW_CAPS_CONFIG_IPSEC_INLINE) {
6002 		param[0] = FW_PARAM_PFVF(NIPSEC_TUNNEL);
6003 		param[1] = FW_PARAM_PFVF(NIPSEC_TRANSPORT);
6004 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
6005 		if (rc == 0) {
6006 			sc->params.nipsec_tunnel = val[0];
6007 			sc->params.nipsec_transport = val[1];
6008 		} else {
6009 			CH_ERR(sc, "failed to query IPsec params: %d.\n", rc);
6010 			MPASS(sc->params.nipsec_tunnel == 0);
6011 			MPASS(sc->params.nipsec_transport == 0);
6012 		}
6013 	}
6014 	if (sc->cryptocaps & FW_CAPS_CONFIG_OFLD_OVER_IPSEC_INLINE) {
6015 		param[0] = FW_PARAM_PFVF(OFLD_NIPSEC_TUNNEL);
6016 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
6017 		if (rc == 0) {
6018 			sc->params.nofld_ipsec_tunnel = val[0];
6019 		} else {
6020 			CH_ERR(sc, "failed to query TOE IPsec params: %d.\n", rc);
6021 			MPASS(sc->params.nofld_ipsec_tunnel == 0);
6022 		}
6023 	}
6024 	/*
6025 	 * We've got the params we wanted to query directly from the firmware.
6026 	 * Grab some others via other means.
6027 	 */
6028 	t4_init_sge_params(sc);
6029 	t4_init_tp_params(sc);
6030 	t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
6031 	t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
6032 
6033 	rc = t4_verify_chip_settings(sc);
6034 	if (rc != 0)
6035 		return (rc);
6036 	t4_init_rx_buf_info(sc);
6037 
6038 	return (rc);
6039 }
6040 
6041 #ifdef KERN_TLS
6042 static void
6043 ktls_tick(void *arg)
6044 {
6045 	struct adapter *sc;
6046 	uint32_t tstamp;
6047 
6048 	sc = arg;
6049 	tstamp = tcp_ts_getticks();
6050 	t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
6051 	t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
6052 	callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
6053 }
6054 
6055 static int
6056 t6_config_kern_tls(struct adapter *sc, bool enable)
6057 {
6058 	int rc;
6059 	uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6060 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) |
6061 	    V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) |
6062 	    V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE);
6063 
6064 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &param);
6065 	if (rc != 0) {
6066 		CH_ERR(sc, "failed to %s NIC TLS: %d\n",
6067 		    enable ?  "enable" : "disable", rc);
6068 		return (rc);
6069 	}
6070 
6071 	if (enable) {
6072 		sc->flags |= KERN_TLS_ON;
6073 		callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
6074 		    C_HARDCLOCK);
6075 	} else {
6076 		sc->flags &= ~KERN_TLS_ON;
6077 		callout_stop(&sc->ktls_tick);
6078 	}
6079 
6080 	return (rc);
6081 }
6082 #endif
6083 
6084 static int
6085 set_params__post_init(struct adapter *sc)
6086 {
6087 	uint32_t mask, param, val;
6088 #ifdef TCP_OFFLOAD
6089 	int i, v, shift;
6090 #endif
6091 
6092 	/* ask for encapsulated CPLs */
6093 	param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
6094 	val = 1;
6095 	(void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6096 
6097 	/* Enable 32b port caps if the firmware supports it. */
6098 	param = FW_PARAM_PFVF(PORT_CAPS32);
6099 	val = 1;
6100 	if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val) == 0)
6101 		sc->params.port_caps32 = 1;
6102 
6103 	/* Let filter + maskhash steer to a part of the VI's RSS region. */
6104 	val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
6105 	t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
6106 	    V_MASKFILTER(val - 1));
6107 
6108 	mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER |
6109 	    F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN |
6110 	    F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
6111 	    F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM;
6112 	val = 0;
6113 	if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) {
6114 		t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE,
6115 		    F_ATTACKFILTERENABLE);
6116 		val |= F_DROPERRORATTACK;
6117 	}
6118 	if (t4_drop_ip_fragments != 0) {
6119 		t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP,
6120 		    F_FRAGMENTDROP);
6121 		val |= F_DROPERRORFRAG;
6122 	}
6123 	if (t4_drop_pkts_with_l2_errors != 0)
6124 		val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN;
6125 	if (t4_drop_pkts_with_l3_errors != 0) {
6126 		val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN |
6127 		    F_DROPERRORCSUMIP;
6128 	}
6129 	if (t4_drop_pkts_with_l4_errors != 0) {
6130 		val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
6131 		    F_DROPERRORTCPOPT | F_DROPERRORCSUM;
6132 	}
6133 	t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val);
6134 
6135 #ifdef TCP_OFFLOAD
6136 	/*
6137 	 * Override the TOE timers with user provided tunables.  This is not the
6138 	 * recommended way to change the timers (the firmware config file is) so
6139 	 * these tunables are not documented.
6140 	 *
6141 	 * All the timer tunables are in microseconds.
6142 	 */
6143 	if (t4_toe_keepalive_idle != 0) {
6144 		v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
6145 		v &= M_KEEPALIVEIDLE;
6146 		t4_set_reg_field(sc, A_TP_KEEP_IDLE,
6147 		    V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
6148 	}
6149 	if (t4_toe_keepalive_interval != 0) {
6150 		v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
6151 		v &= M_KEEPALIVEINTVL;
6152 		t4_set_reg_field(sc, A_TP_KEEP_INTVL,
6153 		    V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
6154 	}
6155 	if (t4_toe_keepalive_count != 0) {
6156 		v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
6157 		t4_set_reg_field(sc, A_TP_SHIFT_CNT,
6158 		    V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
6159 		    V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
6160 		    V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
6161 	}
6162 	if (t4_toe_rexmt_min != 0) {
6163 		v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
6164 		v &= M_RXTMIN;
6165 		t4_set_reg_field(sc, A_TP_RXT_MIN,
6166 		    V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
6167 	}
6168 	if (t4_toe_rexmt_max != 0) {
6169 		v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
6170 		v &= M_RXTMAX;
6171 		t4_set_reg_field(sc, A_TP_RXT_MAX,
6172 		    V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
6173 	}
6174 	if (t4_toe_rexmt_count != 0) {
6175 		v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
6176 		t4_set_reg_field(sc, A_TP_SHIFT_CNT,
6177 		    V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
6178 		    V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
6179 		    V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
6180 	}
6181 	for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
6182 		if (t4_toe_rexmt_backoff[i] != -1) {
6183 			v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
6184 			shift = (i & 3) << 3;
6185 			t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
6186 			    M_TIMERBACKOFFINDEX0 << shift, v << shift);
6187 		}
6188 	}
6189 #endif
6190 
6191 	/*
6192 	 * Limit TOE connections to 2 reassembly "islands".  This is
6193 	 * required to permit migrating TOE connections to either
6194 	 * ULP_MODE_TCPDDP or UPL_MODE_TLS.
6195 	 */
6196 	t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE),
6197 	    V_PASSMODE(2));
6198 
6199 #ifdef KERN_TLS
6200 	if (is_ktls(sc)) {
6201 		sc->tlst.inline_keys = t4_tls_inline_keys;
6202 		if (t4_kern_tls != 0 && is_t6(sc)) {
6203 			sc->tlst.combo_wrs = t4_tls_combo_wrs;
6204 			t6_config_kern_tls(sc, true);
6205 		} else {
6206 			sc->tlst.short_records = t4_tls_short_records;
6207 			sc->tlst.partial_ghash = t4_tls_partial_ghash;
6208 		}
6209 	}
6210 #endif
6211 	return (0);
6212 }
6213 
6214 #undef FW_PARAM_PFVF
6215 #undef FW_PARAM_DEV
6216 
6217 static void
6218 t4_set_desc(struct adapter *sc)
6219 {
6220 	struct adapter_params *p = &sc->params;
6221 
6222 	device_set_descf(sc->dev, "Chelsio %s", p->vpd.id);
6223 }
6224 
6225 static inline void
6226 ifmedia_add4(struct ifmedia *ifm, int m)
6227 {
6228 
6229 	ifmedia_add(ifm, m, 0, NULL);
6230 	ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
6231 	ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
6232 	ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
6233 }
6234 
6235 /*
6236  * This is the selected media, which is not quite the same as the active media.
6237  * The media line in ifconfig is "media: Ethernet selected (active)" if selected
6238  * and active are not the same, and "media: Ethernet selected" otherwise.
6239  */
6240 static void
6241 set_current_media(struct port_info *pi)
6242 {
6243 	struct link_config *lc;
6244 	struct ifmedia *ifm;
6245 	int mword;
6246 	u_int speed;
6247 
6248 	PORT_LOCK_ASSERT_OWNED(pi);
6249 
6250 	/* Leave current media alone if it's already set to IFM_NONE. */
6251 	ifm = &pi->media;
6252 	if (ifm->ifm_cur != NULL &&
6253 	    IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
6254 		return;
6255 
6256 	lc = &pi->link_cfg;
6257 	if (lc->requested_aneg != AUTONEG_DISABLE &&
6258 	    lc->pcaps & FW_PORT_CAP32_ANEG) {
6259 		ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
6260 		return;
6261 	}
6262 	mword = IFM_ETHER | IFM_FDX;
6263 	if (lc->requested_fc & PAUSE_TX)
6264 		mword |= IFM_ETH_TXPAUSE;
6265 	if (lc->requested_fc & PAUSE_RX)
6266 		mword |= IFM_ETH_RXPAUSE;
6267 	if (lc->requested_speed == 0)
6268 		speed = port_top_speed(pi) * 1000;	/* Gbps -> Mbps */
6269 	else
6270 		speed = lc->requested_speed;
6271 	mword |= port_mword(pi, speed_to_fwcap(speed));
6272 	ifmedia_set(ifm, mword);
6273 }
6274 
6275 /*
6276  * Returns true if the ifmedia list for the port cannot change.
6277  */
6278 static bool
6279 fixed_ifmedia(struct port_info *pi)
6280 {
6281 
6282 	return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
6283 	    pi->port_type == FW_PORT_TYPE_BT_XFI ||
6284 	    pi->port_type == FW_PORT_TYPE_BT_XAUI ||
6285 	    pi->port_type == FW_PORT_TYPE_KX4 ||
6286 	    pi->port_type == FW_PORT_TYPE_KX ||
6287 	    pi->port_type == FW_PORT_TYPE_KR ||
6288 	    pi->port_type == FW_PORT_TYPE_BP_AP ||
6289 	    pi->port_type == FW_PORT_TYPE_BP4_AP ||
6290 	    pi->port_type == FW_PORT_TYPE_BP40_BA ||
6291 	    pi->port_type == FW_PORT_TYPE_KR4_100G ||
6292 	    pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
6293 	    pi->port_type == FW_PORT_TYPE_KR_XLAUI);
6294 }
6295 
6296 static void
6297 build_medialist(struct port_info *pi)
6298 {
6299 	uint32_t ss, speed;
6300 	int unknown, mword, bit;
6301 	struct link_config *lc;
6302 	struct ifmedia *ifm;
6303 
6304 	PORT_LOCK_ASSERT_OWNED(pi);
6305 
6306 	if (pi->flags & FIXED_IFMEDIA)
6307 		return;
6308 
6309 	/*
6310 	 * Rebuild the ifmedia list.
6311 	 */
6312 	ifm = &pi->media;
6313 	ifmedia_removeall(ifm);
6314 	lc = &pi->link_cfg;
6315 	ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
6316 	if (__predict_false(ss == 0)) {	/* not supposed to happen. */
6317 		MPASS(ss != 0);
6318 no_media:
6319 		MPASS(LIST_EMPTY(&ifm->ifm_list));
6320 		ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
6321 		ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
6322 		return;
6323 	}
6324 
6325 	unknown = 0;
6326 	for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
6327 		speed = 1 << bit;
6328 		MPASS(speed & M_FW_PORT_CAP32_SPEED);
6329 		if (ss & speed) {
6330 			mword = port_mword(pi, speed);
6331 			if (mword == IFM_NONE) {
6332 				goto no_media;
6333 			} else if (mword == IFM_UNKNOWN)
6334 				unknown++;
6335 			else
6336 				ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
6337 		}
6338 	}
6339 	if (unknown > 0) /* Add one unknown for all unknown media types. */
6340 		ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
6341 	if (lc->pcaps & FW_PORT_CAP32_ANEG)
6342 		ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
6343 
6344 	set_current_media(pi);
6345 }
6346 
6347 /*
6348  * Initialize the requested fields in the link config based on driver tunables.
6349  */
6350 static void
6351 init_link_config(struct port_info *pi)
6352 {
6353 	struct link_config *lc = &pi->link_cfg;
6354 
6355 	PORT_LOCK_ASSERT_OWNED(pi);
6356 
6357 	lc->requested_caps = 0;
6358 	lc->requested_speed = 0;
6359 
6360 	if (t4_autoneg == 0)
6361 		lc->requested_aneg = AUTONEG_DISABLE;
6362 	else if (t4_autoneg == 1)
6363 		lc->requested_aneg = AUTONEG_ENABLE;
6364 	else
6365 		lc->requested_aneg = AUTONEG_AUTO;
6366 
6367 	lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
6368 	    PAUSE_AUTONEG);
6369 
6370 	if (t4_fec & FEC_AUTO)
6371 		lc->requested_fec = FEC_AUTO;
6372 	else if (t4_fec == 0)
6373 		lc->requested_fec = FEC_NONE;
6374 	else {
6375 		/* -1 is handled by the FEC_AUTO block above and not here. */
6376 		lc->requested_fec = t4_fec &
6377 		    (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
6378 		if (lc->requested_fec == 0)
6379 			lc->requested_fec = FEC_AUTO;
6380 	}
6381 	if (t4_force_fec < 0)
6382 		lc->force_fec = -1;
6383 	else if (t4_force_fec > 0)
6384 		lc->force_fec = 1;
6385 	else
6386 		lc->force_fec = 0;
6387 }
6388 
6389 /*
6390  * Makes sure that all requested settings comply with what's supported by the
6391  * port.  Returns the number of settings that were invalid and had to be fixed.
6392  */
6393 static int
6394 fixup_link_config(struct port_info *pi)
6395 {
6396 	int n = 0;
6397 	struct link_config *lc = &pi->link_cfg;
6398 	uint32_t fwspeed;
6399 
6400 	PORT_LOCK_ASSERT_OWNED(pi);
6401 
6402 	/* Speed (when not autonegotiating) */
6403 	if (lc->requested_speed != 0) {
6404 		fwspeed = speed_to_fwcap(lc->requested_speed);
6405 		if ((fwspeed & lc->pcaps) == 0) {
6406 			n++;
6407 			lc->requested_speed = 0;
6408 		}
6409 	}
6410 
6411 	/* Link autonegotiation */
6412 	MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
6413 	    lc->requested_aneg == AUTONEG_DISABLE ||
6414 	    lc->requested_aneg == AUTONEG_AUTO);
6415 	if (lc->requested_aneg == AUTONEG_ENABLE &&
6416 	    !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
6417 		n++;
6418 		lc->requested_aneg = AUTONEG_AUTO;
6419 	}
6420 
6421 	/* Flow control */
6422 	MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
6423 	if (lc->requested_fc & PAUSE_TX &&
6424 	    !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
6425 		n++;
6426 		lc->requested_fc &= ~PAUSE_TX;
6427 	}
6428 	if (lc->requested_fc & PAUSE_RX &&
6429 	    !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
6430 		n++;
6431 		lc->requested_fc &= ~PAUSE_RX;
6432 	}
6433 	if (!(lc->requested_fc & PAUSE_AUTONEG) &&
6434 	    !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
6435 		n++;
6436 		lc->requested_fc |= PAUSE_AUTONEG;
6437 	}
6438 
6439 	/* FEC */
6440 	if ((lc->requested_fec & FEC_RS &&
6441 	    !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
6442 	    (lc->requested_fec & FEC_BASER_RS &&
6443 	    !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
6444 		n++;
6445 		lc->requested_fec = FEC_AUTO;
6446 	}
6447 
6448 	return (n);
6449 }
6450 
6451 /*
6452  * Apply the requested L1 settings, which are expected to be valid, to the
6453  * hardware.
6454  */
6455 static int
6456 apply_link_config(struct port_info *pi)
6457 {
6458 	struct adapter *sc = pi->adapter;
6459 	struct link_config *lc = &pi->link_cfg;
6460 	int rc;
6461 
6462 #ifdef INVARIANTS
6463 	ASSERT_SYNCHRONIZED_OP(sc);
6464 	PORT_LOCK_ASSERT_OWNED(pi);
6465 
6466 	if (lc->requested_aneg == AUTONEG_ENABLE)
6467 		MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
6468 	if (!(lc->requested_fc & PAUSE_AUTONEG))
6469 		MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
6470 	if (lc->requested_fc & PAUSE_TX)
6471 		MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
6472 	if (lc->requested_fc & PAUSE_RX)
6473 		MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
6474 	if (lc->requested_fec & FEC_RS)
6475 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
6476 	if (lc->requested_fec & FEC_BASER_RS)
6477 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
6478 #endif
6479 	if (!(sc->flags & IS_VF)) {
6480 		rc = -t4_link_l1cfg(sc, sc->mbox, pi->hw_port, lc);
6481 		if (rc != 0) {
6482 			device_printf(pi->dev, "l1cfg failed: %d\n", rc);
6483 			return (rc);
6484 		}
6485 	}
6486 
6487 	/*
6488 	 * An L1_CFG will almost always result in a link-change event if the
6489 	 * link is up, and the driver will refresh the actual fec/fc/etc. when
6490 	 * the notification is processed.  If the link is down then the actual
6491 	 * settings are meaningless.
6492 	 *
6493 	 * This takes care of the case where a change in the L1 settings may not
6494 	 * result in a notification.
6495 	 */
6496 	if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
6497 		lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
6498 
6499 	return (0);
6500 }
6501 
6502 #define FW_MAC_EXACT_CHUNK	7
6503 struct mcaddr_ctx {
6504 	if_t ifp;
6505 	const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
6506 	uint64_t hash;
6507 	int i;
6508 	int del;
6509 	int rc;
6510 };
6511 
6512 static u_int
6513 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
6514 {
6515 	struct mcaddr_ctx *ctx = arg;
6516 	struct vi_info *vi = if_getsoftc(ctx->ifp);
6517 	struct port_info *pi = vi->pi;
6518 	struct adapter *sc = pi->adapter;
6519 
6520 	if (ctx->rc < 0)
6521 		return (0);
6522 
6523 	ctx->mcaddr[ctx->i] = LLADDR(sdl);
6524 	MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
6525 	ctx->i++;
6526 
6527 	if (ctx->i == FW_MAC_EXACT_CHUNK) {
6528 		ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
6529 		    ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
6530 		if (ctx->rc < 0) {
6531 			int j;
6532 
6533 			for (j = 0; j < ctx->i; j++) {
6534 				if_printf(ctx->ifp,
6535 				    "failed to add mc address"
6536 				    " %02x:%02x:%02x:"
6537 				    "%02x:%02x:%02x rc=%d\n",
6538 				    ctx->mcaddr[j][0], ctx->mcaddr[j][1],
6539 				    ctx->mcaddr[j][2], ctx->mcaddr[j][3],
6540 				    ctx->mcaddr[j][4], ctx->mcaddr[j][5],
6541 				    -ctx->rc);
6542 			}
6543 			return (0);
6544 		}
6545 		ctx->del = 0;
6546 		ctx->i = 0;
6547 	}
6548 
6549 	return (1);
6550 }
6551 
6552 /*
6553  * Program the port's XGMAC based on parameters in ifnet.  The caller also
6554  * indicates which parameters should be programmed (the rest are left alone).
6555  */
6556 int
6557 update_mac_settings(if_t ifp, int flags)
6558 {
6559 	int rc = 0;
6560 	struct vi_info *vi = if_getsoftc(ifp);
6561 	struct port_info *pi = vi->pi;
6562 	struct adapter *sc = pi->adapter;
6563 	int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
6564 	uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
6565 
6566 	ASSERT_SYNCHRONIZED_OP(sc);
6567 	KASSERT(flags, ("%s: not told what to update.", __func__));
6568 
6569 	if (flags & XGMAC_MTU)
6570 		mtu = if_getmtu(ifp);
6571 
6572 	if (flags & XGMAC_PROMISC)
6573 		promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0;
6574 
6575 	if (flags & XGMAC_ALLMULTI)
6576 		allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0;
6577 
6578 	if (flags & XGMAC_VLANEX)
6579 		vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0;
6580 
6581 	if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
6582 		rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
6583 		    allmulti, 1, vlanex, false);
6584 		if (rc) {
6585 			if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
6586 			    rc);
6587 			return (rc);
6588 		}
6589 	}
6590 
6591 	if (flags & XGMAC_UCADDR) {
6592 		uint8_t ucaddr[ETHER_ADDR_LEN];
6593 
6594 		bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr));
6595 		rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
6596 		    ucaddr, true, &vi->smt_idx);
6597 		if (rc < 0) {
6598 			rc = -rc;
6599 			if_printf(ifp, "change_mac failed: %d\n", rc);
6600 			return (rc);
6601 		} else {
6602 			vi->xact_addr_filt = rc;
6603 			rc = 0;
6604 		}
6605 	}
6606 
6607 	if (flags & XGMAC_MCADDRS) {
6608 		struct epoch_tracker et;
6609 		struct mcaddr_ctx ctx;
6610 		int j;
6611 
6612 		ctx.ifp = ifp;
6613 		ctx.hash = 0;
6614 		ctx.i = 0;
6615 		ctx.del = 1;
6616 		ctx.rc = 0;
6617 		/*
6618 		 * Unlike other drivers, we accumulate list of pointers into
6619 		 * interface address lists and we need to keep it safe even
6620 		 * after if_foreach_llmaddr() returns, thus we must enter the
6621 		 * network epoch.
6622 		 */
6623 		NET_EPOCH_ENTER(et);
6624 		if_foreach_llmaddr(ifp, add_maddr, &ctx);
6625 		if (ctx.rc < 0) {
6626 			NET_EPOCH_EXIT(et);
6627 			rc = -ctx.rc;
6628 			return (rc);
6629 		}
6630 		if (ctx.i > 0) {
6631 			rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
6632 			    ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
6633 			NET_EPOCH_EXIT(et);
6634 			if (rc < 0) {
6635 				rc = -rc;
6636 				for (j = 0; j < ctx.i; j++) {
6637 					if_printf(ifp,
6638 					    "failed to add mcast address"
6639 					    " %02x:%02x:%02x:"
6640 					    "%02x:%02x:%02x rc=%d\n",
6641 					    ctx.mcaddr[j][0], ctx.mcaddr[j][1],
6642 					    ctx.mcaddr[j][2], ctx.mcaddr[j][3],
6643 					    ctx.mcaddr[j][4], ctx.mcaddr[j][5],
6644 					    rc);
6645 				}
6646 				return (rc);
6647 			}
6648 			ctx.del = 0;
6649 		} else
6650 			NET_EPOCH_EXIT(et);
6651 
6652 		rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
6653 		if (rc != 0)
6654 			if_printf(ifp, "failed to set mcast address hash: %d\n",
6655 			    rc);
6656 		if (ctx.del == 0) {
6657 			/* We clobbered the VXLAN entry if there was one. */
6658 			pi->vxlan_tcam_entry = false;
6659 		}
6660 	}
6661 
6662 	if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 &&
6663 	    pi->vxlan_tcam_entry == false) {
6664 		rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac,
6665 		    match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
6666 		    true);
6667 		if (rc < 0) {
6668 			rc = -rc;
6669 			if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n",
6670 			    rc);
6671 		} else {
6672 			MPASS(rc == sc->rawf_base + pi->port_id);
6673 			rc = 0;
6674 			pi->vxlan_tcam_entry = true;
6675 		}
6676 	}
6677 
6678 	return (rc);
6679 }
6680 
6681 /*
6682  * {begin|end}_synchronized_op must be called from the same thread.
6683  */
6684 int
6685 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
6686     char *wmesg)
6687 {
6688 	int rc;
6689 
6690 #ifdef WITNESS
6691 	/* the caller thinks it's ok to sleep, but is it really? */
6692 	if (flags & SLEEP_OK)
6693 		WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, __func__);
6694 #endif
6695 	ADAPTER_LOCK(sc);
6696 	for (;;) {
6697 
6698 		if (vi && IS_DETACHING(vi)) {
6699 			rc = ENXIO;
6700 			goto done;
6701 		}
6702 
6703 		if (!IS_BUSY(sc)) {
6704 			rc = 0;
6705 			break;
6706 		}
6707 
6708 		if (!(flags & SLEEP_OK)) {
6709 			rc = EBUSY;
6710 			goto done;
6711 		}
6712 
6713 		if (mtx_sleep(&sc->flags, &sc->sc_lock,
6714 		    flags & INTR_OK ? PCATCH : 0, wmesg, 0)) {
6715 			rc = EINTR;
6716 			goto done;
6717 		}
6718 	}
6719 
6720 	KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
6721 	SET_BUSY(sc);
6722 #ifdef INVARIANTS
6723 	sc->last_op = wmesg;
6724 	sc->last_op_thr = curthread;
6725 	sc->last_op_flags = flags;
6726 #endif
6727 
6728 done:
6729 	if (!(flags & HOLD_LOCK) || rc)
6730 		ADAPTER_UNLOCK(sc);
6731 
6732 	return (rc);
6733 }
6734 
6735 /*
6736  * Tell if_ioctl and if_init that the VI is going away.  This is
6737  * special variant of begin_synchronized_op and must be paired with a
6738  * call to end_vi_detach.
6739  */
6740 void
6741 begin_vi_detach(struct adapter *sc, struct vi_info *vi)
6742 {
6743 	ADAPTER_LOCK(sc);
6744 	SET_DETACHING(vi);
6745 	wakeup(&sc->flags);
6746 	while (IS_BUSY(sc))
6747 		mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
6748 	SET_BUSY(sc);
6749 #ifdef INVARIANTS
6750 	sc->last_op = "t4detach";
6751 	sc->last_op_thr = curthread;
6752 	sc->last_op_flags = 0;
6753 #endif
6754 	ADAPTER_UNLOCK(sc);
6755 }
6756 
6757 void
6758 end_vi_detach(struct adapter *sc, struct vi_info *vi)
6759 {
6760 	ADAPTER_LOCK(sc);
6761 	KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6762 	CLR_BUSY(sc);
6763 	CLR_DETACHING(vi);
6764 	wakeup(&sc->flags);
6765 	ADAPTER_UNLOCK(sc);
6766 }
6767 
6768 /*
6769  * {begin|end}_synchronized_op must be called from the same thread.
6770  */
6771 void
6772 end_synchronized_op(struct adapter *sc, int flags)
6773 {
6774 
6775 	if (flags & LOCK_HELD)
6776 		ADAPTER_LOCK_ASSERT_OWNED(sc);
6777 	else
6778 		ADAPTER_LOCK(sc);
6779 
6780 	KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6781 	CLR_BUSY(sc);
6782 	wakeup(&sc->flags);
6783 	ADAPTER_UNLOCK(sc);
6784 }
6785 
6786 static int
6787 cxgbe_init_synchronized(struct vi_info *vi)
6788 {
6789 	struct port_info *pi = vi->pi;
6790 	struct adapter *sc = pi->adapter;
6791 	if_t ifp = vi->ifp;
6792 	int rc = 0, i;
6793 	struct sge_txq *txq;
6794 
6795 	ASSERT_SYNCHRONIZED_OP(sc);
6796 
6797 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6798 		return (0);	/* already running */
6799 
6800 	if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0))
6801 		return (rc);	/* error message displayed already */
6802 
6803 	if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
6804 		return (rc); /* error message displayed already */
6805 
6806 	rc = update_mac_settings(ifp, XGMAC_ALL);
6807 	if (rc)
6808 		goto done;	/* error message displayed already */
6809 
6810 	PORT_LOCK(pi);
6811 	if (pi->up_vis == 0) {
6812 		t4_update_port_info(pi);
6813 		fixup_link_config(pi);
6814 		build_medialist(pi);
6815 		apply_link_config(pi);
6816 	}
6817 
6818 	rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
6819 	if (rc != 0) {
6820 		if_printf(ifp, "enable_vi failed: %d\n", rc);
6821 		PORT_UNLOCK(pi);
6822 		goto done;
6823 	}
6824 
6825 	/*
6826 	 * Can't fail from this point onwards.  Review cxgbe_uninit_synchronized
6827 	 * if this changes.
6828 	 */
6829 
6830 	for_each_txq(vi, i, txq) {
6831 		TXQ_LOCK(txq);
6832 		txq->eq.flags |= EQ_ENABLED;
6833 		TXQ_UNLOCK(txq);
6834 	}
6835 
6836 	/*
6837 	 * The first iq of the first port to come up is used for tracing.
6838 	 */
6839 	if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
6840 		sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
6841 		t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
6842 		pi->flags |= HAS_TRACEQ;
6843 	}
6844 
6845 	/* all ok */
6846 	pi->up_vis++;
6847 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
6848 	if (pi->link_cfg.link_ok)
6849 		t4_os_link_changed(pi);
6850 	PORT_UNLOCK(pi);
6851 
6852 	mtx_lock(&vi->tick_mtx);
6853 	if (vi->pi->nvi > 1 || sc->flags & IS_VF)
6854 		callout_reset(&vi->tick, hz, vi_tick, vi);
6855 	else
6856 		callout_reset(&vi->tick, hz, cxgbe_tick, vi);
6857 	mtx_unlock(&vi->tick_mtx);
6858 done:
6859 	if (rc != 0)
6860 		cxgbe_uninit_synchronized(vi);
6861 
6862 	return (rc);
6863 }
6864 
6865 /*
6866  * Idempotent.
6867  */
6868 static int
6869 cxgbe_uninit_synchronized(struct vi_info *vi)
6870 {
6871 	struct port_info *pi = vi->pi;
6872 	struct adapter *sc = pi->adapter;
6873 	if_t ifp = vi->ifp;
6874 	int rc, i;
6875 	struct sge_txq *txq;
6876 
6877 	ASSERT_SYNCHRONIZED_OP(sc);
6878 
6879 	if (!(vi->flags & VI_INIT_DONE)) {
6880 		if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6881 			KASSERT(0, ("uninited VI is running"));
6882 			if_printf(ifp, "uninited VI with running ifnet.  "
6883 			    "vi->flags 0x%016lx, if_flags 0x%08x, "
6884 			    "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp),
6885 			    if_getdrvflags(ifp));
6886 		}
6887 		return (0);
6888 	}
6889 
6890 	/*
6891 	 * Disable the VI so that all its data in either direction is discarded
6892 	 * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
6893 	 * tick) intact as the TP can deliver negative advice or data that it's
6894 	 * holding in its RAM (for an offloaded connection) even after the VI is
6895 	 * disabled.
6896 	 */
6897 	rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
6898 	if (rc) {
6899 		if_printf(ifp, "disable_vi failed: %d\n", rc);
6900 		return (rc);
6901 	}
6902 
6903 	for_each_txq(vi, i, txq) {
6904 		TXQ_LOCK(txq);
6905 		txq->eq.flags &= ~EQ_ENABLED;
6906 		TXQ_UNLOCK(txq);
6907 	}
6908 
6909 	mtx_lock(&vi->tick_mtx);
6910 	callout_stop(&vi->tick);
6911 	mtx_unlock(&vi->tick_mtx);
6912 
6913 	PORT_LOCK(pi);
6914 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6915 		PORT_UNLOCK(pi);
6916 		return (0);
6917 	}
6918 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
6919 	pi->up_vis--;
6920 	if (pi->up_vis > 0) {
6921 		PORT_UNLOCK(pi);
6922 		return (0);
6923 	}
6924 
6925 	pi->link_cfg.link_ok = false;
6926 	pi->link_cfg.speed = 0;
6927 	pi->link_cfg.link_down_rc = 255;
6928 	t4_os_link_changed(pi);
6929 	PORT_UNLOCK(pi);
6930 
6931 	return (0);
6932 }
6933 
6934 /*
6935  * It is ok for this function to fail midway and return right away.  t4_detach
6936  * will walk the entire sc->irq list and clean up whatever is valid.
6937  */
6938 int
6939 t4_setup_intr_handlers(struct adapter *sc)
6940 {
6941 	int rc, rid, p, q, v;
6942 	char s[8];
6943 	struct irq *irq;
6944 	struct port_info *pi;
6945 	struct vi_info *vi;
6946 	struct sge *sge = &sc->sge;
6947 	struct sge_rxq *rxq;
6948 #ifdef TCP_OFFLOAD
6949 	struct sge_ofld_rxq *ofld_rxq;
6950 #endif
6951 #ifdef DEV_NETMAP
6952 	struct sge_nm_rxq *nm_rxq;
6953 #endif
6954 #ifdef RSS
6955 	int nbuckets = rss_getnumbuckets();
6956 #endif
6957 
6958 	/*
6959 	 * Setup interrupts.
6960 	 */
6961 	irq = &sc->irq[0];
6962 	rid = sc->intr_type == INTR_INTX ? 0 : 1;
6963 	if (forwarding_intr_to_fwq(sc))
6964 		return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
6965 
6966 	/* Multiple interrupts. */
6967 	if (sc->flags & IS_VF)
6968 		KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
6969 		    ("%s: too few intr.", __func__));
6970 	else
6971 		KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
6972 		    ("%s: too few intr.", __func__));
6973 
6974 	/* The first one is always error intr on PFs */
6975 	if (!(sc->flags & IS_VF)) {
6976 		rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
6977 		if (rc != 0)
6978 			return (rc);
6979 		irq++;
6980 		rid++;
6981 	}
6982 
6983 	/* The second one is always the firmware event queue (first on VFs) */
6984 	rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
6985 	if (rc != 0)
6986 		return (rc);
6987 	irq++;
6988 	rid++;
6989 
6990 	for_each_port(sc, p) {
6991 		pi = sc->port[p];
6992 		for_each_vi(pi, v, vi) {
6993 			vi->first_intr = rid - 1;
6994 
6995 			if (vi->nnmrxq > 0) {
6996 				int n = max(vi->nrxq, vi->nnmrxq);
6997 
6998 				rxq = &sge->rxq[vi->first_rxq];
6999 #ifdef DEV_NETMAP
7000 				nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
7001 #endif
7002 				for (q = 0; q < n; q++) {
7003 					snprintf(s, sizeof(s), "%x%c%x", p,
7004 					    'a' + v, q);
7005 					if (q < vi->nrxq)
7006 						irq->rxq = rxq++;
7007 #ifdef DEV_NETMAP
7008 					if (q < vi->nnmrxq)
7009 						irq->nm_rxq = nm_rxq++;
7010 
7011 					if (irq->nm_rxq != NULL &&
7012 					    irq->rxq == NULL) {
7013 						/* Netmap rx only */
7014 						rc = t4_alloc_irq(sc, irq, rid,
7015 						    t4_nm_intr, irq->nm_rxq, s);
7016 					}
7017 					if (irq->nm_rxq != NULL &&
7018 					    irq->rxq != NULL) {
7019 						/* NIC and Netmap rx */
7020 						rc = t4_alloc_irq(sc, irq, rid,
7021 						    t4_vi_intr, irq, s);
7022 					}
7023 #endif
7024 					if (irq->rxq != NULL &&
7025 					    irq->nm_rxq == NULL) {
7026 						/* NIC rx only */
7027 						rc = t4_alloc_irq(sc, irq, rid,
7028 						    t4_intr, irq->rxq, s);
7029 					}
7030 					if (rc != 0)
7031 						return (rc);
7032 #ifdef RSS
7033 					if (q < vi->nrxq) {
7034 						bus_bind_intr(sc->dev, irq->res,
7035 						    rss_getcpu(q % nbuckets));
7036 					}
7037 #endif
7038 					irq++;
7039 					rid++;
7040 					vi->nintr++;
7041 				}
7042 			} else {
7043 				for_each_rxq(vi, q, rxq) {
7044 					snprintf(s, sizeof(s), "%x%c%x", p,
7045 					    'a' + v, q);
7046 					rc = t4_alloc_irq(sc, irq, rid,
7047 					    t4_intr, rxq, s);
7048 					if (rc != 0)
7049 						return (rc);
7050 #ifdef RSS
7051 					bus_bind_intr(sc->dev, irq->res,
7052 					    rss_getcpu(q % nbuckets));
7053 #endif
7054 					irq++;
7055 					rid++;
7056 					vi->nintr++;
7057 				}
7058 			}
7059 #ifdef TCP_OFFLOAD
7060 			for_each_ofld_rxq(vi, q, ofld_rxq) {
7061 				snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
7062 				rc = t4_alloc_irq(sc, irq, rid, t4_intr,
7063 				    ofld_rxq, s);
7064 				if (rc != 0)
7065 					return (rc);
7066 				irq++;
7067 				rid++;
7068 				vi->nintr++;
7069 			}
7070 #endif
7071 		}
7072 	}
7073 	MPASS(irq == &sc->irq[sc->intr_count]);
7074 
7075 	return (0);
7076 }
7077 
7078 static void
7079 write_global_rss_key(struct adapter *sc)
7080 {
7081 	int i;
7082 	uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
7083 	uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
7084 
7085 	CTASSERT(RSS_KEYSIZE == 40);
7086 
7087 	rss_getkey((void *)&raw_rss_key[0]);
7088 	for (i = 0; i < nitems(rss_key); i++) {
7089 		rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
7090 	}
7091 	t4_write_rss_key(sc, &rss_key[0], -1, 1);
7092 }
7093 
7094 /*
7095  * Idempotent.
7096  */
7097 static int
7098 adapter_full_init(struct adapter *sc)
7099 {
7100 	int rc, i;
7101 
7102 	ASSERT_SYNCHRONIZED_OP(sc);
7103 
7104 	/*
7105 	 * queues that belong to the adapter (not any particular port).
7106 	 */
7107 	rc = t4_setup_adapter_queues(sc);
7108 	if (rc != 0)
7109 		return (rc);
7110 
7111 	MPASS(sc->params.nports <= nitems(sc->tq));
7112 	for (i = 0; i < sc->params.nports; i++) {
7113 		if (sc->tq[i] != NULL)
7114 			continue;
7115 		sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
7116 		    taskqueue_thread_enqueue, &sc->tq[i]);
7117 		if (sc->tq[i] == NULL) {
7118 			CH_ERR(sc, "failed to allocate task queue %d\n", i);
7119 			return (ENOMEM);
7120 		}
7121 		taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
7122 		    device_get_nameunit(sc->dev), i);
7123 	}
7124 
7125 	if (!(sc->flags & IS_VF)) {
7126 		write_global_rss_key(sc);
7127 		t4_intr_enable(sc);
7128 	}
7129 	return (0);
7130 }
7131 
7132 int
7133 adapter_init(struct adapter *sc)
7134 {
7135 	int rc;
7136 
7137 	ASSERT_SYNCHRONIZED_OP(sc);
7138 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
7139 	KASSERT((sc->flags & FULL_INIT_DONE) == 0,
7140 	    ("%s: FULL_INIT_DONE already", __func__));
7141 
7142 	rc = adapter_full_init(sc);
7143 	if (rc != 0)
7144 		adapter_full_uninit(sc);
7145 	else
7146 		sc->flags |= FULL_INIT_DONE;
7147 
7148 	return (rc);
7149 }
7150 
7151 /*
7152  * Idempotent.
7153  */
7154 static void
7155 adapter_full_uninit(struct adapter *sc)
7156 {
7157 	int i;
7158 
7159 	t4_teardown_adapter_queues(sc);
7160 
7161 	for (i = 0; i < nitems(sc->tq); i++) {
7162 		if (sc->tq[i] == NULL)
7163 			continue;
7164 		taskqueue_free(sc->tq[i]);
7165 		sc->tq[i] = NULL;
7166 	}
7167 
7168 	sc->flags &= ~FULL_INIT_DONE;
7169 }
7170 
7171 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
7172     RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
7173     RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
7174     RSS_HASHTYPE_RSS_UDP_IPV6)
7175 
7176 /* Translates kernel hash types to hardware. */
7177 static int
7178 hashconfig_to_hashen(int hashconfig)
7179 {
7180 	int hashen = 0;
7181 
7182 	if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
7183 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
7184 	if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
7185 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
7186 	if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
7187 		hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
7188 		    F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
7189 	}
7190 	if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
7191 		hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
7192 		    F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
7193 	}
7194 	if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
7195 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
7196 	if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
7197 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
7198 
7199 	return (hashen);
7200 }
7201 
7202 /* Translates hardware hash types to kernel. */
7203 static int
7204 hashen_to_hashconfig(int hashen)
7205 {
7206 	int hashconfig = 0;
7207 
7208 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
7209 		/*
7210 		 * If UDP hashing was enabled it must have been enabled for
7211 		 * either IPv4 or IPv6 (inclusive or).  Enabling UDP without
7212 		 * enabling any 4-tuple hash is nonsense configuration.
7213 		 */
7214 		MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
7215 		    F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
7216 
7217 		if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
7218 			hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
7219 		if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
7220 			hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
7221 	}
7222 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
7223 		hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
7224 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
7225 		hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
7226 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
7227 		hashconfig |= RSS_HASHTYPE_RSS_IPV4;
7228 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
7229 		hashconfig |= RSS_HASHTYPE_RSS_IPV6;
7230 
7231 	return (hashconfig);
7232 }
7233 
7234 /*
7235  * Idempotent.
7236  */
7237 static int
7238 vi_full_init(struct vi_info *vi)
7239 {
7240 	struct adapter *sc = vi->adapter;
7241 	struct sge_rxq *rxq;
7242 	int rc, i, j, extra;
7243 	int hashconfig = rss_gethashconfig();
7244 #ifdef RSS
7245 	int nbuckets = rss_getnumbuckets();
7246 #endif
7247 
7248 	ASSERT_SYNCHRONIZED_OP(sc);
7249 
7250 	/*
7251 	 * Allocate tx/rx/fl queues for this VI.
7252 	 */
7253 	rc = t4_setup_vi_queues(vi);
7254 	if (rc != 0)
7255 		return (rc);
7256 
7257 	/*
7258 	 * Setup RSS for this VI.  Save a copy of the RSS table for later use.
7259 	 */
7260 	if (vi->nrxq > vi->rss_size) {
7261 		CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); "
7262 		    "some queues will never receive traffic.\n", vi->nrxq,
7263 		    vi->rss_size);
7264 	} else if (vi->rss_size % vi->nrxq) {
7265 		CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); "
7266 		    "expect uneven traffic distribution.\n", vi->nrxq,
7267 		    vi->rss_size);
7268 	}
7269 #ifdef RSS
7270 	if (vi->nrxq != nbuckets) {
7271 		CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);"
7272 		    "performance will be impacted.\n", vi->nrxq, nbuckets);
7273 	}
7274 #endif
7275 	if (vi->rss == NULL)
7276 		vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE,
7277 		    M_ZERO | M_WAITOK);
7278 	for (i = 0; i < vi->rss_size;) {
7279 #ifdef RSS
7280 		j = rss_get_indirection_to_bucket(i);
7281 		j %= vi->nrxq;
7282 		rxq = &sc->sge.rxq[vi->first_rxq + j];
7283 		vi->rss[i++] = rxq->iq.abs_id;
7284 #else
7285 		for_each_rxq(vi, j, rxq) {
7286 			vi->rss[i++] = rxq->iq.abs_id;
7287 			if (i == vi->rss_size)
7288 				break;
7289 		}
7290 #endif
7291 	}
7292 
7293 	rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
7294 	    vi->rss, vi->rss_size);
7295 	if (rc != 0) {
7296 		CH_ERR(vi, "rss_config failed: %d\n", rc);
7297 		return (rc);
7298 	}
7299 
7300 	vi->hashen = hashconfig_to_hashen(hashconfig);
7301 
7302 	/*
7303 	 * We may have had to enable some hashes even though the global config
7304 	 * wants them disabled.  This is a potential problem that must be
7305 	 * reported to the user.
7306 	 */
7307 	extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
7308 
7309 	/*
7310 	 * If we consider only the supported hash types, then the enabled hashes
7311 	 * are a superset of the requested hashes.  In other words, there cannot
7312 	 * be any supported hash that was requested but not enabled, but there
7313 	 * can be hashes that were not requested but had to be enabled.
7314 	 */
7315 	extra &= SUPPORTED_RSS_HASHTYPES;
7316 	MPASS((extra & hashconfig) == 0);
7317 
7318 	if (extra) {
7319 		CH_ALERT(vi,
7320 		    "global RSS config (0x%x) cannot be accommodated.\n",
7321 		    hashconfig);
7322 	}
7323 	if (extra & RSS_HASHTYPE_RSS_IPV4)
7324 		CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n");
7325 	if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
7326 		CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n");
7327 	if (extra & RSS_HASHTYPE_RSS_IPV6)
7328 		CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n");
7329 	if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
7330 		CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n");
7331 	if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
7332 		CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n");
7333 	if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
7334 		CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n");
7335 
7336 	rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0],
7337 	    0, 0);
7338 	if (rc != 0) {
7339 		CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc);
7340 		return (rc);
7341 	}
7342 
7343 	return (0);
7344 }
7345 
7346 int
7347 vi_init(struct vi_info *vi)
7348 {
7349 	int rc;
7350 
7351 	ASSERT_SYNCHRONIZED_OP(vi->adapter);
7352 	KASSERT((vi->flags & VI_INIT_DONE) == 0,
7353 	    ("%s: VI_INIT_DONE already", __func__));
7354 
7355 	rc = vi_full_init(vi);
7356 	if (rc != 0)
7357 		vi_full_uninit(vi);
7358 	else
7359 		vi->flags |= VI_INIT_DONE;
7360 
7361 	return (rc);
7362 }
7363 
7364 /*
7365  * Idempotent.
7366  */
7367 static void
7368 vi_full_uninit(struct vi_info *vi)
7369 {
7370 
7371 	if (vi->flags & VI_INIT_DONE) {
7372 		quiesce_vi(vi);
7373 		free(vi->rss, M_CXGBE);
7374 		free(vi->nm_rss, M_CXGBE);
7375 	}
7376 
7377 	t4_teardown_vi_queues(vi);
7378 	vi->flags &= ~VI_INIT_DONE;
7379 }
7380 
7381 static void
7382 quiesce_txq(struct sge_txq *txq)
7383 {
7384 	struct sge_eq *eq = &txq->eq;
7385 	struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
7386 
7387 	MPASS(eq->flags & EQ_SW_ALLOCATED);
7388 	MPASS(!(eq->flags & EQ_ENABLED));
7389 
7390 	/* Wait for the mp_ring to empty. */
7391 	while (!mp_ring_is_idle(txq->r)) {
7392 		mp_ring_check_drainage(txq->r, 4096);
7393 		pause("rquiesce", 1);
7394 	}
7395 	MPASS(txq->txp.npkt == 0);
7396 
7397 	if (eq->flags & EQ_HW_ALLOCATED) {
7398 		/*
7399 		 * Hardware is alive and working normally.  Wait for it to
7400 		 * finish and then wait for the driver to catch up and reclaim
7401 		 * all descriptors.
7402 		 */
7403 		while (spg->cidx != htobe16(eq->pidx))
7404 			pause("equiesce", 1);
7405 		while (eq->cidx != eq->pidx)
7406 			pause("dquiesce", 1);
7407 	} else {
7408 		/*
7409 		 * Hardware is unavailable.  Discard all pending tx and reclaim
7410 		 * descriptors directly.
7411 		 */
7412 		TXQ_LOCK(txq);
7413 		while (eq->cidx != eq->pidx) {
7414 			struct mbuf *m, *nextpkt;
7415 			struct tx_sdesc *txsd;
7416 
7417 			txsd = &txq->sdesc[eq->cidx];
7418 			for (m = txsd->m; m != NULL; m = nextpkt) {
7419 				nextpkt = m->m_nextpkt;
7420 				m->m_nextpkt = NULL;
7421 				m_freem(m);
7422 			}
7423 			IDXINCR(eq->cidx, txsd->desc_used, eq->sidx);
7424 		}
7425 		spg->pidx = spg->cidx = htobe16(eq->cidx);
7426 		TXQ_UNLOCK(txq);
7427 	}
7428 }
7429 
7430 static void
7431 quiesce_wrq(struct sge_wrq *wrq)
7432 {
7433 	struct wrqe *wr;
7434 
7435 	TXQ_LOCK(wrq);
7436 	while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) {
7437 		STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
7438 #ifdef INVARIANTS
7439 		wrq->nwr_pending--;
7440 		wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE);
7441 #endif
7442 		free(wr, M_CXGBE);
7443 	}
7444 	MPASS(wrq->nwr_pending == 0);
7445 	MPASS(wrq->ndesc_needed == 0);
7446 	wrq->nwr_pending = 0;
7447 	wrq->ndesc_needed = 0;
7448 	TXQ_UNLOCK(wrq);
7449 }
7450 
7451 static void
7452 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
7453 {
7454 	/* Synchronize with the interrupt handler */
7455 	while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
7456 		pause("iqfree", 1);
7457 
7458 	if (fl != NULL) {
7459 		MPASS(iq->flags & IQ_HAS_FL);
7460 
7461 		mtx_lock(&sc->sfl_lock);
7462 		FL_LOCK(fl);
7463 		fl->flags |= FL_DOOMED;
7464 		FL_UNLOCK(fl);
7465 		callout_stop(&sc->sfl_callout);
7466 		mtx_unlock(&sc->sfl_lock);
7467 
7468 		KASSERT((fl->flags & FL_STARVING) == 0,
7469 		    ("%s: still starving", __func__));
7470 
7471 		/* Release all buffers if hardware is no longer available. */
7472 		if (!(iq->flags & IQ_HW_ALLOCATED))
7473 			free_fl_buffers(sc, fl);
7474 	}
7475 }
7476 
7477 /*
7478  * Wait for all activity on all the queues of the VI to complete.  It is assumed
7479  * that no new work is being enqueued by the hardware or the driver.  That part
7480  * should be arranged before calling this function.
7481  */
7482 static void
7483 quiesce_vi(struct vi_info *vi)
7484 {
7485 	int i;
7486 	struct adapter *sc = vi->adapter;
7487 	struct sge_rxq *rxq;
7488 	struct sge_txq *txq;
7489 #ifdef TCP_OFFLOAD
7490 	struct sge_ofld_rxq *ofld_rxq;
7491 #endif
7492 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7493 	struct sge_ofld_txq *ofld_txq;
7494 #endif
7495 
7496 	if (!(vi->flags & VI_INIT_DONE))
7497 		return;
7498 
7499 	for_each_txq(vi, i, txq) {
7500 		quiesce_txq(txq);
7501 	}
7502 
7503 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7504 	for_each_ofld_txq(vi, i, ofld_txq) {
7505 		quiesce_wrq(&ofld_txq->wrq);
7506 	}
7507 #endif
7508 
7509 	for_each_rxq(vi, i, rxq) {
7510 		quiesce_iq_fl(sc, &rxq->iq, &rxq->fl);
7511 	}
7512 
7513 #ifdef TCP_OFFLOAD
7514 	for_each_ofld_rxq(vi, i, ofld_rxq) {
7515 		quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl);
7516 	}
7517 #endif
7518 }
7519 
7520 static int
7521 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
7522     driver_intr_t *handler, void *arg, char *name)
7523 {
7524 	int rc;
7525 
7526 	irq->rid = rid;
7527 	irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
7528 	    RF_SHAREABLE | RF_ACTIVE);
7529 	if (irq->res == NULL) {
7530 		device_printf(sc->dev,
7531 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
7532 		return (ENOMEM);
7533 	}
7534 
7535 	rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
7536 	    NULL, handler, arg, &irq->tag);
7537 	if (rc != 0) {
7538 		device_printf(sc->dev,
7539 		    "failed to setup interrupt for rid %d, name %s: %d\n",
7540 		    rid, name, rc);
7541 	} else if (name)
7542 		bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
7543 
7544 	return (rc);
7545 }
7546 
7547 static int
7548 t4_free_irq(struct adapter *sc, struct irq *irq)
7549 {
7550 	if (irq->tag)
7551 		bus_teardown_intr(sc->dev, irq->res, irq->tag);
7552 	if (irq->res)
7553 		bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
7554 
7555 	bzero(irq, sizeof(*irq));
7556 
7557 	return (0);
7558 }
7559 
7560 static void
7561 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
7562 {
7563 
7564 	regs->version = chip_id(sc) | chip_rev(sc) << 10;
7565 	t4_get_regs(sc, buf, regs->len);
7566 }
7567 
7568 #define	A_PL_INDIR_CMD	0x1f8
7569 
7570 #define	S_PL_AUTOINC	31
7571 #define	M_PL_AUTOINC	0x1U
7572 #define	V_PL_AUTOINC(x)	((x) << S_PL_AUTOINC)
7573 #define	G_PL_AUTOINC(x)	(((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
7574 
7575 #define	S_PL_VFID	20
7576 #define	M_PL_VFID	0xffU
7577 #define	V_PL_VFID(x)	((x) << S_PL_VFID)
7578 #define	G_PL_VFID(x)	(((x) >> S_PL_VFID) & M_PL_VFID)
7579 
7580 #define	S_PL_ADDR	0
7581 #define	M_PL_ADDR	0xfffffU
7582 #define	V_PL_ADDR(x)	((x) << S_PL_ADDR)
7583 #define	G_PL_ADDR(x)	(((x) >> S_PL_ADDR) & M_PL_ADDR)
7584 
7585 #define	A_PL_INDIR_DATA	0x1fc
7586 
7587 static uint64_t
7588 read_vf_stat(struct adapter *sc, u_int vin, int reg)
7589 {
7590 	u32 stats[2];
7591 
7592 	if (sc->flags & IS_VF) {
7593 		stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
7594 		stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
7595 	} else {
7596 		mtx_assert(&sc->reg_lock, MA_OWNED);
7597 		t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
7598 		    V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
7599 		stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
7600 		stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
7601 	}
7602 	return (((uint64_t)stats[1]) << 32 | stats[0]);
7603 }
7604 
7605 static void
7606 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
7607 {
7608 
7609 #define GET_STAT(name) \
7610 	read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
7611 
7612 	if (!(sc->flags & IS_VF))
7613 		mtx_lock(&sc->reg_lock);
7614 	stats->tx_bcast_bytes    = GET_STAT(TX_VF_BCAST_BYTES);
7615 	stats->tx_bcast_frames   = GET_STAT(TX_VF_BCAST_FRAMES);
7616 	stats->tx_mcast_bytes    = GET_STAT(TX_VF_MCAST_BYTES);
7617 	stats->tx_mcast_frames   = GET_STAT(TX_VF_MCAST_FRAMES);
7618 	stats->tx_ucast_bytes    = GET_STAT(TX_VF_UCAST_BYTES);
7619 	stats->tx_ucast_frames   = GET_STAT(TX_VF_UCAST_FRAMES);
7620 	stats->tx_drop_frames    = GET_STAT(TX_VF_DROP_FRAMES);
7621 	stats->tx_offload_bytes  = GET_STAT(TX_VF_OFFLOAD_BYTES);
7622 	stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
7623 	stats->rx_bcast_bytes    = GET_STAT(RX_VF_BCAST_BYTES);
7624 	stats->rx_bcast_frames   = GET_STAT(RX_VF_BCAST_FRAMES);
7625 	stats->rx_mcast_bytes    = GET_STAT(RX_VF_MCAST_BYTES);
7626 	stats->rx_mcast_frames   = GET_STAT(RX_VF_MCAST_FRAMES);
7627 	stats->rx_ucast_bytes    = GET_STAT(RX_VF_UCAST_BYTES);
7628 	stats->rx_ucast_frames   = GET_STAT(RX_VF_UCAST_FRAMES);
7629 	stats->rx_err_frames     = GET_STAT(RX_VF_ERR_FRAMES);
7630 	if (!(sc->flags & IS_VF))
7631 		mtx_unlock(&sc->reg_lock);
7632 
7633 #undef GET_STAT
7634 }
7635 
7636 static void
7637 t4_clr_vi_stats(struct adapter *sc, u_int vin)
7638 {
7639 	int reg;
7640 
7641 	t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
7642 	    V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
7643 	for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
7644 	     reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
7645 		t4_write_reg(sc, A_PL_INDIR_DATA, 0);
7646 }
7647 
7648 static void
7649 vi_refresh_stats(struct vi_info *vi)
7650 {
7651 	struct timeval tv;
7652 	const struct timeval interval = {0, 250000};	/* 250ms */
7653 
7654 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7655 
7656 	if (vi->flags & VI_SKIP_STATS)
7657 		return;
7658 
7659 	getmicrotime(&tv);
7660 	timevalsub(&tv, &interval);
7661 	if (timevalcmp(&tv, &vi->last_refreshed, <))
7662 		return;
7663 
7664 	t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats);
7665 	getmicrotime(&vi->last_refreshed);
7666 }
7667 
7668 static void
7669 cxgbe_refresh_stats(struct vi_info *vi)
7670 {
7671 	u_int i, v, tnl_cong_drops, chan_map;
7672 	struct timeval tv;
7673 	const struct timeval interval = {0, 250000};	/* 250ms */
7674 	struct port_info *pi;
7675 	struct adapter *sc;
7676 
7677 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7678 
7679 	if (vi->flags & VI_SKIP_STATS)
7680 		return;
7681 
7682 	getmicrotime(&tv);
7683 	timevalsub(&tv, &interval);
7684 	if (timevalcmp(&tv, &vi->last_refreshed, <))
7685 		return;
7686 
7687 	pi = vi->pi;
7688 	sc = vi->adapter;
7689 	tnl_cong_drops = 0;
7690 	t4_get_port_stats(sc, pi->hw_port, &pi->stats);
7691 	chan_map = pi->rx_e_chan_map;
7692 	while (chan_map) {
7693 		i = ffs(chan_map) - 1;
7694 		mtx_lock(&sc->reg_lock);
7695 		t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
7696 		    A_TP_MIB_TNL_CNG_DROP_0 + i);
7697 		mtx_unlock(&sc->reg_lock);
7698 		tnl_cong_drops += v;
7699 		chan_map &= ~(1 << i);
7700 	}
7701 	pi->tnl_cong_drops = tnl_cong_drops;
7702 	getmicrotime(&vi->last_refreshed);
7703 }
7704 
7705 static void
7706 cxgbe_tick(void *arg)
7707 {
7708 	struct vi_info *vi = arg;
7709 
7710 	MPASS(IS_MAIN_VI(vi));
7711 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7712 
7713 	cxgbe_refresh_stats(vi);
7714 	callout_schedule(&vi->tick, hz);
7715 }
7716 
7717 static void
7718 vi_tick(void *arg)
7719 {
7720 	struct vi_info *vi = arg;
7721 
7722 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7723 
7724 	vi_refresh_stats(vi);
7725 	callout_schedule(&vi->tick, hz);
7726 }
7727 
7728 /* CIM inbound queues */
7729 static const char *t4_ibq[CIM_NUM_IBQ] = {
7730 	"ibq_tp0", "ibq_tp1", "ibq_ulp", "ibq_sge0", "ibq_sge1", "ibq_ncsi"
7731 };
7732 static const char *t7_ibq[CIM_NUM_IBQ_T7] = {
7733 	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
7734 	"ibq_sge1", "ibq_ncsi", NULL, "ibq_ipc1", "ibq_ipc2", "ibq_ipc3",
7735 	"ibq_ipc4", "ibq_ipc5", "ibq_ipc6", "ibq_ipc7"
7736 };
7737 static const char *t7_ibq_sec[] = {
7738 	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
7739 	NULL, NULL, NULL, "ibq_ipc0"
7740 };
7741 
7742 /* CIM outbound queues */
7743 static const char *t4_obq[CIM_NUM_OBQ_T5] = {
7744 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
7745 	"obq_sge_rx_q0", "obq_sge_rx_q1" /* These two are T5/T6 only */
7746 };
7747 static const char *t7_obq[CIM_NUM_OBQ_T7] = {
7748 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
7749 	"obq_sge_rx_q0", NULL, NULL, "obq_ipc1", "obq_ipc2", "obq_ipc3",
7750 	"obq_ipc4", "obq_ipc5", "obq_ipc6", "obq_ipc7"
7751 };
7752 static const char *t7_obq_sec[] = {
7753 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", NULL,
7754 	"obq_sge_rx_q0", NULL, NULL, "obq_ipc0"
7755 };
7756 
7757 static void
7758 cim_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
7759     struct sysctl_oid_list *c0)
7760 {
7761 	struct sysctl_oid *oid;
7762 	struct sysctl_oid_list *children1;
7763 	int i, j, qcount;
7764 	char s[16];
7765 	const char **qname;
7766 
7767 	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "cim",
7768 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM block");
7769 	c0 = SYSCTL_CHILDREN(oid);
7770 
7771 	SYSCTL_ADD_U8(ctx, c0, OID_AUTO, "ncores", CTLFLAG_RD, NULL,
7772 	    sc->params.ncores, "# of active CIM cores");
7773 
7774 	for (i = 0; i < sc->params.ncores; i++) {
7775 		snprintf(s, sizeof(s), "%u", i);
7776 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, s,
7777 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM core");
7778 		children1 = SYSCTL_CHILDREN(oid);
7779 
7780 		/*
7781 		 * CTLFLAG_SKIP because the misc.devlog sysctl already displays
7782 		 * the log for all cores.  Use this sysctl to get the log for a
7783 		 * particular core only.
7784 		 */
7785 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "devlog",
7786 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
7787 		    sc, i, sysctl_devlog, "A", "firmware's device log");
7788 
7789 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "loadavg",
7790 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7791 		    sysctl_loadavg, "A",
7792 		    "microprocessor load averages (select firmwares only)");
7793 
7794 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "qcfg",
7795 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7796 		    chip_id(sc) > CHELSIO_T6 ? sysctl_cim_qcfg_t7 : sysctl_cim_qcfg,
7797 		    "A", "Queue configuration");
7798 
7799 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "la",
7800 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7801 		    sysctl_cim_la, "A", "Logic analyzer");
7802 
7803 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "ma_la",
7804 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7805 		    sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
7806 
7807 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "pif_la",
7808 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7809 		    sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
7810 
7811 		/* IBQs */
7812 		switch (chip_id(sc)) {
7813 		case CHELSIO_T4:
7814 		case CHELSIO_T5:
7815 		case CHELSIO_T6:
7816 			qname = &t4_ibq[0];
7817 			qcount = nitems(t4_ibq);
7818 			break;
7819 		case CHELSIO_T7:
7820 		default:
7821 			if (i == 0) {
7822 				qname = &t7_ibq[0];
7823 				qcount = nitems(t7_ibq);
7824 			} else {
7825 				qname = &t7_ibq_sec[0];
7826 				qcount = nitems(t7_ibq_sec);
7827 			}
7828 			break;
7829 		}
7830 		MPASS(qcount <= sc->chip_params->cim_num_ibq);
7831 		for (j = 0; j < qcount; j++) {
7832 			if (qname[j] == NULL)
7833 				continue;
7834 			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
7835 			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7836 			    (i << 16) | j, sysctl_cim_ibq, "A", NULL);
7837 		}
7838 
7839 		/* OBQs */
7840 		switch (chip_id(sc)) {
7841 		case CHELSIO_T4:
7842 			qname = t4_obq;
7843 			qcount = CIM_NUM_OBQ;
7844 			break;
7845 		case CHELSIO_T5:
7846 		case CHELSIO_T6:
7847 			qname = t4_obq;
7848 			qcount = nitems(t4_obq);
7849 			break;
7850 		case CHELSIO_T7:
7851 		default:
7852 			if (i == 0) {
7853 				qname = t7_obq;
7854 				qcount = nitems(t7_obq);
7855 			} else {
7856 				qname = t7_obq_sec;
7857 				qcount = nitems(t7_obq_sec);
7858 			}
7859 			break;
7860 		}
7861 		MPASS(qcount <= sc->chip_params->cim_num_obq);
7862 		for (j = 0; j < qcount; j++) {
7863 			if (qname[j] == NULL)
7864 				continue;
7865 			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
7866 			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7867 			    (i << 16) | j, sysctl_cim_obq, "A", NULL);
7868 		}
7869 	}
7870 }
7871 
7872 /*
7873  * Should match fw_caps_config_<foo> enums in t4fw_interface.h
7874  */
7875 static char *caps_decoder[] = {
7876 	"\20\001IPMI\002NCSI",				/* 0: NBM */
7877 	"\20\001PPP\002QFC\003DCBX",			/* 1: link */
7878 	"\20\001INGRESS\002EGRESS",			/* 2: switch */
7879 	"\20\001NIC\002VM\003IDS\004UM\005UM_ISGL"	/* 3: NIC */
7880 	    "\006HASHFILTER\007ETHOFLD",
7881 	"\20\001TOE\002SENDPATH",			/* 4: TOE */
7882 	"\20\001RDDP\002RDMAC\003ROCEv2",		/* 5: RDMA */
7883 	"\20\001INITIATOR_PDU\002TARGET_PDU"		/* 6: iSCSI */
7884 	    "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
7885 	    "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
7886 	    "\007T10DIF"
7887 	    "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
7888 	"\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE"	/* 7: Crypto */
7889 	    "\004TLS_HW,\005TOE_IPSEC",
7890 	"\20\001INITIATOR\002TARGET\003CTRL_OFLD"	/* 8: FCoE */
7891 		    "\004PO_INITIATOR\005PO_TARGET",
7892 	"\20\001NVMe_TCP",				/* 9: NVMe */
7893 };
7894 
7895 void
7896 t4_sysctls(struct adapter *sc)
7897 {
7898 	struct sysctl_ctx_list *ctx = &sc->ctx;
7899 	struct sysctl_oid *oid;
7900 	struct sysctl_oid_list *children, *c0;
7901 	static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
7902 
7903 	/*
7904 	 * dev.t4nex.X.
7905 	 */
7906 	oid = device_get_sysctl_tree(sc->dev);
7907 	c0 = children = SYSCTL_CHILDREN(oid);
7908 
7909 	sc->sc_do_rxcopy = 1;
7910 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
7911 	    &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
7912 
7913 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
7914 	    sc->params.nports, "# of ports");
7915 
7916 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
7917 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells,
7918 	    (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A",
7919 	    "available doorbells");
7920 
7921 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
7922 	    sc->params.vpd.cclk, "core clock frequency (in KHz)");
7923 
7924 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
7925 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7926 	    sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val),
7927 	    sysctl_int_array, "A", "interrupt holdoff timer values (us)");
7928 
7929 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
7930 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7931 	    sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val),
7932 	    sysctl_int_array, "A", "interrupt holdoff packet counter values");
7933 
7934 	t4_sge_sysctls(sc, ctx, children);
7935 
7936 	sc->lro_timeout = 100;
7937 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
7938 	    &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
7939 
7940 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
7941 	    &sc->debug_flags, 0, "flags to enable runtime debugging");
7942 
7943 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iflags", CTLFLAG_RW,
7944 	    &sc->intr_flags, 0, "flags for the slow interrupt handler");
7945 
7946 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
7947 	    CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
7948 
7949 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
7950 	    CTLFLAG_RD, sc->fw_version, 0, "firmware version");
7951 
7952 	if (sc->flags & IS_VF)
7953 		return;
7954 
7955 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
7956 	    NULL, chip_rev(sc), "chip hardware revision");
7957 
7958 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
7959 	    CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
7960 
7961 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
7962 	    CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
7963 
7964 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
7965 	    CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
7966 
7967 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
7968 	    CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
7969 
7970 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
7971 	    CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
7972 
7973 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
7974 	    sc->er_version, 0, "expansion ROM version");
7975 
7976 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
7977 	    sc->bs_version, 0, "bootstrap firmware version");
7978 
7979 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
7980 	    NULL, sc->params.scfg_vers, "serial config version");
7981 
7982 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
7983 	    NULL, sc->params.vpd_vers, "VPD version");
7984 
7985 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
7986 	    CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
7987 
7988 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
7989 	    sc->cfcsum, "config file checksum");
7990 
7991 #define SYSCTL_CAP(name, n, text) \
7992 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
7993 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \
7994 	    (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \
7995 	    "available " text " capabilities")
7996 
7997 	SYSCTL_CAP(nbmcaps, 0, "NBM");
7998 	SYSCTL_CAP(linkcaps, 1, "link");
7999 	SYSCTL_CAP(switchcaps, 2, "switch");
8000 	SYSCTL_CAP(nvmecaps, 9, "NVMe");
8001 	SYSCTL_CAP(niccaps, 3, "NIC");
8002 	SYSCTL_CAP(toecaps, 4, "TCP offload");
8003 	SYSCTL_CAP(rdmacaps, 5, "RDMA");
8004 	SYSCTL_CAP(iscsicaps, 6, "iSCSI");
8005 	SYSCTL_CAP(cryptocaps, 7, "crypto");
8006 	SYSCTL_CAP(fcoecaps, 8, "FCoE");
8007 #undef SYSCTL_CAP
8008 
8009 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
8010 	    NULL, sc->tids.nftids, "number of filters");
8011 
8012 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "nipsec_tunnel", CTLFLAG_RD,
8013 	    NULL, sc->params.nipsec_tunnel, "max hw IPsec tunnels");
8014 
8015 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "nipsec_transport", CTLFLAG_RD,
8016 	    NULL, sc->params.nipsec_transport, "max hw IPsec transport pairs");
8017 
8018 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "nofld_ipsec_tunnel", CTLFLAG_RD,
8019 	    NULL, sc->params.nofld_ipsec_tunnel, "max hw IPsec tunnels (TOE)");
8020 
8021 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
8022 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8023 	    sysctl_temperature, "I", "chip temperature (in Celsius)");
8024 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor",
8025 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
8026 	    sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
8027 
8028 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
8029 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd,
8030 	    "I", "core Vdd (in mV)");
8031 
8032 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
8033 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS,
8034 	    sysctl_cpus, "A", "local CPUs");
8035 
8036 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
8037 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS,
8038 	    sysctl_cpus, "A", "preferred CPUs for interrupts");
8039 
8040 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
8041 	    &sc->swintr, 0, "software triggered interrupts");
8042 
8043 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset",
8044 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I",
8045 	    "1 = reset adapter, 0 = zero reset counter");
8046 
8047 	/*
8048 	 * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
8049 	 */
8050 	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
8051 	    CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL,
8052 	    "logs and miscellaneous information");
8053 	children = SYSCTL_CHILDREN(oid);
8054 
8055 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
8056 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8057 	    sysctl_cctrl, "A", "congestion control");
8058 
8059 	cim_sysctls(sc, ctx, children);
8060 
8061 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
8062 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8063 	    sysctl_cpl_stats, "A", "CPL statistics");
8064 
8065 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
8066 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8067 	    sysctl_ddp_stats, "A", "non-TCP DDP statistics");
8068 
8069 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats",
8070 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8071 	    sysctl_tid_stats, "A", "tid stats");
8072 
8073 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
8074 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, -1,
8075 	    sysctl_devlog, "A", "firmware's device log (all cores)");
8076 
8077 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
8078 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8079 	    sysctl_fcoe_stats, "A", "FCoE statistics");
8080 
8081 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
8082 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8083 	    sysctl_hw_sched, "A", "hardware scheduler ");
8084 
8085 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
8086 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8087 	    sysctl_l2t, "A", "hardware L2 table");
8088 
8089 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
8090 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8091 	    sysctl_smt, "A", "hardware source MAC table");
8092 
8093 #ifdef INET6
8094 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
8095 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8096 	    sysctl_clip, "A", "active CLIP table entries");
8097 #endif
8098 
8099 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
8100 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8101 	    sysctl_lb_stats, "A", "loopback statistics");
8102 
8103 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
8104 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8105 	    sysctl_meminfo, "A", "memory regions");
8106 
8107 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
8108 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8109 	    chip_id(sc) >= CHELSIO_T7 ? sysctl_mps_tcam_t7 :
8110 	    (chip_id(sc) >= CHELSIO_T6 ? sysctl_mps_tcam_t6 : sysctl_mps_tcam),
8111 	    "A", "MPS TCAM entries");
8112 
8113 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
8114 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8115 	    sysctl_path_mtus, "A", "path MTUs");
8116 
8117 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
8118 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8119 	    sysctl_pm_stats, "A", "PM statistics");
8120 
8121 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
8122 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8123 	    sysctl_rdma_stats, "A", "RDMA statistics");
8124 
8125 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
8126 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8127 	    sysctl_tcp_stats, "A", "TCP statistics");
8128 
8129 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
8130 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8131 	    sysctl_tids, "A", "TID information");
8132 
8133 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
8134 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8135 	    sysctl_tp_err_stats, "A", "TP error statistics");
8136 
8137 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats",
8138 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8139 	    sysctl_tnl_stats, "A", "TP tunnel statistics");
8140 
8141 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
8142 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
8143 	    sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask");
8144 
8145 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
8146 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8147 	    sysctl_tp_la, "A", "TP logic analyzer");
8148 
8149 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
8150 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8151 	    sysctl_tx_rate, "A", "Tx rate");
8152 
8153 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
8154 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8155 	    sysctl_ulprx_la, "A", "ULPRX logic analyzer");
8156 
8157 	if (chip_id(sc) >= CHELSIO_T5) {
8158 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
8159 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8160 		    sysctl_wcwr_stats, "A", "write combined work requests");
8161 	}
8162 
8163 	if (chip_id(sc) >= CHELSIO_T7) {
8164 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcb_cache",
8165 		    CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tcb_cache, "I",
8166 		    "1 = enabled (default), 0 = disabled (for debug only)");
8167 	}
8168 
8169 #ifdef KERN_TLS
8170 	if (is_ktls(sc)) {
8171 		/*
8172 		 * dev.t4nex.0.tls.
8173 		 */
8174 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls",
8175 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters");
8176 		children = SYSCTL_CHILDREN(oid);
8177 
8178 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
8179 		    CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
8180 		    "keys in work requests (1) or attempt to store TLS keys "
8181 		    "in card memory.");
8182 
8183 		if (is_t6(sc))
8184 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
8185 			    CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to "
8186 			    "combine TCB field updates with TLS record work "
8187 			    "requests.");
8188 		else {
8189 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "short_records",
8190 			    CTLFLAG_RW, &sc->tlst.short_records, 0,
8191 			    "Use cipher-only mode for short records.");
8192 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "partial_ghash",
8193 			    CTLFLAG_RW, &sc->tlst.partial_ghash, 0,
8194 			    "Use partial GHASH for AES-GCM records.");
8195 		}
8196 	}
8197 #endif
8198 
8199 #ifdef TCP_OFFLOAD
8200 	if (is_offload(sc)) {
8201 		int i;
8202 		char s[4];
8203 
8204 		/*
8205 		 * dev.t4nex.X.toe.
8206 		 */
8207 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe",
8208 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters");
8209 		children = SYSCTL_CHILDREN(oid);
8210 
8211 		sc->tt.cong_algorithm = -1;
8212 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
8213 		    CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
8214 		    "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
8215 		    "3 = highspeed)");
8216 
8217 		sc->tt.sndbuf = -1;
8218 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
8219 		    &sc->tt.sndbuf, 0, "hardware send buffer");
8220 
8221 		sc->tt.ddp = 0;
8222 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
8223 		    CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
8224 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
8225 		    &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
8226 
8227 		sc->tt.rx_coalesce = -1;
8228 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
8229 		    CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
8230 
8231 		sc->tt.tls = 1;
8232 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT |
8233 		    CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I",
8234 		    "Inline TLS allowed");
8235 
8236 		sc->tt.tx_align = -1;
8237 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
8238 		    CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
8239 
8240 		sc->tt.tx_zcopy = 0;
8241 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
8242 		    CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
8243 		    "Enable zero-copy aio_write(2)");
8244 
8245 		sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
8246 		SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8247 		    "cop_managed_offloading", CTLFLAG_RW,
8248 		    &sc->tt.cop_managed_offloading, 0,
8249 		    "COP (Connection Offload Policy) controls all TOE offload");
8250 
8251 		sc->tt.autorcvbuf_inc = 16 * 1024;
8252 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
8253 		    CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
8254 		    "autorcvbuf increment");
8255 
8256 		sc->tt.update_hc_on_pmtu_change = 1;
8257 		SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8258 		    "update_hc_on_pmtu_change", CTLFLAG_RW,
8259 		    &sc->tt.update_hc_on_pmtu_change, 0,
8260 		    "Update hostcache entry if the PMTU changes");
8261 
8262 		sc->tt.iso = 1;
8263 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW,
8264 		    &sc->tt.iso, 0, "Enable iSCSI segmentation offload");
8265 
8266 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
8267 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8268 		    sysctl_tp_tick, "A", "TP timer tick (us)");
8269 
8270 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
8271 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
8272 		    sysctl_tp_tick, "A", "TCP timestamp tick (us)");
8273 
8274 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
8275 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
8276 		    sysctl_tp_tick, "A", "DACK tick (us)");
8277 
8278 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
8279 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8280 		    sysctl_tp_dack_timer, "IU", "DACK timer (us)");
8281 
8282 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
8283 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8284 		    A_TP_RXT_MIN, sysctl_tp_timer, "LU",
8285 		    "Minimum retransmit interval (us)");
8286 
8287 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
8288 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8289 		    A_TP_RXT_MAX, sysctl_tp_timer, "LU",
8290 		    "Maximum retransmit interval (us)");
8291 
8292 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
8293 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8294 		    A_TP_PERS_MIN, sysctl_tp_timer, "LU",
8295 		    "Persist timer min (us)");
8296 
8297 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
8298 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8299 		    A_TP_PERS_MAX, sysctl_tp_timer, "LU",
8300 		    "Persist timer max (us)");
8301 
8302 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
8303 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8304 		    A_TP_KEEP_IDLE, sysctl_tp_timer, "LU",
8305 		    "Keepalive idle timer (us)");
8306 
8307 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
8308 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8309 		    A_TP_KEEP_INTVL, sysctl_tp_timer, "LU",
8310 		    "Keepalive interval timer (us)");
8311 
8312 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
8313 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8314 		    A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)");
8315 
8316 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
8317 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8318 		    A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU",
8319 		    "FINWAIT2 timer (us)");
8320 
8321 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
8322 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8323 		    S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU",
8324 		    "Number of SYN retransmissions before abort");
8325 
8326 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
8327 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8328 		    S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU",
8329 		    "Number of retransmissions before abort");
8330 
8331 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
8332 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8333 		    S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU",
8334 		    "Number of keepalive probes before abort");
8335 
8336 		oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
8337 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8338 		    "TOE retransmit backoffs");
8339 		children = SYSCTL_CHILDREN(oid);
8340 		for (i = 0; i < 16; i++) {
8341 			snprintf(s, sizeof(s), "%u", i);
8342 			SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
8343 			    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8344 			    i, sysctl_tp_backoff, "IU",
8345 			    "TOE retransmit backoff");
8346 		}
8347 	}
8348 #endif
8349 }
8350 
8351 void
8352 vi_sysctls(struct vi_info *vi)
8353 {
8354 	struct sysctl_ctx_list *ctx = &vi->ctx;
8355 	struct sysctl_oid *oid;
8356 	struct sysctl_oid_list *children;
8357 
8358 	/*
8359 	 * dev.v?(cxgbe|cxl).X.
8360 	 */
8361 	oid = device_get_sysctl_tree(vi->dev);
8362 	children = SYSCTL_CHILDREN(oid);
8363 
8364 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
8365 	    vi->viid, "VI identifer");
8366 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
8367 	    &vi->nrxq, 0, "# of rx queues");
8368 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
8369 	    &vi->ntxq, 0, "# of tx queues");
8370 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
8371 	    &vi->first_rxq, 0, "index of first rx queue");
8372 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
8373 	    &vi->first_txq, 0, "index of first tx queue");
8374 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
8375 	    vi->rss_base, "start of RSS indirection table");
8376 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
8377 	    vi->rss_size, "size of RSS indirection table");
8378 
8379 	if (IS_MAIN_VI(vi)) {
8380 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
8381 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8382 		    sysctl_noflowq, "IU",
8383 		    "Reserve queue 0 for non-flowid packets");
8384 	}
8385 
8386 	if (vi->adapter->flags & IS_VF) {
8387 		MPASS(vi->flags & TX_USES_VM_WR);
8388 		SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD,
8389 		    NULL, 1, "use VM work requests for transmit");
8390 	} else {
8391 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr",
8392 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8393 		    sysctl_tx_vm_wr, "I", "use VM work requestes for transmit");
8394 	}
8395 
8396 #ifdef TCP_OFFLOAD
8397 	if (vi->nofldrxq != 0) {
8398 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
8399 		    &vi->nofldrxq, 0,
8400 		    "# of rx queues for offloaded TCP connections");
8401 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
8402 		    CTLFLAG_RD, &vi->first_ofld_rxq, 0,
8403 		    "index of first TOE rx queue");
8404 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
8405 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8406 		    sysctl_holdoff_tmr_idx_ofld, "I",
8407 		    "holdoff timer index for TOE queues");
8408 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
8409 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8410 		    sysctl_holdoff_pktc_idx_ofld, "I",
8411 		    "holdoff packet counter index for TOE queues");
8412 	}
8413 #endif
8414 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
8415 	if (vi->nofldtxq != 0) {
8416 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
8417 		    &vi->nofldtxq, 0,
8418 		    "# of tx queues for TOE/ETHOFLD");
8419 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
8420 		    CTLFLAG_RD, &vi->first_ofld_txq, 0,
8421 		    "index of first TOE/ETHOFLD tx queue");
8422 	}
8423 #endif
8424 #ifdef DEV_NETMAP
8425 	if (vi->nnmrxq != 0) {
8426 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
8427 		    &vi->nnmrxq, 0, "# of netmap rx queues");
8428 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
8429 		    &vi->nnmtxq, 0, "# of netmap tx queues");
8430 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
8431 		    CTLFLAG_RD, &vi->first_nm_rxq, 0,
8432 		    "index of first netmap rx queue");
8433 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
8434 		    CTLFLAG_RD, &vi->first_nm_txq, 0,
8435 		    "index of first netmap tx queue");
8436 	}
8437 #endif
8438 
8439 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
8440 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8441 	    sysctl_holdoff_tmr_idx, "I", "holdoff timer index");
8442 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
8443 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8444 	    sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index");
8445 
8446 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
8447 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8448 	    sysctl_qsize_rxq, "I", "rx queue size");
8449 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
8450 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8451 	    sysctl_qsize_txq, "I", "tx queue size");
8452 }
8453 
8454 static void
8455 cxgbe_sysctls(struct port_info *pi)
8456 {
8457 	struct sysctl_ctx_list *ctx = &pi->ctx;
8458 	struct sysctl_oid *oid;
8459 	struct sysctl_oid_list *children, *children2;
8460 	struct adapter *sc = pi->adapter;
8461 	int i;
8462 	char name[16];
8463 	static char *tc_flags = {"\20\1USER"};
8464 
8465 	/*
8466 	 * dev.cxgbe.X.
8467 	 */
8468 	oid = device_get_sysctl_tree(pi->dev);
8469 	children = SYSCTL_CHILDREN(oid);
8470 
8471 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc",
8472 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
8473 	    sysctl_linkdnrc, "A", "reason why link is down");
8474 	if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
8475 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
8476 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
8477 		    sysctl_btphy, "I", "PHY temperature (in Celsius)");
8478 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
8479 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1,
8480 		    sysctl_btphy, "I", "PHY firmware version");
8481 	}
8482 
8483 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
8484 	    CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8485 	    sysctl_pause_settings, "A",
8486 	    "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
8487 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec",
8488 	    CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A",
8489 	    "FEC in use on the link");
8490 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec",
8491 	    CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8492 	    sysctl_requested_fec, "A",
8493 	    "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
8494 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
8495 	    CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A",
8496 	    "FEC recommended by the cable/transceiver");
8497 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
8498 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8499 	    sysctl_autoneg, "I",
8500 	    "autonegotiation (-1 = not supported)");
8501 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec",
8502 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8503 	    sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config");
8504 
8505 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD,
8506 	    &pi->link_cfg.requested_caps, 0, "L1 config requested by driver");
8507 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
8508 	    &pi->link_cfg.pcaps, 0, "port capabilities");
8509 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
8510 	    &pi->link_cfg.acaps, 0, "advertised capabilities");
8511 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
8512 	    &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
8513 
8514 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
8515 	    port_top_speed(pi), "max speed (in Gbps)");
8516 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
8517 	    pi->mps_bg_map, "MPS buffer group map");
8518 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
8519 	    NULL, pi->rx_e_chan_map, "TP rx e-channel map");
8520 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL,
8521 	    pi->tx_chan, "TP tx c-channel");
8522 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL,
8523 	    pi->rx_chan, "TP rx c-channel");
8524 
8525 	if (sc->flags & IS_VF)
8526 		return;
8527 
8528 	/*
8529 	 * dev.(cxgbe|cxl).X.tc.
8530 	 */
8531 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc",
8532 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8533 	    "Tx scheduler traffic classes (cl_rl)");
8534 	children2 = SYSCTL_CHILDREN(oid);
8535 	SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
8536 	    CTLFLAG_RW, &pi->sched_params->pktsize, 0,
8537 	    "pktsize for per-flow cl-rl (0 means up to the driver )");
8538 	SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
8539 	    CTLFLAG_RW, &pi->sched_params->burstsize, 0,
8540 	    "burstsize for per-flow cl-rl (0 means up to the driver)");
8541 	for (i = 0; i < sc->params.nsched_cls; i++) {
8542 		struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
8543 
8544 		snprintf(name, sizeof(name), "%d", i);
8545 		children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
8546 		    SYSCTL_CHILDREN(oid), OID_AUTO, name,
8547 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class"));
8548 		SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state",
8549 		    CTLFLAG_RD, &tc->state, 0, "current state");
8550 		SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
8551 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags,
8552 		    (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags");
8553 		SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
8554 		    CTLFLAG_RD, &tc->refcount, 0, "references to this class");
8555 		SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
8556 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8557 		    (pi->port_id << 16) | i, sysctl_tc_params, "A",
8558 		    "traffic class parameters");
8559 	}
8560 
8561 	/*
8562 	 * dev.cxgbe.X.stats.
8563 	 */
8564 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
8565 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics");
8566 	children = SYSCTL_CHILDREN(oid);
8567 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
8568 	    &pi->tx_parse_error, 0,
8569 	    "# of tx packets with invalid length or # of segments");
8570 
8571 #define T4_LBSTAT(name, stat, desc) do { \
8572 	if (sc->params.tp.lb_mode) { \
8573 		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8574 		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, \
8575 		    A_MPS_PORT_STAT_##stat##_L, \
8576 		    sysctl_handle_t4_portstat64, "QU", desc); \
8577 	} else { \
8578 		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8579 		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8580 		    t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \
8581 		    sysctl_handle_t4_reg64, "QU", desc); \
8582 	} \
8583 } while (0)
8584 
8585 	T4_LBSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
8586 	T4_LBSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
8587 	T4_LBSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
8588 	T4_LBSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
8589 	T4_LBSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
8590 	T4_LBSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
8591 	T4_LBSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
8592 	T4_LBSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
8593 	T4_LBSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
8594 	T4_LBSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
8595 	T4_LBSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
8596 	T4_LBSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
8597 	T4_LBSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
8598 	T4_LBSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
8599 	T4_LBSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
8600 	T4_LBSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
8601 	T4_LBSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
8602 	T4_LBSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
8603 	T4_LBSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
8604 	T4_LBSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
8605 	T4_LBSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
8606 	T4_LBSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
8607 	T4_LBSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
8608 
8609 	T4_LBSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
8610 	T4_LBSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
8611 	T4_LBSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
8612 	T4_LBSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
8613 	T4_LBSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
8614 	T4_LBSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
8615 	T4_LBSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
8616 	if (is_t6(sc)) {
8617 		/* Read from port_stats and may be stale by up to 1s */
8618 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rx_fcs_err",
8619 		    CTLFLAG_RD, &pi->stats.rx_fcs_err,
8620 		    "# of frames received with bad FCS since last link up");
8621 	} else {
8622 		T4_LBSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
8623 		    "# of frames received with bad FCS");
8624 	}
8625 	T4_LBSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
8626 	T4_LBSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
8627 	T4_LBSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
8628 	T4_LBSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
8629 	T4_LBSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
8630 	T4_LBSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
8631 	T4_LBSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
8632 	T4_LBSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
8633 	T4_LBSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
8634 	T4_LBSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
8635 	T4_LBSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
8636 	T4_LBSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
8637 	T4_LBSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
8638 	T4_LBSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
8639 	T4_LBSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
8640 	T4_LBSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
8641 	T4_LBSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
8642 	T4_LBSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
8643 	T4_LBSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
8644 #undef T4_LBSTAT
8645 
8646 #define T4_REGSTAT(name, stat, desc) do { \
8647 	SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8648 	    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8649 	    A_MPS_STAT_##stat##_L, sysctl_handle_t4_reg64, "QU", desc); \
8650 } while (0)
8651 
8652 	if (pi->mps_bg_map & 1) {
8653 		T4_REGSTAT(rx_ovflow0, RX_BG_0_MAC_DROP_FRAME,
8654 		    "# drops due to buffer-group 0 overflows");
8655 		T4_REGSTAT(rx_trunc0, RX_BG_0_MAC_TRUNC_FRAME,
8656 		    "# of buffer-group 0 truncated packets");
8657 	}
8658 	if (pi->mps_bg_map & 2) {
8659 		T4_REGSTAT(rx_ovflow1, RX_BG_1_MAC_DROP_FRAME,
8660 		    "# drops due to buffer-group 1 overflows");
8661 		T4_REGSTAT(rx_trunc1, RX_BG_1_MAC_TRUNC_FRAME,
8662 		    "# of buffer-group 1 truncated packets");
8663 	}
8664 	if (pi->mps_bg_map & 4) {
8665 		T4_REGSTAT(rx_ovflow2, RX_BG_2_MAC_DROP_FRAME,
8666 		    "# drops due to buffer-group 2 overflows");
8667 		T4_REGSTAT(rx_trunc2, RX_BG_2_MAC_TRUNC_FRAME,
8668 		    "# of buffer-group 2 truncated packets");
8669 	}
8670 	if (pi->mps_bg_map & 8) {
8671 		T4_REGSTAT(rx_ovflow3, RX_BG_3_MAC_DROP_FRAME,
8672 		    "# drops due to buffer-group 3 overflows");
8673 		T4_REGSTAT(rx_trunc3, RX_BG_3_MAC_TRUNC_FRAME,
8674 		    "# of buffer-group 3 truncated packets");
8675 	}
8676 #undef T4_REGSTAT
8677 }
8678 
8679 static int
8680 sysctl_int_array(SYSCTL_HANDLER_ARGS)
8681 {
8682 	int rc, *i, space = 0;
8683 	struct sbuf sb;
8684 
8685 	sbuf_new_for_sysctl(&sb, NULL, 64, req);
8686 	for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
8687 		if (space)
8688 			sbuf_printf(&sb, " ");
8689 		sbuf_printf(&sb, "%d", *i);
8690 		space = 1;
8691 	}
8692 	rc = sbuf_finish(&sb);
8693 	sbuf_delete(&sb);
8694 	return (rc);
8695 }
8696 
8697 static int
8698 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
8699 {
8700 	int rc;
8701 	struct sbuf *sb;
8702 
8703 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8704 	if (sb == NULL)
8705 		return (ENOMEM);
8706 
8707 	sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
8708 	rc = sbuf_finish(sb);
8709 	sbuf_delete(sb);
8710 
8711 	return (rc);
8712 }
8713 
8714 static int
8715 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
8716 {
8717 	int rc;
8718 	struct sbuf *sb;
8719 
8720 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8721 	if (sb == NULL)
8722 		return (ENOMEM);
8723 
8724 	sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
8725 	rc = sbuf_finish(sb);
8726 	sbuf_delete(sb);
8727 
8728 	return (rc);
8729 }
8730 
8731 static int
8732 sysctl_btphy(SYSCTL_HANDLER_ARGS)
8733 {
8734 	struct port_info *pi = arg1;
8735 	int op = arg2;
8736 	struct adapter *sc = pi->adapter;
8737 	u_int v;
8738 	int rc;
8739 
8740 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
8741 	if (rc)
8742 		return (rc);
8743 	if (!hw_all_ok(sc))
8744 		rc = ENXIO;
8745 	else {
8746 		/* XXX: magic numbers */
8747 		rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e,
8748 		    op ? 0x20 : 0xc820, &v);
8749 	}
8750 	end_synchronized_op(sc, 0);
8751 	if (rc)
8752 		return (rc);
8753 	if (op == 0)
8754 		v /= 256;
8755 
8756 	rc = sysctl_handle_int(oidp, &v, 0, req);
8757 	return (rc);
8758 }
8759 
8760 static int
8761 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
8762 {
8763 	struct vi_info *vi = arg1;
8764 	int rc, val;
8765 
8766 	val = vi->rsrv_noflowq;
8767 	rc = sysctl_handle_int(oidp, &val, 0, req);
8768 	if (rc != 0 || req->newptr == NULL)
8769 		return (rc);
8770 
8771 	if ((val >= 1) && (vi->ntxq > 1))
8772 		vi->rsrv_noflowq = 1;
8773 	else
8774 		vi->rsrv_noflowq = 0;
8775 
8776 	return (rc);
8777 }
8778 
8779 static int
8780 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)
8781 {
8782 	struct vi_info *vi = arg1;
8783 	struct adapter *sc = vi->adapter;
8784 	int rc, val, i;
8785 
8786 	MPASS(!(sc->flags & IS_VF));
8787 
8788 	val = vi->flags & TX_USES_VM_WR ? 1 : 0;
8789 	rc = sysctl_handle_int(oidp, &val, 0, req);
8790 	if (rc != 0 || req->newptr == NULL)
8791 		return (rc);
8792 
8793 	if (val != 0 && val != 1)
8794 		return (EINVAL);
8795 
8796 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8797 	    "t4txvm");
8798 	if (rc)
8799 		return (rc);
8800 	if (!hw_all_ok(sc))
8801 		rc = ENXIO;
8802 	else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) {
8803 		/*
8804 		 * We don't want parse_pkt to run with one setting (VF or PF)
8805 		 * and then eth_tx to see a different setting but still use
8806 		 * stale information calculated by parse_pkt.
8807 		 */
8808 		rc = EBUSY;
8809 	} else {
8810 		struct port_info *pi = vi->pi;
8811 		struct sge_txq *txq;
8812 		uint32_t ctrl0;
8813 		uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr;
8814 
8815 		if (val) {
8816 			vi->flags |= TX_USES_VM_WR;
8817 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO);
8818 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8819 			    V_TXPKT_INTF(pi->hw_port));
8820 			if (!(sc->flags & IS_VF))
8821 				npkt--;
8822 		} else {
8823 			vi->flags &= ~TX_USES_VM_WR;
8824 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO);
8825 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8826 			    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
8827 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
8828 		}
8829 		for_each_txq(vi, i, txq) {
8830 			txq->cpl_ctrl0 = ctrl0;
8831 			txq->txp.max_npkt = npkt;
8832 		}
8833 	}
8834 	end_synchronized_op(sc, LOCK_HELD);
8835 	return (rc);
8836 }
8837 
8838 static int
8839 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
8840 {
8841 	struct vi_info *vi = arg1;
8842 	struct adapter *sc = vi->adapter;
8843 	int idx, rc, i;
8844 	struct sge_rxq *rxq;
8845 	uint8_t v;
8846 
8847 	idx = vi->tmr_idx;
8848 
8849 	rc = sysctl_handle_int(oidp, &idx, 0, req);
8850 	if (rc != 0 || req->newptr == NULL)
8851 		return (rc);
8852 
8853 	if (idx < 0 || idx >= SGE_NTIMERS)
8854 		return (EINVAL);
8855 
8856 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8857 	    "t4tmr");
8858 	if (rc)
8859 		return (rc);
8860 
8861 	v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
8862 	for_each_rxq(vi, i, rxq) {
8863 #ifdef atomic_store_rel_8
8864 		atomic_store_rel_8(&rxq->iq.intr_params, v);
8865 #else
8866 		rxq->iq.intr_params = v;
8867 #endif
8868 	}
8869 	vi->tmr_idx = idx;
8870 
8871 	end_synchronized_op(sc, LOCK_HELD);
8872 	return (0);
8873 }
8874 
8875 static int
8876 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
8877 {
8878 	struct vi_info *vi = arg1;
8879 	struct adapter *sc = vi->adapter;
8880 	int idx, rc;
8881 
8882 	idx = vi->pktc_idx;
8883 
8884 	rc = sysctl_handle_int(oidp, &idx, 0, req);
8885 	if (rc != 0 || req->newptr == NULL)
8886 		return (rc);
8887 
8888 	if (idx < -1 || idx >= SGE_NCOUNTERS)
8889 		return (EINVAL);
8890 
8891 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8892 	    "t4pktc");
8893 	if (rc)
8894 		return (rc);
8895 
8896 	if (vi->flags & VI_INIT_DONE)
8897 		rc = EBUSY; /* cannot be changed once the queues are created */
8898 	else
8899 		vi->pktc_idx = idx;
8900 
8901 	end_synchronized_op(sc, LOCK_HELD);
8902 	return (rc);
8903 }
8904 
8905 static int
8906 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
8907 {
8908 	struct vi_info *vi = arg1;
8909 	struct adapter *sc = vi->adapter;
8910 	int qsize, rc;
8911 
8912 	qsize = vi->qsize_rxq;
8913 
8914 	rc = sysctl_handle_int(oidp, &qsize, 0, req);
8915 	if (rc != 0 || req->newptr == NULL)
8916 		return (rc);
8917 
8918 	if (qsize < 128 || (qsize & 7))
8919 		return (EINVAL);
8920 
8921 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8922 	    "t4rxqs");
8923 	if (rc)
8924 		return (rc);
8925 
8926 	if (vi->flags & VI_INIT_DONE)
8927 		rc = EBUSY; /* cannot be changed once the queues are created */
8928 	else
8929 		vi->qsize_rxq = qsize;
8930 
8931 	end_synchronized_op(sc, LOCK_HELD);
8932 	return (rc);
8933 }
8934 
8935 static int
8936 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
8937 {
8938 	struct vi_info *vi = arg1;
8939 	struct adapter *sc = vi->adapter;
8940 	int qsize, rc;
8941 
8942 	qsize = vi->qsize_txq;
8943 
8944 	rc = sysctl_handle_int(oidp, &qsize, 0, req);
8945 	if (rc != 0 || req->newptr == NULL)
8946 		return (rc);
8947 
8948 	if (qsize < 128 || qsize > 65536)
8949 		return (EINVAL);
8950 
8951 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8952 	    "t4txqs");
8953 	if (rc)
8954 		return (rc);
8955 
8956 	if (vi->flags & VI_INIT_DONE)
8957 		rc = EBUSY; /* cannot be changed once the queues are created */
8958 	else
8959 		vi->qsize_txq = qsize;
8960 
8961 	end_synchronized_op(sc, LOCK_HELD);
8962 	return (rc);
8963 }
8964 
8965 static int
8966 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
8967 {
8968 	struct port_info *pi = arg1;
8969 	struct adapter *sc = pi->adapter;
8970 	struct link_config *lc = &pi->link_cfg;
8971 	int rc;
8972 
8973 	if (req->newptr == NULL) {
8974 		struct sbuf *sb;
8975 		static char *bits = "\20\1RX\2TX\3AUTO";
8976 
8977 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8978 		if (sb == NULL)
8979 			return (ENOMEM);
8980 
8981 		if (lc->link_ok) {
8982 			sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
8983 			    (lc->requested_fc & PAUSE_AUTONEG), bits);
8984 		} else {
8985 			sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
8986 			    PAUSE_RX | PAUSE_AUTONEG), bits);
8987 		}
8988 		rc = sbuf_finish(sb);
8989 		sbuf_delete(sb);
8990 	} else {
8991 		char s[2];
8992 		int n;
8993 
8994 		s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
8995 		    PAUSE_AUTONEG));
8996 		s[1] = 0;
8997 
8998 		rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8999 		if (rc != 0)
9000 			return(rc);
9001 
9002 		if (s[1] != 0)
9003 			return (EINVAL);
9004 		if (s[0] < '0' || s[0] > '9')
9005 			return (EINVAL);	/* not a number */
9006 		n = s[0] - '0';
9007 		if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
9008 			return (EINVAL);	/* some other bit is set too */
9009 
9010 		rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9011 		    "t4PAUSE");
9012 		if (rc)
9013 			return (rc);
9014 		if (hw_all_ok(sc)) {
9015 			PORT_LOCK(pi);
9016 			lc->requested_fc = n;
9017 			fixup_link_config(pi);
9018 			if (pi->up_vis > 0)
9019 				rc = apply_link_config(pi);
9020 			set_current_media(pi);
9021 			PORT_UNLOCK(pi);
9022 		}
9023 		end_synchronized_op(sc, 0);
9024 	}
9025 
9026 	return (rc);
9027 }
9028 
9029 static int
9030 sysctl_link_fec(SYSCTL_HANDLER_ARGS)
9031 {
9032 	struct port_info *pi = arg1;
9033 	struct link_config *lc = &pi->link_cfg;
9034 	int rc;
9035 	struct sbuf *sb;
9036 
9037 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9038 	if (sb == NULL)
9039 		return (ENOMEM);
9040 	if (lc->link_ok)
9041 		sbuf_printf(sb, "%b", lc->fec, t4_fec_bits);
9042 	else
9043 		sbuf_printf(sb, "no link");
9044 	rc = sbuf_finish(sb);
9045 	sbuf_delete(sb);
9046 
9047 	return (rc);
9048 }
9049 
9050 static int
9051 sysctl_requested_fec(SYSCTL_HANDLER_ARGS)
9052 {
9053 	struct port_info *pi = arg1;
9054 	struct adapter *sc = pi->adapter;
9055 	struct link_config *lc = &pi->link_cfg;
9056 	int rc;
9057 	int8_t old = lc->requested_fec;
9058 
9059 	if (req->newptr == NULL) {
9060 		struct sbuf *sb;
9061 
9062 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9063 		if (sb == NULL)
9064 			return (ENOMEM);
9065 
9066 		sbuf_printf(sb, "%b", old, t4_fec_bits);
9067 		rc = sbuf_finish(sb);
9068 		sbuf_delete(sb);
9069 	} else {
9070 		char s[8];
9071 		int n;
9072 
9073 		snprintf(s, sizeof(s), "%d", old == FEC_AUTO ? -1 :
9074 		    old & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
9075 
9076 		rc = sysctl_handle_string(oidp, s, sizeof(s), req);
9077 		if (rc != 0)
9078 			return(rc);
9079 
9080 		n = strtol(&s[0], NULL, 0);
9081 		if (n < 0 || n & FEC_AUTO)
9082 			n = FEC_AUTO;
9083 		else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
9084 			return (EINVAL);/* some other bit is set too */
9085 
9086 		rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9087 		    "t4reqf");
9088 		if (rc)
9089 			return (rc);
9090 		PORT_LOCK(pi);
9091 		if (lc->requested_fec != old) {
9092 			rc = EBUSY;
9093 			goto done;
9094 		}
9095 		if (n == FEC_AUTO)
9096 			lc->requested_fec = FEC_AUTO;
9097 		else if (n == 0 || n == FEC_NONE)
9098 			lc->requested_fec = FEC_NONE;
9099 		else {
9100 			if ((lc->pcaps |
9101 			    V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
9102 			    lc->pcaps) {
9103 				rc = ENOTSUP;
9104 				goto done;
9105 			}
9106 			lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
9107 			    FEC_MODULE);
9108 		}
9109 		if (hw_all_ok(sc)) {
9110 			fixup_link_config(pi);
9111 			if (pi->up_vis > 0) {
9112 				rc = apply_link_config(pi);
9113 				if (rc != 0) {
9114 					lc->requested_fec = old;
9115 					if (rc == FW_EPROTO)
9116 						rc = ENOTSUP;
9117 				}
9118 			}
9119 		}
9120 done:
9121 		PORT_UNLOCK(pi);
9122 		end_synchronized_op(sc, 0);
9123 	}
9124 
9125 	return (rc);
9126 }
9127 
9128 static int
9129 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
9130 {
9131 	struct port_info *pi = arg1;
9132 	struct adapter *sc = pi->adapter;
9133 	struct link_config *lc = &pi->link_cfg;
9134 	int rc;
9135 	int8_t fec;
9136 	struct sbuf *sb;
9137 
9138 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9139 	if (sb == NULL)
9140 		return (ENOMEM);
9141 
9142 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) {
9143 		rc = EBUSY;
9144 		goto done;
9145 	}
9146 	if (!hw_all_ok(sc)) {
9147 		rc = ENXIO;
9148 		goto done;
9149 	}
9150 	PORT_LOCK(pi);
9151 	if (pi->up_vis == 0) {
9152 		/*
9153 		 * If all the interfaces are administratively down the firmware
9154 		 * does not report transceiver changes.  Refresh port info here.
9155 		 * This is the only reason we have a synchronized op in this
9156 		 * function.  Just PORT_LOCK would have been enough otherwise.
9157 		 */
9158 		t4_update_port_info(pi);
9159 	}
9160 
9161 	fec = lc->fec_hint;
9162 	if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
9163 	    !fec_supported(lc->pcaps)) {
9164 		PORT_UNLOCK(pi);
9165 		sbuf_printf(sb, "n/a");
9166 	} else {
9167 		if (fec == 0)
9168 			fec = FEC_NONE;
9169 		PORT_UNLOCK(pi);
9170 		sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, t4_fec_bits);
9171 	}
9172 	rc = sbuf_finish(sb);
9173 done:
9174 	sbuf_delete(sb);
9175 	end_synchronized_op(sc, 0);
9176 
9177 	return (rc);
9178 }
9179 
9180 static int
9181 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
9182 {
9183 	struct port_info *pi = arg1;
9184 	struct adapter *sc = pi->adapter;
9185 	struct link_config *lc = &pi->link_cfg;
9186 	int rc, val;
9187 
9188 	if (lc->pcaps & FW_PORT_CAP32_ANEG)
9189 		val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
9190 	else
9191 		val = -1;
9192 	rc = sysctl_handle_int(oidp, &val, 0, req);
9193 	if (rc != 0 || req->newptr == NULL)
9194 		return (rc);
9195 	if (val == 0)
9196 		val = AUTONEG_DISABLE;
9197 	else if (val == 1)
9198 		val = AUTONEG_ENABLE;
9199 	else
9200 		val = AUTONEG_AUTO;
9201 
9202 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9203 	    "t4aneg");
9204 	if (rc)
9205 		return (rc);
9206 	PORT_LOCK(pi);
9207 	if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
9208 		rc = ENOTSUP;
9209 		goto done;
9210 	}
9211 	lc->requested_aneg = val;
9212 	if (hw_all_ok(sc)) {
9213 		fixup_link_config(pi);
9214 		if (pi->up_vis > 0)
9215 			rc = apply_link_config(pi);
9216 		set_current_media(pi);
9217 	}
9218 done:
9219 	PORT_UNLOCK(pi);
9220 	end_synchronized_op(sc, 0);
9221 	return (rc);
9222 }
9223 
9224 static int
9225 sysctl_force_fec(SYSCTL_HANDLER_ARGS)
9226 {
9227 	struct port_info *pi = arg1;
9228 	struct adapter *sc = pi->adapter;
9229 	struct link_config *lc = &pi->link_cfg;
9230 	int rc, val;
9231 
9232 	val = lc->force_fec;
9233 	MPASS(val >= -1 && val <= 1);
9234 	rc = sysctl_handle_int(oidp, &val, 0, req);
9235 	if (rc != 0 || req->newptr == NULL)
9236 		return (rc);
9237 	if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC))
9238 		return (ENOTSUP);
9239 	if (val < -1 || val > 1)
9240 		return (EINVAL);
9241 
9242 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff");
9243 	if (rc)
9244 		return (rc);
9245 	PORT_LOCK(pi);
9246 	lc->force_fec = val;
9247 	if (hw_all_ok(sc)) {
9248 		fixup_link_config(pi);
9249 		if (pi->up_vis > 0)
9250 			rc = apply_link_config(pi);
9251 	}
9252 	PORT_UNLOCK(pi);
9253 	end_synchronized_op(sc, 0);
9254 	return (rc);
9255 }
9256 
9257 static int
9258 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
9259 {
9260 	struct adapter *sc = arg1;
9261 	int rc, reg = arg2;
9262 	uint64_t val;
9263 
9264 	mtx_lock(&sc->reg_lock);
9265 	if (hw_off_limits(sc))
9266 		rc = ENXIO;
9267 	else {
9268 		rc = 0;
9269 		val = t4_read_reg64(sc, reg);
9270 	}
9271 	mtx_unlock(&sc->reg_lock);
9272 	if (rc == 0)
9273 		rc = sysctl_handle_64(oidp, &val, 0, req);
9274 	return (rc);
9275 }
9276 
9277 static int
9278 sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS)
9279 {
9280 	struct port_info *pi = arg1;
9281 	struct adapter *sc = pi->adapter;
9282 	int rc, i, reg = arg2;
9283 	uint64_t val;
9284 
9285 	mtx_lock(&sc->reg_lock);
9286 	if (hw_off_limits(sc))
9287 		rc = ENXIO;
9288 	else {
9289 		val = 0;
9290 		for (i = 0; i < sc->params.tp.lb_nchan; i++) {
9291 			val += t4_read_reg64(sc,
9292 			    t4_port_reg(sc, pi->tx_chan + i, reg));
9293 		}
9294 		rc = 0;
9295 	}
9296 	mtx_unlock(&sc->reg_lock);
9297 	if (rc == 0)
9298 		rc = sysctl_handle_64(oidp, &val, 0, req);
9299 	return (rc);
9300 }
9301 
9302 static int
9303 sysctl_temperature(SYSCTL_HANDLER_ARGS)
9304 {
9305 	struct adapter *sc = arg1;
9306 	int rc, t;
9307 	uint32_t param, val;
9308 
9309 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
9310 	if (rc)
9311 		return (rc);
9312 	if (!hw_all_ok(sc))
9313 		rc = ENXIO;
9314 	else {
9315 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9316 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9317 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
9318 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9319 	}
9320 	end_synchronized_op(sc, 0);
9321 	if (rc)
9322 		return (rc);
9323 
9324 	/* unknown is returned as 0 but we display -1 in that case */
9325 	t = val == 0 ? -1 : val;
9326 
9327 	rc = sysctl_handle_int(oidp, &t, 0, req);
9328 	return (rc);
9329 }
9330 
9331 static int
9332 sysctl_vdd(SYSCTL_HANDLER_ARGS)
9333 {
9334 	struct adapter *sc = arg1;
9335 	int rc;
9336 	uint32_t param, val;
9337 
9338 	if (sc->params.core_vdd == 0) {
9339 		rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
9340 		    "t4vdd");
9341 		if (rc)
9342 			return (rc);
9343 		if (!hw_all_ok(sc))
9344 			rc = ENXIO;
9345 		else {
9346 			param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9347 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9348 			    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
9349 			rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1,
9350 			    &param, &val);
9351 		}
9352 		end_synchronized_op(sc, 0);
9353 		if (rc)
9354 			return (rc);
9355 		sc->params.core_vdd = val;
9356 	}
9357 
9358 	return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
9359 }
9360 
9361 static int
9362 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
9363 {
9364 	struct adapter *sc = arg1;
9365 	int rc, v;
9366 	uint32_t param, val;
9367 
9368 	v = sc->sensor_resets;
9369 	rc = sysctl_handle_int(oidp, &v, 0, req);
9370 	if (rc != 0 || req->newptr == NULL || v <= 0)
9371 		return (rc);
9372 
9373 	if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
9374 	    chip_id(sc) < CHELSIO_T5)
9375 		return (ENOTSUP);
9376 
9377 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
9378 	if (rc)
9379 		return (rc);
9380 	if (!hw_all_ok(sc))
9381 		rc = ENXIO;
9382 	else {
9383 		param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9384 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9385 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
9386 		val = 1;
9387 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9388 	}
9389 	end_synchronized_op(sc, 0);
9390 	if (rc == 0)
9391 		sc->sensor_resets++;
9392 	return (rc);
9393 }
9394 
9395 static int
9396 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
9397 {
9398 	struct adapter *sc = arg1;
9399 	struct sbuf *sb;
9400 	int rc;
9401 	uint32_t param, val;
9402 	uint8_t coreid = (uint8_t)arg2;
9403 
9404 	KASSERT(coreid < sc->params.ncores,
9405 	    ("%s: bad coreid %u\n", __func__, coreid));
9406 
9407 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
9408 	if (rc)
9409 		return (rc);
9410 	if (!hw_all_ok(sc))
9411 		rc = ENXIO;
9412 	else {
9413 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9414 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD) |
9415 		    V_FW_PARAMS_PARAM_Y(coreid);
9416 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9417 	}
9418 	end_synchronized_op(sc, 0);
9419 	if (rc)
9420 		return (rc);
9421 
9422 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9423 	if (sb == NULL)
9424 		return (ENOMEM);
9425 
9426 	if (val == 0xffffffff) {
9427 		/* Only debug and custom firmwares report load averages. */
9428 		sbuf_printf(sb, "not available");
9429 	} else {
9430 		sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
9431 		    (val >> 16) & 0xff);
9432 	}
9433 	rc = sbuf_finish(sb);
9434 	sbuf_delete(sb);
9435 
9436 	return (rc);
9437 }
9438 
9439 static int
9440 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
9441 {
9442 	struct adapter *sc = arg1;
9443 	struct sbuf *sb;
9444 	int rc, i;
9445 	uint16_t incr[NMTUS][NCCTRL_WIN];
9446 	static const char *dec_fac[] = {
9447 		"0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
9448 		"0.9375"
9449 	};
9450 
9451 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9452 	if (sb == NULL)
9453 		return (ENOMEM);
9454 
9455 	rc = 0;
9456 	mtx_lock(&sc->reg_lock);
9457 	if (hw_off_limits(sc))
9458 		rc = ENXIO;
9459 	else
9460 		t4_read_cong_tbl(sc, incr);
9461 	mtx_unlock(&sc->reg_lock);
9462 	if (rc)
9463 		goto done;
9464 
9465 	for (i = 0; i < NCCTRL_WIN; ++i) {
9466 		sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
9467 		    incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
9468 		    incr[5][i], incr[6][i], incr[7][i]);
9469 		sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
9470 		    incr[8][i], incr[9][i], incr[10][i], incr[11][i],
9471 		    incr[12][i], incr[13][i], incr[14][i], incr[15][i],
9472 		    sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
9473 	}
9474 
9475 	rc = sbuf_finish(sb);
9476 done:
9477 	sbuf_delete(sb);
9478 	return (rc);
9479 }
9480 
9481 static int
9482 sysctl_cim_ibq(SYSCTL_HANDLER_ARGS)
9483 {
9484 	struct adapter *sc = arg1;
9485 	struct sbuf *sb;
9486 	int rc, i, n, qid, coreid;
9487 	uint32_t *buf, *p;
9488 
9489 	qid = arg2 & 0xffff;
9490 	coreid = arg2 >> 16;
9491 
9492 	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_ibq,
9493 	    ("%s: bad ibq qid %d\n", __func__, qid));
9494 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
9495 	    ("%s: bad coreid %d\n", __func__, coreid));
9496 
9497 	n = 4 * CIM_IBQ_SIZE;
9498 	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
9499 	mtx_lock(&sc->reg_lock);
9500 	if (hw_off_limits(sc))
9501 		rc = -ENXIO;
9502 	else
9503 		rc = t4_read_cim_ibq_core(sc, coreid, qid, buf, n);
9504 	mtx_unlock(&sc->reg_lock);
9505 	if (rc < 0) {
9506 		rc = -rc;
9507 		goto done;
9508 	}
9509 	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
9510 
9511 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9512 	if (sb == NULL) {
9513 		rc = ENOMEM;
9514 		goto done;
9515 	}
9516 	for (i = 0, p = buf; i < n; i += 16, p += 4)
9517 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
9518 		    p[2], p[3]);
9519 	rc = sbuf_finish(sb);
9520 	sbuf_delete(sb);
9521 done:
9522 	free(buf, M_CXGBE);
9523 	return (rc);
9524 }
9525 
9526 static int
9527 sysctl_cim_obq(SYSCTL_HANDLER_ARGS)
9528 {
9529 	struct adapter *sc = arg1;
9530 	struct sbuf *sb;
9531 	int rc, i, n, qid, coreid;
9532 	uint32_t *buf, *p;
9533 
9534 	qid = arg2 & 0xffff;
9535 	coreid = arg2 >> 16;
9536 
9537 	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_obq,
9538 	    ("%s: bad obq qid %d\n", __func__, qid));
9539 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
9540 	    ("%s: bad coreid %d\n", __func__, coreid));
9541 
9542 	n = 6 * CIM_OBQ_SIZE * 4;
9543 	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
9544 	mtx_lock(&sc->reg_lock);
9545 	if (hw_off_limits(sc))
9546 		rc = -ENXIO;
9547 	else
9548 		rc = t4_read_cim_obq_core(sc, coreid, qid, buf, n);
9549 	mtx_unlock(&sc->reg_lock);
9550 	if (rc < 0) {
9551 		rc = -rc;
9552 		goto done;
9553 	}
9554 	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
9555 
9556 	rc = sysctl_wire_old_buffer(req, 0);
9557 	if (rc != 0)
9558 		goto done;
9559 
9560 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9561 	if (sb == NULL) {
9562 		rc = ENOMEM;
9563 		goto done;
9564 	}
9565 	for (i = 0, p = buf; i < n; i += 16, p += 4)
9566 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
9567 		    p[2], p[3]);
9568 	rc = sbuf_finish(sb);
9569 	sbuf_delete(sb);
9570 done:
9571 	free(buf, M_CXGBE);
9572 	return (rc);
9573 }
9574 
9575 static void
9576 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9577 {
9578 	uint32_t *p;
9579 
9580 	sbuf_printf(sb, "Status   Data      PC%s",
9581 	    cfg & F_UPDBGLACAPTPCONLY ? "" :
9582 	    "     LS0Stat  LS0Addr             LS0Data");
9583 
9584 	for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
9585 		if (cfg & F_UPDBGLACAPTPCONLY) {
9586 			sbuf_printf(sb, "\n  %02x   %08x %08x", p[5] & 0xff,
9587 			    p[6], p[7]);
9588 			sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x",
9589 			    (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
9590 			    p[4] & 0xff, p[5] >> 8);
9591 			sbuf_printf(sb, "\n  %02x   %x%07x %x%07x",
9592 			    (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9593 			    p[1] & 0xf, p[2] >> 4);
9594 		} else {
9595 			sbuf_printf(sb,
9596 			    "\n  %02x   %x%07x %x%07x %08x %08x "
9597 			    "%08x%08x%08x%08x",
9598 			    (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9599 			    p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
9600 			    p[6], p[7]);
9601 		}
9602 	}
9603 }
9604 
9605 static void
9606 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9607 {
9608 	uint32_t *p;
9609 
9610 	sbuf_printf(sb, "Status   Inst    Data      PC%s",
9611 	    cfg & F_UPDBGLACAPTPCONLY ? "" :
9612 	    "     LS0Stat  LS0Addr  LS0Data  LS1Stat  LS1Addr  LS1Data");
9613 
9614 	for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
9615 		if (cfg & F_UPDBGLACAPTPCONLY) {
9616 			sbuf_printf(sb, "\n  %02x   %08x %08x %08x",
9617 			    p[3] & 0xff, p[2], p[1], p[0]);
9618 			sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x %02x%06x",
9619 			    (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
9620 			    p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
9621 			sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x",
9622 			    (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
9623 			    p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
9624 			    p[6] >> 16);
9625 		} else {
9626 			sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x "
9627 			    "%08x %08x %08x %08x %08x %08x",
9628 			    (p[9] >> 16) & 0xff,
9629 			    p[9] & 0xffff, p[8] >> 16,
9630 			    p[8] & 0xffff, p[7] >> 16,
9631 			    p[7] & 0xffff, p[6] >> 16,
9632 			    p[2], p[1], p[0], p[5], p[4], p[3]);
9633 		}
9634 	}
9635 }
9636 
9637 static int
9638 sbuf_cim_la(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
9639 {
9640 	uint32_t cfg, *buf;
9641 	int rc;
9642 
9643 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
9644 	buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
9645 	    M_ZERO | flags);
9646 	if (buf == NULL)
9647 		return (ENOMEM);
9648 
9649 	mtx_lock(&sc->reg_lock);
9650 	if (hw_off_limits(sc))
9651 		rc = ENXIO;
9652 	else {
9653 		rc = -t4_cim_read_core(sc, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
9654 		    &cfg);
9655 		if (rc == 0)
9656 			rc = -t4_cim_read_la_core(sc, coreid, buf, NULL);
9657 	}
9658 	mtx_unlock(&sc->reg_lock);
9659 	if (rc == 0) {
9660 		if (chip_id(sc) < CHELSIO_T6)
9661 			sbuf_cim_la4(sc, sb, buf, cfg);
9662 		else
9663 			sbuf_cim_la6(sc, sb, buf, cfg);
9664 	}
9665 	free(buf, M_CXGBE);
9666 	return (rc);
9667 }
9668 
9669 static int
9670 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
9671 {
9672 	struct adapter *sc = arg1;
9673 	int coreid = arg2;
9674 	struct sbuf *sb;
9675 	int rc;
9676 
9677 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9678 	if (sb == NULL)
9679 		return (ENOMEM);
9680 
9681 	rc = sbuf_cim_la(sc, coreid, sb, M_WAITOK);
9682 	if (rc == 0)
9683 		rc = sbuf_finish(sb);
9684 	sbuf_delete(sb);
9685 	return (rc);
9686 }
9687 
9688 static void
9689 dump_cim_regs(struct adapter *sc)
9690 {
9691 	log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n",
9692 	    device_get_nameunit(sc->dev),
9693 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9694 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9695 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2),
9696 	    t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN),
9697 	    t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA));
9698 	log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n",
9699 	    device_get_nameunit(sc->dev),
9700 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9701 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9702 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800),
9703 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800),
9704 	    t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN));
9705 }
9706 
9707 static void
9708 dump_cimla(struct adapter *sc)
9709 {
9710 	struct sbuf sb;
9711 	int rc;
9712 
9713 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9714 		log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n",
9715 		    device_get_nameunit(sc->dev));
9716 		return;
9717 	}
9718 	rc = sbuf_cim_la(sc, 0, &sb, M_WAITOK);
9719 	if (rc == 0) {
9720 		rc = sbuf_finish(&sb);
9721 		if (rc == 0) {
9722 			log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n",
9723 			    device_get_nameunit(sc->dev), sbuf_data(&sb));
9724 		}
9725 	}
9726 	sbuf_delete(&sb);
9727 }
9728 
9729 void
9730 t4_os_cim_err(struct adapter *sc)
9731 {
9732 	atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
9733 }
9734 
9735 static int
9736 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
9737 {
9738 	struct adapter *sc = arg1;
9739 	u_int i;
9740 	struct sbuf *sb;
9741 	uint32_t *buf, *p;
9742 	int rc;
9743 
9744 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9745 	if (sb == NULL)
9746 		return (ENOMEM);
9747 
9748 	buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
9749 	    M_ZERO | M_WAITOK);
9750 
9751 	rc = 0;
9752 	mtx_lock(&sc->reg_lock);
9753 	if (hw_off_limits(sc))
9754 		rc = ENXIO;
9755 	else
9756 		t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
9757 	mtx_unlock(&sc->reg_lock);
9758 	if (rc)
9759 		goto done;
9760 
9761 	p = buf;
9762 	for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9763 		sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
9764 		    p[1], p[0]);
9765 	}
9766 
9767 	sbuf_printf(sb, "\n\nCnt ID Tag UE       Data       RDY VLD");
9768 	for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9769 		sbuf_printf(sb, "\n%3u %2u  %x   %u %08x%08x  %u   %u",
9770 		    (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
9771 		    (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
9772 		    (p[1] >> 2) | ((p[2] & 3) << 30),
9773 		    (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
9774 		    p[0] & 1);
9775 	}
9776 	rc = sbuf_finish(sb);
9777 done:
9778 	sbuf_delete(sb);
9779 	free(buf, M_CXGBE);
9780 	return (rc);
9781 }
9782 
9783 static int
9784 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
9785 {
9786 	struct adapter *sc = arg1;
9787 	u_int i;
9788 	struct sbuf *sb;
9789 	uint32_t *buf, *p;
9790 	int rc;
9791 
9792 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9793 	if (sb == NULL)
9794 		return (ENOMEM);
9795 
9796 	buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
9797 	    M_ZERO | M_WAITOK);
9798 
9799 	rc = 0;
9800 	mtx_lock(&sc->reg_lock);
9801 	if (hw_off_limits(sc))
9802 		rc = ENXIO;
9803 	else
9804 		t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
9805 	mtx_unlock(&sc->reg_lock);
9806 	if (rc)
9807 		goto done;
9808 
9809 	p = buf;
9810 	sbuf_printf(sb, "Cntl ID DataBE   Addr                 Data");
9811 	for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9812 		sbuf_printf(sb, "\n %02x  %02x  %04x  %08x %08x%08x%08x%08x",
9813 		    (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
9814 		    p[4], p[3], p[2], p[1], p[0]);
9815 	}
9816 
9817 	sbuf_printf(sb, "\n\nCntl ID               Data");
9818 	for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9819 		sbuf_printf(sb, "\n %02x  %02x %08x%08x%08x%08x",
9820 		    (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
9821 	}
9822 
9823 	rc = sbuf_finish(sb);
9824 done:
9825 	sbuf_delete(sb);
9826 	free(buf, M_CXGBE);
9827 	return (rc);
9828 }
9829 
9830 static int
9831 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
9832 {
9833 	struct adapter *sc = arg1;
9834 	struct sbuf *sb;
9835 	int rc, i;
9836 	uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9837 	uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9838 	uint16_t thres[CIM_NUM_IBQ];
9839 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
9840 	uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
9841 	u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
9842 	static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
9843 		"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",	/* ibq's */
9844 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",	/* obq's */
9845 		"SGE0-RX", "SGE1-RX"	/* additional obq's (T5 onwards) */
9846 	};
9847 
9848 	MPASS(chip_id(sc) < CHELSIO_T7);
9849 
9850 	cim_num_obq = sc->chip_params->cim_num_obq;
9851 	if (is_t4(sc)) {
9852 		ibq_rdaddr = A_UP_IBQ_0_RDADDR;
9853 		obq_rdaddr = A_UP_OBQ_0_REALADDR;
9854 	} else {
9855 		ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
9856 		obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
9857 	}
9858 	nq = CIM_NUM_IBQ + cim_num_obq;
9859 
9860 	mtx_lock(&sc->reg_lock);
9861 	if (hw_off_limits(sc))
9862 		rc = ENXIO;
9863 	else {
9864 		rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
9865 		if (rc == 0) {
9866 			rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq,
9867 			    obq_wr);
9868 			if (rc == 0)
9869 				t4_read_cimq_cfg(sc, base, size, thres);
9870 		}
9871 	}
9872 	mtx_unlock(&sc->reg_lock);
9873 	if (rc)
9874 		return (rc);
9875 
9876 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9877 	if (sb == NULL)
9878 		return (ENOMEM);
9879 
9880 	sbuf_printf(sb,
9881 	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
9882 
9883 	for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
9884 		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
9885 		    qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
9886 		    G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9887 		    G_QUEREMFLITS(p[2]) * 16);
9888 	for ( ; i < nq; i++, p += 4, wr += 2)
9889 		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u", qname[i],
9890 		    base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
9891 		    wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9892 		    G_QUEREMFLITS(p[2]) * 16);
9893 
9894 	rc = sbuf_finish(sb);
9895 	sbuf_delete(sb);
9896 
9897 	return (rc);
9898 }
9899 
9900 static int
9901 sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS)
9902 {
9903 	struct adapter *sc = arg1;
9904 	u_int coreid = arg2;
9905 	struct sbuf *sb;
9906 	int rc, i;
9907 	u_int addr;
9908 	uint16_t base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
9909 	uint16_t size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
9910 	uint16_t thres[CIM_NUM_IBQ_T7];
9911 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T7], *wr = obq_wr;
9912 	uint32_t stat[4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7)], *p = stat;
9913 	static const char * const qname_ibq_t7[] = {
9914 		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "SGE1", "NC-SI",
9915 		"RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5", "IPC6", "IPC7",
9916 	};
9917 	static const char * const qname_obq_t7[] = {
9918 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", "SGE0-RX",
9919 		"RSVD", "RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5",
9920 		"IPC6", "IPC7"
9921 	};
9922 	static const char * const qname_ibq_sec_t7[] = {
9923 		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "RSVD", "RSVD",
9924 		"RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",	"RSVD", "RSVD",
9925 	};
9926 	static const char * const qname_obq_sec_t7[] = {
9927 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "RSVD", "SGE0-RX",
9928 		"RSVD", "RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",
9929 		"RSVD", "RSVD",
9930 	};
9931 
9932 	MPASS(chip_id(sc) >= CHELSIO_T7);
9933 
9934 	mtx_lock(&sc->reg_lock);
9935 	if (hw_off_limits(sc))
9936 		rc = ENXIO;
9937 	else {
9938 		rc = -t4_cim_read_core(sc, 1, coreid,
9939 		    A_T7_UP_IBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_IBQ_T7, stat);
9940 		if (rc != 0)
9941 			goto unlock;
9942 
9943 		rc = -t4_cim_read_core(sc, 1, coreid,
9944 		    A_T7_UP_OBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_OBQ_T7,
9945 		    &stat[4 * CIM_NUM_IBQ_T7]);
9946 		if (rc != 0)
9947 			goto unlock;
9948 
9949 		addr = A_T7_UP_OBQ_0_SHADOW_REALADDR;
9950 		for (i = 0; i < CIM_NUM_OBQ_T7 * 2; i++, addr += 8) {
9951 			rc = -t4_cim_read_core(sc, 1, coreid, addr, 1,
9952 			    &obq_wr[i]);
9953 			if (rc != 0)
9954 				goto unlock;
9955 		}
9956 		t4_read_cimq_cfg_core(sc, coreid, base, size, thres);
9957 	}
9958 unlock:
9959 	mtx_unlock(&sc->reg_lock);
9960 	if (rc)
9961 		return (rc);
9962 
9963 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9964 	if (sb == NULL)
9965 		return (ENOMEM);
9966 
9967 	sbuf_printf(sb,
9968 	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
9969 
9970 	for (i = 0; i < CIM_NUM_IBQ_T7; i++, p += 4) {
9971 		if (!size[i])
9972 			continue;
9973 
9974 		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
9975 		    coreid == 0 ? qname_ibq_t7[i] : qname_ibq_sec_t7[i],
9976 		    base[i], size[i], thres[i], G_IBQRDADDR(p[0]) & 0xfff,
9977 		    G_IBQWRADDR(p[1]) & 0xfff, G_QUESOPCNT(p[3]),
9978 		    G_QUEEOPCNT(p[3]), G_T7_QUEREMFLITS(p[2]) * 16);
9979 	}
9980 
9981 	for ( ; i < CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7; i++, p += 4, wr += 2) {
9982 		if (!size[i])
9983 			continue;
9984 
9985 		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u",
9986 		    coreid == 0 ? qname_obq_t7[i - CIM_NUM_IBQ_T7] :
9987 		    qname_obq_sec_t7[i - CIM_NUM_IBQ_T7],
9988 		    base[i], size[i], G_QUERDADDR(p[0]) & 0xfff,
9989 		    wr[0] << 1, G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9990 		    G_T7_QUEREMFLITS(p[2]) * 16);
9991 	}
9992 
9993 	rc = sbuf_finish(sb);
9994 	sbuf_delete(sb);
9995 	return (rc);
9996 }
9997 
9998 static int
9999 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
10000 {
10001 	struct adapter *sc = arg1;
10002 	struct sbuf *sb;
10003 	int rc;
10004 	struct tp_cpl_stats stats;
10005 
10006 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10007 	if (sb == NULL)
10008 		return (ENOMEM);
10009 
10010 	rc = 0;
10011 	mtx_lock(&sc->reg_lock);
10012 	if (hw_off_limits(sc))
10013 		rc = ENXIO;
10014 	else
10015 		t4_tp_get_cpl_stats(sc, &stats, 0);
10016 	mtx_unlock(&sc->reg_lock);
10017 	if (rc)
10018 		goto done;
10019 
10020 	if (sc->chip_params->nchan > 2) {
10021 		sbuf_printf(sb, "                 channel 0  channel 1"
10022 		    "  channel 2  channel 3");
10023 		sbuf_printf(sb, "\nCPL requests:   %10u %10u %10u %10u",
10024 		    stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
10025 		sbuf_printf(sb, "\nCPL responses:  %10u %10u %10u %10u",
10026 		    stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
10027 	} else {
10028 		sbuf_printf(sb, "                 channel 0  channel 1");
10029 		sbuf_printf(sb, "\nCPL requests:   %10u %10u",
10030 		    stats.req[0], stats.req[1]);
10031 		sbuf_printf(sb, "\nCPL responses:  %10u %10u",
10032 		    stats.rsp[0], stats.rsp[1]);
10033 	}
10034 
10035 	rc = sbuf_finish(sb);
10036 done:
10037 	sbuf_delete(sb);
10038 	return (rc);
10039 }
10040 
10041 static int
10042 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
10043 {
10044 	struct adapter *sc = arg1;
10045 	struct sbuf *sb;
10046 	int rc;
10047 	struct tp_usm_stats stats;
10048 
10049 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10050 	if (sb == NULL)
10051 		return (ENOMEM);
10052 
10053 	rc = 0;
10054 	mtx_lock(&sc->reg_lock);
10055 	if (hw_off_limits(sc))
10056 		rc = ENXIO;
10057 	else
10058 		t4_get_usm_stats(sc, &stats, 1);
10059 	mtx_unlock(&sc->reg_lock);
10060 	if (rc == 0) {
10061 		sbuf_printf(sb, "Frames: %u\n", stats.frames);
10062 		sbuf_printf(sb, "Octets: %ju\n", stats.octets);
10063 		sbuf_printf(sb, "Drops:  %u", stats.drops);
10064 		rc = sbuf_finish(sb);
10065 	}
10066 	sbuf_delete(sb);
10067 
10068 	return (rc);
10069 }
10070 
10071 static int
10072 sysctl_tid_stats(SYSCTL_HANDLER_ARGS)
10073 {
10074 	struct adapter *sc = arg1;
10075 	struct sbuf *sb;
10076 	int rc;
10077 	struct tp_tid_stats stats;
10078 
10079 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10080 	if (sb == NULL)
10081 		return (ENOMEM);
10082 
10083 	rc = 0;
10084 	mtx_lock(&sc->reg_lock);
10085 	if (hw_off_limits(sc))
10086 		rc = ENXIO;
10087 	else
10088 		t4_tp_get_tid_stats(sc, &stats, 1);
10089 	mtx_unlock(&sc->reg_lock);
10090 	if (rc == 0) {
10091 		sbuf_printf(sb, "Delete:     %u\n", stats.del);
10092 		sbuf_printf(sb, "Invalidate: %u\n", stats.inv);
10093 		sbuf_printf(sb, "Active:     %u\n", stats.act);
10094 		sbuf_printf(sb, "Passive:    %u", stats.pas);
10095 		rc = sbuf_finish(sb);
10096 	}
10097 	sbuf_delete(sb);
10098 
10099 	return (rc);
10100 }
10101 
10102 static const char * const devlog_level_strings[] = {
10103 	[FW_DEVLOG_LEVEL_EMERG]		= "EMERG",
10104 	[FW_DEVLOG_LEVEL_CRIT]		= "CRIT",
10105 	[FW_DEVLOG_LEVEL_ERR]		= "ERR",
10106 	[FW_DEVLOG_LEVEL_NOTICE]	= "NOTICE",
10107 	[FW_DEVLOG_LEVEL_INFO]		= "INFO",
10108 	[FW_DEVLOG_LEVEL_DEBUG]		= "DEBUG"
10109 };
10110 
10111 static const char * const devlog_facility_strings[] = {
10112 	[FW_DEVLOG_FACILITY_CORE]	= "CORE",
10113 	[FW_DEVLOG_FACILITY_CF]		= "CF",
10114 	[FW_DEVLOG_FACILITY_SCHED]	= "SCHED",
10115 	[FW_DEVLOG_FACILITY_TIMER]	= "TIMER",
10116 	[FW_DEVLOG_FACILITY_RES]	= "RES",
10117 	[FW_DEVLOG_FACILITY_HW]		= "HW",
10118 	[FW_DEVLOG_FACILITY_FLR]	= "FLR",
10119 	[FW_DEVLOG_FACILITY_DMAQ]	= "DMAQ",
10120 	[FW_DEVLOG_FACILITY_PHY]	= "PHY",
10121 	[FW_DEVLOG_FACILITY_MAC]	= "MAC",
10122 	[FW_DEVLOG_FACILITY_PORT]	= "PORT",
10123 	[FW_DEVLOG_FACILITY_VI]		= "VI",
10124 	[FW_DEVLOG_FACILITY_FILTER]	= "FILTER",
10125 	[FW_DEVLOG_FACILITY_ACL]	= "ACL",
10126 	[FW_DEVLOG_FACILITY_TM]		= "TM",
10127 	[FW_DEVLOG_FACILITY_QFC]	= "QFC",
10128 	[FW_DEVLOG_FACILITY_DCB]	= "DCB",
10129 	[FW_DEVLOG_FACILITY_ETH]	= "ETH",
10130 	[FW_DEVLOG_FACILITY_OFLD]	= "OFLD",
10131 	[FW_DEVLOG_FACILITY_RI]		= "RI",
10132 	[FW_DEVLOG_FACILITY_ISCSI]	= "ISCSI",
10133 	[FW_DEVLOG_FACILITY_FCOE]	= "FCOE",
10134 	[FW_DEVLOG_FACILITY_FOISCSI]	= "FOISCSI",
10135 	[FW_DEVLOG_FACILITY_FOFCOE]	= "FOFCOE",
10136 	[FW_DEVLOG_FACILITY_CHNET]	= "CHNET",
10137 };
10138 
10139 static int
10140 sbuf_devlog(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
10141 {
10142 	int i, j, rc, nentries, first = 0;
10143 	struct devlog_params *dparams = &sc->params.devlog;
10144 	struct fw_devlog_e *buf, *e;
10145 	uint32_t addr, size;
10146 	uint64_t ftstamp = UINT64_MAX;
10147 
10148 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
10149 	    ("%s: bad coreid %d\n", __func__, coreid));
10150 
10151 	if (dparams->addr == 0)
10152 		return (ENXIO);
10153 
10154 	size = dparams->size / sc->params.ncores;
10155 	addr = dparams->addr + coreid * size;
10156 
10157 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
10158 	buf = malloc(size, M_CXGBE, M_ZERO | flags);
10159 	if (buf == NULL)
10160 		return (ENOMEM);
10161 
10162 	mtx_lock(&sc->reg_lock);
10163 	if (hw_off_limits(sc))
10164 		rc = ENXIO;
10165 	else
10166 		rc = read_via_memwin(sc, 1, addr, (void *)buf, size);
10167 	mtx_unlock(&sc->reg_lock);
10168 	if (rc != 0)
10169 		goto done;
10170 
10171 	nentries = size / sizeof(struct fw_devlog_e);
10172 	for (i = 0; i < nentries; i++) {
10173 		e = &buf[i];
10174 
10175 		if (e->timestamp == 0)
10176 			break;	/* end */
10177 
10178 		e->timestamp = be64toh(e->timestamp);
10179 		e->seqno = be32toh(e->seqno);
10180 		for (j = 0; j < 8; j++)
10181 			e->params[j] = be32toh(e->params[j]);
10182 
10183 		if (e->timestamp < ftstamp) {
10184 			ftstamp = e->timestamp;
10185 			first = i;
10186 		}
10187 	}
10188 
10189 	if (buf[first].timestamp == 0)
10190 		goto done;	/* nothing in the log */
10191 
10192 	sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
10193 	    "Seq#", "Tstamp", "Level", "Facility", "Message");
10194 
10195 	i = first;
10196 	do {
10197 		e = &buf[i];
10198 		if (e->timestamp == 0)
10199 			break;	/* end */
10200 
10201 		sbuf_printf(sb, "%10d  %15ju  %8s  %8s  ",
10202 		    e->seqno, e->timestamp,
10203 		    (e->level < nitems(devlog_level_strings) ?
10204 			devlog_level_strings[e->level] : "UNKNOWN"),
10205 		    (e->facility < nitems(devlog_facility_strings) ?
10206 			devlog_facility_strings[e->facility] : "UNKNOWN"));
10207 		sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
10208 		    e->params[2], e->params[3], e->params[4],
10209 		    e->params[5], e->params[6], e->params[7]);
10210 
10211 		if (++i == nentries)
10212 			i = 0;
10213 	} while (i != first);
10214 done:
10215 	free(buf, M_CXGBE);
10216 	return (rc);
10217 }
10218 
10219 static int
10220 sysctl_devlog(SYSCTL_HANDLER_ARGS)
10221 {
10222 	struct adapter *sc = arg1;
10223 	int rc, i, coreid = arg2;
10224 	struct sbuf *sb;
10225 
10226 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10227 	if (sb == NULL)
10228 		return (ENOMEM);
10229 	if (coreid == -1) {
10230 		/* -1 means all cores */
10231 		for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
10232 			if (sc->params.ncores > 0)
10233 				sbuf_printf(sb, "=== CIM core %u ===\n", i);
10234 			rc = sbuf_devlog(sc, i, sb, M_WAITOK);
10235 		}
10236 	} else {
10237 		KASSERT(coreid >= 0 && coreid < sc->params.ncores,
10238 		    ("%s: bad coreid %d\n", __func__, coreid));
10239 		rc = sbuf_devlog(sc, coreid, sb, M_WAITOK);
10240 	}
10241 	if (rc == 0)
10242 		rc = sbuf_finish(sb);
10243 	sbuf_delete(sb);
10244 	return (rc);
10245 }
10246 
10247 static void
10248 dump_devlog(struct adapter *sc)
10249 {
10250 	int rc, i;
10251 	struct sbuf sb;
10252 
10253 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
10254 		log(LOG_DEBUG, "%s: failed to generate devlog dump.\n",
10255 		    device_get_nameunit(sc->dev));
10256 		return;
10257 	}
10258 	for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
10259 		if (sc->params.ncores > 0)
10260 			sbuf_printf(&sb, "=== CIM core %u ===\n", i);
10261 		rc = sbuf_devlog(sc, i, &sb, M_WAITOK);
10262 	}
10263 	if (rc == 0) {
10264 		sbuf_finish(&sb);
10265 		log(LOG_DEBUG, "%s: device log follows.\n%s",
10266 		    device_get_nameunit(sc->dev), sbuf_data(&sb));
10267 	}
10268 	sbuf_delete(&sb);
10269 }
10270 
10271 static int
10272 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
10273 {
10274 	struct adapter *sc = arg1;
10275 	struct sbuf *sb;
10276 	int rc;
10277 	struct tp_fcoe_stats stats[MAX_NCHAN];
10278 	int i, nchan = sc->chip_params->nchan;
10279 
10280 	rc = 0;
10281 	mtx_lock(&sc->reg_lock);
10282 	if (hw_off_limits(sc))
10283 		rc = ENXIO;
10284 	else {
10285 		for (i = 0; i < nchan; i++)
10286 			t4_get_fcoe_stats(sc, i, &stats[i], 1);
10287 	}
10288 	mtx_unlock(&sc->reg_lock);
10289 	if (rc != 0)
10290 		return (rc);
10291 
10292 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10293 	if (sb == NULL)
10294 		return (ENOMEM);
10295 
10296 	if (nchan > 2) {
10297 		sbuf_printf(sb, "                   channel 0        channel 1"
10298 		    "        channel 2        channel 3");
10299 		sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju %16ju %16ju",
10300 		    stats[0].octets_ddp, stats[1].octets_ddp,
10301 		    stats[2].octets_ddp, stats[3].octets_ddp);
10302 		sbuf_printf(sb, "\nframesDDP:  %16u %16u %16u %16u",
10303 		    stats[0].frames_ddp, stats[1].frames_ddp,
10304 		    stats[2].frames_ddp, stats[3].frames_ddp);
10305 		sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
10306 		    stats[0].frames_drop, stats[1].frames_drop,
10307 		    stats[2].frames_drop, stats[3].frames_drop);
10308 	} else {
10309 		sbuf_printf(sb, "                   channel 0        channel 1");
10310 		sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju",
10311 		    stats[0].octets_ddp, stats[1].octets_ddp);
10312 		sbuf_printf(sb, "\nframesDDP:  %16u %16u",
10313 		    stats[0].frames_ddp, stats[1].frames_ddp);
10314 		sbuf_printf(sb, "\nframesDrop: %16u %16u",
10315 		    stats[0].frames_drop, stats[1].frames_drop);
10316 	}
10317 
10318 	rc = sbuf_finish(sb);
10319 	sbuf_delete(sb);
10320 
10321 	return (rc);
10322 }
10323 
10324 static int
10325 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
10326 {
10327 	struct adapter *sc = arg1;
10328 	struct sbuf *sb;
10329 	int rc, i;
10330 	unsigned int map, kbps, ipg, mode;
10331 	unsigned int pace_tab[NTX_SCHED];
10332 
10333 	sb = sbuf_new_for_sysctl(NULL, NULL, 512, req);
10334 	if (sb == NULL)
10335 		return (ENOMEM);
10336 
10337 	mtx_lock(&sc->reg_lock);
10338 	if (hw_off_limits(sc)) {
10339 		mtx_unlock(&sc->reg_lock);
10340 		rc = ENXIO;
10341 		goto done;
10342 	}
10343 
10344 	map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
10345 	mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
10346 	t4_read_pace_tbl(sc, pace_tab);
10347 	mtx_unlock(&sc->reg_lock);
10348 
10349 	sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
10350 	    "Class IPG (0.1 ns)   Flow IPG (us)");
10351 
10352 	for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
10353 		t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
10354 		sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
10355 		    (mode & (1 << i)) ? "flow" : "class", map & 3);
10356 		if (kbps)
10357 			sbuf_printf(sb, "%9u     ", kbps);
10358 		else
10359 			sbuf_printf(sb, " disabled     ");
10360 
10361 		if (ipg)
10362 			sbuf_printf(sb, "%13u        ", ipg);
10363 		else
10364 			sbuf_printf(sb, "     disabled        ");
10365 
10366 		if (pace_tab[i])
10367 			sbuf_printf(sb, "%10u", pace_tab[i]);
10368 		else
10369 			sbuf_printf(sb, "  disabled");
10370 	}
10371 	rc = sbuf_finish(sb);
10372 done:
10373 	sbuf_delete(sb);
10374 	return (rc);
10375 }
10376 
10377 static int
10378 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
10379 {
10380 	struct adapter *sc = arg1;
10381 	struct sbuf *sb;
10382 	int rc, i, j;
10383 	uint64_t *p0, *p1;
10384 	struct lb_port_stats s[2];
10385 	static const char *stat_name[] = {
10386 		"OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
10387 		"UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
10388 		"Frames128To255:", "Frames256To511:", "Frames512To1023:",
10389 		"Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
10390 		"BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
10391 		"BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
10392 		"BG2FramesTrunc:", "BG3FramesTrunc:"
10393 	};
10394 
10395 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10396 	if (sb == NULL)
10397 		return (ENOMEM);
10398 
10399 	memset(s, 0, sizeof(s));
10400 
10401 	rc = 0;
10402 	for (i = 0; i < sc->chip_params->nchan; i += 2) {
10403 		mtx_lock(&sc->reg_lock);
10404 		if (hw_off_limits(sc))
10405 			rc = ENXIO;
10406 		else {
10407 			t4_get_lb_stats(sc, i, &s[0]);
10408 			t4_get_lb_stats(sc, i + 1, &s[1]);
10409 		}
10410 		mtx_unlock(&sc->reg_lock);
10411 		if (rc != 0)
10412 			break;
10413 
10414 		p0 = &s[0].octets;
10415 		p1 = &s[1].octets;
10416 		sbuf_printf(sb, "%s                       Loopback %u"
10417 		    "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
10418 
10419 		for (j = 0; j < nitems(stat_name); j++)
10420 			sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
10421 				   *p0++, *p1++);
10422 	}
10423 
10424 	if (rc == 0)
10425 		rc = sbuf_finish(sb);
10426 	sbuf_delete(sb);
10427 
10428 	return (rc);
10429 }
10430 
10431 static int
10432 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
10433 {
10434 	int rc = 0;
10435 	struct port_info *pi = arg1;
10436 	struct link_config *lc = &pi->link_cfg;
10437 	struct sbuf *sb;
10438 
10439 	sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
10440 	if (sb == NULL)
10441 		return (ENOMEM);
10442 
10443 	if (lc->link_ok || lc->link_down_rc == 255)
10444 		sbuf_printf(sb, "n/a");
10445 	else
10446 		sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
10447 
10448 	rc = sbuf_finish(sb);
10449 	sbuf_delete(sb);
10450 
10451 	return (rc);
10452 }
10453 
10454 struct mem_desc {
10455 	uint64_t base;
10456 	uint64_t limit;
10457 	u_int idx;
10458 };
10459 
10460 static int
10461 mem_desc_cmp(const void *a, const void *b)
10462 {
10463 	const uint64_t v1 = ((const struct mem_desc *)a)->base;
10464 	const uint64_t v2 = ((const struct mem_desc *)b)->base;
10465 
10466 	if (v1 < v2)
10467 		return (-1);
10468 	else if (v1 > v2)
10469 		return (1);
10470 
10471 	return (0);
10472 }
10473 
10474 static void
10475 mem_region_show(struct sbuf *sb, const char *name, uint64_t from, uint64_t to)
10476 {
10477 	uintmax_t size;
10478 
10479 	if (from == to)
10480 		return;
10481 
10482 	size = to - from + 1;
10483 	if (size == 0)
10484 		return;
10485 
10486 	if (from > UINT32_MAX || to > UINT32_MAX)
10487 		sbuf_printf(sb, "%-18s 0x%012jx-0x%012jx [%ju]\n", name,
10488 		    (uintmax_t)from, (uintmax_t)to, size);
10489 	else
10490 		sbuf_printf(sb, "%-18s 0x%08jx-0x%08jx [%ju]\n", name,
10491 		    (uintmax_t)from, (uintmax_t)to, size);
10492 }
10493 
10494 static int
10495 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
10496 {
10497 	struct adapter *sc = arg1;
10498 	struct sbuf *sb;
10499 	int rc, i, n, nchan;
10500 	uint32_t lo, hi, used, free, alloc;
10501 	static const char *memory[] = {
10502 		"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:"
10503 	};
10504 	static const char *region[] = {
10505 		"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
10506 		"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
10507 		"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
10508 		"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
10509 		"RQUDP region:", "PBL region:", "TXPBL region:",
10510 		"TLSKey region:", "RRQ region:", "NVMe STAG region:",
10511 		"NVMe RQ region:", "NVMe RXPBL region:", "NVMe TPT region:",
10512 		"NVMe TXPBL region:", "DBVFIFO region:", "ULPRX state:",
10513 		"ULPTX state:", "RoCE RRQ region:", "On-chip queues:",
10514 	};
10515 	struct mem_desc avail[4];
10516 	struct mem_desc mem[nitems(region) + 3];	/* up to 3 holes */
10517 	struct mem_desc *md;
10518 
10519 	rc = sysctl_wire_old_buffer(req, 0);
10520 	if (rc != 0)
10521 		return (rc);
10522 
10523 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10524 	if (sb == NULL)
10525 		return (ENOMEM);
10526 
10527 	for (i = 0; i < nitems(mem); i++) {
10528 		mem[i].limit = 0;
10529 		mem[i].idx = i;
10530 	}
10531 
10532 	mtx_lock(&sc->reg_lock);
10533 	if (hw_off_limits(sc)) {
10534 		rc = ENXIO;
10535 		goto done;
10536 	}
10537 
10538 	/* Find and sort the populated memory ranges */
10539 	i = 0;
10540 	lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
10541 	if (lo & F_EDRAM0_ENABLE) {
10542 		hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
10543 		if (chip_id(sc) >= CHELSIO_T7) {
10544 			avail[i].base = (uint64_t)G_T7_EDRAM0_BASE(hi) << 20;
10545 			avail[i].limit = avail[i].base +
10546 			    (G_T7_EDRAM0_SIZE(hi) << 20);
10547 		} else {
10548 			avail[i].base = (uint64_t)G_EDRAM0_BASE(hi) << 20;
10549 			avail[i].limit = avail[i].base +
10550 			    (G_EDRAM0_SIZE(hi) << 20);
10551 		}
10552 		avail[i].idx = 0;
10553 		i++;
10554 	}
10555 	if (lo & F_EDRAM1_ENABLE) {
10556 		hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
10557 		if (chip_id(sc) >= CHELSIO_T7) {
10558 			avail[i].base = (uint64_t)G_T7_EDRAM1_BASE(hi) << 20;
10559 			avail[i].limit = avail[i].base +
10560 			    (G_T7_EDRAM1_SIZE(hi) << 20);
10561 		} else {
10562 			avail[i].base = (uint64_t)G_EDRAM1_BASE(hi) << 20;
10563 			avail[i].limit = avail[i].base +
10564 			    (G_EDRAM1_SIZE(hi) << 20);
10565 		}
10566 		avail[i].idx = 1;
10567 		i++;
10568 	}
10569 	if (lo & F_EXT_MEM_ENABLE) {
10570 		switch (chip_id(sc)) {
10571 		case CHELSIO_T4:
10572 		case CHELSIO_T6:
10573 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
10574 			avail[i].base = (uint64_t)G_EXT_MEM_BASE(hi) << 20;
10575 			avail[i].limit = avail[i].base +
10576 			    (G_EXT_MEM_SIZE(hi) << 20);
10577 			avail[i].idx = 2;
10578 			break;
10579 		case CHELSIO_T5:
10580 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
10581 			avail[i].base = (uint64_t)G_EXT_MEM0_BASE(hi) << 20;
10582 			avail[i].limit = avail[i].base +
10583 			    (G_EXT_MEM0_SIZE(hi) << 20);
10584 			avail[i].idx = 3;	/* Call it MC0 for T5 */
10585 			break;
10586 		default:
10587 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
10588 			avail[i].base = (uint64_t)G_T7_EXT_MEM0_BASE(hi) << 20;
10589 			avail[i].limit = avail[i].base +
10590 			    (G_T7_EXT_MEM0_SIZE(hi) << 20);
10591 			avail[i].idx = 3;	/* Call it MC0 for T7+ */
10592 			break;
10593 		}
10594 		i++;
10595 	}
10596 	if (lo & F_EXT_MEM1_ENABLE && !(lo & F_MC_SPLIT)) {
10597 		/* Only T5 and T7+ have 2 MCs. */
10598 		MPASS(is_t5(sc) || chip_id(sc) >= CHELSIO_T7);
10599 
10600 		hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
10601 		if (chip_id(sc) >= CHELSIO_T7) {
10602 			avail[i].base = (uint64_t)G_T7_EXT_MEM1_BASE(hi) << 20;
10603 			avail[i].limit = avail[i].base +
10604 			    (G_T7_EXT_MEM1_SIZE(hi) << 20);
10605 		} else {
10606 			avail[i].base = (uint64_t)G_EXT_MEM1_BASE(hi) << 20;
10607 			avail[i].limit = avail[i].base +
10608 			    (G_EXT_MEM1_SIZE(hi) << 20);
10609 		}
10610 		avail[i].idx = 4;
10611 		i++;
10612 	}
10613 	if (lo & F_HMA_MUX) {
10614 		/* Only T6+ have HMA. */
10615 		MPASS(chip_id(sc) >= CHELSIO_T6);
10616 
10617 		if (chip_id(sc) >= CHELSIO_T7) {
10618 			hi = t4_read_reg(sc, A_MA_HOST_MEMORY_BAR);
10619 			avail[i].base = (uint64_t)G_HMATARGETBASE(hi) << 20;
10620 			avail[i].limit = avail[i].base +
10621 			    (G_T7_HMA_SIZE(hi) << 20);
10622 		} else {
10623 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
10624 			avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
10625 			avail[i].limit = avail[i].base +
10626 			    (G_EXT_MEM1_SIZE(hi) << 20);
10627 		}
10628 		avail[i].idx = 5;
10629 		i++;
10630 	}
10631 	MPASS(i <= nitems(avail));
10632 	if (!i)                                    /* no memory available */
10633 		goto done;
10634 	qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
10635 
10636 	md = &mem[0];
10637 	(md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
10638 	(md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
10639 	(md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
10640 	(md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10641 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
10642 	(md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
10643 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
10644 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
10645 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
10646 
10647 	/* the next few have explicit upper bounds */
10648 	md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
10649 	md->limit = md->base - 1 +
10650 		    t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
10651 		    G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
10652 	md++;
10653 
10654 	md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
10655 	md->limit = md->base - 1 +
10656 		    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
10657 		    G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
10658 	md++;
10659 
10660 	if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
10661 		if (chip_id(sc) <= CHELSIO_T5)
10662 			md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
10663 		else
10664 			md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
10665 		md->limit = 0;
10666 	} else {
10667 		md->base = 0;
10668 		md->idx = nitems(region);  /* hide it */
10669 	}
10670 	md++;
10671 
10672 #define ulp_region(reg) do {\
10673 		const u_int shift = chip_id(sc) >= CHELSIO_T7 ? 4 : 0; \
10674 		md->base = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT) << shift; \
10675 		md->limit = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) << shift; \
10676 		md->limit += (1 << shift) - 1; \
10677 		md++; \
10678 	} while (0)
10679 
10680 #define	hide_ulp_region() do { \
10681 		md->base = 0; \
10682 		md->idx = nitems(region); \
10683 		md++; \
10684 	} while (0)
10685 
10686 	ulp_region(RX_ISCSI);
10687 	ulp_region(RX_TDDP);
10688 	ulp_region(TX_TPT);
10689 	ulp_region(RX_STAG);
10690 	ulp_region(RX_RQ);
10691 	if (chip_id(sc) < CHELSIO_T7)
10692 		ulp_region(RX_RQUDP);
10693 	else
10694 		hide_ulp_region();
10695 	ulp_region(RX_PBL);
10696 	ulp_region(TX_PBL);
10697 	if (chip_id(sc) >= CHELSIO_T6)
10698 		ulp_region(RX_TLS_KEY);
10699 	else
10700 		hide_ulp_region();
10701 	if (chip_id(sc) >= CHELSIO_T7) {
10702 		ulp_region(RX_RRQ);
10703 		ulp_region(RX_NVME_TCP_STAG);
10704 		ulp_region(RX_NVME_TCP_RQ);
10705 		ulp_region(RX_NVME_TCP_PBL);
10706 		ulp_region(TX_NVME_TCP_TPT);
10707 		ulp_region(TX_NVME_TCP_PBL);
10708 	} else {
10709 		hide_ulp_region();
10710 		hide_ulp_region();
10711 		hide_ulp_region();
10712 		hide_ulp_region();
10713 		hide_ulp_region();
10714 		hide_ulp_region();
10715 	}
10716 #undef ulp_region
10717 #undef hide_ulp_region
10718 
10719 	md->base = 0;
10720 	if (is_t4(sc))
10721 		md->idx = nitems(region);
10722 	else {
10723 		uint32_t size = 0;
10724 		uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
10725 		uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
10726 
10727 		if (is_t5(sc)) {
10728 			if (sge_ctrl & F_VFIFO_ENABLE)
10729 				size = fifo_size << 2;
10730 		} else
10731 			size = G_T6_DBVFIFO_SIZE(fifo_size) << 6;
10732 
10733 		if (size) {
10734 			md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR);
10735 			md->limit = md->base + size - 1;
10736 		} else
10737 			md->idx = nitems(region);
10738 	}
10739 	md++;
10740 
10741 	md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
10742 	md->limit = 0;
10743 	md++;
10744 	md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
10745 	md->limit = 0;
10746 	md++;
10747 
10748 	if (chip_id(sc) >= CHELSIO_T7) {
10749 		t4_tp_pio_read(sc, &lo, 1, A_TP_ROCE_RRQ_BASE, false);
10750 		md->base = lo;
10751 	} else {
10752 		md->base = 0;
10753 		md->idx = nitems(region);
10754 	}
10755 	md++;
10756 
10757 	md->base = sc->vres.ocq.start;
10758 	if (sc->vres.ocq.size)
10759 		md->limit = md->base + sc->vres.ocq.size - 1;
10760 	else
10761 		md->idx = nitems(region);  /* hide it */
10762 	md++;
10763 
10764 	/* add any address-space holes, there can be up to 3 */
10765 	for (n = 0; n < i - 1; n++)
10766 		if (avail[n].limit < avail[n + 1].base)
10767 			(md++)->base = avail[n].limit;
10768 	if (avail[n].limit)
10769 		(md++)->base = avail[n].limit;
10770 
10771 	n = md - mem;
10772 	MPASS(n <= nitems(mem));
10773 	qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
10774 
10775 	for (lo = 0; lo < i; lo++)
10776 		mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
10777 				avail[lo].limit - 1);
10778 
10779 	sbuf_printf(sb, "\n");
10780 	for (i = 0; i < n; i++) {
10781 		if (mem[i].idx >= nitems(region))
10782 			continue;                        /* skip holes */
10783 		if (!mem[i].limit)
10784 			mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
10785 		mem_region_show(sb, region[mem[i].idx], mem[i].base,
10786 				mem[i].limit);
10787 	}
10788 
10789 	lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
10790 	hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
10791 	if (hi != lo  - 1) {
10792 		sbuf_printf(sb, "\n");
10793 		mem_region_show(sb, "uP RAM:", lo, hi);
10794 	}
10795 
10796 	lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
10797 	hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
10798 	if (hi != lo  - 1)
10799 		mem_region_show(sb, "uP Extmem2:", lo, hi);
10800 
10801 	lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
10802 	if (chip_id(sc) >= CHELSIO_T7)
10803 		nchan = 1 << G_T7_PMRXNUMCHN(lo);
10804 	else
10805 		nchan = lo & F_PMRXNUMCHN ? 2 : 1;
10806 	for (i = 0, free = 0; i < nchan; i++)
10807 		free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT));
10808 	sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
10809 		   G_PMRXMAXPAGE(lo), free,
10810 		   t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, nchan);
10811 
10812 	lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
10813 	hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
10814 	if (chip_id(sc) >= CHELSIO_T7)
10815 		nchan = 1 << G_T7_PMTXNUMCHN(lo);
10816 	else
10817 		nchan = 1 << G_PMTXNUMCHN(lo);
10818 	for (i = 0, free = 0; i < nchan; i++)
10819 		free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT));
10820 	sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n",
10821 		   G_PMTXMAXPAGE(lo), free,
10822 		   hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
10823 		   hi >= (1 << 20) ? 'M' : 'K', nchan);
10824 	sbuf_printf(sb, "%u p-structs (%u free)\n",
10825 		   t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT),
10826 		   G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT)));
10827 
10828 	for (i = 0; i < 4; i++) {
10829 		if (chip_id(sc) > CHELSIO_T5)
10830 			lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
10831 		else
10832 			lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
10833 		if (is_t5(sc)) {
10834 			used = G_T5_USED(lo);
10835 			alloc = G_T5_ALLOC(lo);
10836 		} else {
10837 			used = G_USED(lo);
10838 			alloc = G_ALLOC(lo);
10839 		}
10840 		/* For T6+ these are MAC buffer groups */
10841 		sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
10842 		    i, used, alloc);
10843 	}
10844 	for (i = 0; i < sc->chip_params->nchan; i++) {
10845 		if (chip_id(sc) > CHELSIO_T5)
10846 			lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
10847 		else
10848 			lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
10849 		if (is_t5(sc)) {
10850 			used = G_T5_USED(lo);
10851 			alloc = G_T5_ALLOC(lo);
10852 		} else {
10853 			used = G_USED(lo);
10854 			alloc = G_ALLOC(lo);
10855 		}
10856 		/* For T6+ these are MAC buffer groups */
10857 		sbuf_printf(sb,
10858 		    "\nLoopback %d using %u pages out of %u allocated",
10859 		    i, used, alloc);
10860 	}
10861 done:
10862 	mtx_unlock(&sc->reg_lock);
10863 	if (rc == 0)
10864 		rc = sbuf_finish(sb);
10865 	sbuf_delete(sb);
10866 	return (rc);
10867 }
10868 
10869 static inline void
10870 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
10871 {
10872 	*mask = x | y;
10873 	y = htobe64(y);
10874 	memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
10875 }
10876 
10877 static int
10878 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
10879 {
10880 	struct adapter *sc = arg1;
10881 	struct sbuf *sb;
10882 	int rc, i;
10883 
10884 	MPASS(chip_id(sc) <= CHELSIO_T5);
10885 
10886 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10887 	if (sb == NULL)
10888 		return (ENOMEM);
10889 
10890 	sbuf_printf(sb,
10891 	    "Idx  Ethernet address     Mask     Vld Ports PF"
10892 	    "  VF              Replication             P0 P1 P2 P3  ML");
10893 	rc = 0;
10894 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10895 		uint64_t tcamx, tcamy, mask;
10896 		uint32_t cls_lo, cls_hi;
10897 		uint8_t addr[ETHER_ADDR_LEN];
10898 
10899 		mtx_lock(&sc->reg_lock);
10900 		if (hw_off_limits(sc))
10901 			rc = ENXIO;
10902 		else {
10903 			tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
10904 			tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
10905 		}
10906 		mtx_unlock(&sc->reg_lock);
10907 		if (rc != 0)
10908 			break;
10909 		if (tcamx & tcamy)
10910 			continue;
10911 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
10912 		mtx_lock(&sc->reg_lock);
10913 		if (hw_off_limits(sc))
10914 			rc = ENXIO;
10915 		else {
10916 			cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10917 			cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10918 		}
10919 		mtx_unlock(&sc->reg_lock);
10920 		if (rc != 0)
10921 			break;
10922 		sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
10923 			   "  %c   %#x%4u%4d", i, addr[0], addr[1], addr[2],
10924 			   addr[3], addr[4], addr[5], (uintmax_t)mask,
10925 			   (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
10926 			   G_PORTMAP(cls_hi), G_PF(cls_lo),
10927 			   (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
10928 
10929 		if (cls_lo & F_REPLICATE) {
10930 			struct fw_ldst_cmd ldst_cmd;
10931 
10932 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10933 			ldst_cmd.op_to_addrspace =
10934 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10935 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
10936 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10937 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10938 			ldst_cmd.u.mps.rplc.fid_idx =
10939 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10940 				V_FW_LDST_CMD_IDX(i));
10941 
10942 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10943 			    "t4mps");
10944 			if (rc)
10945 				break;
10946 			if (hw_off_limits(sc))
10947 				rc = ENXIO;
10948 			else
10949 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10950 				    sizeof(ldst_cmd), &ldst_cmd);
10951 			end_synchronized_op(sc, 0);
10952 			if (rc != 0)
10953 				break;
10954 			else {
10955 				sbuf_printf(sb, " %08x %08x %08x %08x",
10956 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10957 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10958 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10959 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10960 			}
10961 		} else
10962 			sbuf_printf(sb, "%36s", "");
10963 
10964 		sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
10965 		    G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
10966 		    G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
10967 	}
10968 
10969 	if (rc)
10970 		(void) sbuf_finish(sb);
10971 	else
10972 		rc = sbuf_finish(sb);
10973 	sbuf_delete(sb);
10974 
10975 	return (rc);
10976 }
10977 
10978 static int
10979 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
10980 {
10981 	struct adapter *sc = arg1;
10982 	struct sbuf *sb;
10983 	int rc, i;
10984 
10985 	MPASS(chip_id(sc) == CHELSIO_T6);
10986 
10987 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10988 	if (sb == NULL)
10989 		return (ENOMEM);
10990 
10991 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
10992 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
10993 	    "                           Replication"
10994 	    "                                    P0 P1 P2 P3  ML");
10995 
10996 	rc = 0;
10997 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10998 		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
10999 		uint16_t ivlan;
11000 		uint64_t tcamx, tcamy, val, mask;
11001 		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
11002 		uint8_t addr[ETHER_ADDR_LEN];
11003 
11004 		ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
11005 		if (i < 256)
11006 			ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
11007 		else
11008 			ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
11009 		mtx_lock(&sc->reg_lock);
11010 		if (hw_off_limits(sc))
11011 			rc = ENXIO;
11012 		else {
11013 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11014 			val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
11015 			tcamy = G_DMACH(val) << 32;
11016 			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
11017 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
11018 		}
11019 		mtx_unlock(&sc->reg_lock);
11020 		if (rc != 0)
11021 			break;
11022 
11023 		lookup_type = G_DATALKPTYPE(data2);
11024 		port_num = G_DATAPORTNUM(data2);
11025 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11026 			/* Inner header VNI */
11027 			vniy = ((data2 & F_DATAVIDH2) << 23) |
11028 				       (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
11029 			dip_hit = data2 & F_DATADIPHIT;
11030 			vlan_vld = 0;
11031 		} else {
11032 			vniy = 0;
11033 			dip_hit = 0;
11034 			vlan_vld = data2 & F_DATAVIDH2;
11035 			ivlan = G_VIDL(val);
11036 		}
11037 
11038 		ctl |= V_CTLXYBITSEL(1);
11039 		mtx_lock(&sc->reg_lock);
11040 		if (hw_off_limits(sc))
11041 			rc = ENXIO;
11042 		else {
11043 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11044 			val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
11045 			tcamx = G_DMACH(val) << 32;
11046 			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
11047 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
11048 		}
11049 		mtx_unlock(&sc->reg_lock);
11050 		if (rc != 0)
11051 			break;
11052 
11053 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11054 			/* Inner header VNI mask */
11055 			vnix = ((data2 & F_DATAVIDH2) << 23) |
11056 			       (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
11057 		} else
11058 			vnix = 0;
11059 
11060 		if (tcamx & tcamy)
11061 			continue;
11062 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
11063 
11064 		mtx_lock(&sc->reg_lock);
11065 		if (hw_off_limits(sc))
11066 			rc = ENXIO;
11067 		else {
11068 			cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11069 			cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
11070 		}
11071 		mtx_unlock(&sc->reg_lock);
11072 		if (rc != 0)
11073 			break;
11074 
11075 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11076 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11077 			    "%012jx %06x %06x    -    -   %3c"
11078 			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
11079 			    addr[1], addr[2], addr[3], addr[4], addr[5],
11080 			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
11081 			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11082 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11083 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11084 		} else {
11085 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11086 			    "%012jx    -       -   ", i, addr[0], addr[1],
11087 			    addr[2], addr[3], addr[4], addr[5],
11088 			    (uintmax_t)mask);
11089 
11090 			if (vlan_vld)
11091 				sbuf_printf(sb, "%4u   Y     ", ivlan);
11092 			else
11093 				sbuf_printf(sb, "  -    N     ");
11094 
11095 			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
11096 			    lookup_type ? 'I' : 'O', port_num,
11097 			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11098 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11099 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11100 		}
11101 
11102 
11103 		if (cls_lo & F_T6_REPLICATE) {
11104 			struct fw_ldst_cmd ldst_cmd;
11105 
11106 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11107 			ldst_cmd.op_to_addrspace =
11108 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
11109 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
11110 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
11111 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
11112 			ldst_cmd.u.mps.rplc.fid_idx =
11113 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
11114 				V_FW_LDST_CMD_IDX(i));
11115 
11116 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
11117 			    "t6mps");
11118 			if (rc)
11119 				break;
11120 			if (hw_off_limits(sc))
11121 				rc = ENXIO;
11122 			else
11123 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
11124 				    sizeof(ldst_cmd), &ldst_cmd);
11125 			end_synchronized_op(sc, 0);
11126 			if (rc != 0)
11127 				break;
11128 			else {
11129 				sbuf_printf(sb, " %08x %08x %08x %08x"
11130 				    " %08x %08x %08x %08x",
11131 				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
11132 				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
11133 				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
11134 				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
11135 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
11136 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
11137 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
11138 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
11139 			}
11140 		} else
11141 			sbuf_printf(sb, "%72s", "");
11142 
11143 		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
11144 		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11145 		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11146 		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11147 	}
11148 
11149 	if (rc)
11150 		(void) sbuf_finish(sb);
11151 	else
11152 		rc = sbuf_finish(sb);
11153 	sbuf_delete(sb);
11154 
11155 	return (rc);
11156 }
11157 
11158 static int
11159 sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS)
11160 {
11161 	struct adapter *sc = arg1;
11162 	struct sbuf *sb;
11163 	int rc, i;
11164 
11165 	MPASS(chip_id(sc) >= CHELSIO_T7);
11166 
11167 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11168 	if (sb == NULL)
11169 		return (ENOMEM);
11170 
11171 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
11172 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
11173 	    "                           Replication"
11174 	    "                                    P0 P1 P2 P3  ML");
11175 
11176 	rc = 0;
11177 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
11178 		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
11179 		uint16_t ivlan;
11180 		uint64_t tcamx, tcamy, val, mask;
11181 		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
11182 		uint8_t addr[ETHER_ADDR_LEN];
11183 
11184 		/* Read tcamy */
11185 		ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
11186 		if (chip_rev(sc) == 0) {
11187 			if (i < 256)
11188 				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
11189 			else
11190 				ctl |= V_CTLTCAMINDEX(i - 256) | V_T7_CTLTCAMSEL(1);
11191 		} else {
11192 #if 0
11193 			ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
11194 #endif
11195 			if (i < 512)
11196 				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
11197 			else if (i < 1024)
11198 				ctl |= V_CTLTCAMINDEX(i - 512) | V_T7_CTLTCAMSEL(1);
11199 			else
11200 				ctl |= V_CTLTCAMINDEX(i - 1024) | V_T7_CTLTCAMSEL(2);
11201 		}
11202 
11203 		mtx_lock(&sc->reg_lock);
11204 		if (hw_off_limits(sc))
11205 			rc = ENXIO;
11206 		else {
11207 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11208 			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
11209 			tcamy = G_DMACH(val) << 32;
11210 			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
11211 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
11212 		}
11213 		mtx_unlock(&sc->reg_lock);
11214 		if (rc != 0)
11215 			break;
11216 
11217 		lookup_type = G_DATALKPTYPE(data2);
11218 		port_num = G_DATAPORTNUM(data2);
11219 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11220 			/* Inner header VNI */
11221 			vniy = (((data2 & F_DATAVIDH2) |
11222 			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
11223 			dip_hit = data2 & F_DATADIPHIT;
11224 			vlan_vld = 0;
11225 		} else {
11226 			vniy = 0;
11227 			dip_hit = 0;
11228 			vlan_vld = data2 & F_DATAVIDH2;
11229 			ivlan = G_VIDL(val);
11230 		}
11231 
11232 		ctl |= V_CTLXYBITSEL(1);
11233 		mtx_lock(&sc->reg_lock);
11234 		if (hw_off_limits(sc))
11235 			rc = ENXIO;
11236 		else {
11237 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11238 			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
11239 			tcamx = G_DMACH(val) << 32;
11240 			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
11241 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
11242 		}
11243 		mtx_unlock(&sc->reg_lock);
11244 		if (rc != 0)
11245 			break;
11246 
11247 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11248 			/* Inner header VNI mask */
11249 			vnix = (((data2 & F_DATAVIDH2) |
11250 			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
11251 		} else
11252 			vnix = 0;
11253 
11254 		if (tcamx & tcamy)
11255 			continue;
11256 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
11257 
11258 		mtx_lock(&sc->reg_lock);
11259 		if (hw_off_limits(sc))
11260 			rc = ENXIO;
11261 		else {
11262 			if (chip_rev(sc) == 0) {
11263 				cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11264 				cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
11265 			} else {
11266 				t4_write_reg(sc, A_MPS_CLS_SRAM_H,
11267 				    V_SRAMWRN(0) | V_SRAMINDEX(i));
11268 				cls_lo = t4_read_reg(sc, A_MPS_CLS_SRAM_L);
11269 				cls_hi = t4_read_reg(sc, A_MPS_CLS_SRAM_H);
11270 			}
11271 		}
11272 		mtx_unlock(&sc->reg_lock);
11273 		if (rc != 0)
11274 			break;
11275 
11276 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11277 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11278 			    "%012jx %06x %06x    -    -   %3c"
11279 			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
11280 			    addr[1], addr[2], addr[3], addr[4], addr[5],
11281 			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
11282 			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11283 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11284 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11285 		} else {
11286 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11287 			    "%012jx    -       -   ", i, addr[0], addr[1],
11288 			    addr[2], addr[3], addr[4], addr[5],
11289 			    (uintmax_t)mask);
11290 
11291 			if (vlan_vld)
11292 				sbuf_printf(sb, "%4u   Y     ", ivlan);
11293 			else
11294 				sbuf_printf(sb, "  -    N     ");
11295 
11296 			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
11297 			    lookup_type ? 'I' : 'O', port_num,
11298 			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11299 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11300 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11301 		}
11302 
11303 		if (cls_lo & F_T6_REPLICATE) {
11304 			struct fw_ldst_cmd ldst_cmd;
11305 
11306 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11307 			ldst_cmd.op_to_addrspace =
11308 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
11309 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
11310 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
11311 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
11312 			ldst_cmd.u.mps.rplc.fid_idx =
11313 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
11314 				V_FW_LDST_CMD_IDX(i));
11315 
11316 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
11317 			    "t6mps");
11318 			if (rc)
11319 				break;
11320 			if (hw_off_limits(sc))
11321 				rc = ENXIO;
11322 			else
11323 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
11324 				    sizeof(ldst_cmd), &ldst_cmd);
11325 			end_synchronized_op(sc, 0);
11326 			if (rc != 0)
11327 				break;
11328 			else {
11329 				sbuf_printf(sb, " %08x %08x %08x %08x"
11330 				    " %08x %08x %08x %08x",
11331 				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
11332 				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
11333 				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
11334 				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
11335 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
11336 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
11337 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
11338 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
11339 			}
11340 		} else
11341 			sbuf_printf(sb, "%72s", "");
11342 
11343 		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
11344 		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11345 		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11346 		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11347 	}
11348 
11349 	if (rc)
11350 		(void) sbuf_finish(sb);
11351 	else
11352 		rc = sbuf_finish(sb);
11353 	sbuf_delete(sb);
11354 
11355 	return (rc);
11356 }
11357 
11358 static int
11359 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
11360 {
11361 	struct adapter *sc = arg1;
11362 	struct sbuf *sb;
11363 	int rc;
11364 	uint16_t mtus[NMTUS];
11365 
11366 	rc = 0;
11367 	mtx_lock(&sc->reg_lock);
11368 	if (hw_off_limits(sc))
11369 		rc = ENXIO;
11370 	else
11371 		t4_read_mtu_tbl(sc, mtus, NULL);
11372 	mtx_unlock(&sc->reg_lock);
11373 	if (rc != 0)
11374 		return (rc);
11375 
11376 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11377 	if (sb == NULL)
11378 		return (ENOMEM);
11379 
11380 	sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
11381 	    mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
11382 	    mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
11383 	    mtus[14], mtus[15]);
11384 
11385 	rc = sbuf_finish(sb);
11386 	sbuf_delete(sb);
11387 
11388 	return (rc);
11389 }
11390 
11391 static int
11392 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
11393 {
11394 	struct adapter *sc = arg1;
11395 	struct sbuf *sb;
11396 	int rc, i;
11397 	uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
11398 	uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
11399 	uint32_t stats[T7_PM_RX_CACHE_NSTATS];
11400 	static const char *tx_stats[MAX_PM_NSTATS] = {
11401 		"Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
11402 		"Tx FIFO wait", NULL, "Tx latency"
11403 	};
11404 	static const char *rx_stats[MAX_PM_NSTATS] = {
11405 		"Read:", "Write bypass:", "Write mem:", "Flush:",
11406 		"Rx FIFO wait", NULL, "Rx latency"
11407 	};
11408 
11409 	rc = 0;
11410 	mtx_lock(&sc->reg_lock);
11411 	if (hw_off_limits(sc))
11412 		rc = ENXIO;
11413 	else {
11414 		t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
11415 		t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
11416 		if (chip_id(sc) >= CHELSIO_T7)
11417 			t4_pmrx_cache_get_stats(sc, stats);
11418 	}
11419 	mtx_unlock(&sc->reg_lock);
11420 	if (rc != 0)
11421 		return (rc);
11422 
11423 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11424 	if (sb == NULL)
11425 		return (ENOMEM);
11426 
11427 	sbuf_printf(sb, "                Tx pcmds             Tx bytes");
11428 	for (i = 0; i < 4; i++) {
11429 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11430 		    tx_cyc[i]);
11431 	}
11432 
11433 	sbuf_printf(sb, "\n                Rx pcmds             Rx bytes");
11434 	for (i = 0; i < 4; i++) {
11435 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11436 		    rx_cyc[i]);
11437 	}
11438 
11439 	if (chip_id(sc) > CHELSIO_T5) {
11440 		sbuf_printf(sb,
11441 		    "\n              Total wait      Total occupancy");
11442 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11443 		    tx_cyc[i]);
11444 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11445 		    rx_cyc[i]);
11446 
11447 		i += 2;
11448 		MPASS(i < nitems(tx_stats));
11449 
11450 		sbuf_printf(sb,
11451 		    "\n                   Reads           Total wait");
11452 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11453 		    tx_cyc[i]);
11454 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11455 		    rx_cyc[i]);
11456 	}
11457 
11458 	if (chip_id(sc) >= CHELSIO_T7) {
11459 		i = 0;
11460 		sbuf_printf(sb, "\n\nPM RX Cache Stats\n");
11461 		sbuf_printf(sb, "%-40s    %u\n", "ReqWrite", stats[i++]);
11462 		sbuf_printf(sb, "%-40s    %u\n", "ReqReadInv", stats[i++]);
11463 		sbuf_printf(sb, "%-40s    %u\n", "ReqReadNoInv", stats[i++]);
11464 		sbuf_printf(sb, "%-40s    %u\n", "Write Split Request",
11465 			   stats[i++]);
11466 		sbuf_printf(sb, "%-40s    %u\n",
11467 			   "Normal Read Split (Read Invalidate)", stats[i++]);
11468 		sbuf_printf(sb, "%-40s    %u\n",
11469 			   "Feedback Read Split (Read NoInvalidate)",
11470 			   stats[i++]);
11471 		sbuf_printf(sb, "%-40s    %u\n", "Write Hit", stats[i++]);
11472 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit",
11473 			   stats[i++]);
11474 		sbuf_printf(sb, "%-40s    %u\n", "Feedback Read Hit",
11475 			   stats[i++]);
11476 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full Avail",
11477 			   stats[i++]);
11478 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full UnAvail",
11479 			   stats[i++]);
11480 		sbuf_printf(sb, "%-40s    %u\n",
11481 			   "Normal Read Hit Partial Avail",
11482 			   stats[i++]);
11483 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full Avail",
11484 			   stats[i++]);
11485 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full UnAvail",
11486 			   stats[i++]);
11487 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Partial Avail",
11488 			   stats[i++]);
11489 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Full Free",
11490 			   stats[i++]);
11491 		sbuf_printf(sb, "%-40s    %u\n",
11492 			   "Normal Read Part-avail Mul-Regions",
11493 			   stats[i++]);
11494 		sbuf_printf(sb, "%-40s    %u\n",
11495 			   "FB Read Part-avail Mul-Regions",
11496 			   stats[i++]);
11497 		sbuf_printf(sb, "%-40s    %u\n", "Write Miss FL Used",
11498 			   stats[i++]);
11499 		sbuf_printf(sb, "%-40s    %u\n", "Write Miss LRU Used",
11500 			   stats[i++]);
11501 		sbuf_printf(sb, "%-40s    %u\n",
11502 			   "Write Miss LRU-Multiple Evict", stats[i++]);
11503 		sbuf_printf(sb, "%-40s    %u\n",
11504 			   "Write Hit Increasing Islands", stats[i++]);
11505 		sbuf_printf(sb, "%-40s    %u\n",
11506 			   "Normal Read Island Read split", stats[i++]);
11507 		sbuf_printf(sb, "%-40s    %u\n", "Write Overflow Eviction",
11508 			   stats[i++]);
11509 		sbuf_printf(sb, "%-40s    %u", "Read Overflow Eviction",
11510 			   stats[i++]);
11511 	}
11512 
11513 	rc = sbuf_finish(sb);
11514 	sbuf_delete(sb);
11515 
11516 	return (rc);
11517 }
11518 
11519 static int
11520 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
11521 {
11522 	struct adapter *sc = arg1;
11523 	struct sbuf *sb;
11524 	int rc;
11525 	struct tp_rdma_stats stats;
11526 
11527 	rc = 0;
11528 	mtx_lock(&sc->reg_lock);
11529 	if (hw_off_limits(sc))
11530 		rc = ENXIO;
11531 	else
11532 		t4_tp_get_rdma_stats(sc, &stats, 0);
11533 	mtx_unlock(&sc->reg_lock);
11534 	if (rc != 0)
11535 		return (rc);
11536 
11537 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11538 	if (sb == NULL)
11539 		return (ENOMEM);
11540 
11541 	sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
11542 	sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
11543 
11544 	rc = sbuf_finish(sb);
11545 	sbuf_delete(sb);
11546 
11547 	return (rc);
11548 }
11549 
11550 static int
11551 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
11552 {
11553 	struct adapter *sc = arg1;
11554 	struct sbuf *sb;
11555 	int rc;
11556 	struct tp_tcp_stats v4, v6;
11557 
11558 	rc = 0;
11559 	mtx_lock(&sc->reg_lock);
11560 	if (hw_off_limits(sc))
11561 		rc = ENXIO;
11562 	else
11563 		t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
11564 	mtx_unlock(&sc->reg_lock);
11565 	if (rc != 0)
11566 		return (rc);
11567 
11568 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11569 	if (sb == NULL)
11570 		return (ENOMEM);
11571 
11572 	sbuf_printf(sb,
11573 	    "                                IP                 IPv6\n");
11574 	sbuf_printf(sb, "OutRsts:      %20u %20u\n",
11575 	    v4.tcp_out_rsts, v6.tcp_out_rsts);
11576 	sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
11577 	    v4.tcp_in_segs, v6.tcp_in_segs);
11578 	sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
11579 	    v4.tcp_out_segs, v6.tcp_out_segs);
11580 	sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
11581 	    v4.tcp_retrans_segs, v6.tcp_retrans_segs);
11582 
11583 	rc = sbuf_finish(sb);
11584 	sbuf_delete(sb);
11585 
11586 	return (rc);
11587 }
11588 
11589 static int
11590 sysctl_tids(SYSCTL_HANDLER_ARGS)
11591 {
11592 	struct adapter *sc = arg1;
11593 	struct sbuf *sb;
11594 	int rc;
11595 	uint32_t x, y;
11596 	struct tid_info *t = &sc->tids;
11597 
11598 	rc = 0;
11599 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11600 	if (sb == NULL)
11601 		return (ENOMEM);
11602 
11603 	if (t->natids) {
11604 		sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
11605 		    t->atids_in_use);
11606 	}
11607 
11608 	if (t->nhpftids) {
11609 		sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
11610 		    t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
11611 	}
11612 
11613 	if (t->ntids) {
11614 		bool hashen = false;
11615 
11616 		mtx_lock(&sc->reg_lock);
11617 		if (hw_off_limits(sc))
11618 			rc = ENXIO;
11619 		else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
11620 			hashen = true;
11621 			if (chip_id(sc) <= CHELSIO_T5) {
11622 				x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
11623 				y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
11624 			} else {
11625 				x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
11626 				y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
11627 			}
11628 		}
11629 		mtx_unlock(&sc->reg_lock);
11630 		if (rc != 0)
11631 			goto done;
11632 
11633 		sbuf_printf(sb, "TID range: ");
11634 		if (hashen) {
11635 			if (x)
11636 				sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1);
11637 			sbuf_printf(sb, "%u-%u", y, t->tid_base + t->ntids - 1);
11638 		} else {
11639 			sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base +
11640 			    t->ntids - 1);
11641 		}
11642 		sbuf_printf(sb, ", in use: %u\n",
11643 		    atomic_load_acq_int(&t->tids_in_use));
11644 	}
11645 
11646 	if (t->nstids) {
11647 		sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
11648 		    t->stid_base + t->nstids - 1, t->stids_in_use);
11649 	}
11650 
11651 	if (t->nftids) {
11652 		sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
11653 		    t->ftid_end, t->ftids_in_use);
11654 	}
11655 
11656 	if (t->netids) {
11657 		sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
11658 		    t->etid_base + t->netids - 1, t->etids_in_use);
11659 	}
11660 
11661 	mtx_lock(&sc->reg_lock);
11662 	if (hw_off_limits(sc))
11663 		rc = ENXIO;
11664 	else {
11665 		x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4);
11666 		y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6);
11667 	}
11668 	mtx_unlock(&sc->reg_lock);
11669 	if (rc != 0)
11670 		goto done;
11671 	sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y);
11672 done:
11673 	if (rc == 0)
11674 		rc = sbuf_finish(sb);
11675 	else
11676 		(void)sbuf_finish(sb);
11677 	sbuf_delete(sb);
11678 
11679 	return (rc);
11680 }
11681 
11682 static int
11683 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
11684 {
11685 	struct adapter *sc = arg1;
11686 	struct sbuf *sb;
11687 	int rc;
11688 	struct tp_err_stats stats;
11689 
11690 	rc = 0;
11691 	mtx_lock(&sc->reg_lock);
11692 	if (hw_off_limits(sc))
11693 		rc = ENXIO;
11694 	else
11695 		t4_tp_get_err_stats(sc, &stats, 0);
11696 	mtx_unlock(&sc->reg_lock);
11697 	if (rc != 0)
11698 		return (rc);
11699 
11700 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11701 	if (sb == NULL)
11702 		return (ENOMEM);
11703 
11704 	if (sc->chip_params->nchan > 2) {
11705 		sbuf_printf(sb, "                 channel 0  channel 1"
11706 		    "  channel 2  channel 3\n");
11707 		sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
11708 		    stats.mac_in_errs[0], stats.mac_in_errs[1],
11709 		    stats.mac_in_errs[2], stats.mac_in_errs[3]);
11710 		sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
11711 		    stats.hdr_in_errs[0], stats.hdr_in_errs[1],
11712 		    stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
11713 		sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
11714 		    stats.tcp_in_errs[0], stats.tcp_in_errs[1],
11715 		    stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
11716 		sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
11717 		    stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
11718 		    stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
11719 		sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
11720 		    stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
11721 		    stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
11722 		sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
11723 		    stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
11724 		    stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
11725 		sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
11726 		    stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
11727 		    stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
11728 		sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
11729 		    stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
11730 		    stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
11731 	} else {
11732 		sbuf_printf(sb, "                 channel 0  channel 1\n");
11733 		sbuf_printf(sb, "macInErrs:      %10u %10u\n",
11734 		    stats.mac_in_errs[0], stats.mac_in_errs[1]);
11735 		sbuf_printf(sb, "hdrInErrs:      %10u %10u\n",
11736 		    stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
11737 		sbuf_printf(sb, "tcpInErrs:      %10u %10u\n",
11738 		    stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
11739 		sbuf_printf(sb, "tcp6InErrs:     %10u %10u\n",
11740 		    stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
11741 		sbuf_printf(sb, "tnlCongDrops:   %10u %10u\n",
11742 		    stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
11743 		sbuf_printf(sb, "tnlTxDrops:     %10u %10u\n",
11744 		    stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
11745 		sbuf_printf(sb, "ofldVlanDrops:  %10u %10u\n",
11746 		    stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
11747 		sbuf_printf(sb, "ofldChanDrops:  %10u %10u\n\n",
11748 		    stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
11749 	}
11750 
11751 	sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
11752 	    stats.ofld_no_neigh, stats.ofld_cong_defer);
11753 
11754 	rc = sbuf_finish(sb);
11755 	sbuf_delete(sb);
11756 
11757 	return (rc);
11758 }
11759 
11760 static int
11761 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS)
11762 {
11763 	struct adapter *sc = arg1;
11764 	struct sbuf *sb;
11765 	int rc;
11766 	struct tp_tnl_stats stats;
11767 
11768 	rc = 0;
11769 	mtx_lock(&sc->reg_lock);
11770 	if (hw_off_limits(sc))
11771 		rc = ENXIO;
11772 	else
11773 		t4_tp_get_tnl_stats(sc, &stats, 1);
11774 	mtx_unlock(&sc->reg_lock);
11775 	if (rc != 0)
11776 		return (rc);
11777 
11778 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11779 	if (sb == NULL)
11780 		return (ENOMEM);
11781 
11782 	if (sc->chip_params->nchan > 2) {
11783 		sbuf_printf(sb, "           channel 0  channel 1"
11784 		    "  channel 2  channel 3\n");
11785 		sbuf_printf(sb, "OutPkts:  %10u %10u %10u %10u\n",
11786 		    stats.out_pkt[0], stats.out_pkt[1],
11787 		    stats.out_pkt[2], stats.out_pkt[3]);
11788 		sbuf_printf(sb, "InPkts:   %10u %10u %10u %10u",
11789 		    stats.in_pkt[0], stats.in_pkt[1],
11790 		    stats.in_pkt[2], stats.in_pkt[3]);
11791 	} else {
11792 		sbuf_printf(sb, "           channel 0  channel 1\n");
11793 		sbuf_printf(sb, "OutPkts:  %10u %10u\n",
11794 		    stats.out_pkt[0], stats.out_pkt[1]);
11795 		sbuf_printf(sb, "InPkts:   %10u %10u",
11796 		    stats.in_pkt[0], stats.in_pkt[1]);
11797 	}
11798 
11799 	rc = sbuf_finish(sb);
11800 	sbuf_delete(sb);
11801 
11802 	return (rc);
11803 }
11804 
11805 static int
11806 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
11807 {
11808 	struct adapter *sc = arg1;
11809 	struct tp_params *tpp = &sc->params.tp;
11810 	u_int mask;
11811 	int rc;
11812 
11813 	mask = tpp->la_mask >> 16;
11814 	rc = sysctl_handle_int(oidp, &mask, 0, req);
11815 	if (rc != 0 || req->newptr == NULL)
11816 		return (rc);
11817 	if (mask > 0xffff)
11818 		return (EINVAL);
11819 	mtx_lock(&sc->reg_lock);
11820 	if (hw_off_limits(sc))
11821 		rc = ENXIO;
11822 	else {
11823 		tpp->la_mask = mask << 16;
11824 		t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U,
11825 		    tpp->la_mask);
11826 	}
11827 	mtx_unlock(&sc->reg_lock);
11828 
11829 	return (rc);
11830 }
11831 
11832 struct field_desc {
11833 	const char *name;
11834 	u_int start;
11835 	u_int width;
11836 };
11837 
11838 static void
11839 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
11840 {
11841 	char buf[32];
11842 	int line_size = 0;
11843 
11844 	while (f->name) {
11845 		uint64_t mask = (1ULL << f->width) - 1;
11846 		int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
11847 		    ((uintmax_t)v >> f->start) & mask);
11848 
11849 		if (line_size + len >= 79) {
11850 			line_size = 8;
11851 			sbuf_printf(sb, "\n        ");
11852 		}
11853 		sbuf_printf(sb, "%s ", buf);
11854 		line_size += len + 1;
11855 		f++;
11856 	}
11857 	sbuf_printf(sb, "\n");
11858 }
11859 
11860 static const struct field_desc tp_la0[] = {
11861 	{ "RcfOpCodeOut", 60, 4 },
11862 	{ "State", 56, 4 },
11863 	{ "WcfState", 52, 4 },
11864 	{ "RcfOpcSrcOut", 50, 2 },
11865 	{ "CRxError", 49, 1 },
11866 	{ "ERxError", 48, 1 },
11867 	{ "SanityFailed", 47, 1 },
11868 	{ "SpuriousMsg", 46, 1 },
11869 	{ "FlushInputMsg", 45, 1 },
11870 	{ "FlushInputCpl", 44, 1 },
11871 	{ "RssUpBit", 43, 1 },
11872 	{ "RssFilterHit", 42, 1 },
11873 	{ "Tid", 32, 10 },
11874 	{ "InitTcb", 31, 1 },
11875 	{ "LineNumber", 24, 7 },
11876 	{ "Emsg", 23, 1 },
11877 	{ "EdataOut", 22, 1 },
11878 	{ "Cmsg", 21, 1 },
11879 	{ "CdataOut", 20, 1 },
11880 	{ "EreadPdu", 19, 1 },
11881 	{ "CreadPdu", 18, 1 },
11882 	{ "TunnelPkt", 17, 1 },
11883 	{ "RcfPeerFin", 16, 1 },
11884 	{ "RcfReasonOut", 12, 4 },
11885 	{ "TxCchannel", 10, 2 },
11886 	{ "RcfTxChannel", 8, 2 },
11887 	{ "RxEchannel", 6, 2 },
11888 	{ "RcfRxChannel", 5, 1 },
11889 	{ "RcfDataOutSrdy", 4, 1 },
11890 	{ "RxDvld", 3, 1 },
11891 	{ "RxOoDvld", 2, 1 },
11892 	{ "RxCongestion", 1, 1 },
11893 	{ "TxCongestion", 0, 1 },
11894 	{ NULL }
11895 };
11896 
11897 static const struct field_desc tp_la1[] = {
11898 	{ "CplCmdIn", 56, 8 },
11899 	{ "CplCmdOut", 48, 8 },
11900 	{ "ESynOut", 47, 1 },
11901 	{ "EAckOut", 46, 1 },
11902 	{ "EFinOut", 45, 1 },
11903 	{ "ERstOut", 44, 1 },
11904 	{ "SynIn", 43, 1 },
11905 	{ "AckIn", 42, 1 },
11906 	{ "FinIn", 41, 1 },
11907 	{ "RstIn", 40, 1 },
11908 	{ "DataIn", 39, 1 },
11909 	{ "DataInVld", 38, 1 },
11910 	{ "PadIn", 37, 1 },
11911 	{ "RxBufEmpty", 36, 1 },
11912 	{ "RxDdp", 35, 1 },
11913 	{ "RxFbCongestion", 34, 1 },
11914 	{ "TxFbCongestion", 33, 1 },
11915 	{ "TxPktSumSrdy", 32, 1 },
11916 	{ "RcfUlpType", 28, 4 },
11917 	{ "Eread", 27, 1 },
11918 	{ "Ebypass", 26, 1 },
11919 	{ "Esave", 25, 1 },
11920 	{ "Static0", 24, 1 },
11921 	{ "Cread", 23, 1 },
11922 	{ "Cbypass", 22, 1 },
11923 	{ "Csave", 21, 1 },
11924 	{ "CPktOut", 20, 1 },
11925 	{ "RxPagePoolFull", 18, 2 },
11926 	{ "RxLpbkPkt", 17, 1 },
11927 	{ "TxLpbkPkt", 16, 1 },
11928 	{ "RxVfValid", 15, 1 },
11929 	{ "SynLearned", 14, 1 },
11930 	{ "SetDelEntry", 13, 1 },
11931 	{ "SetInvEntry", 12, 1 },
11932 	{ "CpcmdDvld", 11, 1 },
11933 	{ "CpcmdSave", 10, 1 },
11934 	{ "RxPstructsFull", 8, 2 },
11935 	{ "EpcmdDvld", 7, 1 },
11936 	{ "EpcmdFlush", 6, 1 },
11937 	{ "EpcmdTrimPrefix", 5, 1 },
11938 	{ "EpcmdTrimPostfix", 4, 1 },
11939 	{ "ERssIp4Pkt", 3, 1 },
11940 	{ "ERssIp6Pkt", 2, 1 },
11941 	{ "ERssTcpUdpPkt", 1, 1 },
11942 	{ "ERssFceFipPkt", 0, 1 },
11943 	{ NULL }
11944 };
11945 
11946 static const struct field_desc tp_la2[] = {
11947 	{ "CplCmdIn", 56, 8 },
11948 	{ "MpsVfVld", 55, 1 },
11949 	{ "MpsPf", 52, 3 },
11950 	{ "MpsVf", 44, 8 },
11951 	{ "SynIn", 43, 1 },
11952 	{ "AckIn", 42, 1 },
11953 	{ "FinIn", 41, 1 },
11954 	{ "RstIn", 40, 1 },
11955 	{ "DataIn", 39, 1 },
11956 	{ "DataInVld", 38, 1 },
11957 	{ "PadIn", 37, 1 },
11958 	{ "RxBufEmpty", 36, 1 },
11959 	{ "RxDdp", 35, 1 },
11960 	{ "RxFbCongestion", 34, 1 },
11961 	{ "TxFbCongestion", 33, 1 },
11962 	{ "TxPktSumSrdy", 32, 1 },
11963 	{ "RcfUlpType", 28, 4 },
11964 	{ "Eread", 27, 1 },
11965 	{ "Ebypass", 26, 1 },
11966 	{ "Esave", 25, 1 },
11967 	{ "Static0", 24, 1 },
11968 	{ "Cread", 23, 1 },
11969 	{ "Cbypass", 22, 1 },
11970 	{ "Csave", 21, 1 },
11971 	{ "CPktOut", 20, 1 },
11972 	{ "RxPagePoolFull", 18, 2 },
11973 	{ "RxLpbkPkt", 17, 1 },
11974 	{ "TxLpbkPkt", 16, 1 },
11975 	{ "RxVfValid", 15, 1 },
11976 	{ "SynLearned", 14, 1 },
11977 	{ "SetDelEntry", 13, 1 },
11978 	{ "SetInvEntry", 12, 1 },
11979 	{ "CpcmdDvld", 11, 1 },
11980 	{ "CpcmdSave", 10, 1 },
11981 	{ "RxPstructsFull", 8, 2 },
11982 	{ "EpcmdDvld", 7, 1 },
11983 	{ "EpcmdFlush", 6, 1 },
11984 	{ "EpcmdTrimPrefix", 5, 1 },
11985 	{ "EpcmdTrimPostfix", 4, 1 },
11986 	{ "ERssIp4Pkt", 3, 1 },
11987 	{ "ERssIp6Pkt", 2, 1 },
11988 	{ "ERssTcpUdpPkt", 1, 1 },
11989 	{ "ERssFceFipPkt", 0, 1 },
11990 	{ NULL }
11991 };
11992 
11993 static void
11994 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
11995 {
11996 
11997 	field_desc_show(sb, *p, tp_la0);
11998 }
11999 
12000 static void
12001 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
12002 {
12003 
12004 	if (idx)
12005 		sbuf_printf(sb, "\n");
12006 	field_desc_show(sb, p[0], tp_la0);
12007 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
12008 		field_desc_show(sb, p[1], tp_la0);
12009 }
12010 
12011 static void
12012 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
12013 {
12014 
12015 	if (idx)
12016 		sbuf_printf(sb, "\n");
12017 	field_desc_show(sb, p[0], tp_la0);
12018 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
12019 		field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
12020 }
12021 
12022 static int
12023 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
12024 {
12025 	struct adapter *sc = arg1;
12026 	struct sbuf *sb;
12027 	uint64_t *buf, *p;
12028 	int rc;
12029 	u_int i, inc;
12030 	void (*show_func)(struct sbuf *, uint64_t *, int);
12031 
12032 	rc = 0;
12033 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12034 	if (sb == NULL)
12035 		return (ENOMEM);
12036 
12037 	buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
12038 
12039 	mtx_lock(&sc->reg_lock);
12040 	if (hw_off_limits(sc))
12041 		rc = ENXIO;
12042 	else {
12043 		t4_tp_read_la(sc, buf, NULL);
12044 		switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
12045 		case 2:
12046 			inc = 2;
12047 			show_func = tp_la_show2;
12048 			break;
12049 		case 3:
12050 			inc = 2;
12051 			show_func = tp_la_show3;
12052 			break;
12053 		default:
12054 			inc = 1;
12055 			show_func = tp_la_show;
12056 		}
12057 	}
12058 	mtx_unlock(&sc->reg_lock);
12059 	if (rc != 0)
12060 		goto done;
12061 
12062 	p = buf;
12063 	for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
12064 		(*show_func)(sb, p, i);
12065 	rc = sbuf_finish(sb);
12066 done:
12067 	sbuf_delete(sb);
12068 	free(buf, M_CXGBE);
12069 	return (rc);
12070 }
12071 
12072 static int
12073 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
12074 {
12075 	struct adapter *sc = arg1;
12076 	struct sbuf *sb;
12077 	int rc;
12078 	u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
12079 
12080 	rc = 0;
12081 	mtx_lock(&sc->reg_lock);
12082 	if (hw_off_limits(sc))
12083 		rc = ENXIO;
12084 	else
12085 		t4_get_chan_txrate(sc, nrate, orate);
12086 	mtx_unlock(&sc->reg_lock);
12087 	if (rc != 0)
12088 		return (rc);
12089 
12090 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
12091 	if (sb == NULL)
12092 		return (ENOMEM);
12093 
12094 	if (sc->chip_params->nchan > 2) {
12095 		sbuf_printf(sb, "              channel 0   channel 1"
12096 		    "   channel 2   channel 3\n");
12097 		sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
12098 		    nrate[0], nrate[1], nrate[2], nrate[3]);
12099 		sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
12100 		    orate[0], orate[1], orate[2], orate[3]);
12101 	} else {
12102 		sbuf_printf(sb, "              channel 0   channel 1\n");
12103 		sbuf_printf(sb, "NIC B/s:     %10ju  %10ju\n",
12104 		    nrate[0], nrate[1]);
12105 		sbuf_printf(sb, "Offload B/s: %10ju  %10ju",
12106 		    orate[0], orate[1]);
12107 	}
12108 
12109 	rc = sbuf_finish(sb);
12110 	sbuf_delete(sb);
12111 
12112 	return (rc);
12113 }
12114 
12115 static int
12116 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
12117 {
12118 	struct adapter *sc = arg1;
12119 	struct sbuf *sb;
12120 	uint32_t *buf, *p;
12121 	int rc, i;
12122 
12123 	rc = 0;
12124 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12125 	if (sb == NULL)
12126 		return (ENOMEM);
12127 
12128 	buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
12129 	    M_ZERO | M_WAITOK);
12130 
12131 	mtx_lock(&sc->reg_lock);
12132 	if (hw_off_limits(sc))
12133 		rc = ENXIO;
12134 	else
12135 		t4_ulprx_read_la(sc, buf);
12136 	mtx_unlock(&sc->reg_lock);
12137 	if (rc != 0)
12138 		goto done;
12139 
12140 	p = buf;
12141 	sbuf_printf(sb, "      Pcmd        Type   Message"
12142 	    "                Data");
12143 	for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
12144 		sbuf_printf(sb, "\n%08x%08x  %4x  %08x  %08x%08x%08x%08x",
12145 		    p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
12146 	}
12147 	rc = sbuf_finish(sb);
12148 done:
12149 	sbuf_delete(sb);
12150 	free(buf, M_CXGBE);
12151 	return (rc);
12152 }
12153 
12154 static int
12155 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
12156 {
12157 	struct adapter *sc = arg1;
12158 	struct sbuf *sb;
12159 	int rc;
12160 	uint32_t cfg, s1, s2;
12161 
12162 	MPASS(chip_id(sc) >= CHELSIO_T5);
12163 
12164 	rc = 0;
12165 	mtx_lock(&sc->reg_lock);
12166 	if (hw_off_limits(sc))
12167 		rc = ENXIO;
12168 	else {
12169 		cfg = t4_read_reg(sc, A_SGE_STAT_CFG);
12170 		s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL);
12171 		s2 = t4_read_reg(sc, A_SGE_STAT_MATCH);
12172 	}
12173 	mtx_unlock(&sc->reg_lock);
12174 	if (rc != 0)
12175 		return (rc);
12176 
12177 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12178 	if (sb == NULL)
12179 		return (ENOMEM);
12180 
12181 	if (G_STATSOURCE_T5(cfg) == 7) {
12182 		int mode;
12183 
12184 		mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg);
12185 		if (mode == 0)
12186 			sbuf_printf(sb, "total %d, incomplete %d", s1, s2);
12187 		else if (mode == 1)
12188 			sbuf_printf(sb, "total %d, data overflow %d", s1, s2);
12189 		else
12190 			sbuf_printf(sb, "unknown mode %d", mode);
12191 	}
12192 	rc = sbuf_finish(sb);
12193 	sbuf_delete(sb);
12194 
12195 	return (rc);
12196 }
12197 
12198 static int
12199 sysctl_cpus(SYSCTL_HANDLER_ARGS)
12200 {
12201 	struct adapter *sc = arg1;
12202 	enum cpu_sets op = arg2;
12203 	cpuset_t cpuset;
12204 	struct sbuf *sb;
12205 	int i, rc;
12206 
12207 	MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
12208 
12209 	CPU_ZERO(&cpuset);
12210 	rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
12211 	if (rc != 0)
12212 		return (rc);
12213 
12214 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12215 	if (sb == NULL)
12216 		return (ENOMEM);
12217 
12218 	CPU_FOREACH(i)
12219 		sbuf_printf(sb, "%d ", i);
12220 	rc = sbuf_finish(sb);
12221 	sbuf_delete(sb);
12222 
12223 	return (rc);
12224 }
12225 
12226 static int
12227 sysctl_reset(SYSCTL_HANDLER_ARGS)
12228 {
12229 	struct adapter *sc = arg1;
12230 	u_int val;
12231 	int rc;
12232 
12233 	val = atomic_load_int(&sc->num_resets);
12234 	rc = sysctl_handle_int(oidp, &val, 0, req);
12235 	if (rc != 0 || req->newptr == NULL)
12236 		return (rc);
12237 
12238 	if (val == 0) {
12239 		/* Zero out the counter that tracks reset. */
12240 		atomic_store_int(&sc->num_resets, 0);
12241 		return (0);
12242 	}
12243 
12244 	if (val != 1)
12245 		return (EINVAL);	/* 0 or 1 are the only legal values */
12246 
12247 	if (hw_off_limits(sc))		/* harmless race */
12248 		return (EALREADY);
12249 
12250 	taskqueue_enqueue(reset_tq, &sc->reset_task);
12251 	return (0);
12252 }
12253 
12254 static int
12255 sysctl_tcb_cache(SYSCTL_HANDLER_ARGS)
12256 {
12257 	struct adapter *sc = arg1;
12258 	u_int val, v;
12259 	int rc;
12260 
12261 	mtx_lock(&sc->reg_lock);
12262 	if (hw_off_limits(sc)) {
12263 		rc = ENXIO;
12264 		goto done;
12265 	}
12266 	t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
12267 	mtx_unlock(&sc->reg_lock);
12268 
12269 	val = v & F_GLFL ? 0 : 1;
12270 	rc = sysctl_handle_int(oidp, &val, 0, req);
12271 	if (rc != 0 || req->newptr == NULL)
12272 		return (rc);
12273 	if (val == 0)
12274 		v |= F_GLFL;
12275 	else
12276 		v &= ~F_GLFL;
12277 
12278 	mtx_lock(&sc->reg_lock);
12279 	if (hw_off_limits(sc))
12280 		rc = ENXIO;
12281 	else
12282 		t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
12283 done:
12284 	mtx_unlock(&sc->reg_lock);
12285 	return (rc);
12286 }
12287 
12288 #ifdef TCP_OFFLOAD
12289 static int
12290 sysctl_tls(SYSCTL_HANDLER_ARGS)
12291 {
12292 	struct adapter *sc = arg1;
12293 	int i, j, v, rc;
12294 	struct vi_info *vi;
12295 
12296 	v = sc->tt.tls;
12297 	rc = sysctl_handle_int(oidp, &v, 0, req);
12298 	if (rc != 0 || req->newptr == NULL)
12299 		return (rc);
12300 
12301 	if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS))
12302 		return (ENOTSUP);
12303 
12304 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls");
12305 	if (rc)
12306 		return (rc);
12307 	if (hw_off_limits(sc))
12308 		rc = ENXIO;
12309 	else {
12310 		sc->tt.tls = !!v;
12311 		for_each_port(sc, i) {
12312 			for_each_vi(sc->port[i], j, vi) {
12313 				if (vi->flags & VI_INIT_DONE)
12314 					t4_update_fl_bufsize(vi->ifp);
12315 			}
12316 		}
12317 	}
12318 	end_synchronized_op(sc, 0);
12319 
12320 	return (rc);
12321 
12322 }
12323 
12324 static void
12325 unit_conv(char *buf, size_t len, u_int val, u_int factor)
12326 {
12327 	u_int rem = val % factor;
12328 
12329 	if (rem == 0)
12330 		snprintf(buf, len, "%u", val / factor);
12331 	else {
12332 		while (rem % 10 == 0)
12333 			rem /= 10;
12334 		snprintf(buf, len, "%u.%u", val / factor, rem);
12335 	}
12336 }
12337 
12338 static int
12339 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
12340 {
12341 	struct adapter *sc = arg1;
12342 	char buf[16];
12343 	u_int res, re;
12344 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12345 
12346 	mtx_lock(&sc->reg_lock);
12347 	if (hw_off_limits(sc))
12348 		res = (u_int)-1;
12349 	else
12350 		res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
12351 	mtx_unlock(&sc->reg_lock);
12352 	if (res == (u_int)-1)
12353 		return (ENXIO);
12354 
12355 	switch (arg2) {
12356 	case 0:
12357 		/* timer_tick */
12358 		re = G_TIMERRESOLUTION(res);
12359 		break;
12360 	case 1:
12361 		/* TCP timestamp tick */
12362 		re = G_TIMESTAMPRESOLUTION(res);
12363 		break;
12364 	case 2:
12365 		/* DACK tick */
12366 		re = G_DELAYEDACKRESOLUTION(res);
12367 		break;
12368 	default:
12369 		return (EDOOFUS);
12370 	}
12371 
12372 	unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
12373 
12374 	return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
12375 }
12376 
12377 static int
12378 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
12379 {
12380 	struct adapter *sc = arg1;
12381 	int rc;
12382 	u_int dack_tmr, dack_re, v;
12383 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12384 
12385 	mtx_lock(&sc->reg_lock);
12386 	if (hw_off_limits(sc))
12387 		rc = ENXIO;
12388 	else {
12389 		rc = 0;
12390 		dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc,
12391 		    A_TP_TIMER_RESOLUTION));
12392 		dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER);
12393 	}
12394 	mtx_unlock(&sc->reg_lock);
12395 	if (rc != 0)
12396 		return (rc);
12397 
12398 	v = ((cclk_ps << dack_re) / 1000000) * dack_tmr;
12399 
12400 	return (sysctl_handle_int(oidp, &v, 0, req));
12401 }
12402 
12403 static int
12404 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
12405 {
12406 	struct adapter *sc = arg1;
12407 	int rc, reg = arg2;
12408 	u_int tre;
12409 	u_long tp_tick_us, v;
12410 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12411 
12412 	MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
12413 	    reg == A_TP_PERS_MIN  || reg == A_TP_PERS_MAX ||
12414 	    reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
12415 	    reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
12416 
12417 	mtx_lock(&sc->reg_lock);
12418 	if (hw_off_limits(sc))
12419 		rc = ENXIO;
12420 	else {
12421 		rc = 0;
12422 		tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
12423 		tp_tick_us = (cclk_ps << tre) / 1000000;
12424 		if (reg == A_TP_INIT_SRTT)
12425 			v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
12426 		else
12427 			v = tp_tick_us * t4_read_reg(sc, reg);
12428 	}
12429 	mtx_unlock(&sc->reg_lock);
12430 	if (rc != 0)
12431 		return (rc);
12432 	else
12433 		return (sysctl_handle_long(oidp, &v, 0, req));
12434 }
12435 
12436 /*
12437  * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
12438  * passed to this function.
12439  */
12440 static int
12441 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
12442 {
12443 	struct adapter *sc = arg1;
12444 	int rc, idx = arg2;
12445 	u_int v;
12446 
12447 	MPASS(idx >= 0 && idx <= 24);
12448 
12449 	mtx_lock(&sc->reg_lock);
12450 	if (hw_off_limits(sc))
12451 		rc = ENXIO;
12452 	else {
12453 		rc = 0;
12454 		v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
12455 	}
12456 	mtx_unlock(&sc->reg_lock);
12457 	if (rc != 0)
12458 		return (rc);
12459 	else
12460 		return (sysctl_handle_int(oidp, &v, 0, req));
12461 }
12462 
12463 static int
12464 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
12465 {
12466 	struct adapter *sc = arg1;
12467 	int rc, idx = arg2;
12468 	u_int shift, v, r;
12469 
12470 	MPASS(idx >= 0 && idx < 16);
12471 
12472 	r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
12473 	shift = (idx & 3) << 3;
12474 	mtx_lock(&sc->reg_lock);
12475 	if (hw_off_limits(sc))
12476 		rc = ENXIO;
12477 	else {
12478 		rc = 0;
12479 		v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
12480 	}
12481 	mtx_unlock(&sc->reg_lock);
12482 	if (rc != 0)
12483 		return (rc);
12484 	else
12485 		return (sysctl_handle_int(oidp, &v, 0, req));
12486 }
12487 
12488 static int
12489 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
12490 {
12491 	struct vi_info *vi = arg1;
12492 	struct adapter *sc = vi->adapter;
12493 	int idx, rc, i;
12494 	struct sge_ofld_rxq *ofld_rxq;
12495 	uint8_t v;
12496 
12497 	idx = vi->ofld_tmr_idx;
12498 
12499 	rc = sysctl_handle_int(oidp, &idx, 0, req);
12500 	if (rc != 0 || req->newptr == NULL)
12501 		return (rc);
12502 
12503 	if (idx < 0 || idx >= SGE_NTIMERS)
12504 		return (EINVAL);
12505 
12506 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
12507 	    "t4otmr");
12508 	if (rc)
12509 		return (rc);
12510 
12511 	v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
12512 	for_each_ofld_rxq(vi, i, ofld_rxq) {
12513 #ifdef atomic_store_rel_8
12514 		atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
12515 #else
12516 		ofld_rxq->iq.intr_params = v;
12517 #endif
12518 	}
12519 	vi->ofld_tmr_idx = idx;
12520 
12521 	end_synchronized_op(sc, LOCK_HELD);
12522 	return (0);
12523 }
12524 
12525 static int
12526 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
12527 {
12528 	struct vi_info *vi = arg1;
12529 	struct adapter *sc = vi->adapter;
12530 	int idx, rc;
12531 
12532 	idx = vi->ofld_pktc_idx;
12533 
12534 	rc = sysctl_handle_int(oidp, &idx, 0, req);
12535 	if (rc != 0 || req->newptr == NULL)
12536 		return (rc);
12537 
12538 	if (idx < -1 || idx >= SGE_NCOUNTERS)
12539 		return (EINVAL);
12540 
12541 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
12542 	    "t4opktc");
12543 	if (rc)
12544 		return (rc);
12545 
12546 	if (vi->flags & VI_INIT_DONE)
12547 		rc = EBUSY; /* cannot be changed once the queues are created */
12548 	else
12549 		vi->ofld_pktc_idx = idx;
12550 
12551 	end_synchronized_op(sc, LOCK_HELD);
12552 	return (rc);
12553 }
12554 #endif
12555 
12556 static int
12557 get_sge_context(struct adapter *sc, int mem_id, uint32_t cid, int len,
12558     uint32_t *data)
12559 {
12560 	int rc;
12561 
12562 	if (len < sc->chip_params->sge_ctxt_size)
12563 		return (ENOBUFS);
12564 	if (cid > M_CTXTQID)
12565 		return (EINVAL);
12566 	if (mem_id != CTXT_EGRESS && mem_id != CTXT_INGRESS &&
12567 	    mem_id != CTXT_FLM && mem_id != CTXT_CNM)
12568 		return (EINVAL);
12569 
12570 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
12571 	if (rc)
12572 		return (rc);
12573 
12574 	if (hw_off_limits(sc)) {
12575 		rc = ENXIO;
12576 		goto done;
12577 	}
12578 
12579 	if (sc->flags & FW_OK && !is_t7(sc)) {
12580 		rc = -t4_sge_ctxt_rd(sc, sc->mbox, cid, mem_id, data);
12581 		if (rc == 0)
12582 			goto done;
12583 	}
12584 
12585 	/*
12586 	 * Read via firmware failed or wasn't even attempted.  Read directly via
12587 	 * the backdoor.
12588 	 */
12589 	rc = -t4_sge_ctxt_rd_bd(sc, cid, mem_id, data);
12590 done:
12591 	end_synchronized_op(sc, 0);
12592 	return (rc);
12593 }
12594 
12595 static int
12596 load_fw(struct adapter *sc, struct t4_data *fw)
12597 {
12598 	int rc;
12599 	uint8_t *fw_data;
12600 
12601 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
12602 	if (rc)
12603 		return (rc);
12604 
12605 	if (hw_off_limits(sc)) {
12606 		rc = ENXIO;
12607 		goto done;
12608 	}
12609 
12610 	/*
12611 	 * The firmware, with the sole exception of the memory parity error
12612 	 * handler, runs from memory and not flash.  It is almost always safe to
12613 	 * install a new firmware on a running system.  Just set bit 1 in
12614 	 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
12615 	 */
12616 	if (sc->flags & FULL_INIT_DONE &&
12617 	    (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
12618 		rc = EBUSY;
12619 		goto done;
12620 	}
12621 
12622 	fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
12623 
12624 	rc = copyin(fw->data, fw_data, fw->len);
12625 	if (rc == 0)
12626 		rc = -t4_load_fw(sc, fw_data, fw->len);
12627 
12628 	free(fw_data, M_CXGBE);
12629 done:
12630 	end_synchronized_op(sc, 0);
12631 	return (rc);
12632 }
12633 
12634 static int
12635 load_cfg(struct adapter *sc, struct t4_data *cfg)
12636 {
12637 	int rc;
12638 	uint8_t *cfg_data = NULL;
12639 
12640 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
12641 	if (rc)
12642 		return (rc);
12643 
12644 	if (hw_off_limits(sc)) {
12645 		rc = ENXIO;
12646 		goto done;
12647 	}
12648 
12649 	if (cfg->len == 0) {
12650 		/* clear */
12651 		rc = -t4_load_cfg(sc, NULL, 0);
12652 		goto done;
12653 	}
12654 
12655 	cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
12656 
12657 	rc = copyin(cfg->data, cfg_data, cfg->len);
12658 	if (rc == 0)
12659 		rc = -t4_load_cfg(sc, cfg_data, cfg->len);
12660 
12661 	free(cfg_data, M_CXGBE);
12662 done:
12663 	end_synchronized_op(sc, 0);
12664 	return (rc);
12665 }
12666 
12667 static int
12668 load_boot(struct adapter *sc, struct t4_bootrom *br)
12669 {
12670 	int rc;
12671 	uint8_t *br_data = NULL;
12672 	u_int offset;
12673 
12674 	if (br->len > 1024 * 1024)
12675 		return (EFBIG);
12676 
12677 	if (br->pf_offset == 0) {
12678 		/* pfidx */
12679 		if (br->pfidx_addr > 7)
12680 			return (EINVAL);
12681 		offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
12682 		    A_PCIE_PF_EXPROM_OFST)));
12683 	} else if (br->pf_offset == 1) {
12684 		/* offset */
12685 		offset = G_OFFSET(br->pfidx_addr);
12686 	} else {
12687 		return (EINVAL);
12688 	}
12689 
12690 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
12691 	if (rc)
12692 		return (rc);
12693 
12694 	if (hw_off_limits(sc)) {
12695 		rc = ENXIO;
12696 		goto done;
12697 	}
12698 
12699 	if (br->len == 0) {
12700 		/* clear */
12701 		rc = -t4_load_boot(sc, NULL, offset, 0);
12702 		goto done;
12703 	}
12704 
12705 	br_data = malloc(br->len, M_CXGBE, M_WAITOK);
12706 
12707 	rc = copyin(br->data, br_data, br->len);
12708 	if (rc == 0)
12709 		rc = -t4_load_boot(sc, br_data, offset, br->len);
12710 
12711 	free(br_data, M_CXGBE);
12712 done:
12713 	end_synchronized_op(sc, 0);
12714 	return (rc);
12715 }
12716 
12717 static int
12718 load_bootcfg(struct adapter *sc, struct t4_data *bc)
12719 {
12720 	int rc;
12721 	uint8_t *bc_data = NULL;
12722 
12723 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
12724 	if (rc)
12725 		return (rc);
12726 
12727 	if (hw_off_limits(sc)) {
12728 		rc = ENXIO;
12729 		goto done;
12730 	}
12731 
12732 	if (bc->len == 0) {
12733 		/* clear */
12734 		rc = -t4_load_bootcfg(sc, NULL, 0);
12735 		goto done;
12736 	}
12737 
12738 	bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
12739 
12740 	rc = copyin(bc->data, bc_data, bc->len);
12741 	if (rc == 0)
12742 		rc = -t4_load_bootcfg(sc, bc_data, bc->len);
12743 
12744 	free(bc_data, M_CXGBE);
12745 done:
12746 	end_synchronized_op(sc, 0);
12747 	return (rc);
12748 }
12749 
12750 static int
12751 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
12752 {
12753 	int rc;
12754 	struct cudbg_init *cudbg;
12755 	void *handle, *buf;
12756 
12757 	/* buf is large, don't block if no memory is available */
12758 	buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
12759 	if (buf == NULL)
12760 		return (ENOMEM);
12761 
12762 	handle = cudbg_alloc_handle();
12763 	if (handle == NULL) {
12764 		rc = ENOMEM;
12765 		goto done;
12766 	}
12767 
12768 	cudbg = cudbg_get_init(handle);
12769 	cudbg->adap = sc;
12770 	cudbg->print = (cudbg_print_cb)printf;
12771 
12772 #ifndef notyet
12773 	device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
12774 	    __func__, dump->wr_flash, dump->len, dump->data);
12775 #endif
12776 
12777 	if (dump->wr_flash)
12778 		cudbg->use_flash = 1;
12779 	MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
12780 	memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
12781 
12782 	rc = cudbg_collect(handle, buf, &dump->len);
12783 	if (rc != 0)
12784 		goto done;
12785 
12786 	rc = copyout(buf, dump->data, dump->len);
12787 done:
12788 	cudbg_free_handle(handle);
12789 	free(buf, M_CXGBE);
12790 	return (rc);
12791 }
12792 
12793 static void
12794 free_offload_policy(struct t4_offload_policy *op)
12795 {
12796 	struct offload_rule *r;
12797 	int i;
12798 
12799 	if (op == NULL)
12800 		return;
12801 
12802 	r = &op->rule[0];
12803 	for (i = 0; i < op->nrules; i++, r++) {
12804 		free(r->bpf_prog.bf_insns, M_CXGBE);
12805 	}
12806 	free(op->rule, M_CXGBE);
12807 	free(op, M_CXGBE);
12808 }
12809 
12810 static int
12811 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
12812 {
12813 	int i, rc, len;
12814 	struct t4_offload_policy *op, *old;
12815 	struct bpf_program *bf;
12816 	const struct offload_settings *s;
12817 	struct offload_rule *r;
12818 	void *u;
12819 
12820 	if (!is_offload(sc))
12821 		return (ENODEV);
12822 
12823 	if (uop->nrules == 0) {
12824 		/* Delete installed policies. */
12825 		op = NULL;
12826 		goto set_policy;
12827 	} else if (uop->nrules > 256) { /* arbitrary */
12828 		return (E2BIG);
12829 	}
12830 
12831 	/* Copy userspace offload policy to kernel */
12832 	op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
12833 	op->nrules = uop->nrules;
12834 	len = op->nrules * sizeof(struct offload_rule);
12835 	op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
12836 	rc = copyin(uop->rule, op->rule, len);
12837 	if (rc) {
12838 		free(op->rule, M_CXGBE);
12839 		free(op, M_CXGBE);
12840 		return (rc);
12841 	}
12842 
12843 	r = &op->rule[0];
12844 	for (i = 0; i < op->nrules; i++, r++) {
12845 
12846 		/* Validate open_type */
12847 		if (r->open_type != OPEN_TYPE_LISTEN &&
12848 		    r->open_type != OPEN_TYPE_ACTIVE &&
12849 		    r->open_type != OPEN_TYPE_PASSIVE &&
12850 		    r->open_type != OPEN_TYPE_DONTCARE) {
12851 error:
12852 			/*
12853 			 * Rules 0 to i have malloc'd filters that need to be
12854 			 * freed.  Rules i+1 to nrules have userspace pointers
12855 			 * and should be left alone.
12856 			 */
12857 			op->nrules = i;
12858 			free_offload_policy(op);
12859 			return (rc);
12860 		}
12861 
12862 		/* Validate settings */
12863 		s = &r->settings;
12864 		if ((s->offload != 0 && s->offload != 1) ||
12865 		    s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
12866 		    s->sched_class < -1 ||
12867 		    s->sched_class >= sc->params.nsched_cls) {
12868 			rc = EINVAL;
12869 			goto error;
12870 		}
12871 
12872 		bf = &r->bpf_prog;
12873 		u = bf->bf_insns;	/* userspace ptr */
12874 		bf->bf_insns = NULL;
12875 		if (bf->bf_len == 0) {
12876 			/* legal, matches everything */
12877 			continue;
12878 		}
12879 		len = bf->bf_len * sizeof(*bf->bf_insns);
12880 		bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
12881 		rc = copyin(u, bf->bf_insns, len);
12882 		if (rc != 0)
12883 			goto error;
12884 
12885 		if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
12886 			rc = EINVAL;
12887 			goto error;
12888 		}
12889 	}
12890 set_policy:
12891 	rw_wlock(&sc->policy_lock);
12892 	old = sc->policy;
12893 	sc->policy = op;
12894 	rw_wunlock(&sc->policy_lock);
12895 	free_offload_policy(old);
12896 
12897 	return (0);
12898 }
12899 
12900 #define MAX_READ_BUF_SIZE (128 * 1024)
12901 static int
12902 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
12903 {
12904 	uint32_t addr, remaining, n;
12905 	uint32_t *buf;
12906 	int rc;
12907 	uint8_t *dst;
12908 
12909 	mtx_lock(&sc->reg_lock);
12910 	if (hw_off_limits(sc))
12911 		rc = ENXIO;
12912 	else
12913 		rc = validate_mem_range(sc, mr->addr, mr->len);
12914 	mtx_unlock(&sc->reg_lock);
12915 	if (rc != 0)
12916 		return (rc);
12917 
12918 	buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
12919 	addr = mr->addr;
12920 	remaining = mr->len;
12921 	dst = (void *)mr->data;
12922 
12923 	while (remaining) {
12924 		n = min(remaining, MAX_READ_BUF_SIZE);
12925 		mtx_lock(&sc->reg_lock);
12926 		if (hw_off_limits(sc))
12927 			rc = ENXIO;
12928 		else
12929 			read_via_memwin(sc, 2, addr, buf, n);
12930 		mtx_unlock(&sc->reg_lock);
12931 		if (rc != 0)
12932 			break;
12933 
12934 		rc = copyout(buf, dst, n);
12935 		if (rc != 0)
12936 			break;
12937 
12938 		dst += n;
12939 		remaining -= n;
12940 		addr += n;
12941 	}
12942 
12943 	free(buf, M_CXGBE);
12944 	return (rc);
12945 }
12946 #undef MAX_READ_BUF_SIZE
12947 
12948 static int
12949 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
12950 {
12951 	int rc;
12952 
12953 	if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
12954 		return (EINVAL);
12955 
12956 	if (i2cd->len > sizeof(i2cd->data))
12957 		return (EFBIG);
12958 
12959 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
12960 	if (rc)
12961 		return (rc);
12962 	if (hw_off_limits(sc))
12963 		rc = ENXIO;
12964 	else
12965 		rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
12966 		    i2cd->offset, i2cd->len, &i2cd->data[0]);
12967 	end_synchronized_op(sc, 0);
12968 
12969 	return (rc);
12970 }
12971 
12972 static int
12973 clear_stats(struct adapter *sc, u_int port_id)
12974 {
12975 	int i, v, chan_map;
12976 	struct port_info *pi;
12977 	struct vi_info *vi;
12978 	struct sge_rxq *rxq;
12979 	struct sge_txq *txq;
12980 	struct sge_wrq *wrq;
12981 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12982 	struct sge_ofld_txq *ofld_txq;
12983 #endif
12984 #ifdef TCP_OFFLOAD
12985 	struct sge_ofld_rxq *ofld_rxq;
12986 #endif
12987 
12988 	if (port_id >= sc->params.nports)
12989 		return (EINVAL);
12990 	pi = sc->port[port_id];
12991 	if (pi == NULL)
12992 		return (EIO);
12993 
12994 	mtx_lock(&sc->reg_lock);
12995 	if (!hw_off_limits(sc)) {
12996 		/* MAC stats */
12997 		t4_clr_port_stats(sc, pi->hw_port);
12998 		if (is_t6(sc)) {
12999 			if (pi->fcs_reg != -1)
13000 				pi->fcs_base = t4_read_reg64(sc,
13001 				    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
13002 			else
13003 				pi->stats.rx_fcs_err = 0;
13004 		}
13005 		for_each_vi(pi, v, vi) {
13006 			if (vi->flags & VI_INIT_DONE)
13007 				t4_clr_vi_stats(sc, vi->vin);
13008 		}
13009 		chan_map = pi->rx_e_chan_map;
13010 		v = 0;	/* reuse */
13011 		while (chan_map) {
13012 			i = ffs(chan_map) - 1;
13013 			t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
13014 			    1, A_TP_MIB_TNL_CNG_DROP_0 + i);
13015 			chan_map &= ~(1 << i);
13016 		}
13017 	}
13018 	mtx_unlock(&sc->reg_lock);
13019 	pi->tx_parse_error = 0;
13020 	pi->tnl_cong_drops = 0;
13021 
13022 	/*
13023 	 * Since this command accepts a port, clear stats for
13024 	 * all VIs on this port.
13025 	 */
13026 	for_each_vi(pi, v, vi) {
13027 		if (vi->flags & VI_INIT_DONE) {
13028 
13029 			for_each_rxq(vi, i, rxq) {
13030 #if defined(INET) || defined(INET6)
13031 				rxq->lro.lro_queued = 0;
13032 				rxq->lro.lro_flushed = 0;
13033 #endif
13034 				rxq->rxcsum = 0;
13035 				rxq->vlan_extraction = 0;
13036 				rxq->vxlan_rxcsum = 0;
13037 
13038 				rxq->fl.cl_allocated = 0;
13039 				rxq->fl.cl_recycled = 0;
13040 				rxq->fl.cl_fast_recycled = 0;
13041 			}
13042 
13043 			for_each_txq(vi, i, txq) {
13044 				txq->txcsum = 0;
13045 				txq->tso_wrs = 0;
13046 				txq->vlan_insertion = 0;
13047 				txq->imm_wrs = 0;
13048 				txq->sgl_wrs = 0;
13049 				txq->txpkt_wrs = 0;
13050 				txq->txpkts0_wrs = 0;
13051 				txq->txpkts1_wrs = 0;
13052 				txq->txpkts0_pkts = 0;
13053 				txq->txpkts1_pkts = 0;
13054 				txq->txpkts_flush = 0;
13055 				txq->raw_wrs = 0;
13056 				txq->vxlan_tso_wrs = 0;
13057 				txq->vxlan_txcsum = 0;
13058 				txq->kern_tls_records = 0;
13059 				txq->kern_tls_short = 0;
13060 				txq->kern_tls_partial = 0;
13061 				txq->kern_tls_full = 0;
13062 				txq->kern_tls_octets = 0;
13063 				txq->kern_tls_waste = 0;
13064 				txq->kern_tls_header = 0;
13065 				txq->kern_tls_fin_short = 0;
13066 				txq->kern_tls_cbc = 0;
13067 				txq->kern_tls_gcm = 0;
13068 				if (is_t6(sc)) {
13069 					txq->kern_tls_options = 0;
13070 					txq->kern_tls_fin = 0;
13071 				} else {
13072 					txq->kern_tls_ghash_received = 0;
13073 					txq->kern_tls_ghash_requested = 0;
13074 					txq->kern_tls_lso = 0;
13075 					txq->kern_tls_partial_ghash = 0;
13076 					txq->kern_tls_splitmode = 0;
13077 					txq->kern_tls_trailer = 0;
13078 				}
13079 				mp_ring_reset_stats(txq->r);
13080 			}
13081 
13082 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
13083 			for_each_ofld_txq(vi, i, ofld_txq) {
13084 				ofld_txq->wrq.tx_wrs_direct = 0;
13085 				ofld_txq->wrq.tx_wrs_copied = 0;
13086 				counter_u64_zero(ofld_txq->tx_iscsi_pdus);
13087 				counter_u64_zero(ofld_txq->tx_iscsi_octets);
13088 				counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs);
13089 				counter_u64_zero(ofld_txq->tx_nvme_pdus);
13090 				counter_u64_zero(ofld_txq->tx_nvme_octets);
13091 				counter_u64_zero(ofld_txq->tx_nvme_iso_wrs);
13092 				counter_u64_zero(ofld_txq->tx_aio_jobs);
13093 				counter_u64_zero(ofld_txq->tx_aio_octets);
13094 				counter_u64_zero(ofld_txq->tx_toe_tls_records);
13095 				counter_u64_zero(ofld_txq->tx_toe_tls_octets);
13096 			}
13097 #endif
13098 #ifdef TCP_OFFLOAD
13099 			for_each_ofld_rxq(vi, i, ofld_rxq) {
13100 				ofld_rxq->fl.cl_allocated = 0;
13101 				ofld_rxq->fl.cl_recycled = 0;
13102 				ofld_rxq->fl.cl_fast_recycled = 0;
13103 				counter_u64_zero(
13104 				    ofld_rxq->rx_iscsi_ddp_setup_ok);
13105 				counter_u64_zero(
13106 				    ofld_rxq->rx_iscsi_ddp_setup_error);
13107 				ofld_rxq->rx_iscsi_ddp_pdus = 0;
13108 				ofld_rxq->rx_iscsi_ddp_octets = 0;
13109 				ofld_rxq->rx_iscsi_fl_pdus = 0;
13110 				ofld_rxq->rx_iscsi_fl_octets = 0;
13111 				counter_u64_zero(
13112 				    ofld_rxq->rx_nvme_ddp_setup_ok);
13113 				counter_u64_zero(
13114 				    ofld_rxq->rx_nvme_ddp_setup_no_stag);
13115 				counter_u64_zero(
13116 				    ofld_rxq->rx_nvme_ddp_setup_error);
13117 				counter_u64_zero(ofld_rxq->rx_nvme_ddp_pdus);
13118 				counter_u64_zero(ofld_rxq->rx_nvme_ddp_octets);
13119 				counter_u64_zero(ofld_rxq->rx_nvme_fl_pdus);
13120 				counter_u64_zero(ofld_rxq->rx_nvme_fl_octets);
13121 				counter_u64_zero(
13122 				    ofld_rxq->rx_nvme_invalid_headers);
13123 				counter_u64_zero(
13124 				    ofld_rxq->rx_nvme_header_digest_errors);
13125 				counter_u64_zero(
13126 				    ofld_rxq->rx_nvme_data_digest_errors);
13127 				ofld_rxq->rx_aio_ddp_jobs = 0;
13128 				ofld_rxq->rx_aio_ddp_octets = 0;
13129 				ofld_rxq->rx_toe_tls_records = 0;
13130 				ofld_rxq->rx_toe_tls_octets = 0;
13131 				ofld_rxq->rx_toe_ddp_octets = 0;
13132 				counter_u64_zero(ofld_rxq->ddp_buffer_alloc);
13133 				counter_u64_zero(ofld_rxq->ddp_buffer_reuse);
13134 				counter_u64_zero(ofld_rxq->ddp_buffer_free);
13135 			}
13136 #endif
13137 
13138 			if (IS_MAIN_VI(vi)) {
13139 				wrq = &sc->sge.ctrlq[pi->port_id];
13140 				wrq->tx_wrs_direct = 0;
13141 				wrq->tx_wrs_copied = 0;
13142 			}
13143 		}
13144 	}
13145 
13146 	return (0);
13147 }
13148 
13149 static int
13150 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
13151 {
13152 #ifdef INET6
13153 	struct in6_addr in6;
13154 
13155 	bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
13156 	if (t4_get_clip_entry(sc, &in6, true) != NULL)
13157 		return (0);
13158 	else
13159 		return (EIO);
13160 #else
13161 	return (ENOTSUP);
13162 #endif
13163 }
13164 
13165 static int
13166 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
13167 {
13168 #ifdef INET6
13169 	struct in6_addr in6;
13170 
13171 	bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
13172 	return (t4_release_clip_addr(sc, &in6));
13173 #else
13174 	return (ENOTSUP);
13175 #endif
13176 }
13177 
13178 int
13179 t4_os_find_pci_capability(struct adapter *sc, int cap)
13180 {
13181 	int i;
13182 
13183 	return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
13184 }
13185 
13186 void
13187 t4_os_portmod_changed(struct port_info *pi)
13188 {
13189 	struct adapter *sc = pi->adapter;
13190 	struct vi_info *vi;
13191 	if_t ifp;
13192 	static const char *mod_str[] = {
13193 		NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM",
13194 		"LR_SIMPLEX", "DR"
13195 	};
13196 
13197 	KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
13198 	    ("%s: port_type %u", __func__, pi->port_type));
13199 
13200 	vi = &pi->vi[0];
13201 	if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
13202 		PORT_LOCK(pi);
13203 		build_medialist(pi);
13204 		if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
13205 			fixup_link_config(pi);
13206 			apply_link_config(pi);
13207 		}
13208 		PORT_UNLOCK(pi);
13209 		end_synchronized_op(sc, LOCK_HELD);
13210 	}
13211 
13212 	ifp = vi->ifp;
13213 	if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
13214 		if_printf(ifp, "transceiver unplugged.\n");
13215 	else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
13216 		if_printf(ifp, "unknown transceiver inserted.\n");
13217 	else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
13218 		if_printf(ifp, "unsupported transceiver inserted.\n");
13219 	else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
13220 		if_printf(ifp, "%dGbps %s transceiver inserted.\n",
13221 		    port_top_speed(pi), mod_str[pi->mod_type]);
13222 	} else {
13223 		if_printf(ifp, "transceiver (type %d) inserted.\n",
13224 		    pi->mod_type);
13225 	}
13226 }
13227 
13228 void
13229 t4_os_link_changed(struct port_info *pi)
13230 {
13231 	struct vi_info *vi;
13232 	if_t ifp;
13233 	struct link_config *lc = &pi->link_cfg;
13234 	struct adapter *sc = pi->adapter;
13235 	int v;
13236 
13237 	PORT_LOCK_ASSERT_OWNED(pi);
13238 
13239 	if (is_t6(sc)) {
13240 		if (lc->link_ok) {
13241 			if (lc->speed > 25000 ||
13242 			    (lc->speed == 25000 && lc->fec == FEC_RS))
13243 				pi->fcs_reg = A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS;
13244 			else
13245 				pi->fcs_reg = A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS;
13246 			pi->fcs_base = t4_read_reg64(sc,
13247 			    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
13248 			pi->stats.rx_fcs_err = 0;
13249 		} else {
13250 			pi->fcs_reg = -1;
13251 		}
13252 	} else {
13253 		MPASS(pi->fcs_reg != -1);
13254 		MPASS(pi->fcs_base == 0);
13255 	}
13256 
13257 	for_each_vi(pi, v, vi) {
13258 		ifp = vi->ifp;
13259 		if (ifp == NULL || IS_DETACHING(vi))
13260 			continue;
13261 
13262 		if (lc->link_ok) {
13263 			if_setbaudrate(ifp, IF_Mbps(lc->speed));
13264 			if_link_state_change(ifp, LINK_STATE_UP);
13265 		} else {
13266 			if_link_state_change(ifp, LINK_STATE_DOWN);
13267 		}
13268 	}
13269 }
13270 
13271 void
13272 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
13273 {
13274 	struct adapter *sc;
13275 
13276 	sx_slock(&t4_list_lock);
13277 	SLIST_FOREACH(sc, &t4_list, link) {
13278 		/*
13279 		 * func should not make any assumptions about what state sc is
13280 		 * in - the only guarantee is that sc->sc_lock is a valid lock.
13281 		 */
13282 		func(sc, arg);
13283 	}
13284 	sx_sunlock(&t4_list_lock);
13285 }
13286 
13287 static int
13288 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
13289     struct thread *td)
13290 {
13291 	int rc;
13292 	struct adapter *sc = dev->si_drv1;
13293 
13294 	rc = priv_check(td, PRIV_DRIVER);
13295 	if (rc != 0)
13296 		return (rc);
13297 
13298 	switch (cmd) {
13299 	case CHELSIO_T4_GETREG: {
13300 		struct t4_reg *edata = (struct t4_reg *)data;
13301 
13302 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
13303 			return (EFAULT);
13304 
13305 		mtx_lock(&sc->reg_lock);
13306 		if (hw_off_limits(sc))
13307 			rc = ENXIO;
13308 		else if (edata->size == 4)
13309 			edata->val = t4_read_reg(sc, edata->addr);
13310 		else if (edata->size == 8)
13311 			edata->val = t4_read_reg64(sc, edata->addr);
13312 		else
13313 			rc = EINVAL;
13314 		mtx_unlock(&sc->reg_lock);
13315 
13316 		break;
13317 	}
13318 	case CHELSIO_T4_SETREG: {
13319 		struct t4_reg *edata = (struct t4_reg *)data;
13320 
13321 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
13322 			return (EFAULT);
13323 
13324 		mtx_lock(&sc->reg_lock);
13325 		if (hw_off_limits(sc))
13326 			rc = ENXIO;
13327 		else if (edata->size == 4) {
13328 			if (edata->val & 0xffffffff00000000)
13329 				rc = EINVAL;
13330 			t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
13331 		} else if (edata->size == 8)
13332 			t4_write_reg64(sc, edata->addr, edata->val);
13333 		else
13334 			rc = EINVAL;
13335 		mtx_unlock(&sc->reg_lock);
13336 
13337 		break;
13338 	}
13339 	case CHELSIO_T4_REGDUMP: {
13340 		struct t4_regdump *regs = (struct t4_regdump *)data;
13341 		int reglen = t4_get_regs_len(sc);
13342 		uint8_t *buf;
13343 
13344 		if (regs->len < reglen) {
13345 			regs->len = reglen; /* hint to the caller */
13346 			return (ENOBUFS);
13347 		}
13348 
13349 		regs->len = reglen;
13350 		buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
13351 		mtx_lock(&sc->reg_lock);
13352 		if (hw_off_limits(sc))
13353 			rc = ENXIO;
13354 		else
13355 			get_regs(sc, regs, buf);
13356 		mtx_unlock(&sc->reg_lock);
13357 		if (rc == 0)
13358 			rc = copyout(buf, regs->data, reglen);
13359 		free(buf, M_CXGBE);
13360 		break;
13361 	}
13362 	case CHELSIO_T4_GET_FILTER_MODE:
13363 		rc = get_filter_mode(sc, (uint32_t *)data);
13364 		break;
13365 	case CHELSIO_T4_SET_FILTER_MODE:
13366 		rc = set_filter_mode(sc, *(uint32_t *)data);
13367 		break;
13368 	case CHELSIO_T4_SET_FILTER_MASK:
13369 		rc = set_filter_mask(sc, *(uint32_t *)data);
13370 		break;
13371 	case CHELSIO_T4_GET_FILTER:
13372 		rc = get_filter(sc, (struct t4_filter *)data);
13373 		break;
13374 	case CHELSIO_T4_SET_FILTER:
13375 		rc = set_filter(sc, (struct t4_filter *)data);
13376 		break;
13377 	case CHELSIO_T4_DEL_FILTER:
13378 		rc = del_filter(sc, (struct t4_filter *)data);
13379 		break;
13380 	case CHELSIO_T4_GET_SGE_CONTEXT: {
13381 		struct t4_sge_context *ctxt = (struct t4_sge_context *)data;
13382 
13383 		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
13384 		    sizeof(ctxt->data), &ctxt->data[0]);
13385 		break;
13386 	}
13387 	case CHELSIO_T4_LOAD_FW:
13388 		rc = load_fw(sc, (struct t4_data *)data);
13389 		break;
13390 	case CHELSIO_T4_GET_MEM:
13391 		rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
13392 		break;
13393 	case CHELSIO_T4_GET_I2C:
13394 		rc = read_i2c(sc, (struct t4_i2c_data *)data);
13395 		break;
13396 	case CHELSIO_T4_CLEAR_STATS:
13397 		rc = clear_stats(sc, *(uint32_t *)data);
13398 		break;
13399 	case CHELSIO_T4_SCHED_CLASS:
13400 		rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
13401 		break;
13402 	case CHELSIO_T4_SCHED_QUEUE:
13403 		rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
13404 		break;
13405 	case CHELSIO_T4_GET_TRACER:
13406 		rc = t4_get_tracer(sc, (struct t4_tracer *)data);
13407 		break;
13408 	case CHELSIO_T4_SET_TRACER:
13409 		rc = t4_set_tracer(sc, (struct t4_tracer *)data);
13410 		break;
13411 	case CHELSIO_T4_LOAD_CFG:
13412 		rc = load_cfg(sc, (struct t4_data *)data);
13413 		break;
13414 	case CHELSIO_T4_LOAD_BOOT:
13415 		rc = load_boot(sc, (struct t4_bootrom *)data);
13416 		break;
13417 	case CHELSIO_T4_LOAD_BOOTCFG:
13418 		rc = load_bootcfg(sc, (struct t4_data *)data);
13419 		break;
13420 	case CHELSIO_T4_CUDBG_DUMP:
13421 		rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
13422 		break;
13423 	case CHELSIO_T4_SET_OFLD_POLICY:
13424 		rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
13425 		break;
13426 	case CHELSIO_T4_HOLD_CLIP_ADDR:
13427 		rc = hold_clip_addr(sc, (struct t4_clip_addr *)data);
13428 		break;
13429 	case CHELSIO_T4_RELEASE_CLIP_ADDR:
13430 		rc = release_clip_addr(sc, (struct t4_clip_addr *)data);
13431 		break;
13432 	case CHELSIO_T4_GET_SGE_CTXT: {
13433 		struct t4_sge_ctxt *ctxt = (struct t4_sge_ctxt *)data;
13434 
13435 		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
13436 		    sizeof(ctxt->data), &ctxt->data[0]);
13437 		break;
13438 	}
13439 	default:
13440 		rc = ENOTTY;
13441 	}
13442 
13443 	return (rc);
13444 }
13445 
13446 #ifdef TCP_OFFLOAD
13447 int
13448 toe_capability(struct vi_info *vi, bool enable)
13449 {
13450 	int rc;
13451 	struct port_info *pi = vi->pi;
13452 	struct adapter *sc = pi->adapter;
13453 
13454 	ASSERT_SYNCHRONIZED_OP(sc);
13455 
13456 	if (!is_offload(sc))
13457 		return (ENODEV);
13458 	if (!hw_all_ok(sc))
13459 		return (ENXIO);
13460 
13461 	if (enable) {
13462 #ifdef KERN_TLS
13463 		if (sc->flags & KERN_TLS_ON && is_t6(sc)) {
13464 			int i, j, n;
13465 			struct port_info *p;
13466 			struct vi_info *v;
13467 
13468 			/*
13469 			 * Reconfigure hardware for TOE if TXTLS is not enabled
13470 			 * on any ifnet.
13471 			 */
13472 			n = 0;
13473 			for_each_port(sc, i) {
13474 				p = sc->port[i];
13475 				for_each_vi(p, j, v) {
13476 					if (if_getcapenable(v->ifp) & IFCAP_TXTLS) {
13477 						CH_WARN(sc,
13478 						    "%s has NIC TLS enabled.\n",
13479 						    device_get_nameunit(v->dev));
13480 						n++;
13481 					}
13482 				}
13483 			}
13484 			if (n > 0) {
13485 				CH_WARN(sc, "Disable NIC TLS on all interfaces "
13486 				    "associated with this adapter before "
13487 				    "trying to enable TOE.\n");
13488 				return (EAGAIN);
13489 			}
13490 			rc = t6_config_kern_tls(sc, false);
13491 			if (rc)
13492 				return (rc);
13493 		}
13494 #endif
13495 		if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) {
13496 			/* TOE is already enabled. */
13497 			return (0);
13498 		}
13499 
13500 		/*
13501 		 * We need the port's queues around so that we're able to send
13502 		 * and receive CPLs to/from the TOE even if the ifnet for this
13503 		 * port has never been UP'd administratively.
13504 		 */
13505 		if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
13506 			return (rc);
13507 		if (!(pi->vi[0].flags & VI_INIT_DONE) &&
13508 		    ((rc = vi_init(&pi->vi[0])) != 0))
13509 			return (rc);
13510 
13511 		if (isset(&sc->offload_map, pi->port_id)) {
13512 			/* TOE is enabled on another VI of this port. */
13513 			MPASS(pi->uld_vis > 0);
13514 			pi->uld_vis++;
13515 			return (0);
13516 		}
13517 
13518 		if (!uld_active(sc, ULD_TOM)) {
13519 			rc = t4_activate_uld(sc, ULD_TOM);
13520 			if (rc == EAGAIN) {
13521 				log(LOG_WARNING,
13522 				    "You must kldload t4_tom.ko before trying "
13523 				    "to enable TOE on a cxgbe interface.\n");
13524 			}
13525 			if (rc != 0)
13526 				return (rc);
13527 			KASSERT(sc->tom_softc != NULL,
13528 			    ("%s: TOM activated but softc NULL", __func__));
13529 			KASSERT(uld_active(sc, ULD_TOM),
13530 			    ("%s: TOM activated but flag not set", __func__));
13531 		}
13532 
13533 		/*
13534 		 * Activate iWARP, iSCSI, and NVMe too, if the modules
13535 		 * are loaded.
13536 		 */
13537 		if (!uld_active(sc, ULD_IWARP))
13538 			(void) t4_activate_uld(sc, ULD_IWARP);
13539 		if (!uld_active(sc, ULD_ISCSI))
13540 			(void) t4_activate_uld(sc, ULD_ISCSI);
13541 		if (!uld_active(sc, ULD_NVME))
13542 			(void) t4_activate_uld(sc, ULD_NVME);
13543 
13544 		if (pi->uld_vis++ == 0)
13545 			setbit(&sc->offload_map, pi->port_id);
13546 	} else {
13547 		if ((if_getcapenable(vi->ifp) & IFCAP_TOE) == 0) {
13548 			/* TOE is already disabled. */
13549 			return (0);
13550 		}
13551 		MPASS(isset(&sc->offload_map, pi->port_id));
13552 		MPASS(pi->uld_vis > 0);
13553 		if (--pi->uld_vis == 0)
13554 			clrbit(&sc->offload_map, pi->port_id);
13555 	}
13556 
13557 	return (0);
13558 }
13559 
13560 /*
13561  * Add an upper layer driver to the global list.
13562  */
13563 int
13564 t4_register_uld(struct uld_info *ui, int id)
13565 {
13566 	int rc;
13567 
13568 	if (id < 0 || id > ULD_MAX)
13569 		return (EINVAL);
13570 	sx_xlock(&t4_uld_list_lock);
13571 	if (t4_uld_list[id] != NULL)
13572 		rc = EEXIST;
13573 	else {
13574 		t4_uld_list[id] = ui;
13575 		rc = 0;
13576 	}
13577 	sx_xunlock(&t4_uld_list_lock);
13578 	return (rc);
13579 }
13580 
13581 int
13582 t4_unregister_uld(struct uld_info *ui, int id)
13583 {
13584 
13585 	if (id < 0 || id > ULD_MAX)
13586 		return (EINVAL);
13587 	sx_xlock(&t4_uld_list_lock);
13588 	MPASS(t4_uld_list[id] == ui);
13589 	t4_uld_list[id] = NULL;
13590 	sx_xunlock(&t4_uld_list_lock);
13591 	return (0);
13592 }
13593 
13594 int
13595 t4_activate_uld(struct adapter *sc, int id)
13596 {
13597 	int rc;
13598 
13599 	ASSERT_SYNCHRONIZED_OP(sc);
13600 
13601 	if (id < 0 || id > ULD_MAX)
13602 		return (EINVAL);
13603 
13604 	/* Adapter needs to be initialized before any ULD can be activated. */
13605 	if (!(sc->flags & FULL_INIT_DONE)) {
13606 		rc = adapter_init(sc);
13607 		if (rc != 0)
13608 			return (rc);
13609 	}
13610 
13611 	sx_slock(&t4_uld_list_lock);
13612 	if (t4_uld_list[id] == NULL)
13613 		rc = EAGAIN;	/* load the KLD with this ULD and try again. */
13614 	else {
13615 		rc = t4_uld_list[id]->uld_activate(sc);
13616 		if (rc == 0)
13617 			setbit(&sc->active_ulds, id);
13618 	}
13619 	sx_sunlock(&t4_uld_list_lock);
13620 
13621 	return (rc);
13622 }
13623 
13624 int
13625 t4_deactivate_uld(struct adapter *sc, int id)
13626 {
13627 	int rc;
13628 
13629 	ASSERT_SYNCHRONIZED_OP(sc);
13630 
13631 	if (id < 0 || id > ULD_MAX)
13632 		return (EINVAL);
13633 
13634 	sx_slock(&t4_uld_list_lock);
13635 	if (t4_uld_list[id] == NULL)
13636 		rc = ENXIO;
13637 	else {
13638 		rc = t4_uld_list[id]->uld_deactivate(sc);
13639 		if (rc == 0)
13640 			clrbit(&sc->active_ulds, id);
13641 	}
13642 	sx_sunlock(&t4_uld_list_lock);
13643 
13644 	return (rc);
13645 }
13646 
13647 static int
13648 deactivate_all_uld(struct adapter *sc)
13649 {
13650 	int i, rc;
13651 
13652 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld");
13653 	if (rc != 0)
13654 		return (ENXIO);
13655 	sx_slock(&t4_uld_list_lock);
13656 	for (i = 0; i <= ULD_MAX; i++) {
13657 		if (t4_uld_list[i] == NULL || !uld_active(sc, i))
13658 			continue;
13659 		rc = t4_uld_list[i]->uld_deactivate(sc);
13660 		if (rc != 0)
13661 			break;
13662 		clrbit(&sc->active_ulds, i);
13663 	}
13664 	sx_sunlock(&t4_uld_list_lock);
13665 	end_synchronized_op(sc, 0);
13666 
13667 	return (rc);
13668 }
13669 
13670 static void
13671 stop_all_uld(struct adapter *sc)
13672 {
13673 	int i;
13674 
13675 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0)
13676 		return;
13677 	sx_slock(&t4_uld_list_lock);
13678 	for (i = 0; i <= ULD_MAX; i++) {
13679 		if (t4_uld_list[i] == NULL || !uld_active(sc, i) ||
13680 		    t4_uld_list[i]->uld_stop == NULL)
13681 			continue;
13682 		(void) t4_uld_list[i]->uld_stop(sc);
13683 	}
13684 	sx_sunlock(&t4_uld_list_lock);
13685 	end_synchronized_op(sc, 0);
13686 }
13687 
13688 static void
13689 restart_all_uld(struct adapter *sc)
13690 {
13691 	int i;
13692 
13693 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0)
13694 		return;
13695 	sx_slock(&t4_uld_list_lock);
13696 	for (i = 0; i <= ULD_MAX; i++) {
13697 		if (t4_uld_list[i] == NULL || !uld_active(sc, i) ||
13698 		    t4_uld_list[i]->uld_restart == NULL)
13699 			continue;
13700 		(void) t4_uld_list[i]->uld_restart(sc);
13701 	}
13702 	sx_sunlock(&t4_uld_list_lock);
13703 	end_synchronized_op(sc, 0);
13704 }
13705 
13706 int
13707 uld_active(struct adapter *sc, int id)
13708 {
13709 
13710 	MPASS(id >= 0 && id <= ULD_MAX);
13711 
13712 	return (isset(&sc->active_ulds, id));
13713 }
13714 #endif
13715 
13716 #ifdef KERN_TLS
13717 static int
13718 ktls_capability(struct adapter *sc, bool enable)
13719 {
13720 	ASSERT_SYNCHRONIZED_OP(sc);
13721 
13722 	if (!is_ktls(sc))
13723 		return (ENODEV);
13724 	if (!is_t6(sc))
13725 		return (0);
13726 	if (!hw_all_ok(sc))
13727 		return (ENXIO);
13728 
13729 	if (enable) {
13730 		if (sc->flags & KERN_TLS_ON)
13731 			return (0);	/* already on */
13732 		if (sc->offload_map != 0) {
13733 			CH_WARN(sc,
13734 			    "Disable TOE on all interfaces associated with "
13735 			    "this adapter before trying to enable NIC TLS.\n");
13736 			return (EAGAIN);
13737 		}
13738 		return (t6_config_kern_tls(sc, true));
13739 	} else {
13740 		/*
13741 		 * Nothing to do for disable.  If TOE is enabled sometime later
13742 		 * then toe_capability will reconfigure the hardware.
13743 		 */
13744 		return (0);
13745 	}
13746 }
13747 #endif
13748 
13749 /*
13750  * t  = ptr to tunable.
13751  * nc = number of CPUs.
13752  * c  = compiled in default for that tunable.
13753  */
13754 static void
13755 calculate_nqueues(int *t, int nc, const int c)
13756 {
13757 	int nq;
13758 
13759 	if (*t > 0)
13760 		return;
13761 	nq = *t < 0 ? -*t : c;
13762 	*t = min(nc, nq);
13763 }
13764 
13765 /*
13766  * Come up with reasonable defaults for some of the tunables, provided they're
13767  * not set by the user (in which case we'll use the values as is).
13768  */
13769 static void
13770 tweak_tunables(void)
13771 {
13772 	int nc = mp_ncpus;	/* our snapshot of the number of CPUs */
13773 
13774 	if (t4_ntxq < 1) {
13775 #ifdef RSS
13776 		t4_ntxq = rss_getnumbuckets();
13777 #else
13778 		calculate_nqueues(&t4_ntxq, nc, NTXQ);
13779 #endif
13780 	}
13781 
13782 	calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
13783 
13784 	if (t4_nrxq < 1) {
13785 #ifdef RSS
13786 		t4_nrxq = rss_getnumbuckets();
13787 #else
13788 		calculate_nqueues(&t4_nrxq, nc, NRXQ);
13789 #endif
13790 	}
13791 
13792 	calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
13793 
13794 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
13795 	calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
13796 	calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
13797 #endif
13798 #ifdef TCP_OFFLOAD
13799 	calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
13800 	calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
13801 #endif
13802 
13803 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
13804 	if (t4_toecaps_allowed == -1)
13805 		t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
13806 #else
13807 	if (t4_toecaps_allowed == -1)
13808 		t4_toecaps_allowed = 0;
13809 #endif
13810 
13811 #ifdef TCP_OFFLOAD
13812 	if (t4_rdmacaps_allowed == -1) {
13813 		t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
13814 		    FW_CAPS_CONFIG_RDMA_RDMAC;
13815 	}
13816 
13817 	if (t4_iscsicaps_allowed == -1) {
13818 		t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
13819 		    FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
13820 		    FW_CAPS_CONFIG_ISCSI_T10DIF;
13821 	}
13822 
13823 	if (t4_nvmecaps_allowed == -1)
13824 		t4_nvmecaps_allowed = FW_CAPS_CONFIG_NVME_TCP;
13825 
13826 	if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
13827 		t4_tmr_idx_ofld = TMR_IDX_OFLD;
13828 
13829 	if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
13830 		t4_pktc_idx_ofld = PKTC_IDX_OFLD;
13831 #else
13832 	if (t4_rdmacaps_allowed == -1)
13833 		t4_rdmacaps_allowed = 0;
13834 
13835 	if (t4_iscsicaps_allowed == -1)
13836 		t4_iscsicaps_allowed = 0;
13837 
13838 	if (t4_nvmecaps_allowed == -1)
13839 		t4_nvmecaps_allowed = 0;
13840 #endif
13841 
13842 #ifdef DEV_NETMAP
13843 	calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
13844 	calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
13845 	calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
13846 	calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
13847 #endif
13848 
13849 	if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
13850 		t4_tmr_idx = TMR_IDX;
13851 
13852 	if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
13853 		t4_pktc_idx = PKTC_IDX;
13854 
13855 	if (t4_qsize_txq < 128)
13856 		t4_qsize_txq = 128;
13857 
13858 	if (t4_qsize_rxq < 128)
13859 		t4_qsize_rxq = 128;
13860 	while (t4_qsize_rxq & 7)
13861 		t4_qsize_rxq++;
13862 
13863 	t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
13864 
13865 	/*
13866 	 * Number of VIs to create per-port.  The first VI is the "main" regular
13867 	 * VI for the port.  The rest are additional virtual interfaces on the
13868 	 * same physical port.  Note that the main VI does not have native
13869 	 * netmap support but the extra VIs do.
13870 	 *
13871 	 * Limit the number of VIs per port to the number of available
13872 	 * MAC addresses per port.
13873 	 */
13874 	if (t4_num_vis < 1)
13875 		t4_num_vis = 1;
13876 	if (t4_num_vis > nitems(vi_mac_funcs)) {
13877 		t4_num_vis = nitems(vi_mac_funcs);
13878 		printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
13879 	}
13880 
13881 	if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
13882 		pcie_relaxed_ordering = 1;
13883 #if defined(__i386__) || defined(__amd64__)
13884 		if (cpu_vendor_id == CPU_VENDOR_INTEL)
13885 			pcie_relaxed_ordering = 0;
13886 #endif
13887 	}
13888 }
13889 
13890 #ifdef DDB
13891 static void
13892 t4_dump_mem(struct adapter *sc, u_int addr, u_int len)
13893 {
13894 	uint32_t base, j, off, pf, reg, save, win_pos;
13895 
13896 	reg = chip_id(sc) > CHELSIO_T6 ?
13897 	    PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, 2) :
13898 	    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
13899 	save = t4_read_reg(sc, reg);
13900 	base = sc->memwin[2].mw_base;
13901 
13902 	if (is_t4(sc)) {
13903 		pf = 0;
13904 		win_pos = addr & ~0xf;	/* start must be 16B aligned */
13905 	} else {
13906 		pf = V_PFNUM(sc->pf);
13907 		win_pos = addr & ~0x7f;	/* start must be 128B aligned */
13908 	}
13909 	off = addr - win_pos;
13910 	if (chip_id(sc) > CHELSIO_T6)
13911 		win_pos >>= X_T7_MEMOFST_SHIFT;
13912 	t4_write_reg(sc, reg, win_pos | pf);
13913 	t4_read_reg(sc, reg);
13914 
13915 	while (len > 0 && !db_pager_quit) {
13916 		uint32_t buf[8];
13917 		for (j = 0; j < 8; j++, off += 4)
13918 			buf[j] = htonl(t4_read_reg(sc, base + off));
13919 
13920 		db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
13921 		    buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
13922 		    buf[7]);
13923 		if (len <= sizeof(buf))
13924 			len = 0;
13925 		else
13926 			len -= sizeof(buf);
13927 	}
13928 
13929 	t4_write_reg(sc, reg, save);
13930 	t4_read_reg(sc, reg);
13931 }
13932 
13933 static void
13934 t4_dump_tcb(struct adapter *sc, int tid)
13935 {
13936 	uint32_t tcb_addr;
13937 
13938 	/* Dump TCB for the tid */
13939 	tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
13940 	tcb_addr += tid * TCB_SIZE;
13941 	t4_dump_mem(sc, tcb_addr, TCB_SIZE);
13942 }
13943 
13944 static void
13945 t4_dump_devlog(struct adapter *sc)
13946 {
13947 	struct devlog_params *dparams = &sc->params.devlog;
13948 	struct fw_devlog_e e;
13949 	int i, first, j, m, nentries, rc;
13950 	uint64_t ftstamp = UINT64_MAX;
13951 
13952 	if (dparams->start == 0) {
13953 		db_printf("devlog params not valid\n");
13954 		return;
13955 	}
13956 
13957 	nentries = dparams->size / sizeof(struct fw_devlog_e);
13958 	m = fwmtype_to_hwmtype(dparams->memtype);
13959 
13960 	/* Find the first entry. */
13961 	first = -1;
13962 	for (i = 0; i < nentries && !db_pager_quit; i++) {
13963 		rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
13964 		    sizeof(e), (void *)&e);
13965 		if (rc != 0)
13966 			break;
13967 
13968 		if (e.timestamp == 0)
13969 			break;
13970 
13971 		e.timestamp = be64toh(e.timestamp);
13972 		if (e.timestamp < ftstamp) {
13973 			ftstamp = e.timestamp;
13974 			first = i;
13975 		}
13976 	}
13977 
13978 	if (first == -1)
13979 		return;
13980 
13981 	i = first;
13982 	do {
13983 		rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
13984 		    sizeof(e), (void *)&e);
13985 		if (rc != 0)
13986 			return;
13987 
13988 		if (e.timestamp == 0)
13989 			return;
13990 
13991 		e.timestamp = be64toh(e.timestamp);
13992 		e.seqno = be32toh(e.seqno);
13993 		for (j = 0; j < 8; j++)
13994 			e.params[j] = be32toh(e.params[j]);
13995 
13996 		db_printf("%10d  %15ju  %8s  %8s  ",
13997 		    e.seqno, e.timestamp,
13998 		    (e.level < nitems(devlog_level_strings) ?
13999 			devlog_level_strings[e.level] : "UNKNOWN"),
14000 		    (e.facility < nitems(devlog_facility_strings) ?
14001 			devlog_facility_strings[e.facility] : "UNKNOWN"));
14002 		db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
14003 		    e.params[3], e.params[4], e.params[5], e.params[6],
14004 		    e.params[7]);
14005 
14006 		if (++i == nentries)
14007 			i = 0;
14008 	} while (i != first && !db_pager_quit);
14009 }
14010 
14011 static DB_DEFINE_TABLE(show, t4, show_t4);
14012 
14013 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN)
14014 {
14015 	device_t dev;
14016 	int t;
14017 	bool valid;
14018 
14019 	valid = false;
14020 	t = db_read_token();
14021 	if (t == tIDENT) {
14022 		dev = device_lookup_by_name(db_tok_string);
14023 		valid = true;
14024 	}
14025 	db_skip_to_eol();
14026 	if (!valid) {
14027 		db_printf("usage: show t4 devlog <nexus>\n");
14028 		return;
14029 	}
14030 
14031 	if (dev == NULL) {
14032 		db_printf("device not found\n");
14033 		return;
14034 	}
14035 
14036 	t4_dump_devlog(device_get_softc(dev));
14037 }
14038 
14039 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN)
14040 {
14041 	device_t dev;
14042 	int radix, tid, t;
14043 	bool valid;
14044 
14045 	valid = false;
14046 	radix = db_radix;
14047 	db_radix = 10;
14048 	t = db_read_token();
14049 	if (t == tIDENT) {
14050 		dev = device_lookup_by_name(db_tok_string);
14051 		t = db_read_token();
14052 		if (t == tNUMBER) {
14053 			tid = db_tok_number;
14054 			valid = true;
14055 		}
14056 	}
14057 	db_radix = radix;
14058 	db_skip_to_eol();
14059 	if (!valid) {
14060 		db_printf("usage: show t4 tcb <nexus> <tid>\n");
14061 		return;
14062 	}
14063 
14064 	if (dev == NULL) {
14065 		db_printf("device not found\n");
14066 		return;
14067 	}
14068 	if (tid < 0) {
14069 		db_printf("invalid tid\n");
14070 		return;
14071 	}
14072 
14073 	t4_dump_tcb(device_get_softc(dev), tid);
14074 }
14075 
14076 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN)
14077 {
14078 	device_t dev;
14079 	int radix, t;
14080 	bool valid;
14081 
14082 	valid = false;
14083 	radix = db_radix;
14084 	db_radix = 10;
14085 	t = db_read_token();
14086 	if (t == tIDENT) {
14087 		dev = device_lookup_by_name(db_tok_string);
14088 		t = db_read_token();
14089 		if (t == tNUMBER) {
14090 			addr = db_tok_number;
14091 			t = db_read_token();
14092 			if (t == tNUMBER) {
14093 				count = db_tok_number;
14094 				valid = true;
14095 			}
14096 		}
14097 	}
14098 	db_radix = radix;
14099 	db_skip_to_eol();
14100 	if (!valid) {
14101 		db_printf("usage: show t4 memdump <nexus> <addr> <len>\n");
14102 		return;
14103 	}
14104 
14105 	if (dev == NULL) {
14106 		db_printf("device not found\n");
14107 		return;
14108 	}
14109 	if (addr < 0) {
14110 		db_printf("invalid address\n");
14111 		return;
14112 	}
14113 	if (count <= 0) {
14114 		db_printf("invalid length\n");
14115 		return;
14116 	}
14117 
14118 	t4_dump_mem(device_get_softc(dev), addr, count);
14119 }
14120 #endif
14121 
14122 static eventhandler_tag vxlan_start_evtag;
14123 static eventhandler_tag vxlan_stop_evtag;
14124 
14125 struct vxlan_evargs {
14126 	if_t ifp;
14127 	uint16_t port;
14128 };
14129 
14130 static void
14131 enable_vxlan_rx(struct adapter *sc)
14132 {
14133 	int i, rc;
14134 	struct port_info *pi;
14135 	uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
14136 
14137 	ASSERT_SYNCHRONIZED_OP(sc);
14138 
14139 	t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) |
14140 	    F_VXLAN_EN);
14141 	for_each_port(sc, i) {
14142 		pi = sc->port[i];
14143 		if (pi->vxlan_tcam_entry == true)
14144 			continue;
14145 		rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac,
14146 		    match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
14147 		    true);
14148 		if (rc < 0) {
14149 			rc = -rc;
14150 			CH_ERR(&pi->vi[0],
14151 			    "failed to add VXLAN TCAM entry: %d.\n", rc);
14152 		} else {
14153 			MPASS(rc == sc->rawf_base + pi->port_id);
14154 			pi->vxlan_tcam_entry = true;
14155 		}
14156 	}
14157 }
14158 
14159 static void
14160 t4_vxlan_start(struct adapter *sc, void *arg)
14161 {
14162 	struct vxlan_evargs *v = arg;
14163 
14164 	if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
14165 		return;
14166 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0)
14167 		return;
14168 
14169 	if (sc->vxlan_refcount == 0) {
14170 		sc->vxlan_port = v->port;
14171 		sc->vxlan_refcount = 1;
14172 		if (!hw_off_limits(sc))
14173 			enable_vxlan_rx(sc);
14174 	} else if (sc->vxlan_port == v->port) {
14175 		sc->vxlan_refcount++;
14176 	} else {
14177 		CH_ERR(sc, "VXLAN already configured on port  %d; "
14178 		    "ignoring attempt to configure it on port %d\n",
14179 		    sc->vxlan_port, v->port);
14180 	}
14181 	end_synchronized_op(sc, 0);
14182 }
14183 
14184 static void
14185 t4_vxlan_stop(struct adapter *sc, void *arg)
14186 {
14187 	struct vxlan_evargs *v = arg;
14188 
14189 	if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
14190 		return;
14191 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0)
14192 		return;
14193 
14194 	/*
14195 	 * VXLANs may have been configured before the driver was loaded so we
14196 	 * may see more stops than starts.  This is not handled cleanly but at
14197 	 * least we keep the refcount sane.
14198 	 */
14199 	if (sc->vxlan_port != v->port)
14200 		goto done;
14201 	if (sc->vxlan_refcount == 0) {
14202 		CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; "
14203 		    "ignoring attempt to stop it again.\n", sc->vxlan_port);
14204 	} else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc))
14205 		t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0);
14206 done:
14207 	end_synchronized_op(sc, 0);
14208 }
14209 
14210 static void
14211 t4_vxlan_start_handler(void *arg __unused, if_t ifp,
14212     sa_family_t family, u_int port)
14213 {
14214 	struct vxlan_evargs v;
14215 
14216 	MPASS(family == AF_INET || family == AF_INET6);
14217 	v.ifp = ifp;
14218 	v.port = port;
14219 
14220 	t4_iterate(t4_vxlan_start, &v);
14221 }
14222 
14223 static void
14224 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family,
14225     u_int port)
14226 {
14227 	struct vxlan_evargs v;
14228 
14229 	MPASS(family == AF_INET || family == AF_INET6);
14230 	v.ifp = ifp;
14231 	v.port = port;
14232 
14233 	t4_iterate(t4_vxlan_stop, &v);
14234 }
14235 
14236 
14237 static struct sx mlu;	/* mod load unload */
14238 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
14239 
14240 static int
14241 mod_event(module_t mod, int cmd, void *arg)
14242 {
14243 	int rc = 0;
14244 	static int loaded = 0;
14245 
14246 	switch (cmd) {
14247 	case MOD_LOAD:
14248 		sx_xlock(&mlu);
14249 		if (loaded++ == 0) {
14250 			t4_sge_modload();
14251 			t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
14252 			    t4_filter_rpl, CPL_COOKIE_FILTER);
14253 			t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
14254 			    do_l2t_write_rpl, CPL_COOKIE_FILTER);
14255 			t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
14256 			    t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
14257 			t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
14258 			    t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
14259 			t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
14260 			    t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
14261 			t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
14262 			t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
14263 			t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
14264 			    do_smt_write_rpl);
14265 			sx_init(&t4_list_lock, "T4/T5 adapters");
14266 			SLIST_INIT(&t4_list);
14267 			callout_init(&fatal_callout, 1);
14268 #ifdef TCP_OFFLOAD
14269 			sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
14270 #endif
14271 #ifdef INET6
14272 			t4_clip_modload();
14273 #endif
14274 #ifdef KERN_TLS
14275 			t6_ktls_modload();
14276 			t7_ktls_modload();
14277 #endif
14278 			t4_tracer_modload();
14279 			tweak_tunables();
14280 			vxlan_start_evtag =
14281 			    EVENTHANDLER_REGISTER(vxlan_start,
14282 				t4_vxlan_start_handler, NULL,
14283 				EVENTHANDLER_PRI_ANY);
14284 			vxlan_stop_evtag =
14285 			    EVENTHANDLER_REGISTER(vxlan_stop,
14286 				t4_vxlan_stop_handler, NULL,
14287 				EVENTHANDLER_PRI_ANY);
14288 			reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK,
14289 			    taskqueue_thread_enqueue, &reset_tq);
14290 			taskqueue_start_threads(&reset_tq, 1, PI_SOFT,
14291 			    "t4_rst_thr");
14292 		}
14293 		sx_xunlock(&mlu);
14294 		break;
14295 
14296 	case MOD_UNLOAD:
14297 		sx_xlock(&mlu);
14298 		if (--loaded == 0) {
14299 #ifdef TCP_OFFLOAD
14300 			int i;
14301 #endif
14302 			int tries;
14303 
14304 			taskqueue_free(reset_tq);
14305 
14306 			tries = 0;
14307 			while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
14308 				uprintf("%ju clusters with custom free routine "
14309 				    "still is use.\n", t4_sge_extfree_refs());
14310 				pause("t4unload", 2 * hz);
14311 			}
14312 
14313 			sx_slock(&t4_list_lock);
14314 			if (!SLIST_EMPTY(&t4_list)) {
14315 				rc = EBUSY;
14316 				sx_sunlock(&t4_list_lock);
14317 				goto done_unload;
14318 			}
14319 #ifdef TCP_OFFLOAD
14320 			sx_slock(&t4_uld_list_lock);
14321 			for (i = 0; i <= ULD_MAX; i++) {
14322 				if (t4_uld_list[i] != NULL) {
14323 					rc = EBUSY;
14324 					sx_sunlock(&t4_uld_list_lock);
14325 					sx_sunlock(&t4_list_lock);
14326 					goto done_unload;
14327 				}
14328 			}
14329 			sx_sunlock(&t4_uld_list_lock);
14330 #endif
14331 			sx_sunlock(&t4_list_lock);
14332 
14333 			if (t4_sge_extfree_refs() == 0) {
14334 				EVENTHANDLER_DEREGISTER(vxlan_start,
14335 				    vxlan_start_evtag);
14336 				EVENTHANDLER_DEREGISTER(vxlan_stop,
14337 				    vxlan_stop_evtag);
14338 				t4_tracer_modunload();
14339 #ifdef KERN_TLS
14340 				t7_ktls_modunload();
14341 				t6_ktls_modunload();
14342 #endif
14343 #ifdef INET6
14344 				t4_clip_modunload();
14345 #endif
14346 #ifdef TCP_OFFLOAD
14347 				sx_destroy(&t4_uld_list_lock);
14348 #endif
14349 				sx_destroy(&t4_list_lock);
14350 				t4_sge_modunload();
14351 				loaded = 0;
14352 			} else {
14353 				rc = EBUSY;
14354 				loaded++;	/* undo earlier decrement */
14355 			}
14356 		}
14357 done_unload:
14358 		sx_xunlock(&mlu);
14359 		break;
14360 	}
14361 
14362 	return (rc);
14363 }
14364 
14365 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0);
14366 MODULE_VERSION(t4nex, 1);
14367 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
14368 #ifdef DEV_NETMAP
14369 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
14370 #endif /* DEV_NETMAP */
14371 
14372 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0);
14373 MODULE_VERSION(t5nex, 1);
14374 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
14375 #ifdef DEV_NETMAP
14376 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
14377 #endif /* DEV_NETMAP */
14378 
14379 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0);
14380 MODULE_VERSION(t6nex, 1);
14381 MODULE_DEPEND(t6nex, crypto, 1, 1, 1);
14382 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
14383 #ifdef DEV_NETMAP
14384 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
14385 #endif /* DEV_NETMAP */
14386 
14387 DRIVER_MODULE(chnex, pci, ch_driver, mod_event, 0);
14388 MODULE_VERSION(chnex, 1);
14389 MODULE_DEPEND(chnex, crypto, 1, 1, 1);
14390 MODULE_DEPEND(chnex, firmware, 1, 1, 1);
14391 #ifdef DEV_NETMAP
14392 MODULE_DEPEND(chnex, netmap, 1, 1, 1);
14393 #endif /* DEV_NETMAP */
14394 
14395 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0);
14396 MODULE_VERSION(cxgbe, 1);
14397 
14398 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0);
14399 MODULE_VERSION(cxl, 1);
14400 
14401 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0);
14402 MODULE_VERSION(cc, 1);
14403 
14404 DRIVER_MODULE(che, chnex, che_driver, 0, 0);
14405 MODULE_VERSION(che, 1);
14406 
14407 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0);
14408 MODULE_VERSION(vcxgbe, 1);
14409 
14410 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0);
14411 MODULE_VERSION(vcxl, 1);
14412 
14413 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0);
14414 MODULE_VERSION(vcc, 1);
14415 
14416 DRIVER_MODULE(vche, che, vche_driver, 0, 0);
14417 MODULE_VERSION(vche, 1);
14418