xref: /linux/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h (revision befcc89362383208f62b15887592758165459e3d)
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _HWMGR_H_
24 #define _HWMGR_H_
25 
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "hardwaremanager.h"
29 #include "hwmgr_ppt.h"
30 #include "ppatomctrl.h"
31 #include "power_state.h"
32 #include "smu_helper.h"
33 
34 struct pp_hwmgr;
35 struct phm_fan_speed_info;
36 struct pp_atomctrl_voltage_table;
37 
38 #define VOLTAGE_SCALE 4
39 #define VOLTAGE_VID_OFFSET_SCALE1   625
40 #define VOLTAGE_VID_OFFSET_SCALE2   100
41 
42 enum DISPLAY_GAP {
43 	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
44 	DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
45 	DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
46 	DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
47 };
48 typedef enum DISPLAY_GAP DISPLAY_GAP;
49 
50 enum BACO_STATE {
51 	BACO_STATE_OUT = 0,
52 	BACO_STATE_IN,
53 };
54 
55 struct vi_dpm_level {
56 	bool enabled;
57 	uint32_t value;
58 	uint32_t param1;
59 };
60 
61 struct vi_dpm_table {
62 	uint32_t count;
63 	struct vi_dpm_level dpm_level[];
64 };
65 
66 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
67 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
68 #define PCIE_PERF_REQ_GEN1         2
69 #define PCIE_PERF_REQ_GEN2         3
70 #define PCIE_PERF_REQ_GEN3         4
71 
72 enum PHM_BackEnd_Magic {
73 	PHM_Dummy_Magic       = 0xAA5555AA,
74 	PHM_RV770_Magic       = 0xDCBAABCD,
75 	PHM_Kong_Magic        = 0x239478DF,
76 	PHM_NIslands_Magic    = 0x736C494E,
77 	PHM_Sumo_Magic        = 0x8339FA11,
78 	PHM_SIslands_Magic    = 0x369431AC,
79 	PHM_Trinity_Magic     = 0x96751873,
80 	PHM_CIslands_Magic    = 0x38AC78B0,
81 	PHM_Kv_Magic          = 0xDCBBABC0,
82 	PHM_VIslands_Magic    = 0x20130307,
83 	PHM_Cz_Magic          = 0x67DCBA25,
84 	PHM_Rv_Magic          = 0x20161121
85 };
86 
87 struct phm_set_power_state_input {
88 	const struct pp_hw_power_state *pcurrent_state;
89 	const struct pp_hw_power_state *pnew_state;
90 };
91 
92 struct phm_clock_array {
93 	uint32_t count;
94 	uint32_t values[];
95 };
96 
97 struct phm_clock_voltage_dependency_record {
98 	uint32_t clk;
99 	uint32_t v;
100 };
101 
102 struct phm_vceclock_voltage_dependency_record {
103 	uint32_t ecclk;
104 	uint32_t evclk;
105 	uint32_t v;
106 };
107 
108 struct phm_uvdclock_voltage_dependency_record {
109 	uint32_t vclk;
110 	uint32_t dclk;
111 	uint32_t v;
112 };
113 
114 struct phm_samuclock_voltage_dependency_record {
115 	uint32_t samclk;
116 	uint32_t v;
117 };
118 
119 struct phm_acpclock_voltage_dependency_record {
120 	uint32_t acpclk;
121 	uint32_t v;
122 };
123 
124 struct phm_clock_voltage_dependency_table {
125 	uint32_t count;
126 	struct phm_clock_voltage_dependency_record entries[];
127 };
128 
129 struct phm_phase_shedding_limits_record {
130 	uint32_t  Voltage;
131 	uint32_t    Sclk;
132 	uint32_t    Mclk;
133 };
134 
135 struct phm_uvd_clock_voltage_dependency_record {
136 	uint32_t vclk;
137 	uint32_t dclk;
138 	uint32_t v;
139 };
140 
141 struct phm_uvd_clock_voltage_dependency_table {
142 	uint8_t count;
143 	struct phm_uvd_clock_voltage_dependency_record entries[];
144 };
145 
146 struct phm_acp_clock_voltage_dependency_record {
147 	uint32_t acpclk;
148 	uint32_t v;
149 };
150 
151 struct phm_acp_clock_voltage_dependency_table {
152 	uint32_t count;
153 	struct phm_acp_clock_voltage_dependency_record entries[];
154 };
155 
156 struct phm_vce_clock_voltage_dependency_record {
157 	uint32_t ecclk;
158 	uint32_t evclk;
159 	uint32_t v;
160 };
161 
162 struct phm_phase_shedding_limits_table {
163 	uint32_t count;
164 	struct phm_phase_shedding_limits_record  entries[];
165 };
166 
167 struct phm_vceclock_voltage_dependency_table {
168 	uint8_t count;
169 	struct phm_vceclock_voltage_dependency_record entries[];
170 };
171 
172 struct phm_uvdclock_voltage_dependency_table {
173 	uint8_t count;
174 	struct phm_uvdclock_voltage_dependency_record entries[];
175 };
176 
177 struct phm_samuclock_voltage_dependency_table {
178 	uint8_t count;
179 	struct phm_samuclock_voltage_dependency_record entries[];
180 };
181 
182 struct phm_acpclock_voltage_dependency_table {
183 	uint32_t count;
184 	struct phm_acpclock_voltage_dependency_record entries[];
185 };
186 
187 struct phm_vce_clock_voltage_dependency_table {
188 	uint8_t count;
189 	struct phm_vce_clock_voltage_dependency_record entries[];
190 };
191 
192 
193 enum SMU_ASIC_RESET_MODE {
194     SMU_ASIC_RESET_MODE_0,
195     SMU_ASIC_RESET_MODE_1,
196     SMU_ASIC_RESET_MODE_2,
197 };
198 
199 struct pp_smumgr_func {
200 	char *name;
201 	int (*smu_init)(struct pp_hwmgr  *hwmgr);
202 	int (*smu_fini)(struct pp_hwmgr  *hwmgr);
203 	int (*start_smu)(struct pp_hwmgr  *hwmgr);
204 	int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,
205 				    uint32_t firmware);
206 	int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
207 	int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
208 					    uint32_t firmware);
209 	uint32_t (*get_argument)(struct pp_hwmgr  *hwmgr);
210 	int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
211 	int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
212 					  uint16_t msg, uint32_t parameter);
213 	int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,
214 					 void **table);
215 	int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);
216 	int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
217 	int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
218 	int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
219 	int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
220 	int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
221 	int (*init_smc_table)(struct pp_hwmgr *hwmgr);
222 	int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
223 	int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
224 	int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
225 	uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
226 	uint32_t (*get_mac_definition)(uint32_t value);
227 	bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
228 	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
229 	int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
230 	int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
231 	int (*stop_smc)(struct pp_hwmgr *hwmgr);
232 };
233 
234 struct pp_hwmgr_func {
235 	int (*backend_init)(struct pp_hwmgr *hw_mgr);
236 	int (*backend_fini)(struct pp_hwmgr *hw_mgr);
237 	int (*asic_setup)(struct pp_hwmgr *hw_mgr);
238 	int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
239 
240 	int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
241 				struct pp_power_state  *prequest_ps,
242 			const struct pp_power_state *pcurrent_ps);
243 
244 	int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
245 
246 	int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
247 					enum amd_dpm_forced_level level);
248 
249 	int (*dynamic_state_management_enable)(
250 						struct pp_hwmgr *hw_mgr);
251 	int (*dynamic_state_management_disable)(
252 						struct pp_hwmgr *hw_mgr);
253 
254 	int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
255 				     struct pp_hw_power_state *hw_ps);
256 
257 	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
258 			    unsigned long, struct pp_power_state *);
259 	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
260 	int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
261 	void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
262 	void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
263 	void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
264 	uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
265 	uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
266 	int (*power_state_set)(struct pp_hwmgr *hwmgr,
267 						const void *state);
268 	int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
269 	int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
270 	int (*display_config_changed)(struct pp_hwmgr *hwmgr);
271 	int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
272 	int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
273 						const uint32_t *msg_id);
274 	int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
275 	int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
276 	int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
277 	int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
278 	void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
279 	uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
280 	int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed);
281 	int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
282 	int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed);
283 	int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
284 	int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
285 	int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
286 	int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
287 	bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
288 	int (*check_states_equal)(struct pp_hwmgr *hwmgr,
289 					const struct pp_hw_power_state *pstate1,
290 					const struct pp_hw_power_state *pstate2,
291 					bool *equal);
292 	int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
293 	int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
294 				bool cc6_disable, bool pstate_disable,
295 				bool pstate_switch_disable);
296 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
297 			struct amd_pp_simple_clock_info *info);
298 	int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
299 			PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
300 	int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
301 				const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
302 	int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
303 	int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
304 			enum amd_pp_clock_type type,
305 			struct pp_clock_levels_with_latency *clocks);
306 	int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
307 			enum amd_pp_clock_type type,
308 			struct pp_clock_levels_with_voltage *clocks);
309 	int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
310 	int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
311 			struct pp_display_clock_request *clock);
312 	int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
313 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
314 	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
315 	int (*emit_clock_levels)(struct pp_hwmgr *hwmgr,
316 				 enum pp_clock_type type, char *buf, int *offset);
317 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
318 	int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
319 	int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
320 	int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
321 	int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
322 	int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
323 	int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
324 	int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
325 	int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
326 	int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
327 	int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
328 	int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
329 	int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
330 					uint32_t virtual_addr_low,
331 					uint32_t virtual_addr_hi,
332 					uint32_t mc_addr_low,
333 					uint32_t mc_addr_hi,
334 					uint32_t size);
335 	int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
336 					struct PP_TemperatureRange *range);
337 	int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
338 	int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
339 	int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
340 					enum PP_OD_DPM_TABLE_COMMAND type,
341 					long *input, uint32_t size);
342 	int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
343 				      enum PP_OD_DPM_TABLE_COMMAND type,
344 				      long *input, uint32_t size);
345 	int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
346 	int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
347 	int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
348 	int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
349 	int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
350 	int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
351 	int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
352 	int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
353 	int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
354 	int (*get_bamaco_support)(struct pp_hwmgr *hwmgr);
355 	int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
356 	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
357 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
358 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
359 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
360 	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
361 	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool acquire);
362 	int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
363 	int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
364 	int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
365 					bool disable);
366 	ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
367 	int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
368 };
369 
370 struct pp_table_func {
371 	int (*pptable_init)(struct pp_hwmgr *hw_mgr);
372 	int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
373 	int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
374 	int (*pptable_get_vce_state_table_entry)(
375 						struct pp_hwmgr *hwmgr,
376 						unsigned long i,
377 						struct amd_vce_state *vce_state,
378 						void **clock_info,
379 						unsigned long *flag);
380 };
381 
382 union phm_cac_leakage_record {
383 	struct {
384 		uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
385 		uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
386 	};
387 	struct {
388 		uint16_t Vddc1;
389 		uint16_t Vddc2;
390 		uint16_t Vddc3;
391 	};
392 };
393 
394 struct phm_cac_leakage_table {
395 	uint32_t count;
396 	union phm_cac_leakage_record entries[];
397 };
398 
399 struct phm_samu_clock_voltage_dependency_record {
400 	uint32_t samclk;
401 	uint32_t v;
402 };
403 
404 
405 struct phm_samu_clock_voltage_dependency_table {
406 	uint8_t count;
407 	struct phm_samu_clock_voltage_dependency_record entries[];
408 };
409 
410 struct phm_cac_tdp_table {
411 	uint16_t usTDP;
412 	uint16_t usConfigurableTDP;
413 	uint16_t usTDC;
414 	uint16_t usBatteryPowerLimit;
415 	uint16_t usSmallPowerLimit;
416 	uint16_t usLowCACLeakage;
417 	uint16_t usHighCACLeakage;
418 	uint16_t usMaximumPowerDeliveryLimit;
419 	uint16_t usEDCLimit;
420 	uint16_t usOperatingTempMinLimit;
421 	uint16_t usOperatingTempMaxLimit;
422 	uint16_t usOperatingTempStep;
423 	uint16_t usOperatingTempHyst;
424 	uint16_t usDefaultTargetOperatingTemp;
425 	uint16_t usTargetOperatingTemp;
426 	uint16_t usPowerTuneDataSetID;
427 	uint16_t usSoftwareShutdownTemp;
428 	uint16_t usClockStretchAmount;
429 	uint16_t usTemperatureLimitHotspot;
430 	uint16_t usTemperatureLimitLiquid1;
431 	uint16_t usTemperatureLimitLiquid2;
432 	uint16_t usTemperatureLimitVrVddc;
433 	uint16_t usTemperatureLimitVrMvdd;
434 	uint16_t usTemperatureLimitPlx;
435 	uint8_t  ucLiquid1_I2C_address;
436 	uint8_t  ucLiquid2_I2C_address;
437 	uint8_t  ucLiquid_I2C_Line;
438 	uint8_t  ucVr_I2C_address;
439 	uint8_t  ucVr_I2C_Line;
440 	uint8_t  ucPlx_I2C_address;
441 	uint8_t  ucPlx_I2C_Line;
442 	uint32_t usBoostPowerLimit;
443 	uint8_t  ucCKS_LDO_REFSEL;
444 	uint8_t  ucHotSpotOnly;
445 };
446 
447 struct phm_tdp_table {
448 	uint16_t usTDP;
449 	uint16_t usConfigurableTDP;
450 	uint16_t usTDC;
451 	uint16_t usBatteryPowerLimit;
452 	uint16_t usSmallPowerLimit;
453 	uint16_t usLowCACLeakage;
454 	uint16_t usHighCACLeakage;
455 	uint16_t usMaximumPowerDeliveryLimit;
456 	uint16_t usEDCLimit;
457 	uint16_t usOperatingTempMinLimit;
458 	uint16_t usOperatingTempMaxLimit;
459 	uint16_t usOperatingTempStep;
460 	uint16_t usOperatingTempHyst;
461 	uint16_t usDefaultTargetOperatingTemp;
462 	uint16_t usTargetOperatingTemp;
463 	uint16_t usPowerTuneDataSetID;
464 	uint16_t usSoftwareShutdownTemp;
465 	uint16_t usClockStretchAmount;
466 	uint16_t usTemperatureLimitTedge;
467 	uint16_t usTemperatureLimitHotspot;
468 	uint16_t usTemperatureLimitLiquid1;
469 	uint16_t usTemperatureLimitLiquid2;
470 	uint16_t usTemperatureLimitHBM;
471 	uint16_t usTemperatureLimitVrVddc;
472 	uint16_t usTemperatureLimitVrMvdd;
473 	uint16_t usTemperatureLimitPlx;
474 	uint8_t  ucLiquid1_I2C_address;
475 	uint8_t  ucLiquid2_I2C_address;
476 	uint8_t  ucLiquid_I2C_Line;
477 	uint8_t  ucVr_I2C_address;
478 	uint8_t  ucVr_I2C_Line;
479 	uint8_t  ucPlx_I2C_address;
480 	uint8_t  ucPlx_I2C_Line;
481 	uint8_t  ucLiquid_I2C_LineSDA;
482 	uint8_t  ucVr_I2C_LineSDA;
483 	uint8_t  ucPlx_I2C_LineSDA;
484 	uint32_t usBoostPowerLimit;
485 	uint16_t usBoostStartTemperature;
486 	uint16_t usBoostStopTemperature;
487 	uint32_t  ulBoostClock;
488 };
489 
490 struct phm_ppm_table {
491 	uint8_t   ppm_design;
492 	uint16_t  cpu_core_number;
493 	uint32_t  platform_tdp;
494 	uint32_t  small_ac_platform_tdp;
495 	uint32_t  platform_tdc;
496 	uint32_t  small_ac_platform_tdc;
497 	uint32_t  apu_tdp;
498 	uint32_t  dgpu_tdp;
499 	uint32_t  dgpu_ulv_power;
500 	uint32_t  tj_max;
501 };
502 
503 struct phm_vq_budgeting_record {
504 	uint32_t ulCUs;
505 	uint32_t ulSustainableSOCPowerLimitLow;
506 	uint32_t ulSustainableSOCPowerLimitHigh;
507 	uint32_t ulMinSclkLow;
508 	uint32_t ulMinSclkHigh;
509 	uint8_t  ucDispConfig;
510 	uint32_t ulDClk;
511 	uint32_t ulEClk;
512 	uint32_t ulSustainableSclk;
513 	uint32_t ulSustainableCUs;
514 };
515 
516 struct phm_vq_budgeting_table {
517 	uint8_t numEntries;
518 	struct phm_vq_budgeting_record entries[0];
519 };
520 
521 struct phm_clock_and_voltage_limits {
522 	uint32_t sclk;
523 	uint32_t mclk;
524 	uint32_t gfxclk;
525 	uint16_t vddc;
526 	uint16_t vddci;
527 	uint16_t vddgfx;
528 	uint16_t vddmem;
529 };
530 
531 /* Structure to hold PPTable information */
532 
533 struct phm_ppt_v1_information {
534 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
535 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
536 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
537 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
538 	struct phm_clock_array *valid_sclk_values;
539 	struct phm_clock_array *valid_mclk_values;
540 	struct phm_clock_array *valid_socclk_values;
541 	struct phm_clock_array *valid_dcefclk_values;
542 	struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
543 	struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
544 	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
545 	struct phm_ppm_table *ppm_parameter_table;
546 	struct phm_cac_tdp_table *cac_dtp_table;
547 	struct phm_tdp_table *tdp_table;
548 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
549 	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
550 	struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
551 	struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
552 	struct phm_ppt_v1_pcie_table *pcie_table;
553 	struct phm_ppt_v1_gpio_table *gpio_table;
554 	uint16_t us_ulv_voltage_offset;
555 	uint16_t us_ulv_smnclk_did;
556 	uint16_t us_ulv_mp1clk_did;
557 	uint16_t us_ulv_gfxclk_bypass;
558 	uint16_t us_gfxclk_slew_rate;
559 	uint16_t us_min_gfxclk_freq_limit;
560 };
561 
562 struct phm_ppt_v2_information {
563 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
564 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
565 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
566 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
567 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
568 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
569 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
570 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
571 
572 	struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
573 
574 	struct phm_clock_array *valid_sclk_values;
575 	struct phm_clock_array *valid_mclk_values;
576 	struct phm_clock_array *valid_socclk_values;
577 	struct phm_clock_array *valid_dcefclk_values;
578 
579 	struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
580 	struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
581 
582 	struct phm_ppm_table *ppm_parameter_table;
583 	struct phm_cac_tdp_table *cac_dtp_table;
584 	struct phm_tdp_table *tdp_table;
585 
586 	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
587 	struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
588 	struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
589 	struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
590 
591 	struct phm_ppt_v1_pcie_table *pcie_table;
592 
593 	uint16_t us_ulv_voltage_offset;
594 	uint16_t us_ulv_smnclk_did;
595 	uint16_t us_ulv_mp1clk_did;
596 	uint16_t us_ulv_gfxclk_bypass;
597 	uint16_t us_gfxclk_slew_rate;
598 	uint16_t us_min_gfxclk_freq_limit;
599 
600 	uint8_t  uc_gfx_dpm_voltage_mode;
601 	uint8_t  uc_soc_dpm_voltage_mode;
602 	uint8_t  uc_uclk_dpm_voltage_mode;
603 	uint8_t  uc_uvd_dpm_voltage_mode;
604 	uint8_t  uc_vce_dpm_voltage_mode;
605 	uint8_t  uc_mp0_dpm_voltage_mode;
606 	uint8_t  uc_dcef_dpm_voltage_mode;
607 };
608 
609 struct phm_ppt_v3_information {
610 	uint8_t uc_thermal_controller_type;
611 
612 	uint16_t us_small_power_limit1;
613 	uint16_t us_small_power_limit2;
614 	uint16_t us_boost_power_limit;
615 
616 	uint16_t us_od_turbo_power_limit;
617 	uint16_t us_od_powersave_power_limit;
618 	uint16_t us_software_shutdown_temp;
619 
620 	uint32_t *power_saving_clock_max;
621 	uint32_t *power_saving_clock_min;
622 
623 	uint8_t *od_feature_capabilities;
624 	uint32_t *od_settings_max;
625 	uint32_t *od_settings_min;
626 
627 	void *smc_pptable;
628 };
629 
630 struct phm_dynamic_state_info {
631 	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
632 	struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
633 	struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
634 	struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
635 	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
636 	struct phm_clock_array                    *valid_sclk_values;
637 	struct phm_clock_array                    *valid_mclk_values;
638 	struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
639 	struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
640 	uint32_t                                  mclk_sclk_ratio;
641 	uint32_t                                  sclk_mclk_delta;
642 	uint32_t                                  vddc_vddci_delta;
643 	uint32_t                                  min_vddc_for_pcie_gen2;
644 	struct phm_cac_leakage_table              *cac_leakage_table;
645 	struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
646 
647 	struct phm_vce_clock_voltage_dependency_table
648 					    *vce_clock_voltage_dependency_table;
649 	struct phm_uvd_clock_voltage_dependency_table
650 					    *uvd_clock_voltage_dependency_table;
651 	struct phm_acp_clock_voltage_dependency_table
652 					    *acp_clock_voltage_dependency_table;
653 	struct phm_samu_clock_voltage_dependency_table
654 					   *samu_clock_voltage_dependency_table;
655 
656 	struct phm_ppm_table                          *ppm_parameter_table;
657 	struct phm_cac_tdp_table                      *cac_dtp_table;
658 	struct phm_clock_voltage_dependency_table	*vdd_gfx_dependency_on_sclk;
659 };
660 
661 struct pp_fan_info {
662 	bool bNoFan;
663 	uint8_t   ucTachometerPulsesPerRevolution;
664 	uint32_t   ulMinRPM;
665 	uint32_t   ulMaxRPM;
666 };
667 
668 struct pp_advance_fan_control_parameters {
669 	uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
670 	uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
671 	uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
672 	uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
673 	uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
674 	uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
675 	uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
676 	uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
677 	uint16_t  usTMax;                          /* The max temperature */
678 	uint8_t   ucFanControlMode;
679 	uint16_t  usFanPWMMinLimit;
680 	uint16_t  usFanPWMMaxLimit;
681 	uint16_t  usFanPWMStep;
682 	uint16_t  usDefaultMaxFanPWM;
683 	uint16_t  usFanOutputSensitivity;
684 	uint16_t  usDefaultFanOutputSensitivity;
685 	uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
686 	uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
687 	uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
688 	uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
689 	uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
690 	uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
691 	uint16_t  usFanCurrentLow;                 /* Low current */
692 	uint16_t  usFanCurrentHigh;                /* High current */
693 	uint16_t  usFanRPMLow;                     /* Low RPM */
694 	uint16_t  usFanRPMHigh;                    /* High RPM */
695 	uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
696 	uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
697 	uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
698 	uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
699 	uint16_t  usFanGainHotspot;
700 	uint16_t  usFanGainLiquid;
701 	uint16_t  usFanGainVrVddc;
702 	uint16_t  usFanGainVrMvdd;
703 	uint16_t  usFanGainPlx;
704 	uint16_t  usFanGainHbm;
705 	uint8_t   ucEnableZeroRPM;
706 	uint8_t   ucFanStopTemperature;
707 	uint8_t   ucFanStartTemperature;
708 	uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
709 	uint32_t  ulTargetGfxClk;
710 	uint16_t  usZeroRPMStartTemperature;
711 	uint16_t  usZeroRPMStopTemperature;
712 	uint16_t  usMGpuThrottlingRPMLimit;
713 };
714 
715 struct pp_thermal_controller_info {
716 	uint8_t ucType;
717 	uint8_t ucI2cLine;
718 	uint8_t ucI2cAddress;
719 	uint8_t use_hw_fan_control;
720 	struct pp_fan_info fanInfo;
721 	struct pp_advance_fan_control_parameters advanceFanControlParameters;
722 };
723 
724 struct phm_microcode_version_info {
725 	uint32_t SMC;
726 	uint32_t DMCU;
727 	uint32_t MC;
728 	uint32_t NB;
729 };
730 
731 enum PP_TABLE_VERSION {
732 	PP_TABLE_V0 = 0,
733 	PP_TABLE_V1,
734 	PP_TABLE_V2,
735 	PP_TABLE_MAX
736 };
737 
738 /**
739  * The main hardware manager structure.
740  */
741 #define Workload_Policy_Max 6
742 
743 struct pp_hwmgr {
744 	void *adev;
745 	uint32_t chip_family;
746 	uint32_t chip_id;
747 	uint32_t smu_version;
748 	bool not_vf;
749 	bool pm_en;
750 	bool pp_one_vf;
751 	struct mutex msg_lock;
752 
753 	uint32_t pp_table_version;
754 	void *device;
755 	struct pp_smumgr *smumgr;
756 	const void *soft_pp_table;
757 	uint32_t soft_pp_table_size;
758 	void *hardcode_pp_table;
759 	bool need_pp_table_upload;
760 
761 	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
762 	uint32_t num_vce_state_tables;
763 
764 	enum amd_dpm_forced_level dpm_level;
765 	enum amd_dpm_forced_level saved_dpm_level;
766 	enum amd_dpm_forced_level request_dpm_level;
767 	uint32_t usec_timeout;
768 	void *pptable;
769 	struct phm_platform_descriptor platform_descriptor;
770 	void *backend;
771 
772 	void *smu_backend;
773 	const struct pp_smumgr_func *smumgr_funcs;
774 	bool is_kicker;
775 
776 	enum PP_DAL_POWERLEVEL dal_power_level;
777 	struct phm_dynamic_state_info dyn_state;
778 	const struct pp_hwmgr_func *hwmgr_func;
779 	const struct pp_table_func *pptable_func;
780 
781 	struct pp_power_state    *ps;
782 	uint32_t num_ps;
783 	struct pp_thermal_controller_info thermal_controller;
784 	bool fan_ctrl_is_in_default_mode;
785 	uint32_t fan_ctrl_default_mode;
786 	bool fan_ctrl_enabled;
787 	uint32_t tmin;
788 	struct phm_microcode_version_info microcode_version_info;
789 	uint32_t ps_size;
790 	struct pp_power_state    *current_ps;
791 	struct pp_power_state    *request_ps;
792 	struct pp_power_state    *boot_ps;
793 	struct pp_power_state    *uvd_ps;
794 	const struct amd_pp_display_configuration *display_config;
795 	uint32_t feature_mask;
796 	bool avfs_supported;
797 	/* UMD Pstate */
798 	bool en_umd_pstate;
799 	uint32_t power_profile_mode;
800 	uint32_t default_power_profile_mode;
801 	uint32_t pstate_sclk;
802 	uint32_t pstate_mclk;
803 	bool od_enabled;
804 	uint32_t power_limit;
805 	uint32_t default_power_limit;
806 	uint32_t workload_mask;
807 	uint32_t workload_prority[Workload_Policy_Max];
808 	uint32_t workload_setting[Workload_Policy_Max];
809 	bool gfxoff_state_changed_by_workload;
810 	uint32_t pstate_sclk_peak;
811 	uint32_t pstate_mclk_peak;
812 
813 	struct delayed_work swctf_delayed_work;
814 };
815 
816 int hwmgr_early_init(struct pp_hwmgr *hwmgr);
817 int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
818 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
819 int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
820 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
821 int hwmgr_suspend(struct pp_hwmgr *hwmgr);
822 int hwmgr_resume(struct pp_hwmgr *hwmgr);
823 
824 int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
825 				enum amd_pp_task task_id,
826 				enum amd_pm_state_type *user_state);
827 
828 
829 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
830 
831 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
832 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
833 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
834 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
835 
836 #endif /* _HWMGR_H_ */
837