1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /******************************************************************************
3 *
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 *
6 * Contact Information:
7 * Intel Linux Wireless <ilw@linux.intel.com>
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
9 *
10 *****************************************************************************/
11 #ifndef __il_core_h__
12 #define __il_core_h__
13
14 #include <linux/interrupt.h>
15 #include <linux/pci.h> /* for struct pci_device_id */
16 #include <linux/kernel.h>
17 #include <linux/leds.h>
18 #include <linux/wait.h>
19 #include <linux/io.h>
20 #include <net/mac80211.h>
21 #include <net/ieee80211_radiotap.h>
22
23 #include "commands.h"
24 #include "csr.h"
25 #include "prph.h"
26
27 struct il_host_cmd;
28 struct il_cmd;
29 struct il_tx_queue;
30
31 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
32 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
33 #define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
34 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
35
36 #define RX_QUEUE_SIZE 256
37 #define RX_QUEUE_MASK 255
38 #define RX_QUEUE_SIZE_LOG 8
39
40 /*
41 * RX related structures and functions
42 */
43 #define RX_FREE_BUFFERS 64
44 #define RX_LOW_WATERMARK 8
45
46 #define U32_PAD(n) ((4-(n))&0x3)
47
48 /* CT-KILL constants */
49 #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
50
51 /* Default noise level to report when noise measurement is not available.
52 * This may be because we're:
53 * 1) Not associated (4965, no beacon stats being sent to driver)
54 * 2) Scanning (noise measurement does not apply to associated channel)
55 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
56 * Use default noise value of -127 ... this is below the range of measurable
57 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
58 * Also, -127 works better than 0 when averaging frames with/without
59 * noise info (e.g. averaging might be done in app); measured dBm values are
60 * always negative ... using a negative value as the default keeps all
61 * averages within an s8's (used in some apps) range of negative values. */
62 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
63
64 /*
65 * RTS threshold here is total size [2347] minus 4 FCS bytes
66 * Per spec:
67 * a value of 0 means RTS on all data/management packets
68 * a value > max MSDU size means no RTS
69 * else RTS for data/management frames where MPDU is larger
70 * than RTS value.
71 */
72 #define DEFAULT_RTS_THRESHOLD 2347U
73 #define MIN_RTS_THRESHOLD 0U
74 #define MAX_RTS_THRESHOLD 2347U
75 #define MAX_MSDU_SIZE 2304U
76 #define MAX_MPDU_SIZE 2346U
77 #define DEFAULT_BEACON_INTERVAL 100U
78 #define DEFAULT_SHORT_RETRY_LIMIT 7U
79 #define DEFAULT_LONG_RETRY_LIMIT 4U
80
81 struct il_rx_buf {
82 dma_addr_t page_dma;
83 struct page *page;
84 struct list_head list;
85 };
86
87 #define rxb_addr(r) page_address(r->page)
88
89 /* defined below */
90 struct il_device_cmd;
91
92 struct il_cmd_meta {
93 /* only for SYNC commands, iff the reply skb is wanted */
94 struct il_host_cmd *source;
95 /*
96 * only for ASYNC commands
97 * (which is somewhat stupid -- look at common.c for instance
98 * which duplicates a bunch of code because the callback isn't
99 * invoked for SYNC commands, if it were and its result passed
100 * through it would be simpler...)
101 */
102 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
103 struct il_rx_pkt *pkt);
104
105 /* The CMD_SIZE_HUGE flag bit indicates that the command
106 * structure is stored at the end of the shared queue memory. */
107 u32 flags;
108
109 DEFINE_DMA_UNMAP_ADDR(mapping);
110 DEFINE_DMA_UNMAP_LEN(len);
111 };
112
113 /*
114 * Generic queue structure
115 *
116 * Contains common data for Rx and Tx queues
117 */
118 struct il_queue {
119 int n_bd; /* number of BDs in this queue */
120 int write_ptr; /* 1-st empty entry (idx) host_w */
121 int read_ptr; /* last used entry (idx) host_r */
122 /* use for monitoring and recovering the stuck queue */
123 dma_addr_t dma_addr; /* physical addr for BD's */
124 int n_win; /* safe queue win */
125 u32 id;
126 int low_mark; /* low watermark, resume queue if free
127 * space more than this */
128 int high_mark; /* high watermark, stop queue if free
129 * space less than this */
130 };
131
132 /**
133 * struct il_tx_queue - Tx Queue for DMA
134 * @q: generic Rx/Tx queue descriptor
135 * @bd: base of circular buffer of TFDs
136 * @cmd: array of command/TX buffer pointers
137 * @meta: array of meta data for each command/tx buffer
138 * @dma_addr_cmd: physical address of cmd/tx buffer array
139 * @skbs: array of per-TFD socket buffer pointers
140 * @time_stamp: time (in jiffies) of last read_ptr change
141 * @need_update: indicates need to update read/write idx
142 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
143 *
144 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
145 * descriptors) and required locking structures.
146 */
147 #define TFD_TX_CMD_SLOTS 256
148 #define TFD_CMD_SLOTS 32
149
150 struct il_tx_queue {
151 struct il_queue q;
152 void *tfds;
153 struct il_device_cmd **cmd;
154 struct il_cmd_meta *meta;
155 struct sk_buff **skbs;
156 unsigned long time_stamp;
157 u8 need_update;
158 u8 sched_retry;
159 u8 active;
160 u8 swq_id;
161 };
162
163 /*
164 * EEPROM access time values:
165 *
166 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
167 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
168 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
169 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
170 */
171 #define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
172
173 #define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
174 #define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
175
176 /*
177 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
178 *
179 * IBSS and/or AP operation is allowed *only* on those channels with
180 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
181 * RADAR detection is not supported by the 4965 driver, but is a
182 * requirement for establishing a new network for legal operation on channels
183 * requiring RADAR detection or restricting ACTIVE scanning.
184 *
185 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
186 * It only indicates that 20 MHz channel use is supported; HT40 channel
187 * usage is indicated by a separate set of regulatory flags for each
188 * HT40 channel pair.
189 *
190 * NOTE: Using a channel inappropriately will result in a uCode error!
191 */
192 #define IL_NUM_TX_CALIB_GROUPS 5
193 enum {
194 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
195 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
196 /* Bit 2 Reserved */
197 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
198 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
199 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
200 /* Bit 6 Reserved (was Narrow Channel) */
201 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
202 };
203
204 /* SKU Capabilities */
205 /* 3945 only */
206 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
207 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
208
209 /* *regulatory* channel data format in eeprom, one for each channel.
210 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
211 struct il_eeprom_channel {
212 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
213 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
214 } __packed;
215
216 /* 3945 Specific */
217 #define EEPROM_3945_EEPROM_VERSION (0x2f)
218
219 /* 4965 has two radio transmitters (and 3 radio receivers) */
220 #define EEPROM_TX_POWER_TX_CHAINS (2)
221
222 /* 4965 has room for up to 8 sets of txpower calibration data */
223 #define EEPROM_TX_POWER_BANDS (8)
224
225 /* 4965 factory calibration measures txpower gain settings for
226 * each of 3 target output levels */
227 #define EEPROM_TX_POWER_MEASUREMENTS (3)
228
229 /* 4965 Specific */
230 /* 4965 driver does not work with txpower calibration version < 5 */
231 #define EEPROM_4965_TX_POWER_VERSION (5)
232 #define EEPROM_4965_EEPROM_VERSION (0x2f)
233 #define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
234 #define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
235 #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
236 #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
237
238 /* 2.4 GHz */
239 extern const u8 il_eeprom_band_1[14];
240
241 /*
242 * factory calibration data for one txpower level, on one channel,
243 * measured on one of the 2 tx chains (radio transmitter and associated
244 * antenna). EEPROM contains:
245 *
246 * 1) Temperature (degrees Celsius) of device when measurement was made.
247 *
248 * 2) Gain table idx used to achieve the target measurement power.
249 * This refers to the "well-known" gain tables (see 4965.h).
250 *
251 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
252 *
253 * 4) RF power amplifier detector level measurement (not used).
254 */
255 struct il_eeprom_calib_measure {
256 u8 temperature; /* Device temperature (Celsius) */
257 u8 gain_idx; /* Index into gain table */
258 u8 actual_pow; /* Measured RF output power, half-dBm */
259 s8 pa_det; /* Power amp detector level (not used) */
260 } __packed;
261
262 /*
263 * measurement set for one channel. EEPROM contains:
264 *
265 * 1) Channel number measured
266 *
267 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
268 * (a.k.a. "tx chains") (6 measurements altogether)
269 */
270 struct il_eeprom_calib_ch_info {
271 u8 ch_num;
272 struct il_eeprom_calib_measure
273 measurements[EEPROM_TX_POWER_TX_CHAINS]
274 [EEPROM_TX_POWER_MEASUREMENTS];
275 } __packed;
276
277 /*
278 * txpower subband info.
279 *
280 * For each frequency subband, EEPROM contains the following:
281 *
282 * 1) First and last channels within range of the subband. "0" values
283 * indicate that this sample set is not being used.
284 *
285 * 2) Sample measurement sets for 2 channels close to the range endpoints.
286 */
287 struct il_eeprom_calib_subband_info {
288 u8 ch_from; /* channel number of lowest channel in subband */
289 u8 ch_to; /* channel number of highest channel in subband */
290 struct il_eeprom_calib_ch_info ch1;
291 struct il_eeprom_calib_ch_info ch2;
292 } __packed;
293
294 /*
295 * txpower calibration info. EEPROM contains:
296 *
297 * 1) Factory-measured saturation power levels (maximum levels at which
298 * tx power amplifier can output a signal without too much distortion).
299 * There is one level for 2.4 GHz band and one for 5 GHz band. These
300 * values apply to all channels within each of the bands.
301 *
302 * 2) Factory-measured power supply voltage level. This is assumed to be
303 * constant (i.e. same value applies to all channels/bands) while the
304 * factory measurements are being made.
305 *
306 * 3) Up to 8 sets of factory-measured txpower calibration values.
307 * These are for different frequency ranges, since txpower gain
308 * characteristics of the analog radio circuitry vary with frequency.
309 *
310 * Not all sets need to be filled with data;
311 * struct il_eeprom_calib_subband_info contains range of channels
312 * (0 if unused) for each set of data.
313 */
314 struct il_eeprom_calib_info {
315 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
316 u8 saturation_power52; /* half-dBm */
317 __le16 voltage; /* signed */
318 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
319 } __packed;
320
321 /* General */
322 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
323 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
324 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
325 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
326 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
327 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
328 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
329 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
330 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
331 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
332
333 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
334 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
335 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
336 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
337 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
338 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
339 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
340
341 #define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
342 #define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
343
344 /*
345 * Per-channel regulatory data.
346 *
347 * Each channel that *might* be supported by iwl has a fixed location
348 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
349 * txpower (MSB).
350 *
351 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
352 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
353 *
354 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
355 */
356 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
357 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
358 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
359
360 /*
361 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
362 * 5.0 GHz channels 7, 8, 11, 12, 16
363 * (4915-5080MHz) (none of these is ever supported)
364 */
365 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
366 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
367
368 /*
369 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
370 * (5170-5320MHz)
371 */
372 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
373 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
374
375 /*
376 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
377 * (5500-5700MHz)
378 */
379 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
380 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
381
382 /*
383 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
384 * (5725-5825MHz)
385 */
386 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
387 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
388
389 /*
390 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
391 *
392 * The channel listed is the center of the lower 20 MHz half of the channel.
393 * The overall center frequency is actually 2 channels (10 MHz) above that,
394 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
395 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
396 * and the overall HT40 channel width centers on channel 3.
397 *
398 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
399 * control channel to which to tune. RXON also specifies whether the
400 * control channel is the upper or lower half of a HT40 channel.
401 *
402 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
403 */
404 #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
405
406 /*
407 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
408 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
409 */
410 #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
411
412 #define EEPROM_REGULATORY_BAND_NO_HT40 (0)
413
414 int il_eeprom_init(struct il_priv *il);
415 void il_eeprom_free(struct il_priv *il);
416 const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
417 u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
418 int il_init_channel_map(struct il_priv *il);
419 void il_free_channel_map(struct il_priv *il);
420 const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
421 enum nl80211_band band,
422 u16 channel);
423
424 #define IL_NUM_SCAN_RATES (2)
425
426 struct il4965_channel_tgd_info {
427 u8 type;
428 s8 max_power;
429 };
430
431 struct il4965_channel_tgh_info {
432 s64 last_radar_time;
433 };
434
435 #define IL4965_MAX_RATE (33)
436
437 struct il3945_clip_group {
438 /* maximum power level to prevent clipping for each rate, derived by
439 * us from this band's saturation power in EEPROM */
440 const s8 clip_powers[IL_MAX_RATES];
441 };
442
443 /* current Tx power values to use, one for each rate for each channel.
444 * requested power is limited by:
445 * -- regulatory EEPROM limits for this channel
446 * -- hardware capabilities (clip-powers)
447 * -- spectrum management
448 * -- user preference (e.g. iwconfig)
449 * when requested power is set, base power idx must also be set. */
450 struct il3945_channel_power_info {
451 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
452 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
453 s8 base_power_idx; /* gain idx for power at factory temp. */
454 s8 requested_power; /* power (dBm) requested for this chnl/rate */
455 };
456
457 /* current scan Tx power values to use, one for each scan rate for each
458 * channel. */
459 struct il3945_scan_power_info {
460 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
461 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
462 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
463 };
464
465 /*
466 * One for each channel, holds all channel setup data
467 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
468 * with one another!
469 */
470 struct il_channel_info {
471 struct il4965_channel_tgd_info tgd;
472 struct il4965_channel_tgh_info tgh;
473 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
474 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
475 * HT40 channel */
476
477 u8 channel; /* channel number */
478 u8 flags; /* flags copied from EEPROM */
479 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
480 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
481 s8 min_power; /* always 0 */
482 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
483
484 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
485 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
486 enum nl80211_band band;
487
488 /* HT40 channel info */
489 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
490 u8 ht40_flags; /* flags copied from EEPROM */
491 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
492
493 /* Radio/DSP gain settings for each "normal" data Tx rate.
494 * These include, in addition to RF and DSP gain, a few fields for
495 * remembering/modifying gain settings (idxes). */
496 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
497
498 /* Radio/DSP gain settings for each scan rate, for directed scans. */
499 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
500 };
501
502 #define IL_TX_FIFO_BK 0 /* shared */
503 #define IL_TX_FIFO_BE 1
504 #define IL_TX_FIFO_VI 2 /* shared */
505 #define IL_TX_FIFO_VO 3
506 #define IL_TX_FIFO_UNUSED -1
507
508 /* Minimum number of queues. MAX_NUM is defined in hw specific files.
509 * Set the minimum to accommodate the 4 standard TX queues, 1 command
510 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
511 #define IL_MIN_NUM_QUEUES 10
512
513 #define IL_DEFAULT_CMD_QUEUE_NUM 4
514
515 #define IEEE80211_DATA_LEN 2304
516 #define IEEE80211_4ADDR_LEN 30
517 #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
518 #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
519
520 struct il_frame {
521 union {
522 struct ieee80211_hdr frame;
523 struct il_tx_beacon_cmd beacon;
524 u8 raw[IEEE80211_FRAME_LEN];
525 u8 cmd[360];
526 } u;
527 struct list_head list;
528 };
529
530 enum {
531 CMD_SYNC = 0,
532 CMD_SIZE_NORMAL = 0,
533 CMD_NO_SKB = 0,
534 CMD_SIZE_HUGE = (1 << 0),
535 CMD_ASYNC = (1 << 1),
536 CMD_WANT_SKB = (1 << 2),
537 CMD_MAPPED = (1 << 3),
538 };
539
540 #define DEF_CMD_PAYLOAD_SIZE 320
541
542 /**
543 * struct il_device_cmd
544 *
545 * For allocation of the command and tx queues, this establishes the overall
546 * size of the largest command we send to uCode, except for a scan command
547 * (which is relatively huge; space is allocated separately).
548 */
549 struct il_device_cmd {
550 struct il_cmd_header hdr; /* uCode API */
551 union {
552 u32 flags;
553 u8 val8;
554 u16 val16;
555 u32 val32;
556 struct il_tx_cmd_hdr tx;
557 u8 payload[DEF_CMD_PAYLOAD_SIZE];
558 } __packed cmd;
559 } __packed;
560
561 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
562
563 /**
564 * struct il_device_cmd_huge
565 *
566 * For use when sending huge commands.
567 */
568 struct il_device_cmd_huge {
569 struct il_cmd_header hdr; /* uCode API */
570 union {
571 u8 payload[IL_MAX_CMD_SIZE - sizeof(struct il_cmd_header)];
572 } __packed cmd;
573 } __packed;
574
575 struct il_host_cmd {
576 const void *data;
577 unsigned long reply_page;
578 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
579 struct il_rx_pkt *pkt);
580 u32 flags;
581 u16 len;
582 u8 id;
583 };
584
585 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
586 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
587 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
588
589 /**
590 * struct il_rx_queue - Rx queue
591 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
592 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
593 * @read: Shared idx to newest available Rx buffer
594 * @write: Shared idx to oldest written Rx packet
595 * @free_count: Number of pre-allocated buffers in rx_free
596 * @rx_free: list of free SKBs for use
597 * @rx_used: List of Rx buffers with no SKB
598 * @need_update: flag to indicate we need to update read/write idx
599 * @rb_stts: driver's pointer to receive buffer status
600 * @rb_stts_dma: bus address of receive buffer status
601 *
602 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
603 */
604 struct il_rx_queue {
605 __le32 *bd;
606 dma_addr_t bd_dma;
607 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
608 struct il_rx_buf *queue[RX_QUEUE_SIZE];
609 u32 read;
610 u32 write;
611 u32 free_count;
612 u32 write_actual;
613 struct list_head rx_free;
614 struct list_head rx_used;
615 int need_update;
616 struct il_rb_status *rb_stts;
617 dma_addr_t rb_stts_dma;
618 spinlock_t lock;
619 };
620
621 #define IL_SUPPORTED_RATES_IE_LEN 8
622
623 #define MAX_TID_COUNT 9
624
625 #define IL_INVALID_RATE 0xFF
626 #define IL_INVALID_VALUE -1
627
628 /**
629 * struct il_ht_agg -- aggregation status while waiting for block-ack
630 * @txq_id: Tx queue used for Tx attempt
631 * @frame_count: # frames attempted by Tx command
632 * @wait_for_ba: Expect block-ack before next Tx reply
633 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
634 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
635 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
636 * @rate_n_flags: Rate at which Tx was attempted
637 *
638 * If C_TX indicates that aggregation was attempted, driver must wait
639 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
640 * until block ack arrives.
641 */
642 struct il_ht_agg {
643 u16 txq_id;
644 u16 frame_count;
645 u16 wait_for_ba;
646 u16 start_idx;
647 u64 bitmap;
648 u32 rate_n_flags;
649 #define IL_AGG_OFF 0
650 #define IL_AGG_ON 1
651 #define IL_EMPTYING_HW_QUEUE_ADDBA 2
652 #define IL_EMPTYING_HW_QUEUE_DELBA 3
653 u8 state;
654 };
655
656 struct il_tid_data {
657 u16 seq_number; /* 4965 only */
658 u16 tfds_in_queue;
659 struct il_ht_agg agg;
660 };
661
662 struct il_hw_key {
663 u32 cipher;
664 int keylen;
665 u8 keyidx;
666 u8 key[32];
667 };
668
669 union il_ht_rate_supp {
670 u16 rates;
671 struct {
672 u8 siso_rate;
673 u8 mimo_rate;
674 };
675 };
676
677 #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
678 #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
679 #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
680 #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
681 #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
682 #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
683 #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
684
685 /*
686 * Maximal MPDU density for TX aggregation
687 * 4 - 2us density
688 * 5 - 4us density
689 * 6 - 8us density
690 * 7 - 16us density
691 */
692 #define CFG_HT_MPDU_DENSITY_2USEC (0x4)
693 #define CFG_HT_MPDU_DENSITY_4USEC (0x5)
694 #define CFG_HT_MPDU_DENSITY_8USEC (0x6)
695 #define CFG_HT_MPDU_DENSITY_16USEC (0x7)
696 #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
697 #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
698 #define CFG_HT_MPDU_DENSITY_MIN (0x1)
699
700 struct il_ht_config {
701 bool single_chain_sufficient;
702 enum ieee80211_smps_mode smps; /* current smps mode */
703 };
704
705 /* QoS structures */
706 struct il_qos_info {
707 int qos_active;
708 struct il_qosparam_cmd def_qos_parm;
709 };
710
711 /*
712 * Structure should be accessed with sta_lock held. When station addition
713 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
714 * the commands (il_addsta_cmd and il_link_quality_cmd) without
715 * sta_lock held.
716 */
717 struct il_station_entry {
718 struct il_addsta_cmd sta;
719 struct il_tid_data tid[MAX_TID_COUNT];
720 u8 used;
721 struct il_hw_key keyinfo;
722 struct il_link_quality_cmd *lq;
723 };
724
725 struct il_station_priv_common {
726 u8 sta_id;
727 };
728
729 /**
730 * struct il_vif_priv - driver's ilate per-interface information
731 *
732 * When mac80211 allocates a virtual interface, it can allocate
733 * space for us to put data into.
734 */
735 struct il_vif_priv {
736 u8 ibss_bssid_sta_id;
737 };
738
739 /* one for each uCode image (inst/data, boot/init/runtime) */
740 struct fw_desc {
741 void *v_addr; /* access by driver */
742 dma_addr_t p_addr; /* access by card's busmaster DMA */
743 u32 len; /* bytes */
744 };
745
746 /* uCode file layout */
747 struct il_ucode_header {
748 __le32 ver; /* major/minor/API/serial */
749 struct {
750 __le32 inst_size; /* bytes of runtime code */
751 __le32 data_size; /* bytes of runtime data */
752 __le32 init_size; /* bytes of init code */
753 __le32 init_data_size; /* bytes of init data */
754 __le32 boot_size; /* bytes of bootstrap code */
755 u8 data[0]; /* in same order as sizes */
756 } v1;
757 };
758
759 struct il4965_ibss_seq {
760 u8 mac[ETH_ALEN];
761 u16 seq_num;
762 u16 frag_num;
763 unsigned long packet_time;
764 struct list_head list;
765 };
766
767 struct il_sensitivity_ranges {
768 u16 min_nrg_cck;
769 u16 max_nrg_cck;
770
771 u16 nrg_th_cck;
772 u16 nrg_th_ofdm;
773
774 u16 auto_corr_min_ofdm;
775 u16 auto_corr_min_ofdm_mrc;
776 u16 auto_corr_min_ofdm_x1;
777 u16 auto_corr_min_ofdm_mrc_x1;
778
779 u16 auto_corr_max_ofdm;
780 u16 auto_corr_max_ofdm_mrc;
781 u16 auto_corr_max_ofdm_x1;
782 u16 auto_corr_max_ofdm_mrc_x1;
783
784 u16 auto_corr_max_cck;
785 u16 auto_corr_max_cck_mrc;
786 u16 auto_corr_min_cck;
787 u16 auto_corr_min_cck_mrc;
788
789 u16 barker_corr_th_min;
790 u16 barker_corr_th_min_mrc;
791 u16 nrg_th_cca;
792 };
793
794 /**
795 * struct il_hw_params
796 * @bcast_id: f/w broadcast station ID
797 * @max_txq_num: Max # Tx queues supported
798 * @dma_chnl_num: Number of Tx DMA/FIFO channels
799 * @scd_bc_tbls_size: size of scheduler byte count tables
800 * @tfd_size: TFD size
801 * @tx/rx_chains_num: Number of TX/RX chains
802 * @valid_tx/rx_ant: usable antennas
803 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
804 * @max_rxq_log: Log-base-2 of max_rxq_size
805 * @rx_page_order: Rx buffer page order
806 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
807 * @max_stations:
808 * @ht40_channel: is 40MHz width possible in band 2.4
809 * BIT(NL80211_BAND_5GHZ) BIT(NL80211_BAND_5GHZ)
810 * @sw_crypto: 0 for hw, 1 for sw
811 * @max_xxx_size: for ucode uses
812 * @ct_kill_threshold: temperature threshold
813 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
814 * @struct il_sensitivity_ranges: range of sensitivity values
815 */
816 struct il_hw_params {
817 u8 bcast_id;
818 u8 max_txq_num;
819 u8 dma_chnl_num;
820 u16 scd_bc_tbls_size;
821 u32 tfd_size;
822 u8 tx_chains_num;
823 u8 rx_chains_num;
824 u8 valid_tx_ant;
825 u8 valid_rx_ant;
826 u16 max_rxq_size;
827 u16 max_rxq_log;
828 u32 rx_page_order;
829 u32 rx_wrt_ptr_reg;
830 u8 max_stations;
831 u8 ht40_channel;
832 u8 max_beacon_itrvl; /* in 1024 ms */
833 u32 max_inst_size;
834 u32 max_data_size;
835 u32 max_bsm_size;
836 u32 ct_kill_threshold; /* value in hw-dependent units */
837 u16 beacon_time_tsf_bits;
838 const struct il_sensitivity_ranges *sens;
839 };
840
841 /******************************************************************************
842 *
843 * Functions implemented in core module which are forward declared here
844 * for use by iwl-[4-5].c
845 *
846 * NOTE: The implementation of these functions are not hardware specific
847 * which is why they are in the core module files.
848 *
849 * Naming convention --
850 * il_ <-- Is part of iwlwifi
851 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
852 * il4965_bg_ <-- Called from work queue context
853 * il4965_mac_ <-- mac80211 callback
854 *
855 ****************************************************************************/
856 void il4965_update_chain_flags(struct il_priv *il);
857 extern const u8 il_bcast_addr[ETH_ALEN];
858 int il_queue_space(const struct il_queue *q);
859 static inline int
il_queue_used(const struct il_queue * q,int i)860 il_queue_used(const struct il_queue *q, int i)
861 {
862 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
863 i < q->write_ptr) : !(i <
864 q->read_ptr
865 && i >=
866 q->
867 write_ptr);
868 }
869
870 static inline u8
il_get_cmd_idx(struct il_queue * q,u32 idx,int is_huge)871 il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
872 {
873 /*
874 * This is for init calibration result and scan command which
875 * required buffer > TFD_MAX_PAYLOAD_SIZE,
876 * the big buffer at end of command array
877 */
878 if (is_huge)
879 return q->n_win; /* must be power of 2 */
880
881 /* Otherwise, use normal size buffers */
882 return idx & (q->n_win - 1);
883 }
884
885 struct il_dma_ptr {
886 dma_addr_t dma;
887 void *addr;
888 size_t size;
889 };
890
891 #define IL_OPERATION_MODE_AUTO 0
892 #define IL_OPERATION_MODE_HT_ONLY 1
893 #define IL_OPERATION_MODE_MIXED 2
894 #define IL_OPERATION_MODE_20MHZ 3
895
896 #define IL_TX_CRC_SIZE 4
897 #define IL_TX_DELIMITER_SIZE 4
898
899 #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
900
901 /* Sensitivity and chain noise calibration */
902 #define INITIALIZATION_VALUE 0xFFFF
903 #define IL4965_CAL_NUM_BEACONS 20
904 #define IL_CAL_NUM_BEACONS 16
905 #define MAXIMUM_ALLOWED_PATHLOSS 15
906
907 #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
908
909 #define MAX_FA_OFDM 50
910 #define MIN_FA_OFDM 5
911 #define MAX_FA_CCK 50
912 #define MIN_FA_CCK 5
913
914 #define AUTO_CORR_STEP_OFDM 1
915
916 #define AUTO_CORR_STEP_CCK 3
917 #define AUTO_CORR_MAX_TH_CCK 160
918
919 #define NRG_DIFF 2
920 #define NRG_STEP_CCK 2
921 #define NRG_MARGIN 8
922 #define MAX_NUMBER_CCK_NO_FA 100
923
924 #define AUTO_CORR_CCK_MIN_VAL_DEF (125)
925
926 #define CHAIN_A 0
927 #define CHAIN_B 1
928 #define CHAIN_C 2
929 #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
930 #define ALL_BAND_FILTER 0xFF00
931 #define IN_BAND_FILTER 0xFF
932 #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
933
934 #define NRG_NUM_PREV_STAT_L 20
935 #define NUM_RX_CHAINS 3
936
937 enum il4965_false_alarm_state {
938 IL_FA_TOO_MANY = 0,
939 IL_FA_TOO_FEW = 1,
940 IL_FA_GOOD_RANGE = 2,
941 };
942
943 enum il4965_chain_noise_state {
944 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
945 IL_CHAIN_NOISE_ACCUMULATE,
946 IL_CHAIN_NOISE_CALIBRATED,
947 IL_CHAIN_NOISE_DONE,
948 };
949
950 enum ucode_type {
951 UCODE_NONE = 0,
952 UCODE_INIT,
953 UCODE_RT
954 };
955
956 /* Sensitivity calib data */
957 struct il_sensitivity_data {
958 u32 auto_corr_ofdm;
959 u32 auto_corr_ofdm_mrc;
960 u32 auto_corr_ofdm_x1;
961 u32 auto_corr_ofdm_mrc_x1;
962 u32 auto_corr_cck;
963 u32 auto_corr_cck_mrc;
964
965 u32 last_bad_plcp_cnt_ofdm;
966 u32 last_fa_cnt_ofdm;
967 u32 last_bad_plcp_cnt_cck;
968 u32 last_fa_cnt_cck;
969
970 u32 nrg_curr_state;
971 u32 nrg_prev_state;
972 u32 nrg_value[10];
973 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
974 u32 nrg_silence_ref;
975 u32 nrg_energy_idx;
976 u32 nrg_silence_idx;
977 u32 nrg_th_cck;
978 s32 nrg_auto_corr_silence_diff;
979 u32 num_in_cck_no_fa;
980 u32 nrg_th_ofdm;
981
982 u16 barker_corr_th_min;
983 u16 barker_corr_th_min_mrc;
984 u16 nrg_th_cca;
985 };
986
987 /* Chain noise (differential Rx gain) calib data */
988 struct il_chain_noise_data {
989 u32 active_chains;
990 u32 chain_noise_a;
991 u32 chain_noise_b;
992 u32 chain_noise_c;
993 u32 chain_signal_a;
994 u32 chain_signal_b;
995 u32 chain_signal_c;
996 u16 beacon_count;
997 u8 disconn_array[NUM_RX_CHAINS];
998 u8 delta_gain_code[NUM_RX_CHAINS];
999 u8 radio_write;
1000 u8 state;
1001 };
1002
1003 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
1004 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1005
1006 #define IL_TRAFFIC_ENTRIES (256)
1007 #define IL_TRAFFIC_ENTRY_SIZE (64)
1008
1009 enum {
1010 MEASUREMENT_READY = (1 << 0),
1011 MEASUREMENT_ACTIVE = (1 << 1),
1012 };
1013
1014 /* interrupt stats */
1015 struct isr_stats {
1016 u32 hw;
1017 u32 sw;
1018 u32 err_code;
1019 u32 sch;
1020 u32 alive;
1021 u32 rfkill;
1022 u32 ctkill;
1023 u32 wakeup;
1024 u32 rx;
1025 u32 handlers[IL_CN_MAX];
1026 u32 tx;
1027 u32 unhandled;
1028 };
1029
1030 /* management stats */
1031 enum il_mgmt_stats {
1032 MANAGEMENT_ASSOC_REQ = 0,
1033 MANAGEMENT_ASSOC_RESP,
1034 MANAGEMENT_REASSOC_REQ,
1035 MANAGEMENT_REASSOC_RESP,
1036 MANAGEMENT_PROBE_REQ,
1037 MANAGEMENT_PROBE_RESP,
1038 MANAGEMENT_BEACON,
1039 MANAGEMENT_ATIM,
1040 MANAGEMENT_DISASSOC,
1041 MANAGEMENT_AUTH,
1042 MANAGEMENT_DEAUTH,
1043 MANAGEMENT_ACTION,
1044 MANAGEMENT_MAX,
1045 };
1046 /* control stats */
1047 enum il_ctrl_stats {
1048 CONTROL_BACK_REQ = 0,
1049 CONTROL_BACK,
1050 CONTROL_PSPOLL,
1051 CONTROL_RTS,
1052 CONTROL_CTS,
1053 CONTROL_ACK,
1054 CONTROL_CFEND,
1055 CONTROL_CFENDACK,
1056 CONTROL_MAX,
1057 };
1058
1059 struct traffic_stats {
1060 #ifdef CONFIG_IWLEGACY_DEBUGFS
1061 u32 mgmt[MANAGEMENT_MAX];
1062 u32 ctrl[CONTROL_MAX];
1063 u32 data_cnt;
1064 u64 data_bytes;
1065 #endif
1066 };
1067
1068 /*
1069 * host interrupt timeout value
1070 * used with setting interrupt coalescing timer
1071 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1072 *
1073 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1074 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1075 */
1076 #define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1077 #define IL_HOST_INT_TIMEOUT_DEF (0x40)
1078 #define IL_HOST_INT_TIMEOUT_MIN (0x0)
1079 #define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1080 #define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1081 #define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1082
1083 #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1084
1085 /* TX queue watchdog timeouts in mSecs */
1086 #define IL_DEF_WD_TIMEOUT (2000)
1087 #define IL_LONG_WD_TIMEOUT (10000)
1088 #define IL_MAX_WD_TIMEOUT (120000)
1089
1090 struct il_force_reset {
1091 int reset_request_count;
1092 int reset_success_count;
1093 int reset_reject_count;
1094 unsigned long reset_duration;
1095 unsigned long last_force_reset_jiffies;
1096 };
1097
1098 /* extend beacon time format bit shifting */
1099 /*
1100 * for _3945 devices
1101 * bits 31:24 - extended
1102 * bits 23:0 - interval
1103 */
1104 #define IL3945_EXT_BEACON_TIME_POS 24
1105 /*
1106 * for _4965 devices
1107 * bits 31:22 - extended
1108 * bits 21:0 - interval
1109 */
1110 #define IL4965_EXT_BEACON_TIME_POS 22
1111
1112 struct il_rxon_context {
1113 struct ieee80211_vif *vif;
1114 };
1115
1116 struct il_power_mgr {
1117 struct il_powertable_cmd sleep_cmd;
1118 struct il_powertable_cmd sleep_cmd_next;
1119 int debug_sleep_level_override;
1120 bool pci_pm;
1121 bool ps_disabled;
1122 };
1123
1124 struct il_priv {
1125 struct ieee80211_hw *hw;
1126 struct ieee80211_channel *ieee_channels;
1127 struct ieee80211_rate *ieee_rates;
1128
1129 struct il_cfg *cfg;
1130 const struct il_ops *ops;
1131 #ifdef CONFIG_IWLEGACY_DEBUGFS
1132 const struct il_debugfs_ops *debugfs_ops;
1133 #endif
1134
1135 /* temporary frame storage list */
1136 struct list_head free_frames;
1137 int frames_count;
1138
1139 enum nl80211_band band;
1140 int alloc_rxb_page;
1141
1142 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1143 struct il_rx_buf *rxb);
1144
1145 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1146
1147 /* spectrum measurement report caching */
1148 struct il_spectrum_notification measure_report;
1149 u8 measurement_status;
1150
1151 /* ucode beacon time */
1152 u32 ucode_beacon_time;
1153 int missed_beacon_threshold;
1154
1155 /* track IBSS manager (last beacon) status */
1156 u32 ibss_manager;
1157
1158 /* force reset */
1159 struct il_force_reset force_reset;
1160
1161 /* we allocate array of il_channel_info for NIC's valid channels.
1162 * Access via channel # using indirect idx array */
1163 struct il_channel_info *channel_info; /* channel info array */
1164 u8 channel_count; /* # of channels */
1165
1166 /* thermal calibration */
1167 s32 temperature; /* degrees Kelvin */
1168 s32 last_temperature;
1169
1170 /* Scan related variables */
1171 unsigned long scan_start;
1172 unsigned long scan_start_tsf;
1173 void *scan_cmd;
1174 enum nl80211_band scan_band;
1175 struct cfg80211_scan_request *scan_request;
1176 struct ieee80211_vif *scan_vif;
1177 u8 scan_tx_ant[NUM_NL80211_BANDS];
1178 u8 mgmt_tx_ant;
1179
1180 /* spinlock */
1181 spinlock_t lock; /* protect general shared data */
1182 spinlock_t hcmd_lock; /* protect hcmd */
1183 spinlock_t reg_lock; /* protect hw register access */
1184 struct mutex mutex;
1185
1186 /* basic pci-network driver stuff */
1187 struct pci_dev *pci_dev;
1188
1189 /* pci hardware address support */
1190 void __iomem *hw_base;
1191 u32 hw_rev;
1192 u32 hw_wa_rev;
1193 u8 rev_id;
1194
1195 /* command queue number */
1196 u8 cmd_queue;
1197
1198 /* max number of station keys */
1199 u8 sta_key_max_num;
1200
1201 /* EEPROM MAC addresses */
1202 struct mac_address addresses[1];
1203
1204 /* uCode images, save to reload in case of failure */
1205 int fw_idx; /* firmware we're trying to load */
1206 u32 ucode_ver; /* version of ucode, copy of
1207 il_ucode.ver */
1208 struct fw_desc ucode_code; /* runtime inst */
1209 struct fw_desc ucode_data; /* runtime data original */
1210 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1211 struct fw_desc ucode_init; /* initialization inst */
1212 struct fw_desc ucode_init_data; /* initialization data */
1213 struct fw_desc ucode_boot; /* bootstrap inst */
1214 enum ucode_type ucode_type;
1215 u8 ucode_write_complete; /* the image write is complete */
1216 char firmware_name[25];
1217
1218 struct ieee80211_vif *vif;
1219
1220 struct il_qos_info qos_data;
1221
1222 struct {
1223 bool enabled;
1224 bool is_40mhz;
1225 bool non_gf_sta_present;
1226 u8 protection;
1227 u8 extension_chan_offset;
1228 } ht;
1229
1230 /*
1231 * We declare this const so it can only be
1232 * changed via explicit cast within the
1233 * routines that actually update the physical
1234 * hardware.
1235 */
1236 const struct il_rxon_cmd active;
1237 struct il_rxon_cmd staging;
1238
1239 struct il_rxon_time_cmd timing;
1240
1241 __le16 switch_channel;
1242
1243 /* 1st responses from initialize and runtime uCode images.
1244 * _4965's initialize alive response contains some calibration data. */
1245 struct il_init_alive_resp card_alive_init;
1246 struct il_alive_resp card_alive;
1247
1248 u16 active_rate;
1249
1250 u8 start_calib;
1251 struct il_sensitivity_data sensitivity_data;
1252 struct il_chain_noise_data chain_noise_data;
1253 __le16 sensitivity_tbl[HD_TBL_SIZE];
1254
1255 struct il_ht_config current_ht_config;
1256
1257 /* Rate scaling data */
1258 u8 retry_rate;
1259
1260 wait_queue_head_t wait_command_queue;
1261
1262 int activity_timer_active;
1263
1264 /* Rx and Tx DMA processing queues */
1265 struct il_rx_queue rxq;
1266 struct il_tx_queue *txq;
1267 unsigned long txq_ctx_active_msk;
1268 struct il_dma_ptr kw; /* keep warm address */
1269 struct il_dma_ptr scd_bc_tbls;
1270
1271 u32 scd_base_addr; /* scheduler sram base address */
1272
1273 unsigned long status;
1274
1275 /* counts mgmt, ctl, and data packets */
1276 struct traffic_stats tx_stats;
1277 struct traffic_stats rx_stats;
1278
1279 /* counts interrupts */
1280 struct isr_stats isr_stats;
1281
1282 struct il_power_mgr power_data;
1283
1284 /* context information */
1285 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
1286
1287 /* station table variables */
1288
1289 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1290 spinlock_t sta_lock;
1291 int num_stations;
1292 struct il_station_entry stations[IL_STATION_COUNT];
1293 unsigned long ucode_key_table;
1294
1295 /* queue refcounts */
1296 #define IL_MAX_HW_QUEUES 32
1297 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1298 #define IL_STOP_REASON_PASSIVE 0
1299 unsigned long stop_reason;
1300 /* for each AC */
1301 atomic_t queue_stop_count[4];
1302
1303 /* Indication if ieee80211_ops->open has been called */
1304 u8 is_open;
1305
1306 u8 mac80211_registered;
1307
1308 /* eeprom -- this is in the card's little endian byte order */
1309 u8 *eeprom;
1310 struct il_eeprom_calib_info *calib_info;
1311
1312 enum nl80211_iftype iw_mode;
1313
1314 /* Last Rx'd beacon timestamp */
1315 u64 timestamp;
1316
1317 union {
1318 #if IS_ENABLED(CONFIG_IWL3945)
1319 struct {
1320 void *shared_virt;
1321 dma_addr_t shared_phys;
1322
1323 struct delayed_work thermal_periodic;
1324 struct delayed_work rfkill_poll;
1325
1326 struct il3945_notif_stats stats;
1327 #ifdef CONFIG_IWLEGACY_DEBUGFS
1328 struct il3945_notif_stats accum_stats;
1329 struct il3945_notif_stats delta_stats;
1330 struct il3945_notif_stats max_delta;
1331 #endif
1332
1333 u32 sta_supp_rates;
1334 int last_rx_rssi; /* From Rx packet stats */
1335
1336 /* Rx'd packet timing information */
1337 u32 last_beacon_time;
1338 u64 last_tsf;
1339
1340 /*
1341 * each calibration channel group in the
1342 * EEPROM has a derived clip setting for
1343 * each rate.
1344 */
1345 const struct il3945_clip_group clip_groups[5];
1346
1347 } _3945;
1348 #endif
1349 #if IS_ENABLED(CONFIG_IWL4965)
1350 struct {
1351 struct il_rx_phy_res last_phy_res;
1352 bool last_phy_res_valid;
1353 u32 ampdu_ref;
1354
1355 struct completion firmware_loading_complete;
1356
1357 /*
1358 * chain noise reset and gain commands are the
1359 * two extra calibration commands follows the standard
1360 * phy calibration commands
1361 */
1362 u8 phy_calib_chain_noise_reset_cmd;
1363 u8 phy_calib_chain_noise_gain_cmd;
1364
1365 u8 key_mapping_keys;
1366 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1367
1368 struct il_notif_stats stats;
1369 #ifdef CONFIG_IWLEGACY_DEBUGFS
1370 struct il_notif_stats accum_stats;
1371 struct il_notif_stats delta_stats;
1372 struct il_notif_stats max_delta;
1373 #endif
1374
1375 } _4965;
1376 #endif
1377 };
1378
1379 struct il_hw_params hw_params;
1380
1381 u32 inta_mask;
1382
1383 struct workqueue_struct *workqueue;
1384
1385 struct work_struct restart;
1386 struct work_struct scan_completed;
1387 struct work_struct rx_replenish;
1388 struct work_struct abort_scan;
1389
1390 bool beacon_enabled;
1391 struct sk_buff *beacon_skb;
1392
1393 struct work_struct tx_flush;
1394
1395 struct tasklet_struct irq_tasklet;
1396
1397 struct delayed_work init_alive_start;
1398 struct delayed_work alive_start;
1399 struct delayed_work scan_check;
1400
1401 /* TX Power */
1402 s8 tx_power_user_lmt;
1403 s8 tx_power_device_lmt;
1404 s8 tx_power_next;
1405
1406 #ifdef CONFIG_IWLEGACY_DEBUG
1407 /* debugging info */
1408 u32 debug_level; /* per device debugging will override global
1409 il_debug_level if set */
1410 #endif /* CONFIG_IWLEGACY_DEBUG */
1411 #ifdef CONFIG_IWLEGACY_DEBUGFS
1412 /* debugfs */
1413 u16 tx_traffic_idx;
1414 u16 rx_traffic_idx;
1415 u8 *tx_traffic;
1416 u8 *rx_traffic;
1417 struct dentry *debugfs_dir;
1418 u32 dbgfs_sram_offset, dbgfs_sram_len;
1419 bool disable_ht40;
1420 #endif /* CONFIG_IWLEGACY_DEBUGFS */
1421
1422 struct work_struct txpower_work;
1423 bool disable_sens_cal;
1424 bool disable_chain_noise_cal;
1425 bool disable_tx_power_cal;
1426 struct work_struct run_time_calib_work;
1427 struct timer_list stats_periodic;
1428 struct timer_list watchdog;
1429 bool hw_ready;
1430
1431 struct led_classdev led;
1432 unsigned long blink_on, blink_off;
1433 bool led_registered;
1434 }; /*il_priv */
1435
1436 static inline void
il_txq_ctx_activate(struct il_priv * il,int txq_id)1437 il_txq_ctx_activate(struct il_priv *il, int txq_id)
1438 {
1439 set_bit(txq_id, &il->txq_ctx_active_msk);
1440 }
1441
1442 static inline void
il_txq_ctx_deactivate(struct il_priv * il,int txq_id)1443 il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1444 {
1445 clear_bit(txq_id, &il->txq_ctx_active_msk);
1446 }
1447
1448 static inline int
il_is_associated(struct il_priv * il)1449 il_is_associated(struct il_priv *il)
1450 {
1451 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1452 }
1453
1454 static inline int
il_is_any_associated(struct il_priv * il)1455 il_is_any_associated(struct il_priv *il)
1456 {
1457 return il_is_associated(il);
1458 }
1459
1460 static inline int
il_is_channel_valid(const struct il_channel_info * ch_info)1461 il_is_channel_valid(const struct il_channel_info *ch_info)
1462 {
1463 if (ch_info == NULL)
1464 return 0;
1465 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1466 }
1467
1468 static inline int
il_is_channel_radar(const struct il_channel_info * ch_info)1469 il_is_channel_radar(const struct il_channel_info *ch_info)
1470 {
1471 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1472 }
1473
1474 static inline u8
il_is_channel_a_band(const struct il_channel_info * ch_info)1475 il_is_channel_a_band(const struct il_channel_info *ch_info)
1476 {
1477 return ch_info->band == NL80211_BAND_5GHZ;
1478 }
1479
1480 static inline int
il_is_channel_passive(const struct il_channel_info * ch)1481 il_is_channel_passive(const struct il_channel_info *ch)
1482 {
1483 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1484 }
1485
1486 static inline int
il_is_channel_ibss(const struct il_channel_info * ch)1487 il_is_channel_ibss(const struct il_channel_info *ch)
1488 {
1489 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1490 }
1491
1492 static inline void
__il_free_pages(struct il_priv * il,struct page * page)1493 __il_free_pages(struct il_priv *il, struct page *page)
1494 {
1495 __free_pages(page, il->hw_params.rx_page_order);
1496 il->alloc_rxb_page--;
1497 }
1498
1499 static inline void
il_free_pages(struct il_priv * il,unsigned long page)1500 il_free_pages(struct il_priv *il, unsigned long page)
1501 {
1502 free_pages(page, il->hw_params.rx_page_order);
1503 il->alloc_rxb_page--;
1504 }
1505
1506 #define IWLWIFI_VERSION "in-tree:"
1507 #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1508 #define DRV_AUTHOR "<ilw@linux.intel.com>"
1509
1510 #define IL_PCI_DEVICE(dev, subdev, cfg) \
1511 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1512 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1513 .driver_data = (kernel_ulong_t)&(cfg)
1514
1515 #define TIME_UNIT 1024
1516
1517 #define IL_SKU_G 0x1
1518 #define IL_SKU_A 0x2
1519 #define IL_SKU_N 0x8
1520
1521 #define IL_CMD(x) case x: return #x
1522
1523 /* Size of one Rx buffer in host DRAM */
1524 #define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
1525 #define IL_RX_BUF_SIZE_4K (4 * 1024)
1526 #define IL_RX_BUF_SIZE_8K (8 * 1024)
1527
1528 #ifdef CONFIG_IWLEGACY_DEBUGFS
1529 struct il_debugfs_ops {
1530 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1531 size_t count, loff_t *ppos);
1532 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1533 size_t count, loff_t *ppos);
1534 ssize_t(*general_stats_read) (struct file *file,
1535 char __user *user_buf, size_t count,
1536 loff_t *ppos);
1537 };
1538 #endif
1539
1540 struct il_ops {
1541 /* Handling TX */
1542 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1543 struct il_tx_queue *txq,
1544 u16 byte_cnt);
1545 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1546 struct il_tx_queue *txq, dma_addr_t addr,
1547 u16 len, u8 reset, u8 pad);
1548 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1549 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1550 /* alive notification after init uCode load */
1551 void (*init_alive_start) (struct il_priv *il);
1552 /* check validity of rtc data address */
1553 int (*is_valid_rtc_data_addr) (u32 addr);
1554 /* 1st ucode load */
1555 int (*load_ucode) (struct il_priv *il);
1556
1557 void (*dump_nic_error_log) (struct il_priv *il);
1558 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1559 int (*set_channel_switch) (struct il_priv *il,
1560 struct ieee80211_channel_switch *ch_switch);
1561 /* power management */
1562 int (*apm_init) (struct il_priv *il);
1563
1564 /* tx power */
1565 int (*send_tx_power) (struct il_priv *il);
1566 void (*update_chain_flags) (struct il_priv *il);
1567
1568 /* eeprom operations */
1569 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1570 void (*eeprom_release_semaphore) (struct il_priv *il);
1571
1572 int (*rxon_assoc) (struct il_priv *il);
1573 int (*commit_rxon) (struct il_priv *il);
1574 void (*set_rxon_chain) (struct il_priv *il);
1575
1576 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1577 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1578
1579 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1580 void (*post_scan) (struct il_priv *il);
1581 void (*post_associate) (struct il_priv *il);
1582 void (*config_ap) (struct il_priv *il);
1583 /* station management */
1584 int (*update_bcast_stations) (struct il_priv *il);
1585 int (*manage_ibss_station) (struct il_priv *il,
1586 struct ieee80211_vif *vif, bool add);
1587
1588 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1589 };
1590
1591 struct il_mod_params {
1592 int sw_crypto; /* def: 0 = using hardware encryption */
1593 int disable_hw_scan; /* def: 0 = use h/w scan */
1594 int num_of_queues; /* def: HW dependent */
1595 int disable_11n; /* def: 0 = 11n capabilities enabled */
1596 int amsdu_size_8K; /* def: 0 = disable 8K amsdu size */
1597 int antenna; /* def: 0 = both antennas (use diversity) */
1598 int restart_fw; /* def: 1 = restart firmware */
1599 };
1600
1601 #define IL_LED_SOLID 11
1602 #define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1603
1604 #define IL_LED_ACTIVITY (0<<1)
1605 #define IL_LED_LINK (1<<1)
1606
1607 /*
1608 * LED mode
1609 * IL_LED_DEFAULT: use device default
1610 * IL_LED_RF_STATE: turn LED on/off based on RF state
1611 * LED ON = RF ON
1612 * LED OFF = RF OFF
1613 * IL_LED_BLINK: adjust led blink rate based on blink table
1614 */
1615 enum il_led_mode {
1616 IL_LED_DEFAULT,
1617 IL_LED_RF_STATE,
1618 IL_LED_BLINK,
1619 };
1620
1621 void il_leds_init(struct il_priv *il);
1622 void il_leds_exit(struct il_priv *il);
1623
1624 /**
1625 * struct il_cfg
1626 * @fw_name_pre: Firmware filename prefix. The api version and extension
1627 * (.ucode) will be added to filename before loading from disk. The
1628 * filename is constructed as fw_name_pre<api>.ucode.
1629 * @ucode_api_max: Highest version of uCode API supported by driver.
1630 * @ucode_api_min: Lowest version of uCode API supported by driver.
1631 * @scan_antennas: available antenna for scan operation
1632 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1633 *
1634 * We enable the driver to be backward compatible wrt API version. The
1635 * driver specifies which APIs it supports (with @ucode_api_max being the
1636 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1637 * it has a supported API version. The firmware's API version will be
1638 * stored in @il_priv, enabling the driver to make runtime changes based
1639 * on firmware version used.
1640 *
1641 * For example,
1642 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
1643 * Driver interacts with Firmware API version >= 2.
1644 * } else {
1645 * Driver interacts with Firmware API version 1.
1646 * }
1647 *
1648 * The ideal usage of this infrastructure is to treat a new ucode API
1649 * release as a new hardware revision. That is, through utilizing the
1650 * il_hcmd_utils_ops etc. we accommodate different command structures
1651 * and flows between hardware versions as well as their API
1652 * versions.
1653 *
1654 */
1655 struct il_cfg {
1656 /* params specific to an individual device within a device family */
1657 const char *name;
1658 const char *fw_name_pre;
1659 const unsigned int ucode_api_max;
1660 const unsigned int ucode_api_min;
1661 u8 valid_tx_ant;
1662 u8 valid_rx_ant;
1663 unsigned int sku;
1664 u16 eeprom_ver;
1665 u16 eeprom_calib_ver;
1666 /* module based parameters which can be set from modprobe cmd */
1667 const struct il_mod_params *mod_params;
1668 /* params not likely to change within a device family */
1669 struct il_base_params *base_params;
1670 /* params likely to change within a device family */
1671 u8 scan_rx_antennas[NUM_NL80211_BANDS];
1672 enum il_led_mode led_mode;
1673
1674 int eeprom_size;
1675 int num_of_queues; /* def: HW dependent */
1676 int num_of_ampdu_queues; /* def: HW dependent */
1677 /* for il_apm_init() */
1678 u32 pll_cfg_val;
1679 bool set_l0s;
1680 bool use_bsm;
1681
1682 u16 led_compensation;
1683 int chain_noise_num_beacons;
1684 unsigned int wd_timeout;
1685 bool temperature_kelvin;
1686 const bool ucode_tracing;
1687 const bool sensitivity_calib_by_driver;
1688 const bool chain_noise_calib_by_driver;
1689
1690 const u32 regulatory_bands[7];
1691 };
1692
1693 /***************************
1694 * L i b *
1695 ***************************/
1696
1697 int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1698 unsigned int link_id, u16 queue,
1699 const struct ieee80211_tx_queue_params *params);
1700 int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1701
1702 void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1703 int il_check_rxon_cmd(struct il_priv *il);
1704 int il_full_rxon_required(struct il_priv *il);
1705 int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1706 void il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
1707 struct ieee80211_vif *vif);
1708 void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1709 bool il_is_ht40_tx_allowed(struct il_priv *il,
1710 struct ieee80211_sta_ht_cap *ht_cap);
1711 void il_connection_init_rx_config(struct il_priv *il);
1712 void il_set_rate(struct il_priv *il);
1713 int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1714 u32 decrypt_res, struct ieee80211_rx_status *stats);
1715 void il_irq_handle_error(struct il_priv *il);
1716 int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1717 void il_mac_remove_interface(struct ieee80211_hw *hw,
1718 struct ieee80211_vif *vif);
1719 int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1720 enum nl80211_iftype newtype, bool newp2p);
1721 void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1722 u32 queues, bool drop);
1723 int il_alloc_txq_mem(struct il_priv *il);
1724 void il_free_txq_mem(struct il_priv *il);
1725
1726 #ifdef CONFIG_IWLEGACY_DEBUGFS
1727 void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1728 #else
1729 static inline void
il_update_stats(struct il_priv * il,bool is_tx,__le16 fc,u16 len)1730 il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1731 {
1732 }
1733 #endif
1734
1735 /*****************************************************
1736 * Handlers
1737 ***************************************************/
1738 void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1739 void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1740 void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1741 void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1742
1743 /*****************************************************
1744 * RX
1745 ******************************************************/
1746 void il_cmd_queue_unmap(struct il_priv *il);
1747 void il_cmd_queue_free(struct il_priv *il);
1748 int il_rx_queue_alloc(struct il_priv *il);
1749 void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1750 int il_rx_queue_space(const struct il_rx_queue *q);
1751 void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1752
1753 void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1754 void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1755 void il_chswitch_done(struct il_priv *il, bool is_success);
1756
1757 /*****************************************************
1758 * TX
1759 ******************************************************/
1760 void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1761 int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1762 void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1763 void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1764 void il_tx_queue_free(struct il_priv *il, int txq_id);
1765 void il_setup_watchdog(struct il_priv *il);
1766 /*****************************************************
1767 * TX power
1768 ****************************************************/
1769 int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1770
1771 /*******************************************************************************
1772 * Rate
1773 ******************************************************************************/
1774
1775 u8 il_get_lowest_plcp(struct il_priv *il);
1776
1777 /*******************************************************************************
1778 * Scanning
1779 ******************************************************************************/
1780 void il_init_scan_params(struct il_priv *il);
1781 int il_scan_cancel(struct il_priv *il);
1782 int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1783 void il_force_scan_end(struct il_priv *il);
1784 int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1785 struct ieee80211_scan_request *hw_req);
1786 void il_internal_short_hw_scan(struct il_priv *il);
1787 int il_force_reset(struct il_priv *il, bool external);
1788 u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1789 const u8 *ta, const u8 *ie, int ie_len, int left);
1790 void il_setup_rx_scan_handlers(struct il_priv *il);
1791 u16 il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
1792 u8 n_probes);
1793 u16 il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
1794 struct ieee80211_vif *vif);
1795 void il_setup_scan_deferred_work(struct il_priv *il);
1796 void il_cancel_scan_deferred_work(struct il_priv *il);
1797
1798 /* For faster active scanning, scan will move to the next channel if fewer than
1799 * PLCP_QUIET_THRESH packets are heard on this channel within
1800 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1801 * time if it's a quiet channel (nothing responded to our probe, and there's
1802 * no other traffic).
1803 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
1804 #define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1805 #define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
1806
1807 #define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1808
1809 /*****************************************************
1810 * S e n d i n g H o s t C o m m a n d s *
1811 *****************************************************/
1812
1813 const char *il_get_cmd_string(u8 cmd);
1814 int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1815 int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1816 int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1817 const void *data);
1818 int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1819 void (*callback) (struct il_priv *il,
1820 struct il_device_cmd *cmd,
1821 struct il_rx_pkt *pkt));
1822
1823 int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1824
1825 /*****************************************************
1826 * PCI *
1827 *****************************************************/
1828
1829 void il_bg_watchdog(struct timer_list *t);
1830 u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1831 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1832 u32 beacon_interval);
1833
1834 #ifdef CONFIG_PM_SLEEP
1835 extern const struct dev_pm_ops il_pm_ops;
1836
1837 #define IL_LEGACY_PM_OPS (&il_pm_ops)
1838
1839 #else /* !CONFIG_PM_SLEEP */
1840
1841 #define IL_LEGACY_PM_OPS NULL
1842
1843 #endif /* !CONFIG_PM_SLEEP */
1844
1845 /*****************************************************
1846 * Error Handling Debugging
1847 ******************************************************/
1848 void il4965_dump_nic_error_log(struct il_priv *il);
1849 #ifdef CONFIG_IWLEGACY_DEBUG
1850 void il_print_rx_config_cmd(struct il_priv *il);
1851 #else
1852 static inline void
il_print_rx_config_cmd(struct il_priv * il)1853 il_print_rx_config_cmd(struct il_priv *il)
1854 {
1855 }
1856 #endif
1857
1858 void il_clear_isr_stats(struct il_priv *il);
1859
1860 /*****************************************************
1861 * GEOS
1862 ******************************************************/
1863 int il_init_geos(struct il_priv *il);
1864 void il_free_geos(struct il_priv *il);
1865
1866 /*************** DRIVER STATUS FUNCTIONS *****/
1867
1868 #define S_HCMD_ACTIVE 0 /* host command in progress */
1869 /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
1870 #define S_INT_ENABLED 2
1871 #define S_RFKILL 3
1872 #define S_CT_KILL 4
1873 #define S_INIT 5
1874 #define S_ALIVE 6
1875 #define S_READY 7
1876 #define S_TEMPERATURE 8
1877 #define S_GEO_CONFIGURED 9
1878 #define S_EXIT_PENDING 10
1879 #define S_STATS 12
1880 #define S_SCANNING 13
1881 #define S_SCAN_ABORTING 14
1882 #define S_SCAN_HW 15
1883 #define S_POWER_PMI 16
1884 #define S_FW_ERROR 17
1885 #define S_CHANNEL_SWITCH_PENDING 18
1886
1887 static inline int
il_is_ready(struct il_priv * il)1888 il_is_ready(struct il_priv *il)
1889 {
1890 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
1891 * set but EXIT_PENDING is not */
1892 return test_bit(S_READY, &il->status) &&
1893 test_bit(S_GEO_CONFIGURED, &il->status) &&
1894 !test_bit(S_EXIT_PENDING, &il->status);
1895 }
1896
1897 static inline int
il_is_alive(struct il_priv * il)1898 il_is_alive(struct il_priv *il)
1899 {
1900 return test_bit(S_ALIVE, &il->status);
1901 }
1902
1903 static inline int
il_is_init(struct il_priv * il)1904 il_is_init(struct il_priv *il)
1905 {
1906 return test_bit(S_INIT, &il->status);
1907 }
1908
1909 static inline int
il_is_rfkill(struct il_priv * il)1910 il_is_rfkill(struct il_priv *il)
1911 {
1912 return test_bit(S_RFKILL, &il->status);
1913 }
1914
1915 static inline int
il_is_ctkill(struct il_priv * il)1916 il_is_ctkill(struct il_priv *il)
1917 {
1918 return test_bit(S_CT_KILL, &il->status);
1919 }
1920
1921 static inline int
il_is_ready_rf(struct il_priv * il)1922 il_is_ready_rf(struct il_priv *il)
1923 {
1924
1925 if (il_is_rfkill(il))
1926 return 0;
1927
1928 return il_is_ready(il);
1929 }
1930
1931 void il_send_bt_config(struct il_priv *il);
1932 int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1933 void il_apm_stop(struct il_priv *il);
1934 void _il_apm_stop(struct il_priv *il);
1935
1936 int il_apm_init(struct il_priv *il);
1937
1938 int il_send_rxon_timing(struct il_priv *il);
1939
1940 static inline int
il_send_rxon_assoc(struct il_priv * il)1941 il_send_rxon_assoc(struct il_priv *il)
1942 {
1943 return il->ops->rxon_assoc(il);
1944 }
1945
1946 static inline int
il_commit_rxon(struct il_priv * il)1947 il_commit_rxon(struct il_priv *il)
1948 {
1949 return il->ops->commit_rxon(il);
1950 }
1951
1952 static inline const struct ieee80211_supported_band *
il_get_hw_mode(struct il_priv * il,enum nl80211_band band)1953 il_get_hw_mode(struct il_priv *il, enum nl80211_band band)
1954 {
1955 return il->hw->wiphy->bands[band];
1956 }
1957
1958 /* mac80211 handlers */
1959 int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1960 void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1961 void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1962 struct ieee80211_bss_conf *bss_conf, u64 changes);
1963 void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1964 __le16 fc, __le32 *tx_flags);
1965
1966 irqreturn_t il_isr(int irq, void *data);
1967
1968 void il_set_bit(struct il_priv *p, u32 r, u32 m);
1969 void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1970 bool _il_grab_nic_access(struct il_priv *il);
1971 int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1972 int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1973 u32 il_rd_prph(struct il_priv *il, u32 reg);
1974 void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1975 u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1976 void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1977
il_need_reclaim(struct il_priv * il,struct il_rx_pkt * pkt)1978 static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt)
1979 {
1980 /* Reclaim a command buffer only if this packet is a response
1981 * to a (driver-originated) command. If the packet (e.g. Rx frame)
1982 * originated from uCode, there is no command buffer to reclaim.
1983 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, but
1984 * apparently a few don't get set; catch them here.
1985 */
1986 return !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1987 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX &&
1988 pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX &&
1989 pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA;
1990 }
1991
1992 static inline void
_il_write8(struct il_priv * il,u32 ofs,u8 val)1993 _il_write8(struct il_priv *il, u32 ofs, u8 val)
1994 {
1995 writeb(val, il->hw_base + ofs);
1996 }
1997 #define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1998
1999 static inline void
_il_wr(struct il_priv * il,u32 ofs,u32 val)2000 _il_wr(struct il_priv *il, u32 ofs, u32 val)
2001 {
2002 writel(val, il->hw_base + ofs);
2003 }
2004
2005 static inline u32
_il_rd(struct il_priv * il,u32 ofs)2006 _il_rd(struct il_priv *il, u32 ofs)
2007 {
2008 return readl(il->hw_base + ofs);
2009 }
2010
2011 static inline void
_il_clear_bit(struct il_priv * il,u32 reg,u32 mask)2012 _il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2013 {
2014 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2015 }
2016
2017 static inline void
_il_set_bit(struct il_priv * il,u32 reg,u32 mask)2018 _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2019 {
2020 _il_wr(il, reg, _il_rd(il, reg) | mask);
2021 }
2022
2023 static inline void
_il_release_nic_access(struct il_priv * il)2024 _il_release_nic_access(struct il_priv *il)
2025 {
2026 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2027 }
2028
2029 static inline u32
il_rd(struct il_priv * il,u32 reg)2030 il_rd(struct il_priv *il, u32 reg)
2031 {
2032 u32 value;
2033 unsigned long reg_flags;
2034
2035 spin_lock_irqsave(&il->reg_lock, reg_flags);
2036 _il_grab_nic_access(il);
2037 value = _il_rd(il, reg);
2038 _il_release_nic_access(il);
2039 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2040 return value;
2041 }
2042
2043 static inline void
il_wr(struct il_priv * il,u32 reg,u32 value)2044 il_wr(struct il_priv *il, u32 reg, u32 value)
2045 {
2046 unsigned long reg_flags;
2047
2048 spin_lock_irqsave(&il->reg_lock, reg_flags);
2049 if (likely(_il_grab_nic_access(il))) {
2050 _il_wr(il, reg, value);
2051 _il_release_nic_access(il);
2052 }
2053 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2054 }
2055
2056 static inline u32
_il_rd_prph(struct il_priv * il,u32 reg)2057 _il_rd_prph(struct il_priv *il, u32 reg)
2058 {
2059 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2060 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2061 }
2062
2063 static inline void
_il_wr_prph(struct il_priv * il,u32 addr,u32 val)2064 _il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2065 {
2066 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2067 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2068 }
2069
2070 static inline void
il_set_bits_prph(struct il_priv * il,u32 reg,u32 mask)2071 il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2072 {
2073 unsigned long reg_flags;
2074
2075 spin_lock_irqsave(&il->reg_lock, reg_flags);
2076 if (likely(_il_grab_nic_access(il))) {
2077 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2078 _il_release_nic_access(il);
2079 }
2080 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2081 }
2082
2083 static inline void
il_set_bits_mask_prph(struct il_priv * il,u32 reg,u32 bits,u32 mask)2084 il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2085 {
2086 unsigned long reg_flags;
2087
2088 spin_lock_irqsave(&il->reg_lock, reg_flags);
2089 if (likely(_il_grab_nic_access(il))) {
2090 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2091 _il_release_nic_access(il);
2092 }
2093 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2094 }
2095
2096 static inline void
il_clear_bits_prph(struct il_priv * il,u32 reg,u32 mask)2097 il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2098 {
2099 unsigned long reg_flags;
2100 u32 val;
2101
2102 spin_lock_irqsave(&il->reg_lock, reg_flags);
2103 if (likely(_il_grab_nic_access(il))) {
2104 val = _il_rd_prph(il, reg);
2105 _il_wr_prph(il, reg, (val & ~mask));
2106 _il_release_nic_access(il);
2107 }
2108 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2109 }
2110
2111 #define HW_KEY_DYNAMIC 0
2112 #define HW_KEY_DEFAULT 1
2113
2114 #define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2115 #define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2116 #define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2117 being activated */
2118 #define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2119 (this is for the IBSS BSSID stations) */
2120 #define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
2121
2122 void il_restore_stations(struct il_priv *il);
2123 void il_clear_ucode_stations(struct il_priv *il);
2124 void il_dealloc_bcast_stations(struct il_priv *il);
2125 int il_get_free_ucode_key_idx(struct il_priv *il);
2126 int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2127 int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2128 struct ieee80211_sta *sta, u8 *sta_id_r);
2129 int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2130 int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2131 struct ieee80211_sta *sta);
2132
2133 u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2134 struct ieee80211_sta *sta);
2135
2136 int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2137 u8 flags, bool init);
2138
2139 /**
2140 * il_clear_driver_stations - clear knowledge of all stations from driver
2141 * @il: iwl il struct
2142 *
2143 * This is called during il_down() to make sure that in the case
2144 * we're coming there from a hardware restart mac80211 will be
2145 * able to reconfigure stations -- if we're getting there in the
2146 * normal down flow then the stations will already be cleared.
2147 */
2148 static inline void
il_clear_driver_stations(struct il_priv * il)2149 il_clear_driver_stations(struct il_priv *il)
2150 {
2151 unsigned long flags;
2152
2153 spin_lock_irqsave(&il->sta_lock, flags);
2154 memset(il->stations, 0, sizeof(il->stations));
2155 il->num_stations = 0;
2156 il->ucode_key_table = 0;
2157 spin_unlock_irqrestore(&il->sta_lock, flags);
2158 }
2159
2160 static inline int
il_sta_id(struct ieee80211_sta * sta)2161 il_sta_id(struct ieee80211_sta *sta)
2162 {
2163 if (WARN_ON(!sta))
2164 return IL_INVALID_STATION;
2165
2166 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2167 }
2168
2169 /**
2170 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2171 * @il: iwl il
2172 * @context: the current context
2173 * @sta: mac80211 station
2174 *
2175 * In certain circumstances mac80211 passes a station pointer
2176 * that may be %NULL, for example during TX or key setup. In
2177 * that case, we need to use the broadcast station, so this
2178 * inline wraps that pattern.
2179 */
2180 static inline int
il_sta_id_or_broadcast(struct il_priv * il,struct ieee80211_sta * sta)2181 il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2182 {
2183 int sta_id;
2184
2185 if (!sta)
2186 return il->hw_params.bcast_id;
2187
2188 sta_id = il_sta_id(sta);
2189
2190 /*
2191 * mac80211 should not be passing a partially
2192 * initialised station!
2193 */
2194 WARN_ON(sta_id == IL_INVALID_STATION);
2195
2196 return sta_id;
2197 }
2198
2199 /**
2200 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2201 * @idx -- current idx
2202 * @n_bd -- total number of entries in queue (must be power of 2)
2203 */
2204 static inline int
il_queue_inc_wrap(int idx,int n_bd)2205 il_queue_inc_wrap(int idx, int n_bd)
2206 {
2207 return ++idx & (n_bd - 1);
2208 }
2209
2210 /**
2211 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2212 * @idx -- current idx
2213 * @n_bd -- total number of entries in queue (must be power of 2)
2214 */
2215 static inline int
il_queue_dec_wrap(int idx,int n_bd)2216 il_queue_dec_wrap(int idx, int n_bd)
2217 {
2218 return --idx & (n_bd - 1);
2219 }
2220
2221 /* TODO: Move fw_desc functions to iwl-pci.ko */
2222 static inline void
il_free_fw_desc(struct pci_dev * pci_dev,struct fw_desc * desc)2223 il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2224 {
2225 if (desc->v_addr)
2226 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2227 desc->p_addr);
2228 desc->v_addr = NULL;
2229 desc->len = 0;
2230 }
2231
2232 static inline int
il_alloc_fw_desc(struct pci_dev * pci_dev,struct fw_desc * desc)2233 il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2234 {
2235 if (!desc->len) {
2236 desc->v_addr = NULL;
2237 return -EINVAL;
2238 }
2239
2240 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2241 &desc->p_addr, GFP_KERNEL);
2242 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2243 }
2244
2245 /*
2246 * we have 8 bits used like this:
2247 *
2248 * 7 6 5 4 3 2 1 0
2249 * | | | | | | | |
2250 * | | | | | | +-+-------- AC queue (0-3)
2251 * | | | | | |
2252 * | +-+-+-+-+------------ HW queue ID
2253 * |
2254 * +---------------------- unused
2255 */
2256 static inline void
il_set_swq_id(struct il_tx_queue * txq,u8 ac,u8 hwq)2257 il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2258 {
2259 BUG_ON(ac > 3); /* only have 2 bits */
2260 BUG_ON(hwq > 31); /* only use 5 bits */
2261
2262 txq->swq_id = (hwq << 2) | ac;
2263 }
2264
2265 static inline void
_il_wake_queue(struct il_priv * il,u8 ac)2266 _il_wake_queue(struct il_priv *il, u8 ac)
2267 {
2268 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2269 ieee80211_wake_queue(il->hw, ac);
2270 }
2271
2272 static inline void
_il_stop_queue(struct il_priv * il,u8 ac)2273 _il_stop_queue(struct il_priv *il, u8 ac)
2274 {
2275 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2276 ieee80211_stop_queue(il->hw, ac);
2277 }
2278 static inline void
il_wake_queue(struct il_priv * il,struct il_tx_queue * txq)2279 il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2280 {
2281 u8 queue = txq->swq_id;
2282 u8 ac = queue & 3;
2283 u8 hwq = (queue >> 2) & 0x1f;
2284
2285 if (test_and_clear_bit(hwq, il->queue_stopped))
2286 _il_wake_queue(il, ac);
2287 }
2288
2289 static inline void
il_stop_queue(struct il_priv * il,struct il_tx_queue * txq)2290 il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2291 {
2292 u8 queue = txq->swq_id;
2293 u8 ac = queue & 3;
2294 u8 hwq = (queue >> 2) & 0x1f;
2295
2296 if (!test_and_set_bit(hwq, il->queue_stopped))
2297 _il_stop_queue(il, ac);
2298 }
2299
2300 static inline void
il_wake_queues_by_reason(struct il_priv * il,int reason)2301 il_wake_queues_by_reason(struct il_priv *il, int reason)
2302 {
2303 u8 ac;
2304
2305 if (test_and_clear_bit(reason, &il->stop_reason))
2306 for (ac = 0; ac < 4; ac++)
2307 _il_wake_queue(il, ac);
2308 }
2309
2310 static inline void
il_stop_queues_by_reason(struct il_priv * il,int reason)2311 il_stop_queues_by_reason(struct il_priv *il, int reason)
2312 {
2313 u8 ac;
2314
2315 if (!test_and_set_bit(reason, &il->stop_reason))
2316 for (ac = 0; ac < 4; ac++)
2317 _il_stop_queue(il, ac);
2318 }
2319
2320 #ifdef ieee80211_stop_queue
2321 #undef ieee80211_stop_queue
2322 #endif
2323
2324 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2325
2326 #ifdef ieee80211_wake_queue
2327 #undef ieee80211_wake_queue
2328 #endif
2329
2330 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2331
2332 static inline void
il_disable_interrupts(struct il_priv * il)2333 il_disable_interrupts(struct il_priv *il)
2334 {
2335 clear_bit(S_INT_ENABLED, &il->status);
2336
2337 /* disable interrupts from uCode/NIC to host */
2338 _il_wr(il, CSR_INT_MASK, 0x00000000);
2339
2340 /* acknowledge/clear/reset any interrupts still pending
2341 * from uCode or flow handler (Rx/Tx DMA) */
2342 _il_wr(il, CSR_INT, 0xffffffff);
2343 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2344 }
2345
2346 static inline void
il_enable_rfkill_int(struct il_priv * il)2347 il_enable_rfkill_int(struct il_priv *il)
2348 {
2349 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2350 }
2351
2352 static inline void
il_enable_interrupts(struct il_priv * il)2353 il_enable_interrupts(struct il_priv *il)
2354 {
2355 set_bit(S_INT_ENABLED, &il->status);
2356 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2357 }
2358
2359 /**
2360 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2361 * @il -- pointer to il_priv data structure
2362 * @tsf_bits -- number of bits need to shift for masking)
2363 */
2364 static inline u32
il_beacon_time_mask_low(struct il_priv * il,u16 tsf_bits)2365 il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2366 {
2367 return (1 << tsf_bits) - 1;
2368 }
2369
2370 /**
2371 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2372 * @il -- pointer to il_priv data structure
2373 * @tsf_bits -- number of bits need to shift for masking)
2374 */
2375 static inline u32
il_beacon_time_mask_high(struct il_priv * il,u16 tsf_bits)2376 il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2377 {
2378 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2379 }
2380
2381 /**
2382 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2383 *
2384 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2385 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2386 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2387 * in which the last frame was written to
2388 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2389 * which was transferred
2390 */
2391 struct il_rb_status {
2392 __le16 closed_rb_num;
2393 __le16 closed_fr_num;
2394 __le16 finished_rb_num;
2395 __le16 finished_fr_nam;
2396 __le32 __unused; /* 3945 only */
2397 } __packed;
2398
2399 #define TFD_QUEUE_SIZE_MAX 256
2400 #define TFD_QUEUE_SIZE_BC_DUP 64
2401 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2402 #define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2403 #define IL_NUM_OF_TBS 20
2404
2405 static inline u8
il_get_dma_hi_addr(dma_addr_t addr)2406 il_get_dma_hi_addr(dma_addr_t addr)
2407 {
2408 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2409 }
2410
2411 /**
2412 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2413 *
2414 * This structure contains dma address and length of transmission address
2415 *
2416 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2417 * unaligned on 16 bit boundary
2418 * @hi_n_len: 0-3 [35:32] portion of dma
2419 * 4-15 length of the tx buffer
2420 */
2421 struct il_tfd_tb {
2422 __le32 lo;
2423 __le16 hi_n_len;
2424 } __packed;
2425
2426 /**
2427 * struct il_tfd
2428 *
2429 * Transmit Frame Descriptor (TFD)
2430 *
2431 * @ __reserved1[3] reserved
2432 * @ num_tbs 0-4 number of active tbs
2433 * 5 reserved
2434 * 6-7 padding (not used)
2435 * @ tbs[20] transmit frame buffer descriptors
2436 * @ __pad padding
2437 *
2438 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2439 * Both driver and device share these circular buffers, each of which must be
2440 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2441 *
2442 * Driver must indicate the physical address of the base of each
2443 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
2444 *
2445 * Each TFD contains pointer/size information for up to 20 data buffers
2446 * in host DRAM. These buffers collectively contain the (one) frame described
2447 * by the TFD. Each buffer must be a single contiguous block of memory within
2448 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2449 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2450 * Tx frame, up to 8 KBytes in size.
2451 *
2452 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2453 */
2454 struct il_tfd {
2455 u8 __reserved1[3];
2456 u8 num_tbs;
2457 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2458 __le32 __pad;
2459 } __packed;
2460 /* PCI registers */
2461 #define PCI_CFG_RETRY_TIMEOUT 0x041
2462
2463 struct il_rate_info {
2464 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2465 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2466 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2467 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2468 u8 prev_ieee; /* previous rate in IEEE speeds */
2469 u8 next_ieee; /* next rate in IEEE speeds */
2470 u8 prev_rs; /* previous rate used in rs algo */
2471 u8 next_rs; /* next rate used in rs algo */
2472 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2473 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2474 };
2475
2476 struct il3945_rate_info {
2477 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2478 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2479 u8 prev_ieee; /* previous rate in IEEE speeds */
2480 u8 next_ieee; /* next rate in IEEE speeds */
2481 u8 prev_rs; /* previous rate used in rs algo */
2482 u8 next_rs; /* next rate used in rs algo */
2483 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2484 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2485 u8 table_rs_idx; /* idx in rate scale table cmd */
2486 u8 prev_table_rs; /* prev in rate table cmd */
2487 };
2488
2489 /*
2490 * These serve as idxes into
2491 * struct il_rate_info il_rates[RATE_COUNT];
2492 */
2493 enum {
2494 RATE_1M_IDX = 0,
2495 RATE_2M_IDX,
2496 RATE_5M_IDX,
2497 RATE_11M_IDX,
2498 RATE_6M_IDX,
2499 RATE_9M_IDX,
2500 RATE_12M_IDX,
2501 RATE_18M_IDX,
2502 RATE_24M_IDX,
2503 RATE_36M_IDX,
2504 RATE_48M_IDX,
2505 RATE_54M_IDX,
2506 RATE_60M_IDX,
2507 RATE_COUNT,
2508 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2509 RATE_COUNT_3945 = RATE_COUNT - 1,
2510 RATE_INVM_IDX = RATE_COUNT,
2511 RATE_INVALID = RATE_COUNT,
2512 };
2513
2514 enum {
2515 RATE_6M_IDX_TBL = 0,
2516 RATE_9M_IDX_TBL,
2517 RATE_12M_IDX_TBL,
2518 RATE_18M_IDX_TBL,
2519 RATE_24M_IDX_TBL,
2520 RATE_36M_IDX_TBL,
2521 RATE_48M_IDX_TBL,
2522 RATE_54M_IDX_TBL,
2523 RATE_1M_IDX_TBL,
2524 RATE_2M_IDX_TBL,
2525 RATE_5M_IDX_TBL,
2526 RATE_11M_IDX_TBL,
2527 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2528 };
2529
2530 enum {
2531 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2532 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2533 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2534 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2535 IL_LAST_CCK_RATE = RATE_11M_IDX,
2536 };
2537
2538 /* #define vs. enum to keep from defaulting to 'large integer' */
2539 #define RATE_6M_MASK (1 << RATE_6M_IDX)
2540 #define RATE_9M_MASK (1 << RATE_9M_IDX)
2541 #define RATE_12M_MASK (1 << RATE_12M_IDX)
2542 #define RATE_18M_MASK (1 << RATE_18M_IDX)
2543 #define RATE_24M_MASK (1 << RATE_24M_IDX)
2544 #define RATE_36M_MASK (1 << RATE_36M_IDX)
2545 #define RATE_48M_MASK (1 << RATE_48M_IDX)
2546 #define RATE_54M_MASK (1 << RATE_54M_IDX)
2547 #define RATE_60M_MASK (1 << RATE_60M_IDX)
2548 #define RATE_1M_MASK (1 << RATE_1M_IDX)
2549 #define RATE_2M_MASK (1 << RATE_2M_IDX)
2550 #define RATE_5M_MASK (1 << RATE_5M_IDX)
2551 #define RATE_11M_MASK (1 << RATE_11M_IDX)
2552
2553 /* uCode API values for legacy bit rates, both OFDM and CCK */
2554 enum {
2555 RATE_6M_PLCP = 13,
2556 RATE_9M_PLCP = 15,
2557 RATE_12M_PLCP = 5,
2558 RATE_18M_PLCP = 7,
2559 RATE_24M_PLCP = 9,
2560 RATE_36M_PLCP = 11,
2561 RATE_48M_PLCP = 1,
2562 RATE_54M_PLCP = 3,
2563 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2564 RATE_1M_PLCP = 10,
2565 RATE_2M_PLCP = 20,
2566 RATE_5M_PLCP = 55,
2567 RATE_11M_PLCP = 110,
2568 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
2569 };
2570
2571 /* uCode API values for OFDM high-throughput (HT) bit rates */
2572 enum {
2573 RATE_SISO_6M_PLCP = 0,
2574 RATE_SISO_12M_PLCP = 1,
2575 RATE_SISO_18M_PLCP = 2,
2576 RATE_SISO_24M_PLCP = 3,
2577 RATE_SISO_36M_PLCP = 4,
2578 RATE_SISO_48M_PLCP = 5,
2579 RATE_SISO_54M_PLCP = 6,
2580 RATE_SISO_60M_PLCP = 7,
2581 RATE_MIMO2_6M_PLCP = 0x8,
2582 RATE_MIMO2_12M_PLCP = 0x9,
2583 RATE_MIMO2_18M_PLCP = 0xa,
2584 RATE_MIMO2_24M_PLCP = 0xb,
2585 RATE_MIMO2_36M_PLCP = 0xc,
2586 RATE_MIMO2_48M_PLCP = 0xd,
2587 RATE_MIMO2_54M_PLCP = 0xe,
2588 RATE_MIMO2_60M_PLCP = 0xf,
2589 RATE_SISO_INVM_PLCP,
2590 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2591 };
2592
2593 /* MAC header values for bit rates */
2594 enum {
2595 RATE_6M_IEEE = 12,
2596 RATE_9M_IEEE = 18,
2597 RATE_12M_IEEE = 24,
2598 RATE_18M_IEEE = 36,
2599 RATE_24M_IEEE = 48,
2600 RATE_36M_IEEE = 72,
2601 RATE_48M_IEEE = 96,
2602 RATE_54M_IEEE = 108,
2603 RATE_60M_IEEE = 120,
2604 RATE_1M_IEEE = 2,
2605 RATE_2M_IEEE = 4,
2606 RATE_5M_IEEE = 11,
2607 RATE_11M_IEEE = 22,
2608 };
2609
2610 #define IL_CCK_BASIC_RATES_MASK \
2611 (RATE_1M_MASK | \
2612 RATE_2M_MASK)
2613
2614 #define IL_CCK_RATES_MASK \
2615 (IL_CCK_BASIC_RATES_MASK | \
2616 RATE_5M_MASK | \
2617 RATE_11M_MASK)
2618
2619 #define IL_OFDM_BASIC_RATES_MASK \
2620 (RATE_6M_MASK | \
2621 RATE_12M_MASK | \
2622 RATE_24M_MASK)
2623
2624 #define IL_OFDM_RATES_MASK \
2625 (IL_OFDM_BASIC_RATES_MASK | \
2626 RATE_9M_MASK | \
2627 RATE_18M_MASK | \
2628 RATE_36M_MASK | \
2629 RATE_48M_MASK | \
2630 RATE_54M_MASK)
2631
2632 #define IL_BASIC_RATES_MASK \
2633 (IL_OFDM_BASIC_RATES_MASK | \
2634 IL_CCK_BASIC_RATES_MASK)
2635
2636 #define RATES_MASK ((1 << RATE_COUNT) - 1)
2637 #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2638
2639 #define IL_INVALID_VALUE -1
2640
2641 #define IL_MIN_RSSI_VAL -100
2642 #define IL_MAX_RSSI_VAL 0
2643
2644 /* These values specify how many Tx frame attempts before
2645 * searching for a new modulation mode */
2646 #define IL_LEGACY_FAILURE_LIMIT 160
2647 #define IL_LEGACY_SUCCESS_LIMIT 480
2648 #define IL_LEGACY_TBL_COUNT 160
2649
2650 #define IL_NONE_LEGACY_FAILURE_LIMIT 400
2651 #define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2652 #define IL_NONE_LEGACY_TBL_COUNT 1500
2653
2654 /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2655 #define IL_RS_GOOD_RATIO 12800 /* 100% */
2656 #define RATE_SCALE_SWITCH 10880 /* 85% */
2657 #define RATE_HIGH_TH 10880 /* 85% */
2658 #define RATE_INCREASE_TH 6400 /* 50% */
2659 #define RATE_DECREASE_TH 1920 /* 15% */
2660
2661 /* possible actions when in legacy mode */
2662 #define IL_LEGACY_SWITCH_ANTENNA1 0
2663 #define IL_LEGACY_SWITCH_ANTENNA2 1
2664 #define IL_LEGACY_SWITCH_SISO 2
2665 #define IL_LEGACY_SWITCH_MIMO2_AB 3
2666 #define IL_LEGACY_SWITCH_MIMO2_AC 4
2667 #define IL_LEGACY_SWITCH_MIMO2_BC 5
2668
2669 /* possible actions when in siso mode */
2670 #define IL_SISO_SWITCH_ANTENNA1 0
2671 #define IL_SISO_SWITCH_ANTENNA2 1
2672 #define IL_SISO_SWITCH_MIMO2_AB 2
2673 #define IL_SISO_SWITCH_MIMO2_AC 3
2674 #define IL_SISO_SWITCH_MIMO2_BC 4
2675 #define IL_SISO_SWITCH_GI 5
2676
2677 /* possible actions when in mimo mode */
2678 #define IL_MIMO2_SWITCH_ANTENNA1 0
2679 #define IL_MIMO2_SWITCH_ANTENNA2 1
2680 #define IL_MIMO2_SWITCH_SISO_A 2
2681 #define IL_MIMO2_SWITCH_SISO_B 3
2682 #define IL_MIMO2_SWITCH_SISO_C 4
2683 #define IL_MIMO2_SWITCH_GI 5
2684
2685 #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2686
2687 #define IL_ACTION_LIMIT 3 /* # possible actions */
2688
2689 #define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
2690
2691 /* load per tid defines for A-MPDU activation */
2692 #define IL_AGG_TPT_THREHOLD 0
2693 #define IL_AGG_LOAD_THRESHOLD 10
2694 #define IL_AGG_ALL_TID 0xff
2695 #define TID_QUEUE_CELL_SPACING 50 /*mS */
2696 #define TID_QUEUE_MAX_SIZE 20
2697 #define TID_ROUND_VALUE 5 /* mS */
2698 #define TID_MAX_LOAD_COUNT 8
2699
2700 #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2701 #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2702
2703 extern const struct il_rate_info il_rates[RATE_COUNT];
2704
2705 enum il_table_type {
2706 LQ_NONE,
2707 LQ_G, /* legacy types */
2708 LQ_A,
2709 LQ_SISO, /* high-throughput types */
2710 LQ_MIMO2,
2711 LQ_MAX,
2712 };
2713
2714 #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2715 #define is_siso(tbl) ((tbl) == LQ_SISO)
2716 #define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2717 #define is_mimo(tbl) (is_mimo2(tbl))
2718 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2719 #define is_a_band(tbl) ((tbl) == LQ_A)
2720 #define is_g_and(tbl) ((tbl) == LQ_G)
2721
2722 #define ANT_NONE 0x0
2723 #define ANT_A BIT(0)
2724 #define ANT_B BIT(1)
2725 #define ANT_AB (ANT_A | ANT_B)
2726 #define ANT_C BIT(2)
2727 #define ANT_AC (ANT_A | ANT_C)
2728 #define ANT_BC (ANT_B | ANT_C)
2729 #define ANT_ABC (ANT_AB | ANT_C)
2730
2731 #define IL_MAX_MCS_DISPLAY_SIZE 12
2732
2733 struct il_rate_mcs_info {
2734 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2735 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2736 };
2737
2738 /**
2739 * struct il_rate_scale_data -- tx success history for one rate
2740 */
2741 struct il_rate_scale_data {
2742 u64 data; /* bitmap of successful frames */
2743 s32 success_counter; /* number of frames successful */
2744 s32 success_ratio; /* per-cent * 128 */
2745 s32 counter; /* number of frames attempted */
2746 s32 average_tpt; /* success ratio * expected throughput */
2747 unsigned long stamp;
2748 };
2749
2750 /**
2751 * struct il_scale_tbl_info -- tx params and success history for all rates
2752 *
2753 * There are two of these in struct il_lq_sta,
2754 * one for "active", and one for "search".
2755 */
2756 struct il_scale_tbl_info {
2757 enum il_table_type lq_type;
2758 u8 ant_type;
2759 u8 is_SGI; /* 1 = short guard interval */
2760 u8 is_ht40; /* 1 = 40 MHz channel width */
2761 u8 is_dup; /* 1 = duplicated data streams */
2762 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2763 u8 max_search; /* maximun number of tables we can search */
2764 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
2765 u32 current_rate; /* rate_n_flags, uCode API format */
2766 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
2767 };
2768
2769 struct il_traffic_load {
2770 unsigned long time_stamp; /* age of the oldest stats */
2771 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
2772 * slice */
2773 u32 total; /* total num of packets during the
2774 * last TID_MAX_TIME_DIFF */
2775 u8 queue_count; /* number of queues that has
2776 * been used since the last cleanup */
2777 u8 head; /* start of the circular buffer */
2778 };
2779
2780 /**
2781 * struct il_lq_sta -- driver's rate scaling ilate structure
2782 *
2783 * Pointer to this gets passed back and forth between driver and mac80211.
2784 */
2785 struct il_lq_sta {
2786 u8 active_tbl; /* idx of active table, range 0-1 */
2787 u8 enable_counter; /* indicates HT mode */
2788 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
2789 u8 search_better_tbl; /* 1: currently trying alternate mode */
2790 s32 last_tpt;
2791
2792 /* The following determine when to search for a new mode */
2793 u32 table_count_limit;
2794 u32 max_failure_limit; /* # failed frames before new search */
2795 u32 max_success_limit; /* # successful frames before new search */
2796 u32 table_count;
2797 u32 total_failed; /* total failed frames, any/all rates */
2798 u32 total_success; /* total successful frames, any/all rates */
2799 u64 flush_timer; /* time staying in mode before new search */
2800
2801 u8 action_counter; /* # mode-switch actions tried */
2802 u8 is_green;
2803 u8 is_dup;
2804 enum nl80211_band band;
2805
2806 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2807 u32 supp_rates;
2808 u16 active_legacy_rate;
2809 u16 active_siso_rate;
2810 u16 active_mimo2_rate;
2811 s8 max_rate_idx; /* Max rate set by user */
2812 u8 missed_rate_counter;
2813
2814 struct il_link_quality_cmd lq;
2815 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
2816 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2817 u8 tx_agg_tid_en;
2818 u32 dbg_fixed_rate;
2819 struct il_priv *drv;
2820
2821 /* used to be in sta_info */
2822 int last_txrate_idx;
2823 /* last tx rate_n_flags */
2824 u32 last_rate_n_flags;
2825 /* packets destined for this STA are aggregated */
2826 u8 is_agg;
2827 };
2828
2829 /*
2830 * il_station_priv: Driver's ilate station information
2831 *
2832 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2833 * in the structure for use by driver. This structure is places in that
2834 * space.
2835 *
2836 * The common struct MUST be first because it is shared between
2837 * 3945 and 4965!
2838 */
2839 struct il_station_priv {
2840 struct il_station_priv_common common;
2841 struct il_lq_sta lq_sta;
2842 atomic_t pending_frames;
2843 bool client;
2844 bool asleep;
2845 };
2846
2847 static inline u8
il4965_num_of_ant(u8 m)2848 il4965_num_of_ant(u8 m)
2849 {
2850 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2851 }
2852
2853 static inline u8
il4965_first_antenna(u8 mask)2854 il4965_first_antenna(u8 mask)
2855 {
2856 if (mask & ANT_A)
2857 return ANT_A;
2858 if (mask & ANT_B)
2859 return ANT_B;
2860 return ANT_C;
2861 }
2862
2863 /**
2864 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2865 *
2866 * The specific throughput table used is based on the type of network
2867 * the associated with, including A, B, G, and G w/ TGG protection
2868 */
2869 void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2870
2871 /* Initialize station's rate scaling information after adding station */
2872 void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2873 u8 sta_id);
2874 void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2875 u8 sta_id);
2876
2877 /**
2878 * il_rate_control_register - Register the rate control algorithm callbacks
2879 *
2880 * Since the rate control algorithm is hardware specific, there is no need
2881 * or reason to place it as a stand alone module. The driver can call
2882 * il_rate_control_register in order to register the rate control callbacks
2883 * with the mac80211 subsystem. This should be performed prior to calling
2884 * ieee80211_register_hw
2885 *
2886 */
2887 int il4965_rate_control_register(void);
2888 int il3945_rate_control_register(void);
2889
2890 /**
2891 * il_rate_control_unregister - Unregister the rate control callbacks
2892 *
2893 * This should be called after calling ieee80211_unregister_hw, but before
2894 * the driver is unloaded.
2895 */
2896 void il4965_rate_control_unregister(void);
2897 void il3945_rate_control_unregister(void);
2898
2899 int il_power_update_mode(struct il_priv *il, bool force);
2900 void il_power_initialize(struct il_priv *il);
2901
2902 extern u32 il_debug_level;
2903
2904 #ifdef CONFIG_IWLEGACY_DEBUG
2905 /*
2906 * il_get_debug_level: Return active debug level for device
2907 *
2908 * Using sysfs it is possible to set per device debug level. This debug
2909 * level will be used if set, otherwise the global debug level which can be
2910 * set via module parameter is used.
2911 */
2912 static inline u32
il_get_debug_level(struct il_priv * il)2913 il_get_debug_level(struct il_priv *il)
2914 {
2915 if (il->debug_level)
2916 return il->debug_level;
2917 else
2918 return il_debug_level;
2919 }
2920 #else
2921 static inline u32
il_get_debug_level(struct il_priv * il)2922 il_get_debug_level(struct il_priv *il)
2923 {
2924 return il_debug_level;
2925 }
2926 #endif
2927
2928 #define il_print_hex_error(il, p, len) \
2929 do { \
2930 print_hex_dump(KERN_ERR, "iwl data: ", \
2931 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2932 } while (0)
2933
2934 #ifdef CONFIG_IWLEGACY_DEBUG
2935 #define IL_DBG(level, fmt, args...) \
2936 do { \
2937 if (il_get_debug_level(il) & level) \
2938 dev_err(&il->hw->wiphy->dev, "%s " fmt, __func__, \
2939 ##args); \
2940 } while (0)
2941
2942 #define il_print_hex_dump(il, level, p, len) \
2943 do { \
2944 if (il_get_debug_level(il) & level) \
2945 print_hex_dump(KERN_DEBUG, "iwl data: ", \
2946 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2947 } while (0)
2948
2949 #else
2950 #define IL_DBG(level, fmt, args...) no_printk(fmt, ##args)
2951 static inline void
il_print_hex_dump(struct il_priv * il,int level,const void * p,u32 len)2952 il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2953 {
2954 }
2955 #endif /* CONFIG_IWLEGACY_DEBUG */
2956
2957 #ifdef CONFIG_IWLEGACY_DEBUGFS
2958 void il_dbgfs_register(struct il_priv *il, const char *name);
2959 void il_dbgfs_unregister(struct il_priv *il);
2960 #else
il_dbgfs_register(struct il_priv * il,const char * name)2961 static inline void il_dbgfs_register(struct il_priv *il, const char *name)
2962 {
2963 }
2964
2965 static inline void
il_dbgfs_unregister(struct il_priv * il)2966 il_dbgfs_unregister(struct il_priv *il)
2967 {
2968 }
2969 #endif /* CONFIG_IWLEGACY_DEBUGFS */
2970
2971 /*
2972 * To use the debug system:
2973 *
2974 * If you are defining a new debug classification, simply add it to the #define
2975 * list here in the form of
2976 *
2977 * #define IL_DL_xxxx VALUE
2978 *
2979 * where xxxx should be the name of the classification (for example, WEP).
2980 *
2981 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
2982 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
2983 * to send output to that classification.
2984 *
2985 * The active debug levels can be accessed via files
2986 *
2987 * /sys/module/iwl4965/parameters/debug
2988 * /sys/module/iwl3945/parameters/debug
2989 * /sys/class/net/wlan0/device/debug_level
2990 *
2991 * when CONFIG_IWLEGACY_DEBUG=y.
2992 */
2993
2994 /* 0x0000000F - 0x00000001 */
2995 #define IL_DL_INFO (1 << 0)
2996 #define IL_DL_MAC80211 (1 << 1)
2997 #define IL_DL_HCMD (1 << 2)
2998 #define IL_DL_STATE (1 << 3)
2999 /* 0x000000F0 - 0x00000010 */
3000 #define IL_DL_MACDUMP (1 << 4)
3001 #define IL_DL_HCMD_DUMP (1 << 5)
3002 #define IL_DL_EEPROM (1 << 6)
3003 #define IL_DL_RADIO (1 << 7)
3004 /* 0x00000F00 - 0x00000100 */
3005 #define IL_DL_POWER (1 << 8)
3006 #define IL_DL_TEMP (1 << 9)
3007 #define IL_DL_NOTIF (1 << 10)
3008 #define IL_DL_SCAN (1 << 11)
3009 /* 0x0000F000 - 0x00001000 */
3010 #define IL_DL_ASSOC (1 << 12)
3011 #define IL_DL_DROP (1 << 13)
3012 #define IL_DL_TXPOWER (1 << 14)
3013 #define IL_DL_AP (1 << 15)
3014 /* 0x000F0000 - 0x00010000 */
3015 #define IL_DL_FW (1 << 16)
3016 #define IL_DL_RF_KILL (1 << 17)
3017 #define IL_DL_FW_ERRORS (1 << 18)
3018 #define IL_DL_LED (1 << 19)
3019 /* 0x00F00000 - 0x00100000 */
3020 #define IL_DL_RATE (1 << 20)
3021 #define IL_DL_CALIB (1 << 21)
3022 #define IL_DL_WEP (1 << 22)
3023 #define IL_DL_TX (1 << 23)
3024 /* 0x0F000000 - 0x01000000 */
3025 #define IL_DL_RX (1 << 24)
3026 #define IL_DL_ISR (1 << 25)
3027 #define IL_DL_HT (1 << 26)
3028 /* 0xF0000000 - 0x10000000 */
3029 #define IL_DL_11H (1 << 28)
3030 #define IL_DL_STATS (1 << 29)
3031 #define IL_DL_TX_REPLY (1 << 30)
3032 #define IL_DL_QOS (1 << 31)
3033
3034 #define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3035 #define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3036 #define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3037 #define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3038 #define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3039 #define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3040 #define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3041 #define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3042 #define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3043 #define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3044 #define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3045 #define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3046 #define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3047 #define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3048 #define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3049 #define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3050 #define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3051 #define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3052 #define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3053 #define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3054 #define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3055 #define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3056 #define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3057 #define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3058 #define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3059 #define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3060 #define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3061 #define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3062 #define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3063
3064 #endif /* __il_core_h__ */
3065