1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1990 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 #include "opt_capsicum.h"
35 #include "opt_ktrace.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/capsicum.h>
40 #include <sys/kernel.h>
41 #include <sys/ktrace.h>
42 #include <sys/lock.h>
43 #include <sys/malloc.h>
44 #include <sys/mutex.h>
45 #include <sys/pcpu.h>
46 #include <sys/priv.h>
47 #include <sys/proc.h>
48 #include <sys/smp.h>
49 #include <sys/sysent.h>
50 #include <sys/sysproto.h>
51 #include <sys/uio.h>
52
53 #include <vm/vm.h>
54 #include <vm/pmap.h>
55 #include <vm/vm_kern.h> /* for kernel_map */
56 #include <vm/vm_map.h>
57 #include <vm/vm_extern.h>
58
59 #include <machine/frame.h>
60 #include <machine/md_var.h>
61 #include <machine/pcb.h>
62 #include <machine/specialreg.h>
63 #include <machine/sysarch.h>
64 #include <machine/tss.h>
65 #include <machine/vmparam.h>
66
67 #include <security/audit/audit.h>
68
69 static void user_ldt_deref(struct proc_ldt *pldt);
70 static void user_ldt_derefl(struct proc_ldt *pldt);
71
72 #define MAX_LD 8192
73
74 int max_ldt_segment = 512;
75 SYSCTL_INT(_machdep, OID_AUTO, max_ldt_segment, CTLFLAG_RDTUN,
76 &max_ldt_segment, 0,
77 "Maximum number of allowed LDT segments in the single address space");
78
79 static void
max_ldt_segment_init(void * arg __unused)80 max_ldt_segment_init(void *arg __unused)
81 {
82
83 if (max_ldt_segment <= 0)
84 max_ldt_segment = 1;
85 if (max_ldt_segment > MAX_LD)
86 max_ldt_segment = MAX_LD;
87 }
88 SYSINIT(maxldt, SI_SUB_VM_CONF, SI_ORDER_ANY, max_ldt_segment_init, NULL);
89
90 #ifndef _SYS_SYSPROTO_H_
91 struct sysarch_args {
92 int op;
93 char *parms;
94 };
95 #endif
96
97 int
sysarch_ldt(struct thread * td,struct sysarch_args * uap,int uap_space)98 sysarch_ldt(struct thread *td, struct sysarch_args *uap, int uap_space)
99 {
100 struct i386_ldt_args *largs, la;
101 struct user_segment_descriptor *lp;
102 int error = 0;
103
104 /*
105 * XXXKIB check that the BSM generation code knows to encode
106 * the op argument.
107 */
108 AUDIT_ARG_CMD(uap->op);
109 if (uap_space == UIO_USERSPACE) {
110 error = copyin(uap->parms, &la, sizeof(struct i386_ldt_args));
111 if (error != 0)
112 return (error);
113 largs = &la;
114 } else
115 largs = (struct i386_ldt_args *)uap->parms;
116
117 switch (uap->op) {
118 case I386_GET_LDT:
119 error = amd64_get_ldt(td, largs);
120 break;
121 case I386_SET_LDT:
122 if (largs->descs != NULL && largs->num > max_ldt_segment)
123 return (EINVAL);
124 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
125 if (largs->descs != NULL) {
126 lp = malloc(largs->num * sizeof(struct
127 user_segment_descriptor), M_TEMP, M_WAITOK);
128 error = copyin(largs->descs, lp, largs->num *
129 sizeof(struct user_segment_descriptor));
130 if (error == 0)
131 error = amd64_set_ldt(td, largs, lp);
132 free(lp, M_TEMP);
133 } else {
134 error = amd64_set_ldt(td, largs, NULL);
135 }
136 break;
137 }
138 return (error);
139 }
140
141 void
update_gdt_gsbase(struct thread * td,uint32_t base)142 update_gdt_gsbase(struct thread *td, uint32_t base)
143 {
144 struct user_segment_descriptor *sd;
145
146 if (td != curthread)
147 return;
148 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
149 critical_enter();
150 sd = PCPU_GET(gs32p);
151 sd->sd_lobase = base & 0xffffff;
152 sd->sd_hibase = (base >> 24) & 0xff;
153 critical_exit();
154 }
155
156 void
update_gdt_fsbase(struct thread * td,uint32_t base)157 update_gdt_fsbase(struct thread *td, uint32_t base)
158 {
159 struct user_segment_descriptor *sd;
160
161 if (td != curthread)
162 return;
163 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
164 critical_enter();
165 sd = PCPU_GET(fs32p);
166 sd->sd_lobase = base & 0xffffff;
167 sd->sd_hibase = (base >> 24) & 0xff;
168 critical_exit();
169 }
170
171 int
sysarch(struct thread * td,struct sysarch_args * uap)172 sysarch(struct thread *td, struct sysarch_args *uap)
173 {
174 struct pcb *pcb;
175 struct vm_map *map;
176 uint32_t i386base;
177 uint64_t a64base;
178 struct i386_ioperm_args iargs;
179 struct i386_get_xfpustate i386xfpu;
180 struct i386_set_pkru i386pkru;
181 struct amd64_get_xfpustate a64xfpu;
182 struct amd64_set_pkru a64pkru;
183 int error;
184
185 #ifdef CAPABILITY_MODE
186 /*
187 * When adding new operations, add a new case statement here to
188 * explicitly indicate whether or not the operation is safe to
189 * perform in capability mode.
190 */
191 switch (uap->op) {
192 case I386_GET_LDT:
193 case I386_SET_LDT:
194 case I386_GET_IOPERM:
195 case I386_GET_FSBASE:
196 case I386_SET_FSBASE:
197 case I386_GET_GSBASE:
198 case I386_SET_GSBASE:
199 case I386_GET_XFPUSTATE:
200 case I386_SET_PKRU:
201 case I386_CLEAR_PKRU:
202 case AMD64_GET_FSBASE:
203 case AMD64_SET_FSBASE:
204 case AMD64_GET_GSBASE:
205 case AMD64_SET_GSBASE:
206 case AMD64_GET_XFPUSTATE:
207 case AMD64_SET_PKRU:
208 case AMD64_CLEAR_PKRU:
209 case AMD64_GET_TLSBASE:
210 case AMD64_SET_TLSBASE:
211 case AMD64_DISABLE_TLSBASE:
212 break;
213
214 case I386_SET_IOPERM:
215 default:
216 if (CAP_TRACING(td))
217 ktrcapfail(CAPFAIL_SYSCALL, &uap->op);
218 if (IN_CAPABILITY_MODE(td))
219 return (ECAPMODE);
220 break;
221 }
222 #endif
223
224 if (uap->op == I386_GET_LDT || uap->op == I386_SET_LDT)
225 return (sysarch_ldt(td, uap, UIO_USERSPACE));
226
227 error = 0;
228 pcb = td->td_pcb;
229
230 /*
231 * XXXKIB check that the BSM generation code knows to encode
232 * the op argument.
233 */
234 AUDIT_ARG_CMD(uap->op);
235 switch (uap->op) {
236 case I386_GET_IOPERM:
237 case I386_SET_IOPERM:
238 if ((error = copyin(uap->parms, &iargs,
239 sizeof(struct i386_ioperm_args))) != 0)
240 return (error);
241 break;
242 case I386_GET_XFPUSTATE:
243 if ((error = copyin(uap->parms, &i386xfpu,
244 sizeof(struct i386_get_xfpustate))) != 0)
245 return (error);
246 a64xfpu.addr = (void *)(uintptr_t)i386xfpu.addr;
247 a64xfpu.len = i386xfpu.len;
248 break;
249 case I386_SET_PKRU:
250 case I386_CLEAR_PKRU:
251 if ((error = copyin(uap->parms, &i386pkru,
252 sizeof(struct i386_set_pkru))) != 0)
253 return (error);
254 a64pkru.addr = (void *)(uintptr_t)i386pkru.addr;
255 a64pkru.len = i386pkru.len;
256 a64pkru.keyidx = i386pkru.keyidx;
257 a64pkru.flags = i386pkru.flags;
258 break;
259 case AMD64_GET_XFPUSTATE:
260 if ((error = copyin(uap->parms, &a64xfpu,
261 sizeof(struct amd64_get_xfpustate))) != 0)
262 return (error);
263 break;
264 case AMD64_SET_PKRU:
265 case AMD64_CLEAR_PKRU:
266 if ((error = copyin(uap->parms, &a64pkru,
267 sizeof(struct amd64_set_pkru))) != 0)
268 return (error);
269 break;
270 default:
271 break;
272 }
273
274 switch (uap->op) {
275 case I386_GET_IOPERM:
276 error = amd64_get_ioperm(td, &iargs);
277 if (error == 0)
278 error = copyout(&iargs, uap->parms,
279 sizeof(struct i386_ioperm_args));
280 break;
281 case I386_SET_IOPERM:
282 error = amd64_set_ioperm(td, &iargs);
283 break;
284 case I386_GET_FSBASE:
285 update_pcb_bases(pcb);
286 i386base = pcb->pcb_fsbase;
287 error = copyout(&i386base, uap->parms, sizeof(i386base));
288 break;
289 case I386_SET_FSBASE:
290 error = copyin(uap->parms, &i386base, sizeof(i386base));
291 if (error == 0) {
292 set_pcb_flags(pcb, PCB_FULL_IRET);
293 pcb->pcb_fsbase = i386base;
294 td->td_frame->tf_fs = _ufssel;
295 update_gdt_fsbase(td, i386base);
296 }
297 break;
298 case I386_GET_GSBASE:
299 update_pcb_bases(pcb);
300 i386base = pcb->pcb_gsbase;
301 error = copyout(&i386base, uap->parms, sizeof(i386base));
302 break;
303 case I386_SET_GSBASE:
304 error = copyin(uap->parms, &i386base, sizeof(i386base));
305 if (error == 0) {
306 set_pcb_flags(pcb, PCB_FULL_IRET);
307 pcb->pcb_gsbase = i386base;
308 td->td_frame->tf_gs = _ugssel;
309 update_gdt_gsbase(td, i386base);
310 }
311 break;
312 case AMD64_GET_FSBASE:
313 update_pcb_bases(pcb);
314 error = copyout(&pcb->pcb_fsbase, uap->parms,
315 sizeof(pcb->pcb_fsbase));
316 break;
317 case AMD64_GET_TLSBASE:
318 if ((pcb->pcb_flags & PCB_TLSBASE) == 0) {
319 error = ESRCH;
320 } else {
321 error = copyout(&pcb->pcb_tlsbase, uap->parms,
322 sizeof(pcb->pcb_tlsbase));
323 }
324 break;
325
326 case AMD64_SET_FSBASE:
327 case AMD64_SET_TLSBASE:
328 error = copyin(uap->parms, &a64base, sizeof(a64base));
329 if (error == 0) {
330 if (a64base < curproc->p_sysent->sv_maxuser) {
331 set_pcb_flags(pcb, PCB_FULL_IRET);
332 pcb->pcb_fsbase = a64base;
333 td->td_frame->tf_fs = _ufssel;
334 if (uap->op == AMD64_SET_TLSBASE) {
335 pcb->pcb_tlsbase = a64base;
336 set_pcb_flags(pcb, PCB_TLSBASE);
337 }
338 } else
339 error = EINVAL;
340 }
341 break;
342
343 case AMD64_GET_GSBASE:
344 update_pcb_bases(pcb);
345 error = copyout(&pcb->pcb_gsbase, uap->parms,
346 sizeof(pcb->pcb_gsbase));
347 break;
348
349 case AMD64_SET_GSBASE:
350 error = copyin(uap->parms, &a64base, sizeof(a64base));
351 if (error == 0) {
352 if (a64base < curproc->p_sysent->sv_maxuser) {
353 set_pcb_flags(pcb, PCB_FULL_IRET);
354 pcb->pcb_gsbase = a64base;
355 td->td_frame->tf_gs = _ugssel;
356 } else
357 error = EINVAL;
358 }
359 break;
360
361 case I386_GET_XFPUSTATE:
362 case AMD64_GET_XFPUSTATE:
363 if (a64xfpu.len > cpu_max_ext_state_size -
364 sizeof(struct savefpu))
365 return (EINVAL);
366 fpugetregs(td);
367 error = copyout((char *)(get_pcb_user_save_td(td) + 1),
368 a64xfpu.addr, a64xfpu.len);
369 break;
370
371 case I386_SET_PKRU:
372 case AMD64_SET_PKRU:
373 /*
374 * Read-lock the map to synchronize with parallel
375 * pmap_vmspace_copy() on fork.
376 */
377 map = &td->td_proc->p_vmspace->vm_map;
378 vm_map_lock_read(map);
379 error = pmap_pkru_set(PCPU_GET(curpmap),
380 (vm_offset_t)a64pkru.addr, (vm_offset_t)a64pkru.addr +
381 a64pkru.len, a64pkru.keyidx, a64pkru.flags);
382 vm_map_unlock_read(map);
383 break;
384
385 case I386_CLEAR_PKRU:
386 case AMD64_CLEAR_PKRU:
387 if (a64pkru.flags != 0 || a64pkru.keyidx != 0) {
388 error = EINVAL;
389 break;
390 }
391 map = &td->td_proc->p_vmspace->vm_map;
392 vm_map_lock_read(map);
393 error = pmap_pkru_clear(PCPU_GET(curpmap),
394 (vm_offset_t)a64pkru.addr,
395 (vm_offset_t)a64pkru.addr + a64pkru.len);
396 vm_map_unlock_read(map);
397 break;
398
399 case AMD64_DISABLE_TLSBASE:
400 clear_pcb_flags(pcb, PCB_TLSBASE);
401 update_pcb_bases(pcb);
402 break;
403
404 default:
405 error = EINVAL;
406 break;
407 }
408 return (error);
409 }
410
411 int
amd64_set_ioperm(struct thread * td,struct i386_ioperm_args * uap)412 amd64_set_ioperm(struct thread *td, struct i386_ioperm_args *uap)
413 {
414 char *iomap;
415 struct amd64tss *tssp;
416 struct system_segment_descriptor *tss_sd;
417 struct pcb *pcb;
418 u_int i;
419 int error;
420
421 if ((error = priv_check(td, PRIV_IO)) != 0)
422 return (error);
423 if ((error = securelevel_gt(td->td_ucred, 0)) != 0)
424 return (error);
425 if (uap->start > uap->start + uap->length ||
426 uap->start + uap->length > IOPAGES * PAGE_SIZE * NBBY)
427 return (EINVAL);
428
429 /*
430 * XXX
431 * While this is restricted to root, we should probably figure out
432 * whether any other driver is using this i/o address, as so not to
433 * cause confusion. This probably requires a global 'usage registry'.
434 */
435 pcb = td->td_pcb;
436 if (pcb->pcb_tssp == NULL) {
437 tssp = kmem_malloc(ctob(IOPAGES + 1), M_WAITOK);
438 pmap_pti_add_kva((vm_offset_t)tssp, (vm_offset_t)tssp +
439 ctob(IOPAGES + 1), false);
440 iomap = (char *)&tssp[1];
441 memset(iomap, 0xff, IOPERM_BITMAP_SIZE);
442 critical_enter();
443 /* Takes care of tss_rsp0. */
444 memcpy(tssp, PCPU_PTR(common_tss), sizeof(struct amd64tss));
445 tssp->tss_iobase = sizeof(*tssp);
446 pcb->pcb_tssp = tssp;
447 tss_sd = PCPU_GET(tss);
448 tss_sd->sd_lobase = (u_long)tssp & 0xffffff;
449 tss_sd->sd_hibase = ((u_long)tssp >> 24) & 0xfffffffffful;
450 tss_sd->sd_type = SDT_SYSTSS;
451 ltr(GSEL(GPROC0_SEL, SEL_KPL));
452 PCPU_SET(tssp, tssp);
453 critical_exit();
454 } else
455 iomap = (char *)&pcb->pcb_tssp[1];
456 for (i = uap->start; i < uap->start + uap->length; i++) {
457 if (uap->enable)
458 iomap[i >> 3] &= ~(1 << (i & 7));
459 else
460 iomap[i >> 3] |= (1 << (i & 7));
461 }
462 return (error);
463 }
464
465 int
amd64_get_ioperm(struct thread * td,struct i386_ioperm_args * uap)466 amd64_get_ioperm(struct thread *td, struct i386_ioperm_args *uap)
467 {
468 int i, state;
469 char *iomap;
470
471 if (uap->start >= IOPAGES * PAGE_SIZE * NBBY)
472 return (EINVAL);
473 if (td->td_pcb->pcb_tssp == NULL) {
474 uap->length = 0;
475 goto done;
476 }
477
478 iomap = (char *)&td->td_pcb->pcb_tssp[1];
479
480 i = uap->start;
481 state = (iomap[i >> 3] >> (i & 7)) & 1;
482 uap->enable = !state;
483 uap->length = 1;
484
485 for (i = uap->start + 1; i < IOPAGES * PAGE_SIZE * NBBY; i++) {
486 if (state != ((iomap[i >> 3] >> (i & 7)) & 1))
487 break;
488 uap->length++;
489 }
490
491 done:
492 return (0);
493 }
494
495 /*
496 * Update the GDT entry pointing to the LDT to point to the LDT of the
497 * current process.
498 */
499 static void
set_user_ldt(struct mdproc * mdp)500 set_user_ldt(struct mdproc *mdp)
501 {
502
503 *PCPU_GET(ldt) = mdp->md_ldt_sd;
504 lldt(GSEL(GUSERLDT_SEL, SEL_KPL));
505 }
506
507 static void
set_user_ldt_rv(void * arg)508 set_user_ldt_rv(void *arg)
509 {
510 struct proc *orig, *target;
511 struct proc_ldt *ldt;
512
513 orig = arg;
514 target = curthread->td_proc;
515
516 ldt = (void *)atomic_load_acq_ptr((uintptr_t *)&orig->p_md.md_ldt);
517 if (target->p_md.md_ldt != ldt)
518 return;
519
520 set_user_ldt(&target->p_md);
521 }
522
523 struct proc_ldt *
user_ldt_alloc(struct proc * p,int force)524 user_ldt_alloc(struct proc *p, int force)
525 {
526 struct proc_ldt *pldt, *new_ldt;
527 struct mdproc *mdp;
528 struct soft_segment_descriptor sldt;
529 vm_offset_t sva;
530 vm_size_t sz;
531
532 mtx_assert(&dt_lock, MA_OWNED);
533 mdp = &p->p_md;
534 if (!force && mdp->md_ldt != NULL)
535 return (mdp->md_ldt);
536 mtx_unlock(&dt_lock);
537 new_ldt = malloc(sizeof(struct proc_ldt), M_SUBPROC, M_WAITOK);
538 sz = max_ldt_segment * sizeof(struct user_segment_descriptor);
539 new_ldt->ldt_base = kmem_malloc(sz, M_WAITOK | M_ZERO);
540 sva = (uintptr_t)new_ldt->ldt_base;
541 pmap_pti_add_kva(sva, sva + sz, false);
542 new_ldt->ldt_refcnt = 1;
543 sldt.ssd_base = sva;
544 sldt.ssd_limit = sz - 1;
545 sldt.ssd_type = SDT_SYSLDT;
546 sldt.ssd_dpl = SEL_KPL;
547 sldt.ssd_p = 1;
548 sldt.ssd_long = 0;
549 sldt.ssd_def32 = 0;
550 sldt.ssd_gran = 0;
551 mtx_lock(&dt_lock);
552 pldt = mdp->md_ldt;
553 if (pldt != NULL && !force) {
554 pmap_pti_remove_kva(sva, sva + sz);
555 kmem_free(new_ldt->ldt_base, sz);
556 free(new_ldt, M_SUBPROC);
557 return (pldt);
558 }
559
560 if (pldt != NULL) {
561 bcopy(pldt->ldt_base, new_ldt->ldt_base, max_ldt_segment *
562 sizeof(struct user_segment_descriptor));
563 user_ldt_derefl(pldt);
564 }
565 critical_enter();
566 ssdtosyssd(&sldt, &p->p_md.md_ldt_sd);
567 atomic_thread_fence_rel();
568 mdp->md_ldt = new_ldt;
569 critical_exit();
570 smp_rendezvous(NULL, set_user_ldt_rv, NULL, p);
571
572 return (mdp->md_ldt);
573 }
574
575 void
user_ldt_free(struct thread * td)576 user_ldt_free(struct thread *td)
577 {
578 struct proc *p = td->td_proc;
579 struct mdproc *mdp = &p->p_md;
580 struct proc_ldt *pldt;
581
582 mtx_lock(&dt_lock);
583 if ((pldt = mdp->md_ldt) == NULL) {
584 mtx_unlock(&dt_lock);
585 return;
586 }
587
588 critical_enter();
589 mdp->md_ldt = NULL;
590 atomic_thread_fence_rel();
591 bzero(&mdp->md_ldt_sd, sizeof(mdp->md_ldt_sd));
592 if (td == curthread)
593 lldt(GSEL(GNULL_SEL, SEL_KPL));
594 critical_exit();
595 user_ldt_deref(pldt);
596 }
597
598 static void
user_ldt_derefl(struct proc_ldt * pldt)599 user_ldt_derefl(struct proc_ldt *pldt)
600 {
601 vm_offset_t sva;
602 vm_size_t sz;
603
604 if (--pldt->ldt_refcnt == 0) {
605 sva = (vm_offset_t)pldt->ldt_base;
606 sz = max_ldt_segment * sizeof(struct user_segment_descriptor);
607 pmap_pti_remove_kva(sva, sva + sz);
608 kmem_free(pldt->ldt_base, sz);
609 free(pldt, M_SUBPROC);
610 }
611 }
612
613 static void
user_ldt_deref(struct proc_ldt * pldt)614 user_ldt_deref(struct proc_ldt *pldt)
615 {
616
617 mtx_assert(&dt_lock, MA_OWNED);
618 user_ldt_derefl(pldt);
619 mtx_unlock(&dt_lock);
620 }
621
622 /*
623 * Note for the authors of compat layers (linux, etc): copyout() in
624 * the function below is not a problem since it presents data in
625 * arch-specific format (i.e. i386-specific in this case), not in
626 * the OS-specific one.
627 */
628 int
amd64_get_ldt(struct thread * td,struct i386_ldt_args * uap)629 amd64_get_ldt(struct thread *td, struct i386_ldt_args *uap)
630 {
631 struct proc_ldt *pldt;
632 struct user_segment_descriptor *lp;
633 uint64_t *data;
634 u_int i, num;
635 int error;
636
637 #ifdef DEBUG
638 printf("amd64_get_ldt: start=%u num=%u descs=%p\n",
639 uap->start, uap->num, (void *)uap->descs);
640 #endif
641
642 pldt = td->td_proc->p_md.md_ldt;
643 if (pldt == NULL || uap->start >= max_ldt_segment || uap->num == 0) {
644 td->td_retval[0] = 0;
645 return (0);
646 }
647 num = min(uap->num, max_ldt_segment - uap->start);
648 lp = &((struct user_segment_descriptor *)(pldt->ldt_base))[uap->start];
649 data = malloc(num * sizeof(struct user_segment_descriptor), M_TEMP,
650 M_WAITOK);
651 mtx_lock(&dt_lock);
652 for (i = 0; i < num; i++)
653 data[i] = ((volatile uint64_t *)lp)[i];
654 mtx_unlock(&dt_lock);
655 error = copyout(data, uap->descs, num *
656 sizeof(struct user_segment_descriptor));
657 free(data, M_TEMP);
658 if (error == 0)
659 td->td_retval[0] = num;
660 return (error);
661 }
662
663 int
amd64_set_ldt(struct thread * td,struct i386_ldt_args * uap,struct user_segment_descriptor * descs)664 amd64_set_ldt(struct thread *td, struct i386_ldt_args *uap,
665 struct user_segment_descriptor *descs)
666 {
667 struct mdproc *mdp;
668 struct proc_ldt *pldt;
669 struct user_segment_descriptor *dp;
670 struct proc *p;
671 u_int largest_ld, i;
672 int error;
673
674 #ifdef DEBUG
675 printf("amd64_set_ldt: start=%u num=%u descs=%p\n",
676 uap->start, uap->num, (void *)uap->descs);
677 #endif
678 mdp = &td->td_proc->p_md;
679 error = 0;
680
681 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
682 p = td->td_proc;
683 if (descs == NULL) {
684 /* Free descriptors */
685 if (uap->start == 0 && uap->num == 0)
686 uap->num = max_ldt_segment;
687 if (uap->num == 0)
688 return (EINVAL);
689 if ((pldt = mdp->md_ldt) == NULL ||
690 uap->start >= max_ldt_segment)
691 return (0);
692 largest_ld = uap->start + uap->num;
693 if (largest_ld > max_ldt_segment)
694 largest_ld = max_ldt_segment;
695 if (largest_ld < uap->start)
696 return (EINVAL);
697 mtx_lock(&dt_lock);
698 for (i = uap->start; i < largest_ld; i++)
699 ((volatile uint64_t *)(pldt->ldt_base))[i] = 0;
700 mtx_unlock(&dt_lock);
701 return (0);
702 }
703
704 if (!(uap->start == LDT_AUTO_ALLOC && uap->num == 1)) {
705 /* verify range of descriptors to modify */
706 largest_ld = uap->start + uap->num;
707 if (uap->start >= max_ldt_segment ||
708 largest_ld > max_ldt_segment ||
709 largest_ld < uap->start)
710 return (EINVAL);
711 }
712
713 /* Check descriptors for access violations */
714 for (i = 0; i < uap->num; i++) {
715 dp = &descs[i];
716
717 switch (dp->sd_type) {
718 case SDT_SYSNULL: /* system null */
719 dp->sd_p = 0;
720 break;
721 case SDT_SYS286TSS:
722 case SDT_SYSLDT:
723 case SDT_SYS286BSY:
724 case SDT_SYS286CGT:
725 case SDT_SYSTASKGT:
726 case SDT_SYS286IGT:
727 case SDT_SYS286TGT:
728 case SDT_SYSNULL2:
729 case SDT_SYSTSS:
730 case SDT_SYSNULL3:
731 case SDT_SYSBSY:
732 case SDT_SYSCGT:
733 case SDT_SYSNULL4:
734 case SDT_SYSIGT:
735 case SDT_SYSTGT:
736 return (EACCES);
737
738 /* memory segment types */
739 case SDT_MEMEC: /* memory execute only conforming */
740 case SDT_MEMEAC: /* memory execute only accessed conforming */
741 case SDT_MEMERC: /* memory execute read conforming */
742 case SDT_MEMERAC: /* memory execute read accessed conforming */
743 /* Must be "present" if executable and conforming. */
744 if (dp->sd_p == 0)
745 return (EACCES);
746 break;
747 case SDT_MEMRO: /* memory read only */
748 case SDT_MEMROA: /* memory read only accessed */
749 case SDT_MEMRW: /* memory read write */
750 case SDT_MEMRWA: /* memory read write accessed */
751 case SDT_MEMROD: /* memory read only expand dwn limit */
752 case SDT_MEMRODA: /* memory read only expand dwn lim accessed */
753 case SDT_MEMRWD: /* memory read write expand dwn limit */
754 case SDT_MEMRWDA: /* memory read write expand dwn lim acessed */
755 case SDT_MEME: /* memory execute only */
756 case SDT_MEMEA: /* memory execute only accessed */
757 case SDT_MEMER: /* memory execute read */
758 case SDT_MEMERA: /* memory execute read accessed */
759 break;
760 default:
761 return(EINVAL);
762 }
763
764 /* Only user (ring-3) descriptors may be present. */
765 if ((dp->sd_p != 0) && (dp->sd_dpl != SEL_UPL))
766 return (EACCES);
767 }
768
769 if (uap->start == LDT_AUTO_ALLOC && uap->num == 1) {
770 /* Allocate a free slot */
771 mtx_lock(&dt_lock);
772 pldt = user_ldt_alloc(p, 0);
773 if (pldt == NULL) {
774 mtx_unlock(&dt_lock);
775 return (ENOMEM);
776 }
777
778 /*
779 * start scanning a bit up to leave room for NVidia and
780 * Wine, which still user the "Blat" method of allocation.
781 */
782 i = 16;
783 dp = &((struct user_segment_descriptor *)(pldt->ldt_base))[i];
784 for (; i < max_ldt_segment; ++i, ++dp) {
785 if (dp->sd_type == SDT_SYSNULL)
786 break;
787 }
788 if (i >= max_ldt_segment) {
789 mtx_unlock(&dt_lock);
790 return (ENOSPC);
791 }
792 uap->start = i;
793 error = amd64_set_ldt_data(td, i, 1, descs);
794 mtx_unlock(&dt_lock);
795 } else {
796 largest_ld = uap->start + uap->num;
797 if (largest_ld > max_ldt_segment)
798 return (EINVAL);
799 mtx_lock(&dt_lock);
800 if (user_ldt_alloc(p, 0) != NULL) {
801 error = amd64_set_ldt_data(td, uap->start, uap->num,
802 descs);
803 }
804 mtx_unlock(&dt_lock);
805 }
806 if (error == 0)
807 td->td_retval[0] = uap->start;
808 return (error);
809 }
810
811 int
amd64_set_ldt_data(struct thread * td,int start,int num,struct user_segment_descriptor * descs)812 amd64_set_ldt_data(struct thread *td, int start, int num,
813 struct user_segment_descriptor *descs)
814 {
815 struct mdproc *mdp;
816 struct proc_ldt *pldt;
817 volatile uint64_t *dst, *src;
818 int i;
819
820 mtx_assert(&dt_lock, MA_OWNED);
821
822 mdp = &td->td_proc->p_md;
823 pldt = mdp->md_ldt;
824 dst = (volatile uint64_t *)(pldt->ldt_base);
825 src = (volatile uint64_t *)descs;
826 for (i = 0; i < num; i++)
827 dst[start + i] = src[i];
828 return (0);
829 }
830