xref: /linux/drivers/net/ethernet/stmicro/stmmac/common.h (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3   STMMAC Common Header File
4 
5   Copyright (C) 2007-2009  STMicroelectronics Ltd
6 
7 
8   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10 
11 #ifndef __COMMON_H__
12 #define __COMMON_H__
13 
14 #include <linux/etherdevice.h>
15 #include <linux/netdevice.h>
16 #include <linux/stmmac.h>
17 #include <linux/phy.h>
18 #include <linux/pcs/pcs-xpcs.h>
19 #include <linux/module.h>
20 #if IS_ENABLED(CONFIG_VLAN_8021Q)
21 #define STMMAC_VLAN_TAG_USED
22 #include <linux/if_vlan.h>
23 #endif
24 
25 #include "descs.h"
26 #include "hwif.h"
27 #include "mmc.h"
28 
29 /* Synopsys Core versions */
30 #define	DWMAC_CORE_3_40		0x34
31 #define	DWMAC_CORE_3_50		0x35
32 #define	DWMAC_CORE_3_70		0x37
33 #define	DWMAC_CORE_4_00		0x40
34 #define DWMAC_CORE_4_10		0x41
35 #define DWMAC_CORE_5_00		0x50
36 #define DWMAC_CORE_5_10		0x51
37 #define DWMAC_CORE_5_20		0x52
38 #define DWXGMAC_CORE_2_10	0x21
39 #define DWXGMAC_CORE_2_20	0x22
40 #define DWXLGMAC_CORE_2_00	0x20
41 
42 /* Device ID */
43 #define DWXGMAC_ID		0x76
44 #define DWXLGMAC_ID		0x27
45 
46 #define STMMAC_CHAN0	0	/* Always supported and default for all chips */
47 
48 /* TX and RX Descriptor Length, these need to be power of two.
49  * TX descriptor length less than 64 may cause transmit queue timed out error.
50  * RX descriptor length less than 64 may cause inconsistent Rx chain error.
51  */
52 #define DMA_MIN_TX_SIZE		64
53 #define DMA_MAX_TX_SIZE		1024
54 #define DMA_DEFAULT_TX_SIZE	512
55 #define DMA_MIN_RX_SIZE		64
56 #define DMA_MAX_RX_SIZE		1024
57 #define DMA_DEFAULT_RX_SIZE	512
58 #define STMMAC_GET_ENTRY(x, size)	((x + 1) & (size - 1))
59 
60 #undef FRAME_FILTER_DEBUG
61 /* #define FRAME_FILTER_DEBUG */
62 
63 struct stmmac_q_tx_stats {
64 	u64_stats_t tx_bytes;
65 	u64_stats_t tx_set_ic_bit;
66 	u64_stats_t tx_tso_frames;
67 	u64_stats_t tx_tso_nfrags;
68 };
69 
70 struct stmmac_napi_tx_stats {
71 	u64_stats_t tx_packets;
72 	u64_stats_t tx_pkt_n;
73 	u64_stats_t poll;
74 	u64_stats_t tx_clean;
75 	u64_stats_t tx_set_ic_bit;
76 };
77 
78 struct stmmac_txq_stats {
79 	/* Updates protected by tx queue lock. */
80 	struct u64_stats_sync q_syncp;
81 	struct stmmac_q_tx_stats q;
82 
83 	/* Updates protected by NAPI poll logic. */
84 	struct u64_stats_sync napi_syncp;
85 	struct stmmac_napi_tx_stats napi;
86 } ____cacheline_aligned_in_smp;
87 
88 struct stmmac_napi_rx_stats {
89 	u64_stats_t rx_bytes;
90 	u64_stats_t rx_packets;
91 	u64_stats_t rx_pkt_n;
92 	u64_stats_t poll;
93 };
94 
95 struct stmmac_rxq_stats {
96 	/* Updates protected by NAPI poll logic. */
97 	struct u64_stats_sync napi_syncp;
98 	struct stmmac_napi_rx_stats napi;
99 } ____cacheline_aligned_in_smp;
100 
101 /* Updates on each CPU protected by not allowing nested irqs. */
102 struct stmmac_pcpu_stats {
103 	struct u64_stats_sync syncp;
104 	u64_stats_t rx_normal_irq_n[MTL_MAX_RX_QUEUES];
105 	u64_stats_t tx_normal_irq_n[MTL_MAX_TX_QUEUES];
106 };
107 
108 /* Extra statistic and debug information exposed by ethtool */
109 struct stmmac_extra_stats {
110 	/* Transmit errors */
111 	unsigned long tx_underflow ____cacheline_aligned;
112 	unsigned long tx_carrier;
113 	unsigned long tx_losscarrier;
114 	unsigned long vlan_tag;
115 	unsigned long tx_deferred;
116 	unsigned long tx_vlan;
117 	unsigned long tx_jabber;
118 	unsigned long tx_frame_flushed;
119 	unsigned long tx_payload_error;
120 	unsigned long tx_ip_header_error;
121 	unsigned long tx_collision;
122 	/* Receive errors */
123 	unsigned long rx_desc;
124 	unsigned long sa_filter_fail;
125 	unsigned long overflow_error;
126 	unsigned long ipc_csum_error;
127 	unsigned long rx_collision;
128 	unsigned long rx_crc_errors;
129 	unsigned long dribbling_bit;
130 	unsigned long rx_length;
131 	unsigned long rx_mii;
132 	unsigned long rx_multicast;
133 	unsigned long rx_gmac_overflow;
134 	unsigned long rx_watchdog;
135 	unsigned long da_rx_filter_fail;
136 	unsigned long sa_rx_filter_fail;
137 	unsigned long rx_missed_cntr;
138 	unsigned long rx_overflow_cntr;
139 	unsigned long rx_vlan;
140 	unsigned long rx_split_hdr_pkt_n;
141 	/* Tx/Rx IRQ error info */
142 	unsigned long tx_undeflow_irq;
143 	unsigned long tx_process_stopped_irq;
144 	unsigned long tx_jabber_irq;
145 	unsigned long rx_overflow_irq;
146 	unsigned long rx_buf_unav_irq;
147 	unsigned long rx_process_stopped_irq;
148 	unsigned long rx_watchdog_irq;
149 	unsigned long tx_early_irq;
150 	unsigned long fatal_bus_error_irq;
151 	/* Tx/Rx IRQ Events */
152 	unsigned long rx_early_irq;
153 	unsigned long threshold;
154 	unsigned long irq_receive_pmt_irq_n;
155 	/* MMC info */
156 	unsigned long mmc_tx_irq_n;
157 	unsigned long mmc_rx_irq_n;
158 	unsigned long mmc_rx_csum_offload_irq_n;
159 	/* EEE */
160 	unsigned long irq_tx_path_in_lpi_mode_n;
161 	unsigned long irq_tx_path_exit_lpi_mode_n;
162 	unsigned long irq_rx_path_in_lpi_mode_n;
163 	unsigned long irq_rx_path_exit_lpi_mode_n;
164 	unsigned long phy_eee_wakeup_error_n;
165 	/* Extended RDES status */
166 	unsigned long ip_hdr_err;
167 	unsigned long ip_payload_err;
168 	unsigned long ip_csum_bypassed;
169 	unsigned long ipv4_pkt_rcvd;
170 	unsigned long ipv6_pkt_rcvd;
171 	unsigned long no_ptp_rx_msg_type_ext;
172 	unsigned long ptp_rx_msg_type_sync;
173 	unsigned long ptp_rx_msg_type_follow_up;
174 	unsigned long ptp_rx_msg_type_delay_req;
175 	unsigned long ptp_rx_msg_type_delay_resp;
176 	unsigned long ptp_rx_msg_type_pdelay_req;
177 	unsigned long ptp_rx_msg_type_pdelay_resp;
178 	unsigned long ptp_rx_msg_type_pdelay_follow_up;
179 	unsigned long ptp_rx_msg_type_announce;
180 	unsigned long ptp_rx_msg_type_management;
181 	unsigned long ptp_rx_msg_pkt_reserved_type;
182 	unsigned long ptp_frame_type;
183 	unsigned long ptp_ver;
184 	unsigned long timestamp_dropped;
185 	unsigned long av_pkt_rcvd;
186 	unsigned long av_tagged_pkt_rcvd;
187 	unsigned long vlan_tag_priority_val;
188 	unsigned long l3_filter_match;
189 	unsigned long l4_filter_match;
190 	unsigned long l3_l4_filter_no_match;
191 	/* PCS */
192 	unsigned long irq_pcs_ane_n;
193 	unsigned long irq_pcs_link_n;
194 	unsigned long irq_rgmii_n;
195 	unsigned long pcs_link;
196 	unsigned long pcs_duplex;
197 	unsigned long pcs_speed;
198 	/* debug register */
199 	unsigned long mtl_tx_status_fifo_full;
200 	unsigned long mtl_tx_fifo_not_empty;
201 	unsigned long mmtl_fifo_ctrl;
202 	unsigned long mtl_tx_fifo_read_ctrl_write;
203 	unsigned long mtl_tx_fifo_read_ctrl_wait;
204 	unsigned long mtl_tx_fifo_read_ctrl_read;
205 	unsigned long mtl_tx_fifo_read_ctrl_idle;
206 	unsigned long mac_tx_in_pause;
207 	unsigned long mac_tx_frame_ctrl_xfer;
208 	unsigned long mac_tx_frame_ctrl_idle;
209 	unsigned long mac_tx_frame_ctrl_wait;
210 	unsigned long mac_tx_frame_ctrl_pause;
211 	unsigned long mac_gmii_tx_proto_engine;
212 	unsigned long mtl_rx_fifo_fill_level_full;
213 	unsigned long mtl_rx_fifo_fill_above_thresh;
214 	unsigned long mtl_rx_fifo_fill_below_thresh;
215 	unsigned long mtl_rx_fifo_fill_level_empty;
216 	unsigned long mtl_rx_fifo_read_ctrl_flush;
217 	unsigned long mtl_rx_fifo_read_ctrl_read_data;
218 	unsigned long mtl_rx_fifo_read_ctrl_status;
219 	unsigned long mtl_rx_fifo_read_ctrl_idle;
220 	unsigned long mtl_rx_fifo_ctrl_active;
221 	unsigned long mac_rx_frame_ctrl_fifo;
222 	unsigned long mac_gmii_rx_proto_engine;
223 	/* EST */
224 	unsigned long mtl_est_cgce;
225 	unsigned long mtl_est_hlbs;
226 	unsigned long mtl_est_hlbf;
227 	unsigned long mtl_est_btre;
228 	unsigned long mtl_est_btrlm;
229 	unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES];
230 	unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES];
231 	/* per queue statistics */
232 	struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
233 	struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
234 	struct stmmac_pcpu_stats __percpu *pcpu_stats;
235 	unsigned long rx_dropped;
236 	unsigned long rx_errors;
237 	unsigned long tx_dropped;
238 	unsigned long tx_errors;
239 };
240 
241 /* Safety Feature statistics exposed by ethtool */
242 struct stmmac_safety_stats {
243 	unsigned long mac_errors[32];
244 	unsigned long mtl_errors[32];
245 	unsigned long dma_errors[32];
246 	unsigned long dma_dpp_errors[32];
247 };
248 
249 /* Number of fields in Safety Stats */
250 #define STMMAC_SAFETY_FEAT_SIZE	\
251 	(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
252 
253 /* CSR Frequency Access Defines*/
254 #define CSR_F_35M	35000000
255 #define CSR_F_60M	60000000
256 #define CSR_F_100M	100000000
257 #define CSR_F_150M	150000000
258 #define CSR_F_250M	250000000
259 #define CSR_F_300M	300000000
260 #define CSR_F_500M	500000000
261 #define CSR_F_800M	800000000
262 
263 #define	MAC_CSR_H_FRQ_MASK	0x20
264 
265 #define HASH_TABLE_SIZE 64
266 #define PAUSE_TIME 0xffff
267 
268 /* Flow Control defines */
269 #define FLOW_OFF	0
270 #define FLOW_RX		1
271 #define FLOW_TX		2
272 #define FLOW_AUTO	(FLOW_TX | FLOW_RX)
273 
274 /* PCS defines */
275 #define STMMAC_PCS_RGMII	(1 << 0)
276 #define STMMAC_PCS_SGMII	(1 << 1)
277 
278 #define SF_DMA_MODE 1		/* DMA STORE-AND-FORWARD Operation Mode */
279 
280 /* DMA HW feature register fields */
281 #define DMA_HW_FEAT_MIISEL	0x00000001	/* 10/100 Mbps Support */
282 #define DMA_HW_FEAT_GMIISEL	0x00000002	/* 1000 Mbps Support */
283 #define DMA_HW_FEAT_HDSEL	0x00000004	/* Half-Duplex Support */
284 #define DMA_HW_FEAT_EXTHASHEN	0x00000008	/* Expanded DA Hash Filter */
285 #define DMA_HW_FEAT_HASHSEL	0x00000010	/* HASH Filter */
286 #define DMA_HW_FEAT_ADDMAC	0x00000020	/* Multiple MAC Addr Reg */
287 #define DMA_HW_FEAT_PCSSEL	0x00000040	/* PCS registers */
288 #define DMA_HW_FEAT_L3L4FLTREN	0x00000080	/* Layer 3 & Layer 4 Feature */
289 #define DMA_HW_FEAT_SMASEL	0x00000100	/* SMA(MDIO) Interface */
290 #define DMA_HW_FEAT_RWKSEL	0x00000200	/* PMT Remote Wakeup */
291 #define DMA_HW_FEAT_MGKSEL	0x00000400	/* PMT Magic Packet */
292 #define DMA_HW_FEAT_MMCSEL	0x00000800	/* RMON Module */
293 #define DMA_HW_FEAT_TSVER1SEL	0x00001000	/* Only IEEE 1588-2002 */
294 #define DMA_HW_FEAT_TSVER2SEL	0x00002000	/* IEEE 1588-2008 PTPv2 */
295 #define DMA_HW_FEAT_EEESEL	0x00004000	/* Energy Efficient Ethernet */
296 #define DMA_HW_FEAT_AVSEL	0x00008000	/* AV Feature */
297 #define DMA_HW_FEAT_TXCOESEL	0x00010000	/* Checksum Offload in Tx */
298 #define DMA_HW_FEAT_RXTYP1COE	0x00020000	/* IP COE (Type 1) in Rx */
299 #define DMA_HW_FEAT_RXTYP2COE	0x00040000	/* IP COE (Type 2) in Rx */
300 #define DMA_HW_FEAT_RXFIFOSIZE	0x00080000	/* Rx FIFO > 2048 Bytes */
301 #define DMA_HW_FEAT_RXCHCNT	0x00300000	/* No. additional Rx Channels */
302 #define DMA_HW_FEAT_TXCHCNT	0x00c00000	/* No. additional Tx Channels */
303 #define DMA_HW_FEAT_ENHDESSEL	0x01000000	/* Alternate Descriptor */
304 /* Timestamping with Internal System Time */
305 #define DMA_HW_FEAT_INTTSEN	0x02000000
306 #define DMA_HW_FEAT_FLEXIPPSEN	0x04000000	/* Flexible PPS Output */
307 #define DMA_HW_FEAT_SAVLANINS	0x08000000	/* Source Addr or VLAN */
308 #define DMA_HW_FEAT_ACTPHYIF	0x70000000	/* Active/selected PHY iface */
309 #define DEFAULT_DMA_PBL		8
310 
311 /* MSI defines */
312 #define STMMAC_MSI_VEC_MAX	32
313 
314 /* PCS status and mask defines */
315 #define	PCS_ANE_IRQ		BIT(2)	/* PCS Auto-Negotiation */
316 #define	PCS_LINK_IRQ		BIT(1)	/* PCS Link */
317 #define	PCS_RGSMIIIS_IRQ	BIT(0)	/* RGMII or SMII Interrupt */
318 
319 /* Max/Min RI Watchdog Timer count value */
320 #define MAX_DMA_RIWT		0xff
321 #define MIN_DMA_RIWT		0x10
322 #define DEF_DMA_RIWT		0xa0
323 /* Tx coalesce parameters */
324 #define STMMAC_COAL_TX_TIMER	5000
325 #define STMMAC_MAX_COAL_TX_TICK	100000
326 #define STMMAC_TX_MAX_FRAMES	256
327 #define STMMAC_TX_FRAMES	25
328 #define STMMAC_RX_FRAMES	0
329 
330 /* Packets types */
331 enum packets_types {
332 	PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
333 	PACKET_PTPQ = 0x2, /* PTP Packets */
334 	PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
335 	PACKET_UPQ = 0x4, /* Untagged Packets */
336 	PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
337 };
338 
339 /* Rx IPC status */
340 enum rx_frame_status {
341 	good_frame = 0x0,
342 	discard_frame = 0x1,
343 	csum_none = 0x2,
344 	llc_snap = 0x4,
345 	dma_own = 0x8,
346 	rx_not_ls = 0x10,
347 };
348 
349 /* Tx status */
350 enum tx_frame_status {
351 	tx_done = 0x0,
352 	tx_not_ls = 0x1,
353 	tx_err = 0x2,
354 	tx_dma_own = 0x4,
355 	tx_err_bump_tc = 0x8,
356 };
357 
358 enum dma_irq_status {
359 	tx_hard_error = 0x1,
360 	tx_hard_error_bump_tc = 0x2,
361 	handle_rx = 0x4,
362 	handle_tx = 0x8,
363 };
364 
365 enum dma_irq_dir {
366 	DMA_DIR_RX = 0x1,
367 	DMA_DIR_TX = 0x2,
368 	DMA_DIR_RXTX = 0x3,
369 };
370 
371 enum request_irq_err {
372 	REQ_IRQ_ERR_ALL,
373 	REQ_IRQ_ERR_TX,
374 	REQ_IRQ_ERR_RX,
375 	REQ_IRQ_ERR_SFTY,
376 	REQ_IRQ_ERR_SFTY_UE,
377 	REQ_IRQ_ERR_SFTY_CE,
378 	REQ_IRQ_ERR_LPI,
379 	REQ_IRQ_ERR_WOL,
380 	REQ_IRQ_ERR_MAC,
381 	REQ_IRQ_ERR_NO,
382 };
383 
384 /* EEE and LPI defines */
385 #define	CORE_IRQ_TX_PATH_IN_LPI_MODE	(1 << 0)
386 #define	CORE_IRQ_TX_PATH_EXIT_LPI_MODE	(1 << 1)
387 #define	CORE_IRQ_RX_PATH_IN_LPI_MODE	(1 << 2)
388 #define	CORE_IRQ_RX_PATH_EXIT_LPI_MODE	(1 << 3)
389 
390 /* FPE defines */
391 #define FPE_EVENT_UNKNOWN		0
392 #define FPE_EVENT_TRSP			BIT(0)
393 #define FPE_EVENT_TVER			BIT(1)
394 #define FPE_EVENT_RRSP			BIT(2)
395 #define FPE_EVENT_RVER			BIT(3)
396 
397 #define CORE_IRQ_MTL_RX_OVERFLOW	BIT(8)
398 
399 /* Physical Coding Sublayer */
400 struct rgmii_adv {
401 	unsigned int pause;
402 	unsigned int duplex;
403 	unsigned int lp_pause;
404 	unsigned int lp_duplex;
405 };
406 
407 #define STMMAC_PCS_PAUSE	1
408 #define STMMAC_PCS_ASYM_PAUSE	2
409 
410 /* DMA HW capabilities */
411 struct dma_features {
412 	unsigned int mbps_10_100;
413 	unsigned int mbps_1000;
414 	unsigned int half_duplex;
415 	unsigned int hash_filter;
416 	unsigned int multi_addr;
417 	unsigned int pcs;
418 	unsigned int sma_mdio;
419 	unsigned int pmt_remote_wake_up;
420 	unsigned int pmt_magic_frame;
421 	unsigned int rmon;
422 	/* IEEE 1588-2002 */
423 	unsigned int time_stamp;
424 	/* IEEE 1588-2008 */
425 	unsigned int atime_stamp;
426 	/* 802.3az - Energy-Efficient Ethernet (EEE) */
427 	unsigned int eee;
428 	unsigned int av;
429 	unsigned int hash_tb_sz;
430 	unsigned int tsoen;
431 	/* TX and RX csum */
432 	unsigned int tx_coe;
433 	unsigned int rx_coe;
434 	unsigned int rx_coe_type1;
435 	unsigned int rx_coe_type2;
436 	unsigned int rxfifo_over_2048;
437 	/* TX and RX number of channels */
438 	unsigned int number_rx_channel;
439 	unsigned int number_tx_channel;
440 	/* TX and RX number of queues */
441 	unsigned int number_rx_queues;
442 	unsigned int number_tx_queues;
443 	/* PPS output */
444 	unsigned int pps_out_num;
445 	/* Number of Traffic Classes */
446 	unsigned int numtc;
447 	/* DCB Feature Enable */
448 	unsigned int dcben;
449 	/* IEEE 1588 High Word Register Enable */
450 	unsigned int advthword;
451 	/* PTP Offload Enable */
452 	unsigned int ptoen;
453 	/* One-Step Timestamping Enable */
454 	unsigned int osten;
455 	/* Priority-Based Flow Control Enable */
456 	unsigned int pfcen;
457 	/* Alternate (enhanced) DESC mode */
458 	unsigned int enh_desc;
459 	/* TX and RX FIFO sizes */
460 	unsigned int tx_fifo_size;
461 	unsigned int rx_fifo_size;
462 	/* Automotive Safety Package */
463 	unsigned int asp;
464 	/* RX Parser */
465 	unsigned int frpsel;
466 	unsigned int frpbs;
467 	unsigned int frpes;
468 	unsigned int addr64;
469 	unsigned int host_dma_width;
470 	unsigned int rssen;
471 	unsigned int vlhash;
472 	unsigned int sphen;
473 	unsigned int vlins;
474 	unsigned int dvlan;
475 	unsigned int l3l4fnum;
476 	unsigned int arpoffsel;
477 	/* One Step for PTP over UDP/IP Feature Enable */
478 	unsigned int pou_ost_en;
479 	/* Tx Timestamp FIFO Depth */
480 	unsigned int ttsfd;
481 	/* Queue/Channel-Based VLAN tag insertion on Tx */
482 	unsigned int cbtisel;
483 	/* Supported Parallel Instruction Processor Engines */
484 	unsigned int frppipe_num;
485 	/* Number of Extended VLAN Tag Filters */
486 	unsigned int nrvf_num;
487 	/* TSN Features */
488 	unsigned int estwid;
489 	unsigned int estdep;
490 	unsigned int estsel;
491 	unsigned int fpesel;
492 	unsigned int tbssel;
493 	/* Number of DMA channels enabled for TBS */
494 	unsigned int tbs_ch_num;
495 	/* Per-Stream Filtering Enable */
496 	unsigned int sgfsel;
497 	/* Numbers of Auxiliary Snapshot Inputs */
498 	unsigned int aux_snapshot_n;
499 	/* Timestamp System Time Source */
500 	unsigned int tssrc;
501 	/* Enhanced DMA Enable */
502 	unsigned int edma;
503 	/* Different Descriptor Cache Enable */
504 	unsigned int ediffc;
505 	/* VxLAN/NVGRE Enable */
506 	unsigned int vxn;
507 	/* Debug Memory Interface Enable */
508 	unsigned int dbgmem;
509 	/* Number of Policing Counters */
510 	unsigned int pcsel;
511 };
512 
513 /* RX Buffer size must be multiple of 4/8/16 bytes */
514 #define BUF_SIZE_16KiB 16368
515 #define BUF_SIZE_8KiB 8188
516 #define BUF_SIZE_4KiB 4096
517 #define BUF_SIZE_2KiB 2048
518 
519 /* Power Down and WOL */
520 #define PMT_NOT_SUPPORTED 0
521 #define PMT_SUPPORTED 1
522 
523 /* Common MAC defines */
524 #define MAC_CTRL_REG		0x00000000	/* MAC Control */
525 #define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
526 #define MAC_ENABLE_RX		0x00000004	/* Receiver Enable */
527 
528 /* Default LPI timers */
529 #define STMMAC_DEFAULT_LIT_LS	0x3E8
530 #define STMMAC_DEFAULT_TWT_LS	0x1E
531 #define STMMAC_ET_MAX		0xFFFFF
532 
533 /* Common LPI register bits */
534 #define LPI_CTRL_STATUS_LPITCSE	BIT(21)	/* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */
535 #define LPI_CTRL_STATUS_LPIATE	BIT(20)	/* LPI Timer Enable, gmac4 only */
536 #define LPI_CTRL_STATUS_LPITXA	BIT(19)	/* Enable LPI TX Automate */
537 #define LPI_CTRL_STATUS_PLSEN	BIT(18)	/* Enable PHY Link Status */
538 #define LPI_CTRL_STATUS_PLS	BIT(17)	/* PHY Link Status */
539 #define LPI_CTRL_STATUS_LPIEN	BIT(16)	/* LPI Enable */
540 #define LPI_CTRL_STATUS_RLPIST	BIT(9)	/* Receive LPI state, gmac1000 only? */
541 #define LPI_CTRL_STATUS_TLPIST	BIT(8)	/* Transmit LPI state, gmac1000 only? */
542 #define LPI_CTRL_STATUS_RLPIEX	BIT(3)	/* Receive LPI Exit */
543 #define LPI_CTRL_STATUS_RLPIEN	BIT(2)	/* Receive LPI Entry */
544 #define LPI_CTRL_STATUS_TLPIEX	BIT(1)	/* Transmit LPI Exit */
545 #define LPI_CTRL_STATUS_TLPIEN	BIT(0)	/* Transmit LPI Entry */
546 
547 #define STMMAC_CHAIN_MODE	0x1
548 #define STMMAC_RING_MODE	0x2
549 
550 #define JUMBO_LEN		9000
551 
552 /* Receive Side Scaling */
553 #define STMMAC_RSS_HASH_KEY_SIZE	40
554 #define STMMAC_RSS_MAX_TABLE_SIZE	256
555 
556 /* VLAN */
557 #define STMMAC_VLAN_NONE	0x0
558 #define STMMAC_VLAN_REMOVE	0x1
559 #define STMMAC_VLAN_INSERT	0x2
560 #define STMMAC_VLAN_REPLACE	0x3
561 
562 struct mac_device_info;
563 
564 struct mac_link {
565 	u32 caps;
566 	u32 speed_mask;
567 	u32 speed10;
568 	u32 speed100;
569 	u32 speed1000;
570 	u32 speed2500;
571 	u32 duplex;
572 	struct {
573 		u32 speed2500;
574 		u32 speed5000;
575 		u32 speed10000;
576 	} xgmii;
577 	struct {
578 		u32 speed25000;
579 		u32 speed40000;
580 		u32 speed50000;
581 		u32 speed100000;
582 	} xlgmii;
583 };
584 
585 struct mii_regs {
586 	unsigned int addr;	/* MII Address */
587 	unsigned int data;	/* MII Data */
588 	unsigned int addr_shift;	/* MII address shift */
589 	unsigned int reg_shift;		/* MII reg shift */
590 	unsigned int addr_mask;		/* MII address mask */
591 	unsigned int reg_mask;		/* MII reg mask */
592 	unsigned int clk_csr_shift;
593 	unsigned int clk_csr_mask;
594 };
595 
596 struct mac_device_info {
597 	const struct stmmac_ops *mac;
598 	const struct stmmac_desc_ops *desc;
599 	const struct stmmac_dma_ops *dma;
600 	const struct stmmac_mode_ops *mode;
601 	const struct stmmac_hwtimestamp *ptp;
602 	const struct stmmac_tc_ops *tc;
603 	const struct stmmac_mmc_ops *mmc;
604 	const struct stmmac_est_ops *est;
605 	struct dw_xpcs *xpcs;
606 	struct phylink_pcs *phylink_pcs;
607 	struct mii_regs mii;	/* MII register Addresses */
608 	struct mac_link link;
609 	void __iomem *pcsr;     /* vpointer to device CSRs */
610 	unsigned int multicast_filter_bins;
611 	unsigned int unicast_filter_entries;
612 	unsigned int mcast_bits_log2;
613 	unsigned int rx_csum;
614 	unsigned int pcs;
615 	unsigned int pmt;
616 	unsigned int ps;
617 	unsigned int xlgmac;
618 	unsigned int num_vlan;
619 	u32 vlan_filter[32];
620 	bool vlan_fail_q_en;
621 	u8 vlan_fail_q;
622 	bool hw_vlan_en;
623 };
624 
625 struct stmmac_rx_routing {
626 	u32 reg_mask;
627 	u32 reg_shift;
628 };
629 
630 int dwmac100_setup(struct stmmac_priv *priv);
631 int dwmac1000_setup(struct stmmac_priv *priv);
632 int dwmac4_setup(struct stmmac_priv *priv);
633 int dwxgmac2_setup(struct stmmac_priv *priv);
634 int dwxlgmac2_setup(struct stmmac_priv *priv);
635 
636 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
637 			 unsigned int high, unsigned int low);
638 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
639 			 unsigned int high, unsigned int low);
640 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
641 
642 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
643 				unsigned int high, unsigned int low);
644 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
645 				unsigned int high, unsigned int low);
646 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
647 
648 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
649 
650 #endif /* __COMMON_H__ */
651