1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_DP_H
8 #define ATH12K_DP_H
9
10 #include "hal_desc.h"
11 #include "hal_rx.h"
12 #include "hw.h"
13
14 #define MAX_RXDMA_PER_PDEV 2
15
16 struct ath12k_base;
17 struct ath12k_peer;
18 struct ath12k_dp;
19 struct ath12k_vif;
20 struct ath12k_link_vif;
21 struct hal_tcl_status_ring;
22 struct ath12k_ext_irq_grp;
23
24 #define DP_MON_PURGE_TIMEOUT_MS 100
25 #define DP_MON_SERVICE_BUDGET 128
26
27 struct dp_srng {
28 u32 *vaddr_unaligned;
29 u32 *vaddr;
30 dma_addr_t paddr_unaligned;
31 dma_addr_t paddr;
32 int size;
33 u32 ring_id;
34 };
35
36 struct dp_rxdma_mon_ring {
37 struct dp_srng refill_buf_ring;
38 struct idr bufs_idr;
39 /* Protects bufs_idr */
40 spinlock_t idr_lock;
41 int bufs_max;
42 };
43
44 struct dp_rxdma_ring {
45 struct dp_srng refill_buf_ring;
46 int bufs_max;
47 };
48
49 #define ATH12K_TX_COMPL_NEXT(ab, x) (((x) + 1) % DP_TX_COMP_RING_SIZE(ab))
50
51 struct dp_tx_ring {
52 u8 tcl_data_ring_id;
53 struct dp_srng tcl_data_ring;
54 struct dp_srng tcl_comp_ring;
55 struct hal_wbm_completion_ring_tx *tx_status;
56 int tx_status_head;
57 int tx_status_tail;
58 };
59
60 struct ath12k_pdev_mon_stats {
61 u32 status_ppdu_state;
62 u32 status_ppdu_start;
63 u32 status_ppdu_end;
64 u32 status_ppdu_compl;
65 u32 status_ppdu_start_mis;
66 u32 status_ppdu_end_mis;
67 u32 status_ppdu_done;
68 u32 dest_ppdu_done;
69 u32 dest_mpdu_done;
70 u32 dest_mpdu_drop;
71 u32 dup_mon_linkdesc_cnt;
72 u32 dup_mon_buf_cnt;
73 u32 dest_mon_stuck;
74 u32 dest_mon_not_reaped;
75 };
76
77 enum dp_mon_status_buf_state {
78 DP_MON_STATUS_MATCH,
79 DP_MON_STATUS_NO_DMA,
80 DP_MON_STATUS_LAG,
81 DP_MON_STATUS_LEAD,
82 DP_MON_STATUS_REPLINISH,
83 };
84
85 struct dp_link_desc_bank {
86 void *vaddr_unaligned;
87 void *vaddr;
88 dma_addr_t paddr_unaligned;
89 dma_addr_t paddr;
90 u32 size;
91 };
92
93 /* Size to enforce scatter idle list mode */
94 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
95 #define DP_LINK_DESC_BANKS_MAX 8
96
97 #define DP_LINK_DESC_START 0x4000
98 #define DP_LINK_DESC_SHIFT 3
99
100 #define DP_LINK_DESC_COOKIE_SET(id, page) \
101 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))
102
103 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
104
105 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
106 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
107 #define DP_RX_DESC_COOKIE_MAX \
108 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
109 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
110
111 enum ath12k_dp_ppdu_state {
112 DP_PPDU_STATUS_START,
113 DP_PPDU_STATUS_DONE,
114 };
115
116 struct dp_mon_mpdu {
117 struct list_head list;
118 struct sk_buff *head;
119 struct sk_buff *tail;
120 u32 err_bitmap;
121 u8 decap_format;
122 };
123
124 #define DP_MON_MAX_STATUS_BUF 32
125
126 struct ath12k_mon_data {
127 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
128 struct hal_rx_mon_ppdu_info mon_ppdu_info;
129
130 u32 mon_ppdu_status;
131 u32 mon_last_buf_cookie;
132 u64 mon_last_linkdesc_paddr;
133 u16 chan_noise_floor;
134 u32 err_bitmap;
135 u8 decap_format;
136
137 struct ath12k_pdev_mon_stats rx_mon_stats;
138 enum dp_mon_status_buf_state buf_state;
139 /* lock for monitor data */
140 spinlock_t mon_lock;
141 struct sk_buff_head rx_status_q;
142 struct dp_mon_mpdu *mon_mpdu;
143 struct list_head dp_rx_mon_mpdu_list;
144 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info;
145 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info;
146 };
147
148 struct ath12k_pdev_dp {
149 u32 mac_id;
150 atomic_t num_tx_pending;
151 wait_queue_head_t tx_empty_waitq;
152 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];
153 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];
154
155 struct ieee80211_rx_status rx_status;
156 struct ath12k_mon_data mon_data;
157 };
158
159 #define DP_NUM_CLIENTS_MAX 64
160 #define DP_AVG_TIDS_PER_CLIENT 2
161 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
162 #define DP_AVG_MSDUS_PER_FLOW 128
163 #define DP_AVG_FLOWS_PER_TID 2
164 #define DP_AVG_MPDUS_PER_TID_MAX 128
165 #define DP_AVG_MSDUS_PER_MPDU 4
166
167 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
168
169 #define DP_BA_WIN_SZ_MAX 1024
170
171 #define DP_TCL_NUM_RING_MAX 4
172
173 #define DP_IDLE_SCATTER_BUFS_MAX 16
174
175 #define DP_WBM_RELEASE_RING_SIZE 64
176 #define DP_TCL_DATA_RING_SIZE 512
177 #define DP_TX_COMP_RING_SIZE(ab) \
178 ((ab)->profile_param->dp_params.tx_comp_ring_size)
179 #define DP_TX_IDR_SIZE(ab) DP_TX_COMP_RING_SIZE(ab)
180 #define DP_TCL_CMD_RING_SIZE 32
181 #define DP_TCL_STATUS_RING_SIZE 32
182 #define DP_REO_DST_RING_MAX 8
183 #define DP_REO_DST_RING_SIZE 2048
184 #define DP_REO_REINJECT_RING_SIZE 32
185 #define DP_RX_RELEASE_RING_SIZE 1024
186 #define DP_REO_EXCEPTION_RING_SIZE 128
187 #define DP_REO_CMD_RING_SIZE 128
188 #define DP_REO_STATUS_RING_SIZE 2048
189 #define DP_RXDMA_BUF_RING_SIZE 4096
190 #define DP_RX_MAC_BUF_RING_SIZE 2048
191 #define DP_RXDMA_REFILL_RING_SIZE 2048
192 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
193 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
194 #define DP_RXDMA_MONITOR_BUF_RING_SIZE(ab) \
195 ((ab)->profile_param->dp_params.rxdma_monitor_buf_ring_size)
196 #define DP_RXDMA_MONITOR_DST_RING_SIZE(ab) \
197 ((ab)->profile_param->dp_params.rxdma_monitor_dst_ring_size)
198 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
199 #define DP_TX_MONITOR_BUF_RING_SIZE 4096
200 #define DP_TX_MONITOR_DEST_RING_SIZE 2048
201
202 #define DP_TX_MONITOR_BUF_SIZE 2048
203 #define DP_TX_MONITOR_BUF_SIZE_MIN 48
204 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192
205
206 #define DP_RX_BUFFER_SIZE 2048
207 #define DP_RX_BUFFER_SIZE_LITE 1024
208 #define DP_RX_BUFFER_ALIGN_SIZE 128
209
210 #define RX_MON_STATUS_BASE_BUF_SIZE 2048
211 #define RX_MON_STATUS_BUF_ALIGN 128
212 #define RX_MON_STATUS_BUF_RESERVATION 128
213 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \
214 (RX_MON_STATUS_BUF_RESERVATION + \
215 RX_MON_STATUS_BUF_ALIGN + \
216 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
217
218 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
219 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)
220
221 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
222 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
223
224 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
225 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
226 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
227
228 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20
229 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10
230
231 #define ATH12K_NUM_POOL_TX_DESC(ab) \
232 ((ab)->profile_param->dp_params.num_pool_tx_desc)
233 /* TODO: revisit this count during testing */
234 #define ATH12K_RX_DESC_COUNT(ab) \
235 ((ab)->profile_param->dp_params.rx_desc_count)
236
237 #define ATH12K_PAGE_SIZE PAGE_SIZE
238
239 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned
240 * SPT pages which makes lower 12bits 0
241 */
242 #define ATH12K_MAX_PPT_ENTRIES 1024
243
244 /* Total 512 entries in a SPT, i.e 4K Page/8 */
245 #define ATH12K_MAX_SPT_ENTRIES 512
246
247 #define ATH12K_NUM_RX_SPT_PAGES(ab) ((ATH12K_RX_DESC_COUNT(ab)) / \
248 ATH12K_MAX_SPT_ENTRIES)
249
250 #define ATH12K_TX_SPT_PAGES_PER_POOL(ab) (ATH12K_NUM_POOL_TX_DESC(ab) / \
251 ATH12K_MAX_SPT_ENTRIES)
252 #define ATH12K_NUM_TX_SPT_PAGES(ab) (ATH12K_TX_SPT_PAGES_PER_POOL(ab) * \
253 ATH12K_HW_MAX_QUEUES)
254
255 #define ATH12K_TX_SPT_PAGE_OFFSET 0
256 #define ATH12K_RX_SPT_PAGE_OFFSET(ab) ATH12K_NUM_TX_SPT_PAGES(ab)
257
258 /* The SPT pages are divided for RX and TX, first block for RX
259 * and remaining for TX
260 */
261 #define ATH12K_NUM_TX_SPT_PAGE_START(ab) ATH12K_NUM_RX_SPT_PAGES(ab)
262
263 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA
264
265 /* 4K aligned address have last 12 bits set to 0, this check is done
266 * so that two spt pages address can be stored per 8bytes
267 * of CMEM (PPT)
268 */
269 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF
270 #define ATH12K_SPT_4K_ALIGN_OFFSET 12
271 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))
272
273 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
274 #define ATH12K_CMEM_ADDR_MSB 0x10
275
276 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
277 #define ATH12K_CC_SPT_MSB 8
278 #define ATH12K_CC_PPT_MSB 19
279 #define ATH12K_CC_PPT_SHIFT 9
280 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
281 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
282
283 #define DP_REO_QREF_NUM GENMASK(31, 16)
284 #define DP_MAX_PEER_ID 2047
285
286 /* Total size of the LUT is based on 2K peers, each having reference
287 * for 17tids, note each entry is of type ath12k_reo_queue_ref
288 * hence total size is 2048 * 17 * 8 = 278528
289 */
290 #define DP_REOQ_LUT_SIZE 278528
291
292 /* Invalid TX Bank ID value */
293 #define DP_INVALID_BANK_ID -1
294
295 #define MAX_TQM_RELEASE_REASON 15
296 #define MAX_FW_TX_STATUS 7
297
298 struct ath12k_dp_tx_bank_profile {
299 u8 is_configured;
300 u32 num_users;
301 u32 bank_config;
302 };
303
304 struct ath12k_hp_update_timer {
305 struct timer_list timer;
306 bool started;
307 bool init;
308 u32 tx_num;
309 u32 timer_tx_num;
310 u32 ring_id;
311 u32 interval;
312 struct ath12k_base *ab;
313 };
314
315 struct ath12k_rx_desc_info {
316 struct list_head list;
317 struct sk_buff *skb;
318 u32 cookie;
319 u32 magic;
320 u8 in_use : 1,
321 device_id : 3,
322 reserved : 4;
323 };
324
325 struct ath12k_tx_desc_info {
326 struct list_head list;
327 struct sk_buff *skb;
328 struct sk_buff *skb_ext_desc;
329 u32 desc_id; /* Cookie */
330 u8 mac_id;
331 u8 pool_id;
332 };
333
334 struct ath12k_tx_desc_params {
335 struct sk_buff *skb;
336 struct sk_buff *skb_ext_desc;
337 u8 mac_id;
338 };
339
340 struct ath12k_spt_info {
341 dma_addr_t paddr;
342 u64 *vaddr;
343 };
344
345 struct ath12k_reo_queue_ref {
346 u32 info0;
347 u32 info1;
348 } __packed;
349
350 struct ath12k_reo_q_addr_lut {
351 u32 *vaddr_unaligned;
352 u32 *vaddr;
353 dma_addr_t paddr_unaligned;
354 dma_addr_t paddr;
355 u32 size;
356 };
357
358 struct ath12k_link_stats {
359 u32 tx_enqueued;
360 u32 tx_completed;
361 u32 tx_bcast_mcast;
362 u32 tx_dropped;
363 u32 tx_encap_type[HAL_TCL_ENCAP_TYPE_MAX];
364 u32 tx_encrypt_type[HAL_ENCRYPT_TYPE_MAX];
365 u32 tx_desc_type[HAL_TCL_DESC_TYPE_MAX];
366 };
367
368 struct ath12k_dp {
369 struct ath12k_base *ab;
370 u32 mon_dest_ring_stuck_cnt;
371 u8 num_bank_profiles;
372 /* protects the access and update of bank_profiles */
373 spinlock_t tx_bank_lock;
374 struct ath12k_dp_tx_bank_profile *bank_profiles;
375 enum ath12k_htc_ep_id eid;
376 struct completion htt_tgt_version_received;
377 u8 htt_tgt_ver_major;
378 u8 htt_tgt_ver_minor;
379 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
380 enum hal_rx_buf_return_buf_manager idle_link_rbm;
381 struct dp_srng wbm_idle_ring;
382 struct dp_srng wbm_desc_rel_ring;
383 struct dp_srng reo_reinject_ring;
384 struct dp_srng rx_rel_ring;
385 struct dp_srng reo_except_ring;
386 struct dp_srng reo_cmd_ring;
387 struct dp_srng reo_status_ring;
388 enum ath12k_peer_metadata_version peer_metadata_ver;
389 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
390 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
391 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
392 struct list_head reo_cmd_list;
393 struct list_head reo_cmd_cache_flush_list;
394 u32 reo_cmd_cache_flush_count;
395
396 /* protects access to below fields,
397 * - reo_cmd_list
398 * - reo_cmd_cache_flush_list
399 * - reo_cmd_cache_flush_count
400 */
401 spinlock_t reo_cmd_lock;
402 struct ath12k_hp_update_timer reo_cmd_timer;
403 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
404 struct ath12k_spt_info *spt_info;
405 u32 num_spt_pages;
406 u32 rx_ppt_base;
407 struct ath12k_rx_desc_info **rxbaddr;
408 struct ath12k_tx_desc_info **txbaddr;
409 struct list_head rx_desc_free_list;
410 /* protects the free desc list */
411 spinlock_t rx_desc_lock;
412
413 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES];
414 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES];
415 /* protects the free and used desc lists */
416 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];
417
418 struct dp_rxdma_ring rx_refill_buf_ring;
419 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
420 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
421 struct dp_rxdma_mon_ring rxdma_mon_buf_ring;
422 struct dp_rxdma_mon_ring tx_mon_buf_ring;
423 struct dp_rxdma_mon_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
424 struct ath12k_reo_q_addr_lut reoq_lut;
425 struct ath12k_reo_q_addr_lut ml_reoq_lut;
426 };
427
428 /* HTT definitions */
429 #define HTT_TAG_TCL_METADATA_VERSION 5
430
431 #define HTT_TCL_META_DATA_TYPE GENMASK(1, 0)
432 #define HTT_TCL_META_DATA_VALID_HTT BIT(2)
433
434 /* vdev meta data */
435 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3)
436 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11)
437 #define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13)
438
439 /* peer meta data */
440 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3)
441
442 /* Global sequence number */
443 #define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3
444 #define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2)
445 #define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3)
446 #define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128
447
448 /* HTT tx completion is overlaid in wbm_release_ring */
449 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13)
450 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)
451 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4)
452
453 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24)
454
455 struct htt_tx_wbm_completion {
456 __le32 rsvd0[2];
457 __le32 info0;
458 __le32 info1;
459 __le32 info2;
460 __le32 info3;
461 __le32 info4;
462 __le32 rsvd1;
463
464 } __packed;
465
466 enum htt_h2t_msg_type {
467 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
468 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
469 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
470 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
471 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
472 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a,
473 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,
474 };
475
476 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
477 #define HTT_OPTION_TCL_METADATA_VER_V1 1
478 #define HTT_OPTION_TCL_METADATA_VER_V2 2
479 #define HTT_OPTION_TAG GENMASK(7, 0)
480 #define HTT_OPTION_LEN GENMASK(15, 8)
481 #define HTT_OPTION_VALUE GENMASK(31, 16)
482 #define HTT_TCL_METADATA_VER_SZ 4
483
484 struct htt_ver_req_cmd {
485 __le32 ver_reg_info;
486 __le32 tcl_metadata_version;
487 } __packed;
488
489 enum htt_srng_ring_type {
490 HTT_HW_TO_SW_RING,
491 HTT_SW_TO_HW_RING,
492 HTT_SW_TO_SW_RING,
493 };
494
495 enum htt_srng_ring_id {
496 HTT_RXDMA_HOST_BUF_RING,
497 HTT_RXDMA_MONITOR_STATUS_RING,
498 HTT_RXDMA_MONITOR_BUF_RING,
499 HTT_RXDMA_MONITOR_DESC_RING,
500 HTT_RXDMA_MONITOR_DEST_RING,
501 HTT_HOST1_TO_FW_RXBUF_RING,
502 HTT_HOST2_TO_FW_RXBUF_RING,
503 HTT_RXDMA_NON_MONITOR_DEST_RING,
504 HTT_RXDMA_HOST_BUF_RING2,
505 HTT_TX_MON_HOST2MON_BUF_RING,
506 HTT_TX_MON_MON2HOST_DEST_RING,
507 HTT_RX_MON_HOST2MON_BUF_RING,
508 HTT_RX_MON_MON2HOST_DEST_RING,
509 };
510
511 /* host -> target HTT_SRING_SETUP message
512 *
513 * After target is booted up, Host can send SRING setup message for
514 * each host facing LMAC SRING. Target setups up HW registers based
515 * on setup message and confirms back to Host if response_required is set.
516 * Host should wait for confirmation message before sending new SRING
517 * setup message
518 *
519 * The message would appear as follows:
520 *
521 * |31 24|23 20|19|18 16|15|14 8|7 0|
522 * |--------------- +-----------------+----------------+------------------|
523 * | ring_type | ring_id | pdev_id | msg_type |
524 * |----------------------------------------------------------------------|
525 * | ring_base_addr_lo |
526 * |----------------------------------------------------------------------|
527 * | ring_base_addr_hi |
528 * |----------------------------------------------------------------------|
529 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
530 * |----------------------------------------------------------------------|
531 * | ring_head_offset32_remote_addr_lo |
532 * |----------------------------------------------------------------------|
533 * | ring_head_offset32_remote_addr_hi |
534 * |----------------------------------------------------------------------|
535 * | ring_tail_offset32_remote_addr_lo |
536 * |----------------------------------------------------------------------|
537 * | ring_tail_offset32_remote_addr_hi |
538 * |----------------------------------------------------------------------|
539 * | ring_msi_addr_lo |
540 * |----------------------------------------------------------------------|
541 * | ring_msi_addr_hi |
542 * |----------------------------------------------------------------------|
543 * | ring_msi_data |
544 * |----------------------------------------------------------------------|
545 * | intr_timer_th |IM| intr_batch_counter_th |
546 * |----------------------------------------------------------------------|
547 * | reserved |RR|PTCF| intr_low_threshold |
548 * |----------------------------------------------------------------------|
549 * Where
550 * IM = sw_intr_mode
551 * RR = response_required
552 * PTCF = prefetch_timer_cfg
553 *
554 * The message is interpreted as follows:
555 * dword0 - b'0:7 - msg_type: This will be set to
556 * HTT_H2T_MSG_TYPE_SRING_SETUP
557 * b'8:15 - pdev_id:
558 * 0 (for rings at SOC/UMAC level),
559 * 1/2/3 mac id (for rings at LMAC level)
560 * b'16:23 - ring_id: identify which ring is to setup,
561 * more details can be got from enum htt_srng_ring_id
562 * b'24:31 - ring_type: identify type of host rings,
563 * more details can be got from enum htt_srng_ring_type
564 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
565 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
566 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
567 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
568 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
569 * SW_TO_HW_RING.
570 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
571 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
572 * Lower 32 bits of memory address of the remote variable
573 * storing the 4-byte word offset that identifies the head
574 * element within the ring.
575 * (The head offset variable has type u32.)
576 * Valid for HW_TO_SW and SW_TO_SW rings.
577 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
578 * Upper 32 bits of memory address of the remote variable
579 * storing the 4-byte word offset that identifies the head
580 * element within the ring.
581 * (The head offset variable has type u32.)
582 * Valid for HW_TO_SW and SW_TO_SW rings.
583 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
584 * Lower 32 bits of memory address of the remote variable
585 * storing the 4-byte word offset that identifies the tail
586 * element within the ring.
587 * (The tail offset variable has type u32.)
588 * Valid for HW_TO_SW and SW_TO_SW rings.
589 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
590 * Upper 32 bits of memory address of the remote variable
591 * storing the 4-byte word offset that identifies the tail
592 * element within the ring.
593 * (The tail offset variable has type u32.)
594 * Valid for HW_TO_SW and SW_TO_SW rings.
595 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
596 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
597 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
598 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
599 * dword10 - b'0:31 - ring_msi_data: MSI data
600 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
601 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
602 * dword11 - b'0:14 - intr_batch_counter_th:
603 * batch counter threshold is in units of 4-byte words.
604 * HW internally maintains and increments batch count.
605 * (see SRING spec for detail description).
606 * When batch count reaches threshold value, an interrupt
607 * is generated by HW.
608 * b'15 - sw_intr_mode:
609 * This configuration shall be static.
610 * Only programmed at power up.
611 * 0: generate pulse style sw interrupts
612 * 1: generate level style sw interrupts
613 * b'16:31 - intr_timer_th:
614 * The timer init value when timer is idle or is
615 * initialized to start downcounting.
616 * In 8us units (to cover a range of 0 to 524 ms)
617 * dword12 - b'0:15 - intr_low_threshold:
618 * Used only by Consumer ring to generate ring_sw_int_p.
619 * Ring entries low threshold water mark, that is used
620 * in combination with the interrupt timer as well as
621 * the clearing of the level interrupt.
622 * b'16:18 - prefetch_timer_cfg:
623 * Used only by Consumer ring to set timer mode to
624 * support Application prefetch handling.
625 * The external tail offset/pointer will be updated
626 * at following intervals:
627 * 3'b000: (Prefetch feature disabled; used only for debug)
628 * 3'b001: 1 usec
629 * 3'b010: 4 usec
630 * 3'b011: 8 usec (default)
631 * 3'b100: 16 usec
632 * Others: Reserved
633 * b'19 - response_required:
634 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
635 * b'20:31 - reserved: reserved for future use
636 */
637
638 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
639 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
640 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
641 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
642
643 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
644 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
645 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
646 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
647 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
648 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
649
650 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
651 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
652 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
653
654 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
655 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16)
656 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
657
658 struct htt_srng_setup_cmd {
659 __le32 info0;
660 __le32 ring_base_addr_lo;
661 __le32 ring_base_addr_hi;
662 __le32 info1;
663 __le32 ring_head_off32_remote_addr_lo;
664 __le32 ring_head_off32_remote_addr_hi;
665 __le32 ring_tail_off32_remote_addr_lo;
666 __le32 ring_tail_off32_remote_addr_hi;
667 __le32 ring_msi_addr_lo;
668 __le32 ring_msi_addr_hi;
669 __le32 msi_data;
670 __le32 intr_info;
671 __le32 info2;
672 } __packed;
673
674 /* host -> target FW PPDU_STATS config message
675 *
676 * @details
677 * The following field definitions describe the format of the HTT host
678 * to target FW for PPDU_STATS_CFG msg.
679 * The message allows the host to configure the PPDU_STATS_IND messages
680 * produced by the target.
681 *
682 * |31 24|23 16|15 8|7 0|
683 * |-----------------------------------------------------------|
684 * | REQ bit mask | pdev_mask | msg type |
685 * |-----------------------------------------------------------|
686 * Header fields:
687 * - MSG_TYPE
688 * Bits 7:0
689 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
690 * Value: 0x11
691 * - PDEV_MASK
692 * Bits 8:15
693 * Purpose: identifies which pdevs this PPDU stats configuration applies to
694 * Value: This is a overloaded field, refer to usage and interpretation of
695 * PDEV in interface document.
696 * Bit 8 : Reserved for SOC stats
697 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
698 * Indicates MACID_MASK in DBS
699 * - REQ_TLV_BIT_MASK
700 * Bits 16:31
701 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
702 * needs to be included in the target's PPDU_STATS_IND messages.
703 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
704 *
705 */
706
707 struct htt_ppdu_stats_cfg_cmd {
708 __le32 msg;
709 } __packed;
710
711 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
712 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8)
713 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9)
714 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
715
716 enum htt_ppdu_stats_tag_type {
717 HTT_PPDU_STATS_TAG_COMMON,
718 HTT_PPDU_STATS_TAG_USR_COMMON,
719 HTT_PPDU_STATS_TAG_USR_RATE,
720 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
721 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
722 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
723 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
724 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
725 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
726 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
727 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
728 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
729 HTT_PPDU_STATS_TAG_INFO,
730 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
731
732 /* New TLV's are added above to this line */
733 HTT_PPDU_STATS_TAG_MAX,
734 };
735
736 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
737 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
738 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
739 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
740 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
741 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
742 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
743 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
744
745 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
746 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
747 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
748 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
749 BIT(HTT_PPDU_STATS_TAG_INFO) | \
750 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
751 HTT_PPDU_STATS_TAG_DEFAULT)
752
753 enum htt_stats_internal_ppdu_frametype {
754 HTT_STATS_PPDU_FTYPE_CTRL,
755 HTT_STATS_PPDU_FTYPE_DATA,
756 HTT_STATS_PPDU_FTYPE_BAR,
757 HTT_STATS_PPDU_FTYPE_MAX
758 };
759
760 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
761 *
762 * details:
763 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
764 * configure RXDMA rings.
765 * The configuration is per ring based and includes both packet subtypes
766 * and PPDU/MPDU TLVs.
767 *
768 * The message would appear as follows:
769 *
770 * |31 29|28|27|26|25|24|23 16|15 8|7 0|
771 * |-------+--+--+--+--+--+-----------+----------------+---------------|
772 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
773 * |-------------------------------------------------------------------|
774 * | rsvd2 | ring_buffer_size |
775 * |-------------------------------------------------------------------|
776 * | packet_type_enable_flags_0 |
777 * |-------------------------------------------------------------------|
778 * | packet_type_enable_flags_1 |
779 * |-------------------------------------------------------------------|
780 * | packet_type_enable_flags_2 |
781 * |-------------------------------------------------------------------|
782 * | packet_type_enable_flags_3 |
783 * |-------------------------------------------------------------------|
784 * | tlv_filter_in_flags |
785 * |-------------------------------------------------------------------|
786 * Where:
787 * PS = pkt_swap
788 * SS = status_swap
789 * The message is interpreted as follows:
790 * dword0 - b'0:7 - msg_type: This will be set to
791 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
792 * b'8:15 - pdev_id:
793 * 0 (for rings at SOC/UMAC level),
794 * 1/2/3 mac id (for rings at LMAC level)
795 * b'16:23 - ring_id : Identify the ring to configure.
796 * More details can be got from enum htt_srng_ring_id
797 * b'24 - status_swap: 1 is to swap status TLV
798 * b'25 - pkt_swap: 1 is to swap packet TLV
799 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets
800 * configuration fields are valid
801 * b'27 - drop_thresh_valid (DT): flag to indicate if the
802 * rx_drop_threshold field is valid
803 * b'28 - rx_mon_global_en: Enable/Disable global register
804 * configuration in Rx monitor module.
805 * b'29:31 - rsvd1: reserved for future use
806 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,
807 * in byte units.
808 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
809 * - b'16:31 - rsvd2: Reserved for future use
810 * dword2 - b'0:31 - packet_type_enable_flags_0:
811 * Enable MGMT packet from 0b0000 to 0b1001
812 * bits from low to high: FP, MD, MO - 3 bits
813 * FP: Filter_Pass
814 * MD: Monitor_Direct
815 * MO: Monitor_Other
816 * 10 mgmt subtypes * 3 bits -> 30 bits
817 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
818 * dword3 - b'0:31 - packet_type_enable_flags_1:
819 * Enable MGMT packet from 0b1010 to 0b1111
820 * bits from low to high: FP, MD, MO - 3 bits
821 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
822 * dword4 - b'0:31 - packet_type_enable_flags_2:
823 * Enable CTRL packet from 0b0000 to 0b1001
824 * bits from low to high: FP, MD, MO - 3 bits
825 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
826 * dword5 - b'0:31 - packet_type_enable_flags_3:
827 * Enable CTRL packet from 0b1010 to 0b1111,
828 * MCAST_DATA, UCAST_DATA, NULL_DATA
829 * bits from low to high: FP, MD, MO - 3 bits
830 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
831 * dword6 - b'0:31 - tlv_filter_in_flags:
832 * Filter in Attention/MPDU/PPDU/Header/User tlvs
833 * Refer to CFG_TLV_FILTER_IN_FLAG defs
834 */
835
836 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
837 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
838 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
839 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
840 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
841 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID BIT(26)
842 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL BIT(27)
843 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON BIT(28)
844
845 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
846 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16)
847 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19)
848 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22)
849
850 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0)
851 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE BIT(17)
852 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE BIT(18)
853 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE BIT(19)
854
855 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET BIT(0)
856 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1)
857
858 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0)
859 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16)
860 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0)
861 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16)
862 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0)
863 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16)
864 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0)
865
866 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23)
867 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0)
868 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16)
869 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0)
870
871 enum htt_rx_filter_tlv_flags {
872 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
873 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
874 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
875 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
876 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
877 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
878 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
879 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
880 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
881 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
882 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
883 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
884 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
885 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13),
886 };
887
888 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
889 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
890 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
891 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
892 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
893 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
894 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
895 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
896 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
897 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
898 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
899 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
900 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
901 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
902 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
903 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
904 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
905 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
906 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
907 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
908 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
909 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
910 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
911 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
912 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
913 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
914 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
915 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
916 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
917 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
918 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
919 };
920
921 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
922 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
923 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
924 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
925 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
926 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
927 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
928 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
929 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
930 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
931 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
932 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
933 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
934 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
935 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
936 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
937 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
938 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
939 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
940 };
941
942 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
943 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
944 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
945 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
946 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
947 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
948 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
949 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
950 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
951 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
952 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
953 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
954 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
955 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
956 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
957 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
958 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
959 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
960 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
961 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
962 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
963 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
964 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
965 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
966 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
967 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
968 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
969 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
970 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
971 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
972 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
973 };
974
975 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
976 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
977 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
978 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
979 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
980 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
981 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
982 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
983 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
984 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
985 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
986 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
987 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
988 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
989 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
990 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
991 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
992 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
993 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
994 };
995
996 enum htt_rx_data_pkt_filter_tlv_flasg3 {
997 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
998 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
999 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
1000 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
1001 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
1002 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
1003 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
1004 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
1005 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
1006 };
1007
1008 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
1009 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
1010 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
1011 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
1012 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
1013 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
1014 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
1015 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
1016 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
1017 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
1018
1019 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
1020 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
1021 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
1022 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
1023 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
1024 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
1025 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
1026 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
1027 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
1028 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
1029
1030 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
1031 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
1032 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
1033 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
1034 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
1035 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
1036 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
1037 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
1038 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
1039 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
1040
1041 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
1042 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
1043 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
1044 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
1045 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
1046
1047 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
1048 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
1049 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
1050 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
1051 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
1052
1053 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
1054 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
1055 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
1056 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
1057 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
1058
1059 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
1060 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
1061 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
1062
1063 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
1064 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
1065 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
1066
1067 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
1068 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
1069 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
1070
1071 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
1072 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
1073 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
1074 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
1075 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
1076 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
1077
1078 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
1079 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
1080 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
1081 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
1082 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
1083 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
1084
1085 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
1086 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
1087 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
1088 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
1089 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
1090 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
1091
1092 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1093 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1094 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1095
1096 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1097 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1098 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1099
1100 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1101 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1102 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1103
1104 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
1105 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
1106 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1107
1108 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
1109 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
1110 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1111
1112 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
1113 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
1114 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1115
1116 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
1117 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
1118 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1119
1120 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
1121 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
1122 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1123 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1124 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1125 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1126 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1127 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1128 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1129
1130 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
1131 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
1132 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1133 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1134 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1135 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1136 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1137 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1138 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1139
1140 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
1141
1142 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
1143
1144 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
1145
1146 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
1147
1148 #define HTT_RX_MON_FILTER_TLV_FLAGS \
1149 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1150 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1151 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1152 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1153 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1154 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1155
1156 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
1157 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1158 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1159 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1160 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1161 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1162 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1163
1164 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
1165 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1166 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
1167 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1168 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
1169 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
1170 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
1171 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
1172 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
1173
1174 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \
1175 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1176 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
1177 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1178 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
1179 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
1180 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
1181 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
1182 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1183 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1184 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1185 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1186 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \
1187 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO)
1188
1189 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */
1190 #define HTT_RX_TLV_FLAGS_RXDMA_RING \
1191 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1192 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1193 HTT_RX_FILTER_TLV_FLAGS_MSDU_END)
1194
1195 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1196 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1197
1198 struct htt_rx_ring_selection_cfg_cmd {
1199 __le32 info0;
1200 __le32 info1;
1201 __le32 pkt_type_en_flags0;
1202 __le32 pkt_type_en_flags1;
1203 __le32 pkt_type_en_flags2;
1204 __le32 pkt_type_en_flags3;
1205 __le32 rx_filter_tlv;
1206 __le32 rx_packet_offset;
1207 __le32 rx_mpdu_offset;
1208 __le32 rx_msdu_offset;
1209 __le32 rx_attn_offset;
1210 __le32 info2;
1211 __le32 reserved[2];
1212 __le32 rx_mpdu_start_end_mask;
1213 __le32 rx_msdu_end_word_mask;
1214 __le32 info3;
1215 } __packed;
1216
1217 #define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32
1218 #define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7
1219 #define HTT_RX_RING_PKT_TLV_OFFSET 0x1
1220
1221 struct htt_rx_ring_tlv_filter {
1222 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
1223 u32 pkt_filter_flags0; /* MGMT */
1224 u32 pkt_filter_flags1; /* MGMT */
1225 u32 pkt_filter_flags2; /* CTRL */
1226 u32 pkt_filter_flags3; /* DATA */
1227 bool offset_valid;
1228 u16 rx_packet_offset;
1229 u16 rx_header_offset;
1230 u16 rx_mpdu_end_offset;
1231 u16 rx_mpdu_start_offset;
1232 u16 rx_msdu_end_offset;
1233 u16 rx_msdu_start_offset;
1234 u16 rx_attn_offset;
1235 u16 rx_mpdu_start_wmask;
1236 u16 rx_mpdu_end_wmask;
1237 u32 rx_msdu_end_wmask;
1238 u32 conf_len_ctrl;
1239 u32 conf_len_mgmt;
1240 u32 conf_len_data;
1241 u16 rx_drop_threshold;
1242 bool enable_log_mgmt_type;
1243 bool enable_log_ctrl_type;
1244 bool enable_log_data_type;
1245 bool enable_rx_tlv_offset;
1246 u16 rx_tlv_offset;
1247 bool drop_threshold_valid;
1248 bool rxmon_disable;
1249 };
1250
1251 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0
1252 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1
1253 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2
1254 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3
1255
1256 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1257 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1258 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
1259 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
1260 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
1261
1262 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0)
1263 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16)
1264 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19)
1265 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22)
1266 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25)
1267
1268 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0)
1269
1270 struct htt_tx_ring_selection_cfg_cmd {
1271 __le32 info0;
1272 __le32 info1;
1273 __le32 info2;
1274 __le32 tlv_filter_mask_in0;
1275 __le32 tlv_filter_mask_in1;
1276 __le32 tlv_filter_mask_in2;
1277 __le32 tlv_filter_mask_in3;
1278 __le32 reserved[3];
1279 } __packed;
1280
1281 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)
1282 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4)
1283 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8)
1284
1285 #define HTT_TX_MON_FILTER_HYBRID_MODE \
1286 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \
1287 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \
1288 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \
1289 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \
1290 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \
1291 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \
1292 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \
1293 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \
1294 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \
1295 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \
1296 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \
1297 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \
1298 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2)
1299
1300 struct htt_tx_ring_tlv_filter {
1301 u32 tx_mon_downstream_tlv_flags;
1302 u32 tx_mon_upstream_tlv_flags0;
1303 u32 tx_mon_upstream_tlv_flags1;
1304 u32 tx_mon_upstream_tlv_flags2;
1305 bool tx_mon_mgmt_filter;
1306 bool tx_mon_data_filter;
1307 bool tx_mon_ctrl_filter;
1308 u16 tx_mon_pkt_dma_len;
1309 } __packed;
1310
1311 enum htt_tx_mon_upstream_tlv_flags0 {
1312 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1),
1313 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2),
1314 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3),
1315 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4),
1316 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5),
1317 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6),
1318 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7),
1319 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8),
1320 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9),
1321 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10),
1322 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11),
1323 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12),
1324 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13),
1325 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14),
1326 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15),
1327 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16),
1328 };
1329
1330 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11)
1331
1332 /* HTT message target->host */
1333
1334 enum htt_t2h_msg_type {
1335 HTT_T2H_MSG_TYPE_VERSION_CONF,
1336 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
1337 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
1338 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
1339 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
1340 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
1341 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
1342 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
1343 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1344 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1345 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1346 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,
1347 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b,
1348 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c,
1349 };
1350
1351 #define HTT_TARGET_VERSION_MAJOR 3
1352
1353 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1354 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
1355 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
1356
1357 struct htt_t2h_version_conf_msg {
1358 __le32 version;
1359 } __packed;
1360
1361 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
1362 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
1363 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
1364 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
1365 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
1366 #define HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID GENMASK(15, 0)
1367 #define HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL GENMASK(31, 16)
1368 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1369 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
1370
1371 struct htt_t2h_peer_map_event {
1372 __le32 info;
1373 __le32 mac_addr_l32;
1374 __le32 info1;
1375 __le32 info2;
1376 } __packed;
1377
1378 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1379 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1380 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1381 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1382 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1383 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1384
1385 struct htt_t2h_peer_unmap_event {
1386 __le32 info;
1387 __le32 mac_addr_l32;
1388 __le32 info1;
1389 } __packed;
1390
1391 struct htt_resp_msg {
1392 union {
1393 struct htt_t2h_version_conf_msg version_msg;
1394 struct htt_t2h_peer_map_event peer_map_ev;
1395 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1396 };
1397 } __packed;
1398
1399 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\
1400 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32)))
1401 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0)
1402 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8)
1403 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16)
1404 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0)
1405 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0
1406 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1
1407
1408 struct htt_t2h_vdev_txrx_stats_ind {
1409 __le32 vdev_id;
1410 __le32 rx_msdu_byte_cnt_lo;
1411 __le32 rx_msdu_byte_cnt_hi;
1412 __le32 rx_msdu_cnt_lo;
1413 __le32 rx_msdu_cnt_hi;
1414 __le32 tx_msdu_byte_cnt_lo;
1415 __le32 tx_msdu_byte_cnt_hi;
1416 __le32 tx_msdu_cnt_lo;
1417 __le32 tx_msdu_cnt_hi;
1418 __le32 tx_retry_cnt_lo;
1419 __le32 tx_retry_cnt_hi;
1420 __le32 tx_retry_byte_cnt_lo;
1421 __le32 tx_retry_byte_cnt_hi;
1422 __le32 tx_drop_cnt_lo;
1423 __le32 tx_drop_cnt_hi;
1424 __le32 tx_drop_byte_cnt_lo;
1425 __le32 tx_drop_byte_cnt_hi;
1426 __le32 msdu_ttl_cnt_lo;
1427 __le32 msdu_ttl_cnt_hi;
1428 __le32 msdu_ttl_byte_cnt_lo;
1429 __le32 msdu_ttl_byte_cnt_hi;
1430 } __packed;
1431
1432 struct htt_t2h_vdev_common_stats_tlv {
1433 __le32 soc_drop_count_lo;
1434 __le32 soc_drop_count_hi;
1435 } __packed;
1436
1437 /* ppdu stats
1438 *
1439 * @details
1440 * The following field definitions describe the format of the HTT target
1441 * to host ppdu stats indication message.
1442 *
1443 *
1444 * |31 16|15 12|11 10|9 8|7 0 |
1445 * |----------------------------------------------------------------------|
1446 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1447 * |----------------------------------------------------------------------|
1448 * | ppdu_id |
1449 * |----------------------------------------------------------------------|
1450 * | Timestamp in us |
1451 * |----------------------------------------------------------------------|
1452 * | reserved |
1453 * |----------------------------------------------------------------------|
1454 * | type-specific stats info |
1455 * | (see htt_ppdu_stats.h) |
1456 * |----------------------------------------------------------------------|
1457 * Header fields:
1458 * - MSG_TYPE
1459 * Bits 7:0
1460 * Purpose: Identifies this is a PPDU STATS indication
1461 * message.
1462 * Value: 0x1d
1463 * - mac_id
1464 * Bits 9:8
1465 * Purpose: mac_id of this ppdu_id
1466 * Value: 0-3
1467 * - pdev_id
1468 * Bits 11:10
1469 * Purpose: pdev_id of this ppdu_id
1470 * Value: 0-3
1471 * 0 (for rings at SOC level),
1472 * 1/2/3 PDEV -> 0/1/2
1473 * - payload_size
1474 * Bits 31:16
1475 * Purpose: total tlv size
1476 * Value: payload_size in bytes
1477 */
1478
1479 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1480 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1481
1482 struct ath12k_htt_ppdu_stats_msg {
1483 __le32 info;
1484 __le32 ppdu_id;
1485 __le32 timestamp;
1486 __le32 rsvd;
1487 u8 data[];
1488 } __packed;
1489
1490 struct htt_tlv {
1491 __le32 header;
1492 u8 value[];
1493 } __packed;
1494
1495 #define HTT_TLV_TAG GENMASK(11, 0)
1496 #define HTT_TLV_LEN GENMASK(23, 12)
1497
1498 enum HTT_PPDU_STATS_BW {
1499 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1500 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1501 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1502 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1503 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1504 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1505 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1506 };
1507
1508 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1509 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1510 /* bw - HTT_PPDU_STATS_BW */
1511 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1512
1513 struct htt_ppdu_stats_common {
1514 __le32 ppdu_id;
1515 __le16 sched_cmdid;
1516 u8 ring_id;
1517 u8 num_users;
1518 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1519 __le32 chain_mask;
1520 __le32 fes_duration_us; /* frame exchange sequence */
1521 __le32 ppdu_sch_eval_start_tstmp_us;
1522 __le32 ppdu_sch_end_tstmp_us;
1523 __le32 ppdu_start_tstmp_us;
1524 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1525 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1526 */
1527 __le16 phy_mode;
1528 __le16 bw_mhz;
1529 } __packed;
1530
1531 enum htt_ppdu_stats_gi {
1532 HTT_PPDU_STATS_SGI_0_8_US,
1533 HTT_PPDU_STATS_SGI_0_4_US,
1534 HTT_PPDU_STATS_SGI_1_6_US,
1535 HTT_PPDU_STATS_SGI_3_2_US,
1536 };
1537
1538 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1539 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1540
1541 enum HTT_PPDU_STATS_PPDU_TYPE {
1542 HTT_PPDU_STATS_PPDU_TYPE_SU,
1543 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,
1544 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA,
1545 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA,
1546 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG,
1547 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN,
1548 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP,
1549 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG,
1550 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP,
1551 HTT_PPDU_STATS_PPDU_TYPE_MAX
1552 };
1553
1554 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1555 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1556
1557 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1558 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1559 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1560 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1561 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1562 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1563 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1564 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1565 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1566 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1567 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1568
1569 #define HTT_USR_RATE_PPDU_TYPE(_val) \
1570 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M)
1571 #define HTT_USR_RATE_PREAMBLE(_val) \
1572 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M)
1573 #define HTT_USR_RATE_BW(_val) \
1574 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M)
1575 #define HTT_USR_RATE_NSS(_val) \
1576 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M)
1577 #define HTT_USR_RATE_MCS(_val) \
1578 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M)
1579 #define HTT_USR_RATE_GI(_val) \
1580 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M)
1581 #define HTT_USR_RATE_DCM(_val) \
1582 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M)
1583
1584 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1585 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1586 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1587 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1588 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1589 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1590 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1591 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1592 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1593 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1594 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1595
1596 struct htt_ppdu_stats_user_rate {
1597 u8 tid_num;
1598 u8 reserved0;
1599 __le16 sw_peer_id;
1600 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1601 __le16 ru_end;
1602 __le16 ru_start;
1603 __le16 resp_ru_end;
1604 __le16 resp_ru_start;
1605 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1606 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1607 /* Note: resp_rate_info is only valid for if resp_type is UL */
1608 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1609 } __packed;
1610
1611 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1612 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1613 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1614 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1615 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1616 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1617
1618 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1619 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M)
1620 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1621 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M)
1622 #define HTT_TX_INFO_RATECODE(_flags) \
1623 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M)
1624 #define HTT_TX_INFO_PEERID(_flags) \
1625 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M)
1626
1627 enum htt_ppdu_stats_usr_compln_status {
1628 HTT_PPDU_STATS_USER_STATUS_OK,
1629 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1630 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1631 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1632 HTT_PPDU_STATS_USER_STATUS_ABORT,
1633 };
1634
1635 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1636 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1637 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1638 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1639
1640 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1641 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M)
1642 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1643 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M)
1644 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1645 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M)
1646
1647 struct htt_ppdu_stats_usr_cmpltn_cmn {
1648 u8 status;
1649 u8 tid_num;
1650 __le16 sw_peer_id;
1651 /* RSSI value of last ack packet (units = dB above noise floor) */
1652 __le32 ack_rssi;
1653 __le16 mpdu_tried;
1654 __le16 mpdu_success;
1655 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1656 } __packed;
1657
1658 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1659 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1660 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1661
1662 #define HTT_PPDU_STATS_NON_QOS_TID 16
1663
1664 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1665 __le32 ppdu_id;
1666 __le16 sw_peer_id;
1667 __le16 reserved0;
1668 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1669 __le16 current_seq;
1670 __le16 start_seq;
1671 __le32 success_bytes;
1672 } __packed;
1673
1674 struct htt_ppdu_user_stats {
1675 u16 peer_id;
1676 u16 delay_ba;
1677 u32 tlv_flags;
1678 bool is_valid_peer_id;
1679 struct htt_ppdu_stats_user_rate rate;
1680 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1681 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1682 };
1683
1684 #define HTT_PPDU_STATS_MAX_USERS 8
1685 #define HTT_PPDU_DESC_MAX_DEPTH 16
1686
1687 struct htt_ppdu_stats {
1688 struct htt_ppdu_stats_common common;
1689 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1690 };
1691
1692 struct htt_ppdu_stats_info {
1693 u32 tlv_bitmap;
1694 u32 ppdu_id;
1695 u32 frame_type;
1696 u32 frame_ctrl;
1697 u32 delay_ba;
1698 u32 bar_num_users;
1699 struct htt_ppdu_stats ppdu_stats;
1700 struct list_head list;
1701 };
1702
1703 /* @brief target -> host MLO offset indiciation message
1704 *
1705 * @details
1706 * The following field definitions describe the format of the HTT target
1707 * to host mlo offset indication message.
1708 *
1709 *
1710 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0|
1711 * |---------------------------------------------------------------------|
1712 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype|
1713 * |---------------------------------------------------------------------|
1714 * | sync_timestamp_lo_us |
1715 * |---------------------------------------------------------------------|
1716 * | sync_timestamp_hi_us |
1717 * |---------------------------------------------------------------------|
1718 * | mlo_offset_lo |
1719 * |---------------------------------------------------------------------|
1720 * | mlo_offset_hi |
1721 * |---------------------------------------------------------------------|
1722 * | mlo_offset_clcks |
1723 * |---------------------------------------------------------------------|
1724 * | rsvd2 | mlo_comp_clks |mlo_comp_us |
1725 * |---------------------------------------------------------------------|
1726 * | rsvd3 |mlo_comp_timer |
1727 * |---------------------------------------------------------------------|
1728 * Header fields
1729 * - MSG_TYPE
1730 * Bits 7:0
1731 * Purpose: Identifies this is a MLO offset indication msg
1732 * - PDEV_ID
1733 * Bits 9:8
1734 * Purpose: Pdev of this MLO offset
1735 * - CHIP_ID
1736 * Bits 12:10
1737 * Purpose: chip_id of this MLO offset
1738 * - MAC_FREQ
1739 * Bits 28:13
1740 * - SYNC_TIMESTAMP_LO_US
1741 * Purpose: clock frequency of the mac HW block in MHz
1742 * Bits: 31:0
1743 * Purpose: lower 32 bits of the WLAN global time stamp at which
1744 * last sync interrupt was received
1745 * - SYNC_TIMESTAMP_HI_US
1746 * Bits: 31:0
1747 * Purpose: upper 32 bits of WLAN global time stamp at which
1748 * last sync interrupt was received
1749 * - MLO_OFFSET_LO
1750 * Bits: 31:0
1751 * Purpose: lower 32 bits of the MLO offset in us
1752 * - MLO_OFFSET_HI
1753 * Bits: 31:0
1754 * Purpose: upper 32 bits of the MLO offset in us
1755 * - MLO_COMP_US
1756 * Bits: 15:0
1757 * Purpose: MLO time stamp compensation applied in us
1758 * - MLO_COMP_CLCKS
1759 * Bits: 25:16
1760 * Purpose: MLO time stamp compensation applied in clock ticks
1761 * - MLO_COMP_TIMER
1762 * Bits: 21:0
1763 * Purpose: Periodic timer at which compensation is applied
1764 */
1765
1766 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0)
1767 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8)
1768
1769 struct ath12k_htt_mlo_offset_msg {
1770 __le32 info;
1771 __le32 sync_timestamp_lo_us;
1772 __le32 sync_timestamp_hi_us;
1773 __le32 mlo_offset_hi;
1774 __le32 mlo_offset_lo;
1775 __le32 mlo_offset_clks;
1776 __le32 mlo_comp_clks;
1777 __le32 mlo_comp_timer;
1778 } __packed;
1779
1780 /* @brief host -> target FW extended statistics retrieve
1781 *
1782 * @details
1783 * The following field definitions describe the format of the HTT host
1784 * to target FW extended stats retrieve message.
1785 * The message specifies the type of stats the host wants to retrieve.
1786 *
1787 * |31 24|23 16|15 8|7 0|
1788 * |-----------------------------------------------------------|
1789 * | reserved | stats type | pdev_mask | msg type |
1790 * |-----------------------------------------------------------|
1791 * | config param [0] |
1792 * |-----------------------------------------------------------|
1793 * | config param [1] |
1794 * |-----------------------------------------------------------|
1795 * | config param [2] |
1796 * |-----------------------------------------------------------|
1797 * | config param [3] |
1798 * |-----------------------------------------------------------|
1799 * | reserved |
1800 * |-----------------------------------------------------------|
1801 * | cookie LSBs |
1802 * |-----------------------------------------------------------|
1803 * | cookie MSBs |
1804 * |-----------------------------------------------------------|
1805 * Header fields:
1806 * - MSG_TYPE
1807 * Bits 7:0
1808 * Purpose: identifies this is a extended stats upload request message
1809 * Value: 0x10
1810 * - PDEV_MASK
1811 * Bits 8:15
1812 * Purpose: identifies the mask of PDEVs to retrieve stats from
1813 * Value: This is a overloaded field, refer to usage and interpretation of
1814 * PDEV in interface document.
1815 * Bit 8 : Reserved for SOC stats
1816 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1817 * Indicates MACID_MASK in DBS
1818 * - STATS_TYPE
1819 * Bits 23:16
1820 * Purpose: identifies which FW statistics to upload
1821 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1822 * - Reserved
1823 * Bits 31:24
1824 * - CONFIG_PARAM [0]
1825 * Bits 31:0
1826 * Purpose: give an opaque configuration value to the specified stats type
1827 * Value: stats-type specific configuration value
1828 * Refer to htt_stats.h for interpretation for each stats sub_type
1829 * - CONFIG_PARAM [1]
1830 * Bits 31:0
1831 * Purpose: give an opaque configuration value to the specified stats type
1832 * Value: stats-type specific configuration value
1833 * Refer to htt_stats.h for interpretation for each stats sub_type
1834 * - CONFIG_PARAM [2]
1835 * Bits 31:0
1836 * Purpose: give an opaque configuration value to the specified stats type
1837 * Value: stats-type specific configuration value
1838 * Refer to htt_stats.h for interpretation for each stats sub_type
1839 * - CONFIG_PARAM [3]
1840 * Bits 31:0
1841 * Purpose: give an opaque configuration value to the specified stats type
1842 * Value: stats-type specific configuration value
1843 * Refer to htt_stats.h for interpretation for each stats sub_type
1844 * - Reserved [31:0] for future use.
1845 * - COOKIE_LSBS
1846 * Bits 31:0
1847 * Purpose: Provide a mechanism to match a target->host stats confirmation
1848 * message with its preceding host->target stats request message.
1849 * Value: LSBs of the opaque cookie specified by the host-side requestor
1850 * - COOKIE_MSBS
1851 * Bits 31:0
1852 * Purpose: Provide a mechanism to match a target->host stats confirmation
1853 * message with its preceding host->target stats request message.
1854 * Value: MSBs of the opaque cookie specified by the host-side requestor
1855 */
1856
1857 struct htt_ext_stats_cfg_hdr {
1858 u8 msg_type;
1859 u8 pdev_mask;
1860 u8 stats_type;
1861 u8 reserved;
1862 } __packed;
1863
1864 struct htt_ext_stats_cfg_cmd {
1865 struct htt_ext_stats_cfg_hdr hdr;
1866 __le32 cfg_param0;
1867 __le32 cfg_param1;
1868 __le32 cfg_param2;
1869 __le32 cfg_param3;
1870 __le32 reserved;
1871 __le32 cookie_lsb;
1872 __le32 cookie_msb;
1873 } __packed;
1874
1875 /* htt stats config default params */
1876 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1877 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1878 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1879 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1880 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1881 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1882 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1883 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1884
1885 /* HTT_DBG_EXT_STATS_PEER_INFO
1886 * PARAMS:
1887 * @config_param0:
1888 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1889 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1890 * [Bit31 : Bit16] sw_peer_id
1891 * @config_param1:
1892 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1893 * 0 bit htt_peer_stats_cmn_tlv
1894 * 1 bit htt_peer_details_tlv
1895 * 2 bit htt_tx_peer_rate_stats_tlv
1896 * 3 bit htt_rx_peer_rate_stats_tlv
1897 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1898 * 5 bit htt_rx_tid_stats_tlv
1899 * 6 bit htt_msdu_flow_stats_tlv
1900 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1901 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1902 * [Bit31 : Bit16] reserved
1903 */
1904 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1905 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1906
1907 /* Used to set different configs to the specified stats type.*/
1908 struct htt_ext_stats_cfg_params {
1909 u32 cfg0;
1910 u32 cfg1;
1911 u32 cfg2;
1912 u32 cfg3;
1913 };
1914
1915 enum vdev_stats_offload_timer_duration {
1916 ATH12K_STATS_TIMER_DUR_500MS = 1,
1917 ATH12K_STATS_TIMER_DUR_1SEC = 2,
1918 ATH12K_STATS_TIMER_DUR_2SEC = 3,
1919 };
1920
1921 #define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0)
1922 #define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8)
1923 #define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16)
1924 #define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24)
1925 #define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0)
1926 #define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8)
1927
1928 struct htt_mac_addr {
1929 __le32 mac_addr_l32;
1930 __le32 mac_addr_h16;
1931 } __packed;
1932
ath12k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1933 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1934 {
1935 memcpy(addr, &addr_l32, 4);
1936 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1937 }
1938
1939 int ath12k_dp_service_srng(struct ath12k_base *ab,
1940 struct ath12k_ext_irq_grp *irq_grp,
1941 int budget);
1942 int ath12k_dp_htt_connect(struct ath12k_dp *dp);
1943 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif);
1944 void ath12k_dp_free(struct ath12k_base *ab);
1945 int ath12k_dp_alloc(struct ath12k_base *ab);
1946 void ath12k_dp_cc_config(struct ath12k_base *ab);
1947 void ath12k_dp_partner_cc_init(struct ath12k_base *ab);
1948 int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
1949 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar);
1950 void ath12k_dp_pdev_free(struct ath12k_base *ab);
1951 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
1952 int mac_id, enum hal_ring_type ring_type);
1953 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);
1954 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);
1955 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);
1956 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
1957 enum hal_ring_type type, int ring_num,
1958 int mac_id, int num_entries);
1959 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
1960 struct dp_link_desc_bank *desc_bank,
1961 u32 ring_type, struct dp_srng *ring);
1962 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
1963 struct dp_link_desc_bank *link_desc_banks,
1964 u32 ring_type, struct hal_srng *srng,
1965 u32 n_link_desc);
1966 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1967 u32 cookie);
1968 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1969 u32 desc_id);
1970 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab);
1971 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab);
1972 #endif
1973