1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Type definitions for the Microsoft hypervisor. 4 */ 5 #ifndef _HV_HVGDK_MINI_H 6 #define _HV_HVGDK_MINI_H 7 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 11 struct hv_u128 { 12 u64 low_part; 13 u64 high_part; 14 } __packed; 15 16 /* NOTE: when adding below, update hv_result_to_string() */ 17 #define HV_STATUS_SUCCESS 0x0 18 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 19 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 20 #define HV_STATUS_INVALID_ALIGNMENT 0x4 21 #define HV_STATUS_INVALID_PARAMETER 0x5 22 #define HV_STATUS_ACCESS_DENIED 0x6 23 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 24 #define HV_STATUS_OPERATION_DENIED 0x8 25 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 26 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA 27 #define HV_STATUS_INSUFFICIENT_MEMORY 0xB 28 #define HV_STATUS_INVALID_PARTITION_ID 0xD 29 #define HV_STATUS_INVALID_VP_INDEX 0xE 30 #define HV_STATUS_NOT_FOUND 0x10 31 #define HV_STATUS_INVALID_PORT_ID 0x11 32 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 33 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 34 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 35 #define HV_STATUS_INVALID_VP_STATE 0x15 36 #define HV_STATUS_NO_RESOURCES 0x1D 37 #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 38 #define HV_STATUS_INVALID_LP_INDEX 0x41 39 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 40 #define HV_STATUS_OPERATION_FAILED 0x71 41 #define HV_STATUS_TIME_OUT 0x78 42 #define HV_STATUS_CALL_PENDING 0x79 43 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 44 45 /* 46 * The Hyper-V TimeRefCount register and the TSC 47 * page provide a guest VM clock with 100ns tick rate 48 */ 49 #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) 50 51 #define HV_HYP_PAGE_SHIFT 12 52 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) 53 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 54 #define HV_HYP_LARGE_PAGE_SHIFT 21 55 56 #define HV_PARTITION_ID_INVALID ((u64)0) 57 #define HV_PARTITION_ID_SELF ((u64)-1) 58 59 /* Hyper-V specific model specific registers (MSRs) */ 60 61 #if defined(CONFIG_X86) 62 /* HV_X64_SYNTHETIC_MSR */ 63 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 64 #define HV_X64_MSR_HYPERCALL 0x40000001 65 #define HV_X64_MSR_VP_INDEX 0x40000002 66 #define HV_X64_MSR_RESET 0x40000003 67 #define HV_X64_MSR_VP_RUNTIME 0x40000010 68 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 69 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 70 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 71 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 72 73 /* Define the virtual APIC registers */ 74 #define HV_X64_MSR_EOI 0x40000070 75 #define HV_X64_MSR_ICR 0x40000071 76 #define HV_X64_MSR_TPR 0x40000072 77 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 78 79 /* Define synthetic interrupt controller model specific registers. */ 80 #define HV_X64_MSR_SCONTROL 0x40000080 81 #define HV_X64_MSR_SVERSION 0x40000081 82 #define HV_X64_MSR_SIEFP 0x40000082 83 #define HV_X64_MSR_SIMP 0x40000083 84 #define HV_X64_MSR_EOM 0x40000084 85 #define HV_X64_MSR_SIRBP 0x40000085 86 #define HV_X64_MSR_SINT0 0x40000090 87 #define HV_X64_MSR_SINT1 0x40000091 88 #define HV_X64_MSR_SINT2 0x40000092 89 #define HV_X64_MSR_SINT3 0x40000093 90 #define HV_X64_MSR_SINT4 0x40000094 91 #define HV_X64_MSR_SINT5 0x40000095 92 #define HV_X64_MSR_SINT6 0x40000096 93 #define HV_X64_MSR_SINT7 0x40000097 94 #define HV_X64_MSR_SINT8 0x40000098 95 #define HV_X64_MSR_SINT9 0x40000099 96 #define HV_X64_MSR_SINT10 0x4000009A 97 #define HV_X64_MSR_SINT11 0x4000009B 98 #define HV_X64_MSR_SINT12 0x4000009C 99 #define HV_X64_MSR_SINT13 0x4000009D 100 #define HV_X64_MSR_SINT14 0x4000009E 101 #define HV_X64_MSR_SINT15 0x4000009F 102 103 /* Define synthetic interrupt controller model specific registers for nested hypervisor */ 104 #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 105 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 106 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 107 #define HV_X64_MSR_NESTED_SIMP 0x40001083 108 #define HV_X64_MSR_NESTED_EOM 0x40001084 109 #define HV_X64_MSR_NESTED_SINT0 0x40001090 110 111 /* 112 * Synthetic Timer MSRs. Four timers per vcpu. 113 */ 114 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 115 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 116 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 117 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 118 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 119 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 120 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 121 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 122 123 /* Hyper-V guest idle MSR */ 124 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 125 126 /* Hyper-V guest crash notification MSR's */ 127 #define HV_X64_MSR_CRASH_P0 0x40000100 128 #define HV_X64_MSR_CRASH_P1 0x40000101 129 #define HV_X64_MSR_CRASH_P2 0x40000102 130 #define HV_X64_MSR_CRASH_P3 0x40000103 131 #define HV_X64_MSR_CRASH_P4 0x40000104 132 #define HV_X64_MSR_CRASH_CTL 0x40000105 133 134 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 135 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 136 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 137 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 138 139 #define HV_X64_MSR_CRASH_PARAMS \ 140 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 141 142 #define HV_IPI_LOW_VECTOR 0x10 143 #define HV_IPI_HIGH_VECTOR 0xff 144 145 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 146 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 147 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 148 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 149 150 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 151 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 152 153 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 154 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 155 156 /* Number of XMM registers used in hypercall input/output */ 157 #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 158 159 struct hv_reenlightenment_control { 160 u64 vector : 8; 161 u64 reserved1 : 8; 162 u64 enabled : 1; 163 u64 reserved2 : 15; 164 u64 target_vp : 32; 165 } __packed; 166 167 struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ 168 u64 inprogress : 1; 169 u64 reserved : 63; 170 } __packed; 171 172 struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ 173 u64 enabled : 1; 174 u64 reserved : 63; 175 } __packed; 176 177 /* TSC emulation after migration */ 178 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 179 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 180 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 181 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 182 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) 183 184 #endif /* CONFIG_X86 */ 185 186 struct hv_output_get_partition_id { 187 u64 partition_id; 188 } __packed; 189 190 /* HV_CRASH_CTL_REG_CONTENTS */ 191 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 192 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 193 194 union hv_reference_tsc_msr { 195 u64 as_uint64; 196 struct { 197 u64 enable : 1; 198 u64 reserved : 11; 199 u64 pfn : 52; 200 } __packed; 201 }; 202 203 /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */ 204 #define HV_MAX_SPARSE_VCPU_BANKS (64) 205 /* The number of vCPUs in one sparse bank */ 206 #define HV_VCPUS_PER_SPARSE_BANK (64) 207 208 /* 209 * Some of Hyper-V structs do not use hv_vpset where linux uses them. 210 * 211 * struct hv_vpset is usually used as part of hypercall input. The portion 212 * that counts as "fixed size input header" vs. "variable size input header" 213 * varies per hypercall. See comments at relevant hypercall call sites as to 214 * how the "valid_bank_mask" field should be accounted. 215 */ 216 struct hv_vpset { /* HV_VP_SET */ 217 u64 format; 218 u64 valid_bank_mask; 219 u64 bank_contents[]; 220 } __packed; 221 222 /* 223 * Version info reported by hypervisor 224 * Changed to a union for convenience 225 */ 226 union hv_hypervisor_version_info { 227 struct { 228 u32 build_number; 229 230 u32 minor_version : 16; 231 u32 major_version : 16; 232 233 u32 service_pack; 234 235 u32 service_number : 24; 236 u32 service_branch : 8; 237 }; 238 struct { 239 u32 eax; 240 u32 ebx; 241 u32 ecx; 242 u32 edx; 243 }; 244 }; 245 246 /* HV_CPUID_FUNCTION */ 247 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 248 #define HYPERV_CPUID_INTERFACE 0x40000001 249 #define HYPERV_CPUID_VERSION 0x40000002 250 #define HYPERV_CPUID_FEATURES 0x40000003 251 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 252 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 253 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 254 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 255 #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C 256 257 #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 258 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ 259 260 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 261 /* Support for the extended IOAPIC RTE format */ 262 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) 263 264 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 265 #define HYPERV_CPUID_MIN 0x40000005 266 #define HYPERV_CPUID_MAX 0x4000ffff 267 268 /* 269 * HV_X64_HYPERVISOR_FEATURES (EAX), or 270 * HV_PARTITION_PRIVILEGE_MASK [31-0] 271 */ 272 #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0) 273 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) 274 #define HV_MSR_SYNIC_AVAILABLE BIT(2) 275 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) 276 #define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4) 277 #define HV_MSR_HYPERCALL_AVAILABLE BIT(5) 278 #define HV_MSR_VP_INDEX_AVAILABLE BIT(6) 279 #define HV_MSR_RESET_AVAILABLE BIT(7) 280 #define HV_MSR_STAT_PAGES_AVAILABLE BIT(8) 281 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) 282 #define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10) 283 #define HV_ACCESS_FREQUENCY_MSRS BIT(11) 284 #define HV_ACCESS_REENLIGHTENMENT BIT(13) 285 #define HV_ACCESS_TSC_INVARIANT BIT(15) 286 287 /* 288 * HV_X64_HYPERVISOR_FEATURES (EBX), or 289 * HV_PARTITION_PRIVILEGE_MASK [63-32] 290 */ 291 #define HV_CREATE_PARTITIONS BIT(0) 292 #define HV_ACCESS_PARTITION_ID BIT(1) 293 #define HV_ACCESS_MEMORY_POOL BIT(2) 294 #define HV_ADJUST_MESSAGE_BUFFERS BIT(3) 295 #define HV_POST_MESSAGES BIT(4) 296 #define HV_SIGNAL_EVENTS BIT(5) 297 #define HV_CREATE_PORT BIT(6) 298 #define HV_CONNECT_PORT BIT(7) 299 #define HV_ACCESS_STATS BIT(8) 300 #define HV_DEBUGGING BIT(11) 301 #define HV_CPU_MANAGEMENT BIT(12) 302 #define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20) 303 #define HV_ISOLATION BIT(22) 304 305 #if defined(CONFIG_X86) 306 /* HV_X64_HYPERVISOR_FEATURES (EDX) */ 307 #define HV_X64_MWAIT_AVAILABLE BIT(0) 308 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 309 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 310 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 311 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) 312 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 313 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 314 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 315 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 316 #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) 317 /* 318 * Support for returning hypercall output block via XMM 319 * registers is available 320 */ 321 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) 322 /* stimer Direct Mode is available */ 323 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 324 325 /* 326 * Implementation recommendations. Indicates which behaviors the hypervisor 327 * recommends the OS implement for optimal performance. 328 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 329 */ 330 /* HV_X64_ENLIGHTENMENT_INFORMATION */ 331 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 332 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 333 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 334 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 335 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 336 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 337 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 338 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 339 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 340 #define HV_X64_HYPERV_NESTED BIT(12) 341 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 342 #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) 343 344 /* 345 * CPU management features identification. 346 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. 347 */ 348 #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) 349 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) 350 #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) 351 #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) 352 353 /* 354 * Virtual processor will never share a physical core with another virtual 355 * processor, except for virtual processors that are reported as sibling SMT 356 * threads. 357 */ 358 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 359 360 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 361 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 362 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 363 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 364 365 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ 366 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) 367 368 /* 369 * This is specific to AMD and specifies that enlightened TLB flush is 370 * supported. If guest opts in to this feature, ASID invalidations only 371 * flushes gva -> hpa mapping entries. To flush the TLB entries derived 372 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace 373 * or HvFlushGuestPhysicalAddressList). 374 */ 375 #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) 376 377 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ 378 #define HV_PARAVISOR_PRESENT BIT(0) 379 380 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ 381 #define HV_ISOLATION_TYPE GENMASK(3, 0) 382 #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) 383 #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) 384 385 /* HYPERV_CPUID_FEATURES.ECX bits. */ 386 #define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9) 387 #define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10) 388 389 enum hv_isolation_type { 390 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ 391 HV_ISOLATION_TYPE_VBS = 1, 392 HV_ISOLATION_TYPE_SNP = 2, 393 HV_ISOLATION_TYPE_TDX = 3 394 }; 395 396 union hv_x64_msr_hypercall_contents { 397 u64 as_uint64; 398 struct { 399 u64 enable : 1; 400 u64 reserved : 11; 401 u64 guest_physical_address : 52; 402 } __packed; 403 }; 404 #endif /* CONFIG_X86 */ 405 406 #if defined(CONFIG_ARM64) 407 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8) 408 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) 409 #endif /* CONFIG_ARM64 */ 410 411 #if defined(CONFIG_X86) 412 #define HV_MAXIMUM_PROCESSORS 2048 413 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 414 #define HV_MAXIMUM_PROCESSORS 320 415 #endif /* CONFIG_ARM64 */ 416 417 #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1) 418 #define HV_VP_INDEX_SELF ((u32)-2) 419 #define HV_ANY_VP ((u32)-1) 420 421 union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ 422 u64 as_uint64; 423 struct { 424 u64 enable : 1; 425 u64 reserved : 11; 426 u64 pfn : 52; 427 } __packed; 428 }; 429 430 /* Declare the various hypercall operations. */ 431 /* HV_CALL_CODE */ 432 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 433 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 434 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 435 #define HVCALL_SEND_IPI 0x000b 436 #define HVCALL_ENABLE_VP_VTL 0x000f 437 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 438 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 439 #define HVCALL_SEND_IPI_EX 0x0015 440 #define HVCALL_CREATE_PARTITION 0x0040 441 #define HVCALL_INITIALIZE_PARTITION 0x0041 442 #define HVCALL_FINALIZE_PARTITION 0x0042 443 #define HVCALL_DELETE_PARTITION 0x0043 444 #define HVCALL_GET_PARTITION_PROPERTY 0x0044 445 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 446 #define HVCALL_GET_PARTITION_ID 0x0046 447 #define HVCALL_DEPOSIT_MEMORY 0x0048 448 #define HVCALL_WITHDRAW_MEMORY 0x0049 449 #define HVCALL_MAP_GPA_PAGES 0x004b 450 #define HVCALL_UNMAP_GPA_PAGES 0x004c 451 #define HVCALL_INSTALL_INTERCEPT 0x004d 452 #define HVCALL_CREATE_VP 0x004e 453 #define HVCALL_DELETE_VP 0x004f 454 #define HVCALL_GET_VP_REGISTERS 0x0050 455 #define HVCALL_SET_VP_REGISTERS 0x0051 456 #define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052 457 #define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056 458 #define HVCALL_DELETE_PORT 0x0058 459 #define HVCALL_DISCONNECT_PORT 0x005b 460 #define HVCALL_POST_MESSAGE 0x005c 461 #define HVCALL_SIGNAL_EVENT 0x005d 462 #define HVCALL_POST_DEBUG_DATA 0x0069 463 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a 464 #define HVCALL_RESET_DEBUG_SESSION 0x006b 465 #define HVCALL_MAP_STATS_PAGE 0x006c 466 #define HVCALL_UNMAP_STATS_PAGE 0x006d 467 #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076 468 #define HVCALL_GET_SYSTEM_PROPERTY 0x007b 469 #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c 470 #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d 471 #define HVCALL_RETARGET_INTERRUPT 0x007e 472 #define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b 473 #define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091 474 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094 475 #define HVCALL_CREATE_PORT 0x0095 476 #define HVCALL_CONNECT_PORT 0x0096 477 #define HVCALL_START_VP 0x0099 478 #define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a 479 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 480 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 481 #define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0 482 #define HVCALL_POST_MESSAGE_DIRECT 0x00c1 483 #define HVCALL_DISPATCH_VP 0x00c2 484 #define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9 485 #define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7 486 #define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8 487 #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db 488 #define HVCALL_MAP_VP_STATE_PAGE 0x00e1 489 #define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2 490 #define HVCALL_GET_VP_STATE 0x00e3 491 #define HVCALL_SET_VP_STATE 0x00e4 492 #define HVCALL_GET_VP_CPUID_VALUES 0x00f4 493 #define HVCALL_MMIO_READ 0x0106 494 #define HVCALL_MMIO_WRITE 0x0107 495 496 /* HV_HYPERCALL_INPUT */ 497 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 498 #define HV_HYPERCALL_FAST_BIT BIT(16) 499 #define HV_HYPERCALL_VARHEAD_OFFSET 17 500 #define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17) 501 #define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27) 502 #define HV_HYPERCALL_NESTED BIT_ULL(31) 503 #define HV_HYPERCALL_REP_COMP_OFFSET 32 504 #define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32) 505 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 506 #define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44) 507 #define HV_HYPERCALL_REP_START_OFFSET 48 508 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 509 #define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60) 510 #define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \ 511 HV_HYPERCALL_RSVD1_MASK | \ 512 HV_HYPERCALL_RSVD2_MASK) 513 514 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 515 struct hv_guest_mapping_flush { 516 u64 address_space; 517 u64 flags; 518 } __packed; 519 520 /* 521 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 522 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 523 */ 524 #define HV_MAX_FLUSH_PAGES (2048) 525 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0 526 #define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1 527 528 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 529 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 530 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 531 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 532 533 /* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */ 534 union hv_gpa_page_range { 535 u64 address_space; 536 struct { 537 u64 additional_pages : 11; 538 u64 largepage : 1; 539 u64 basepfn : 52; 540 } page; 541 struct { 542 u64 reserved : 12; 543 u64 page_size : 1; 544 u64 reserved1 : 8; 545 u64 base_large_pfn : 43; 546 }; 547 }; 548 549 /* 550 * All input flush parameters should be in single page. The max flush 551 * count is equal with how many entries of union hv_gpa_page_range can 552 * be populated into the input parameter page. 553 */ 554 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 555 sizeof(union hv_gpa_page_range)) 556 557 struct hv_guest_mapping_flush_list { 558 u64 address_space; 559 u64 flags; 560 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 561 }; 562 563 struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */ 564 u64 address_space; 565 u64 flags; 566 u64 processor_mask; 567 u64 gva_list[]; 568 } __packed; 569 570 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 571 struct hv_tlb_flush_ex { 572 u64 address_space; 573 u64 flags; 574 struct hv_vpset hv_vp_set; 575 u64 gva_list[]; 576 } __packed; 577 578 struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */ 579 volatile u32 tsc_sequence; 580 u32 reserved1; 581 volatile u64 tsc_scale; 582 volatile s64 tsc_offset; 583 } __packed; 584 585 /* Define the number of synthetic interrupt sources. */ 586 #define HV_SYNIC_SINT_COUNT (16) 587 588 /* Define the expected SynIC version. */ 589 #define HV_SYNIC_VERSION_1 (0x1) 590 /* Valid SynIC vectors are 16-255. */ 591 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 592 593 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 594 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 595 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 596 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 597 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 598 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 599 600 /* Hyper-V defined statically assigned SINTs */ 601 #define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000 602 #define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001 603 #define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002 604 #define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005 605 606 /* mshv assigned SINT for doorbell */ 607 #define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX 608 609 enum hv_interrupt_type { 610 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000, 611 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001, 612 HV_X64_INTERRUPT_TYPE_SMI = 0x0002, 613 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003, 614 HV_X64_INTERRUPT_TYPE_NMI = 0x0004, 615 HV_X64_INTERRUPT_TYPE_INIT = 0x0005, 616 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006, 617 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007, 618 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008, 619 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009, 620 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A, 621 }; 622 623 /* Define synthetic interrupt source. */ 624 union hv_synic_sint { 625 u64 as_uint64; 626 struct { 627 u64 vector : 8; 628 u64 reserved1 : 8; 629 u64 masked : 1; 630 u64 auto_eoi : 1; 631 u64 polling : 1; 632 u64 as_intercept : 1; 633 u64 proxy : 1; 634 u64 reserved2 : 43; 635 } __packed; 636 }; 637 638 union hv_x64_xsave_xfem_register { 639 u64 as_uint64; 640 struct { 641 u32 low_uint32; 642 u32 high_uint32; 643 } __packed; 644 struct { 645 u64 legacy_x87 : 1; 646 u64 legacy_sse : 1; 647 u64 avx : 1; 648 u64 mpx_bndreg : 1; 649 u64 mpx_bndcsr : 1; 650 u64 avx_512_op_mask : 1; 651 u64 avx_512_zmmhi : 1; 652 u64 avx_512_zmm16_31 : 1; 653 u64 rsvd8_9 : 2; 654 u64 pasid : 1; 655 u64 cet_u : 1; 656 u64 cet_s : 1; 657 u64 rsvd13_16 : 4; 658 u64 xtile_cfg : 1; 659 u64 xtile_data : 1; 660 u64 rsvd19_63 : 45; 661 } __packed; 662 }; 663 664 /* Synthetic timer configuration */ 665 union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */ 666 u64 as_uint64; 667 struct { 668 u64 enable : 1; 669 u64 periodic : 1; 670 u64 lazy : 1; 671 u64 auto_enable : 1; 672 u64 apic_vector : 8; 673 u64 direct_mode : 1; 674 u64 reserved_z0 : 3; 675 u64 sintx : 4; 676 u64 reserved_z1 : 44; 677 } __packed; 678 }; 679 680 /* Define the number of synthetic timers */ 681 #define HV_SYNIC_STIMER_COUNT (4) 682 683 /* Define port identifier type. */ 684 union hv_port_id { 685 u32 asu32; 686 struct { 687 u32 id : 24; 688 u32 reserved : 8; 689 } __packed u; 690 }; 691 692 #define HV_MESSAGE_SIZE (256) 693 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 694 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 695 696 /* Define hypervisor message types. */ 697 enum hv_message_type { 698 HVMSG_NONE = 0x00000000, 699 700 /* Memory access messages. */ 701 HVMSG_UNMAPPED_GPA = 0x80000000, 702 HVMSG_GPA_INTERCEPT = 0x80000001, 703 704 /* Timer notification messages. */ 705 HVMSG_TIMER_EXPIRED = 0x80000010, 706 707 /* Error messages. */ 708 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 709 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 710 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 711 712 /* 713 * Opaque intercept message. The original intercept message is only 714 * accessible from the mapped intercept message page. 715 */ 716 HVMSG_OPAQUE_INTERCEPT = 0x8000003F, 717 718 /* Trace buffer complete messages. */ 719 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 720 721 /* Hypercall intercept */ 722 HVMSG_HYPERCALL_INTERCEPT = 0x80000050, 723 724 /* SynIC intercepts */ 725 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060, 726 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061, 727 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062, 728 729 /* Async call completion intercept */ 730 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070, 731 732 /* Root scheduler messages */ 733 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100, 734 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101, 735 736 /* Platform-specific processor intercept messages. */ 737 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000, 738 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 739 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 740 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 741 HVMSG_X64_APIC_EOI = 0x80010004, 742 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005, 743 HVMSG_X64_IOMMU_PRQ = 0x80010006, 744 HVMSG_X64_HALT = 0x80010007, 745 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008, 746 HVMSG_X64_SIPI_INTERCEPT = 0x80010009, 747 }; 748 749 /* Define the format of the SIMP register */ 750 union hv_synic_simp { 751 u64 as_uint64; 752 struct { 753 u64 simp_enabled : 1; 754 u64 preserved : 11; 755 u64 base_simp_gpa : 52; 756 } __packed; 757 }; 758 759 union hv_message_flags { 760 u8 asu8; 761 struct { 762 u8 msg_pending : 1; 763 u8 reserved : 7; 764 } __packed; 765 }; 766 767 struct hv_message_header { 768 u32 message_type; 769 u8 payload_size; 770 union hv_message_flags message_flags; 771 u8 reserved[2]; 772 union { 773 u64 sender; 774 union hv_port_id port; 775 }; 776 } __packed; 777 778 /* 779 * Message format for notifications delivered via 780 * intercept message(as_intercept=1) 781 */ 782 struct hv_notification_message_payload { 783 u32 sint_index; 784 } __packed; 785 786 struct hv_message { 787 struct hv_message_header header; 788 union { 789 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 790 } u; 791 } __packed; 792 793 /* Define the synthetic interrupt message page layout. */ 794 struct hv_message_page { 795 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 796 } __packed; 797 798 /* Define timer message payload structure. */ 799 struct hv_timer_message_payload { 800 u32 timer_index; 801 u32 reserved; 802 u64 expiration_time; /* When the timer expired */ 803 u64 delivery_time; /* When the message was delivered */ 804 } __packed; 805 806 struct hv_x64_segment_register { 807 u64 base; 808 u32 limit; 809 u16 selector; 810 union { 811 struct { 812 u16 segment_type : 4; 813 u16 non_system_segment : 1; 814 u16 descriptor_privilege_level : 2; 815 u16 present : 1; 816 u16 reserved : 4; 817 u16 available : 1; 818 u16 _long : 1; 819 u16 _default : 1; 820 u16 granularity : 1; 821 } __packed; 822 u16 attributes; 823 }; 824 } __packed; 825 826 struct hv_x64_table_register { 827 u16 pad[3]; 828 u16 limit; 829 u64 base; 830 } __packed; 831 832 #define HV_NORMAL_VTL 0 833 834 union hv_input_vtl { 835 u8 as_uint8; 836 struct { 837 u8 target_vtl : 4; 838 u8 use_target_vtl : 1; 839 u8 reserved_z : 3; 840 }; 841 } __packed; 842 843 struct hv_init_vp_context { 844 u64 rip; 845 u64 rsp; 846 u64 rflags; 847 848 struct hv_x64_segment_register cs; 849 struct hv_x64_segment_register ds; 850 struct hv_x64_segment_register es; 851 struct hv_x64_segment_register fs; 852 struct hv_x64_segment_register gs; 853 struct hv_x64_segment_register ss; 854 struct hv_x64_segment_register tr; 855 struct hv_x64_segment_register ldtr; 856 857 struct hv_x64_table_register idtr; 858 struct hv_x64_table_register gdtr; 859 860 u64 efer; 861 u64 cr0; 862 u64 cr3; 863 u64 cr4; 864 u64 msr_cr_pat; 865 } __packed; 866 867 struct hv_enable_vp_vtl { 868 u64 partition_id; 869 u32 vp_index; 870 union hv_input_vtl target_vtl; 871 u8 mbz0; 872 u16 mbz1; 873 struct hv_init_vp_context vp_context; 874 } __packed; 875 876 struct hv_get_vp_from_apic_id_in { 877 u64 partition_id; 878 union hv_input_vtl target_vtl; 879 u8 res[7]; 880 u32 apic_ids[]; 881 } __packed; 882 883 struct hv_nested_enlightenments_control { 884 struct { 885 u32 directhypercall : 1; 886 u32 reserved : 31; 887 } __packed features; 888 struct { 889 u32 inter_partition_comm : 1; 890 u32 reserved : 31; 891 } __packed hypercall_controls; 892 } __packed; 893 894 /* Define virtual processor assist page structure. */ 895 struct hv_vp_assist_page { 896 u32 apic_assist; 897 u32 reserved1; 898 u32 vtl_entry_reason; 899 u32 vtl_reserved; 900 u64 vtl_ret_x64rax; 901 u64 vtl_ret_x64rcx; 902 struct hv_nested_enlightenments_control nested_control; 903 u8 enlighten_vmentry; 904 u8 reserved2[7]; 905 u64 current_nested_vmcs; 906 u8 synthetic_time_unhalted_timer_expired; 907 u8 reserved3[7]; 908 u8 virtualization_fault_information[40]; 909 u8 reserved4[8]; 910 u8 intercept_message[256]; 911 u8 vtl_ret_actions[256]; 912 } __packed; 913 914 enum hv_register_name { 915 /* Suspend Registers */ 916 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000, 917 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001, 918 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003, 919 920 /* Version - 128-bit result same as CPUID 0x40000002 */ 921 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100, 922 923 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */ 924 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200, 925 HV_REGISTER_FEATURES_INFO = 0x00000201, 926 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202, 927 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203, 928 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204, 929 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205, 930 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206, 931 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207, 932 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208, 933 934 /* Guest Crash Registers */ 935 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210, 936 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211, 937 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212, 938 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213, 939 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214, 940 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215, 941 942 /* Misc */ 943 HV_REGISTER_VP_RUNTIME = 0x00090000, 944 HV_REGISTER_GUEST_OS_ID = 0x00090002, 945 HV_REGISTER_VP_INDEX = 0x00090003, 946 HV_REGISTER_TIME_REF_COUNT = 0x00090004, 947 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007, 948 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013, 949 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014, 950 HV_REGISTER_REFERENCE_TSC = 0x00090017, 951 952 /* Hypervisor-defined Registers (Synic) */ 953 HV_REGISTER_SINT0 = 0x000A0000, 954 HV_REGISTER_SINT1 = 0x000A0001, 955 HV_REGISTER_SINT2 = 0x000A0002, 956 HV_REGISTER_SINT3 = 0x000A0003, 957 HV_REGISTER_SINT4 = 0x000A0004, 958 HV_REGISTER_SINT5 = 0x000A0005, 959 HV_REGISTER_SINT6 = 0x000A0006, 960 HV_REGISTER_SINT7 = 0x000A0007, 961 HV_REGISTER_SINT8 = 0x000A0008, 962 HV_REGISTER_SINT9 = 0x000A0009, 963 HV_REGISTER_SINT10 = 0x000A000A, 964 HV_REGISTER_SINT11 = 0x000A000B, 965 HV_REGISTER_SINT12 = 0x000A000C, 966 HV_REGISTER_SINT13 = 0x000A000D, 967 HV_REGISTER_SINT14 = 0x000A000E, 968 HV_REGISTER_SINT15 = 0x000A000F, 969 HV_REGISTER_SCONTROL = 0x000A0010, 970 HV_REGISTER_SVERSION = 0x000A0011, 971 HV_REGISTER_SIEFP = 0x000A0012, 972 HV_REGISTER_SIMP = 0x000A0013, 973 HV_REGISTER_EOM = 0x000A0014, 974 HV_REGISTER_SIRBP = 0x000A0015, 975 976 HV_REGISTER_NESTED_SINT0 = 0x000A1000, 977 HV_REGISTER_NESTED_SINT1 = 0x000A1001, 978 HV_REGISTER_NESTED_SINT2 = 0x000A1002, 979 HV_REGISTER_NESTED_SINT3 = 0x000A1003, 980 HV_REGISTER_NESTED_SINT4 = 0x000A1004, 981 HV_REGISTER_NESTED_SINT5 = 0x000A1005, 982 HV_REGISTER_NESTED_SINT6 = 0x000A1006, 983 HV_REGISTER_NESTED_SINT7 = 0x000A1007, 984 HV_REGISTER_NESTED_SINT8 = 0x000A1008, 985 HV_REGISTER_NESTED_SINT9 = 0x000A1009, 986 HV_REGISTER_NESTED_SINT10 = 0x000A100A, 987 HV_REGISTER_NESTED_SINT11 = 0x000A100B, 988 HV_REGISTER_NESTED_SINT12 = 0x000A100C, 989 HV_REGISTER_NESTED_SINT13 = 0x000A100D, 990 HV_REGISTER_NESTED_SINT14 = 0x000A100E, 991 HV_REGISTER_NESTED_SINT15 = 0x000A100F, 992 HV_REGISTER_NESTED_SCONTROL = 0x000A1010, 993 HV_REGISTER_NESTED_SVERSION = 0x000A1011, 994 HV_REGISTER_NESTED_SIFP = 0x000A1012, 995 HV_REGISTER_NESTED_SIPP = 0x000A1013, 996 HV_REGISTER_NESTED_EOM = 0x000A1014, 997 HV_REGISTER_NESTED_SIRBP = 0x000a1015, 998 999 /* Hypervisor-defined Registers (Synthetic Timers) */ 1000 HV_REGISTER_STIMER0_CONFIG = 0x000B0000, 1001 HV_REGISTER_STIMER0_COUNT = 0x000B0001, 1002 1003 /* VSM */ 1004 HV_REGISTER_VSM_VP_STATUS = 0x000D0003, 1005 }; 1006 1007 /* 1008 * Arch compatibility regs for use with hv_set/get_register 1009 */ 1010 #if defined(CONFIG_X86) 1011 1012 /* 1013 * To support arch-generic code calling hv_set/get_register: 1014 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq 1015 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 1016 */ 1017 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0) 1018 #define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1) 1019 #define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2) 1020 #define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3) 1021 #define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4) 1022 #define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL) 1023 1024 #define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX) 1025 #define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) 1026 #define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) 1027 1028 #define HV_MSR_SINT0 (HV_X64_MSR_SINT0) 1029 #define HV_MSR_SVERSION (HV_X64_MSR_SVERSION) 1030 #define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL) 1031 #define HV_MSR_SIEFP (HV_X64_MSR_SIEFP) 1032 #define HV_MSR_SIMP (HV_X64_MSR_SIMP) 1033 #define HV_MSR_EOM (HV_X64_MSR_EOM) 1034 #define HV_MSR_SIRBP (HV_X64_MSR_SIRBP) 1035 1036 #define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL) 1037 #define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION) 1038 #define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP) 1039 #define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP) 1040 #define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM) 1041 #define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0) 1042 1043 #define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) 1044 #define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) 1045 1046 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1047 1048 #define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0) 1049 #define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1) 1050 #define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2) 1051 #define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3) 1052 #define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4) 1053 #define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL) 1054 1055 #define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX) 1056 #define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) 1057 #define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) 1058 1059 #define HV_MSR_SINT0 (HV_REGISTER_SINT0) 1060 #define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL) 1061 #define HV_MSR_SIEFP (HV_REGISTER_SIEFP) 1062 #define HV_MSR_SIMP (HV_REGISTER_SIMP) 1063 #define HV_MSR_EOM (HV_REGISTER_EOM) 1064 #define HV_MSR_SIRBP (HV_REGISTER_SIRBP) 1065 1066 #define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) 1067 #define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) 1068 1069 #endif /* CONFIG_ARM64 */ 1070 1071 union hv_explicit_suspend_register { 1072 u64 as_uint64; 1073 struct { 1074 u64 suspended : 1; 1075 u64 reserved : 63; 1076 } __packed; 1077 }; 1078 1079 union hv_intercept_suspend_register { 1080 u64 as_uint64; 1081 struct { 1082 u64 suspended : 1; 1083 u64 reserved : 63; 1084 } __packed; 1085 }; 1086 1087 union hv_dispatch_suspend_register { 1088 u64 as_uint64; 1089 struct { 1090 u64 suspended : 1; 1091 u64 reserved : 63; 1092 } __packed; 1093 }; 1094 1095 union hv_arm64_pending_interruption_register { 1096 u64 as_uint64; 1097 struct { 1098 u64 interruption_pending : 1; 1099 u64 interruption_type: 1; 1100 u64 reserved : 30; 1101 u64 error_code : 32; 1102 } __packed; 1103 }; 1104 1105 union hv_arm64_interrupt_state_register { 1106 u64 as_uint64; 1107 struct { 1108 u64 interrupt_shadow : 1; 1109 u64 reserved : 63; 1110 } __packed; 1111 }; 1112 1113 union hv_arm64_pending_synthetic_exception_event { 1114 u64 as_uint64[2]; 1115 struct { 1116 u8 event_pending : 1; 1117 u8 event_type : 3; 1118 u8 reserved : 4; 1119 u8 rsvd[3]; 1120 u32 exception_type; 1121 u64 context; 1122 } __packed; 1123 }; 1124 1125 union hv_x64_interrupt_state_register { 1126 u64 as_uint64; 1127 struct { 1128 u64 interrupt_shadow : 1; 1129 u64 nmi_masked : 1; 1130 u64 reserved : 62; 1131 } __packed; 1132 }; 1133 1134 union hv_x64_pending_interruption_register { 1135 u64 as_uint64; 1136 struct { 1137 u32 interruption_pending : 1; 1138 u32 interruption_type : 3; 1139 u32 deliver_error_code : 1; 1140 u32 instruction_length : 4; 1141 u32 nested_event : 1; 1142 u32 reserved : 6; 1143 u32 interruption_vector : 16; 1144 u32 error_code; 1145 } __packed; 1146 }; 1147 1148 union hv_register_value { 1149 struct hv_u128 reg128; 1150 u64 reg64; 1151 u32 reg32; 1152 u16 reg16; 1153 u8 reg8; 1154 1155 struct hv_x64_segment_register segment; 1156 struct hv_x64_table_register table; 1157 union hv_explicit_suspend_register explicit_suspend; 1158 union hv_intercept_suspend_register intercept_suspend; 1159 union hv_dispatch_suspend_register dispatch_suspend; 1160 #ifdef CONFIG_ARM64 1161 union hv_arm64_interrupt_state_register interrupt_state; 1162 union hv_arm64_pending_interruption_register pending_interruption; 1163 #endif 1164 #ifdef CONFIG_X86 1165 union hv_x64_interrupt_state_register interrupt_state; 1166 union hv_x64_pending_interruption_register pending_interruption; 1167 #endif 1168 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event; 1169 }; 1170 1171 /* NOTE: Linux helper struct - NOT from Hyper-V code. */ 1172 struct hv_output_get_vp_registers { 1173 DECLARE_FLEX_ARRAY(union hv_register_value, values); 1174 }; 1175 1176 #if defined(CONFIG_ARM64) 1177 /* HvGetVpRegisters returns an array of these output elements */ 1178 struct hv_get_vp_registers_output { 1179 union { 1180 struct { 1181 u32 a; 1182 u32 b; 1183 u32 c; 1184 u32 d; 1185 } as32 __packed; 1186 struct { 1187 u64 low; 1188 u64 high; 1189 } as64 __packed; 1190 }; 1191 }; 1192 1193 #endif /* CONFIG_ARM64 */ 1194 1195 struct hv_register_assoc { 1196 u32 name; /* enum hv_register_name */ 1197 u32 reserved1; 1198 u64 reserved2; 1199 union hv_register_value value; 1200 } __packed; 1201 1202 struct hv_input_get_vp_registers { 1203 u64 partition_id; 1204 u32 vp_index; 1205 union hv_input_vtl input_vtl; 1206 u8 rsvd_z8; 1207 u16 rsvd_z16; 1208 u32 names[]; 1209 } __packed; 1210 1211 struct hv_input_set_vp_registers { 1212 u64 partition_id; 1213 u32 vp_index; 1214 union hv_input_vtl input_vtl; 1215 u8 rsvd_z8; 1216 u16 rsvd_z16; 1217 struct hv_register_assoc elements[]; 1218 } __packed; 1219 1220 #define HV_UNMAP_GPA_LARGE_PAGE 0x2 1221 1222 /* HvCallSendSyntheticClusterIpi hypercall */ 1223 struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */ 1224 u32 vector; 1225 u32 reserved; 1226 u64 cpu_mask; 1227 } __packed; 1228 1229 #define HV_VTL_MASK GENMASK(3, 0) 1230 1231 /* Hyper-V memory host visibility */ 1232 enum hv_mem_host_visibility { 1233 VMBUS_PAGE_NOT_VISIBLE = 0, 1234 VMBUS_PAGE_VISIBLE_READ_ONLY = 1, 1235 VMBUS_PAGE_VISIBLE_READ_WRITE = 3 1236 }; 1237 1238 /* HvCallModifySparseGpaPageHostVisibility hypercall */ 1239 #define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2) 1240 struct hv_gpa_range_for_visibility { 1241 u64 partition_id; 1242 u32 host_visibility : 2; 1243 u32 reserved0 : 30; 1244 u32 reserved1; 1245 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT]; 1246 } __packed; 1247 1248 #if defined(CONFIG_X86) 1249 union hv_msi_address_register { /* HV_MSI_ADDRESS */ 1250 u32 as_uint32; 1251 struct { 1252 u32 reserved1 : 2; 1253 u32 destination_mode : 1; 1254 u32 redirection_hint : 1; 1255 u32 reserved2 : 8; 1256 u32 destination_id : 8; 1257 u32 msi_base : 12; 1258 }; 1259 } __packed; 1260 1261 union hv_msi_data_register { /* HV_MSI_ENTRY.Data */ 1262 u32 as_uint32; 1263 struct { 1264 u32 vector : 8; 1265 u32 delivery_mode : 3; 1266 u32 reserved1 : 3; 1267 u32 level_assert : 1; 1268 u32 trigger_mode : 1; 1269 u32 reserved2 : 16; 1270 }; 1271 } __packed; 1272 1273 union hv_msi_entry { /* HV_MSI_ENTRY */ 1274 1275 u64 as_uint64; 1276 struct { 1277 union hv_msi_address_register address; 1278 union hv_msi_data_register data; 1279 } __packed; 1280 }; 1281 1282 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ 1283 1284 union hv_msi_entry { 1285 u64 as_uint64[2]; 1286 struct { 1287 u64 address; 1288 u32 data; 1289 u32 reserved; 1290 } __packed; 1291 }; 1292 #endif /* CONFIG_ARM64 */ 1293 1294 union hv_ioapic_rte { 1295 u64 as_uint64; 1296 1297 struct { 1298 u32 vector : 8; 1299 u32 delivery_mode : 3; 1300 u32 destination_mode : 1; 1301 u32 delivery_status : 1; 1302 u32 interrupt_polarity : 1; 1303 u32 remote_irr : 1; 1304 u32 trigger_mode : 1; 1305 u32 interrupt_mask : 1; 1306 u32 reserved1 : 15; 1307 1308 u32 reserved2 : 24; 1309 u32 destination_id : 8; 1310 }; 1311 1312 struct { 1313 u32 low_uint32; 1314 u32 high_uint32; 1315 }; 1316 } __packed; 1317 1318 enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */ 1319 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */ 1320 HV_INTERRUPT_SOURCE_IOAPIC, 1321 }; 1322 1323 struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */ 1324 u32 source; 1325 u32 reserved1; 1326 union { 1327 union hv_msi_entry msi_entry; 1328 union hv_ioapic_rte ioapic_rte; 1329 }; 1330 } __packed; 1331 1332 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1 1333 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2 1334 1335 struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */ 1336 u32 vector; 1337 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */ 1338 union { 1339 u64 vp_mask; 1340 struct hv_vpset vp_set; 1341 }; 1342 } __packed; 1343 1344 struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */ 1345 u64 partition_id; /* use "self" */ 1346 u64 device_id; 1347 struct hv_interrupt_entry int_entry; 1348 u64 reserved2; 1349 struct hv_device_interrupt_target int_target; 1350 } __packed __aligned(8); 1351 1352 enum hv_intercept_type { 1353 #if defined(CONFIG_X86) 1354 HV_INTERCEPT_TYPE_X64_IO_PORT = 0x00000000, 1355 HV_INTERCEPT_TYPE_X64_MSR = 0x00000001, 1356 HV_INTERCEPT_TYPE_X64_CPUID = 0x00000002, 1357 #endif 1358 HV_INTERCEPT_TYPE_EXCEPTION = 0x00000003, 1359 /* Used to be HV_INTERCEPT_TYPE_REGISTER */ 1360 HV_INTERCEPT_TYPE_RESERVED0 = 0x00000004, 1361 HV_INTERCEPT_TYPE_MMIO = 0x00000005, 1362 #if defined(CONFIG_X86) 1363 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0x00000006, 1364 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0x00000007, 1365 #endif 1366 HV_INTERCEPT_TYPE_HYPERCALL = 0x00000008, 1367 #if defined(CONFIG_X86) 1368 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0x00000009, 1369 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0x0000000A, 1370 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0x0000000B, 1371 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0x0000000C, 1372 #endif 1373 HV_INTERCEPT_TYPE_MAX, 1374 HV_INTERCEPT_TYPE_INVALID = 0xFFFFFFFF, 1375 }; 1376 1377 union hv_intercept_parameters { 1378 /* HV_INTERCEPT_PARAMETERS is defined to be an 8-byte field. */ 1379 u64 as_uint64; 1380 #if defined(CONFIG_X86) 1381 /* HV_INTERCEPT_TYPE_X64_IO_PORT */ 1382 u16 io_port; 1383 /* HV_INTERCEPT_TYPE_X64_CPUID */ 1384 u32 cpuid_index; 1385 /* HV_INTERCEPT_TYPE_X64_APIC_WRITE */ 1386 u32 apic_write_mask; 1387 /* HV_INTERCEPT_TYPE_EXCEPTION */ 1388 u16 exception_vector; 1389 /* HV_INTERCEPT_TYPE_X64_MSR_INDEX */ 1390 u32 msr_index; 1391 #endif 1392 /* N.B. Other intercept types do not have any parameters. */ 1393 }; 1394 1395 /* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */ 1396 #define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64 1397 1398 struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */ 1399 u64 gpa; 1400 u32 size; 1401 u32 reserved; 1402 } __packed; 1403 1404 struct hv_mmio_read_output { 1405 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1406 } __packed; 1407 1408 struct hv_mmio_write_input { 1409 u64 gpa; 1410 u32 size; 1411 u32 reserved; 1412 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH]; 1413 } __packed; 1414 1415 #endif /* _HV_HVGDK_MINI_H */ 1416