1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/iopoll.h>
29 #include <linux/seq_buf.h>
30 #include <linux/string_helpers.h>
31
32 #include <drm/display/drm_dp_helper.h>
33 #include <drm/display/drm_scdc_helper.h>
34 #include <drm/drm_print.h>
35 #include <drm/drm_privacy_screen_consumer.h>
36 #include <drm/intel/step.h>
37
38 #include "icl_dsi.h"
39 #include "intel_alpm.h"
40 #include "intel_audio.h"
41 #include "intel_audio_regs.h"
42 #include "intel_backlight.h"
43 #include "intel_combo_phy.h"
44 #include "intel_combo_phy_regs.h"
45 #include "intel_connector.h"
46 #include "intel_crtc.h"
47 #include "intel_cx0_phy.h"
48 #include "intel_cx0_phy_regs.h"
49 #include "intel_ddi.h"
50 #include "intel_ddi_buf_trans.h"
51 #include "intel_de.h"
52 #include "intel_display_power.h"
53 #include "intel_display_regs.h"
54 #include "intel_display_types.h"
55 #include "intel_display_utils.h"
56 #include "intel_display_wa.h"
57 #include "intel_dkl_phy.h"
58 #include "intel_dkl_phy_regs.h"
59 #include "intel_dp.h"
60 #include "intel_dp_aux.h"
61 #include "intel_dp_link_training.h"
62 #include "intel_dp_mst.h"
63 #include "intel_dp_test.h"
64 #include "intel_dp_tunnel.h"
65 #include "intel_dpio_phy.h"
66 #include "intel_dsi.h"
67 #include "intel_encoder.h"
68 #include "intel_fdi.h"
69 #include "intel_fifo_underrun.h"
70 #include "intel_gmbus.h"
71 #include "intel_hdcp.h"
72 #include "intel_hdmi.h"
73 #include "intel_hotplug.h"
74 #include "intel_hti.h"
75 #include "intel_lspcon.h"
76 #include "intel_lt_phy.h"
77 #include "intel_mg_phy_regs.h"
78 #include "intel_modeset_lock.h"
79 #include "intel_panel.h"
80 #include "intel_pfit.h"
81 #include "intel_pps.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_snps_phy.h"
85 #include "intel_tc.h"
86 #include "intel_vdsc.h"
87 #include "intel_vdsc_regs.h"
88 #include "intel_vrr.h"
89 #include "skl_scaler.h"
90 #include "skl_universal_plane.h"
91
92 struct intel_dpll;
93
94 static const u8 index_to_dp_signal_levels[] = {
95 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
96 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
97 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
98 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
99 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
100 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
101 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
102 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
103 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
104 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
105 };
106
intel_ddi_hdmi_level(struct intel_encoder * encoder,const struct intel_ddi_buf_trans * trans)107 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
108 const struct intel_ddi_buf_trans *trans)
109 {
110 int level;
111
112 level = intel_bios_hdmi_level_shift(encoder->devdata);
113 if (level < 0)
114 level = trans->hdmi_default_entry;
115
116 return level;
117 }
118
has_buf_trans_select(struct intel_display * display)119 static bool has_buf_trans_select(struct intel_display *display)
120 {
121 return DISPLAY_VER(display) < 10 && !display->platform.broxton;
122 }
123
has_iboost(struct intel_display * display)124 static bool has_iboost(struct intel_display *display)
125 {
126 return DISPLAY_VER(display) == 9 && !display->platform.broxton;
127 }
128
129 /*
130 * Starting with Haswell, DDI port buffers must be programmed with correct
131 * values in advance. This function programs the correct values for
132 * DP/eDP/FDI use cases.
133 */
hsw_prepare_dp_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)134 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
135 const struct intel_crtc_state *crtc_state)
136 {
137 struct intel_display *display = to_intel_display(encoder);
138 u32 iboost_bit = 0;
139 int i, n_entries;
140 enum port port = encoder->port;
141 const struct intel_ddi_buf_trans *trans;
142
143 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
144 if (drm_WARN_ON_ONCE(display->drm, !trans))
145 return;
146
147 /* If we're boosting the current, set bit 31 of trans1 */
148 if (has_iboost(display) &&
149 intel_bios_dp_boost_level(encoder->devdata))
150 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
151
152 for (i = 0; i < n_entries; i++) {
153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i),
154 trans->entries[i].hsw.trans1 | iboost_bit);
155 intel_de_write(display, DDI_BUF_TRANS_HI(port, i),
156 trans->entries[i].hsw.trans2);
157 }
158 }
159
160 /*
161 * Starting with Haswell, DDI port buffers must be programmed with correct
162 * values in advance. This function programs the correct values for
163 * HDMI/DVI use cases.
164 */
hsw_prepare_hdmi_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)165 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
166 const struct intel_crtc_state *crtc_state)
167 {
168 struct intel_display *display = to_intel_display(encoder);
169 int level = intel_ddi_level(encoder, crtc_state, 0);
170 u32 iboost_bit = 0;
171 int n_entries;
172 enum port port = encoder->port;
173 const struct intel_ddi_buf_trans *trans;
174
175 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
176 if (drm_WARN_ON_ONCE(display->drm, !trans))
177 return;
178
179 /* If we're boosting the current, set bit 31 of trans1 */
180 if (has_iboost(display) &&
181 intel_bios_hdmi_boost_level(encoder->devdata))
182 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
183
184 /* Entry 9 is for HDMI: */
185 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9),
186 trans->entries[level].hsw.trans1 | iboost_bit);
187 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9),
188 trans->entries[level].hsw.trans2);
189 }
190
intel_ddi_buf_status_reg(struct intel_display * display,enum port port)191 static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
192 {
193 if (DISPLAY_VER(display) >= 14)
194 return XELPDP_PORT_BUF_CTL1(display, port);
195 else
196 return DDI_BUF_CTL(port);
197 }
198
intel_wait_ddi_buf_idle(struct intel_display * display,enum port port)199 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)
200 {
201 /*
202 * Bspec's platform specific timeouts:
203 * MTL+ : 100 us
204 * BXT : fixed 16 us
205 * HSW-ADL: 8 us
206 *
207 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short
208 */
209 if (display->platform.broxton) {
210 udelay(16);
211 return;
212 }
213
214 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
215 if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port),
216 DDI_BUF_IS_IDLE, 10))
217 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",
218 port_name(port));
219 }
220
intel_wait_ddi_buf_active(struct intel_encoder * encoder)221 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
222 {
223 struct intel_display *display = to_intel_display(encoder);
224 enum port port = encoder->port;
225
226 /*
227 * Bspec's platform specific timeouts:
228 * MTL+ : 10000 us
229 * DG2 : 1200 us
230 * TGL-ADL combo PHY: 1000 us
231 * TGL-ADL TypeC PHY: 3000 us
232 * HSW-ICL : fixed 518 us
233 */
234 if (DISPLAY_VER(display) < 10) {
235 usleep_range(518, 1000);
236 return;
237 }
238
239 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
240 if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port),
241 DDI_BUF_IS_IDLE, 10))
242 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",
243 port_name(port));
244 }
245
hsw_pll_to_ddi_pll_sel(const struct intel_dpll * pll)246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
247 {
248 switch (pll->info->id) {
249 case DPLL_ID_WRPLL1:
250 return PORT_CLK_SEL_WRPLL1;
251 case DPLL_ID_WRPLL2:
252 return PORT_CLK_SEL_WRPLL2;
253 case DPLL_ID_SPLL:
254 return PORT_CLK_SEL_SPLL;
255 case DPLL_ID_LCPLL_810:
256 return PORT_CLK_SEL_LCPLL_810;
257 case DPLL_ID_LCPLL_1350:
258 return PORT_CLK_SEL_LCPLL_1350;
259 case DPLL_ID_LCPLL_2700:
260 return PORT_CLK_SEL_LCPLL_2700;
261 default:
262 MISSING_CASE(pll->info->id);
263 return PORT_CLK_SEL_NONE;
264 }
265 }
266
icl_pll_to_ddi_clk_sel(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
268 const struct intel_crtc_state *crtc_state)
269 {
270 const struct intel_dpll *pll = crtc_state->intel_dpll;
271 int clock = crtc_state->port_clock;
272 const enum intel_dpll_id id = pll->info->id;
273
274 switch (id) {
275 default:
276 /*
277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
278 * here, so do warn if this get passed in
279 */
280 MISSING_CASE(id);
281 return DDI_CLK_SEL_NONE;
282 case DPLL_ID_ICL_TBTPLL:
283 switch (clock) {
284 case 162000:
285 return DDI_CLK_SEL_TBT_162;
286 case 270000:
287 return DDI_CLK_SEL_TBT_270;
288 case 540000:
289 return DDI_CLK_SEL_TBT_540;
290 case 810000:
291 return DDI_CLK_SEL_TBT_810;
292 default:
293 MISSING_CASE(clock);
294 return DDI_CLK_SEL_NONE;
295 }
296 case DPLL_ID_ICL_MGPLL1:
297 case DPLL_ID_ICL_MGPLL2:
298 case DPLL_ID_ICL_MGPLL3:
299 case DPLL_ID_ICL_MGPLL4:
300 case DPLL_ID_TGL_MGPLL5:
301 case DPLL_ID_TGL_MGPLL6:
302 return DDI_CLK_SEL_MG;
303 }
304 }
305
ddi_buf_phy_link_rate(int port_clock)306 static u32 ddi_buf_phy_link_rate(int port_clock)
307 {
308 switch (port_clock) {
309 case 162000:
310 return DDI_BUF_PHY_LINK_RATE(0);
311 case 216000:
312 return DDI_BUF_PHY_LINK_RATE(4);
313 case 243000:
314 return DDI_BUF_PHY_LINK_RATE(5);
315 case 270000:
316 return DDI_BUF_PHY_LINK_RATE(1);
317 case 324000:
318 return DDI_BUF_PHY_LINK_RATE(6);
319 case 432000:
320 return DDI_BUF_PHY_LINK_RATE(7);
321 case 540000:
322 return DDI_BUF_PHY_LINK_RATE(2);
323 case 810000:
324 return DDI_BUF_PHY_LINK_RATE(3);
325 default:
326 MISSING_CASE(port_clock);
327 return DDI_BUF_PHY_LINK_RATE(0);
328 }
329 }
330
dp_phy_lane_stagger_delay(int port_clock)331 static int dp_phy_lane_stagger_delay(int port_clock)
332 {
333 /*
334 * Return the number of symbol clocks delay used to stagger the
335 * assertion/desassertion of the port lane enables. The target delay
336 * time is 100 ns or greater, return the number of symbols specific to
337 * the provided port_clock (aka link clock) corresponding to this delay
338 * time, i.e. so that
339 *
340 * number_of_symbols * duration_of_one_symbol >= 100 ns
341 *
342 * The delay must be applied only on TypeC DP outputs, for everything else
343 * the delay must be set to 0.
344 *
345 * Return the number of link symbols per 100 ns:
346 * port_clock (10 kHz) -> bits / 100 us
347 * / symbol_size -> symbols / 100 us
348 * / 1000 -> symbols / 100 ns
349 */
350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);
351 }
352
intel_ddi_init_dp_buf_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)353 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
354 const struct intel_crtc_state *crtc_state)
355 {
356 struct intel_display *display = to_intel_display(encoder);
357 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
358 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
359
360 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |
362 DDI_BUF_TRANS_SELECT(0);
363
364 if (dig_port->lane_reversal)
365 intel_dp->DP |= DDI_BUF_PORT_REVERSAL;
366 if (dig_port->ddi_a_4_lanes)
367 intel_dp->DP |= DDI_A_4_LANES;
368
369 if (DISPLAY_VER(display) >= 14) {
370 if (intel_dp_is_uhbr(crtc_state))
371 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
372 else
373 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
374 }
375
376 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
378 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
379 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
380 }
381
382 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);
384
385 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);
386 }
387 }
388
icl_calc_tbt_pll_link(struct intel_display * display,enum port port)389 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port)
390 {
391 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
392
393 switch (val) {
394 case DDI_CLK_SEL_NONE:
395 return 0;
396 case DDI_CLK_SEL_TBT_162:
397 return 162000;
398 case DDI_CLK_SEL_TBT_270:
399 return 270000;
400 case DDI_CLK_SEL_TBT_540:
401 return 540000;
402 case DDI_CLK_SEL_TBT_810:
403 return 810000;
404 default:
405 MISSING_CASE(val);
406 return 0;
407 }
408 }
409
ddi_dotclock_get(struct intel_crtc_state * pipe_config)410 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
411 {
412 /* CRT dotclock is determined via other means */
413 if (pipe_config->has_pch_encoder)
414 return;
415
416 pipe_config->hw.adjusted_mode.crtc_clock =
417 intel_crtc_dotclock(pipe_config);
418 }
419
intel_ddi_set_dp_msa(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)420 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
421 const struct drm_connector_state *conn_state)
422 {
423 struct intel_display *display = to_intel_display(crtc_state);
424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
425 u32 temp;
426
427 if (!intel_crtc_has_dp_encoder(crtc_state))
428 return;
429
430 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
431
432 temp = DP_MSA_MISC_SYNC_CLOCK;
433
434 switch (crtc_state->pipe_bpp) {
435 case 18:
436 temp |= DP_MSA_MISC_6_BPC;
437 break;
438 case 24:
439 temp |= DP_MSA_MISC_8_BPC;
440 break;
441 case 30:
442 temp |= DP_MSA_MISC_10_BPC;
443 break;
444 case 36:
445 temp |= DP_MSA_MISC_12_BPC;
446 break;
447 default:
448 MISSING_CASE(crtc_state->pipe_bpp);
449 break;
450 }
451
452 /* nonsense combination */
453 drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
454 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
455
456 if (crtc_state->limited_color_range)
457 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
458
459 /*
460 * As per DP 1.2 spec section 2.3.4.3 while sending
461 * YCBCR 444 signals we should program MSA MISC1/0 fields with
462 * colorspace information.
463 */
464 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
465 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
466
467 /*
468 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
469 * of Color Encoding Format and Content Color Gamut] while sending
470 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
471 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
472 */
473 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
474 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
475
476 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder),
477 temp);
478 }
479
bdw_trans_port_sync_master_select(enum transcoder master_transcoder)480 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
481 {
482 if (master_transcoder == TRANSCODER_EDP)
483 return 0;
484 else
485 return master_transcoder + 1;
486 }
487
488 static void
intel_ddi_config_transcoder_dp2(const struct intel_crtc_state * crtc_state,bool enable)489 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state,
490 bool enable)
491 {
492 struct intel_display *display = to_intel_display(crtc_state);
493 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
494 u32 val = 0;
495
496 if (!HAS_DP20(display))
497 return;
498
499 if (enable && intel_dp_is_uhbr(crtc_state))
500 val = TRANS_DP2_128B132B_CHANNEL_CODING;
501
502 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);
503 }
504
505 /*
506 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
507 *
508 * Only intended to be used by intel_ddi_enable_transcoder_func() and
509 * intel_ddi_config_transcoder_func().
510 */
511 static u32
intel_ddi_transcoder_func_reg_val_get(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)512 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
513 const struct intel_crtc_state *crtc_state)
514 {
515 struct intel_display *display = to_intel_display(crtc_state);
516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
517 enum pipe pipe = crtc->pipe;
518 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
519 enum port port = encoder->port;
520 u32 temp;
521
522 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
523 temp = TRANS_DDI_FUNC_ENABLE;
524 if (DISPLAY_VER(display) >= 12)
525 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
526 else
527 temp |= TRANS_DDI_SELECT_PORT(port);
528
529 switch (crtc_state->pipe_bpp) {
530 default:
531 MISSING_CASE(crtc_state->pipe_bpp);
532 fallthrough;
533 case 18:
534 temp |= TRANS_DDI_BPC_6;
535 break;
536 case 24:
537 temp |= TRANS_DDI_BPC_8;
538 break;
539 case 30:
540 temp |= TRANS_DDI_BPC_10;
541 break;
542 case 36:
543 temp |= TRANS_DDI_BPC_12;
544 break;
545 }
546
547 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
548 temp |= TRANS_DDI_PVSYNC;
549 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
550 temp |= TRANS_DDI_PHSYNC;
551
552 if (cpu_transcoder == TRANSCODER_EDP) {
553 switch (pipe) {
554 default:
555 MISSING_CASE(pipe);
556 fallthrough;
557 case PIPE_A:
558 /* On Haswell, can only use the always-on power well for
559 * eDP when not using the panel fitter, and when not
560 * using motion blur mitigation (which we don't
561 * support). */
562 if (crtc_state->pch_pfit.force_thru)
563 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
564 else
565 temp |= TRANS_DDI_EDP_INPUT_A_ON;
566 break;
567 case PIPE_B:
568 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
569 break;
570 case PIPE_C:
571 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
572 break;
573 }
574 }
575
576 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
577 if (crtc_state->has_hdmi_sink)
578 temp |= TRANS_DDI_MODE_SELECT_HDMI;
579 else
580 temp |= TRANS_DDI_MODE_SELECT_DVI;
581
582 if (crtc_state->hdmi_scrambling)
583 temp |= TRANS_DDI_HDMI_SCRAMBLING;
584 if (crtc_state->hdmi_high_tmds_clock_ratio)
585 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
586 if (DISPLAY_VER(display) >= 14)
587 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
588 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
590 temp |= (crtc_state->fdi_lanes - 1) << 1;
591 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
592 intel_dp_is_uhbr(crtc_state)) {
593 if (intel_dp_is_uhbr(crtc_state))
594 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
595 else
596 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
597 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
598
599 if (DISPLAY_VER(display) >= 12) {
600 enum transcoder master;
601
602 master = crtc_state->mst_master_transcoder;
603 if (drm_WARN_ON(display->drm,
604 master == INVALID_TRANSCODER))
605 master = TRANSCODER_A;
606 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
607 }
608 } else {
609 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
610 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
611 }
612
613 if (IS_DISPLAY_VER(display, 8, 10) &&
614 crtc_state->master_transcoder != INVALID_TRANSCODER) {
615 u8 master_select =
616 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
617
618 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
619 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
620 }
621
622 return temp;
623 }
624
intel_ddi_enable_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)625 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
626 const struct intel_crtc_state *crtc_state)
627 {
628 struct intel_display *display = to_intel_display(crtc_state);
629 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
630
631 if (DISPLAY_VER(display) >= 11) {
632 enum transcoder master_transcoder = crtc_state->master_transcoder;
633 u32 ctl2 = 0;
634
635 if (master_transcoder != INVALID_TRANSCODER) {
636 u8 master_select =
637 bdw_trans_port_sync_master_select(master_transcoder);
638
639 ctl2 |= PORT_SYNC_MODE_ENABLE |
640 PORT_SYNC_MODE_MASTER_SELECT(master_select);
641 }
642
643 intel_de_write(display,
644 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
645 ctl2);
646 }
647
648 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
649 intel_ddi_transcoder_func_reg_val_get(encoder,
650 crtc_state));
651 }
652
653 /*
654 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
655 * bit for the DDI function and enables the DP2 configuration. Called for all
656 * transcoder types.
657 */
658 void
intel_ddi_config_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)659 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
660 const struct intel_crtc_state *crtc_state)
661 {
662 struct intel_display *display = to_intel_display(crtc_state);
663 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
664 u32 ctl;
665
666 intel_ddi_config_transcoder_dp2(crtc_state, true);
667
668 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
669 ctl &= ~TRANS_DDI_FUNC_ENABLE;
670 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
671 ctl);
672 }
673
674 /*
675 * Disable the DDI function and port syncing.
676 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port,
677 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master
678 * transcoders these are done later in intel_ddi_post_disable_dp().
679 */
intel_ddi_disable_transcoder_func(const struct intel_crtc_state * crtc_state)680 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
681 {
682 struct intel_display *display = to_intel_display(crtc_state);
683 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
684 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
685 u32 ctl;
686
687 if (DISPLAY_VER(display) >= 11)
688 intel_de_write(display,
689 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
690 0);
691
692 ctl = intel_de_read(display,
693 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
694
695 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
696
697 ctl &= ~TRANS_DDI_FUNC_ENABLE;
698
699 if (IS_DISPLAY_VER(display, 8, 10))
700 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
701 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
702
703 if (DISPLAY_VER(display) >= 12) {
704 if (!intel_dp_mst_is_master_trans(crtc_state)) {
705 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
706 TRANS_DDI_MODE_SELECT_MASK);
707 }
708 } else {
709 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
710 }
711
712 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
713 ctl);
714
715 if (intel_dp_mst_is_slave_trans(crtc_state))
716 intel_ddi_config_transcoder_dp2(crtc_state, false);
717
718 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
719 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
720 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");
721 /* Quirk time at 100ms for reliable operation */
722 msleep(100);
723 }
724 }
725
intel_ddi_toggle_hdcp_bits(struct intel_encoder * intel_encoder,enum transcoder cpu_transcoder,bool enable,u32 hdcp_mask)726 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
727 enum transcoder cpu_transcoder,
728 bool enable, u32 hdcp_mask)
729 {
730 struct intel_display *display = to_intel_display(intel_encoder);
731 struct ref_tracker *wakeref;
732 int ret = 0;
733
734 wakeref = intel_display_power_get_if_enabled(display,
735 intel_encoder->power_domain);
736 if (drm_WARN_ON(display->drm, !wakeref))
737 return -ENXIO;
738
739 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
740 hdcp_mask, enable ? hdcp_mask : 0);
741 intel_display_power_put(display, intel_encoder->power_domain, wakeref);
742 return ret;
743 }
744
intel_ddi_connector_get_hw_state(struct intel_connector * intel_connector)745 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
746 {
747 struct intel_display *display = to_intel_display(intel_connector);
748 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
749 int type = intel_connector->base.connector_type;
750 enum port port = encoder->port;
751 enum transcoder cpu_transcoder;
752 struct ref_tracker *wakeref;
753 enum pipe pipe = 0;
754 u32 ddi_mode;
755 bool ret;
756
757 wakeref = intel_display_power_get_if_enabled(display,
758 encoder->power_domain);
759 if (!wakeref)
760 return false;
761
762 /* Note: This returns false for DP MST primary encoders. */
763 if (!encoder->get_hw_state(encoder, &pipe)) {
764 ret = false;
765 goto out;
766 }
767
768 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
769 cpu_transcoder = TRANSCODER_EDP;
770 else
771 cpu_transcoder = (enum transcoder) pipe;
772
773 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
774 TRANS_DDI_MODE_SELECT_MASK;
775
776 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI ||
777 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
778 ret = type == DRM_MODE_CONNECTOR_HDMIA;
779 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
780 ret = type == DRM_MODE_CONNECTOR_VGA;
781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
782 ret = type == DRM_MODE_CONNECTOR_eDP ||
783 type == DRM_MODE_CONNECTOR_DisplayPort;
784 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
785 /*
786 * encoder->get_hw_state() should have bailed out on MST. This
787 * must be SST and non-eDP.
788 */
789 ret = type == DRM_MODE_CONNECTOR_DisplayPort;
790 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {
791 /* encoder->get_hw_state() should have bailed out on MST. */
792 ret = false;
793 } else {
794 ret = false;
795 }
796
797 out:
798 intel_display_power_put(display, encoder->power_domain, wakeref);
799
800 return ret;
801 }
802
intel_ddi_get_encoder_pipes(struct intel_encoder * encoder,u8 * pipe_mask,bool * is_dp_mst)803 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
804 u8 *pipe_mask, bool *is_dp_mst)
805 {
806 struct intel_display *display = to_intel_display(encoder);
807 enum port port = encoder->port;
808 struct ref_tracker *wakeref;
809 enum pipe p;
810 u32 tmp;
811 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
812
813 *pipe_mask = 0;
814 *is_dp_mst = false;
815
816 wakeref = intel_display_power_get_if_enabled(display,
817 encoder->power_domain);
818 if (!wakeref)
819 return;
820
821 tmp = intel_de_read(display, DDI_BUF_CTL(port));
822 if (!(tmp & DDI_BUF_CTL_ENABLE))
823 goto out;
824
825 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {
826 tmp = intel_de_read(display,
827 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP));
828
829 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
830 default:
831 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
832 fallthrough;
833 case TRANS_DDI_EDP_INPUT_A_ON:
834 case TRANS_DDI_EDP_INPUT_A_ONOFF:
835 *pipe_mask = BIT(PIPE_A);
836 break;
837 case TRANS_DDI_EDP_INPUT_B_ONOFF:
838 *pipe_mask = BIT(PIPE_B);
839 break;
840 case TRANS_DDI_EDP_INPUT_C_ONOFF:
841 *pipe_mask = BIT(PIPE_C);
842 break;
843 }
844
845 goto out;
846 }
847
848 for_each_pipe(display, p) {
849 enum transcoder cpu_transcoder = (enum transcoder)p;
850 u32 port_mask, ddi_select, ddi_mode;
851 struct ref_tracker *trans_wakeref;
852
853 trans_wakeref = intel_display_power_get_if_enabled(display,
854 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
855 if (!trans_wakeref)
856 continue;
857
858 if (DISPLAY_VER(display) >= 12) {
859 port_mask = TGL_TRANS_DDI_PORT_MASK;
860 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
861 } else {
862 port_mask = TRANS_DDI_PORT_MASK;
863 ddi_select = TRANS_DDI_SELECT_PORT(port);
864 }
865
866 tmp = intel_de_read(display,
867 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
868 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
869 trans_wakeref);
870
871 if ((tmp & port_mask) != ddi_select)
872 continue;
873
874 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
875
876 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
877 mst_pipe_mask |= BIT(p);
878 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
879 dp128b132b_pipe_mask |= BIT(p);
880
881 *pipe_mask |= BIT(p);
882 }
883
884 if (!*pipe_mask)
885 drm_dbg_kms(display->drm,
886 "No pipe for [ENCODER:%d:%s] found\n",
887 encoder->base.base.id, encoder->base.name);
888
889 if (!mst_pipe_mask && dp128b132b_pipe_mask) {
890 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
891
892 /*
893 * If we don't have 8b/10b MST, but have more than one
894 * transcoder in 128b/132b mode, we know it must be 128b/132b
895 * MST.
896 *
897 * Otherwise, we fall back to checking the current MST
898 * state. It's not accurate for hardware takeover at probe, but
899 * we don't expect MST to have been enabled at that point, and
900 * can assume it's SST.
901 */
902 if (hweight8(dp128b132b_pipe_mask) > 1 ||
903 intel_dp_mst_active_streams(intel_dp))
904 mst_pipe_mask = dp128b132b_pipe_mask;
905 }
906
907 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
908 drm_dbg_kms(display->drm,
909 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
910 encoder->base.base.id, encoder->base.name,
911 *pipe_mask);
912 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
913 }
914
915 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
916 drm_dbg_kms(display->drm,
917 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
918 encoder->base.base.id, encoder->base.name,
919 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
920 else
921 *is_dp_mst = mst_pipe_mask;
922
923 out:
924 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) {
925 tmp = intel_de_read(display, BXT_PHY_CTL(port));
926 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
927 BXT_PHY_LANE_POWERDOWN_ACK |
928 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
929 drm_err(display->drm,
930 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
931 encoder->base.base.id, encoder->base.name, tmp);
932 }
933
934 intel_display_power_put(display, encoder->power_domain, wakeref);
935 }
936
intel_ddi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)937 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
938 enum pipe *pipe)
939 {
940 u8 pipe_mask;
941 bool is_mst;
942
943 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
944
945 if (is_mst || !pipe_mask)
946 return false;
947
948 *pipe = ffs(pipe_mask) - 1;
949
950 return true;
951 }
952
953 static enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)954 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
955 const struct intel_crtc_state *crtc_state)
956 {
957 struct intel_display *display = to_intel_display(dig_port);
958
959 /*
960 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
961 * DC states enabled at the same time, while for driver initiated AUX
962 * transfers we need the same AUX IOs to be powered but with DC states
963 * disabled. Accordingly use the AUX_IO_<port> power domain here which
964 * leaves DC states enabled.
965 *
966 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
967 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
968 * well, so we can acquire a wider AUX_<port> power domain reference
969 * instead of a specific AUX_IO_<port> reference without powering up any
970 * extra wells.
971 */
972 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state))
973 return intel_display_power_aux_io_domain(display, dig_port->aux_ch);
974 else if (DISPLAY_VER(display) < 14 &&
975 (intel_crtc_has_dp_encoder(crtc_state) ||
976 intel_encoder_is_tc(&dig_port->base)))
977 return intel_aux_power_domain(dig_port);
978 else
979 return POWER_DOMAIN_INVALID;
980 }
981
982 static void
main_link_aux_power_domain_get(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)983 main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
984 const struct intel_crtc_state *crtc_state)
985 {
986 struct intel_display *display = to_intel_display(dig_port);
987 enum intel_display_power_domain domain =
988 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
989
990 drm_WARN_ON(display->drm, dig_port->aux_wakeref);
991
992 if (domain == POWER_DOMAIN_INVALID)
993 return;
994
995 dig_port->aux_wakeref = intel_display_power_get(display, domain);
996 }
997
998 static void
main_link_aux_power_domain_put(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)999 main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
1000 const struct intel_crtc_state *crtc_state)
1001 {
1002 struct intel_display *display = to_intel_display(dig_port);
1003 enum intel_display_power_domain domain =
1004 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
1005 struct ref_tracker *wf;
1006
1007 wf = fetch_and_zero(&dig_port->aux_wakeref);
1008 if (!wf)
1009 return;
1010
1011 intel_display_power_put(display, domain, wf);
1012 }
1013
intel_ddi_get_power_domains(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1014 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
1015 struct intel_crtc_state *crtc_state)
1016 {
1017 struct intel_display *display = to_intel_display(encoder);
1018 struct intel_digital_port *dig_port;
1019
1020 /*
1021 * TODO: Add support for MST encoders. Atm, the following should never
1022 * happen since fake-MST encoders don't set their get_power_domains()
1023 * hook.
1024 */
1025 if (drm_WARN_ON(display->drm,
1026 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
1027 return;
1028
1029 dig_port = enc_to_dig_port(encoder);
1030
1031 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
1032 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
1033 dig_port->ddi_io_wakeref = intel_display_power_get(display,
1034 dig_port->ddi_io_power_domain);
1035 }
1036
1037 main_link_aux_power_domain_get(dig_port, crtc_state);
1038 }
1039
intel_ddi_enable_transcoder_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1040 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
1041 const struct intel_crtc_state *crtc_state)
1042 {
1043 struct intel_display *display = to_intel_display(crtc_state);
1044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1045 enum phy phy = intel_encoder_to_phy(encoder);
1046 u32 val;
1047
1048 if (cpu_transcoder == TRANSCODER_EDP)
1049 return;
1050
1051 if (DISPLAY_VER(display) >= 13)
1052 val = TGL_TRANS_CLK_SEL_PORT(phy);
1053 else if (DISPLAY_VER(display) >= 12)
1054 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
1055 else
1056 val = TRANS_CLK_SEL_PORT(encoder->port);
1057
1058 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
1059 }
1060
intel_ddi_disable_transcoder_clock(const struct intel_crtc_state * crtc_state)1061 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
1062 {
1063 struct intel_display *display = to_intel_display(crtc_state);
1064 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1065 u32 val;
1066
1067 if (cpu_transcoder == TRANSCODER_EDP)
1068 return;
1069
1070 if (DISPLAY_VER(display) >= 12)
1071 val = TGL_TRANS_CLK_SEL_DISABLED;
1072 else
1073 val = TRANS_CLK_SEL_DISABLED;
1074
1075 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
1076 }
1077
_skl_ddi_set_iboost(struct intel_display * display,enum port port,u8 iboost)1078 static void _skl_ddi_set_iboost(struct intel_display *display,
1079 enum port port, u8 iboost)
1080 {
1081 u32 tmp;
1082
1083 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);
1084 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1085 if (iboost)
1086 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1087 else
1088 tmp |= BALANCE_LEG_DISABLE(port);
1089 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp);
1090 }
1091
skl_ddi_set_iboost(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int level)1092 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1093 const struct intel_crtc_state *crtc_state,
1094 int level)
1095 {
1096 struct intel_display *display = to_intel_display(encoder);
1097 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1098 u8 iboost;
1099
1100 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1101 iboost = intel_bios_hdmi_boost_level(encoder->devdata);
1102 else
1103 iboost = intel_bios_dp_boost_level(encoder->devdata);
1104
1105 if (iboost == 0) {
1106 const struct intel_ddi_buf_trans *trans;
1107 int n_entries;
1108
1109 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
1110 if (drm_WARN_ON_ONCE(display->drm, !trans))
1111 return;
1112
1113 iboost = trans->entries[level].hsw.i_boost;
1114 }
1115
1116 /* Make sure that the requested I_boost is valid */
1117 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1118 drm_err(display->drm, "Invalid I_boost value %u\n", iboost);
1119 return;
1120 }
1121
1122 _skl_ddi_set_iboost(display, encoder->port, iboost);
1123
1124 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1125 _skl_ddi_set_iboost(display, PORT_E, iboost);
1126 }
1127
intel_ddi_dp_voltage_max(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1128 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1129 const struct intel_crtc_state *crtc_state)
1130 {
1131 struct intel_display *display = to_intel_display(intel_dp);
1132 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1133 int n_entries;
1134
1135 intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
1136
1137 if (drm_WARN_ON(display->drm, n_entries < 1))
1138 n_entries = 1;
1139 if (drm_WARN_ON(display->drm,
1140 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1141 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1142
1143 return index_to_dp_signal_levels[n_entries - 1] &
1144 DP_TRAIN_VOLTAGE_SWING_MASK;
1145 }
1146
1147 /*
1148 * We assume that the full set of pre-emphasis values can be
1149 * used on all DDI platforms. Should that change we need to
1150 * rethink this code.
1151 */
intel_ddi_dp_preemph_max(struct intel_dp * intel_dp)1152 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1153 {
1154 return DP_TRAIN_PRE_EMPH_LEVEL_3;
1155 }
1156
icl_combo_phy_loadgen_select(const struct intel_crtc_state * crtc_state,int lane)1157 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1158 int lane)
1159 {
1160 if (crtc_state->port_clock > 600000)
1161 return 0;
1162
1163 if (crtc_state->lane_count == 4)
1164 return lane >= 1 ? LOADGEN_SELECT : 0;
1165 else
1166 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1167 }
1168
icl_ddi_combo_vswing_program(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1169 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1170 const struct intel_crtc_state *crtc_state)
1171 {
1172 struct intel_display *display = to_intel_display(encoder);
1173 const struct intel_ddi_buf_trans *trans;
1174 enum phy phy = intel_encoder_to_phy(encoder);
1175 int n_entries, ln;
1176 u32 val;
1177
1178 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
1179 if (drm_WARN_ON_ONCE(display->drm, !trans))
1180 return;
1181
1182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1183 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1184
1185 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1186 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1187 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val,
1188 intel_dp->hobl_active ? val : 0);
1189 }
1190
1191 /* Set PORT_TX_DW5 */
1192 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1193 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1194 COEFF_POLARITY | CURSOR_PROGRAM |
1195 TAP2_DISABLE | TAP3_DISABLE);
1196 val |= SCALING_MODE_SEL(0x2);
1197 val |= RTERM_SELECT(0x6);
1198 val |= TAP3_DISABLE;
1199 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1200
1201 /* Program PORT_TX_DW2 */
1202 for (ln = 0; ln < 4; ln++) {
1203 int level = intel_ddi_level(encoder, crtc_state, ln);
1204
1205 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),
1206 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1207 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1208 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1209 RCOMP_SCALAR(0x98));
1210 }
1211
1212 /* Program PORT_TX_DW4 */
1213 /* We cannot write to GRP. It would overwrite individual loadgen. */
1214 for (ln = 0; ln < 4; ln++) {
1215 int level = intel_ddi_level(encoder, crtc_state, ln);
1216
1217 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
1218 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1219 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1220 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1221 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1222 }
1223
1224 /* Program PORT_TX_DW7 */
1225 for (ln = 0; ln < 4; ln++) {
1226 int level = intel_ddi_level(encoder, crtc_state, ln);
1227
1228 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),
1229 N_SCALAR_MASK,
1230 N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1231 }
1232 }
1233
icl_combo_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1234 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1235 const struct intel_crtc_state *crtc_state)
1236 {
1237 struct intel_display *display = to_intel_display(encoder);
1238 enum phy phy = intel_encoder_to_phy(encoder);
1239 u32 val;
1240 int ln;
1241
1242 /*
1243 * 1. If port type is eDP or DP,
1244 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1245 * else clear to 0b.
1246 */
1247 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
1248 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1249 val &= ~COMMON_KEEPER_EN;
1250 else
1251 val |= COMMON_KEEPER_EN;
1252 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
1253
1254 /* 2. Program loadgen select */
1255 /*
1256 * Program PORT_TX_DW4 depending on Bit rate and used lanes
1257 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1258 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1259 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1260 */
1261 for (ln = 0; ln < 4; ln++) {
1262 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
1263 LOADGEN_SELECT,
1264 icl_combo_phy_loadgen_select(crtc_state, ln));
1265 }
1266
1267 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1268 intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
1269 0, SUS_CLOCK_CONFIG);
1270
1271 /* 4. Clear training enable to change swing values */
1272 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1273 val &= ~TX_TRAINING_EN;
1274 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1275
1276 /* 5. Program swing and de-emphasis */
1277 icl_ddi_combo_vswing_program(encoder, crtc_state);
1278
1279 /* 6. Set training enable to trigger update */
1280 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1281 val |= TX_TRAINING_EN;
1282 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1283 }
1284
icl_mg_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1285 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1286 const struct intel_crtc_state *crtc_state)
1287 {
1288 struct intel_display *display = to_intel_display(encoder);
1289 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1290 const struct intel_ddi_buf_trans *trans;
1291 int n_entries, ln;
1292
1293 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1294 return;
1295
1296 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
1297 if (drm_WARN_ON_ONCE(display->drm, !trans))
1298 return;
1299
1300 for (ln = 0; ln < 2; ln++) {
1301 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),
1302 CRI_USE_FS32, 0);
1303 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),
1304 CRI_USE_FS32, 0);
1305 }
1306
1307 /* Program MG_TX_SWINGCTRL with values from vswing table */
1308 for (ln = 0; ln < 2; ln++) {
1309 int level;
1310
1311 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1312
1313 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),
1314 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1315 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1316
1317 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1318
1319 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),
1320 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1321 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1322 }
1323
1324 /* Program MG_TX_DRVCTRL with values from vswing table */
1325 for (ln = 0; ln < 2; ln++) {
1326 int level;
1327
1328 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1329
1330 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),
1331 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1332 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1333 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1334 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1335 CRI_TXDEEMPH_OVERRIDE_EN);
1336
1337 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1338
1339 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),
1340 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1341 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1342 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1343 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1344 CRI_TXDEEMPH_OVERRIDE_EN);
1345
1346 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1347 }
1348
1349 /*
1350 * Program MG_CLKHUB<LN, port being used> with value from frequency table
1351 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1352 * values from table for which TX1 and TX2 enabled.
1353 */
1354 for (ln = 0; ln < 2; ln++) {
1355 intel_de_rmw(display, MG_CLKHUB(ln, tc_port),
1356 CFG_LOW_RATE_LKREN_EN,
1357 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1358 }
1359
1360 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1361 for (ln = 0; ln < 2; ln++) {
1362 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),
1363 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1364 CFG_AMI_CK_DIV_OVERRIDE_EN,
1365 crtc_state->port_clock > 500000 ?
1366 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1367 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1368
1369 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),
1370 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1371 CFG_AMI_CK_DIV_OVERRIDE_EN,
1372 crtc_state->port_clock > 500000 ?
1373 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1374 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1375 }
1376
1377 /* Program MG_TX_PISO_READLOAD with values from vswing table */
1378 for (ln = 0; ln < 2; ln++) {
1379 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),
1380 0, CRI_CALCINIT);
1381 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),
1382 0, CRI_CALCINIT);
1383 }
1384 }
1385
tgl_dkl_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1386 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1387 const struct intel_crtc_state *crtc_state)
1388 {
1389 struct intel_display *display = to_intel_display(encoder);
1390 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1391 const struct intel_ddi_buf_trans *trans;
1392 int n_entries, ln;
1393
1394 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1395 return;
1396
1397 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
1398 if (drm_WARN_ON_ONCE(display->drm, !trans))
1399 return;
1400
1401 for (ln = 0; ln < 2; ln++) {
1402 int level;
1403
1404 /* Wa_16011342517:adl-p */
1405 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011342517)) {
1406 if ((intel_encoder_is_hdmi(encoder) &&
1407 crtc_state->port_clock == 594000) ||
1408 (intel_encoder_is_dp(encoder) &&
1409 crtc_state->port_clock == 162000)) {
1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1411 LOADGEN_SHARING_PMD_DISABLE, 1);
1412 } else {
1413 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1414 LOADGEN_SHARING_PMD_DISABLE, 0);
1415 }
1416 }
1417
1418 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1419
1420 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1421
1422 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
1423 DKL_TX_PRESHOOT_COEFF_MASK |
1424 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1425 DKL_TX_VSWING_CONTROL_MASK,
1426 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1427 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1428 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1429
1430 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1431
1432 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
1433 DKL_TX_PRESHOOT_COEFF_MASK |
1434 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1435 DKL_TX_VSWING_CONTROL_MASK,
1436 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1437 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1438 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1439
1440 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1441 DKL_TX_DP20BITMODE, 0);
1442
1443 if (display->platform.alderlake_p) {
1444 u32 val;
1445
1446 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1447 if (ln == 0) {
1448 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1449 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1450 } else {
1451 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1452 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1453 }
1454 } else {
1455 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1456 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1457 }
1458
1459 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1460 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1461 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1462 val);
1463 }
1464 }
1465 }
1466
translate_signal_level(struct intel_dp * intel_dp,u8 signal_levels)1467 static int translate_signal_level(struct intel_dp *intel_dp,
1468 u8 signal_levels)
1469 {
1470 struct intel_display *display = to_intel_display(intel_dp);
1471 const u8 *signal_array;
1472 size_t array_size;
1473 int i;
1474
1475 signal_array = index_to_dp_signal_levels;
1476 array_size = ARRAY_SIZE(index_to_dp_signal_levels);
1477
1478 for (i = 0; i < array_size; i++) {
1479 if (signal_array[i] == signal_levels)
1480 return i;
1481 }
1482
1483 drm_WARN(display->drm, 1,
1484 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1485 signal_levels);
1486
1487 return 0;
1488 }
1489
intel_ddi_dp_level(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int lane)1490 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1491 const struct intel_crtc_state *crtc_state,
1492 int lane)
1493 {
1494 u8 train_set = intel_dp->train_set[lane];
1495
1496 if (intel_dp_is_uhbr(crtc_state)) {
1497 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1498 } else {
1499 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1500 DP_TRAIN_PRE_EMPHASIS_MASK);
1501
1502 return translate_signal_level(intel_dp, signal_levels);
1503 }
1504 }
1505
intel_ddi_level(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int lane)1506 int intel_ddi_level(struct intel_encoder *encoder,
1507 const struct intel_crtc_state *crtc_state,
1508 int lane)
1509 {
1510 struct intel_display *display = to_intel_display(encoder);
1511 const struct intel_ddi_buf_trans *trans;
1512 int level, n_entries;
1513
1514 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries);
1515 if (drm_WARN_ON_ONCE(display->drm, !trans))
1516 return 0;
1517
1518 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1519 level = intel_ddi_hdmi_level(encoder, trans);
1520 else
1521 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1522 lane);
1523
1524 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))
1525 level = n_entries - 1;
1526
1527 return level;
1528 }
1529
1530 static void
hsw_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1531 hsw_set_signal_levels(struct intel_encoder *encoder,
1532 const struct intel_crtc_state *crtc_state)
1533 {
1534 struct intel_display *display = to_intel_display(encoder);
1535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1536 int level = intel_ddi_level(encoder, crtc_state, 0);
1537 enum port port = encoder->port;
1538 u32 signal_levels;
1539
1540 if (has_iboost(display))
1541 skl_ddi_set_iboost(encoder, crtc_state, level);
1542
1543 /* HDMI ignores the rest */
1544 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1545 return;
1546
1547 signal_levels = DDI_BUF_TRANS_SELECT(level);
1548
1549 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1550 signal_levels);
1551
1552 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1553 intel_dp->DP |= signal_levels;
1554
1555 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);
1556 intel_de_posting_read(display, DDI_BUF_CTL(port));
1557 }
1558
_icl_ddi_enable_clock(struct intel_display * display,intel_reg_t reg,u32 clk_sel_mask,u32 clk_sel,u32 clk_off)1559 static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg,
1560 u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1561 {
1562 mutex_lock(&display->dpll.lock);
1563
1564 intel_de_rmw(display, reg, clk_sel_mask, clk_sel);
1565
1566 /*
1567 * "This step and the step before must be
1568 * done with separate register writes."
1569 */
1570 intel_de_rmw(display, reg, clk_off, 0);
1571
1572 mutex_unlock(&display->dpll.lock);
1573 }
1574
_icl_ddi_disable_clock(struct intel_display * display,intel_reg_t reg,u32 clk_off)1575 static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg,
1576 u32 clk_off)
1577 {
1578 mutex_lock(&display->dpll.lock);
1579
1580 intel_de_rmw(display, reg, 0, clk_off);
1581
1582 mutex_unlock(&display->dpll.lock);
1583 }
1584
_icl_ddi_is_clock_enabled(struct intel_display * display,intel_reg_t reg,u32 clk_off)1585 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg,
1586 u32 clk_off)
1587 {
1588 return !(intel_de_read(display, reg) & clk_off);
1589 }
1590
1591 static struct intel_dpll *
_icl_ddi_get_pll(struct intel_display * display,intel_reg_t reg,u32 clk_sel_mask,u32 clk_sel_shift)1592 _icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg,
1593 u32 clk_sel_mask, u32 clk_sel_shift)
1594 {
1595 enum intel_dpll_id id;
1596
1597 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
1598
1599 return intel_get_dpll_by_id(display, id);
1600 }
1601
adls_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1602 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1603 const struct intel_crtc_state *crtc_state)
1604 {
1605 struct intel_display *display = to_intel_display(encoder);
1606 const struct intel_dpll *pll = crtc_state->intel_dpll;
1607 enum phy phy = intel_encoder_to_phy(encoder);
1608
1609 if (drm_WARN_ON(display->drm, !pll))
1610 return;
1611
1612 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),
1613 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1614 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1615 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1616 }
1617
adls_ddi_disable_clock(struct intel_encoder * encoder)1618 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1619 {
1620 struct intel_display *display = to_intel_display(encoder);
1621 enum phy phy = intel_encoder_to_phy(encoder);
1622
1623 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),
1624 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1625 }
1626
adls_ddi_is_clock_enabled(struct intel_encoder * encoder)1627 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1628 {
1629 struct intel_display *display = to_intel_display(encoder);
1630 enum phy phy = intel_encoder_to_phy(encoder);
1631
1632 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),
1633 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1634 }
1635
adls_ddi_get_pll(struct intel_encoder * encoder)1636 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1637 {
1638 struct intel_display *display = to_intel_display(encoder);
1639 enum phy phy = intel_encoder_to_phy(encoder);
1640
1641 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
1642 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1643 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1644 }
1645
rkl_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1646 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1647 const struct intel_crtc_state *crtc_state)
1648 {
1649 struct intel_display *display = to_intel_display(encoder);
1650 const struct intel_dpll *pll = crtc_state->intel_dpll;
1651 enum phy phy = intel_encoder_to_phy(encoder);
1652
1653 if (drm_WARN_ON(display->drm, !pll))
1654 return;
1655
1656 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
1657 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1658 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1659 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1660 }
1661
rkl_ddi_disable_clock(struct intel_encoder * encoder)1662 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1663 {
1664 struct intel_display *display = to_intel_display(encoder);
1665 enum phy phy = intel_encoder_to_phy(encoder);
1666
1667 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
1668 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1669 }
1670
rkl_ddi_is_clock_enabled(struct intel_encoder * encoder)1671 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1672 {
1673 struct intel_display *display = to_intel_display(encoder);
1674 enum phy phy = intel_encoder_to_phy(encoder);
1675
1676 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
1677 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1678 }
1679
rkl_ddi_get_pll(struct intel_encoder * encoder)1680 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1681 {
1682 struct intel_display *display = to_intel_display(encoder);
1683 enum phy phy = intel_encoder_to_phy(encoder);
1684
1685 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
1686 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1687 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1688 }
1689
dg1_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1690 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1691 const struct intel_crtc_state *crtc_state)
1692 {
1693 struct intel_display *display = to_intel_display(encoder);
1694 const struct intel_dpll *pll = crtc_state->intel_dpll;
1695 enum phy phy = intel_encoder_to_phy(encoder);
1696
1697 if (drm_WARN_ON(display->drm, !pll))
1698 return;
1699
1700 /*
1701 * If we fail this, something went very wrong: first 2 PLLs should be
1702 * used by first 2 phys and last 2 PLLs by last phys
1703 */
1704 if (drm_WARN_ON(display->drm,
1705 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1706 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1707 return;
1708
1709 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),
1710 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1711 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1712 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1713 }
1714
dg1_ddi_disable_clock(struct intel_encoder * encoder)1715 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1716 {
1717 struct intel_display *display = to_intel_display(encoder);
1718 enum phy phy = intel_encoder_to_phy(encoder);
1719
1720 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),
1721 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1722 }
1723
dg1_ddi_is_clock_enabled(struct intel_encoder * encoder)1724 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1725 {
1726 struct intel_display *display = to_intel_display(encoder);
1727 enum phy phy = intel_encoder_to_phy(encoder);
1728
1729 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),
1730 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1731 }
1732
dg1_ddi_get_pll(struct intel_encoder * encoder)1733 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1734 {
1735 struct intel_display *display = to_intel_display(encoder);
1736 enum phy phy = intel_encoder_to_phy(encoder);
1737 enum intel_dpll_id id;
1738 u32 val;
1739
1740 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
1741 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1742 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1743 id = val;
1744
1745 /*
1746 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1747 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1748 * bit for phy C and D.
1749 */
1750 if (phy >= PHY_C)
1751 id += DPLL_ID_DG1_DPLL2;
1752
1753 return intel_get_dpll_by_id(display, id);
1754 }
1755
icl_ddi_combo_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1756 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1757 const struct intel_crtc_state *crtc_state)
1758 {
1759 struct intel_display *display = to_intel_display(encoder);
1760 const struct intel_dpll *pll = crtc_state->intel_dpll;
1761 enum phy phy = intel_encoder_to_phy(encoder);
1762
1763 if (drm_WARN_ON(display->drm, !pll))
1764 return;
1765
1766 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
1767 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1768 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1769 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1770 }
1771
icl_ddi_combo_disable_clock(struct intel_encoder * encoder)1772 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1773 {
1774 struct intel_display *display = to_intel_display(encoder);
1775 enum phy phy = intel_encoder_to_phy(encoder);
1776
1777 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
1778 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1779 }
1780
icl_ddi_combo_is_clock_enabled(struct intel_encoder * encoder)1781 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1782 {
1783 struct intel_display *display = to_intel_display(encoder);
1784 enum phy phy = intel_encoder_to_phy(encoder);
1785
1786 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
1787 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1788 }
1789
icl_ddi_combo_get_pll(struct intel_encoder * encoder)1790 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1791 {
1792 struct intel_display *display = to_intel_display(encoder);
1793 enum phy phy = intel_encoder_to_phy(encoder);
1794
1795 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
1796 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1797 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1798 }
1799
jsl_ddi_tc_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1800 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1801 const struct intel_crtc_state *crtc_state)
1802 {
1803 struct intel_display *display = to_intel_display(encoder);
1804 const struct intel_dpll *pll = crtc_state->intel_dpll;
1805 enum port port = encoder->port;
1806
1807 if (drm_WARN_ON(display->drm, !pll))
1808 return;
1809
1810 /*
1811 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1812 * MG does not exist, but the programming is required to ungate DDIC and DDID."
1813 */
1814 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1815
1816 icl_ddi_combo_enable_clock(encoder, crtc_state);
1817 }
1818
jsl_ddi_tc_disable_clock(struct intel_encoder * encoder)1819 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1820 {
1821 struct intel_display *display = to_intel_display(encoder);
1822 enum port port = encoder->port;
1823
1824 icl_ddi_combo_disable_clock(encoder);
1825
1826 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1827 }
1828
jsl_ddi_tc_is_clock_enabled(struct intel_encoder * encoder)1829 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1830 {
1831 struct intel_display *display = to_intel_display(encoder);
1832 enum port port = encoder->port;
1833 u32 tmp;
1834
1835 tmp = intel_de_read(display, DDI_CLK_SEL(port));
1836
1837 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1838 return false;
1839
1840 return icl_ddi_combo_is_clock_enabled(encoder);
1841 }
1842
icl_ddi_tc_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1843 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1844 const struct intel_crtc_state *crtc_state)
1845 {
1846 struct intel_display *display = to_intel_display(encoder);
1847 const struct intel_dpll *pll = crtc_state->intel_dpll;
1848 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1849 enum port port = encoder->port;
1850
1851 if (drm_WARN_ON(display->drm, !pll))
1852 return;
1853
1854 intel_de_write(display, DDI_CLK_SEL(port),
1855 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1856
1857 mutex_lock(&display->dpll.lock);
1858
1859 intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
1860 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1861
1862 mutex_unlock(&display->dpll.lock);
1863 }
1864
icl_ddi_tc_disable_clock(struct intel_encoder * encoder)1865 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1866 {
1867 struct intel_display *display = to_intel_display(encoder);
1868 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1869 enum port port = encoder->port;
1870
1871 mutex_lock(&display->dpll.lock);
1872
1873 intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
1874 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1875
1876 mutex_unlock(&display->dpll.lock);
1877
1878 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1879 }
1880
icl_ddi_tc_is_clock_enabled(struct intel_encoder * encoder)1881 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1882 {
1883 struct intel_display *display = to_intel_display(encoder);
1884 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1885 enum port port = encoder->port;
1886 u32 tmp;
1887
1888 tmp = intel_de_read(display, DDI_CLK_SEL(port));
1889
1890 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1891 return false;
1892
1893 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
1894
1895 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1896 }
1897
icl_ddi_tc_get_pll(struct intel_encoder * encoder)1898 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1899 {
1900 struct intel_display *display = to_intel_display(encoder);
1901 enum tc_port tc_port = intel_encoder_to_tc(encoder);
1902 enum port port = encoder->port;
1903 enum intel_dpll_id id;
1904 u32 tmp;
1905
1906 tmp = intel_de_read(display, DDI_CLK_SEL(port));
1907
1908 switch (tmp & DDI_CLK_SEL_MASK) {
1909 case DDI_CLK_SEL_TBT_162:
1910 case DDI_CLK_SEL_TBT_270:
1911 case DDI_CLK_SEL_TBT_540:
1912 case DDI_CLK_SEL_TBT_810:
1913 id = DPLL_ID_ICL_TBTPLL;
1914 break;
1915 case DDI_CLK_SEL_MG:
1916 id = icl_tc_port_to_pll_id(tc_port);
1917 break;
1918 default:
1919 MISSING_CASE(tmp);
1920 fallthrough;
1921 case DDI_CLK_SEL_NONE:
1922 return NULL;
1923 }
1924
1925 return intel_get_dpll_by_id(display, id);
1926 }
1927
bxt_ddi_get_pll(struct intel_encoder * encoder)1928 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1929 {
1930 struct intel_display *display = to_intel_display(encoder->base.dev);
1931 enum intel_dpll_id id;
1932
1933 switch (encoder->port) {
1934 case PORT_A:
1935 id = DPLL_ID_SKL_DPLL0;
1936 break;
1937 case PORT_B:
1938 id = DPLL_ID_SKL_DPLL1;
1939 break;
1940 case PORT_C:
1941 id = DPLL_ID_SKL_DPLL2;
1942 break;
1943 default:
1944 MISSING_CASE(encoder->port);
1945 return NULL;
1946 }
1947
1948 return intel_get_dpll_by_id(display, id);
1949 }
1950
skl_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1951 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1952 const struct intel_crtc_state *crtc_state)
1953 {
1954 struct intel_display *display = to_intel_display(encoder);
1955 const struct intel_dpll *pll = crtc_state->intel_dpll;
1956 enum port port = encoder->port;
1957
1958 if (drm_WARN_ON(display->drm, !pll))
1959 return;
1960
1961 mutex_lock(&display->dpll.lock);
1962
1963 intel_de_rmw(display, DPLL_CTRL2,
1964 DPLL_CTRL2_DDI_CLK_OFF(port) |
1965 DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1966 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1967 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1968
1969 mutex_unlock(&display->dpll.lock);
1970 }
1971
skl_ddi_disable_clock(struct intel_encoder * encoder)1972 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1973 {
1974 struct intel_display *display = to_intel_display(encoder);
1975 enum port port = encoder->port;
1976
1977 mutex_lock(&display->dpll.lock);
1978
1979 intel_de_rmw(display, DPLL_CTRL2,
1980 0, DPLL_CTRL2_DDI_CLK_OFF(port));
1981
1982 mutex_unlock(&display->dpll.lock);
1983 }
1984
skl_ddi_is_clock_enabled(struct intel_encoder * encoder)1985 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1986 {
1987 struct intel_display *display = to_intel_display(encoder);
1988 enum port port = encoder->port;
1989
1990 /*
1991 * FIXME Not sure if the override affects both
1992 * the PLL selection and the CLK_OFF bit.
1993 */
1994 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1995 }
1996
skl_ddi_get_pll(struct intel_encoder * encoder)1997 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1998 {
1999 struct intel_display *display = to_intel_display(encoder);
2000 enum port port = encoder->port;
2001 enum intel_dpll_id id;
2002 u32 tmp;
2003
2004 tmp = intel_de_read(display, DPLL_CTRL2);
2005
2006 /*
2007 * FIXME Not sure if the override affects both
2008 * the PLL selection and the CLK_OFF bit.
2009 */
2010 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
2011 return NULL;
2012
2013 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
2014 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
2015
2016 return intel_get_dpll_by_id(display, id);
2017 }
2018
hsw_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2019 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
2020 const struct intel_crtc_state *crtc_state)
2021 {
2022 struct intel_display *display = to_intel_display(encoder);
2023 const struct intel_dpll *pll = crtc_state->intel_dpll;
2024 enum port port = encoder->port;
2025
2026 if (drm_WARN_ON(display->drm, !pll))
2027 return;
2028
2029 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2030 }
2031
hsw_ddi_disable_clock(struct intel_encoder * encoder)2032 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
2033 {
2034 struct intel_display *display = to_intel_display(encoder);
2035 enum port port = encoder->port;
2036
2037 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2038 }
2039
hsw_ddi_is_clock_enabled(struct intel_encoder * encoder)2040 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
2041 {
2042 struct intel_display *display = to_intel_display(encoder);
2043 enum port port = encoder->port;
2044
2045 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
2046 }
2047
hsw_ddi_get_pll(struct intel_encoder * encoder)2048 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
2049 {
2050 struct intel_display *display = to_intel_display(encoder);
2051 enum port port = encoder->port;
2052 enum intel_dpll_id id;
2053 u32 tmp;
2054
2055 tmp = intel_de_read(display, PORT_CLK_SEL(port));
2056
2057 switch (tmp & PORT_CLK_SEL_MASK) {
2058 case PORT_CLK_SEL_WRPLL1:
2059 id = DPLL_ID_WRPLL1;
2060 break;
2061 case PORT_CLK_SEL_WRPLL2:
2062 id = DPLL_ID_WRPLL2;
2063 break;
2064 case PORT_CLK_SEL_SPLL:
2065 id = DPLL_ID_SPLL;
2066 break;
2067 case PORT_CLK_SEL_LCPLL_810:
2068 id = DPLL_ID_LCPLL_810;
2069 break;
2070 case PORT_CLK_SEL_LCPLL_1350:
2071 id = DPLL_ID_LCPLL_1350;
2072 break;
2073 case PORT_CLK_SEL_LCPLL_2700:
2074 id = DPLL_ID_LCPLL_2700;
2075 break;
2076 default:
2077 MISSING_CASE(tmp);
2078 fallthrough;
2079 case PORT_CLK_SEL_NONE:
2080 return NULL;
2081 }
2082
2083 return intel_get_dpll_by_id(display, id);
2084 }
2085
intel_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2086 void intel_ddi_enable_clock(struct intel_encoder *encoder,
2087 const struct intel_crtc_state *crtc_state)
2088 {
2089 if (encoder->enable_clock)
2090 encoder->enable_clock(encoder, crtc_state);
2091 }
2092
intel_ddi_disable_clock(struct intel_encoder * encoder)2093 void intel_ddi_disable_clock(struct intel_encoder *encoder)
2094 {
2095 if (encoder->disable_clock)
2096 encoder->disable_clock(encoder);
2097 }
2098
intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder * encoder)2099 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2100 {
2101 struct intel_display *display = to_intel_display(encoder);
2102 u32 port_mask;
2103 bool ddi_clk_needed;
2104
2105 /*
2106 * In case of DP MST, we sanitize the primary encoder only, not the
2107 * virtual ones.
2108 */
2109 if (encoder->type == INTEL_OUTPUT_DP_MST)
2110 return;
2111
2112 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2113 u8 pipe_mask;
2114 bool is_mst;
2115
2116 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2117 /*
2118 * In the unlikely case that BIOS enables DP in MST mode, just
2119 * warn since our MST HW readout is incomplete.
2120 */
2121 if (drm_WARN_ON(display->drm, is_mst))
2122 return;
2123 }
2124
2125 port_mask = BIT(encoder->port);
2126 ddi_clk_needed = encoder->base.crtc;
2127
2128 if (encoder->type == INTEL_OUTPUT_DSI) {
2129 struct intel_encoder *other_encoder;
2130
2131 port_mask = intel_dsi_encoder_ports(encoder);
2132 /*
2133 * Sanity check that we haven't incorrectly registered another
2134 * encoder using any of the ports of this DSI encoder.
2135 */
2136 for_each_intel_encoder(display->drm, other_encoder) {
2137 if (other_encoder == encoder)
2138 continue;
2139
2140 if (drm_WARN_ON(display->drm,
2141 port_mask & BIT(other_encoder->port)))
2142 return;
2143 }
2144 /*
2145 * For DSI we keep the ddi clocks gated
2146 * except during enable/disable sequence.
2147 */
2148 ddi_clk_needed = false;
2149 }
2150
2151 if (ddi_clk_needed || !encoder->is_clock_enabled ||
2152 !encoder->is_clock_enabled(encoder))
2153 return;
2154
2155 drm_dbg_kms(display->drm,
2156 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2157 encoder->base.base.id, encoder->base.name);
2158
2159 encoder->disable_clock(encoder);
2160 }
2161
2162 static void
tgl_dkl_phy_check_and_rewrite(struct intel_display * display,enum tc_port tc_port,u32 ln0,u32 ln1)2163 tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
2164 enum tc_port tc_port, u32 ln0, u32 ln1)
2165 {
2166 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
2167 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
2168 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
2169 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
2170 }
2171
2172 static void
icl_program_mg_dp_mode(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)2173 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2174 const struct intel_crtc_state *crtc_state)
2175 {
2176 struct intel_display *display = to_intel_display(crtc_state);
2177 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
2178 enum intel_tc_pin_assignment pin_assignment;
2179 u32 ln0, ln1;
2180 u8 width;
2181
2182 if (DISPLAY_VER(display) >= 14)
2183 return;
2184
2185 if (!intel_encoder_is_tc(&dig_port->base) ||
2186 intel_tc_port_in_tbt_alt_mode(dig_port))
2187 return;
2188
2189 if (DISPLAY_VER(display) >= 12) {
2190 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
2191 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
2192 } else {
2193 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
2194 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
2195 }
2196
2197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2198 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2199
2200 /* DPPATC */
2201 pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
2202 width = crtc_state->lane_count;
2203
2204 switch (pin_assignment) {
2205 case INTEL_TC_PIN_ASSIGNMENT_NONE:
2206 drm_WARN_ON(display->drm,
2207 !intel_tc_port_in_legacy_mode(dig_port));
2208 if (width == 1) {
2209 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2210 } else {
2211 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2212 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2213 }
2214 break;
2215 case INTEL_TC_PIN_ASSIGNMENT_A:
2216 if (width == 4) {
2217 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2218 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2219 }
2220 break;
2221 case INTEL_TC_PIN_ASSIGNMENT_B:
2222 if (width == 2) {
2223 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2224 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2225 }
2226 break;
2227 case INTEL_TC_PIN_ASSIGNMENT_C:
2228 case INTEL_TC_PIN_ASSIGNMENT_E:
2229 if (width == 1) {
2230 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2231 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2232 } else {
2233 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2234 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2235 }
2236 break;
2237 case INTEL_TC_PIN_ASSIGNMENT_D:
2238 case INTEL_TC_PIN_ASSIGNMENT_F:
2239 if (width == 1) {
2240 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2241 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2242 } else {
2243 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2244 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2245 }
2246 break;
2247 default:
2248 MISSING_CASE(pin_assignment);
2249 }
2250
2251 if (DISPLAY_VER(display) >= 12) {
2252 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
2253 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
2254 /* WA_14018221282 */
2255 if (IS_DISPLAY_VER(display, 12, 13))
2256 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
2257
2258 } else {
2259 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
2260 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
2261 }
2262 }
2263
2264 static enum transcoder
tgl_dp_tp_transcoder(const struct intel_crtc_state * crtc_state)2265 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2266 {
2267 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2268 return crtc_state->mst_master_transcoder;
2269 else
2270 return crtc_state->cpu_transcoder;
2271 }
2272
dp_tp_ctl_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2273 intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2274 const struct intel_crtc_state *crtc_state)
2275 {
2276 struct intel_display *display = to_intel_display(encoder);
2277
2278 if (DISPLAY_VER(display) >= 12)
2279 return TGL_DP_TP_CTL(display,
2280 tgl_dp_tp_transcoder(crtc_state));
2281 else
2282 return DP_TP_CTL(encoder->port);
2283 }
2284
dp_tp_status_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2285 static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2286 const struct intel_crtc_state *crtc_state)
2287 {
2288 struct intel_display *display = to_intel_display(encoder);
2289
2290 if (DISPLAY_VER(display) >= 12)
2291 return TGL_DP_TP_STATUS(display,
2292 tgl_dp_tp_transcoder(crtc_state));
2293 else
2294 return DP_TP_STATUS(encoder->port);
2295 }
2296
intel_ddi_clear_act_sent(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2297 void intel_ddi_clear_act_sent(struct intel_encoder *encoder,
2298 const struct intel_crtc_state *crtc_state)
2299 {
2300 struct intel_display *display = to_intel_display(encoder);
2301
2302 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state),
2303 DP_TP_STATUS_ACT_SENT);
2304 }
2305
intel_ddi_wait_for_act_sent(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2306 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder,
2307 const struct intel_crtc_state *crtc_state)
2308 {
2309 struct intel_display *display = to_intel_display(encoder);
2310
2311 if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
2312 DP_TP_STATUS_ACT_SENT, 1))
2313 drm_err(display->drm, "Timed out waiting for ACT sent\n");
2314 }
2315
intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)2316 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2317 const struct intel_crtc_state *crtc_state,
2318 bool enable)
2319 {
2320 struct intel_display *display = to_intel_display(intel_dp);
2321
2322 if (!crtc_state->vrr.enable)
2323 return;
2324
2325 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2326 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2327 drm_dbg_kms(display->drm,
2328 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2329 str_enable_disable(enable));
2330 }
2331
intel_dp_sink_set_fec_ready(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)2332 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2333 const struct intel_crtc_state *crtc_state,
2334 bool enable)
2335 {
2336 struct intel_display *display = to_intel_display(intel_dp);
2337
2338 if (!crtc_state->fec_enable)
2339 return;
2340
2341 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
2342 enable ? DP_FEC_READY : 0) <= 0)
2343 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",
2344 str_enabled_disabled(enable));
2345
2346 if (enable &&
2347 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
2348 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
2349 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");
2350 }
2351
wait_for_fec_detected(struct drm_dp_aux * aux,bool enabled)2352 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2353 {
2354 struct intel_display *display = to_intel_display(aux->drm_dev);
2355 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
2356 u8 status = 0;
2357 int ret, err;
2358
2359 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status),
2360 err || (status & mask),
2361 10 * 1000, 200 * 1000, false);
2362
2363 /* Either can be non-zero, but not both */
2364 ret = ret ?: err;
2365 if (ret) {
2366 drm_dbg_kms(display->drm,
2367 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n",
2368 str_enabled_disabled(enabled), ret, status);
2369 return ret;
2370 }
2371
2372 return 0;
2373 }
2374
intel_ddi_wait_for_fec_status(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,bool enabled)2375 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
2376 const struct intel_crtc_state *crtc_state,
2377 bool enabled)
2378 {
2379 struct intel_display *display = to_intel_display(encoder);
2380 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2381 int ret;
2382
2383 if (!crtc_state->fec_enable)
2384 return 0;
2385
2386 if (enabled)
2387 ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state),
2388 DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
2389 else
2390 ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state),
2391 DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
2392
2393 if (ret) {
2394 drm_err(display->drm,
2395 "Timeout waiting for FEC live state to get %s\n",
2396 str_enabled_disabled(enabled));
2397 return ret;
2398 }
2399 /*
2400 * At least the Synoptics MST hub doesn't set the detected flag for
2401 * FEC decoding disabling so skip waiting for that.
2402 */
2403 if (enabled) {
2404 ret = wait_for_fec_detected(&intel_dp->aux, enabled);
2405 if (ret)
2406 return ret;
2407 }
2408
2409 return 0;
2410 }
2411
intel_ddi_enable_fec(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2412 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2413 const struct intel_crtc_state *crtc_state)
2414 {
2415 struct intel_display *display = to_intel_display(encoder);
2416 int i;
2417 int ret;
2418
2419 if (!crtc_state->fec_enable)
2420 return;
2421
2422 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2423 0, DP_TP_CTL_FEC_ENABLE);
2424
2425 if (DISPLAY_VER(display) < 30)
2426 return;
2427
2428 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
2429 if (!ret)
2430 return;
2431
2432 for (i = 0; i < 3; i++) {
2433 drm_dbg_kms(display->drm, "Retry FEC enabling\n");
2434
2435 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2436 DP_TP_CTL_FEC_ENABLE, 0);
2437
2438 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
2439 if (ret)
2440 continue;
2441
2442 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2443 0, DP_TP_CTL_FEC_ENABLE);
2444
2445 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
2446 if (!ret)
2447 return;
2448 }
2449
2450 drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n");
2451 }
2452
intel_ddi_disable_fec(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2453 static void intel_ddi_disable_fec(struct intel_encoder *encoder,
2454 const struct intel_crtc_state *crtc_state)
2455 {
2456 struct intel_display *display = to_intel_display(encoder);
2457
2458 if (!crtc_state->fec_enable)
2459 return;
2460
2461 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2462 DP_TP_CTL_FEC_ENABLE, 0);
2463 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
2464 }
2465
intel_ddi_power_up_lanes(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2466 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2467 const struct intel_crtc_state *crtc_state)
2468 {
2469 struct intel_display *display = to_intel_display(encoder);
2470 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2471
2472 if (intel_encoder_is_combo(encoder)) {
2473 enum phy phy = intel_encoder_to_phy(encoder);
2474
2475 intel_combo_phy_power_up_lanes(display, phy, false,
2476 crtc_state->lane_count,
2477 dig_port->lane_reversal);
2478 }
2479 }
2480
2481 /*
2482 * Splitter enable for eDP MSO is limited to certain pipes, on certain
2483 * platforms.
2484 */
intel_ddi_splitter_pipe_mask(struct intel_display * display)2485 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)
2486 {
2487 if (DISPLAY_VER(display) > 20)
2488 return ~0;
2489 else if (display->platform.alderlake_p)
2490 return BIT(PIPE_A) | BIT(PIPE_B);
2491 else
2492 return BIT(PIPE_A);
2493 }
2494
intel_ddi_mso_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)2495 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2496 struct intel_crtc_state *pipe_config)
2497 {
2498 struct intel_display *display = to_intel_display(pipe_config);
2499 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2500 enum pipe pipe = crtc->pipe;
2501 u32 dss1;
2502
2503 if (!HAS_MSO(display))
2504 return;
2505
2506 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
2507
2508 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2509 if (!pipe_config->splitter.enable)
2510 return;
2511
2512 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {
2513 pipe_config->splitter.enable = false;
2514 return;
2515 }
2516
2517 switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2518 default:
2519 drm_WARN(display->drm, true,
2520 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2521 fallthrough;
2522 case SPLITTER_CONFIGURATION_2_SEGMENT:
2523 pipe_config->splitter.link_count = 2;
2524 break;
2525 case SPLITTER_CONFIGURATION_4_SEGMENT:
2526 pipe_config->splitter.link_count = 4;
2527 break;
2528 }
2529
2530 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2531 }
2532
intel_ddi_mso_configure(const struct intel_crtc_state * crtc_state)2533 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2534 {
2535 struct intel_display *display = to_intel_display(crtc_state);
2536 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2537 enum pipe pipe = crtc->pipe;
2538 u32 dss1 = 0;
2539
2540 if (!HAS_MSO(display))
2541 return;
2542
2543 if (crtc_state->splitter.enable) {
2544 dss1 |= SPLITTER_ENABLE;
2545 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2546 if (crtc_state->splitter.link_count == 2)
2547 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2548 else
2549 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2550 }
2551
2552 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
2553 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2554 OVERLAP_PIXELS_MASK, dss1);
2555 }
2556
2557 static void
mtl_ddi_enable_d2d(struct intel_encoder * encoder)2558 mtl_ddi_enable_d2d(struct intel_encoder *encoder)
2559 {
2560 struct intel_display *display = to_intel_display(encoder);
2561 enum port port = encoder->port;
2562 intel_reg_t reg;
2563 u32 set_bits, wait_bits;
2564 int ret;
2565
2566 if (DISPLAY_VER(display) < 14)
2567 return;
2568
2569 if (DISPLAY_VER(display) >= 20) {
2570 reg = DDI_BUF_CTL(port);
2571 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
2572 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
2573 } else {
2574 reg = XELPDP_PORT_BUF_CTL1(display, port);
2575 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
2576 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
2577 }
2578
2579 intel_de_rmw(display, reg, 0, set_bits);
2580
2581 ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100);
2582 if (ret) {
2583 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
2584 port_name(port));
2585 }
2586 }
2587
mtl_port_buf_ctl_program(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2588 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2589 const struct intel_crtc_state *crtc_state)
2590 {
2591 struct intel_display *display = to_intel_display(encoder);
2592 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2593 enum port port = encoder->port;
2594 u32 val = 0;
2595
2596 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
2597
2598 if (intel_dp_is_uhbr(crtc_state))
2599 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2600 else
2601 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
2602
2603 if (dig_port->lane_reversal)
2604 val |= XELPDP_PORT_REVERSAL;
2605
2606 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
2607 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK,
2608 val);
2609 }
2610
mtl_port_buf_ctl_io_selection(struct intel_encoder * encoder)2611 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
2612 {
2613 struct intel_display *display = to_intel_display(encoder);
2614 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2615 u32 val;
2616
2617 val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
2618 XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
2619 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
2620 XELPDP_PORT_BUF_IO_SELECT_TBT, val);
2621 }
2622
mtl_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2623 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2624 struct intel_encoder *encoder,
2625 const struct intel_crtc_state *crtc_state,
2626 const struct drm_connector_state *conn_state)
2627 {
2628 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2629 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2630 bool transparent_mode;
2631 int ret;
2632
2633 intel_dp_set_link_params(intel_dp,
2634 crtc_state->port_clock,
2635 crtc_state->lane_count);
2636
2637 /*
2638 * We only configure what the register value will be here. Actual
2639 * enabling happens during link training farther down.
2640 */
2641 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2642
2643 /*
2644 * 1. Enable Power Wells
2645 *
2646 * This was handled at the beginning of intel_atomic_commit_tail(),
2647 * before we called down into this function.
2648 */
2649
2650 /* 2. PMdemand was already set */
2651
2652 /* 3. Select Thunderbolt */
2653 mtl_port_buf_ctl_io_selection(encoder);
2654
2655 /* 5. Enable the port PLL */
2656 intel_ddi_enable_clock(encoder, crtc_state);
2657
2658 /*
2659 * 6.a Configure Transcoder Clock Select to direct the Port clock to the
2660 * Transcoder.
2661 */
2662 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2663
2664 /*
2665 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
2666 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2667 * Transport Select
2668 */
2669 intel_ddi_config_transcoder_func(encoder, crtc_state);
2670
2671 /*
2672 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2673 */
2674 intel_ddi_mso_configure(crtc_state);
2675
2676 if (!is_mst)
2677 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2678
2679 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp);
2680 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode);
2681
2682 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2683 if (!is_mst)
2684 intel_dp_sink_enable_decompression(state,
2685 to_intel_connector(conn_state->connector),
2686 crtc_state);
2687
2688 /*
2689 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2690 * in the FEC_CONFIGURATION register to 1 before initiating link
2691 * training
2692 */
2693 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
2694
2695 intel_dp_check_frl_training(intel_dp);
2696 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2697
2698 /*
2699 * 6. The rest of the below are substeps under the bspec's "Enable and
2700 * Train Display Port" step. Note that steps that are specific to
2701 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2702 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2703 * us when active_mst_links==0, so any steps designated for "single
2704 * stream or multi-stream master transcoder" can just be performed
2705 * unconditionally here.
2706 *
2707 * mtl_ddi_prepare_link_retrain() that is called by
2708 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
2709 * 6.i and 6.j
2710 *
2711 * 6.k Follow DisplayPort specification training sequence (see notes for
2712 * failure handling)
2713 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2714 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2715 * (timeout after 800 us)
2716 */
2717 intel_dp_start_link_train(state, intel_dp, crtc_state);
2718
2719 /* 6.n Set DP_TP_CTL link training to Normal */
2720 if (!is_trans_port_sync_mode(crtc_state))
2721 intel_dp_stop_link_train(intel_dp, crtc_state);
2722
2723 /* 6.o Configure and enable FEC if needed */
2724 intel_ddi_enable_fec(encoder, crtc_state);
2725
2726 /* 7.a 128b/132b SST. */
2727 if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2728 /* VCPID 1, start slot 0 for 128b/132b, tu slots */
2729 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
2730 if (ret < 0)
2731 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2732 }
2733
2734 if (!is_mst)
2735 intel_dsc_dp_pps_write(encoder, crtc_state);
2736 }
2737
tgl_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2738 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2739 struct intel_encoder *encoder,
2740 const struct intel_crtc_state *crtc_state,
2741 const struct drm_connector_state *conn_state)
2742 {
2743 struct intel_display *display = to_intel_display(encoder);
2744 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2745 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2746 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2747 int ret;
2748
2749 intel_dp_set_link_params(intel_dp,
2750 crtc_state->port_clock,
2751 crtc_state->lane_count);
2752
2753 /*
2754 * We only configure what the register value will be here. Actual
2755 * enabling happens during link training farther down.
2756 */
2757 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2758
2759 /*
2760 * 1. Enable Power Wells
2761 *
2762 * This was handled at the beginning of intel_atomic_commit_tail(),
2763 * before we called down into this function.
2764 */
2765
2766 /* 2. Enable Panel Power if PPS is required */
2767 intel_pps_on(intel_dp);
2768
2769 /*
2770 * 3. For non-TBT Type-C ports, set FIA lane count
2771 * (DFLEXDPSP.DPX4TXLATC)
2772 *
2773 * This was done before tgl_ddi_pre_enable_dp by
2774 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2775 */
2776
2777 /*
2778 * 4. Enable the port PLL.
2779 *
2780 * The PLL enabling itself was already done before this function by
2781 * hsw_crtc_enable()->intel_enable_dpll(). We need only
2782 * configure the PLL to port mapping here.
2783 */
2784 intel_ddi_enable_clock(encoder, crtc_state);
2785
2786 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2787 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2788 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2789 dig_port->ddi_io_wakeref = intel_display_power_get(display,
2790 dig_port->ddi_io_power_domain);
2791 }
2792
2793 /* 6. Program DP_MODE */
2794 icl_program_mg_dp_mode(dig_port, crtc_state);
2795
2796 /*
2797 * 7. The rest of the below are substeps under the bspec's "Enable and
2798 * Train Display Port" step. Note that steps that are specific to
2799 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2800 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2801 * us when active_mst_links==0, so any steps designated for "single
2802 * stream or multi-stream master transcoder" can just be performed
2803 * unconditionally here.
2804 */
2805
2806 /*
2807 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2808 * Transcoder.
2809 */
2810 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2811
2812 /*
2813 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2814 * Transport Select
2815 */
2816 intel_ddi_config_transcoder_func(encoder, crtc_state);
2817
2818 /*
2819 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2820 * selected
2821 *
2822 * This will be handled by the intel_dp_start_link_train() farther
2823 * down this function.
2824 */
2825
2826 /* 7.e Configure voltage swing and related IO settings */
2827 encoder->set_signal_levels(encoder, crtc_state);
2828
2829 /*
2830 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2831 * the used lanes of the DDI.
2832 */
2833 intel_ddi_power_up_lanes(encoder, crtc_state);
2834
2835 /*
2836 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2837 */
2838 intel_ddi_mso_configure(crtc_state);
2839
2840 if (!is_mst)
2841 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2842
2843 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2844 if (!is_mst)
2845 intel_dp_sink_enable_decompression(state,
2846 to_intel_connector(conn_state->connector),
2847 crtc_state);
2848 /*
2849 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2850 * in the FEC_CONFIGURATION register to 1 before initiating link
2851 * training
2852 */
2853 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
2854
2855 intel_dp_check_frl_training(intel_dp);
2856 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2857
2858 /*
2859 * 7.i Follow DisplayPort specification training sequence (see notes for
2860 * failure handling)
2861 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2862 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2863 * (timeout after 800 us)
2864 */
2865 intel_dp_start_link_train(state, intel_dp, crtc_state);
2866
2867 /* 7.k Set DP_TP_CTL link training to Normal */
2868 if (!is_trans_port_sync_mode(crtc_state))
2869 intel_dp_stop_link_train(intel_dp, crtc_state);
2870
2871 /* 7.l Configure and enable FEC if needed */
2872 intel_ddi_enable_fec(encoder, crtc_state);
2873
2874 if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2875 /* VCPID 1, start slot 0 for 128b/132b, tu slots */
2876 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
2877 if (ret < 0)
2878 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2879 }
2880
2881 if (!is_mst)
2882 intel_dsc_dp_pps_write(encoder, crtc_state);
2883 }
2884
hsw_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2885 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2886 struct intel_encoder *encoder,
2887 const struct intel_crtc_state *crtc_state,
2888 const struct drm_connector_state *conn_state)
2889 {
2890 struct intel_display *display = to_intel_display(encoder);
2891 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2892 enum port port = encoder->port;
2893 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2894 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2895
2896 if (DISPLAY_VER(display) < 11)
2897 drm_WARN_ON(display->drm,
2898 is_mst && (port == PORT_A || port == PORT_E));
2899 else
2900 drm_WARN_ON(display->drm, is_mst && port == PORT_A);
2901
2902 intel_dp_set_link_params(intel_dp,
2903 crtc_state->port_clock,
2904 crtc_state->lane_count);
2905
2906 /*
2907 * We only configure what the register value will be here. Actual
2908 * enabling happens during link training farther down.
2909 */
2910 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2911
2912 intel_pps_on(intel_dp);
2913
2914 intel_ddi_enable_clock(encoder, crtc_state);
2915
2916 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2917 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2918 dig_port->ddi_io_wakeref = intel_display_power_get(display,
2919 dig_port->ddi_io_power_domain);
2920 }
2921
2922 icl_program_mg_dp_mode(dig_port, crtc_state);
2923
2924 if (has_buf_trans_select(display))
2925 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2926
2927 encoder->set_signal_levels(encoder, crtc_state);
2928
2929 intel_ddi_power_up_lanes(encoder, crtc_state);
2930
2931 if (!is_mst)
2932 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2933 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2934 if (!is_mst)
2935 intel_dp_sink_enable_decompression(state,
2936 to_intel_connector(conn_state->connector),
2937 crtc_state);
2938 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
2939 intel_dp_start_link_train(state, intel_dp, crtc_state);
2940 if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&
2941 !is_trans_port_sync_mode(crtc_state))
2942 intel_dp_stop_link_train(intel_dp, crtc_state);
2943
2944 intel_ddi_enable_fec(encoder, crtc_state);
2945
2946 if (!is_mst) {
2947 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2948 intel_dsc_dp_pps_write(encoder, crtc_state);
2949 }
2950 }
2951
intel_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2952 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2953 struct intel_encoder *encoder,
2954 const struct intel_crtc_state *crtc_state,
2955 const struct drm_connector_state *conn_state)
2956 {
2957 struct intel_display *display = to_intel_display(encoder);
2958
2959 if (HAS_DP20(display))
2960 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
2961 crtc_state);
2962
2963 /* Panel replay has to be enabled in sink dpcd before link training. */
2964 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder));
2965
2966 if (DISPLAY_VER(display) >= 14)
2967 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2968 else if (DISPLAY_VER(display) >= 12)
2969 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2970 else
2971 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2972
2973 /* MST will call a setting of MSA after an allocating of Virtual Channel
2974 * from MST encoder pre_enable callback.
2975 */
2976 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2977 intel_ddi_set_dp_msa(crtc_state, conn_state);
2978 }
2979
intel_ddi_pre_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2980 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2981 struct intel_encoder *encoder,
2982 const struct intel_crtc_state *crtc_state,
2983 const struct drm_connector_state *conn_state)
2984 {
2985 struct intel_display *display = to_intel_display(encoder);
2986 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2987 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2988
2989 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2990 intel_ddi_enable_clock(encoder, crtc_state);
2991
2992 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2993 dig_port->ddi_io_wakeref = intel_display_power_get(display,
2994 dig_port->ddi_io_power_domain);
2995
2996 icl_program_mg_dp_mode(dig_port, crtc_state);
2997
2998 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2999
3000 dig_port->set_infoframes(encoder,
3001 crtc_state->has_infoframe,
3002 crtc_state, conn_state);
3003 }
3004
3005 /*
3006 * Note: Also called from the ->pre_enable of the first active MST stream
3007 * encoder on its primary encoder.
3008 *
3009 * When called from DP MST code:
3010 *
3011 * - conn_state will be NULL
3012 *
3013 * - encoder will be the primary encoder (i.e. mst->primary)
3014 *
3015 * - the main connector associated with this port won't be active or linked to a
3016 * crtc
3017 *
3018 * - crtc_state will be the state of the first stream to be activated on this
3019 * port, and it may not be the same stream that will be deactivated last, but
3020 * each stream should have a state that is identical when it comes to the DP
3021 * link parameters.
3022 */
intel_ddi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3023 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3024 struct intel_encoder *encoder,
3025 const struct intel_crtc_state *crtc_state,
3026 const struct drm_connector_state *conn_state)
3027 {
3028 struct intel_display *display = to_intel_display(state);
3029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3030 enum pipe pipe = crtc->pipe;
3031
3032 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);
3033
3034 intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
3035
3036 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3037 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3038 conn_state);
3039 } else {
3040 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3041
3042 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3043 conn_state);
3044
3045 /* FIXME precompute everything properly */
3046 /* FIXME how do we turn infoframes off again? */
3047 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp))
3048 dig_port->set_infoframes(encoder,
3049 crtc_state->has_infoframe,
3050 crtc_state, conn_state);
3051 }
3052 }
3053
3054 static void
mtl_ddi_disable_d2d(struct intel_encoder * encoder)3055 mtl_ddi_disable_d2d(struct intel_encoder *encoder)
3056 {
3057 struct intel_display *display = to_intel_display(encoder);
3058 enum port port = encoder->port;
3059 intel_reg_t reg;
3060 u32 clr_bits, wait_bits;
3061 int ret;
3062
3063 if (DISPLAY_VER(display) < 14)
3064 return;
3065
3066 if (DISPLAY_VER(display) >= 20) {
3067 reg = DDI_BUF_CTL(port);
3068 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3069 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
3070 } else {
3071 reg = XELPDP_PORT_BUF_CTL1(display, port);
3072 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
3073 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
3074 }
3075
3076 intel_de_rmw(display, reg, clr_bits, 0);
3077
3078 ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100);
3079 if (ret)
3080 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
3081 port_name(port));
3082 }
3083
intel_ddi_buf_enable(struct intel_encoder * encoder,u32 buf_ctl)3084 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl)
3085 {
3086 struct intel_display *display = to_intel_display(encoder);
3087 enum port port = encoder->port;
3088
3089 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);
3090 intel_de_posting_read(display, DDI_BUF_CTL(port));
3091
3092 intel_wait_ddi_buf_active(encoder);
3093 }
3094
intel_ddi_buf_disable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3095 static void intel_ddi_buf_disable(struct intel_encoder *encoder,
3096 const struct intel_crtc_state *crtc_state)
3097 {
3098 struct intel_display *display = to_intel_display(encoder);
3099 enum port port = encoder->port;
3100
3101 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
3102
3103 if (DISPLAY_VER(display) >= 14)
3104 intel_wait_ddi_buf_idle(display, port);
3105
3106 mtl_ddi_disable_d2d(encoder);
3107
3108 if (intel_crtc_has_dp_encoder(crtc_state)) {
3109 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
3110 DP_TP_CTL_ENABLE, 0);
3111 }
3112
3113 intel_ddi_disable_fec(encoder, crtc_state);
3114
3115 if (DISPLAY_VER(display) < 14)
3116 intel_wait_ddi_buf_idle(display, port);
3117
3118 intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
3119 }
3120
intel_ddi_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3121 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3122 struct intel_encoder *encoder,
3123 const struct intel_crtc_state *old_crtc_state,
3124 const struct drm_connector_state *old_conn_state)
3125 {
3126 struct intel_display *display = to_intel_display(encoder);
3127 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3128 struct intel_dp *intel_dp = &dig_port->dp;
3129 struct ref_tracker *wakeref;
3130 bool is_mst = intel_crtc_has_type(old_crtc_state,
3131 INTEL_OUTPUT_DP_MST);
3132
3133 if (!is_mst)
3134 intel_dp_set_infoframes(encoder, false,
3135 old_crtc_state, old_conn_state);
3136
3137 /*
3138 * Power down sink before disabling the port, otherwise we end
3139 * up getting interrupts from the sink on detecting link loss.
3140 */
3141 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3142
3143 if (DISPLAY_VER(display) >= 12) {
3144 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) {
3145 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3146
3147 intel_de_rmw(display,
3148 TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
3149 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
3150 0);
3151 }
3152 } else {
3153 if (!is_mst)
3154 intel_ddi_disable_transcoder_clock(old_crtc_state);
3155 }
3156
3157 intel_ddi_buf_disable(encoder, old_crtc_state);
3158
3159 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
3160
3161 intel_ddi_config_transcoder_dp2(old_crtc_state, false);
3162
3163 /*
3164 * From TGL spec: "If single stream or multi-stream master transcoder:
3165 * Configure Transcoder Clock select to direct no clock to the
3166 * transcoder"
3167 */
3168 if (DISPLAY_VER(display) >= 12)
3169 intel_ddi_disable_transcoder_clock(old_crtc_state);
3170
3171 intel_pps_vdd_on(intel_dp);
3172 intel_pps_off(intel_dp);
3173
3174 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3175
3176 if (wakeref)
3177 intel_display_power_put(display,
3178 dig_port->ddi_io_power_domain,
3179 wakeref);
3180
3181 intel_ddi_disable_clock(encoder);
3182
3183 /* De-select Thunderbolt */
3184 if (DISPLAY_VER(display) >= 14)
3185 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
3186 XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
3187 }
3188
intel_ddi_post_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3189 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3190 struct intel_encoder *encoder,
3191 const struct intel_crtc_state *old_crtc_state,
3192 const struct drm_connector_state *old_conn_state)
3193 {
3194 struct intel_display *display = to_intel_display(encoder);
3195 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3196 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3197 struct ref_tracker *wakeref;
3198
3199 dig_port->set_infoframes(encoder, false,
3200 old_crtc_state, old_conn_state);
3201
3202 if (DISPLAY_VER(display) < 12)
3203 intel_ddi_disable_transcoder_clock(old_crtc_state);
3204
3205 intel_ddi_buf_disable(encoder, old_crtc_state);
3206
3207 if (DISPLAY_VER(display) >= 12)
3208 intel_ddi_disable_transcoder_clock(old_crtc_state);
3209
3210 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3211 if (wakeref)
3212 intel_display_power_put(display,
3213 dig_port->ddi_io_power_domain,
3214 wakeref);
3215
3216 intel_ddi_disable_clock(encoder);
3217
3218 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3219 }
3220
intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3221 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
3222 struct intel_encoder *encoder,
3223 const struct intel_crtc_state *old_crtc_state,
3224 const struct drm_connector_state *old_conn_state)
3225 {
3226 struct intel_display *display = to_intel_display(encoder);
3227 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3228 struct intel_crtc *pipe_crtc;
3229 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI);
3230
3231 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
3232 const struct intel_crtc_state *old_pipe_crtc_state =
3233 intel_atomic_get_old_crtc_state(state, pipe_crtc);
3234
3235 intel_crtc_vblank_off(old_pipe_crtc_state);
3236 }
3237
3238 intel_disable_transcoder(old_crtc_state);
3239
3240 /* 128b/132b SST */
3241 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) {
3242 /* VCPID 1, start slot 0 for 128b/132b, clear */
3243 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0);
3244
3245 intel_ddi_clear_act_sent(encoder, old_crtc_state);
3246
3247 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
3248 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
3249
3250 intel_ddi_wait_for_act_sent(encoder, old_crtc_state);
3251 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
3252 }
3253
3254 intel_vrr_transcoder_disable(old_crtc_state);
3255
3256 intel_ddi_disable_transcoder_func(old_crtc_state);
3257
3258 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
3259 const struct intel_crtc_state *old_pipe_crtc_state =
3260 intel_atomic_get_old_crtc_state(state, pipe_crtc);
3261
3262 intel_dsc_disable(old_pipe_crtc_state);
3263
3264 if (DISPLAY_VER(display) >= 9)
3265 skl_scaler_disable(old_pipe_crtc_state);
3266 else
3267 ilk_pfit_disable(old_pipe_crtc_state);
3268 }
3269 }
3270
3271 /*
3272 * Note: Also called from the ->post_disable of the last active MST stream
3273 * encoder on its primary encoder. See also the comment for
3274 * intel_ddi_pre_enable().
3275 */
intel_ddi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3276 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3277 struct intel_encoder *encoder,
3278 const struct intel_crtc_state *old_crtc_state,
3279 const struct drm_connector_state *old_conn_state)
3280 {
3281 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
3282 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state,
3283 old_conn_state);
3284
3285 /*
3286 * When called from DP MST code:
3287 * - old_conn_state will be NULL
3288 * - encoder will be the main encoder (ie. mst->primary)
3289 * - the main connector associated with this port
3290 * won't be active or linked to a crtc
3291 * - old_crtc_state will be the state of the last stream to
3292 * be deactivated on this port, and it may not be the same
3293 * stream that was activated last, but each stream
3294 * should have a state that is identical when it comes to
3295 * the DP link parameters
3296 */
3297
3298 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3299 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3300 old_conn_state);
3301 else
3302 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3303 old_conn_state);
3304 }
3305
3306 /*
3307 * Note: Also called from the ->post_pll_disable of the last active MST stream
3308 * encoder on its primary encoder. See also the comment for
3309 * intel_ddi_pre_enable().
3310 */
intel_ddi_post_pll_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3311 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
3312 struct intel_encoder *encoder,
3313 const struct intel_crtc_state *old_crtc_state,
3314 const struct drm_connector_state *old_conn_state)
3315 {
3316 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3317
3318 main_link_aux_power_domain_put(dig_port, old_crtc_state);
3319
3320 if (intel_encoder_is_tc(encoder))
3321 intel_tc_port_put_link(dig_port);
3322 }
3323
trans_port_sync_stop_link_train(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3324 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3325 struct intel_encoder *encoder,
3326 const struct intel_crtc_state *crtc_state)
3327 {
3328 const struct drm_connector_state *conn_state;
3329 struct drm_connector *conn;
3330 int i;
3331
3332 if (!crtc_state->sync_mode_slaves_mask)
3333 return;
3334
3335 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3336 struct intel_encoder *slave_encoder =
3337 to_intel_encoder(conn_state->best_encoder);
3338 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3339 const struct intel_crtc_state *slave_crtc_state;
3340
3341 if (!slave_crtc)
3342 continue;
3343
3344 slave_crtc_state =
3345 intel_atomic_get_new_crtc_state(state, slave_crtc);
3346
3347 if (slave_crtc_state->master_transcoder !=
3348 crtc_state->cpu_transcoder)
3349 continue;
3350
3351 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
3352 slave_crtc_state);
3353 }
3354
3355 usleep_range(200, 400);
3356
3357 intel_dp_stop_link_train(enc_to_intel_dp(encoder),
3358 crtc_state);
3359 }
3360
intel_ddi_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3361 static void intel_ddi_enable_dp(struct intel_atomic_state *state,
3362 struct intel_encoder *encoder,
3363 const struct intel_crtc_state *crtc_state,
3364 const struct drm_connector_state *conn_state)
3365 {
3366 struct intel_display *display = to_intel_display(encoder);
3367 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3368 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3369 enum port port = encoder->port;
3370
3371 if (port == PORT_A && DISPLAY_VER(display) < 9)
3372 intel_dp_stop_link_train(intel_dp, crtc_state);
3373
3374 drm_connector_update_privacy_screen(conn_state);
3375 intel_edp_backlight_on(crtc_state, conn_state);
3376
3377 intel_panel_prepare(crtc_state, conn_state);
3378
3379 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp))
3380 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3381
3382 trans_port_sync_stop_link_train(state, encoder, crtc_state);
3383 }
3384
3385 static intel_reg_t
gen9_chicken_trans_reg_by_port(struct intel_display * display,enum port port)3386 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)
3387 {
3388 static const enum transcoder trans[] = {
3389 [PORT_A] = TRANSCODER_EDP,
3390 [PORT_B] = TRANSCODER_A,
3391 [PORT_C] = TRANSCODER_B,
3392 [PORT_D] = TRANSCODER_C,
3393 [PORT_E] = TRANSCODER_A,
3394 };
3395
3396 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);
3397
3398 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))
3399 port = PORT_A;
3400
3401 return CHICKEN_TRANS(display, trans[port]);
3402 }
3403
intel_ddi_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3404 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
3405 struct intel_encoder *encoder,
3406 const struct intel_crtc_state *crtc_state,
3407 const struct drm_connector_state *conn_state)
3408 {
3409 struct intel_display *display = to_intel_display(encoder);
3410 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3411 struct drm_connector *connector = conn_state->connector;
3412 enum port port = encoder->port;
3413 u32 buf_ctl = 0;
3414
3415 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3416 crtc_state->hdmi_high_tmds_clock_ratio,
3417 crtc_state->hdmi_scrambling))
3418 drm_dbg_kms(display->drm,
3419 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3420 connector->base.id, connector->name);
3421
3422 if (has_buf_trans_select(display))
3423 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3424
3425 /* e. Enable D2D Link for C10/C20 Phy */
3426 mtl_ddi_enable_d2d(encoder);
3427
3428 encoder->set_signal_levels(encoder, crtc_state);
3429
3430 /* Display WA #1143: skl,kbl,cfl */
3431 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
3432 /*
3433 * For some reason these chicken bits have been
3434 * stuffed into a transcoder register, event though
3435 * the bits affect a specific DDI port rather than
3436 * a specific transcoder.
3437 */
3438 intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
3439 u32 val;
3440
3441 val = intel_de_read(display, reg);
3442
3443 if (port == PORT_E)
3444 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3445 DDIE_TRAINING_OVERRIDE_VALUE;
3446 else
3447 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3448 DDI_TRAINING_OVERRIDE_VALUE;
3449
3450 intel_de_write(display, reg, val);
3451 intel_de_posting_read(display, reg);
3452
3453 udelay(1);
3454
3455 if (port == PORT_E)
3456 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3457 DDIE_TRAINING_OVERRIDE_VALUE);
3458 else
3459 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3460 DDI_TRAINING_OVERRIDE_VALUE);
3461
3462 intel_de_write(display, reg, val);
3463 }
3464
3465 intel_ddi_power_up_lanes(encoder, crtc_state);
3466
3467 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3468 * are ignored so nothing special needs to be done besides
3469 * enabling the port.
3470 *
3471 * On ADL_P the PHY link rate and lane count must be programmed but
3472 * these are both 0 for HDMI.
3473 *
3474 * But MTL onwards HDMI2.1 is supported and in TMDS mode this
3475 * is filled with lane count, already set in the crtc_state.
3476 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
3477 */
3478 if (dig_port->lane_reversal)
3479 buf_ctl |= DDI_BUF_PORT_REVERSAL;
3480 if (dig_port->ddi_a_4_lanes)
3481 buf_ctl |= DDI_A_4_LANES;
3482
3483 if (DISPLAY_VER(display) >= 14) {
3484 u32 port_buf = 0;
3485
3486 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
3487
3488 if (dig_port->lane_reversal)
3489 port_buf |= XELPDP_PORT_REVERSAL;
3490
3491 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
3492 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
3493
3494 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
3495
3496 if (DISPLAY_VER(display) >= 20)
3497 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3498 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
3499 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port));
3500 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
3501 }
3502
3503 intel_ddi_buf_enable(encoder, buf_ctl);
3504 }
3505
intel_ddi_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3506 static void intel_ddi_enable(struct intel_atomic_state *state,
3507 struct intel_encoder *encoder,
3508 const struct intel_crtc_state *crtc_state,
3509 const struct drm_connector_state *conn_state)
3510 {
3511 struct intel_display *display = to_intel_display(encoder);
3512 struct intel_crtc *pipe_crtc;
3513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3514 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
3515
3516 /* 128b/132b SST */
3517 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3518 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3519 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
3520
3521 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
3522 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
3523 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
3524 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
3525 }
3526
3527 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3528
3529 intel_vrr_transcoder_enable(crtc_state);
3530
3531 /* 128b/132b SST */
3532 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3533 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3534
3535 intel_ddi_clear_act_sent(encoder, crtc_state);
3536
3537 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
3538 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
3539
3540 intel_ddi_wait_for_act_sent(encoder, crtc_state);
3541 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
3542 }
3543
3544 intel_enable_transcoder(crtc_state);
3545
3546 intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
3547
3548 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
3549 const struct intel_crtc_state *pipe_crtc_state =
3550 intel_atomic_get_new_crtc_state(state, pipe_crtc);
3551
3552 intel_crtc_vblank_on(pipe_crtc_state);
3553 }
3554
3555 if (is_hdmi)
3556 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
3557 else
3558 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
3559
3560 intel_hdcp_enable(state, encoder, crtc_state, conn_state);
3561
3562 }
3563
intel_ddi_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3564 static void intel_ddi_disable_dp(struct intel_atomic_state *state,
3565 struct intel_encoder *encoder,
3566 const struct intel_crtc_state *old_crtc_state,
3567 const struct drm_connector_state *old_conn_state)
3568 {
3569 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3570 struct intel_connector *connector =
3571 to_intel_connector(old_conn_state->connector);
3572
3573 intel_dp->link.active = false;
3574
3575 intel_panel_unprepare(old_conn_state);
3576 intel_psr_disable(intel_dp, old_crtc_state);
3577 intel_alpm_disable(intel_dp);
3578 intel_edp_backlight_off(old_conn_state);
3579 /* Disable the decompression in DP Sink */
3580 intel_dp_sink_disable_decompression(state,
3581 connector, old_crtc_state);
3582 /* Disable Ignore_MSA bit in DP Sink */
3583 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3584 false);
3585 }
3586
intel_ddi_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3587 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state,
3588 struct intel_encoder *encoder,
3589 const struct intel_crtc_state *old_crtc_state,
3590 const struct drm_connector_state *old_conn_state)
3591 {
3592 struct intel_display *display = to_intel_display(encoder);
3593 struct drm_connector *connector = old_conn_state->connector;
3594
3595 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3596 false, false))
3597 drm_dbg_kms(display->drm,
3598 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3599 connector->base.id, connector->name);
3600 }
3601
intel_ddi_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3602 static void intel_ddi_disable(struct intel_atomic_state *state,
3603 struct intel_encoder *encoder,
3604 const struct intel_crtc_state *old_crtc_state,
3605 const struct drm_connector_state *old_conn_state)
3606 {
3607 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder));
3608
3609 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3610
3611 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3612 intel_ddi_disable_hdmi(state, encoder, old_crtc_state,
3613 old_conn_state);
3614 else
3615 intel_ddi_disable_dp(state, encoder, old_crtc_state,
3616 old_conn_state);
3617 }
3618
intel_ddi_update_pipe_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3619 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3620 struct intel_encoder *encoder,
3621 const struct intel_crtc_state *crtc_state,
3622 const struct drm_connector_state *conn_state)
3623 {
3624 intel_ddi_set_dp_msa(crtc_state, conn_state);
3625
3626 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3627
3628 intel_backlight_update(state, encoder, crtc_state, conn_state);
3629 drm_connector_update_privacy_screen(conn_state);
3630 }
3631
intel_ddi_update_pipe_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3632 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder,
3633 const struct intel_crtc_state *crtc_state,
3634 const struct drm_connector_state *conn_state)
3635 {
3636 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);
3637 }
3638
intel_ddi_update_pipe(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3639 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3640 struct intel_encoder *encoder,
3641 const struct intel_crtc_state *crtc_state,
3642 const struct drm_connector_state *conn_state)
3643 {
3644
3645 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3646 !intel_encoder_is_mst(encoder))
3647 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3648 conn_state);
3649
3650 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3651 intel_ddi_update_pipe_hdmi(encoder, crtc_state,
3652 conn_state);
3653
3654 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3655 }
3656
intel_ddi_update_active_dpll(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)3657 void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3658 struct intel_encoder *encoder,
3659 struct intel_crtc *crtc)
3660 {
3661 struct intel_display *display = to_intel_display(encoder);
3662 const struct intel_crtc_state *crtc_state =
3663 intel_atomic_get_new_crtc_state(state, crtc);
3664 struct intel_crtc *pipe_crtc;
3665
3666 /* FIXME: Add NVL+ and DG2 pll_mgr */
3667 if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)
3668 return;
3669
3670 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc,
3671 intel_crtc_joined_pipe_mask(crtc_state))
3672 intel_dpll_update_active(state, pipe_crtc, encoder);
3673 }
3674
3675 /*
3676 * Note: Also called from the ->pre_pll_enable of the first active MST stream
3677 * encoder on its primary encoder. See also the comment for
3678 * intel_ddi_pre_enable().
3679 */
3680 static void
intel_ddi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3681 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3682 struct intel_encoder *encoder,
3683 const struct intel_crtc_state *crtc_state,
3684 const struct drm_connector_state *conn_state)
3685 {
3686 struct intel_display *display = to_intel_display(encoder);
3687 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3688 bool is_tc_port = intel_encoder_is_tc(encoder);
3689
3690 if (is_tc_port) {
3691 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3692
3693 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3694 intel_ddi_update_active_dpll(state, encoder, crtc);
3695 }
3696
3697 main_link_aux_power_domain_get(dig_port, crtc_state);
3698
3699 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3700 /*
3701 * Program the lane count for static/dynamic connections on
3702 * Type-C ports. Skip this step for TBT.
3703 */
3704 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3705 else if (display->platform.geminilake || display->platform.broxton)
3706 bxt_dpio_phy_set_lane_optim_mask(encoder,
3707 crtc_state->lane_lat_optim_mask);
3708
3709 /*
3710 * There is no direct connection between the PLL and PPS, however
3711 * enabling PPS before PLL is required to avoid PLL/DDI BUF timeouts
3712 * during system resume. Do that matching the Bspec order as well.
3713 */
3714 if (DISPLAY_VER(display) >= 14)
3715 intel_pps_on(&dig_port->dp);
3716 }
3717
adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder * encoder)3718 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3719 {
3720 struct intel_display *display = to_intel_display(encoder);
3721 enum tc_port tc_port = intel_encoder_to_tc(encoder);
3722 int ln;
3723
3724 for (ln = 0; ln < 2; ln++)
3725 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
3726 DKL_PCS_DW5_CORE_SOFTRESET, 0);
3727 }
3728
mtl_ddi_prepare_link_retrain(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3729 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3730 const struct intel_crtc_state *crtc_state)
3731 {
3732 struct intel_display *display = to_intel_display(crtc_state);
3733 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3734 struct intel_encoder *encoder = &dig_port->base;
3735 u32 dp_tp_ctl;
3736
3737 /*
3738 * TODO: To train with only a different voltage swing entry is not
3739 * necessary disable and enable port
3740 */
3741 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3742
3743 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
3744
3745 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3746 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3747 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
3748 intel_dp_is_uhbr(crtc_state)) {
3749 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3750 } else {
3751 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3752 if (crtc_state->enhanced_framing)
3753 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3754 }
3755 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3756 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3757
3758 /* 6.f Enable D2D Link */
3759 mtl_ddi_enable_d2d(encoder);
3760
3761 /* 6.g Configure voltage swing and related IO settings */
3762 encoder->set_signal_levels(encoder, crtc_state);
3763
3764 /* 6.h Configure PORT_BUF_CTL1 */
3765 mtl_port_buf_ctl_program(encoder, crtc_state);
3766
3767 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3768 if (DISPLAY_VER(display) >= 20)
3769 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3770
3771 intel_ddi_buf_enable(encoder, intel_dp->DP);
3772 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3773
3774 /*
3775 * 6.k If AUX-Less ALPM is going to be enabled:
3776 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
3777 */
3778 intel_alpm_port_configure(intel_dp, crtc_state);
3779
3780 /*
3781 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
3782 * register
3783 */
3784 intel_lnl_mac_transmit_lfps(encoder, crtc_state);
3785 }
3786
intel_ddi_prepare_link_retrain(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3787 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3788 const struct intel_crtc_state *crtc_state)
3789 {
3790 struct intel_display *display = to_intel_display(intel_dp);
3791 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3792 struct intel_encoder *encoder = &dig_port->base;
3793 u32 dp_tp_ctl;
3794
3795 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3796
3797 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
3798
3799 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3800 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
3801 intel_dp_is_uhbr(crtc_state)) {
3802 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3803 } else {
3804 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3805 if (crtc_state->enhanced_framing)
3806 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3807 }
3808 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3809 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3810
3811 if (display->platform.alderlake_p &&
3812 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3813 adlp_tbt_to_dp_alt_switch_wa(encoder);
3814
3815 intel_ddi_buf_enable(encoder, intel_dp->DP);
3816 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3817 }
3818
intel_ddi_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)3819 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3820 const struct intel_crtc_state *crtc_state,
3821 u8 dp_train_pat)
3822 {
3823 struct intel_display *display = to_intel_display(intel_dp);
3824 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3825 u32 temp;
3826
3827 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
3828
3829 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3830 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3831 case DP_TRAINING_PATTERN_DISABLE:
3832 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3833 break;
3834 case DP_TRAINING_PATTERN_1:
3835 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3836 break;
3837 case DP_TRAINING_PATTERN_2:
3838 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3839 break;
3840 case DP_TRAINING_PATTERN_3:
3841 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3842 break;
3843 case DP_TRAINING_PATTERN_4:
3844 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3845 break;
3846 }
3847
3848 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);
3849 }
3850
intel_ddi_set_idle_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3851 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3852 const struct intel_crtc_state *crtc_state)
3853 {
3854 struct intel_display *display = to_intel_display(intel_dp);
3855 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3856 enum port port = encoder->port;
3857
3858 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
3859 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3860
3861 /*
3862 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3863 * reason we need to set idle transmission mode is to work around a HW
3864 * issue where we enable the pipe while not in idle link-training mode.
3865 * In this case there is requirement to wait for a minimum number of
3866 * idle patterns to be sent.
3867 */
3868 if (port == PORT_A && DISPLAY_VER(display) < 12)
3869 return;
3870
3871 if (intel_de_wait_for_set_ms(display,
3872 dp_tp_status_reg(encoder, crtc_state),
3873 DP_TP_STATUS_IDLE_DONE, 2))
3874 drm_err(display->drm,
3875 "Timed out waiting for DP idle patterns\n");
3876 }
3877
intel_ddi_is_audio_enabled(struct intel_display * display,enum transcoder cpu_transcoder)3878 static bool intel_ddi_is_audio_enabled(struct intel_display *display,
3879 enum transcoder cpu_transcoder)
3880 {
3881 if (cpu_transcoder == TRANSCODER_EDP)
3882 return false;
3883
3884 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO))
3885 return false;
3886
3887 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &
3888 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3889 }
3890
tgl_ddi_min_voltage_level(const struct intel_crtc_state * crtc_state)3891 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3892 {
3893 if (crtc_state->port_clock > 594000)
3894 return 2;
3895 else
3896 return 0;
3897 }
3898
jsl_ddi_min_voltage_level(const struct intel_crtc_state * crtc_state)3899 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3900 {
3901 if (crtc_state->port_clock > 594000)
3902 return 3;
3903 else
3904 return 0;
3905 }
3906
icl_ddi_min_voltage_level(const struct intel_crtc_state * crtc_state)3907 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3908 {
3909 if (crtc_state->port_clock > 594000)
3910 return 1;
3911 else
3912 return 0;
3913 }
3914
intel_ddi_compute_min_voltage_level(struct intel_crtc_state * crtc_state)3915 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)
3916 {
3917 struct intel_display *display = to_intel_display(crtc_state);
3918
3919 if (DISPLAY_VER(display) >= 14)
3920 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3921 else if (DISPLAY_VER(display) >= 12)
3922 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);
3923 else if (display->platform.jasperlake || display->platform.elkhartlake)
3924 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);
3925 else if (DISPLAY_VER(display) >= 11)
3926 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3927 }
3928
bdw_transcoder_master_readout(struct intel_display * display,enum transcoder cpu_transcoder)3929 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display,
3930 enum transcoder cpu_transcoder)
3931 {
3932 u32 master_select;
3933
3934 if (DISPLAY_VER(display) >= 11) {
3935 u32 ctl2 = intel_de_read(display,
3936 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder));
3937
3938 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3939 return INVALID_TRANSCODER;
3940
3941 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3942 } else {
3943 u32 ctl = intel_de_read(display,
3944 TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3945
3946 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3947 return INVALID_TRANSCODER;
3948
3949 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3950 }
3951
3952 if (master_select == 0)
3953 return TRANSCODER_EDP;
3954 else
3955 return master_select - 1;
3956 }
3957
bdw_get_trans_port_sync_config(struct intel_crtc_state * crtc_state)3958 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3959 {
3960 struct intel_display *display = to_intel_display(crtc_state);
3961 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3962 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3963 enum transcoder cpu_transcoder;
3964
3965 crtc_state->master_transcoder =
3966 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder);
3967
3968 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) {
3969 enum intel_display_power_domain power_domain;
3970 struct ref_tracker *trans_wakeref;
3971
3972 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3973 trans_wakeref = intel_display_power_get_if_enabled(display,
3974 power_domain);
3975
3976 if (!trans_wakeref)
3977 continue;
3978
3979 if (bdw_transcoder_master_readout(display, cpu_transcoder) ==
3980 crtc_state->cpu_transcoder)
3981 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3982
3983 intel_display_power_put(display, power_domain, trans_wakeref);
3984 }
3985
3986 drm_WARN_ON(display->drm,
3987 crtc_state->master_transcoder != INVALID_TRANSCODER &&
3988 crtc_state->sync_mode_slaves_mask);
3989 }
3990
intel_ddi_read_func_ctl_dvi(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,u32 ddi_func_ctl)3991 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder,
3992 struct intel_crtc_state *crtc_state,
3993 u32 ddi_func_ctl)
3994 {
3995 struct intel_display *display = to_intel_display(encoder);
3996
3997 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
3998 if (DISPLAY_VER(display) >= 14)
3999 crtc_state->lane_count =
4000 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4001 else
4002 crtc_state->lane_count = 4;
4003 }
4004
intel_ddi_read_func_ctl_hdmi(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,u32 ddi_func_ctl)4005 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder,
4006 struct intel_crtc_state *crtc_state,
4007 u32 ddi_func_ctl)
4008 {
4009 crtc_state->has_hdmi_sink = true;
4010
4011 crtc_state->infoframes.enable |=
4012 intel_hdmi_infoframes_enabled(encoder, crtc_state);
4013
4014 if (crtc_state->infoframes.enable)
4015 crtc_state->has_infoframe = true;
4016
4017 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
4018 crtc_state->hdmi_scrambling = true;
4019 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4020 crtc_state->hdmi_high_tmds_clock_ratio = true;
4021
4022 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);
4023 }
4024
intel_ddi_read_func_ctl_fdi(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,u32 ddi_func_ctl)4025 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder,
4026 struct intel_crtc_state *crtc_state,
4027 u32 ddi_func_ctl)
4028 {
4029 struct intel_display *display = to_intel_display(encoder);
4030
4031 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4032 crtc_state->enhanced_framing =
4033 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
4034 DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4035 }
4036
intel_ddi_read_func_ctl_dp_sst(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,u32 ddi_func_ctl)4037 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
4038 struct intel_crtc_state *crtc_state,
4039 u32 ddi_func_ctl)
4040 {
4041 struct intel_display *display = to_intel_display(encoder);
4042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4043 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4045
4046 if (encoder->type == INTEL_OUTPUT_EDP)
4047 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
4048 else
4049 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
4050 crtc_state->lane_count =
4051 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4052
4053 if (DISPLAY_VER(display) >= 12 &&
4054 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)
4055 crtc_state->mst_master_transcoder =
4056 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
4057
4058 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
4059 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
4060
4061 crtc_state->enhanced_framing =
4062 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
4063 DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4064
4065 if (DISPLAY_VER(display) >= 11)
4066 crtc_state->fec_enable =
4067 intel_de_read(display,
4068 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
4069
4070 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp))
4071 crtc_state->infoframes.enable |=
4072 intel_lspcon_infoframes_enabled(encoder, crtc_state);
4073 else
4074 crtc_state->infoframes.enable |=
4075 intel_hdmi_infoframes_enabled(encoder, crtc_state);
4076 }
4077
intel_ddi_read_func_ctl_dp_mst(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,u32 ddi_func_ctl)4078 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
4079 struct intel_crtc_state *crtc_state,
4080 u32 ddi_func_ctl)
4081 {
4082 struct intel_display *display = to_intel_display(encoder);
4083 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4084 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4085
4086 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4087 crtc_state->lane_count =
4088 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4089
4090 if (DISPLAY_VER(display) >= 12)
4091 crtc_state->mst_master_transcoder =
4092 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
4093
4094 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
4095
4096 if (DISPLAY_VER(display) >= 11)
4097 crtc_state->fec_enable =
4098 intel_de_read(display,
4099 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
4100
4101 crtc_state->infoframes.enable |=
4102 intel_hdmi_infoframes_enabled(encoder, crtc_state);
4103 }
4104
intel_ddi_read_func_ctl(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)4105 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
4106 struct intel_crtc_state *pipe_config)
4107 {
4108 struct intel_display *display = to_intel_display(encoder);
4109 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4110 u32 ddi_func_ctl, ddi_mode, flags = 0;
4111
4112 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
4113 if (ddi_func_ctl & TRANS_DDI_PHSYNC)
4114 flags |= DRM_MODE_FLAG_PHSYNC;
4115 else
4116 flags |= DRM_MODE_FLAG_NHSYNC;
4117 if (ddi_func_ctl & TRANS_DDI_PVSYNC)
4118 flags |= DRM_MODE_FLAG_PVSYNC;
4119 else
4120 flags |= DRM_MODE_FLAG_NVSYNC;
4121
4122 pipe_config->hw.adjusted_mode.flags |= flags;
4123
4124 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) {
4125 case TRANS_DDI_BPC_6:
4126 pipe_config->pipe_bpp = 18;
4127 break;
4128 case TRANS_DDI_BPC_8:
4129 pipe_config->pipe_bpp = 24;
4130 break;
4131 case TRANS_DDI_BPC_10:
4132 pipe_config->pipe_bpp = 30;
4133 break;
4134 case TRANS_DDI_BPC_12:
4135 pipe_config->pipe_bpp = 36;
4136 break;
4137 default:
4138 break;
4139 }
4140
4141 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK;
4142
4143 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) {
4144 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl);
4145 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
4146 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl);
4147 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
4148 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl);
4149 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
4150 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
4151 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
4152 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
4153 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
4154 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4155
4156 /*
4157 * If this is true, we know we're being called from mst stream
4158 * encoder's ->get_config().
4159 */
4160 if (intel_dp_mst_active_streams(intel_dp))
4161 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
4162 else
4163 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
4164 }
4165 }
4166
4167 /*
4168 * Note: Also called from the ->get_config of the MST stream encoders on their
4169 * primary encoder, via the platform specific hooks here. See also the comment
4170 * for intel_ddi_pre_enable().
4171 */
intel_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)4172 static void intel_ddi_get_config(struct intel_encoder *encoder,
4173 struct intel_crtc_state *pipe_config)
4174 {
4175 struct intel_display *display = to_intel_display(encoder);
4176 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4177
4178 /* XXX: DSI transcoder paranoia */
4179 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)))
4180 return;
4181
4182 intel_ddi_read_func_ctl(encoder, pipe_config);
4183
4184 intel_ddi_mso_get_config(encoder, pipe_config);
4185
4186 pipe_config->has_audio =
4187 intel_ddi_is_audio_enabled(display, cpu_transcoder);
4188
4189 if (encoder->type == INTEL_OUTPUT_EDP)
4190 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
4191
4192 ddi_dotclock_get(pipe_config);
4193
4194 if (display->platform.geminilake || display->platform.broxton)
4195 pipe_config->lane_lat_optim_mask =
4196 bxt_dpio_phy_get_lane_lat_optim_mask(encoder);
4197
4198 intel_ddi_compute_min_voltage_level(pipe_config);
4199
4200 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4201
4202 intel_read_infoframe(encoder, pipe_config,
4203 HDMI_INFOFRAME_TYPE_AVI,
4204 &pipe_config->infoframes.avi);
4205 intel_read_infoframe(encoder, pipe_config,
4206 HDMI_INFOFRAME_TYPE_SPD,
4207 &pipe_config->infoframes.spd);
4208 intel_read_infoframe(encoder, pipe_config,
4209 HDMI_INFOFRAME_TYPE_VENDOR,
4210 &pipe_config->infoframes.hdmi);
4211 intel_read_infoframe(encoder, pipe_config,
4212 HDMI_INFOFRAME_TYPE_DRM,
4213 &pipe_config->infoframes.drm);
4214
4215 if (DISPLAY_VER(display) >= 8)
4216 bdw_get_trans_port_sync_config(pipe_config);
4217
4218 intel_psr_get_config(encoder, pipe_config);
4219
4220 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4221 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4222 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
4223
4224 intel_audio_codec_get_config(encoder, pipe_config);
4225 }
4226
intel_ddi_get_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct intel_dpll * pll)4227 void intel_ddi_get_clock(struct intel_encoder *encoder,
4228 struct intel_crtc_state *crtc_state,
4229 struct intel_dpll *pll)
4230 {
4231 struct intel_display *display = to_intel_display(encoder);
4232 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4233 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4234 bool pll_active;
4235
4236 if (drm_WARN_ON(display->drm, !pll))
4237 return;
4238
4239 port_dpll->pll = pll;
4240 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
4241 drm_WARN_ON(display->drm, !pll_active);
4242
4243 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4244
4245 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
4246 &crtc_state->dpll_hw_state);
4247 }
4248
icl_ddi_tc_pll_is_tbt(const struct intel_dpll * pll)4249 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
4250 {
4251 return pll->info->id == DPLL_ID_ICL_TBTPLL;
4252 }
4253
mtl_ddi_cx0_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,enum icl_port_dpll_id port_dpll_id,enum intel_dpll_id pll_id)4254 static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
4255 struct intel_crtc_state *crtc_state,
4256 enum icl_port_dpll_id port_dpll_id,
4257 enum intel_dpll_id pll_id)
4258 {
4259 struct intel_display *display = to_intel_display(encoder);
4260 struct icl_port_dpll *port_dpll;
4261 struct intel_dpll *pll;
4262 bool pll_active;
4263
4264 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4265 pll = intel_get_dpll_by_id(display, pll_id);
4266
4267 if (drm_WARN_ON(display->drm, !pll))
4268 return;
4269
4270 port_dpll->pll = pll;
4271 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
4272 drm_WARN_ON(display->drm, !pll_active);
4273
4274 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4275
4276 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
4277 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4278 else
4279 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
4280 &crtc_state->dpll_hw_state);
4281
4282 intel_ddi_get_config(encoder, crtc_state);
4283 }
4284
4285 /*
4286 * Get the configuration for either a port using a C10 PHY PLL, or a port using a
4287 * C20 PHY PLL in the cases of:
4288 * - BMG port A/B
4289 * - PTL port B eDP over TypeC PHY
4290 */
mtl_ddi_non_tc_phy_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4291 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
4292 struct intel_crtc_state *crtc_state)
4293 {
4294 struct intel_display *display = to_intel_display(encoder);
4295
4296 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
4297 mtl_port_to_pll_id(display, encoder->port));
4298 }
4299
mtl_ddi_tc_phy_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4300 static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
4301 struct intel_crtc_state *crtc_state)
4302 {
4303 struct intel_display *display = to_intel_display(encoder);
4304
4305 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
4306 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
4307 DPLL_ID_ICL_TBTPLL);
4308 else
4309 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY,
4310 mtl_port_to_pll_id(display, encoder->port));
4311 }
4312
dg2_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4313 static void dg2_ddi_get_config(struct intel_encoder *encoder,
4314 struct intel_crtc_state *crtc_state)
4315 {
4316 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);
4317 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);
4318
4319 intel_ddi_get_config(encoder, crtc_state);
4320 }
4321
adls_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4322 static void adls_ddi_get_config(struct intel_encoder *encoder,
4323 struct intel_crtc_state *crtc_state)
4324 {
4325 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
4326 intel_ddi_get_config(encoder, crtc_state);
4327 }
4328
rkl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4329 static void rkl_ddi_get_config(struct intel_encoder *encoder,
4330 struct intel_crtc_state *crtc_state)
4331 {
4332 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
4333 intel_ddi_get_config(encoder, crtc_state);
4334 }
4335
dg1_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4336 static void dg1_ddi_get_config(struct intel_encoder *encoder,
4337 struct intel_crtc_state *crtc_state)
4338 {
4339 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
4340 intel_ddi_get_config(encoder, crtc_state);
4341 }
4342
icl_ddi_combo_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4343 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
4344 struct intel_crtc_state *crtc_state)
4345 {
4346 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
4347 intel_ddi_get_config(encoder, crtc_state);
4348 }
4349
4350 static enum icl_port_dpll_id
icl_ddi_tc_port_pll_type(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)4351 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
4352 const struct intel_crtc_state *crtc_state)
4353 {
4354 struct intel_display *display = to_intel_display(encoder);
4355 const struct intel_dpll *pll = crtc_state->intel_dpll;
4356
4357 if (drm_WARN_ON(display->drm, !pll))
4358 return ICL_PORT_DPLL_DEFAULT;
4359
4360 if (icl_ddi_tc_pll_is_tbt(pll))
4361 return ICL_PORT_DPLL_DEFAULT;
4362 else
4363 return ICL_PORT_DPLL_MG_PHY;
4364 }
4365
4366 enum icl_port_dpll_id
intel_ddi_port_pll_type(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)4367 intel_ddi_port_pll_type(struct intel_encoder *encoder,
4368 const struct intel_crtc_state *crtc_state)
4369 {
4370 if (!encoder->port_pll_type)
4371 return ICL_PORT_DPLL_DEFAULT;
4372
4373 return encoder->port_pll_type(encoder, crtc_state);
4374 }
4375
icl_ddi_tc_get_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct intel_dpll * pll)4376 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
4377 struct intel_crtc_state *crtc_state,
4378 struct intel_dpll *pll)
4379 {
4380 struct intel_display *display = to_intel_display(encoder);
4381 enum icl_port_dpll_id port_dpll_id;
4382 struct icl_port_dpll *port_dpll;
4383 bool pll_active;
4384
4385 if (drm_WARN_ON(display->drm, !pll))
4386 return;
4387
4388 if (icl_ddi_tc_pll_is_tbt(pll))
4389 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4390 else
4391 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
4392
4393 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4394
4395 port_dpll->pll = pll;
4396 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
4397 drm_WARN_ON(display->drm, !pll_active);
4398
4399 icl_set_active_port_dpll(crtc_state, port_dpll_id);
4400
4401 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
4402 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
4403 else
4404 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
4405 &crtc_state->dpll_hw_state);
4406 }
4407
icl_ddi_tc_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4408 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
4409 struct intel_crtc_state *crtc_state)
4410 {
4411 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
4412 intel_ddi_get_config(encoder, crtc_state);
4413 }
4414
bxt_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4415 static void bxt_ddi_get_config(struct intel_encoder *encoder,
4416 struct intel_crtc_state *crtc_state)
4417 {
4418 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
4419 intel_ddi_get_config(encoder, crtc_state);
4420 }
4421
skl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4422 static void skl_ddi_get_config(struct intel_encoder *encoder,
4423 struct intel_crtc_state *crtc_state)
4424 {
4425 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
4426 intel_ddi_get_config(encoder, crtc_state);
4427 }
4428
hsw_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4429 void hsw_ddi_get_config(struct intel_encoder *encoder,
4430 struct intel_crtc_state *crtc_state)
4431 {
4432 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
4433 intel_ddi_get_config(encoder, crtc_state);
4434 }
4435
intel_ddi_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)4436 static void intel_ddi_sync_state(struct intel_encoder *encoder,
4437 const struct intel_crtc_state *crtc_state)
4438 {
4439 if (intel_encoder_is_tc(encoder))
4440 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
4441 crtc_state);
4442
4443 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||
4444 (!crtc_state && intel_encoder_is_dp(encoder)))
4445 intel_dp_sync_state(encoder, crtc_state);
4446 }
4447
intel_ddi_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4448 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4449 struct intel_crtc_state *crtc_state)
4450 {
4451 struct intel_display *display = to_intel_display(encoder);
4452 bool fastset = true;
4453
4454 if (intel_encoder_is_tc(encoder)) {
4455 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
4456 encoder->base.base.id, encoder->base.name);
4457 crtc_state->uapi.mode_changed = true;
4458 fastset = false;
4459 }
4460
4461 if (intel_crtc_has_dp_encoder(crtc_state) &&
4462 !intel_dp_initial_fastset_check(encoder, crtc_state))
4463 fastset = false;
4464
4465 return fastset;
4466 }
4467
4468 static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4469 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4470 struct intel_crtc_state *crtc_state,
4471 struct drm_connector_state *conn_state)
4472 {
4473 switch (conn_state->connector->connector_type) {
4474 case DRM_MODE_CONNECTOR_HDMIA:
4475 return INTEL_OUTPUT_HDMI;
4476 case DRM_MODE_CONNECTOR_eDP:
4477 return INTEL_OUTPUT_EDP;
4478 case DRM_MODE_CONNECTOR_DisplayPort:
4479 return INTEL_OUTPUT_DP;
4480 default:
4481 MISSING_CASE(conn_state->connector->connector_type);
4482 return INTEL_OUTPUT_UNUSED;
4483 }
4484 }
4485
intel_ddi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)4486 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4487 struct intel_crtc_state *pipe_config,
4488 struct drm_connector_state *conn_state)
4489 {
4490 struct intel_display *display = to_intel_display(encoder);
4491 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4492 enum port port = encoder->port;
4493 int ret;
4494
4495 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
4496 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4497
4498 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4499 pipe_config->has_hdmi_sink =
4500 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state);
4501
4502 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4503 } else {
4504 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4505 }
4506
4507 if (ret)
4508 return ret;
4509
4510 if (display->platform.haswell && crtc->pipe == PIPE_A &&
4511 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4512 pipe_config->pch_pfit.force_thru =
4513 pipe_config->pch_pfit.enabled ||
4514 pipe_config->crc_enabled;
4515
4516 if (display->platform.geminilake || display->platform.broxton)
4517 pipe_config->lane_lat_optim_mask =
4518 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4519
4520 intel_ddi_compute_min_voltage_level(pipe_config);
4521
4522 return 0;
4523 }
4524
mode_equal(const struct drm_display_mode * mode1,const struct drm_display_mode * mode2)4525 static bool mode_equal(const struct drm_display_mode *mode1,
4526 const struct drm_display_mode *mode2)
4527 {
4528 return drm_mode_match(mode1, mode2,
4529 DRM_MODE_MATCH_TIMINGS |
4530 DRM_MODE_MATCH_FLAGS |
4531 DRM_MODE_MATCH_3D_FLAGS) &&
4532 mode1->clock == mode2->clock; /* we want an exact match */
4533 }
4534
m_n_equal(const struct intel_link_m_n * m_n_1,const struct intel_link_m_n * m_n_2)4535 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4536 const struct intel_link_m_n *m_n_2)
4537 {
4538 return m_n_1->tu == m_n_2->tu &&
4539 m_n_1->data_m == m_n_2->data_m &&
4540 m_n_1->data_n == m_n_2->data_n &&
4541 m_n_1->link_m == m_n_2->link_m &&
4542 m_n_1->link_n == m_n_2->link_n;
4543 }
4544
crtcs_port_sync_compatible(const struct intel_crtc_state * crtc_state1,const struct intel_crtc_state * crtc_state2)4545 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4546 const struct intel_crtc_state *crtc_state2)
4547 {
4548 /*
4549 * FIXME the modeset sequence is currently wrong and
4550 * can't deal with joiner + port sync at the same time.
4551 */
4552 return crtc_state1->hw.active && crtc_state2->hw.active &&
4553 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
4554 crtc_state1->output_types == crtc_state2->output_types &&
4555 crtc_state1->output_format == crtc_state2->output_format &&
4556 crtc_state1->lane_count == crtc_state2->lane_count &&
4557 crtc_state1->port_clock == crtc_state2->port_clock &&
4558 mode_equal(&crtc_state1->hw.adjusted_mode,
4559 &crtc_state2->hw.adjusted_mode) &&
4560 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4561 }
4562
4563 static u8
intel_ddi_port_sync_transcoders(const struct intel_crtc_state * ref_crtc_state,int tile_group_id)4564 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4565 int tile_group_id)
4566 {
4567 struct intel_display *display = to_intel_display(ref_crtc_state);
4568 struct drm_connector *connector;
4569 const struct drm_connector_state *conn_state;
4570 struct intel_atomic_state *state =
4571 to_intel_atomic_state(ref_crtc_state->uapi.state);
4572 u8 transcoders = 0;
4573 int i;
4574
4575 /*
4576 * We don't enable port sync on BDW due to missing w/as and
4577 * due to not having adjusted the modeset sequence appropriately.
4578 * From, xe3lpd onwards we have defeatured this with reference to
4579 * Wa_16024710867
4580 */
4581 if (!IS_DISPLAY_VER(display, 9, 20))
4582 return 0;
4583
4584 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4585 return 0;
4586
4587 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4588 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4589 const struct intel_crtc_state *crtc_state;
4590
4591 if (!crtc)
4592 continue;
4593
4594 if (!connector->has_tile ||
4595 connector->tile_group->id !=
4596 tile_group_id)
4597 continue;
4598 crtc_state = intel_atomic_get_new_crtc_state(state,
4599 crtc);
4600 if (!crtcs_port_sync_compatible(ref_crtc_state,
4601 crtc_state))
4602 continue;
4603 transcoders |= BIT(crtc_state->cpu_transcoder);
4604 }
4605
4606 return transcoders;
4607 }
4608
intel_ddi_compute_config_late(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4609 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4610 struct intel_crtc_state *crtc_state,
4611 struct drm_connector_state *conn_state)
4612 {
4613 struct intel_display *display = to_intel_display(encoder);
4614 struct drm_connector *connector = conn_state->connector;
4615 u8 port_sync_transcoders = 0;
4616 int ret = 0;
4617
4618 if (intel_crtc_has_dp_encoder(crtc_state))
4619 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state);
4620
4621 if (ret)
4622 return ret;
4623
4624 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
4625 encoder->base.base.id, encoder->base.name,
4626 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4627
4628 if (connector->has_tile)
4629 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4630 connector->tile_group->id);
4631
4632 /*
4633 * EDP Transcoders cannot be ensalved
4634 * make them a master always when present
4635 */
4636 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4637 crtc_state->master_transcoder = TRANSCODER_EDP;
4638 else
4639 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4640
4641 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4642 crtc_state->master_transcoder = INVALID_TRANSCODER;
4643 crtc_state->sync_mode_slaves_mask =
4644 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4645 }
4646
4647 return 0;
4648 }
4649
intel_ddi_encoder_destroy(struct drm_encoder * encoder)4650 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4651 {
4652 struct intel_display *display = to_intel_display(encoder->dev);
4653 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4654
4655 intel_dp_encoder_flush_work(encoder);
4656 if (intel_encoder_is_tc(&dig_port->base))
4657 intel_tc_port_cleanup(dig_port);
4658 intel_display_power_flush_work(display);
4659
4660 drm_encoder_cleanup(encoder);
4661 kfree(dig_port->hdcp.port_data.streams);
4662 kfree(dig_port);
4663 }
4664
intel_ddi_encoder_reset(struct drm_encoder * encoder)4665 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4666 {
4667 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4668 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4669
4670 intel_dp->reset_link_params = true;
4671 intel_dp_invalidate_source_oui(intel_dp);
4672
4673 intel_pps_encoder_reset(intel_dp);
4674
4675 if (intel_encoder_is_tc(&dig_port->base))
4676 intel_tc_port_init_mode(dig_port);
4677 }
4678
intel_ddi_encoder_late_register(struct drm_encoder * _encoder)4679 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
4680 {
4681 struct intel_encoder *encoder = to_intel_encoder(_encoder);
4682
4683 intel_tc_port_link_reset(enc_to_dig_port(encoder));
4684
4685 return 0;
4686 }
4687
4688 static const struct drm_encoder_funcs intel_ddi_funcs = {
4689 .reset = intel_ddi_encoder_reset,
4690 .destroy = intel_ddi_encoder_destroy,
4691 .late_register = intel_ddi_encoder_late_register,
4692 };
4693
intel_ddi_init_dp_connector(struct intel_digital_port * dig_port)4694 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4695 {
4696 struct intel_display *display = to_intel_display(dig_port);
4697 struct intel_connector *connector;
4698 enum port port = dig_port->base.port;
4699
4700 connector = intel_connector_alloc();
4701 if (!connector)
4702 return -ENOMEM;
4703
4704 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4705 if (DISPLAY_VER(display) >= 14)
4706 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
4707 else
4708 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4709 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4710 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4711
4712 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4713 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4714
4715 if (!intel_dp_init_connector(dig_port, connector)) {
4716 kfree(connector);
4717 return -EINVAL;
4718 }
4719
4720 if (dig_port->base.type == INTEL_OUTPUT_EDP) {
4721 struct drm_privacy_screen *privacy_screen;
4722
4723 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL);
4724 if (!IS_ERR(privacy_screen)) {
4725 drm_connector_attach_privacy_screen_provider(&connector->base,
4726 privacy_screen);
4727 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
4728 drm_warn(display->drm, "Error getting privacy-screen\n");
4729 }
4730 }
4731
4732 return 0;
4733 }
4734
intel_ddi_cleanup_dp_connector(struct intel_digital_port * dig_port)4735 static void intel_ddi_cleanup_dp_connector(struct intel_digital_port *dig_port)
4736 {
4737 struct intel_dp *intel_dp = &dig_port->dp;
4738 struct intel_connector *connector = intel_dp->attached_connector;
4739
4740 intel_dp_cleanup_connector(dig_port, connector);
4741 kfree(connector);
4742 }
4743
intel_hdmi_reset_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4744 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4745 struct drm_modeset_acquire_ctx *ctx)
4746 {
4747 struct intel_display *display = to_intel_display(encoder);
4748 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4749 struct intel_connector *connector = hdmi->attached_connector;
4750 struct i2c_adapter *ddc = connector->base.ddc;
4751 struct drm_connector_state *conn_state;
4752 struct intel_crtc_state *crtc_state;
4753 struct intel_crtc *crtc;
4754 u8 config;
4755 int ret;
4756
4757 if (connector->base.status != connector_status_connected)
4758 return 0;
4759
4760 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
4761 ctx);
4762 if (ret)
4763 return ret;
4764
4765 conn_state = connector->base.state;
4766
4767 crtc = to_intel_crtc(conn_state->crtc);
4768 if (!crtc)
4769 return 0;
4770
4771 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4772 if (ret)
4773 return ret;
4774
4775 crtc_state = to_intel_crtc_state(crtc->base.state);
4776
4777 drm_WARN_ON(display->drm,
4778 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4779
4780 if (!crtc_state->hw.active)
4781 return 0;
4782
4783 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4784 !crtc_state->hdmi_scrambling)
4785 return 0;
4786
4787 if (conn_state->commit &&
4788 !try_wait_for_completion(&conn_state->commit->hw_done))
4789 return 0;
4790
4791 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config);
4792 if (ret < 0) {
4793 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
4794 connector->base.base.id, connector->base.name, ret);
4795 return 0;
4796 }
4797
4798 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4799 crtc_state->hdmi_high_tmds_clock_ratio &&
4800 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4801 crtc_state->hdmi_scrambling)
4802 return 0;
4803
4804 /*
4805 * HDMI 2.0 says that one should not send scrambled data
4806 * prior to configuring the sink scrambling, and that
4807 * TMDS clock/data transmission should be suspended when
4808 * changing the TMDS clock rate in the sink. So let's
4809 * just do a full modeset here, even though some sinks
4810 * would be perfectly happy if were to just reconfigure
4811 * the SCDC settings on the fly.
4812 */
4813 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);
4814 }
4815
intel_ddi_link_check(struct intel_encoder * encoder)4816 static void intel_ddi_link_check(struct intel_encoder *encoder)
4817 {
4818 struct intel_display *display = to_intel_display(encoder);
4819 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4820
4821 /* TODO: Move checking the HDMI link state here as well. */
4822 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector);
4823
4824 intel_dp_link_check(encoder);
4825 }
4826
4827 static enum intel_hotplug_state
intel_ddi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)4828 intel_ddi_hotplug(struct intel_encoder *encoder,
4829 struct intel_connector *connector)
4830 {
4831 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4832 struct intel_dp *intel_dp = &dig_port->dp;
4833 bool is_tc = intel_encoder_is_tc(encoder);
4834 struct drm_modeset_acquire_ctx ctx;
4835 enum intel_hotplug_state state;
4836 int ret;
4837
4838 if (intel_dp_test_phy(intel_dp))
4839 return INTEL_HOTPLUG_UNCHANGED;
4840
4841 state = intel_encoder_hotplug(encoder, connector);
4842
4843 if (!intel_tc_port_link_reset(dig_port)) {
4844 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
4845 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
4846 ret = intel_hdmi_reset_link(encoder, &ctx);
4847 drm_WARN_ON(encoder->base.dev, ret);
4848 } else {
4849 intel_dp_check_link_state(intel_dp);
4850 }
4851 }
4852
4853 /*
4854 * Unpowered type-c dongles can take some time to boot and be
4855 * responsible, so here giving some time to those dongles to power up
4856 * and then retrying the probe.
4857 *
4858 * On many platforms the HDMI live state signal is known to be
4859 * unreliable, so we can't use it to detect if a sink is connected or
4860 * not. Instead we detect if it's connected based on whether we can
4861 * read the EDID or not. That in turn has a problem during disconnect,
4862 * since the HPD interrupt may be raised before the DDC lines get
4863 * disconnected (due to how the required length of DDC vs. HPD
4864 * connector pins are specified) and so we'll still be able to get a
4865 * valid EDID. To solve this schedule another detection cycle if this
4866 * time around we didn't detect any change in the sink's connection
4867 * status.
4868 *
4869 * Type-c connectors which get their HPD signal deasserted then
4870 * reasserted, without unplugging/replugging the sink from the
4871 * connector, introduce a delay until the AUX channel communication
4872 * becomes functional. Retry the detection for 5 seconds on type-c
4873 * connectors to account for this delay.
4874 */
4875 if (state == INTEL_HOTPLUG_UNCHANGED &&
4876 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4877 !dig_port->dp.is_mst)
4878 state = INTEL_HOTPLUG_RETRY;
4879
4880 return state;
4881 }
4882
lpt_digital_port_connected(struct intel_encoder * encoder)4883 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4884 {
4885 struct intel_display *display = to_intel_display(encoder);
4886 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
4887
4888 return intel_de_read(display, SDEISR) & bit;
4889 }
4890
hsw_digital_port_connected(struct intel_encoder * encoder)4891 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4892 {
4893 struct intel_display *display = to_intel_display(encoder);
4894 u32 bit = display->hotplug.hpd[encoder->hpd_pin];
4895
4896 return intel_de_read(display, DEISR) & bit;
4897 }
4898
bdw_digital_port_connected(struct intel_encoder * encoder)4899 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4900 {
4901 struct intel_display *display = to_intel_display(encoder);
4902 u32 bit = display->hotplug.hpd[encoder->hpd_pin];
4903
4904 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;
4905 }
4906
intel_ddi_init_hdmi_connector(struct intel_digital_port * dig_port)4907 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4908 {
4909 struct intel_connector *connector;
4910 enum port port = dig_port->base.port;
4911
4912 connector = intel_connector_alloc();
4913 if (!connector)
4914 return -ENOMEM;
4915
4916 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4917
4918 if (!intel_hdmi_init_connector(dig_port, connector)) {
4919 /*
4920 * HDMI connector init failures may just mean conflicting DDC
4921 * pins or not having enough lanes. Handle them gracefully, but
4922 * don't fail the entire DDI init.
4923 */
4924 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG;
4925 kfree(connector);
4926 }
4927
4928 return 0;
4929 }
4930
intel_ddi_a_force_4_lanes(struct intel_digital_port * dig_port)4931 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4932 {
4933 struct intel_display *display = to_intel_display(dig_port);
4934
4935 if (dig_port->base.port != PORT_A)
4936 return false;
4937
4938 if (dig_port->ddi_a_4_lanes)
4939 return false;
4940
4941 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4942 * supported configuration
4943 */
4944 if (display->platform.geminilake || display->platform.broxton)
4945 return true;
4946
4947 return false;
4948 }
4949
4950 static int
intel_ddi_max_lanes(struct intel_digital_port * dig_port)4951 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4952 {
4953 struct intel_display *display = to_intel_display(dig_port);
4954 enum port port = dig_port->base.port;
4955 int max_lanes = 4;
4956
4957 if (DISPLAY_VER(display) >= 11)
4958 return max_lanes;
4959
4960 if (port == PORT_A || port == PORT_E) {
4961 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4962 max_lanes = port == PORT_A ? 4 : 0;
4963 else
4964 /* Both A and E share 2 lanes */
4965 max_lanes = 2;
4966 }
4967
4968 /*
4969 * Some BIOS might fail to set this bit on port A if eDP
4970 * wasn't lit up at boot. Force this bit set when needed
4971 * so we use the proper lane count for our calculations.
4972 */
4973 if (intel_ddi_a_force_4_lanes(dig_port)) {
4974 drm_dbg_kms(display->drm,
4975 "Forcing DDI_A_4_LANES for port A\n");
4976 dig_port->ddi_a_4_lanes = true;
4977 max_lanes = 4;
4978 }
4979
4980 return max_lanes;
4981 }
4982
xelpd_hpd_pin(struct intel_display * display,enum port port)4983 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
4984 {
4985 if (port >= PORT_D_XELPD)
4986 return HPD_PORT_D + port - PORT_D_XELPD;
4987 else if (port >= PORT_TC1)
4988 return HPD_PORT_TC1 + port - PORT_TC1;
4989 else
4990 return HPD_PORT_A + port - PORT_A;
4991 }
4992
dg1_hpd_pin(struct intel_display * display,enum port port)4993 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)
4994 {
4995 if (port >= PORT_TC1)
4996 return HPD_PORT_C + port - PORT_TC1;
4997 else
4998 return HPD_PORT_A + port - PORT_A;
4999 }
5000
tgl_hpd_pin(struct intel_display * display,enum port port)5001 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)
5002 {
5003 if (port >= PORT_TC1)
5004 return HPD_PORT_TC1 + port - PORT_TC1;
5005 else
5006 return HPD_PORT_A + port - PORT_A;
5007 }
5008
rkl_hpd_pin(struct intel_display * display,enum port port)5009 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)
5010 {
5011 if (HAS_PCH_TGP(display))
5012 return tgl_hpd_pin(display, port);
5013
5014 if (port >= PORT_TC1)
5015 return HPD_PORT_C + port - PORT_TC1;
5016 else
5017 return HPD_PORT_A + port - PORT_A;
5018 }
5019
icl_hpd_pin(struct intel_display * display,enum port port)5020 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)
5021 {
5022 if (port >= PORT_C)
5023 return HPD_PORT_TC1 + port - PORT_C;
5024 else
5025 return HPD_PORT_A + port - PORT_A;
5026 }
5027
ehl_hpd_pin(struct intel_display * display,enum port port)5028 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)
5029 {
5030 if (port == PORT_D)
5031 return HPD_PORT_A;
5032
5033 if (HAS_PCH_TGP(display))
5034 return icl_hpd_pin(display, port);
5035
5036 return HPD_PORT_A + port - PORT_A;
5037 }
5038
skl_hpd_pin(struct intel_display * display,enum port port)5039 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)
5040 {
5041 if (HAS_PCH_TGP(display))
5042 return icl_hpd_pin(display, port);
5043
5044 return HPD_PORT_A + port - PORT_A;
5045 }
5046
intel_ddi_is_tc(struct intel_display * display,enum port port)5047 static bool intel_ddi_is_tc(struct intel_display *display, enum port port)
5048 {
5049 if (DISPLAY_VER(display) >= 12)
5050 return port >= PORT_TC1;
5051 else if (DISPLAY_VER(display) >= 11)
5052 return port >= PORT_C;
5053 else
5054 return false;
5055 }
5056
intel_ddi_encoder_suspend(struct intel_encoder * encoder)5057 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
5058 {
5059 intel_dp_encoder_suspend(encoder);
5060 }
5061
intel_ddi_tc_encoder_suspend_complete(struct intel_encoder * encoder)5062 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
5063 {
5064 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5065 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5066
5067 /*
5068 * TODO: Move this to intel_dp_encoder_suspend(),
5069 * once modeset locking around that is removed.
5070 */
5071 intel_encoder_link_check_flush_work(encoder);
5072 intel_tc_port_suspend(dig_port);
5073 }
5074
intel_ddi_encoder_shutdown(struct intel_encoder * encoder)5075 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
5076 {
5077 if (intel_encoder_is_dp(encoder))
5078 intel_dp_encoder_shutdown(encoder);
5079 if (intel_encoder_is_hdmi(encoder))
5080 intel_hdmi_encoder_shutdown(encoder);
5081 }
5082
intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder * encoder)5083 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
5084 {
5085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5086 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5087
5088 intel_tc_port_cleanup(dig_port);
5089 }
5090
5091 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
5092 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5093
port_strap_detected(struct intel_display * display,enum port port)5094 static bool port_strap_detected(struct intel_display *display, enum port port)
5095 {
5096 /* straps not used on skl+ */
5097 if (DISPLAY_VER(display) >= 9)
5098 return true;
5099
5100 switch (port) {
5101 case PORT_A:
5102 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
5103 case PORT_B:
5104 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
5105 case PORT_C:
5106 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
5107 case PORT_D:
5108 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
5109 case PORT_E:
5110 return true; /* no strap for DDI-E */
5111 default:
5112 MISSING_CASE(port);
5113 return false;
5114 }
5115 }
5116
need_aux_ch(struct intel_encoder * encoder,bool init_dp)5117 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
5118 {
5119 return init_dp || intel_encoder_is_tc(encoder);
5120 }
5121
assert_has_icl_dsi(struct intel_display * display)5122 static bool assert_has_icl_dsi(struct intel_display *display)
5123 {
5124 return !drm_WARN(display->drm, !display->platform.alderlake_p &&
5125 !display->platform.tigerlake && DISPLAY_VER(display) != 11,
5126 "Platform does not support DSI\n");
5127 }
5128
port_in_use(struct intel_display * display,enum port port)5129 static bool port_in_use(struct intel_display *display, enum port port)
5130 {
5131 struct intel_encoder *encoder;
5132
5133 for_each_intel_encoder(display->drm, encoder) {
5134 /* FIXME what about second port for dual link DSI? */
5135 if (encoder->port == port)
5136 return true;
5137 }
5138
5139 return false;
5140 }
5141
intel_ddi_encoder_name(struct intel_display * display,enum port port,enum phy phy,struct seq_buf * s)5142 static const char *intel_ddi_encoder_name(struct intel_display *display,
5143 enum port port, enum phy phy,
5144 struct seq_buf *s)
5145 {
5146 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) {
5147 seq_buf_printf(s, "DDI %c/PHY %c",
5148 port_name(port - PORT_D_XELPD + PORT_D),
5149 phy_name(phy));
5150 } else if (DISPLAY_VER(display) >= 12) {
5151 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);
5152
5153 seq_buf_printf(s, "DDI %s%c/PHY %s%c",
5154 port >= PORT_TC1 ? "TC" : "",
5155 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
5156 tc_port != TC_PORT_NONE ? "TC" : "",
5157 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5158 } else if (DISPLAY_VER(display) >= 11) {
5159 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port);
5160
5161 seq_buf_printf(s, "DDI %c%s/PHY %s%c",
5162 port_name(port),
5163 port >= PORT_C ? " (TC)" : "",
5164 tc_port != TC_PORT_NONE ? "TC" : "",
5165 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5166 } else {
5167 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy));
5168 }
5169
5170 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s));
5171
5172 return seq_buf_str(s);
5173 }
5174
intel_ddi_init(struct intel_display * display,const struct intel_bios_encoder_data * devdata)5175 void intel_ddi_init(struct intel_display *display,
5176 const struct intel_bios_encoder_data *devdata)
5177 {
5178 struct intel_digital_port *dig_port;
5179 struct intel_encoder *encoder;
5180 DECLARE_SEQ_BUF(encoder_name, 20);
5181 bool init_hdmi, init_dp;
5182 enum port port;
5183 enum phy phy;
5184 u32 ddi_buf_ctl;
5185
5186 port = intel_bios_encoder_port(devdata);
5187 if (port == PORT_NONE)
5188 return;
5189
5190 if (!port_strap_detected(display, port)) {
5191 drm_dbg_kms(display->drm,
5192 "Port %c strap not detected\n", port_name(port));
5193 return;
5194 }
5195
5196 if (!assert_port_valid(display, port))
5197 return;
5198
5199 if (port_in_use(display, port)) {
5200 drm_dbg_kms(display->drm,
5201 "Port %c already claimed\n", port_name(port));
5202 return;
5203 }
5204
5205 if (intel_bios_encoder_supports_dsi(devdata)) {
5206 /* BXT/GLK handled elsewhere, for now at least */
5207 if (!assert_has_icl_dsi(display))
5208 return;
5209
5210 icl_dsi_init(display, devdata);
5211 return;
5212 }
5213
5214 phy = intel_port_to_phy(display, port);
5215
5216 /*
5217 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
5218 * have taken over some of the PHYs and made them unavailable to the
5219 * driver. In that case we should skip initializing the corresponding
5220 * outputs.
5221 */
5222 if (intel_hti_uses_phy(display, phy)) {
5223 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n",
5224 port_name(port), phy_name(phy));
5225 return;
5226 }
5227
5228 init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
5229 intel_bios_encoder_supports_hdmi(devdata);
5230 init_dp = intel_bios_encoder_supports_dp(devdata);
5231
5232 if (intel_bios_encoder_is_lspcon(devdata)) {
5233 /*
5234 * Lspcon device needs to be driven with DP connector
5235 * with special detection sequence. So make sure DP
5236 * is initialized before lspcon.
5237 */
5238 init_dp = true;
5239 init_hdmi = false;
5240 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n",
5241 port_name(port));
5242 }
5243
5244 if (!init_dp && !init_hdmi) {
5245 drm_dbg_kms(display->drm,
5246 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5247 port_name(port));
5248 return;
5249 }
5250
5251 if (intel_phy_is_snps(display, phy) &&
5252 display->snps.phy_failed_calibration & BIT(phy)) {
5253 drm_dbg_kms(display->drm,
5254 "SNPS PHY %c failed to calibrate, proceeding anyway\n",
5255 phy_name(phy));
5256 }
5257
5258 dig_port = intel_dig_port_alloc();
5259 if (!dig_port)
5260 return;
5261
5262 encoder = &dig_port->base;
5263 encoder->devdata = devdata;
5264
5265 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs,
5266 DRM_MODE_ENCODER_TMDS, "%s",
5267 intel_ddi_encoder_name(display, port, phy, &encoder_name));
5268
5269 intel_encoder_link_check_init(encoder, intel_ddi_link_check);
5270
5271 encoder->hotplug = intel_ddi_hotplug;
5272 encoder->compute_output_type = intel_ddi_compute_output_type;
5273 encoder->compute_config = intel_ddi_compute_config;
5274 encoder->compute_config_late = intel_ddi_compute_config_late;
5275 encoder->enable = intel_ddi_enable;
5276 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5277 encoder->pre_enable = intel_ddi_pre_enable;
5278 encoder->disable = intel_ddi_disable;
5279 encoder->post_pll_disable = intel_ddi_post_pll_disable;
5280 encoder->post_disable = intel_ddi_post_disable;
5281 encoder->update_pipe = intel_ddi_update_pipe;
5282 encoder->audio_enable = intel_audio_codec_enable;
5283 encoder->audio_disable = intel_audio_codec_disable;
5284 encoder->get_hw_state = intel_ddi_get_hw_state;
5285 encoder->sync_state = intel_ddi_sync_state;
5286 encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
5287 encoder->suspend = intel_ddi_encoder_suspend;
5288 encoder->shutdown = intel_ddi_encoder_shutdown;
5289 encoder->get_power_domains = intel_ddi_get_power_domains;
5290
5291 encoder->type = INTEL_OUTPUT_DDI;
5292 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
5293 encoder->port = port;
5294 encoder->cloneable = 0;
5295 encoder->pipe_mask = ~0;
5296
5297 if (HAS_LT_PHY(display)) {
5298 encoder->enable_clock = intel_mtl_pll_enable_clock;
5299 encoder->disable_clock = intel_mtl_pll_disable_clock;
5300 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5301 if (intel_encoder_is_tc(encoder))
5302 encoder->get_config = mtl_ddi_tc_phy_get_config;
5303 else
5304 encoder->get_config = mtl_ddi_non_tc_phy_get_config;
5305 } else if (DISPLAY_VER(display) >= 14) {
5306 encoder->enable_clock = intel_mtl_pll_enable_clock;
5307 encoder->disable_clock = intel_mtl_pll_disable_clock;
5308 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5309 if (intel_encoder_is_tc(encoder))
5310 encoder->get_config = mtl_ddi_tc_phy_get_config;
5311 else
5312 encoder->get_config = mtl_ddi_non_tc_phy_get_config;
5313 } else if (display->platform.dg2) {
5314 encoder->enable_clock = intel_mpllb_enable;
5315 encoder->disable_clock = intel_mpllb_disable;
5316 encoder->get_config = dg2_ddi_get_config;
5317 } else if (display->platform.alderlake_s) {
5318 encoder->enable_clock = adls_ddi_enable_clock;
5319 encoder->disable_clock = adls_ddi_disable_clock;
5320 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
5321 encoder->get_config = adls_ddi_get_config;
5322 } else if (display->platform.rocketlake) {
5323 encoder->enable_clock = rkl_ddi_enable_clock;
5324 encoder->disable_clock = rkl_ddi_disable_clock;
5325 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
5326 encoder->get_config = rkl_ddi_get_config;
5327 } else if (display->platform.dg1) {
5328 encoder->enable_clock = dg1_ddi_enable_clock;
5329 encoder->disable_clock = dg1_ddi_disable_clock;
5330 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
5331 encoder->get_config = dg1_ddi_get_config;
5332 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
5333 if (intel_ddi_is_tc(display, port)) {
5334 encoder->enable_clock = jsl_ddi_tc_enable_clock;
5335 encoder->disable_clock = jsl_ddi_tc_disable_clock;
5336 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
5337 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5338 encoder->get_config = icl_ddi_combo_get_config;
5339 } else {
5340 encoder->enable_clock = icl_ddi_combo_enable_clock;
5341 encoder->disable_clock = icl_ddi_combo_disable_clock;
5342 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5343 encoder->get_config = icl_ddi_combo_get_config;
5344 }
5345 } else if (DISPLAY_VER(display) >= 11) {
5346 if (intel_ddi_is_tc(display, port)) {
5347 encoder->enable_clock = icl_ddi_tc_enable_clock;
5348 encoder->disable_clock = icl_ddi_tc_disable_clock;
5349 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
5350 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5351 encoder->get_config = icl_ddi_tc_get_config;
5352 } else {
5353 encoder->enable_clock = icl_ddi_combo_enable_clock;
5354 encoder->disable_clock = icl_ddi_combo_disable_clock;
5355 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5356 encoder->get_config = icl_ddi_combo_get_config;
5357 }
5358 } else if (display->platform.geminilake || display->platform.broxton) {
5359 /* BXT/GLK have fixed PLL->port mapping */
5360 encoder->get_config = bxt_ddi_get_config;
5361 } else if (DISPLAY_VER(display) == 9) {
5362 encoder->enable_clock = skl_ddi_enable_clock;
5363 encoder->disable_clock = skl_ddi_disable_clock;
5364 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
5365 encoder->get_config = skl_ddi_get_config;
5366 } else if (display->platform.broadwell || display->platform.haswell) {
5367 encoder->enable_clock = hsw_ddi_enable_clock;
5368 encoder->disable_clock = hsw_ddi_disable_clock;
5369 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
5370 encoder->get_config = hsw_ddi_get_config;
5371 }
5372
5373 if (HAS_LT_PHY(display)) {
5374 encoder->set_signal_levels = intel_lt_phy_set_signal_levels;
5375 } else if (DISPLAY_VER(display) >= 14) {
5376 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
5377 } else if (display->platform.dg2) {
5378 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
5379 } else if (DISPLAY_VER(display) >= 12) {
5380 if (intel_encoder_is_combo(encoder))
5381 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5382 else
5383 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
5384 } else if (DISPLAY_VER(display) >= 11) {
5385 if (intel_encoder_is_combo(encoder))
5386 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5387 else
5388 encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
5389 } else if (display->platform.geminilake || display->platform.broxton) {
5390 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels;
5391 } else {
5392 encoder->set_signal_levels = hsw_set_signal_levels;
5393 }
5394
5395 intel_ddi_buf_trans_init(encoder);
5396
5397 if (DISPLAY_VER(display) >= 13)
5398 encoder->hpd_pin = xelpd_hpd_pin(display, port);
5399 else if (display->platform.dg1)
5400 encoder->hpd_pin = dg1_hpd_pin(display, port);
5401 else if (display->platform.rocketlake)
5402 encoder->hpd_pin = rkl_hpd_pin(display, port);
5403 else if (DISPLAY_VER(display) >= 12)
5404 encoder->hpd_pin = tgl_hpd_pin(display, port);
5405 else if (display->platform.jasperlake || display->platform.elkhartlake)
5406 encoder->hpd_pin = ehl_hpd_pin(display, port);
5407 else if (DISPLAY_VER(display) == 11)
5408 encoder->hpd_pin = icl_hpd_pin(display, port);
5409 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
5410 encoder->hpd_pin = skl_hpd_pin(display, port);
5411 else
5412 encoder->hpd_pin = intel_hpd_pin_default(port);
5413
5414 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));
5415
5416 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) ||
5417 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL;
5418
5419 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;
5420
5421 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5422
5423 if (need_aux_ch(encoder, init_dp)) {
5424 dig_port->aux_ch = intel_dp_aux_ch(encoder);
5425 if (dig_port->aux_ch == AUX_CH_NONE)
5426 goto err_aux_ch_init;
5427 }
5428
5429 /*
5430 * FIXME: We currently need to store dedicated_external because devdata
5431 * does not live long enough for when intel_encoder_is_tc() is called on
5432 * the unbind path. This needs to be fixed by making sure that the VBT
5433 * data is kept long enough, so that
5434 * intel_bios_encoder_is_dedicated_external() can be called directly
5435 * from intel_encoder_is_tc().
5436 */
5437 if (intel_bios_encoder_is_dedicated_external(devdata))
5438 dig_port->dedicated_external = true;
5439
5440 if (intel_encoder_is_tc(encoder)) {
5441 bool is_legacy =
5442 !intel_bios_encoder_supports_typec_usb(devdata) &&
5443 !intel_bios_encoder_supports_tbt(devdata);
5444
5445 if (!is_legacy && init_hdmi) {
5446 is_legacy = !init_dp;
5447
5448 drm_dbg_kms(display->drm,
5449 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
5450 port_name(port),
5451 str_yes_no(init_dp),
5452 is_legacy ? "legacy" : "non-legacy");
5453 }
5454
5455 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
5456 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
5457
5458 dig_port->lock = intel_tc_port_lock;
5459 dig_port->unlock = intel_tc_port_unlock;
5460
5461 if (intel_tc_port_init(dig_port, is_legacy) < 0)
5462 goto err_aux_ch_init;
5463 }
5464
5465 drm_WARN_ON(display->drm, port > PORT_I);
5466 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);
5467
5468 if (DISPLAY_VER(display) >= 11) {
5469 if (intel_encoder_is_tc(encoder))
5470 dig_port->connected = intel_tc_port_connected;
5471 else
5472 dig_port->connected = lpt_digital_port_connected;
5473 } else if (display->platform.geminilake || display->platform.broxton) {
5474 dig_port->connected = bdw_digital_port_connected;
5475 } else if (DISPLAY_VER(display) == 9) {
5476 dig_port->connected = lpt_digital_port_connected;
5477 } else if (display->platform.broadwell) {
5478 if (port == PORT_A)
5479 dig_port->connected = bdw_digital_port_connected;
5480 else
5481 dig_port->connected = lpt_digital_port_connected;
5482 } else if (display->platform.haswell) {
5483 if (port == PORT_A)
5484 dig_port->connected = hsw_digital_port_connected;
5485 else
5486 dig_port->connected = lpt_digital_port_connected;
5487 }
5488
5489 intel_infoframe_init(dig_port);
5490
5491 if (init_dp) {
5492 if (intel_ddi_init_dp_connector(dig_port))
5493 goto err_dp_connector_init;
5494
5495 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5496
5497 if (dig_port->dp.mso_link_count)
5498 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display);
5499 }
5500
5501 /*
5502 * In theory we don't need the encoder->type check,
5503 * but leave it just in case we have some really bad VBTs...
5504 */
5505 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5506 if (intel_ddi_init_hdmi_connector(dig_port))
5507 goto err_hdmi_connector_init;
5508 }
5509
5510 return;
5511
5512 err_hdmi_connector_init:
5513 if (init_dp)
5514 intel_ddi_cleanup_dp_connector(dig_port);
5515 err_dp_connector_init:
5516 if (intel_encoder_is_tc(encoder))
5517 intel_tc_port_cleanup(dig_port);
5518 err_aux_ch_init:
5519 drm_encoder_cleanup(&encoder->base);
5520 kfree(dig_port);
5521 }
5522