1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright Fiona Klute <fiona.klute@gmx.de> */
3
4 #include <linux/of_net.h>
5 #include "main.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rx.h"
12 #include "rtw8703b.h"
13 #include "rtw8703b_tables.h"
14 #include "rtw8723x.h"
15
16 #define BIT_MASK_TXQ_INIT (BIT(7))
17 #define WLAN_RL_VAL 0x3030
18 /* disable BAR */
19 #define WLAN_BAR_VAL 0x0201ffff
20 #define WLAN_PIFS_VAL 0
21 #define WLAN_RX_PKT_LIMIT 0x18
22 #define WLAN_SLOT_TIME 0x09
23 #define WLAN_SPEC_SIFS 0x100a
24 #define WLAN_MAX_AGG_NR 0x1f
25 #define WLAN_AMPDU_MAX_TIME 0x70
26
27 /* unit is 32us */
28 #define TBTT_PROHIBIT_SETUP_TIME 0x04
29 #define TBTT_PROHIBIT_HOLD_TIME 0x80
30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64
31
32 #define TRANS_SEQ_END \
33 0xFFFF, \
34 RTW_PWR_CUT_ALL_MSK, \
35 RTW_PWR_INTF_ALL_MSK, \
36 0, \
37 RTW_PWR_CMD_END, 0, 0
38
39 /* rssi in percentage % (dbm = % - 100) */
40 /* These are used to select simple signal quality levels, might need
41 * tweaking. Same for rf_para tables below.
42 */
43 static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30};
44 static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30};
45 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} };
46
47 /* Actually decreasing wifi TX power/RX gain isn't implemented in
48 * rtw8703b, but hopefully adjusting the BT side helps.
49 */
50 static const struct coex_rf_para rf_para_tx_8703b[] = {
51 {0, 0, false, 7}, /* for normal */
52 {0, 10, false, 7}, /* for WL-CPT */
53 {1, 0, true, 4},
54 {1, 2, true, 4},
55 {1, 10, true, 4},
56 {1, 15, true, 4}
57 };
58
59 static const struct coex_rf_para rf_para_rx_8703b[] = {
60 {0, 0, false, 7}, /* for normal */
61 {0, 10, false, 7}, /* for WL-CPT */
62 {1, 0, true, 5},
63 {1, 2, true, 5},
64 {1, 10, true, 5},
65 {1, 15, true, 5}
66 };
67
68 static const u32 rtw8703b_ofdm_swing_table[] = {
69 0x0b40002d, /* 0, -15.0dB */
70 0x0c000030, /* 1, -14.5dB */
71 0x0cc00033, /* 2, -14.0dB */
72 0x0d800036, /* 3, -13.5dB */
73 0x0e400039, /* 4, -13.0dB */
74 0x0f00003c, /* 5, -12.5dB */
75 0x10000040, /* 6, -12.0dB */
76 0x11000044, /* 7, -11.5dB */
77 0x12000048, /* 8, -11.0dB */
78 0x1300004c, /* 9, -10.5dB */
79 0x14400051, /* 10, -10.0dB */
80 0x15800056, /* 11, -9.5dB */
81 0x16c0005b, /* 12, -9.0dB */
82 0x18000060, /* 13, -8.5dB */
83 0x19800066, /* 14, -8.0dB */
84 0x1b00006c, /* 15, -7.5dB */
85 0x1c800072, /* 16, -7.0dB */
86 0x1e400079, /* 17, -6.5dB */
87 0x20000080, /* 18, -6.0dB */
88 0x22000088, /* 19, -5.5dB */
89 0x24000090, /* 20, -5.0dB */
90 0x26000098, /* 21, -4.5dB */
91 0x288000a2, /* 22, -4.0dB */
92 0x2ac000ab, /* 23, -3.5dB */
93 0x2d4000b5, /* 24, -3.0dB */
94 0x300000c0, /* 25, -2.5dB */
95 0x32c000cb, /* 26, -2.0dB */
96 0x35c000d7, /* 27, -1.5dB */
97 0x390000e4, /* 28, -1.0dB */
98 0x3c8000f2, /* 29, -0.5dB */
99 0x40000100, /* 30, +0dB */
100 0x43c0010f, /* 31, +0.5dB */
101 0x47c0011f, /* 32, +1.0dB */
102 0x4c000130, /* 33, +1.5dB */
103 0x50800142, /* 34, +2.0dB */
104 0x55400155, /* 35, +2.5dB */
105 0x5a400169, /* 36, +3.0dB */
106 0x5fc0017f, /* 37, +3.5dB */
107 0x65400195, /* 38, +4.0dB */
108 0x6b8001ae, /* 39, +4.5dB */
109 0x71c001c7, /* 40, +5.0dB */
110 0x788001e2, /* 41, +5.5dB */
111 0x7f8001fe /* 42, +6.0dB */
112 };
113
114 static const u32 rtw8703b_cck_pwr_regs[] = {
115 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29,
116 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3,
117 };
118
119 static const u8 rtw8703b_cck_swing_table[][16] = {
120 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
122 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
124 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
126 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
128 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
130 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
132 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
134 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
136 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
138 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
140 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
142 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
144 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
146 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
148 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
150 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
152 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
154 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
156 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
158 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
160 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
162 };
163
164 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table)
165 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table)
166
167 static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = {
168 /* set up external crystal (XTAL) */
169 {REG_PAD_CTRL1 + 2,
170 RTW_PWR_CUT_ALL_MSK,
171 RTW_PWR_INTF_ALL_MSK,
172 RTW_PWR_ADDR_MAC,
173 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
174 /* set CLK_REQ to high active */
175 {0x0069,
176 RTW_PWR_CUT_ALL_MSK,
177 RTW_PWR_INTF_ALL_MSK,
178 RTW_PWR_ADDR_MAC,
179 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
180 /* unlock ISO/CLK/power control register */
181 {REG_RSV_CTRL,
182 RTW_PWR_CUT_ALL_MSK,
183 RTW_PWR_INTF_ALL_MSK,
184 RTW_PWR_ADDR_MAC,
185 RTW_PWR_CMD_WRITE, 0xff, 0},
186 {TRANS_SEQ_END},
187 };
188
189 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = {
190 {0x0005,
191 RTW_PWR_CUT_ALL_MSK,
192 RTW_PWR_INTF_ALL_MSK,
193 RTW_PWR_ADDR_MAC,
194 RTW_PWR_CMD_WRITE, BIT(7), 0},
195 {TRANS_SEQ_END},
196 };
197
198 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = {
199 {0x0023,
200 RTW_PWR_CUT_ALL_MSK,
201 RTW_PWR_INTF_SDIO_MSK,
202 RTW_PWR_ADDR_MAC,
203 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
204 {0x0007,
205 RTW_PWR_CUT_ALL_MSK,
206 RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK,
207 RTW_PWR_ADDR_MAC,
208 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
209 {0x0006,
210 RTW_PWR_CUT_ALL_MSK,
211 RTW_PWR_INTF_ALL_MSK,
212 RTW_PWR_ADDR_MAC,
213 RTW_PWR_CMD_WRITE, BIT(0), 0},
214 {0x0005,
215 RTW_PWR_CUT_ALL_MSK,
216 RTW_PWR_INTF_ALL_MSK,
217 RTW_PWR_ADDR_MAC,
218 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
219 {TRANS_SEQ_END},
220 };
221
222 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = {
223 {0x0020,
224 RTW_PWR_CUT_ALL_MSK,
225 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
226 RTW_PWR_ADDR_MAC,
227 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
228 {0x0067,
229 RTW_PWR_CUT_ALL_MSK,
230 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
231 RTW_PWR_ADDR_MAC,
232 RTW_PWR_CMD_WRITE, BIT(4), 0},
233 {0x0001,
234 RTW_PWR_CUT_ALL_MSK,
235 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
236 RTW_PWR_ADDR_MAC,
237 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
238 {0x0000,
239 RTW_PWR_CUT_ALL_MSK,
240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
241 RTW_PWR_ADDR_MAC,
242 RTW_PWR_CMD_WRITE, BIT(5), 0},
243 {0x0005,
244 RTW_PWR_CUT_ALL_MSK,
245 RTW_PWR_INTF_ALL_MSK,
246 RTW_PWR_ADDR_MAC,
247 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
248 {0x0075,
249 RTW_PWR_CUT_ALL_MSK,
250 RTW_PWR_INTF_PCI_MSK,
251 RTW_PWR_ADDR_MAC,
252 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
253 {0x0004,
254 RTW_PWR_CUT_ALL_MSK,
255 RTW_PWR_INTF_PCI_MSK,
256 RTW_PWR_ADDR_MAC,
257 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
258 {0x0004,
259 RTW_PWR_CUT_ALL_MSK,
260 RTW_PWR_INTF_PCI_MSK,
261 RTW_PWR_ADDR_MAC,
262 RTW_PWR_CMD_WRITE, BIT(3), 0},
263 /* wait for power ready */
264 {0x0006,
265 RTW_PWR_CUT_ALL_MSK,
266 RTW_PWR_INTF_ALL_MSK,
267 RTW_PWR_ADDR_MAC,
268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
269 {0x0075,
270 RTW_PWR_CUT_ALL_MSK,
271 RTW_PWR_INTF_PCI_MSK,
272 RTW_PWR_ADDR_MAC,
273 RTW_PWR_CMD_WRITE, BIT(0), 0},
274 {0x0006,
275 RTW_PWR_CUT_ALL_MSK,
276 RTW_PWR_INTF_ALL_MSK,
277 RTW_PWR_ADDR_MAC,
278 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
279 {0x0005,
280 RTW_PWR_CUT_ALL_MSK,
281 RTW_PWR_INTF_ALL_MSK,
282 RTW_PWR_ADDR_MAC,
283 RTW_PWR_CMD_WRITE, BIT(7), 0},
284 {0x0005,
285 RTW_PWR_CUT_ALL_MSK,
286 RTW_PWR_INTF_ALL_MSK,
287 RTW_PWR_ADDR_MAC,
288 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
289 {0x0005,
290 RTW_PWR_CUT_ALL_MSK,
291 RTW_PWR_INTF_ALL_MSK,
292 RTW_PWR_ADDR_MAC,
293 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
294 {0x0005,
295 RTW_PWR_CUT_ALL_MSK,
296 RTW_PWR_INTF_ALL_MSK,
297 RTW_PWR_ADDR_MAC,
298 RTW_PWR_CMD_POLLING, BIT(0), 0},
299 {0x0010,
300 RTW_PWR_CUT_ALL_MSK,
301 RTW_PWR_INTF_ALL_MSK,
302 RTW_PWR_ADDR_MAC,
303 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
304 {0x0049,
305 RTW_PWR_CUT_ALL_MSK,
306 RTW_PWR_INTF_ALL_MSK,
307 RTW_PWR_ADDR_MAC,
308 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
309 {0x0063,
310 RTW_PWR_CUT_ALL_MSK,
311 RTW_PWR_INTF_ALL_MSK,
312 RTW_PWR_ADDR_MAC,
313 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
314 {0x0062,
315 RTW_PWR_CUT_ALL_MSK,
316 RTW_PWR_INTF_ALL_MSK,
317 RTW_PWR_ADDR_MAC,
318 RTW_PWR_CMD_WRITE, BIT(1), 0},
319 {0x0058,
320 RTW_PWR_CUT_ALL_MSK,
321 RTW_PWR_INTF_ALL_MSK,
322 RTW_PWR_ADDR_MAC,
323 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
324 {0x005A,
325 RTW_PWR_CUT_ALL_MSK,
326 RTW_PWR_INTF_ALL_MSK,
327 RTW_PWR_ADDR_MAC,
328 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
329 {0x0068,
330 RTW_PWR_CUT_TEST_MSK,
331 RTW_PWR_INTF_ALL_MSK,
332 RTW_PWR_ADDR_MAC,
333 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
334 {0x0069,
335 RTW_PWR_CUT_ALL_MSK,
336 RTW_PWR_INTF_ALL_MSK,
337 RTW_PWR_ADDR_MAC,
338 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
339 {TRANS_SEQ_END},
340 };
341
342 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = {
343 {0x001f,
344 RTW_PWR_CUT_ALL_MSK,
345 RTW_PWR_INTF_ALL_MSK,
346 RTW_PWR_ADDR_MAC,
347 RTW_PWR_CMD_WRITE, 0xff, 0},
348 {0x0049,
349 RTW_PWR_CUT_ALL_MSK,
350 RTW_PWR_INTF_ALL_MSK,
351 RTW_PWR_ADDR_MAC,
352 RTW_PWR_CMD_WRITE, BIT(1), 0},
353 {0x0006,
354 RTW_PWR_CUT_ALL_MSK,
355 RTW_PWR_INTF_ALL_MSK,
356 RTW_PWR_ADDR_MAC,
357 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
358 {0x0005,
359 RTW_PWR_CUT_ALL_MSK,
360 RTW_PWR_INTF_ALL_MSK,
361 RTW_PWR_ADDR_MAC,
362 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
363 {0x0005,
364 RTW_PWR_CUT_ALL_MSK,
365 RTW_PWR_INTF_ALL_MSK,
366 RTW_PWR_ADDR_MAC,
367 RTW_PWR_CMD_POLLING, BIT(1), 0},
368 {0x0010,
369 RTW_PWR_CUT_ALL_MSK,
370 RTW_PWR_INTF_ALL_MSK,
371 RTW_PWR_ADDR_MAC,
372 RTW_PWR_CMD_WRITE, BIT(6), 0},
373 {0x0000,
374 RTW_PWR_CUT_ALL_MSK,
375 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
376 RTW_PWR_ADDR_MAC,
377 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
378 {0x0020,
379 RTW_PWR_CUT_ALL_MSK,
380 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
381 RTW_PWR_ADDR_MAC,
382 RTW_PWR_CMD_WRITE, BIT(0), 0},
383 {TRANS_SEQ_END},
384 };
385
386 static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = {
387 {REG_SYS_FUNC_EN + 1,
388 RTW_PWR_CUT_ALL_MSK,
389 RTW_PWR_INTF_SDIO_MSK,
390 RTW_PWR_ADDR_MAC,
391 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0},
392 /* reset MCU ready */
393 {REG_MCUFW_CTRL,
394 RTW_PWR_CUT_ALL_MSK,
395 RTW_PWR_INTF_SDIO_MSK,
396 RTW_PWR_ADDR_MAC,
397 RTW_PWR_CMD_WRITE, 0xff, 0},
398 /* reset MCU IO wrapper */
399 {REG_RSV_CTRL + 1,
400 RTW_PWR_CUT_ALL_MSK,
401 RTW_PWR_INTF_SDIO_MSK,
402 RTW_PWR_ADDR_MAC,
403 RTW_PWR_CMD_WRITE, BIT(0), 0},
404 {REG_RSV_CTRL + 1,
405 RTW_PWR_CUT_ALL_MSK,
406 RTW_PWR_INTF_SDIO_MSK,
407 RTW_PWR_ADDR_MAC,
408 RTW_PWR_CMD_WRITE, BIT(0), 1},
409 {TRANS_SEQ_END},
410 };
411
412 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = {
413 {0x0301,
414 RTW_PWR_CUT_ALL_MSK,
415 RTW_PWR_INTF_ALL_MSK,
416 RTW_PWR_ADDR_MAC,
417 RTW_PWR_CMD_WRITE, 0xff, 0xff},
418 {0x0522,
419 RTW_PWR_CUT_ALL_MSK,
420 RTW_PWR_INTF_ALL_MSK,
421 RTW_PWR_ADDR_MAC,
422 RTW_PWR_CMD_WRITE, 0xff, 0xff},
423 {0x05f8,
424 RTW_PWR_CUT_ALL_MSK,
425 RTW_PWR_INTF_ALL_MSK,
426 RTW_PWR_ADDR_MAC,
427 RTW_PWR_CMD_POLLING, 0xff, 0},
428 {0x05f9,
429 RTW_PWR_CUT_ALL_MSK,
430 RTW_PWR_INTF_ALL_MSK,
431 RTW_PWR_ADDR_MAC,
432 RTW_PWR_CMD_POLLING, 0xff, 0},
433 {0x05fa,
434 RTW_PWR_CUT_ALL_MSK,
435 RTW_PWR_INTF_ALL_MSK,
436 RTW_PWR_ADDR_MAC,
437 RTW_PWR_CMD_POLLING, 0xff, 0},
438 {0x05fb,
439 RTW_PWR_CUT_ALL_MSK,
440 RTW_PWR_INTF_ALL_MSK,
441 RTW_PWR_ADDR_MAC,
442 RTW_PWR_CMD_POLLING, 0xff, 0},
443 {0x0002,
444 RTW_PWR_CUT_ALL_MSK,
445 RTW_PWR_INTF_ALL_MSK,
446 RTW_PWR_ADDR_MAC,
447 RTW_PWR_CMD_WRITE, BIT(0), 0},
448 {0x0002,
449 RTW_PWR_CUT_ALL_MSK,
450 RTW_PWR_INTF_ALL_MSK,
451 RTW_PWR_ADDR_MAC,
452 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
453 {0x0002,
454 RTW_PWR_CUT_ALL_MSK,
455 RTW_PWR_INTF_ALL_MSK,
456 RTW_PWR_ADDR_MAC,
457 RTW_PWR_CMD_WRITE, BIT(1), 0},
458 {0x0100,
459 RTW_PWR_CUT_ALL_MSK,
460 RTW_PWR_INTF_ALL_MSK,
461 RTW_PWR_ADDR_MAC,
462 RTW_PWR_CMD_WRITE, 0xff, 0x03},
463 {0x0101,
464 RTW_PWR_CUT_ALL_MSK,
465 RTW_PWR_INTF_ALL_MSK,
466 RTW_PWR_ADDR_MAC,
467 RTW_PWR_CMD_WRITE, BIT(1), 0},
468 {0x0093,
469 RTW_PWR_CUT_ALL_MSK,
470 RTW_PWR_INTF_SDIO_MSK,
471 RTW_PWR_ADDR_MAC,
472 RTW_PWR_CMD_WRITE, 0xff, 0},
473 {0x0553,
474 RTW_PWR_CUT_ALL_MSK,
475 RTW_PWR_INTF_ALL_MSK,
476 RTW_PWR_ADDR_MAC,
477 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
478 {TRANS_SEQ_END},
479 };
480
481 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8703b[] = {
482 trans_pre_enable_8703b,
483 trans_carddis_to_cardemu_8703b,
484 trans_cardemu_to_act_8703b,
485 NULL
486 };
487
488 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8703b[] = {
489 trans_act_to_lps_8703b,
490 trans_act_to_reset_mcu_8703b,
491 trans_act_to_cardemu_8703b,
492 trans_cardemu_to_carddis_8703b,
493 NULL
494 };
495
496 static const struct rtw_page_table page_table_8703b[] = {
497 {12, 2, 2, 0, 1},
498 {12, 2, 2, 0, 1},
499 {12, 2, 2, 0, 1},
500 {12, 2, 2, 0, 1},
501 {12, 2, 2, 0, 1},
502 };
503
504 static const struct rtw_rqpn rqpn_table_8703b[] = {
505 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
506 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
507 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
508 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
509 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
510 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
511 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
512 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
513 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
514 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
515 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
516 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
517 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
518 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
519 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
520 };
521
try_mac_from_devicetree(struct rtw_dev * rtwdev)522 static void try_mac_from_devicetree(struct rtw_dev *rtwdev)
523 {
524 #if defined(CONFIG_OF)
525 struct device_node *node = rtwdev->dev->of_node;
526 struct rtw_efuse *efuse = &rtwdev->efuse;
527 int ret;
528
529 if (node) {
530 ret = of_get_mac_address(node, efuse->addr);
531 if (ret == 0) {
532 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
533 "got wifi mac address from DT: %pM\n",
534 efuse->addr);
535 }
536 }
537 #endif
538 }
539
rtw8703b_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)540 static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
541 {
542 struct rtw_efuse *efuse = &rtwdev->efuse;
543 int ret;
544
545 ret = rtw8723x_read_efuse(rtwdev, log_map);
546 if (ret != 0)
547 return ret;
548
549 if (!is_valid_ether_addr(efuse->addr))
550 try_mac_from_devicetree(rtwdev);
551
552 return 0;
553 }
554
rtw8703b_pwrtrack_init(struct rtw_dev * rtwdev)555 static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev)
556 {
557 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
558 u8 path;
559
560 /* TODO: The vendor driver selects these using tables in
561 * halrf_powertracking_ce.c, functions are called
562 * get_swing_index and get_cck_swing_index. There the current
563 * fixed values are only the defaults in case no match is
564 * found.
565 */
566 dm_info->default_ofdm_index = 30;
567 dm_info->default_cck_index = 20;
568
569 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
570 ewma_thermal_init(&dm_info->avg_thermal[path]);
571 dm_info->delta_power_index[path] = 0;
572 }
573 dm_info->pwr_trk_triggered = false;
574 dm_info->pwr_trk_init_trigger = true;
575 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
576 dm_info->txagc_remnant_cck = 0;
577 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0;
578 }
579
rtw8703b_phy_set_param(struct rtw_dev * rtwdev)580 static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev)
581 {
582 u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
583
584 /* power on BB/RF domain */
585 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
586 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
587 rtw_write8_set(rtwdev, REG_RF_CTRL,
588 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
589 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780);
590 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
591
592 rtw_phy_load_tables(rtwdev);
593
594 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
595 /* 0xff is from vendor driver, rtw8723d uses
596 * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet
597 * in Hi Queue Tx immediately". I wonder if setting all bits
598 * is really necessary.
599 */
600 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);
601 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
602
603 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
604 xtal_cap | (xtal_cap << 6));
605 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
606
607 /* Init EDCA */
608 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS);
609 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
610 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */
611 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */
612 /* TXOP */
613 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
614 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
615 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
616 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
617
618 /* Init retry */
619 rtw_write8(rtwdev, REG_ACKTO, 0x40);
620
621 /* Set up RX aggregation. sdio.c also sets DMA mode, but not
622 * the burst parameters.
623 */
624 rtw_write8(rtwdev, REG_RXDMA_MODE,
625 BIT_DMA_MODE |
626 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) |
627 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE));
628
629 /* Init beacon parameters */
630 rtw_write8(rtwdev, REG_BCN_CTRL,
631 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
632 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
633 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1,
634 TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
635 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2,
636 (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0)
637 | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
638
639 /* configure packet burst */
640 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
641 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
642 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
643 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
644 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT);
645 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
646
647 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
648 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
649 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
650 rtw_write16(rtwdev, REG_ATIMWND, 0x2);
651
652 rtw_phy_init(rtwdev);
653
654 if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) {
655 rtwdev->dm_info.rx_cck_agc_report_type = 1;
656 } else {
657 rtwdev->dm_info.rx_cck_agc_report_type = 0;
658 rtw_warn(rtwdev, "unexpected cck agc report type");
659 }
660
661 rtw8723x_lck(rtwdev);
662
663 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
664 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
665
666 rtw8703b_pwrtrack_init(rtwdev);
667 }
668
rtw8703b_check_spur_ov_thres(struct rtw_dev * rtwdev,u32 freq,u32 thres)669 static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev,
670 u32 freq, u32 thres)
671 {
672 bool ret = false;
673
674 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
675 rtw_write32(rtwdev, REG_PSDFN, freq);
676 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
677
678 msleep(30);
679 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
680 ret = true;
681
682 rtw_write32(rtwdev, REG_PSDFN, freq);
683 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
684
685 return ret;
686 }
687
rtw8703b_cfg_notch(struct rtw_dev * rtwdev,u8 channel,bool notch)688 static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
689 {
690 if (!notch) {
691 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
692 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
693 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
694 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
695 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
696 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
697 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
698 return;
699 }
700
701 switch (channel) {
702 case 5:
703 fallthrough;
704 case 13:
705 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
706 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
707 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000);
708 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
709 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
710 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
711 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
712 break;
713 case 6:
714 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4);
715 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
716 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600);
717 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
718 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
719 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
720 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
721 break;
722 case 7:
723 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3);
724 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
725 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
726 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
727 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
728 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000);
729 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
730 break;
731 case 8:
732 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa);
733 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
734 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
735 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
736 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
737 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380);
738 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
739 break;
740 case 14:
741 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
742 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
743 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
744 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
745 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
746 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000);
747 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
748 break;
749 default:
750 rtw_warn(rtwdev,
751 "Bug: Notch filter enable called for channel %u!",
752 channel);
753 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
754 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
755 break;
756 }
757 }
758
rtw8703b_spur_cal(struct rtw_dev * rtwdev,u8 channel)759 static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel)
760 {
761 bool notch;
762 u32 freq;
763
764 if (channel == 5) {
765 freq = FREQ_CH5;
766 } else if (channel == 6) {
767 freq = FREQ_CH6;
768 } else if (channel == 7) {
769 freq = FREQ_CH7;
770 } else if (channel == 8) {
771 freq = FREQ_CH8;
772 } else if (channel == 13) {
773 freq = FREQ_CH13;
774 } else if (channel == 14) {
775 freq = FREQ_CH14;
776 } else {
777 rtw8703b_cfg_notch(rtwdev, channel, false);
778 return;
779 }
780
781 notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES);
782 rtw8703b_cfg_notch(rtwdev, channel, notch);
783 }
784
rtw8703b_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)785 static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
786 {
787 u32 rf_cfgch_a;
788 u32 rf_cfgch_b;
789 /* default value for 20M */
790 u32 rf_rck = 0x00000C08;
791
792 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
793 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
794
795 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
796 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
797 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
798 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
799
800 rf_cfgch_a &= ~RFCFGCH_BW_MASK;
801 switch (bw) {
802 case RTW_CHANNEL_WIDTH_20:
803 rf_cfgch_a |= RFCFGCH_BW_20M;
804 break;
805 case RTW_CHANNEL_WIDTH_40:
806 rf_cfgch_a |= RFCFGCH_BW_40M;
807 rf_rck = 0x00000C4C;
808 break;
809 default:
810 break;
811 }
812
813 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
814 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
815
816 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck);
817 rtw8703b_spur_cal(rtwdev, channel);
818 }
819
820 #define CCK_DFIR_NR_8703B 2
821 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = {
822 [0] = {
823 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD },
824 { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B },
825 },
826 [1] = {
827 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 },
828 { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 },
829 },
830 };
831
rtw8703b_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)832 static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
833 u8 primary_ch_idx)
834 {
835 const struct rtw_backup_info *cck_dfir;
836 int i;
837
838 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
839
840 for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++)
841 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
842
843 switch (bw) {
844 case RTW_CHANNEL_WIDTH_20:
845 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
846 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
847 rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE,
848 GENMASK(31, 30), 0x0);
849 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000);
850 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000);
851 break;
852 case RTW_CHANNEL_WIDTH_40:
853 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
854 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
855 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000);
856 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000);
857 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
858 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0);
859 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00,
860 primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1);
861
862 rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26),
863 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2);
864 break;
865 default:
866 break;
867 }
868 }
869
rtw8703b_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)870 static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel,
871 u8 bw, u8 primary_chan_idx)
872 {
873 rtw8703b_set_channel_rf(rtwdev, channel, bw);
874 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
875 rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
876 }
877
878 /* Not all indices are valid, based on available data. None of the
879 * known valid values are positive, so use 0x7f as "invalid".
880 */
881 #define LNA_IDX_INVALID 0x7f
882 static const s8 lna_gain_table[16] = {
883 -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID,
884 -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19,
885 -32, LNA_IDX_INVALID, -36, -42,
886 LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48,
887 };
888
get_cck_rx_pwr(struct rtw_dev * rtwdev,u8 lna_idx,u8 vga_idx)889 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
890 {
891 s8 lna_gain = 0;
892
893 if (lna_idx < ARRAY_SIZE(lna_gain_table))
894 lna_gain = lna_gain_table[lna_idx];
895
896 if (lna_gain >= 0) {
897 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
898 return -120;
899 }
900
901 return lna_gain - 2 * vga_idx;
902 }
903
query_phy_status_cck(struct rtw_dev * rtwdev,u8 * phy_raw,struct rtw_rx_pkt_stat * pkt_stat)904 static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw,
905 struct rtw_rx_pkt_stat *pkt_stat)
906 {
907 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw;
908 u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS;
909 u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS;
910 s8 rx_power;
911
912 if (rtwdev->dm_info.rx_cck_agc_report_type == 1)
913 lna_idx = FIELD_PREP(BIT_LNA_H_MASK,
914 phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT)
915 | FIELD_PREP(BIT_LNA_L_MASK, lna_idx);
916 else
917 lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx);
918 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
919
920 pkt_stat->rx_power[RF_PATH_A] = rx_power;
921 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
922 rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi;
923 pkt_stat->signal_power = rx_power;
924 }
925
query_phy_status_ofdm(struct rtw_dev * rtwdev,u8 * phy_raw,struct rtw_rx_pkt_stat * pkt_stat)926 static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw,
927 struct rtw_rx_pkt_stat *pkt_stat)
928 {
929 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw;
930 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
931 s8 val_s8;
932
933 val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F;
934 pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110;
935 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
936 pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2);
937
938 /* signal power reported by HW */
939 val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1;
940 pkt_stat->signal_power = (val_s8 & 0x7f) - 110;
941
942 pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A];
943 pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A];
944
945 dm_info->curr_rx_rate = pkt_stat->rate;
946 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
947 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1;
948 /* convert to KHz (used only for debugfs) */
949 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1;
950
951 /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0
952 * range. rx_evm_dbm needs the absolute (positive) value.
953 */
954 val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A];
955 val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64);
956 val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
957 dm_info->rx_evm_dbm[RF_PATH_A] = val_s8;
958 }
959
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)960 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
961 struct rtw_rx_pkt_stat *pkt_stat)
962 {
963 if (pkt_stat->rate <= DESC_RATE11M)
964 query_phy_status_cck(rtwdev, phy_status, pkt_stat);
965 else
966 query_phy_status_ofdm(rtwdev, phy_status, pkt_stat);
967 }
968
969 #define ADDA_ON_VAL_8703B 0x03c00014
970
971 static
rtw8703b_iqk_config_mac(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)972 void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev,
973 const struct rtw8723x_iqk_backup_regs *backup)
974 {
975 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F);
976 for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++)
977 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i],
978 backup->mac8[i] & (~BIT(3)));
979 }
980
981 #define IQK_LTE_WRITE_VAL_8703B 0x00007700
982 #define IQK_DELAY_TIME_8703B 4
983
rtw8703b_iqk_one_shot(struct rtw_dev * rtwdev,bool tx)984 static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx)
985 {
986 u32 regval;
987 ktime_t t;
988 s64 dur;
989 int ret;
990
991 /* enter IQK mode */
992 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
993 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B);
994
995 /* One shot, LOK & IQK */
996 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000);
997 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
998
999 t = ktime_get();
1000 msleep(IQK_DELAY_TIME_8703B);
1001 ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000,
1002 100000, false, rtwdev,
1003 REG_IQK_RDY);
1004 dur = ktime_us_delta(ktime_get(), t);
1005
1006 if (ret)
1007 #if defined(__linux__)
1008 rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n",
1009 tx ? "TX" : "RX", dur);
1010 #elif defined(__FreeBSD__)
1011 rtw_warn(rtwdev, "[IQK] %s timed out after %jdus!\n",
1012 tx ? "TX" : "RX", (intmax_t)dur);
1013 #endif
1014 else
1015 rtw_dbg(rtwdev, RTW_DBG_RFK,
1016 #if defined(__linux__)
1017 "[IQK] %s done after %lldus\n",
1018 tx ? "TX" : "RX", dur);
1019 #elif defined(__FreeBSD__)
1020 "[IQK] %s done after %jdus\n",
1021 tx ? "TX" : "RX", (intmax_t)dur);
1022 #endif
1023 }
1024
rtw8703b_iqk_txrx_path_post(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1025 static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev,
1026 const struct rtw8723x_iqk_backup_regs *backup)
1027 {
1028 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup);
1029 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg);
1030
1031 /* leave IQK mode */
1032 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1033 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0);
1034 }
1035
rtw8703b_iqk_check_tx_failed(struct rtw_dev * rtwdev)1036 static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev)
1037 {
1038 s32 tx_x, tx_y;
1039 u32 tx_fail;
1040
1041 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
1042 rtw_read32(rtwdev, REG_IQK_RES_RY));
1043 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
1044 rtw_read32(rtwdev, REG_IQK_RES_TX),
1045 rtw_read32(rtwdev, REG_IQK_RES_TY));
1046 rtw_dbg(rtwdev, RTW_DBG_RFK,
1047 "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n",
1048 rtw_read32(rtwdev, REG_IQK_RDY),
1049 rtw_read32(rtwdev, 0xe98));
1050
1051 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
1052 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1053 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1054
1055 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR)
1056 return IQK_TX_OK;
1057
1058 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n");
1059
1060 return 0;
1061 }
1062
rtw8703b_iqk_check_rx_failed(struct rtw_dev * rtwdev)1063 static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev)
1064 {
1065 s32 rx_x, rx_y;
1066 u32 rx_fail;
1067
1068 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
1069 rtw_read32(rtwdev, REG_IQK_RES_RX),
1070 rtw_read32(rtwdev, REG_IQK_RES_RY));
1071
1072 rtw_dbg(rtwdev, RTW_DBG_RFK,
1073 "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n",
1074 rtw_read32(rtwdev, 0xea0),
1075 rtw_read32(rtwdev, 0xea8));
1076
1077 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
1078 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
1079 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
1080 rx_y = abs(iqkxy_to_s32(rx_y));
1081
1082 if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR &&
1083 rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER &&
1084 rx_y < IQK_RX_Y_LMT)
1085 return IQK_RX_OK;
1086
1087 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n");
1088
1089 return 0;
1090 }
1091
rtw8703b_iqk_tx_path(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1092 static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev,
1093 const struct rtw8723x_iqk_backup_regs *backup)
1094 {
1095 u8 status;
1096
1097 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n");
1098
1099 /* IQK setting */
1100 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1101 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1102 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
1103 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
1104 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1105 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1106 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);
1107 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);
1108 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);
1109 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);
1110
1111 /* LO calibration setting */
1112 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
1113
1114 /* leave IQK mode */
1115 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);
1116
1117 /* PA, PAD setting */
1118 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);
1119 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7);
1120 rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400);
1121
1122 rtw8703b_iqk_one_shot(rtwdev, true);
1123 status = rtw8703b_iqk_check_tx_failed(rtwdev);
1124
1125 rtw8703b_iqk_txrx_path_post(rtwdev, backup);
1126
1127 return status;
1128 }
1129
rtw8703b_iqk_rx_path(struct rtw_dev * rtwdev,const struct rtw8723x_iqk_backup_regs * backup)1130 static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev,
1131 const struct rtw8723x_iqk_backup_regs *backup)
1132 {
1133 u8 status;
1134 u32 tx_x, tx_y;
1135
1136 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n");
1137 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n",
1138 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
1139 rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000);
1140
1141 /* disable IQC mode */
1142 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1143
1144 /* IQK setting */
1145 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1146 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1147
1148 /* path IQK setting */
1149 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
1150 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
1151 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1152 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1153 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);
1154 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);
1155 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);
1156 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);
1157
1158 /* LOK setting */
1159 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
1160
1161 /* RX IQK mode */
1162 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);
1163 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);
1164 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);
1165 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7);
1166
1167 rtw8703b_iqk_one_shot(rtwdev, true);
1168 /* leave IQK mode */
1169 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);
1170 status = rtw8703b_iqk_check_tx_failed(rtwdev);
1171
1172 if (!status)
1173 goto restore;
1174
1175 /* second round */
1176 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1177 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1178
1179 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y));
1180 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
1181 rtw_read32(rtwdev, REG_TXIQK_11N),
1182 BIT_SET_TXIQK_11N(tx_x, tx_y));
1183
1184 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n");
1185 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n",
1186 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
1187
1188 /* IQK setting */
1189 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1190 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
1191 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
1192 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1193 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1194 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000);
1195 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f);
1196 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);
1197 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);
1198
1199 /* LO calibration setting */
1200 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
1201
1202 /* leave IQK mode */
1203 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);
1204 /* modify RX IQK mode table */
1205 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);
1206 /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */
1207 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);
1208 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);
1209 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77);
1210
1211 /* PA, PAD setting */
1212 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);
1213 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5);
1214
1215 rtw8703b_iqk_one_shot(rtwdev, false);
1216 status |= rtw8703b_iqk_check_rx_failed(rtwdev);
1217
1218 restore:
1219 rtw8703b_iqk_txrx_path_post(rtwdev, backup);
1220
1221 return status;
1222 }
1223
1224 static
rtw8703b_iqk_one_round(struct rtw_dev * rtwdev,s32 result[][IQK_NR],u8 t,const struct rtw8723x_iqk_backup_regs * backup)1225 void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t,
1226 const struct rtw8723x_iqk_backup_regs *backup)
1227 {
1228 u32 i;
1229 u8 a_ok;
1230
1231 rtw_dbg(rtwdev, RTW_DBG_RFK,
1232 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t);
1233
1234 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B);
1235 rtw8703b_iqk_config_mac(rtwdev, backup);
1236 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
1237 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600);
1238 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
1239 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000);
1240
1241 for (i = 0; i < PATH_IQK_RETRY; i++) {
1242 a_ok = rtw8703b_iqk_tx_path(rtwdev, backup);
1243 if (a_ok == IQK_TX_OK) {
1244 rtw_dbg(rtwdev, RTW_DBG_RFK,
1245 "[IQK] path A TX IQK success!\n");
1246 result[t][IQK_S1_TX_X] =
1247 rtw_read32_mask(rtwdev, REG_IQK_RES_TX,
1248 BIT_MASK_RES_TX);
1249 result[t][IQK_S1_TX_Y] =
1250 rtw_read32_mask(rtwdev, REG_IQK_RES_TY,
1251 BIT_MASK_RES_TY);
1252 break;
1253 }
1254
1255 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n");
1256 result[t][IQK_S1_TX_X] = 0x100;
1257 result[t][IQK_S1_TX_Y] = 0x0;
1258 }
1259
1260 for (i = 0; i < PATH_IQK_RETRY; i++) {
1261 a_ok = rtw8703b_iqk_rx_path(rtwdev, backup);
1262 if (a_ok == (IQK_TX_OK | IQK_RX_OK)) {
1263 rtw_dbg(rtwdev, RTW_DBG_RFK,
1264 "[IQK] path A RX IQK success!\n");
1265 result[t][IQK_S1_RX_X] =
1266 rtw_read32_mask(rtwdev, REG_IQK_RES_RX,
1267 BIT_MASK_RES_RX);
1268 result[t][IQK_S1_RX_Y] =
1269 rtw_read32_mask(rtwdev, REG_IQK_RES_RY,
1270 BIT_MASK_RES_RY);
1271 break;
1272 }
1273
1274 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n");
1275 result[t][IQK_S1_RX_X] = 0x100;
1276 result[t][IQK_S1_RX_Y] = 0x0;
1277 }
1278
1279 if (a_ok == 0x0)
1280 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n");
1281
1282 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1283 mdelay(1);
1284 }
1285
1286 static
rtw8703b_iqk_fill_a_matrix(struct rtw_dev * rtwdev,const s32 result[])1287 void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[])
1288 {
1289 u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16);
1290 s32 tx1_a, tx1_a_ext;
1291 s32 tx1_c, tx1_c_ext;
1292 s32 oldval_1;
1293 s32 x, y;
1294
1295 if (result[IQK_S1_TX_X] == 0)
1296 return;
1297
1298 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1299 BIT_MASK_TXIQ_ELM_D);
1300
1301 x = iqkxy_to_s32(result[IQK_S1_TX_X]);
1302 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext);
1303 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1304 BIT_MASK_TXIQ_ELM_A, tx1_a);
1305 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
1306 BIT_MASK_OFDM0_EXT_A, tx1_a_ext);
1307
1308 y = iqkxy_to_s32(result[IQK_S1_TX_Y]);
1309 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext);
1310 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1311 BIT_SET_TXIQ_ELM_C1(tx1_c));
1312 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1313 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c));
1314 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
1315 BIT_MASK_OFDM0_EXT_C, tx1_c_ext);
1316
1317 rtw_dbg(rtwdev, RTW_DBG_RFK,
1318 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
1319 x, tx1_a, oldval_1);
1320 rtw_dbg(rtwdev, RTW_DBG_RFK,
1321 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
1322
1323 if (result[IQK_S1_RX_X] == 0)
1324 return;
1325
1326 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]);
1327 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_Y]);
1328 rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi);
1329 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,
1330 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y]));
1331 }
1332
rtw8703b_phy_calibration(struct rtw_dev * rtwdev)1333 static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev)
1334 {
1335 /* For some reason path A is called S1 and B S0 in shared
1336 * rtw88 calibration data.
1337 */
1338 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1339 struct rtw8723x_iqk_backup_regs backup;
1340 u8 final_candidate = IQK_ROUND_INVALID;
1341 s32 result[IQK_ROUND_SIZE][IQK_NR];
1342 bool good;
1343 u8 i, j;
1344
1345 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n");
1346
1347 memset(result, 0, sizeof(result));
1348
1349 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup);
1350 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup);
1351 rtw8723x_iqk_backup_regs(rtwdev, &backup);
1352
1353 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) {
1354 rtw8723x_iqk_config_path_ctrl(rtwdev);
1355 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B);
1356
1357 rtw8703b_iqk_one_round(rtwdev, result, i, &backup);
1358
1359 rtw_dbg(rtwdev, RTW_DBG_RFK,
1360 "[IQK] back to BB mode, load original values!\n");
1361 if (i > IQK_ROUND_0)
1362 rtw8723x_iqk_restore_regs(rtwdev, &backup);
1363 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup);
1364 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup);
1365
1366 for (j = IQK_ROUND_0; j < i; j++) {
1367 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i);
1368
1369 if (good) {
1370 final_candidate = j;
1371 rtw_dbg(rtwdev, RTW_DBG_RFK,
1372 "[IQK] cmp %d:%d final_candidate is %x\n",
1373 j, i, final_candidate);
1374 goto iqk_done;
1375 }
1376 }
1377 }
1378
1379 if (final_candidate == IQK_ROUND_INVALID) {
1380 s32 reg_tmp = 0;
1381
1382 for (i = 0; i < IQK_NR; i++)
1383 reg_tmp += result[IQK_ROUND_HYBRID][i];
1384
1385 if (reg_tmp != 0) {
1386 final_candidate = IQK_ROUND_HYBRID;
1387 } else {
1388 WARN(1, "IQK failed\n");
1389 goto out;
1390 }
1391 }
1392
1393 iqk_done:
1394 /* only path A is calibrated in rtl8703b */
1395 rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]);
1396
1397 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X];
1398 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y];
1399 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X];
1400 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y];
1401 dm_info->iqk.done = true;
1402
1403 out:
1404 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg);
1405
1406 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n",
1407 final_candidate);
1408
1409 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++)
1410 rtw_dbg(rtwdev, RTW_DBG_RFK,
1411 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n",
1412 i,
1413 result[i][0], result[i][1], result[i][2], result[i][3],
1414 result[i][4], result[i][5], result[i][6], result[i][7],
1415 final_candidate == i ? "(final candidate)" : "");
1416
1417 rtw_dbg(rtwdev, RTW_DBG_RFK,
1418 "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1419 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE),
1420 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N),
1421 rtw_read32(rtwdev, REG_A_RXIQI),
1422 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N));
1423 rtw_dbg(rtwdev, RTW_DBG_RFK,
1424 "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1425 rtw_read32(rtwdev, REG_TXIQ_AB_S0),
1426 rtw_read32(rtwdev, REG_TXIQ_CD_S0),
1427 rtw_read32(rtwdev, REG_RXIQ_AB_S0));
1428
1429 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n");
1430 }
1431
rtw8703b_set_iqk_matrix_by_result(struct rtw_dev * rtwdev,u32 ofdm_swing,u8 rf_path)1432 static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev,
1433 u32 ofdm_swing, u8 rf_path)
1434 {
1435 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1436 s32 ele_A, ele_D, ele_C;
1437 s32 ele_A_ext, ele_C_ext, ele_D_ext;
1438 s32 iqk_result_x;
1439 s32 iqk_result_y;
1440 s32 value32;
1441
1442 switch (rf_path) {
1443 default:
1444 case RF_PATH_A:
1445 iqk_result_x = dm_info->iqk.result.s1_x;
1446 iqk_result_y = dm_info->iqk.result.s1_y;
1447 break;
1448 case RF_PATH_B:
1449 iqk_result_x = dm_info->iqk.result.s0_x;
1450 iqk_result_y = dm_info->iqk.result.s0_y;
1451 break;
1452 }
1453
1454 /* new element D */
1455 ele_D = OFDM_SWING_D(ofdm_swing);
1456 iqk_mult(iqk_result_x, ele_D, &ele_D_ext);
1457 /* new element A */
1458 iqk_result_x = iqkxy_to_s32(iqk_result_x);
1459 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext);
1460 /* new element C */
1461 iqk_result_y = iqkxy_to_s32(iqk_result_y);
1462 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext);
1463
1464 switch (rf_path) {
1465 case RF_PATH_A:
1466 default:
1467 /* write new elements A, C, D, and element B is always 0 */
1468 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1469 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32);
1470 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1471 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1472 value32);
1473 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1474 value32 &= ~BIT_MASK_OFDM0_EXTS;
1475 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext);
1476 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1477 break;
1478
1479 case RF_PATH_B:
1480 /* write new elements A, C, D, and element B is always 0 */
1481 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1482 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32);
1483 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1484 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS,
1485 value32);
1486 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1487 value32 &= ~BIT_MASK_OFDM0_EXTS_B;
1488 value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext);
1489 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1490 break;
1491 }
1492 }
1493
rtw8703b_set_iqk_matrix(struct rtw_dev * rtwdev,s8 ofdm_index,u8 rf_path)1494 static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index,
1495 u8 rf_path)
1496 {
1497 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1498 s32 value32;
1499 u32 ofdm_swing;
1500
1501 ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1);
1502
1503 ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index];
1504
1505 if (dm_info->iqk.done) {
1506 rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path);
1507 return;
1508 }
1509
1510 switch (rf_path) {
1511 case RF_PATH_A:
1512 default:
1513 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing);
1514 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1515 0x00);
1516
1517 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1518 value32 &= ~BIT_MASK_OFDM0_EXTS;
1519 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1520 break;
1521
1522 case RF_PATH_B:
1523 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing);
1524 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS,
1525 0x00);
1526
1527 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1528 value32 &= ~BIT_MASK_OFDM0_EXTS_B;
1529 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1530 break;
1531 }
1532 }
1533
rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev * rtwdev,s8 swing_idx,s8 txagc_idx)1534 static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1535 s8 txagc_idx)
1536 {
1537 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1538
1539 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx;
1540
1541 /* Only path A is calibrated for rtl8703b */
1542 rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A);
1543 }
1544
rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev * rtwdev,s8 swing_idx,s8 txagc_idx)1545 static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1546 s8 txagc_idx)
1547 {
1548 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1549
1550 dm_info->txagc_remnant_cck = txagc_idx;
1551
1552 swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1);
1553
1554 BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs)
1555 != ARRAY_SIZE(rtw8703b_cck_swing_table[0]));
1556
1557 for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++)
1558 rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i],
1559 rtw8703b_cck_swing_table[swing_idx][i]);
1560 }
1561
rtw8703b_pwrtrack_set(struct rtw_dev * rtwdev,u8 path)1562 static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1563 {
1564 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1565 struct rtw_hal *hal = &rtwdev->hal;
1566 u8 limit_ofdm;
1567 u8 limit_cck = 21;
1568 s8 final_ofdm_swing_index;
1569 s8 final_cck_swing_index;
1570
1571 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev);
1572
1573 final_ofdm_swing_index = dm_info->default_ofdm_index +
1574 dm_info->delta_power_index[path];
1575 final_cck_swing_index = dm_info->default_cck_index +
1576 dm_info->delta_power_index[path];
1577
1578 if (final_ofdm_swing_index > limit_ofdm)
1579 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm,
1580 final_ofdm_swing_index - limit_ofdm);
1581 else if (final_ofdm_swing_index < 0)
1582 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1583 final_ofdm_swing_index);
1584 else
1585 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1586
1587 if (final_cck_swing_index > limit_cck)
1588 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck,
1589 final_cck_swing_index - limit_cck);
1590 else if (final_cck_swing_index < 0)
1591 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0,
1592 final_cck_swing_index);
1593 else
1594 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1595
1596 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel);
1597 }
1598
rtw8703b_phy_pwrtrack(struct rtw_dev * rtwdev)1599 static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev)
1600 {
1601 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1602 struct rtw_swing_table swing_table;
1603 u8 thermal_value, delta, path;
1604 bool do_iqk = false;
1605
1606 rtw_phy_config_swing_table(rtwdev, &swing_table);
1607
1608 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1609 return;
1610
1611 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1612
1613 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1614
1615 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1616
1617 if (do_iqk)
1618 rtw8723x_lck(rtwdev);
1619
1620 if (dm_info->pwr_trk_init_trigger)
1621 dm_info->pwr_trk_init_trigger = false;
1622 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1623 RF_PATH_A))
1624 goto iqk;
1625
1626 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1627
1628 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1629
1630 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1631 s8 delta_cur, delta_last;
1632
1633 delta_last = dm_info->delta_power_index[path];
1634 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table,
1635 path, RF_PATH_A, delta);
1636 if (delta_last == delta_cur)
1637 continue;
1638
1639 dm_info->delta_power_index[path] = delta_cur;
1640 rtw8703b_pwrtrack_set(rtwdev, path);
1641 }
1642
1643 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta);
1644
1645 iqk:
1646 if (do_iqk)
1647 rtw8703b_phy_calibration(rtwdev);
1648 }
1649
rtw8703b_pwr_track(struct rtw_dev * rtwdev)1650 static void rtw8703b_pwr_track(struct rtw_dev *rtwdev)
1651 {
1652 struct rtw_efuse *efuse = &rtwdev->efuse;
1653 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1654
1655 if (efuse->power_track_type != 0) {
1656 rtw_warn(rtwdev, "unsupported power track type");
1657 return;
1658 }
1659
1660 if (!dm_info->pwr_trk_triggered) {
1661 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1662 GENMASK(17, 16), 0x03);
1663 dm_info->pwr_trk_triggered = true;
1664 return;
1665 }
1666
1667 rtw8703b_phy_pwrtrack(rtwdev);
1668 dm_info->pwr_trk_triggered = false;
1669 }
1670
rtw8703b_coex_set_gnt_fix(struct rtw_dev * rtwdev)1671 static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev)
1672 {
1673 }
1674
rtw8703b_coex_set_gnt_debug(struct rtw_dev * rtwdev)1675 static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev)
1676 {
1677 }
1678
rtw8703b_coex_set_rfe_type(struct rtw_dev * rtwdev)1679 static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev)
1680 {
1681 struct rtw_coex *coex = &rtwdev->coex;
1682 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1683
1684 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1685 coex_rfe->ant_switch_polarity = 0;
1686 coex_rfe->ant_switch_exist = false;
1687 coex_rfe->ant_switch_with_bt = false;
1688 coex_rfe->ant_switch_diversity = false;
1689 coex_rfe->wlg_at_btg = true;
1690
1691 /* disable LTE coex on wifi side */
1692 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1693 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1694 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1695 }
1696
rtw8703b_coex_set_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)1697 static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1698 {
1699 }
1700
rtw8703b_coex_set_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1701 static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1702 {
1703 }
1704
1705 static const u8 rtw8703b_pwrtrk_2gb_n[] = {
1706 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1707 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1708 };
1709
1710 static const u8 rtw8703b_pwrtrk_2gb_p[] = {
1711 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1712 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15
1713 };
1714
1715 static const u8 rtw8703b_pwrtrk_2ga_n[] = {
1716 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1717 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1718 };
1719
1720 static const u8 rtw8703b_pwrtrk_2ga_p[] = {
1721 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1722 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15
1723 };
1724
1725 static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = {
1726 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1727 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1728 };
1729
1730 static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = {
1731 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1732 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13
1733 };
1734
1735 static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = {
1736 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1737 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
1738 };
1739
1740 static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = {
1741 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1742 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13
1743 };
1744
1745 static const s8 rtw8703b_pwrtrk_xtal_n[] = {
1746 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3,
1747 -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1
1748 };
1749
1750 static const s8 rtw8703b_pwrtrk_xtal_p[] = {
1751 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1,
1752 -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30
1753 };
1754
1755 static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = {
1756 .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n,
1757 .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p,
1758 .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n,
1759 .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p,
1760 .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n,
1761 .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p,
1762 .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n,
1763 .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p,
1764 .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n,
1765 .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p,
1766 };
1767
1768 static const struct rtw_rfe_def rtw8703b_rfe_defs[] = {
1769 [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl,
1770 .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl,
1771 .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, },
1772 };
1773
1774 /* Shared-Antenna Coex Table */
1775 static const struct coex_table_para table_sant_8703b[] = {
1776 {0xffffffff, 0xffffffff}, /* case-0 */
1777 {0x55555555, 0x55555555},
1778 {0x66555555, 0x66555555},
1779 {0xaaaaaaaa, 0xaaaaaaaa},
1780 {0x5a5a5a5a, 0x5a5a5a5a},
1781 {0xfafafafa, 0xfafafafa}, /* case-5 */
1782 {0x6a5a5555, 0xaaaaaaaa},
1783 {0x6a5a56aa, 0x6a5a56aa},
1784 {0x6a5a5a5a, 0x6a5a5a5a},
1785 {0x66555555, 0x5a5a5a5a},
1786 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1787 {0x66555555, 0x6a5a5aaa},
1788 {0x66555555, 0x5a5a5aaa},
1789 {0x66555555, 0x6aaa5aaa},
1790 {0x66555555, 0xaaaa5aaa},
1791 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1792 {0xffff55ff, 0xfafafafa},
1793 {0xffff55ff, 0x6afa5afa},
1794 {0xaaffffaa, 0xfafafafa},
1795 {0xaa5555aa, 0x5a5a5a5a},
1796 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1797 {0xaa5555aa, 0xaaaaaaaa},
1798 {0xffffffff, 0x5a5a5a5a},
1799 {0xffffffff, 0x5a5a5a5a},
1800 {0xffffffff, 0x55555555},
1801 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1802 {0x55555555, 0x5a5a5a5a},
1803 {0x55555555, 0xaaaaaaaa},
1804 {0x55555555, 0x6a5a6a5a},
1805 {0x66556655, 0x66556655},
1806 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1807 {0xffffffff, 0x5aaa5aaa},
1808 {0x56555555, 0x5a5a5aaa},
1809 };
1810
1811 /* Shared-Antenna TDMA */
1812 static const struct coex_tdma_para tdma_sant_8703b[] = {
1813 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1814 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1815 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1816 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1817 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1818 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1819 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1820 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1821 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1822 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1823 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1824 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1825 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1826 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1827 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1828 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1829 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1830 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1831 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1832 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1833 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1834 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1835 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1836 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1837 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1838 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1839 { {0x51, 0x08, 0x03, 0x10, 0x50} },
1840 { {0x61, 0x08, 0x03, 0x11, 0x11} },
1841 };
1842
1843 static const struct rtw_chip_ops rtw8703b_ops = {
1844 .power_on = rtw_power_on,
1845 .power_off = rtw_power_off,
1846 .mac_init = rtw8723x_mac_init,
1847 .mac_postinit = rtw8723x_mac_postinit,
1848 .dump_fw_crash = NULL,
1849 .shutdown = NULL,
1850 .read_efuse = rtw8703b_read_efuse,
1851 .phy_set_param = rtw8703b_phy_set_param,
1852 .set_channel = rtw8703b_set_channel,
1853 .query_phy_status = query_phy_status,
1854 .read_rf = rtw_phy_read_rf_sipi,
1855 .write_rf = rtw_phy_write_rf_reg_sipi,
1856 .set_tx_power_index = rtw8723x_set_tx_power_index,
1857 .set_antenna = NULL,
1858 .cfg_ldo25 = rtw8723x_cfg_ldo25,
1859 .efuse_grant = rtw8723x_efuse_grant,
1860 .set_ampdu_factor = NULL,
1861 .false_alarm_statistics = rtw8723x_false_alarm_statistics,
1862 .phy_calibration = rtw8703b_phy_calibration,
1863 .dpk_track = NULL,
1864 /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which
1865 * is used in its cck_pd_set function. According to comments
1866 * in the vendor driver code it doesn't exist in this chip
1867 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only
1868 * *written* to).
1869 */
1870 .cck_pd_set = NULL,
1871 .pwr_track = rtw8703b_pwr_track,
1872 .config_bfee = NULL,
1873 .set_gid_table = NULL,
1874 .cfg_csi_rate = NULL,
1875 .adaptivity_init = NULL,
1876 .adaptivity = NULL,
1877 .cfo_init = NULL,
1878 .cfo_track = NULL,
1879 .config_tx_path = NULL,
1880 .config_txrx_mode = NULL,
1881 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum,
1882
1883 /* for coex */
1884 .coex_set_init = rtw8723x_coex_cfg_init,
1885 .coex_set_ant_switch = NULL,
1886 .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix,
1887 .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug,
1888 .coex_set_rfe_type = rtw8703b_coex_set_rfe_type,
1889 .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power,
1890 .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain,
1891 };
1892
1893 const struct rtw_chip_info rtw8703b_hw_spec = {
1894 .ops = &rtw8703b_ops,
1895 .id = RTW_CHIP_TYPE_8703B,
1896
1897 .fw_name = "rtw88/rtw8703b_fw.bin",
1898 .wlan_cpu = RTW_WCPU_8051,
1899 .tx_pkt_desc_sz = 40,
1900 .tx_buf_desc_sz = 16,
1901 .rx_pkt_desc_sz = 24,
1902 .rx_buf_desc_sz = 8,
1903 .phy_efuse_size = 256,
1904 .log_efuse_size = 512,
1905 .ptct_efuse_size = 15,
1906 .txff_size = 32768,
1907 .rxff_size = 16384,
1908 .rsvd_drv_pg_num = 8,
1909 .band = RTW_BAND_2G,
1910 .page_size = TX_PAGE_SIZE,
1911 .csi_buf_pg_num = 0,
1912 .dig_min = 0x20,
1913 .txgi_factor = 1,
1914 .is_pwr_by_rate_dec = true,
1915 .rx_ldpc = false,
1916 .tx_stbc = false,
1917 .max_power_index = 0x3f,
1918 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1919 .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */
1920 .hw_feature_report = true,
1921 .c2h_ra_report_size = 7,
1922 .old_datarate_fb_limit = true,
1923
1924 .path_div_supported = false,
1925 .ht_supported = true,
1926 .vht_supported = false,
1927 .lps_deep_mode_supported = 0,
1928
1929 .sys_func_en = 0xFD,
1930 .pwr_on_seq = card_enable_flow_8703b,
1931 .pwr_off_seq = card_disable_flow_8703b,
1932 .rqpn_table = rqpn_table_8703b,
1933 .prioq_addrs = &rtw8723x_common.prioq_addrs,
1934 .page_table = page_table_8703b,
1935 /* used only in pci.c, not needed for SDIO devices */
1936 .intf_table = NULL,
1937
1938 .dig = rtw8723x_common.dig,
1939 .dig_cck = rtw8723x_common.dig_cck,
1940
1941 .rf_sipi_addr = {0x840, 0x844},
1942 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr,
1943 .fix_rf_phy_num = 2,
1944 .ltecoex_addr = &rtw8723x_common.ltecoex_addr,
1945
1946 .mac_tbl = &rtw8703b_mac_tbl,
1947 .agc_tbl = &rtw8703b_agc_tbl,
1948 .bb_tbl = &rtw8703b_bb_tbl,
1949 .rf_tbl = {&rtw8703b_rf_a_tbl},
1950
1951 .rfe_defs = rtw8703b_rfe_defs,
1952 .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs),
1953
1954 .iqk_threshold = 8,
1955
1956 /* WOWLAN firmware exists, but not implemented yet */
1957 .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin",
1958 .wowlan_stub = NULL,
1959 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
1960
1961 /* Vendor driver has a time-based format, converted from
1962 * 20180330
1963 */
1964 .coex_para_ver = 0x0133ed6a,
1965 .bt_desired_ver = 0x1c,
1966 .scbd_support = true,
1967 .new_scbd10_def = true,
1968 .ble_hid_profile_support = false,
1969 .wl_mimo_ps_support = false,
1970 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
1971 .bt_rssi_type = COEX_BTRSSI_RATIO,
1972 .ant_isolation = 15,
1973 .rssi_tolerance = 2,
1974 .bt_rssi_step = bt_rssi_step_8703b,
1975 .wl_rssi_step = wl_rssi_step_8703b,
1976 /* sant -> shared antenna, nsant -> non-shared antenna
1977 * Not sure if 8703b versions with non-shard antenna even exist.
1978 */
1979 .table_sant_num = ARRAY_SIZE(table_sant_8703b),
1980 .table_sant = table_sant_8703b,
1981 .table_nsant_num = 0,
1982 .table_nsant = NULL,
1983 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b),
1984 .tdma_sant = tdma_sant_8703b,
1985 .tdma_nsant_num = 0,
1986 .tdma_nsant = NULL,
1987 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b),
1988 .wl_rf_para_tx = rf_para_tx_8703b,
1989 .wl_rf_para_rx = rf_para_rx_8703b,
1990 .bt_afh_span_bw20 = 0x20,
1991 .bt_afh_span_bw40 = 0x30,
1992 .afh_5g_num = ARRAY_SIZE(afh_5g_8703b),
1993 .afh_5g = afh_5g_8703b,
1994 /* REG_BTG_SEL doesn't seem to have a counterpart in the
1995 * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3.
1996 *
1997 * It is used in the cardemu_to_act power sequence by though
1998 * (by address, 0x0067), comment: "0x67[0] = 0 to disable
1999 * BT_GPS_SEL pins" That seems to fit.
2000 */
2001 .btg_reg = NULL,
2002 /* These registers are used to read (and print) from if
2003 * CONFIG_RTW88_DEBUGFS is enabled.
2004 */
2005 .coex_info_hw_regs_num = 0,
2006 .coex_info_hw_regs = NULL,
2007 };
2008 EXPORT_SYMBOL(rtw8703b_hw_spec);
2009
2010 MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin");
2011 MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin");
2012
2013 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>");
2014 MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver");
2015 MODULE_LICENSE("Dual BSD/GPL");
2016