1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9 #include <asm/perf_event.h>
10 #include <asm/posted_intr.h>
11
12 #include "capabilities.h"
13 #include "../kvm_cache_regs.h"
14 #include "vmcs.h"
15 #include "vmx_ops.h"
16 #include "../cpuid.h"
17 #include "run_flags.h"
18 #include "../mmu.h"
19
20 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
21
22 #ifdef CONFIG_X86_64
23 #define MAX_NR_USER_RETURN_MSRS 7
24 #else
25 #define MAX_NR_USER_RETURN_MSRS 4
26 #endif
27
28 #define MAX_NR_LOADSTORE_MSRS 8
29
30 struct vmx_msrs {
31 unsigned int nr;
32 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
33 };
34
35 struct vmx_uret_msr {
36 bool load_into_hardware;
37 u64 data;
38 u64 mask;
39 };
40
41 enum segment_cache_field {
42 SEG_FIELD_SEL = 0,
43 SEG_FIELD_BASE = 1,
44 SEG_FIELD_LIMIT = 2,
45 SEG_FIELD_AR = 3,
46
47 SEG_FIELD_NR = 4
48 };
49
50 #define RTIT_ADDR_RANGE 4
51
52 struct pt_ctx {
53 u64 ctl;
54 u64 status;
55 u64 output_base;
56 u64 output_mask;
57 u64 cr3_match;
58 u64 addr_a[RTIT_ADDR_RANGE];
59 u64 addr_b[RTIT_ADDR_RANGE];
60 };
61
62 struct pt_desc {
63 u64 ctl_bitmask;
64 u32 num_address_ranges;
65 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
66 struct pt_ctx host;
67 struct pt_ctx guest;
68 };
69
70 union vmx_exit_reason {
71 struct {
72 u32 basic : 16;
73 u32 reserved16 : 1;
74 u32 reserved17 : 1;
75 u32 reserved18 : 1;
76 u32 reserved19 : 1;
77 u32 reserved20 : 1;
78 u32 reserved21 : 1;
79 u32 reserved22 : 1;
80 u32 reserved23 : 1;
81 u32 reserved24 : 1;
82 u32 reserved25 : 1;
83 u32 bus_lock_detected : 1;
84 u32 enclave_mode : 1;
85 u32 smi_pending_mtf : 1;
86 u32 smi_from_vmx_root : 1;
87 u32 reserved30 : 1;
88 u32 failed_vmentry : 1;
89 };
90 u32 full;
91 };
92
93 struct lbr_desc {
94 /* Basic info about guest LBR records. */
95 struct x86_pmu_lbr records;
96
97 /*
98 * Emulate LBR feature via passthrough LBR registers when the
99 * per-vcpu guest LBR event is scheduled on the current pcpu.
100 *
101 * The records may be inaccurate if the host reclaims the LBR.
102 */
103 struct perf_event *event;
104
105 /* True if LBRs are marked as not intercepted in the MSR bitmap */
106 bool msr_passthrough;
107 };
108
109 extern struct x86_pmu_lbr vmx_lbr_caps;
110
111 /*
112 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
113 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
114 */
115 struct nested_vmx {
116 /* Has the level1 guest done vmxon? */
117 bool vmxon;
118 gpa_t vmxon_ptr;
119 bool pml_full;
120
121 /* The guest-physical address of the current VMCS L1 keeps for L2 */
122 gpa_t current_vmptr;
123 /*
124 * Cache of the guest's VMCS, existing outside of guest memory.
125 * Loaded from guest memory during VMPTRLD. Flushed to guest
126 * memory during VMCLEAR and VMPTRLD.
127 */
128 struct vmcs12 *cached_vmcs12;
129 /*
130 * Cache of the guest's shadow VMCS, existing outside of guest
131 * memory. Loaded from guest memory during VM entry. Flushed
132 * to guest memory during VM exit.
133 */
134 struct vmcs12 *cached_shadow_vmcs12;
135
136 /*
137 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
138 */
139 struct gfn_to_hva_cache shadow_vmcs12_cache;
140
141 /*
142 * GPA to HVA cache for VMCS12
143 */
144 struct gfn_to_hva_cache vmcs12_cache;
145
146 /*
147 * Indicates if the shadow vmcs or enlightened vmcs must be updated
148 * with the data held by struct vmcs12.
149 */
150 bool need_vmcs12_to_shadow_sync;
151 bool dirty_vmcs12;
152
153 /*
154 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
155 * changes in MSR bitmap for L1 or switching to a different L2. Note,
156 * this flag can only be used reliably in conjunction with a paravirt L1
157 * which informs L0 whether any changes to MSR bitmap for L2 were done
158 * on its side.
159 */
160 bool force_msr_bitmap_recalc;
161
162 /*
163 * Indicates lazily loaded guest state has not yet been decached from
164 * vmcs02.
165 */
166 bool need_sync_vmcs02_to_vmcs12_rare;
167
168 /*
169 * vmcs02 has been initialized, i.e. state that is constant for
170 * vmcs02 has been written to the backing VMCS. Initialization
171 * is delayed until L1 actually attempts to run a nested VM.
172 */
173 bool vmcs02_initialized;
174
175 bool change_vmcs01_virtual_apic_mode;
176 bool reload_vmcs01_apic_access_page;
177 bool update_vmcs01_cpu_dirty_logging;
178 bool update_vmcs01_apicv_status;
179 bool update_vmcs01_hwapic_isr;
180
181 /*
182 * Enlightened VMCS has been enabled. It does not mean that L1 has to
183 * use it. However, VMX features available to L1 will be limited based
184 * on what the enlightened VMCS supports.
185 */
186 bool enlightened_vmcs_enabled;
187
188 /* L2 must run next, and mustn't decide to exit to L1. */
189 bool nested_run_pending;
190
191 /* Pending MTF VM-exit into L1. */
192 bool mtf_pending;
193
194 struct loaded_vmcs vmcs02;
195
196 /*
197 * Guest pages referred to in the vmcs02 with host-physical
198 * pointers, so we must keep them pinned while L2 runs.
199 */
200 struct kvm_host_map apic_access_page_map;
201 struct kvm_host_map virtual_apic_map;
202 struct kvm_host_map pi_desc_map;
203
204 struct pi_desc *pi_desc;
205 bool pi_pending;
206 u16 posted_intr_nv;
207
208 struct hrtimer preemption_timer;
209 u64 preemption_timer_deadline;
210 bool has_preemption_timer_deadline;
211 bool preemption_timer_expired;
212
213 /*
214 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in
215 * order to propagate the guest's pre-VM-Enter value into vmcs02. For
216 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value.
217 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_
218 * userspace restores MSRs before nested state. If userspace restores
219 * MSRs after nested state, the snapshot holds garbage, but KVM can't
220 * detect that, and the garbage value in vmcs02 will be overwritten by
221 * MSR restoration in any case.
222 */
223 u64 pre_vmenter_debugctl;
224 u64 pre_vmenter_bndcfgs;
225
226 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
227 int l1_tpr_threshold;
228
229 u16 vpid02;
230 u16 last_vpid;
231
232 struct nested_vmx_msrs msrs;
233
234 /* SMM related state */
235 struct {
236 /* in VMX operation on SMM entry? */
237 bool vmxon;
238 /* in guest mode on SMM entry? */
239 bool guest_mode;
240 } smm;
241
242 #ifdef CONFIG_KVM_HYPERV
243 gpa_t hv_evmcs_vmptr;
244 struct kvm_host_map hv_evmcs_map;
245 struct hv_enlightened_vmcs *hv_evmcs;
246 #endif
247 };
248
249 struct vcpu_vmx {
250 struct kvm_vcpu vcpu;
251 u8 fail;
252 u8 x2apic_msr_bitmap_mode;
253
254 /*
255 * If true, host state has been stored in vmx->loaded_vmcs for
256 * the CPU registers that only need to be switched when transitioning
257 * to/from the kernel, and the registers have been loaded with guest
258 * values. If false, host state is loaded in the CPU registers
259 * and vmx->loaded_vmcs->host_state is invalid.
260 */
261 bool guest_state_loaded;
262
263 unsigned long exit_qualification;
264 u32 exit_intr_info;
265 u32 idt_vectoring_info;
266 ulong rflags;
267
268 /*
269 * User return MSRs are always emulated when enabled in the guest, but
270 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
271 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
272 * be loaded into hardware if those conditions aren't met.
273 */
274 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
275 bool guest_uret_msrs_loaded;
276 #ifdef CONFIG_X86_64
277 u64 msr_host_kernel_gs_base;
278 u64 msr_guest_kernel_gs_base;
279 #endif
280
281 u64 spec_ctrl;
282 u32 msr_ia32_umwait_control;
283
284 /*
285 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
286 * non-nested (L1) guest, it always points to vmcs01. For a nested
287 * guest (L2), it points to a different VMCS.
288 */
289 struct loaded_vmcs vmcs01;
290 struct loaded_vmcs *loaded_vmcs;
291
292 struct msr_autoload {
293 struct vmx_msrs guest;
294 struct vmx_msrs host;
295 } msr_autoload;
296
297 struct msr_autostore {
298 struct vmx_msrs guest;
299 } msr_autostore;
300
301 struct {
302 int vm86_active;
303 ulong save_rflags;
304 struct kvm_segment segs[8];
305 } rmode;
306 struct {
307 u32 bitmask; /* 4 bits per segment (1 bit per field) */
308 struct kvm_save_segment {
309 u16 selector;
310 unsigned long base;
311 u32 limit;
312 u32 ar;
313 } seg[8];
314 } segment_cache;
315 int vpid;
316 bool emulation_required;
317
318 union vmx_exit_reason exit_reason;
319
320 /* Posted interrupt descriptor */
321 struct pi_desc pi_desc;
322
323 /* Used if this vCPU is waiting for PI notification wakeup. */
324 struct list_head pi_wakeup_list;
325
326 /* Support for a guest hypervisor (nested VMX) */
327 struct nested_vmx nested;
328
329 /* Dynamic PLE window. */
330 unsigned int ple_window;
331 bool ple_window_dirty;
332
333 /* Support for PML */
334 #define PML_LOG_NR_ENTRIES 512
335 /* PML is written backwards: this is the first entry written by the CPU */
336 #define PML_HEAD_INDEX (PML_LOG_NR_ENTRIES-1)
337
338 struct page *pml_pg;
339
340 /* apic deadline value in host tsc */
341 u64 hv_deadline_tsc;
342
343 /*
344 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
345 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
346 * in msr_ia32_feature_control_valid_bits.
347 */
348 u64 msr_ia32_feature_control;
349 u64 msr_ia32_feature_control_valid_bits;
350 /* SGX Launch Control public key hash */
351 u64 msr_ia32_sgxlepubkeyhash[4];
352 u64 msr_ia32_mcu_opt_ctrl;
353 bool disable_fb_clear;
354
355 struct pt_desc pt_desc;
356 struct lbr_desc lbr_desc;
357
358 /* Save desired MSR intercept (read: pass-through) state */
359 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 16
360 struct {
361 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
362 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
363 } shadow_msr_intercept;
364
365 /* ve_info must be page aligned. */
366 struct vmx_ve_information *ve_info;
367 };
368
369 struct kvm_vmx {
370 struct kvm kvm;
371
372 unsigned int tss_addr;
373 bool ept_identity_pagetable_done;
374 gpa_t ept_identity_map_addr;
375 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */
376 u64 *pid_table;
377 };
378
379 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
380 struct loaded_vmcs *buddy);
381 int allocate_vpid(void);
382 void free_vpid(int vpid);
383 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
384 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
385 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
386 unsigned long fs_base, unsigned long gs_base);
387 int vmx_get_cpl(struct kvm_vcpu *vcpu);
388 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu);
389 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
390 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
391 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
392 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
393 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
394 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
395 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
396 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
397 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
398 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
399 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
400 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
401 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
402
403 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
404 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
405 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
406 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
407 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
408 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
409 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
410 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
411 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
412 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
413 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
414 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
415 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
416 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
417 unsigned int flags);
418 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
419 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
420
421 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
422 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
423
424 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
425 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
426
427 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags);
428
vmx_set_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type,bool value)429 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
430 int type, bool value)
431 {
432 if (value)
433 vmx_enable_intercept_for_msr(vcpu, msr, type);
434 else
435 vmx_disable_intercept_for_msr(vcpu, msr, type);
436 }
437
438 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
439
440 /*
441 * Note, early Intel manuals have the write-low and read-high bitmap offsets
442 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
443 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
444 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
445 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
446 * VM-Exit.
447 */
448 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
449 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
450 u32 msr) \
451 { \
452 int f = sizeof(unsigned long); \
453 \
454 if (msr <= 0x1fff) \
455 return bitop##_bit(msr, bitmap + base / f); \
456 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
457 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
458 return (rtype)true; \
459 }
460 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
461 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
462 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
463
BUILD_VMX_MSR_BITMAP_HELPERS(bool,test,test)464 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
465 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
466 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
467
468 static inline u8 vmx_get_rvi(void)
469 {
470 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
471 }
472
473 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
474 (VM_ENTRY_LOAD_DEBUG_CONTROLS)
475 #ifdef CONFIG_X86_64
476 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
477 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \
478 VM_ENTRY_IA32E_MODE)
479 #else
480 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
481 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS
482 #endif
483 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \
484 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
485 VM_ENTRY_LOAD_IA32_PAT | \
486 VM_ENTRY_LOAD_IA32_EFER | \
487 VM_ENTRY_LOAD_BNDCFGS | \
488 VM_ENTRY_PT_CONCEAL_PIP | \
489 VM_ENTRY_LOAD_IA32_RTIT_CTL)
490
491 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
492 (VM_EXIT_SAVE_DEBUG_CONTROLS | \
493 VM_EXIT_ACK_INTR_ON_EXIT)
494 #ifdef CONFIG_X86_64
495 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
496 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \
497 VM_EXIT_HOST_ADDR_SPACE_SIZE)
498 #else
499 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
500 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
501 #endif
502 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \
503 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
504 VM_EXIT_SAVE_IA32_PAT | \
505 VM_EXIT_LOAD_IA32_PAT | \
506 VM_EXIT_SAVE_IA32_EFER | \
507 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \
508 VM_EXIT_LOAD_IA32_EFER | \
509 VM_EXIT_CLEAR_BNDCFGS | \
510 VM_EXIT_PT_CONCEAL_PIP | \
511 VM_EXIT_CLEAR_IA32_RTIT_CTL)
512
513 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \
514 (PIN_BASED_EXT_INTR_MASK | \
515 PIN_BASED_NMI_EXITING)
516 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \
517 (PIN_BASED_VIRTUAL_NMIS | \
518 PIN_BASED_POSTED_INTR | \
519 PIN_BASED_VMX_PREEMPTION_TIMER)
520
521 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
522 (CPU_BASED_HLT_EXITING | \
523 CPU_BASED_CR3_LOAD_EXITING | \
524 CPU_BASED_CR3_STORE_EXITING | \
525 CPU_BASED_UNCOND_IO_EXITING | \
526 CPU_BASED_MOV_DR_EXITING | \
527 CPU_BASED_USE_TSC_OFFSETTING | \
528 CPU_BASED_MWAIT_EXITING | \
529 CPU_BASED_MONITOR_EXITING | \
530 CPU_BASED_INVLPG_EXITING | \
531 CPU_BASED_RDPMC_EXITING | \
532 CPU_BASED_INTR_WINDOW_EXITING)
533
534 #ifdef CONFIG_X86_64
535 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
536 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \
537 CPU_BASED_CR8_LOAD_EXITING | \
538 CPU_BASED_CR8_STORE_EXITING)
539 #else
540 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
541 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
542 #endif
543
544 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \
545 (CPU_BASED_RDTSC_EXITING | \
546 CPU_BASED_TPR_SHADOW | \
547 CPU_BASED_USE_IO_BITMAPS | \
548 CPU_BASED_MONITOR_TRAP_FLAG | \
549 CPU_BASED_USE_MSR_BITMAPS | \
550 CPU_BASED_NMI_WINDOW_EXITING | \
551 CPU_BASED_PAUSE_EXITING | \
552 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \
553 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
554
555 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0
556 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \
557 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \
558 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
559 SECONDARY_EXEC_WBINVD_EXITING | \
560 SECONDARY_EXEC_ENABLE_VPID | \
561 SECONDARY_EXEC_ENABLE_EPT | \
562 SECONDARY_EXEC_UNRESTRICTED_GUEST | \
563 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \
564 SECONDARY_EXEC_DESC | \
565 SECONDARY_EXEC_ENABLE_RDTSCP | \
566 SECONDARY_EXEC_ENABLE_INVPCID | \
567 SECONDARY_EXEC_APIC_REGISTER_VIRT | \
568 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \
569 SECONDARY_EXEC_SHADOW_VMCS | \
570 SECONDARY_EXEC_ENABLE_XSAVES | \
571 SECONDARY_EXEC_RDSEED_EXITING | \
572 SECONDARY_EXEC_RDRAND_EXITING | \
573 SECONDARY_EXEC_ENABLE_PML | \
574 SECONDARY_EXEC_TSC_SCALING | \
575 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
576 SECONDARY_EXEC_PT_USE_GPA | \
577 SECONDARY_EXEC_PT_CONCEAL_VMX | \
578 SECONDARY_EXEC_ENABLE_VMFUNC | \
579 SECONDARY_EXEC_BUS_LOCK_DETECTION | \
580 SECONDARY_EXEC_NOTIFY_VM_EXITING | \
581 SECONDARY_EXEC_ENCLS_EXITING | \
582 SECONDARY_EXEC_EPT_VIOLATION_VE)
583
584 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0
585 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \
586 (TERTIARY_EXEC_IPI_VIRT)
587
588 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \
589 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \
590 { \
591 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
592 vmcs_write##bits(uname, val); \
593 vmx->loaded_vmcs->controls_shadow.lname = val; \
594 } \
595 } \
596 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \
597 { \
598 return vmcs->controls_shadow.lname; \
599 } \
600 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \
601 { \
602 return __##lname##_controls_get(vmx->loaded_vmcs); \
603 } \
604 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \
605 { \
606 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
607 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
608 } \
609 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \
610 { \
611 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
612 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
613 }
614 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
615 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
616 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
617 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
618 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
619 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
620
621 /*
622 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
623 * cache on demand. Other registers not listed here are synced to
624 * the cache immediately after VM-Exit.
625 */
626 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \
627 (1 << VCPU_REGS_RSP) | \
628 (1 << VCPU_EXREG_RFLAGS) | \
629 (1 << VCPU_EXREG_PDPTR) | \
630 (1 << VCPU_EXREG_SEGMENTS) | \
631 (1 << VCPU_EXREG_CR0) | \
632 (1 << VCPU_EXREG_CR3) | \
633 (1 << VCPU_EXREG_CR4) | \
634 (1 << VCPU_EXREG_EXIT_INFO_1) | \
635 (1 << VCPU_EXREG_EXIT_INFO_2))
636
vmx_l1_guest_owned_cr0_bits(void)637 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void)
638 {
639 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS;
640
641 /*
642 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging
643 * in order to construct shadow PTEs with the correct protections.
644 * Note! CR0.WP technically can be passed through to the guest if
645 * paging is disabled, but checking CR0.PG would generate a cyclical
646 * dependency of sorts due to forcing the caller to ensure CR0 holds
647 * the correct value prior to determining which CR0 bits can be owned
648 * by L1. Keep it simple and limit the optimization to EPT.
649 */
650 if (!enable_ept)
651 bits &= ~X86_CR0_WP;
652 return bits;
653 }
654
to_kvm_vmx(struct kvm * kvm)655 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
656 {
657 return container_of(kvm, struct kvm_vmx, kvm);
658 }
659
to_vmx(struct kvm_vcpu * vcpu)660 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
661 {
662 return container_of(vcpu, struct vcpu_vmx, vcpu);
663 }
664
vcpu_to_lbr_desc(struct kvm_vcpu * vcpu)665 static inline struct lbr_desc *vcpu_to_lbr_desc(struct kvm_vcpu *vcpu)
666 {
667 return &to_vmx(vcpu)->lbr_desc;
668 }
669
vcpu_to_lbr_records(struct kvm_vcpu * vcpu)670 static inline struct x86_pmu_lbr *vcpu_to_lbr_records(struct kvm_vcpu *vcpu)
671 {
672 return &vcpu_to_lbr_desc(vcpu)->records;
673 }
674
intel_pmu_lbr_is_enabled(struct kvm_vcpu * vcpu)675 static inline bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu)
676 {
677 return !!vcpu_to_lbr_records(vcpu)->nr;
678 }
679
680 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu);
681 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
682 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
683
vmx_get_exit_qual(struct kvm_vcpu * vcpu)684 static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
685 {
686 struct vcpu_vmx *vmx = to_vmx(vcpu);
687
688 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1))
689 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
690
691 return vmx->exit_qualification;
692 }
693
vmx_get_intr_info(struct kvm_vcpu * vcpu)694 static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
695 {
696 struct vcpu_vmx *vmx = to_vmx(vcpu);
697
698 if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2))
699 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
700
701 return vmx->exit_intr_info;
702 }
703
704 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
705 void free_vmcs(struct vmcs *vmcs);
706 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
707 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
708 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
709
alloc_vmcs(bool shadow)710 static inline struct vmcs *alloc_vmcs(bool shadow)
711 {
712 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
713 GFP_KERNEL_ACCOUNT);
714 }
715
vmx_has_waitpkg(struct vcpu_vmx * vmx)716 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
717 {
718 return secondary_exec_controls_get(vmx) &
719 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
720 }
721
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)722 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
723 {
724 if (!enable_ept)
725 return true;
726
727 return allow_smaller_maxphyaddr &&
728 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr;
729 }
730
is_unrestricted_guest(struct kvm_vcpu * vcpu)731 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
732 {
733 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
734 (secondary_exec_controls_get(to_vmx(vcpu)) &
735 SECONDARY_EXEC_UNRESTRICTED_GUEST));
736 }
737
738 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)739 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
740 {
741 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
742 }
743
744 void dump_vmcs(struct kvm_vcpu *vcpu);
745
vmx_get_instr_info_reg2(u32 vmx_instr_info)746 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
747 {
748 return (vmx_instr_info >> 28) & 0xf;
749 }
750
vmx_can_use_ipiv(struct kvm_vcpu * vcpu)751 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu)
752 {
753 return lapic_in_kernel(vcpu) && enable_ipiv;
754 }
755
vmx_segment_cache_clear(struct vcpu_vmx * vmx)756 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
757 {
758 vmx->segment_cache.bitmask = 0;
759 }
760
761 #endif /* __KVM_X86_VMX_H */
762