1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * DesignWare MIPI DSI Host Controller v1.02 driver
4 *
5 * Copyright (c) 2016 Linaro Limited.
6 * Copyright (c) 2014-2016 HiSilicon Limited.
7 *
8 * Author:
9 * Xinliang Liu <z.liuxinliang@hisilicon.com>
10 * Xinliang Liu <xinliang.liu@linaro.org>
11 * Xinwei Kong <kong.kongxinwei@hisilicon.com>
12 */
13
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/delay.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_device.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
28 #include <drm/drm_simple_kms_helper.h>
29
30 #include "dw_dsi_reg.h"
31
32 #define MAX_TX_ESC_CLK 10
33 #define ROUND(x, y) ((x) / (y) + \
34 ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
35 #define PHY_REF_CLK_RATE 19200000
36 #define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000))
37
38 #define encoder_to_dsi(encoder) \
39 container_of(encoder, struct dw_dsi, encoder)
40 #define host_to_dsi(host) \
41 container_of(host, struct dw_dsi, host)
42
43 struct mipi_phy_params {
44 u32 clk_t_lpx;
45 u32 clk_t_hs_prepare;
46 u32 clk_t_hs_zero;
47 u32 clk_t_hs_trial;
48 u32 clk_t_wakeup;
49 u32 data_t_lpx;
50 u32 data_t_hs_prepare;
51 u32 data_t_hs_zero;
52 u32 data_t_hs_trial;
53 u32 data_t_ta_go;
54 u32 data_t_ta_get;
55 u32 data_t_wakeup;
56 u32 hstx_ckg_sel;
57 u32 pll_fbd_div5f;
58 u32 pll_fbd_div1f;
59 u32 pll_fbd_2p;
60 u32 pll_enbwt;
61 u32 pll_fbd_p;
62 u32 pll_fbd_s;
63 u32 pll_pre_div1p;
64 u32 pll_pre_p;
65 u32 pll_vco_750M;
66 u32 pll_lpf_rs;
67 u32 pll_lpf_cs;
68 u32 clklp2hs_time;
69 u32 clkhs2lp_time;
70 u32 lp2hs_time;
71 u32 hs2lp_time;
72 u32 clk_to_data_delay;
73 u32 data_to_clk_delay;
74 u32 lane_byte_clk_kHz;
75 u32 clk_division;
76 };
77
78 struct dsi_hw_ctx {
79 void __iomem *base;
80 struct clk *pclk;
81 };
82
83 struct dw_dsi {
84 struct drm_encoder encoder;
85 struct device *dev;
86 struct mipi_dsi_host host;
87 struct drm_display_mode cur_mode;
88 struct dsi_hw_ctx *ctx;
89 struct mipi_phy_params phy;
90
91 u32 lanes;
92 enum mipi_dsi_pixel_format format;
93 unsigned long mode_flags;
94 bool enable;
95 };
96
97 struct dsi_data {
98 struct dw_dsi dsi;
99 struct dsi_hw_ctx ctx;
100 };
101
102 struct dsi_phy_range {
103 u32 min_range_kHz;
104 u32 max_range_kHz;
105 u32 pll_vco_750M;
106 u32 hstx_ckg_sel;
107 };
108
109 static const struct dsi_phy_range dphy_range_info[] = {
110 { 46875, 62500, 1, 7 },
111 { 62500, 93750, 0, 7 },
112 { 93750, 125000, 1, 6 },
113 { 125000, 187500, 0, 6 },
114 { 187500, 250000, 1, 5 },
115 { 250000, 375000, 0, 5 },
116 { 375000, 500000, 1, 4 },
117 { 500000, 750000, 0, 4 },
118 { 750000, 1000000, 1, 0 },
119 { 1000000, 1500000, 0, 0 }
120 };
121
dsi_calc_phy_rate(u32 req_kHz,struct mipi_phy_params * phy)122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
123 {
124 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
125 u32 tmp_kHz = req_kHz;
126 u32 i = 0;
127 u32 q_pll = 1;
128 u32 m_pll = 0;
129 u32 n_pll = 0;
130 u32 r_pll = 1;
131 u32 m_n = 0;
132 u32 m_n_int = 0;
133 u32 f_kHz = 0;
134 u64 temp;
135
136 /*
137 * Find a rate >= req_kHz.
138 */
139 do {
140 f_kHz = tmp_kHz;
141
142 for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
143 if (f_kHz >= dphy_range_info[i].min_range_kHz &&
144 f_kHz <= dphy_range_info[i].max_range_kHz)
145 break;
146
147 if (i == ARRAY_SIZE(dphy_range_info)) {
148 DRM_ERROR("%dkHz out of range\n", f_kHz);
149 return 0;
150 }
151
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
154
155 if (phy->hstx_ckg_sel <= 7 &&
156 phy->hstx_ckg_sel >= 4)
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
158
159 temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
160 m_n_int = div64_u64_rem(temp, 1000000000, &temp);
161 m_n = div_u64(temp, 100000000);
162
163 if (m_n_int % 2 == 0) {
164 if (m_n * 6 >= 50) {
165 n_pll = 2;
166 m_pll = (m_n_int + 1) * n_pll;
167 } else if (m_n * 6 >= 30) {
168 n_pll = 3;
169 m_pll = m_n_int * n_pll + 2;
170 } else {
171 n_pll = 1;
172 m_pll = m_n_int * n_pll;
173 }
174 } else {
175 if (m_n * 6 >= 50) {
176 n_pll = 1;
177 m_pll = (m_n_int + 1) * n_pll;
178 } else if (m_n * 6 >= 30) {
179 n_pll = 1;
180 m_pll = (m_n_int + 1) * n_pll;
181 } else if (m_n * 6 >= 10) {
182 n_pll = 3;
183 m_pll = m_n_int * n_pll + 1;
184 } else {
185 n_pll = 2;
186 m_pll = m_n_int * n_pll;
187 }
188 }
189
190 if (n_pll == 1) {
191 phy->pll_fbd_p = 0;
192 phy->pll_pre_div1p = 1;
193 } else {
194 phy->pll_fbd_p = n_pll;
195 phy->pll_pre_div1p = 0;
196 }
197
198 if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
199 r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
200
201 if (m_pll == 2) {
202 phy->pll_pre_p = 0;
203 phy->pll_fbd_s = 0;
204 phy->pll_fbd_div1f = 0;
205 phy->pll_fbd_div5f = 1;
206 } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
207 phy->pll_pre_p = m_pll / (2 * r_pll);
208 phy->pll_fbd_s = 0;
209 phy->pll_fbd_div1f = 1;
210 phy->pll_fbd_div5f = 0;
211 } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
212 if (((m_pll / (2 * r_pll)) % 2) == 0) {
213 phy->pll_pre_p =
214 (m_pll / (2 * r_pll)) / 2 - 1;
215 phy->pll_fbd_s =
216 (m_pll / (2 * r_pll)) % 2 + 2;
217 } else {
218 phy->pll_pre_p =
219 (m_pll / (2 * r_pll)) / 2;
220 phy->pll_fbd_s =
221 (m_pll / (2 * r_pll)) % 2;
222 }
223 phy->pll_fbd_div1f = 0;
224 phy->pll_fbd_div5f = 0;
225 } else {
226 phy->pll_pre_p = 0;
227 phy->pll_fbd_s = 0;
228 phy->pll_fbd_div1f = 0;
229 phy->pll_fbd_div5f = 1;
230 }
231
232 f_kHz = div64_u64((u64)1000000000 * (u64)m_pll,
233 (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
234 if (f_kHz >= req_kHz)
235 break;
236
237 tmp_kHz += 10;
238
239 } while (true);
240
241 return f_kHz;
242 }
243
dsi_get_phy_params(u32 phy_req_kHz,struct mipi_phy_params * phy)244 static void dsi_get_phy_params(u32 phy_req_kHz,
245 struct mipi_phy_params *phy)
246 {
247 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
248 u32 phy_rate_kHz;
249 u32 ui;
250
251 memset(phy, 0, sizeof(*phy));
252
253 phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
254 if (!phy_rate_kHz)
255 return;
256
257 ui = 1000000 / phy_rate_kHz;
258
259 phy->clk_t_lpx = ROUND(50, 8 * ui);
260 phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
261
262 phy->clk_t_hs_zero = ROUND(262, 8 * ui);
263 phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
264 phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
265 if (phy->clk_t_wakeup > 0xff)
266 phy->clk_t_wakeup = 0xff;
267 phy->data_t_wakeup = phy->clk_t_wakeup;
268 phy->data_t_lpx = phy->clk_t_lpx;
269 phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
270 phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
271 phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
272 phy->data_t_ta_go = 3;
273 phy->data_t_ta_get = 4;
274
275 phy->pll_enbwt = 1;
276 phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
277 phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
278 phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
279 phy->hs2lp_time = phy->clkhs2lp_time;
280 phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
281 phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
282 phy->clkhs2lp_time;
283
284 phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
285 phy->clk_division =
286 DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
287 }
288
dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)289 static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)
290 {
291 u32 val;
292
293 /*
294 * TODO: only support RGB888 now, to support more
295 */
296 switch (format) {
297 case MIPI_DSI_FMT_RGB888:
298 val = DSI_24BITS_1;
299 break;
300 default:
301 val = DSI_24BITS_1;
302 break;
303 }
304
305 return val;
306 }
307
308 /*
309 * dsi phy reg write function
310 */
dsi_phy_tst_set(void __iomem * base,u32 reg,u32 val)311 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
312 {
313 u32 reg_write = 0x10000 + reg;
314
315 /*
316 * latch reg first
317 */
318 writel(reg_write, base + PHY_TST_CTRL1);
319 writel(0x02, base + PHY_TST_CTRL0);
320 writel(0x00, base + PHY_TST_CTRL0);
321
322 /*
323 * then latch value
324 */
325 writel(val, base + PHY_TST_CTRL1);
326 writel(0x02, base + PHY_TST_CTRL0);
327 writel(0x00, base + PHY_TST_CTRL0);
328 }
329
dsi_set_phy_timer(void __iomem * base,struct mipi_phy_params * phy,u32 lanes)330 static void dsi_set_phy_timer(void __iomem *base,
331 struct mipi_phy_params *phy,
332 u32 lanes)
333 {
334 u32 val;
335
336 /*
337 * Set lane value and phy stop wait time.
338 */
339 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
340 writel(val, base + PHY_IF_CFG);
341
342 /*
343 * Set phy clk division.
344 */
345 val = readl(base + CLKMGR_CFG) | phy->clk_division;
346 writel(val, base + CLKMGR_CFG);
347
348 /*
349 * Set lp and hs switching params.
350 */
351 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
352 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
354 phy->clkhs2lp_time);
355 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
356 phy->clklp2hs_time);
357 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
358 phy->data_to_clk_delay);
359 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),
360 phy->clk_to_data_delay);
361 }
362
dsi_set_mipi_phy(void __iomem * base,struct mipi_phy_params * phy,u32 lanes)363 static void dsi_set_mipi_phy(void __iomem *base,
364 struct mipi_phy_params *phy,
365 u32 lanes)
366 {
367 u32 delay_count;
368 u32 val;
369 u32 i;
370
371 /* phy timer setting */
372 dsi_set_phy_timer(base, phy, lanes);
373
374 /*
375 * Reset to clean up phy tst params.
376 */
377 writel(0, base + PHY_RSTZ);
378 writel(0, base + PHY_TST_CTRL0);
379 writel(1, base + PHY_TST_CTRL0);
380 writel(0, base + PHY_TST_CTRL0);
381
382 /*
383 * Clock lane timing control setting: TLPX, THS-PREPARE,
384 * THS-ZERO, THS-TRAIL, TWAKEUP.
385 */
386 dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
387 dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
388 dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
389 dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
390 dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
391
392 /*
393 * Data lane timing control setting: TLPX, THS-PREPARE,
394 * THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP.
395 */
396 for (i = 0; i < lanes; i++) {
397 dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
398 dsi_phy_tst_set(base, DATA_THS_PREPARE(i),
399 phy->data_t_hs_prepare);
400 dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
401 dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
402 dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
403 dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
404 dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
405 }
406
407 /*
408 * physical configuration: I, pll I, pll II, pll III,
409 * pll IV, pll V.
410 */
411 dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
412 val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
413 (phy->pll_fbd_2p << 1) + phy->pll_enbwt;
414 dsi_phy_tst_set(base, PHY_CFG_PLL_I, val);
415 dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
416 dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
417 val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
418 dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val);
419 val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
420 phy->pll_lpf_cs;
421 dsi_phy_tst_set(base, PHY_CFG_PLL_V, val);
422
423 writel(PHY_ENABLECLK, base + PHY_RSTZ);
424 udelay(1);
425 writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
426 udelay(1);
427 writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
428 usleep_range(1000, 1500);
429
430 /*
431 * wait for phy's clock ready
432 */
433 delay_count = 100;
434 while (delay_count) {
435 val = readl(base + PHY_STATUS);
436 if ((BIT(0) | BIT(2)) & val)
437 break;
438
439 udelay(1);
440 delay_count--;
441 }
442
443 if (!delay_count)
444 DRM_INFO("phylock and phystopstateclklane is not ready.\n");
445 }
446
dsi_set_mode_timing(void __iomem * base,u32 lane_byte_clk_kHz,struct drm_display_mode * mode,enum mipi_dsi_pixel_format format)447 static void dsi_set_mode_timing(void __iomem *base,
448 u32 lane_byte_clk_kHz,
449 struct drm_display_mode *mode,
450 enum mipi_dsi_pixel_format format)
451 {
452 u32 hfp, hbp, hsw, vfp, vbp, vsw;
453 u32 hline_time;
454 u32 hsa_time;
455 u32 hbp_time;
456 u32 pixel_clk_kHz;
457 int htot, vtot;
458 u32 val;
459 u64 tmp;
460
461 val = dsi_get_dpi_color_coding(format);
462 writel(val, base + DPI_COLOR_CODING);
463
464 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2;
465 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1;
466 writel(val, base + DPI_CFG_POL);
467
468 /*
469 * The DSI IP accepts vertical timing using lines as normal,
470 * but horizontal timing is a mixture of pixel-clocks for the
471 * active region and byte-lane clocks for the blanking-related
472 * timings. hfp is specified as the total hline_time in byte-
473 * lane clocks minus hsa, hbp and active.
474 */
475 pixel_clk_kHz = mode->clock;
476 htot = mode->htotal;
477 vtot = mode->vtotal;
478 hfp = mode->hsync_start - mode->hdisplay;
479 hbp = mode->htotal - mode->hsync_end;
480 hsw = mode->hsync_end - mode->hsync_start;
481 vfp = mode->vsync_start - mode->vdisplay;
482 vbp = mode->vtotal - mode->vsync_end;
483 vsw = mode->vsync_end - mode->vsync_start;
484 if (vsw > 15) {
485 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
486 vsw = 15;
487 }
488
489 hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
490 hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
491 tmp = (u64)htot * (u64)lane_byte_clk_kHz;
492 hline_time = DIV_ROUND_UP_ULL(tmp, pixel_clk_kHz);
493
494 /* all specified in byte-lane clocks */
495 writel(hsa_time, base + VID_HSA_TIME);
496 writel(hbp_time, base + VID_HBP_TIME);
497 writel(hline_time, base + VID_HLINE_TIME);
498
499 writel(vsw, base + VID_VSA_LINES);
500 writel(vbp, base + VID_VBP_LINES);
501 writel(vfp, base + VID_VFP_LINES);
502 writel(mode->vdisplay, base + VID_VACTIVE_LINES);
503 writel(mode->hdisplay, base + VID_PKT_SIZE);
504
505 DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n",
506 htot, hfp, hbp, hsw);
507 DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n",
508 vtot, vfp, vbp, vsw);
509 DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n",
510 hsa_time, hbp_time, hline_time);
511 }
512
dsi_set_video_mode(void __iomem * base,unsigned long flags)513 static void dsi_set_video_mode(void __iomem *base, unsigned long flags)
514 {
515 u32 val;
516 u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
517 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
518 u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO |
519 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
520 u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
521
522 /*
523 * choose video mode type
524 */
525 if ((flags & mode_mask) == non_burst_sync_pulse)
526 val = DSI_NON_BURST_SYNC_PULSES;
527 else if ((flags & mode_mask) == non_burst_sync_event)
528 val = DSI_NON_BURST_SYNC_EVENTS;
529 else
530 val = DSI_BURST_SYNC_PULSES_1;
531 writel(val, base + VID_MODE_CFG);
532
533 writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
534 writel(DSI_VIDEO_MODE, base + MODE_CFG);
535 }
536
dsi_mipi_init(struct dw_dsi * dsi)537 static void dsi_mipi_init(struct dw_dsi *dsi)
538 {
539 struct dsi_hw_ctx *ctx = dsi->ctx;
540 struct mipi_phy_params *phy = &dsi->phy;
541 struct drm_display_mode *mode = &dsi->cur_mode;
542 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
543 void __iomem *base = ctx->base;
544 u32 dphy_req_kHz;
545
546 /*
547 * count phy params
548 */
549 dphy_req_kHz = mode->clock * bpp / dsi->lanes;
550 dsi_get_phy_params(dphy_req_kHz, phy);
551
552 /* reset Core */
553 writel(RESET, base + PWR_UP);
554
555 /* set dsi phy params */
556 dsi_set_mipi_phy(base, phy, dsi->lanes);
557
558 /* set dsi mode timing */
559 dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
560
561 /* set dsi video mode */
562 dsi_set_video_mode(base, dsi->mode_flags);
563
564 /* dsi wake up */
565 writel(POWERUP, base + PWR_UP);
566
567 DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
568 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
569 }
570
dsi_encoder_disable(struct drm_encoder * encoder)571 static void dsi_encoder_disable(struct drm_encoder *encoder)
572 {
573 struct dw_dsi *dsi = encoder_to_dsi(encoder);
574 struct dsi_hw_ctx *ctx = dsi->ctx;
575 void __iomem *base = ctx->base;
576
577 if (!dsi->enable)
578 return;
579
580 writel(0, base + PWR_UP);
581 writel(0, base + LPCLK_CTRL);
582 writel(0, base + PHY_RSTZ);
583 clk_disable_unprepare(ctx->pclk);
584
585 dsi->enable = false;
586 }
587
dsi_encoder_enable(struct drm_encoder * encoder)588 static void dsi_encoder_enable(struct drm_encoder *encoder)
589 {
590 struct dw_dsi *dsi = encoder_to_dsi(encoder);
591 struct dsi_hw_ctx *ctx = dsi->ctx;
592 int ret;
593
594 if (dsi->enable)
595 return;
596
597 ret = clk_prepare_enable(ctx->pclk);
598 if (ret) {
599 DRM_ERROR("fail to enable pclk: %d\n", ret);
600 return;
601 }
602
603 dsi_mipi_init(dsi);
604
605 dsi->enable = true;
606 }
607
dsi_encoder_phy_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)608 static enum drm_mode_status dsi_encoder_phy_mode_valid(
609 struct drm_encoder *encoder,
610 const struct drm_display_mode *mode)
611 {
612 struct dw_dsi *dsi = encoder_to_dsi(encoder);
613 struct mipi_phy_params phy;
614 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
615 u32 req_kHz, act_kHz, lane_byte_clk_kHz;
616
617 /* Calculate the lane byte clk using the adjusted mode clk */
618 memset(&phy, 0, sizeof(phy));
619 req_kHz = mode->clock * bpp / dsi->lanes;
620 act_kHz = dsi_calc_phy_rate(req_kHz, &phy);
621 lane_byte_clk_kHz = act_kHz / 8;
622
623 DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...",
624 mode->hdisplay, mode->vdisplay, bpp,
625 drm_mode_vrefresh(mode), mode->clock);
626
627 /*
628 * Make sure the adjusted mode clock and the lane byte clk
629 * have a common denominator base frequency
630 */
631 if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) {
632 DRM_DEBUG_DRIVER("OK!\n");
633 return MODE_OK;
634 }
635
636 DRM_DEBUG_DRIVER("BAD!\n");
637 return MODE_BAD;
638 }
639
dsi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)640 static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder,
641 const struct drm_display_mode *mode)
642
643 {
644 const struct drm_crtc_helper_funcs *crtc_funcs = NULL;
645 struct drm_crtc *crtc = NULL;
646 struct drm_display_mode adj_mode;
647 enum drm_mode_status ret;
648
649 /*
650 * The crtc might adjust the mode, so go through the
651 * possible crtcs (technically just one) and call
652 * mode_fixup to figure out the adjusted mode before we
653 * validate it.
654 */
655 drm_for_each_crtc(crtc, encoder->dev) {
656 /*
657 * reset adj_mode to the mode value each time,
658 * so we don't adjust the mode twice
659 */
660 drm_mode_init(&adj_mode, mode);
661
662 crtc_funcs = crtc->helper_private;
663 if (crtc_funcs && crtc_funcs->mode_fixup)
664 if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
665 return MODE_BAD;
666
667 ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
668 if (ret != MODE_OK)
669 return ret;
670 }
671 return MODE_OK;
672 }
673
dsi_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)674 static void dsi_encoder_mode_set(struct drm_encoder *encoder,
675 struct drm_display_mode *mode,
676 struct drm_display_mode *adj_mode)
677 {
678 struct dw_dsi *dsi = encoder_to_dsi(encoder);
679
680 drm_mode_copy(&dsi->cur_mode, adj_mode);
681 }
682
dsi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)683 static int dsi_encoder_atomic_check(struct drm_encoder *encoder,
684 struct drm_crtc_state *crtc_state,
685 struct drm_connector_state *conn_state)
686 {
687 /* do nothing */
688 return 0;
689 }
690
691 static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = {
692 .atomic_check = dsi_encoder_atomic_check,
693 .mode_valid = dsi_encoder_mode_valid,
694 .mode_set = dsi_encoder_mode_set,
695 .enable = dsi_encoder_enable,
696 .disable = dsi_encoder_disable
697 };
698
dw_drm_encoder_init(struct device * dev,struct drm_device * drm_dev,struct drm_encoder * encoder)699 static int dw_drm_encoder_init(struct device *dev,
700 struct drm_device *drm_dev,
701 struct drm_encoder *encoder)
702 {
703 int ret;
704 u32 crtc_mask = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
705
706 if (!crtc_mask) {
707 DRM_ERROR("failed to find crtc mask\n");
708 return -EINVAL;
709 }
710
711 encoder->possible_crtcs = crtc_mask;
712 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
713 if (ret) {
714 DRM_ERROR("failed to init dsi encoder\n");
715 return ret;
716 }
717
718 drm_encoder_helper_add(encoder, &dw_encoder_helper_funcs);
719
720 return 0;
721 }
722
723 static const struct component_ops dsi_ops;
dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * mdsi)724 static int dsi_host_attach(struct mipi_dsi_host *host,
725 struct mipi_dsi_device *mdsi)
726 {
727 struct dw_dsi *dsi = host_to_dsi(host);
728 struct device *dev = host->dev;
729 int ret;
730
731 if (mdsi->lanes < 1 || mdsi->lanes > 4) {
732 DRM_ERROR("dsi device params invalid\n");
733 return -EINVAL;
734 }
735
736 dsi->lanes = mdsi->lanes;
737 dsi->format = mdsi->format;
738 dsi->mode_flags = mdsi->mode_flags;
739
740 ret = component_add(dev, &dsi_ops);
741 if (ret)
742 return ret;
743
744 return 0;
745 }
746
dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * mdsi)747 static int dsi_host_detach(struct mipi_dsi_host *host,
748 struct mipi_dsi_device *mdsi)
749 {
750 struct device *dev = host->dev;
751
752 component_del(dev, &dsi_ops);
753
754 return 0;
755 }
756
757 static const struct mipi_dsi_host_ops dsi_host_ops = {
758 .attach = dsi_host_attach,
759 .detach = dsi_host_detach,
760 };
761
dsi_host_init(struct device * dev,struct dw_dsi * dsi)762 static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
763 {
764 struct mipi_dsi_host *host = &dsi->host;
765 int ret;
766
767 host->dev = dev;
768 host->ops = &dsi_host_ops;
769 ret = mipi_dsi_host_register(host);
770 if (ret) {
771 DRM_ERROR("failed to register dsi host\n");
772 return ret;
773 }
774
775 return 0;
776 }
777
dsi_bridge_init(struct drm_device * dev,struct dw_dsi * dsi)778 static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi)
779 {
780 struct drm_encoder *encoder = &dsi->encoder;
781 struct drm_bridge *bridge;
782 struct device_node *np = dsi->dev->of_node;
783 int ret;
784
785 /*
786 * Get the endpoint node. In our case, dsi has one output port1
787 * to which the external HDMI bridge is connected.
788 */
789 ret = drm_of_find_panel_or_bridge(np, 1, 0, NULL, &bridge);
790 if (ret)
791 return ret;
792
793 /* associate the bridge to dsi encoder */
794 return drm_bridge_attach(encoder, bridge, NULL, 0);
795 }
796
dsi_bind(struct device * dev,struct device * master,void * data)797 static int dsi_bind(struct device *dev, struct device *master, void *data)
798 {
799 struct dsi_data *ddata = dev_get_drvdata(dev);
800 struct dw_dsi *dsi = &ddata->dsi;
801 struct drm_device *drm_dev = data;
802 int ret;
803
804 ret = dw_drm_encoder_init(dev, drm_dev, &dsi->encoder);
805 if (ret)
806 return ret;
807
808 ret = dsi_bridge_init(drm_dev, dsi);
809 if (ret)
810 return ret;
811
812 return 0;
813 }
814
dsi_unbind(struct device * dev,struct device * master,void * data)815 static void dsi_unbind(struct device *dev, struct device *master, void *data)
816 {
817 /* do nothing */
818 }
819
820 static const struct component_ops dsi_ops = {
821 .bind = dsi_bind,
822 .unbind = dsi_unbind,
823 };
824
dsi_parse_dt(struct platform_device * pdev,struct dw_dsi * dsi)825 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
826 {
827 struct dsi_hw_ctx *ctx = dsi->ctx;
828 struct resource *res;
829
830 ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
831 if (IS_ERR(ctx->pclk)) {
832 DRM_ERROR("failed to get pclk clock\n");
833 return PTR_ERR(ctx->pclk);
834 }
835
836 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
837 ctx->base = devm_ioremap_resource(&pdev->dev, res);
838 if (IS_ERR(ctx->base)) {
839 DRM_ERROR("failed to remap dsi io region\n");
840 return PTR_ERR(ctx->base);
841 }
842
843 return 0;
844 }
845
dsi_probe(struct platform_device * pdev)846 static int dsi_probe(struct platform_device *pdev)
847 {
848 struct dsi_data *data;
849 struct dw_dsi *dsi;
850 struct dsi_hw_ctx *ctx;
851 int ret;
852
853 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
854 if (!data) {
855 DRM_ERROR("failed to allocate dsi data.\n");
856 return -ENOMEM;
857 }
858 dsi = &data->dsi;
859 ctx = &data->ctx;
860 dsi->ctx = ctx;
861 dsi->dev = &pdev->dev;
862
863 ret = dsi_parse_dt(pdev, dsi);
864 if (ret)
865 return ret;
866
867 platform_set_drvdata(pdev, data);
868
869 ret = dsi_host_init(&pdev->dev, dsi);
870 if (ret)
871 return ret;
872
873 return 0;
874 }
875
dsi_remove(struct platform_device * pdev)876 static void dsi_remove(struct platform_device *pdev)
877 {
878 struct dsi_data *data = platform_get_drvdata(pdev);
879 struct dw_dsi *dsi = &data->dsi;
880
881 mipi_dsi_host_unregister(&dsi->host);
882 }
883
884 static const struct of_device_id dsi_of_match[] = {
885 {.compatible = "hisilicon,hi6220-dsi"},
886 { }
887 };
888 MODULE_DEVICE_TABLE(of, dsi_of_match);
889
890 static struct platform_driver dsi_driver = {
891 .probe = dsi_probe,
892 .remove = dsi_remove,
893 .driver = {
894 .name = "dw-dsi",
895 .of_match_table = dsi_of_match,
896 },
897 };
898
899 module_platform_driver(dsi_driver);
900
901 MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
902 MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
903 MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
904 MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
905 MODULE_LICENSE("GPL v2");
906