xref: /linux/drivers/ufs/core/ufshcd.c (revision 102c16a1f9a9d0ba3b166bf5ca399adf832b65a1)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Universal Flash Storage Host controller driver Core
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6  *
7  * Authors:
8  *	Santosh Yaraganavi <santosh.sy@samsung.com>
9  *	Vinayak Holikatti <h.vinayak@samsung.com>
10  */
11 
12 #include <linux/async.h>
13 #include <linux/devfreq.h>
14 #include <linux/nls.h>
15 #include <linux/of.h>
16 #include <linux/bitfield.h>
17 #include <linux/blk-pm.h>
18 #include <linux/blkdev.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/pm_opp.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/sched/clock.h>
26 #include <linux/iopoll.h>
27 #include <scsi/scsi_cmnd.h>
28 #include <scsi/scsi_dbg.h>
29 #include <scsi/scsi_driver.h>
30 #include <scsi/scsi_eh.h>
31 #include "ufshcd-priv.h"
32 #include <ufs/ufs_quirks.h>
33 #include <ufs/unipro.h>
34 #include "ufs-sysfs.h"
35 #include "ufs-debugfs.h"
36 #include "ufs-fault-injection.h"
37 #include "ufs_bsg.h"
38 #include "ufshcd-crypto.h"
39 #include <linux/unaligned.h>
40 
41 #define CREATE_TRACE_POINTS
42 #include "ufs_trace.h"
43 
44 #define UFSHCD_ENABLE_INTRS	(UTP_TRANSFER_REQ_COMPL |\
45 				 UTP_TASK_REQ_COMPL |\
46 				 UFSHCD_ERROR_MASK)
47 
48 #define UFSHCD_ENABLE_MCQ_INTRS	(UTP_TASK_REQ_COMPL |\
49 				 UFSHCD_ERROR_MASK |\
50 				 MCQ_CQ_EVENT_STATUS)
51 
52 
53 /* UIC command timeout, unit: ms */
54 enum {
55 	UIC_CMD_TIMEOUT_DEFAULT	= 500,
56 	UIC_CMD_TIMEOUT_MAX	= 2000,
57 };
58 /* NOP OUT retries waiting for NOP IN response */
59 #define NOP_OUT_RETRIES    10
60 /* Timeout after 50 msecs if NOP OUT hangs without response */
61 #define NOP_OUT_TIMEOUT    50 /* msecs */
62 
63 /* Query request retries */
64 #define QUERY_REQ_RETRIES 3
65 /* Query request timeout */
66 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
67 
68 /* Advanced RPMB request timeout */
69 #define ADVANCED_RPMB_REQ_TIMEOUT  3000 /* 3 seconds */
70 
71 /* Task management command timeout */
72 #define TM_CMD_TIMEOUT	100 /* msecs */
73 
74 /* maximum number of retries for a general UIC command  */
75 #define UFS_UIC_COMMAND_RETRIES 3
76 
77 /* maximum number of link-startup retries */
78 #define DME_LINKSTARTUP_RETRIES 3
79 
80 /* maximum number of reset retries before giving up */
81 #define MAX_HOST_RESET_RETRIES 5
82 
83 /* Maximum number of error handler retries before giving up */
84 #define MAX_ERR_HANDLER_RETRIES 5
85 
86 /* Expose the flag value from utp_upiu_query.value */
87 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
88 
89 /* Interrupt aggregation default timeout, unit: 40us */
90 #define INT_AGGR_DEF_TO	0x02
91 
92 /* default delay of autosuspend: 2000 ms */
93 #define RPM_AUTOSUSPEND_DELAY_MS 2000
94 
95 /* Default delay of RPM device flush delayed work */
96 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
97 
98 /* Default value of wait time before gating device ref clock */
99 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
100 
101 /* Polling time to wait for fDeviceInit */
102 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
103 
104 /* Default RTC update every 10 seconds */
105 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC)
106 
107 /* bMaxNumOfRTT is equal to two after device manufacturing */
108 #define DEFAULT_MAX_NUM_RTT 2
109 
110 /* UFSHC 4.0 compliant HC support this mode. */
111 static bool use_mcq_mode = true;
112 
is_mcq_supported(struct ufs_hba * hba)113 static bool is_mcq_supported(struct ufs_hba *hba)
114 {
115 	return hba->mcq_sup && use_mcq_mode;
116 }
117 
118 module_param(use_mcq_mode, bool, 0644);
119 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default");
120 
121 static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT;
122 
uic_cmd_timeout_set(const char * val,const struct kernel_param * kp)123 static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp)
124 {
125 	return param_set_uint_minmax(val, kp, UIC_CMD_TIMEOUT_DEFAULT,
126 				     UIC_CMD_TIMEOUT_MAX);
127 }
128 
129 static const struct kernel_param_ops uic_cmd_timeout_ops = {
130 	.set = uic_cmd_timeout_set,
131 	.get = param_get_uint,
132 };
133 
134 module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644);
135 MODULE_PARM_DESC(uic_cmd_timeout,
136 		 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively");
137 
138 #define ufshcd_toggle_vreg(_dev, _vreg, _on)				\
139 	({                                                              \
140 		int _ret;                                               \
141 		if (_on)                                                \
142 			_ret = ufshcd_enable_vreg(_dev, _vreg);         \
143 		else                                                    \
144 			_ret = ufshcd_disable_vreg(_dev, _vreg);        \
145 		_ret;                                                   \
146 	})
147 
148 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
149 	size_t __len = (len);                                            \
150 	print_hex_dump(KERN_ERR, prefix_str,                             \
151 		       __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
152 		       16, 4, buf, __len, false);                        \
153 } while (0)
154 
ufshcd_dump_regs(struct ufs_hba * hba,size_t offset,size_t len,const char * prefix)155 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
156 		     const char *prefix)
157 {
158 	u32 *regs;
159 	size_t pos;
160 
161 	if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
162 		return -EINVAL;
163 
164 	regs = kzalloc(len, GFP_ATOMIC);
165 	if (!regs)
166 		return -ENOMEM;
167 
168 	for (pos = 0; pos < len; pos += 4) {
169 		if (offset == 0 &&
170 		    pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
171 		    pos <= REG_UIC_ERROR_CODE_DME)
172 			continue;
173 		regs[pos / 4] = ufshcd_readl(hba, offset + pos);
174 	}
175 
176 	ufshcd_hex_dump(prefix, regs, len);
177 	kfree(regs);
178 
179 	return 0;
180 }
181 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
182 
183 enum {
184 	UFSHCD_MAX_CHANNEL	= 0,
185 	UFSHCD_MAX_ID		= 1,
186 };
187 
188 static const char *const ufshcd_state_name[] = {
189 	[UFSHCD_STATE_RESET]			= "reset",
190 	[UFSHCD_STATE_OPERATIONAL]		= "operational",
191 	[UFSHCD_STATE_ERROR]			= "error",
192 	[UFSHCD_STATE_EH_SCHEDULED_FATAL]	= "eh_fatal",
193 	[UFSHCD_STATE_EH_SCHEDULED_NON_FATAL]	= "eh_non_fatal",
194 };
195 
196 /* UFSHCD error handling flags */
197 enum {
198 	UFSHCD_EH_IN_PROGRESS = (1 << 0),
199 };
200 
201 /* UFSHCD UIC layer error flags */
202 enum {
203 	UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
204 	UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
205 	UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
206 	UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
207 	UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
208 	UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
209 	UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
210 };
211 
212 #define ufshcd_set_eh_in_progress(h) \
213 	((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
214 #define ufshcd_eh_in_progress(h) \
215 	((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
216 #define ufshcd_clear_eh_in_progress(h) \
217 	((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
218 
219 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
220 	[UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
221 	[UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
222 	[UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
223 	[UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
224 	[UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
225 	[UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
226 	/*
227 	 * For DeepSleep, the link is first put in hibern8 and then off.
228 	 * Leaving the link in hibern8 is not supported.
229 	 */
230 	[UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
231 };
232 
233 static inline enum ufs_dev_pwr_mode
ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)234 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
235 {
236 	return ufs_pm_lvl_states[lvl].dev_state;
237 }
238 
239 static inline enum uic_link_state
ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)240 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
241 {
242 	return ufs_pm_lvl_states[lvl].link_state;
243 }
244 
245 static inline enum ufs_pm_level
ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,enum uic_link_state link_state)246 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
247 					enum uic_link_state link_state)
248 {
249 	enum ufs_pm_level lvl;
250 
251 	for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
252 		if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
253 			(ufs_pm_lvl_states[lvl].link_state == link_state))
254 			return lvl;
255 	}
256 
257 	/* if no match found, return the level 0 */
258 	return UFS_PM_LVL_0;
259 }
260 
ufshcd_has_pending_tasks(struct ufs_hba * hba)261 static bool ufshcd_has_pending_tasks(struct ufs_hba *hba)
262 {
263 	return hba->outstanding_tasks || hba->active_uic_cmd ||
264 	       hba->uic_async_done;
265 }
266 
ufshcd_is_ufs_dev_busy(struct ufs_hba * hba)267 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba)
268 {
269 	return scsi_host_busy(hba->host) || ufshcd_has_pending_tasks(hba);
270 }
271 
272 static const struct ufs_dev_quirk ufs_fixups[] = {
273 	/* UFS cards deviations table */
274 	{ .wmanufacturerid = UFS_VENDOR_MICRON,
275 	  .model = UFS_ANY_MODEL,
276 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
277 	{ .wmanufacturerid = UFS_VENDOR_SAMSUNG,
278 	  .model = UFS_ANY_MODEL,
279 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
280 		   UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
281 		   UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
282 	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
283 	  .model = UFS_ANY_MODEL,
284 	  .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
285 	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
286 	  .model = "hB8aL1" /*H28U62301AMR*/,
287 	  .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
288 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
289 	  .model = UFS_ANY_MODEL,
290 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
291 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
292 	  .model = "THGLF2G9C8KBADG",
293 	  .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
294 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
295 	  .model = "THGLF2G9D8KBADG",
296 	  .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
297 	{}
298 };
299 
300 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
301 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
302 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
303 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
304 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
305 static void ufshcd_hba_exit(struct ufs_hba *hba);
306 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params);
307 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
308 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
309 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
310 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
311 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
312 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
313 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
314 			     bool scale_up);
315 static irqreturn_t ufshcd_intr(int irq, void *__hba);
316 static int ufshcd_change_power_mode(struct ufs_hba *hba,
317 			     struct ufs_pa_layer_attr *pwr_mode);
318 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
319 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
320 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
321 					 struct ufs_vreg *vreg);
322 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
323 						 bool enable);
324 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
325 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
326 
ufshcd_enable_irq(struct ufs_hba * hba)327 void ufshcd_enable_irq(struct ufs_hba *hba)
328 {
329 	if (!hba->is_irq_enabled) {
330 		enable_irq(hba->irq);
331 		hba->is_irq_enabled = true;
332 	}
333 }
334 EXPORT_SYMBOL_GPL(ufshcd_enable_irq);
335 
ufshcd_disable_irq(struct ufs_hba * hba)336 void ufshcd_disable_irq(struct ufs_hba *hba)
337 {
338 	if (hba->is_irq_enabled) {
339 		disable_irq(hba->irq);
340 		hba->is_irq_enabled = false;
341 	}
342 }
343 EXPORT_SYMBOL_GPL(ufshcd_disable_irq);
344 
ufshcd_configure_wb(struct ufs_hba * hba)345 static void ufshcd_configure_wb(struct ufs_hba *hba)
346 {
347 	if (!ufshcd_is_wb_allowed(hba))
348 		return;
349 
350 	ufshcd_wb_toggle(hba, true);
351 
352 	ufshcd_wb_toggle_buf_flush_during_h8(hba, true);
353 
354 	if (ufshcd_is_wb_buf_flush_allowed(hba))
355 		ufshcd_wb_toggle_buf_flush(hba, true);
356 }
357 
ufshcd_add_cmd_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)358 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
359 				      enum ufs_trace_str_t str_t)
360 {
361 	struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
362 	struct utp_upiu_header *header;
363 
364 	if (!trace_ufshcd_upiu_enabled())
365 		return;
366 
367 	if (str_t == UFS_CMD_SEND)
368 		header = &rq->header;
369 	else
370 		header = &hba->lrb[tag].ucd_rsp_ptr->header;
371 
372 	trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
373 			  UFS_TSF_CDB);
374 }
375 
ufshcd_add_query_upiu_trace(struct ufs_hba * hba,enum ufs_trace_str_t str_t,struct utp_upiu_req * rq_rsp)376 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
377 					enum ufs_trace_str_t str_t,
378 					struct utp_upiu_req *rq_rsp)
379 {
380 	if (!trace_ufshcd_upiu_enabled())
381 		return;
382 
383 	trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
384 			  &rq_rsp->qr, UFS_TSF_OSF);
385 }
386 
ufshcd_add_tm_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)387 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
388 				     enum ufs_trace_str_t str_t)
389 {
390 	struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
391 
392 	if (!trace_ufshcd_upiu_enabled())
393 		return;
394 
395 	if (str_t == UFS_TM_SEND)
396 		trace_ufshcd_upiu(dev_name(hba->dev), str_t,
397 				  &descp->upiu_req.req_header,
398 				  &descp->upiu_req.input_param1,
399 				  UFS_TSF_TM_INPUT);
400 	else
401 		trace_ufshcd_upiu(dev_name(hba->dev), str_t,
402 				  &descp->upiu_rsp.rsp_header,
403 				  &descp->upiu_rsp.output_param1,
404 				  UFS_TSF_TM_OUTPUT);
405 }
406 
ufshcd_add_uic_command_trace(struct ufs_hba * hba,const struct uic_command * ucmd,enum ufs_trace_str_t str_t)407 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
408 					 const struct uic_command *ucmd,
409 					 enum ufs_trace_str_t str_t)
410 {
411 	u32 cmd;
412 
413 	if (!trace_ufshcd_uic_command_enabled())
414 		return;
415 
416 	if (str_t == UFS_CMD_SEND)
417 		cmd = ucmd->command;
418 	else
419 		cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
420 
421 	trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
422 				 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
423 				 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
424 				 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
425 }
426 
ufshcd_add_command_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)427 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
428 				     enum ufs_trace_str_t str_t)
429 {
430 	u64 lba = 0;
431 	u8 opcode = 0, group_id = 0;
432 	u32 doorbell = 0;
433 	u32 intr;
434 	int hwq_id = -1;
435 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
436 	struct scsi_cmnd *cmd = lrbp->cmd;
437 	struct request *rq = scsi_cmd_to_rq(cmd);
438 	int transfer_len = -1;
439 
440 	if (!cmd)
441 		return;
442 
443 	/* trace UPIU also */
444 	ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
445 	if (!trace_ufshcd_command_enabled())
446 		return;
447 
448 	opcode = cmd->cmnd[0];
449 
450 	if (opcode == READ_10 || opcode == WRITE_10) {
451 		/*
452 		 * Currently we only fully trace read(10) and write(10) commands
453 		 */
454 		transfer_len =
455 		       be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
456 		lba = scsi_get_lba(cmd);
457 		if (opcode == WRITE_10)
458 			group_id = lrbp->cmd->cmnd[6];
459 	} else if (opcode == UNMAP) {
460 		/*
461 		 * The number of Bytes to be unmapped beginning with the lba.
462 		 */
463 		transfer_len = blk_rq_bytes(rq);
464 		lba = scsi_get_lba(cmd);
465 	}
466 
467 	intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
468 
469 	if (hba->mcq_enabled) {
470 		struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq);
471 
472 		hwq_id = hwq->id;
473 	} else {
474 		doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
475 	}
476 	trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id,
477 			     transfer_len, intr, lba, opcode, group_id);
478 }
479 
ufshcd_print_clk_freqs(struct ufs_hba * hba)480 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
481 {
482 	struct ufs_clk_info *clki;
483 	struct list_head *head = &hba->clk_list_head;
484 
485 	if (list_empty(head))
486 		return;
487 
488 	list_for_each_entry(clki, head, list) {
489 		if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
490 				clki->max_freq)
491 			dev_err(hba->dev, "clk: %s, rate: %u\n",
492 					clki->name, clki->curr_freq);
493 	}
494 }
495 
ufshcd_print_evt(struct ufs_hba * hba,u32 id,const char * err_name)496 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
497 			     const char *err_name)
498 {
499 	int i;
500 	bool found = false;
501 	const struct ufs_event_hist *e;
502 
503 	if (id >= UFS_EVT_CNT)
504 		return;
505 
506 	e = &hba->ufs_stats.event[id];
507 
508 	for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
509 		int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
510 
511 		if (e->tstamp[p] == 0)
512 			continue;
513 		dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
514 			e->val[p], div_u64(e->tstamp[p], 1000));
515 		found = true;
516 	}
517 
518 	if (!found)
519 		dev_err(hba->dev, "No record of %s\n", err_name);
520 	else
521 		dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
522 }
523 
ufshcd_print_evt_hist(struct ufs_hba * hba)524 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
525 {
526 	ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
527 
528 	ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
529 	ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
530 	ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
531 	ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
532 	ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
533 	ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
534 			 "auto_hibern8_err");
535 	ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
536 	ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
537 			 "link_startup_fail");
538 	ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
539 	ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
540 			 "suspend_fail");
541 	ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail");
542 	ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR,
543 			 "wlun suspend_fail");
544 	ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
545 	ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
546 	ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
547 
548 	ufshcd_vops_dbg_register_dump(hba);
549 }
550 
551 static
ufshcd_print_tr(struct ufs_hba * hba,int tag,bool pr_prdt)552 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt)
553 {
554 	const struct ufshcd_lrb *lrbp;
555 	int prdt_length;
556 
557 	lrbp = &hba->lrb[tag];
558 
559 	dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
560 			tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
561 	dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
562 			tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
563 	dev_err(hba->dev,
564 		"UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
565 		tag, (u64)lrbp->utrd_dma_addr);
566 
567 	ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
568 			sizeof(struct utp_transfer_req_desc));
569 	dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
570 		(u64)lrbp->ucd_req_dma_addr);
571 	ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
572 			sizeof(struct utp_upiu_req));
573 	dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
574 		(u64)lrbp->ucd_rsp_dma_addr);
575 	ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
576 			sizeof(struct utp_upiu_rsp));
577 
578 	prdt_length = le16_to_cpu(
579 		lrbp->utr_descriptor_ptr->prd_table_length);
580 	if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
581 		prdt_length /= ufshcd_sg_entry_size(hba);
582 
583 	dev_err(hba->dev,
584 		"UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
585 		tag, prdt_length,
586 		(u64)lrbp->ucd_prdt_dma_addr);
587 
588 	if (pr_prdt)
589 		ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
590 			ufshcd_sg_entry_size(hba) * prdt_length);
591 }
592 
ufshcd_print_tr_iter(struct request * req,void * priv)593 static bool ufshcd_print_tr_iter(struct request *req, void *priv)
594 {
595 	struct scsi_device *sdev = req->q->queuedata;
596 	struct Scsi_Host *shost = sdev->host;
597 	struct ufs_hba *hba = shost_priv(shost);
598 
599 	ufshcd_print_tr(hba, req->tag, *(bool *)priv);
600 
601 	return true;
602 }
603 
604 /**
605  * ufshcd_print_trs_all - print trs for all started requests.
606  * @hba: per-adapter instance.
607  * @pr_prdt: need to print prdt or not.
608  */
ufshcd_print_trs_all(struct ufs_hba * hba,bool pr_prdt)609 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt)
610 {
611 	blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt);
612 }
613 
ufshcd_print_tmrs(struct ufs_hba * hba,unsigned long bitmap)614 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
615 {
616 	int tag;
617 
618 	for_each_set_bit(tag, &bitmap, hba->nutmrs) {
619 		struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
620 
621 		dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
622 		ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
623 	}
624 }
625 
ufshcd_print_host_state(struct ufs_hba * hba)626 static void ufshcd_print_host_state(struct ufs_hba *hba)
627 {
628 	const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
629 
630 	dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
631 	dev_err(hba->dev, "%d outstanding reqs, tasks=0x%lx\n",
632 		scsi_host_busy(hba->host), hba->outstanding_tasks);
633 	dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
634 		hba->saved_err, hba->saved_uic_err);
635 	dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
636 		hba->curr_dev_pwr_mode, hba->uic_link_state);
637 	dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
638 		hba->pm_op_in_progress, hba->is_sys_suspended);
639 	dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
640 		hba->auto_bkops_enabled, hba->host->host_self_blocked);
641 	dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
642 	dev_err(hba->dev,
643 		"last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
644 		div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
645 		hba->ufs_stats.hibern8_exit_cnt);
646 	dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
647 		div_u64(hba->ufs_stats.last_intr_ts, 1000),
648 		hba->ufs_stats.last_intr_status);
649 	dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
650 		hba->eh_flags, hba->req_abort_count);
651 	dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
652 		hba->ufs_version, hba->capabilities, hba->caps);
653 	dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
654 		hba->dev_quirks);
655 	if (sdev_ufs)
656 		dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
657 			sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
658 
659 	ufshcd_print_clk_freqs(hba);
660 }
661 
662 /**
663  * ufshcd_print_pwr_info - print power params as saved in hba
664  * power info
665  * @hba: per-adapter instance
666  */
ufshcd_print_pwr_info(struct ufs_hba * hba)667 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
668 {
669 	static const char * const names[] = {
670 		"INVALID MODE",
671 		"FAST MODE",
672 		"SLOW_MODE",
673 		"INVALID MODE",
674 		"FASTAUTO_MODE",
675 		"SLOWAUTO_MODE",
676 		"INVALID MODE",
677 	};
678 
679 	/*
680 	 * Using dev_dbg to avoid messages during runtime PM to avoid
681 	 * never-ending cycles of messages written back to storage by user space
682 	 * causing runtime resume, causing more messages and so on.
683 	 */
684 	dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
685 		 __func__,
686 		 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
687 		 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
688 		 names[hba->pwr_info.pwr_rx],
689 		 names[hba->pwr_info.pwr_tx],
690 		 hba->pwr_info.hs_rate);
691 }
692 
ufshcd_device_reset(struct ufs_hba * hba)693 static void ufshcd_device_reset(struct ufs_hba *hba)
694 {
695 	int err;
696 
697 	err = ufshcd_vops_device_reset(hba);
698 
699 	if (!err) {
700 		ufshcd_set_ufs_dev_active(hba);
701 		if (ufshcd_is_wb_allowed(hba)) {
702 			hba->dev_info.wb_enabled = false;
703 			hba->dev_info.wb_buf_flush_enabled = false;
704 		}
705 		if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE)
706 			hba->dev_info.rtc_time_baseline = 0;
707 	}
708 	if (err != -EOPNOTSUPP)
709 		ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
710 }
711 
ufshcd_delay_us(unsigned long us,unsigned long tolerance)712 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
713 {
714 	if (!us)
715 		return;
716 
717 	if (us < 10)
718 		udelay(us);
719 	else
720 		usleep_range(us, us + tolerance);
721 }
722 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
723 
724 /**
725  * ufshcd_wait_for_register - wait for register value to change
726  * @hba: per-adapter interface
727  * @reg: mmio register offset
728  * @mask: mask to apply to the read register value
729  * @val: value to wait for
730  * @interval_us: polling interval in microseconds
731  * @timeout_ms: timeout in milliseconds
732  *
733  * Return: -ETIMEDOUT on error, zero on success.
734  */
ufshcd_wait_for_register(struct ufs_hba * hba,u32 reg,u32 mask,u32 val,unsigned long interval_us,unsigned long timeout_ms)735 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
736 				    u32 val, unsigned long interval_us,
737 				    unsigned long timeout_ms)
738 {
739 	u32 v;
740 
741 	val &= mask; /* ignore bits that we don't intend to wait on */
742 
743 	return read_poll_timeout(ufshcd_readl, v, (v & mask) == val,
744 				 interval_us, timeout_ms * 1000, false, hba, reg);
745 }
746 
747 /**
748  * ufshcd_get_intr_mask - Get the interrupt bit mask
749  * @hba: Pointer to adapter instance
750  *
751  * Return: interrupt bit mask per version
752  */
ufshcd_get_intr_mask(struct ufs_hba * hba)753 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
754 {
755 	if (hba->ufs_version <= ufshci_version(2, 0))
756 		return INTERRUPT_MASK_ALL_VER_11;
757 
758 	return INTERRUPT_MASK_ALL_VER_21;
759 }
760 
761 /**
762  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
763  * @hba: Pointer to adapter instance
764  *
765  * Return: UFSHCI version supported by the controller
766  */
ufshcd_get_ufs_version(struct ufs_hba * hba)767 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
768 {
769 	u32 ufshci_ver;
770 
771 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
772 		ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
773 	else
774 		ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
775 
776 	/*
777 	 * UFSHCI v1.x uses a different version scheme, in order
778 	 * to allow the use of comparisons with the ufshci_version
779 	 * function, we convert it to the same scheme as ufs 2.0+.
780 	 */
781 	if (ufshci_ver & 0x00010000)
782 		return ufshci_version(1, ufshci_ver & 0x00000100);
783 
784 	return ufshci_ver;
785 }
786 
787 /**
788  * ufshcd_is_device_present - Check if any device connected to
789  *			      the host controller
790  * @hba: pointer to adapter instance
791  *
792  * Return: true if device present, false if no device detected
793  */
ufshcd_is_device_present(struct ufs_hba * hba)794 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
795 {
796 	return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
797 }
798 
799 /**
800  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
801  * @lrbp: pointer to local command reference block
802  * @cqe: pointer to the completion queue entry
803  *
804  * This function is used to get the OCS field from UTRD
805  *
806  * Return: the OCS field in the UTRD.
807  */
ufshcd_get_tr_ocs(struct ufshcd_lrb * lrbp,struct cq_entry * cqe)808 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp,
809 				      struct cq_entry *cqe)
810 {
811 	if (cqe)
812 		return le32_to_cpu(cqe->status) & MASK_OCS;
813 
814 	return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS;
815 }
816 
817 /**
818  * ufshcd_utrl_clear() - Clear requests from the controller request list.
819  * @hba: per adapter instance
820  * @mask: mask with one bit set for each request to be cleared
821  */
ufshcd_utrl_clear(struct ufs_hba * hba,u32 mask)822 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
823 {
824 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
825 		mask = ~mask;
826 	/*
827 	 * From the UFSHCI specification: "UTP Transfer Request List CLear
828 	 * Register (UTRLCLR): This field is bit significant. Each bit
829 	 * corresponds to a slot in the UTP Transfer Request List, where bit 0
830 	 * corresponds to request slot 0. A bit in this field is set to ‘0’
831 	 * by host software to indicate to the host controller that a transfer
832 	 * request slot is cleared. The host controller
833 	 * shall free up any resources associated to the request slot
834 	 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
835 	 * host software indicates no change to request slots by setting the
836 	 * associated bits in this field to ‘1’. Bits in this field shall only
837 	 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
838 	 */
839 	ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
840 }
841 
842 /**
843  * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
844  * @hba: per adapter instance
845  * @pos: position of the bit to be cleared
846  */
ufshcd_utmrl_clear(struct ufs_hba * hba,u32 pos)847 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
848 {
849 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
850 		ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
851 	else
852 		ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
853 }
854 
855 /**
856  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
857  * @reg: Register value of host controller status
858  *
859  * Return: 0 on success; a positive value if failed.
860  */
ufshcd_get_lists_status(u32 reg)861 static inline int ufshcd_get_lists_status(u32 reg)
862 {
863 	return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
864 }
865 
866 /**
867  * ufshcd_get_uic_cmd_result - Get the UIC command result
868  * @hba: Pointer to adapter instance
869  *
870  * This function gets the result of UIC command completion
871  *
872  * Return: 0 on success; non-zero value on error.
873  */
ufshcd_get_uic_cmd_result(struct ufs_hba * hba)874 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
875 {
876 	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
877 	       MASK_UIC_COMMAND_RESULT;
878 }
879 
880 /**
881  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
882  * @hba: Pointer to adapter instance
883  *
884  * This function gets UIC command argument3
885  *
886  * Return: 0 on success; non-zero value on error.
887  */
ufshcd_get_dme_attr_val(struct ufs_hba * hba)888 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
889 {
890 	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
891 }
892 
893 /**
894  * ufshcd_get_req_rsp - returns the TR response transaction type
895  * @ucd_rsp_ptr: pointer to response UPIU
896  *
897  * Return: UPIU type.
898  */
899 static inline enum upiu_response_transaction
ufshcd_get_req_rsp(struct utp_upiu_rsp * ucd_rsp_ptr)900 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
901 {
902 	return ucd_rsp_ptr->header.transaction_code;
903 }
904 
905 /**
906  * ufshcd_is_exception_event - Check if the device raised an exception event
907  * @ucd_rsp_ptr: pointer to response UPIU
908  *
909  * The function checks if the device raised an exception event indicated in
910  * the Device Information field of response UPIU.
911  *
912  * Return: true if exception is raised, false otherwise.
913  */
ufshcd_is_exception_event(struct utp_upiu_rsp * ucd_rsp_ptr)914 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
915 {
916 	return ucd_rsp_ptr->header.device_information & 1;
917 }
918 
919 /**
920  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
921  * @hba: per adapter instance
922  */
923 static inline void
ufshcd_reset_intr_aggr(struct ufs_hba * hba)924 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
925 {
926 	ufshcd_writel(hba, INT_AGGR_ENABLE |
927 		      INT_AGGR_COUNTER_AND_TIMER_RESET,
928 		      REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
929 }
930 
931 /**
932  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
933  * @hba: per adapter instance
934  * @cnt: Interrupt aggregation counter threshold
935  * @tmout: Interrupt aggregation timeout value
936  */
937 static inline void
ufshcd_config_intr_aggr(struct ufs_hba * hba,u8 cnt,u8 tmout)938 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
939 {
940 	ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
941 		      INT_AGGR_COUNTER_THLD_VAL(cnt) |
942 		      INT_AGGR_TIMEOUT_VAL(tmout),
943 		      REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
944 }
945 
946 /**
947  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
948  * @hba: per adapter instance
949  */
ufshcd_disable_intr_aggr(struct ufs_hba * hba)950 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
951 {
952 	ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
953 }
954 
955 /**
956  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
957  *			When run-stop registers are set to 1, it indicates the
958  *			host controller that it can process the requests
959  * @hba: per adapter instance
960  */
ufshcd_enable_run_stop_reg(struct ufs_hba * hba)961 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
962 {
963 	ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
964 		      REG_UTP_TASK_REQ_LIST_RUN_STOP);
965 	ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
966 		      REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
967 }
968 
969 /**
970  * ufshcd_hba_start - Start controller initialization sequence
971  * @hba: per adapter instance
972  */
ufshcd_hba_start(struct ufs_hba * hba)973 static inline void ufshcd_hba_start(struct ufs_hba *hba)
974 {
975 	u32 val = CONTROLLER_ENABLE;
976 
977 	if (ufshcd_crypto_enable(hba))
978 		val |= CRYPTO_GENERAL_ENABLE;
979 
980 	ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
981 }
982 
983 /**
984  * ufshcd_is_hba_active - Get controller state
985  * @hba: per adapter instance
986  *
987  * Return: true if and only if the controller is active.
988  */
ufshcd_is_hba_active(struct ufs_hba * hba)989 bool ufshcd_is_hba_active(struct ufs_hba *hba)
990 {
991 	return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
992 }
993 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active);
994 
995 /**
996  * ufshcd_pm_qos_init - initialize PM QoS request
997  * @hba: per adapter instance
998  */
ufshcd_pm_qos_init(struct ufs_hba * hba)999 void ufshcd_pm_qos_init(struct ufs_hba *hba)
1000 {
1001 
1002 	if (hba->pm_qos_enabled)
1003 		return;
1004 
1005 	cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE);
1006 
1007 	if (cpu_latency_qos_request_active(&hba->pm_qos_req))
1008 		hba->pm_qos_enabled = true;
1009 }
1010 
1011 /**
1012  * ufshcd_pm_qos_exit - remove request from PM QoS
1013  * @hba: per adapter instance
1014  */
ufshcd_pm_qos_exit(struct ufs_hba * hba)1015 void ufshcd_pm_qos_exit(struct ufs_hba *hba)
1016 {
1017 	if (!hba->pm_qos_enabled)
1018 		return;
1019 
1020 	cpu_latency_qos_remove_request(&hba->pm_qos_req);
1021 	hba->pm_qos_enabled = false;
1022 }
1023 
1024 /**
1025  * ufshcd_pm_qos_update - update PM QoS request
1026  * @hba: per adapter instance
1027  * @on: If True, vote for perf PM QoS mode otherwise power save mode
1028  */
ufshcd_pm_qos_update(struct ufs_hba * hba,bool on)1029 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on)
1030 {
1031 	if (!hba->pm_qos_enabled)
1032 		return;
1033 
1034 	cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE);
1035 }
1036 
1037 /**
1038  * ufshcd_set_clk_freq - set UFS controller clock frequencies
1039  * @hba: per adapter instance
1040  * @scale_up: If True, set max possible frequency othewise set low frequency
1041  *
1042  * Return: 0 if successful; < 0 upon failure.
1043  */
ufshcd_set_clk_freq(struct ufs_hba * hba,bool scale_up)1044 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
1045 {
1046 	int ret = 0;
1047 	struct ufs_clk_info *clki;
1048 	struct list_head *head = &hba->clk_list_head;
1049 
1050 	if (list_empty(head))
1051 		goto out;
1052 
1053 	list_for_each_entry(clki, head, list) {
1054 		if (!IS_ERR_OR_NULL(clki->clk)) {
1055 			if (scale_up && clki->max_freq) {
1056 				if (clki->curr_freq == clki->max_freq)
1057 					continue;
1058 
1059 				ret = clk_set_rate(clki->clk, clki->max_freq);
1060 				if (ret) {
1061 					dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1062 						__func__, clki->name,
1063 						clki->max_freq, ret);
1064 					break;
1065 				}
1066 				trace_ufshcd_clk_scaling(dev_name(hba->dev),
1067 						"scaled up", clki->name,
1068 						clki->curr_freq,
1069 						clki->max_freq);
1070 
1071 				clki->curr_freq = clki->max_freq;
1072 
1073 			} else if (!scale_up && clki->min_freq) {
1074 				if (clki->curr_freq == clki->min_freq)
1075 					continue;
1076 
1077 				ret = clk_set_rate(clki->clk, clki->min_freq);
1078 				if (ret) {
1079 					dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1080 						__func__, clki->name,
1081 						clki->min_freq, ret);
1082 					break;
1083 				}
1084 				trace_ufshcd_clk_scaling(dev_name(hba->dev),
1085 						"scaled down", clki->name,
1086 						clki->curr_freq,
1087 						clki->min_freq);
1088 				clki->curr_freq = clki->min_freq;
1089 			}
1090 		}
1091 		dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1092 				clki->name, clk_get_rate(clki->clk));
1093 	}
1094 
1095 out:
1096 	return ret;
1097 }
1098 
ufshcd_opp_config_clks(struct device * dev,struct opp_table * opp_table,struct dev_pm_opp * opp,void * data,bool scaling_down)1099 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1100 			   struct dev_pm_opp *opp, void *data,
1101 			   bool scaling_down)
1102 {
1103 	struct ufs_hba *hba = dev_get_drvdata(dev);
1104 	struct list_head *head = &hba->clk_list_head;
1105 	struct ufs_clk_info *clki;
1106 	unsigned long freq;
1107 	u8 idx = 0;
1108 	int ret;
1109 
1110 	list_for_each_entry(clki, head, list) {
1111 		if (!IS_ERR_OR_NULL(clki->clk)) {
1112 			freq = dev_pm_opp_get_freq_indexed(opp, idx++);
1113 
1114 			/* Do not set rate for clocks having frequency as 0 */
1115 			if (!freq)
1116 				continue;
1117 
1118 			ret = clk_set_rate(clki->clk, freq);
1119 			if (ret) {
1120 				dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n",
1121 					__func__, clki->name, freq, ret);
1122 				return ret;
1123 			}
1124 
1125 			trace_ufshcd_clk_scaling(dev_name(dev),
1126 				(scaling_down ? "scaled down" : "scaled up"),
1127 				clki->name, hba->clk_scaling.target_freq, freq);
1128 		}
1129 	}
1130 
1131 	return 0;
1132 }
1133 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks);
1134 
ufshcd_opp_set_rate(struct ufs_hba * hba,unsigned long freq)1135 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq)
1136 {
1137 	struct dev_pm_opp *opp;
1138 	int ret;
1139 
1140 	opp = dev_pm_opp_find_freq_floor_indexed(hba->dev,
1141 						 &freq, 0);
1142 	if (IS_ERR(opp))
1143 		return PTR_ERR(opp);
1144 
1145 	ret = dev_pm_opp_set_opp(hba->dev, opp);
1146 	dev_pm_opp_put(opp);
1147 
1148 	return ret;
1149 }
1150 
1151 /**
1152  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1153  * @hba: per adapter instance
1154  * @freq: frequency to scale
1155  * @scale_up: True if scaling up and false if scaling down
1156  *
1157  * Return: 0 if successful; < 0 upon failure.
1158  */
ufshcd_scale_clks(struct ufs_hba * hba,unsigned long freq,bool scale_up)1159 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
1160 			     bool scale_up)
1161 {
1162 	int ret = 0;
1163 	ktime_t start = ktime_get();
1164 
1165 	ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1166 	if (ret)
1167 		goto out;
1168 
1169 	if (hba->use_pm_opp)
1170 		ret = ufshcd_opp_set_rate(hba, freq);
1171 	else
1172 		ret = ufshcd_set_clk_freq(hba, scale_up);
1173 	if (ret)
1174 		goto out;
1175 
1176 	ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1177 	if (ret) {
1178 		if (hba->use_pm_opp)
1179 			ufshcd_opp_set_rate(hba,
1180 					    hba->devfreq->previous_freq);
1181 		else
1182 			ufshcd_set_clk_freq(hba, !scale_up);
1183 		goto out;
1184 	}
1185 
1186 	ufshcd_pm_qos_update(hba, scale_up);
1187 
1188 out:
1189 	trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1190 			(scale_up ? "up" : "down"),
1191 			ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1192 	return ret;
1193 }
1194 
1195 /**
1196  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1197  * @hba: per adapter instance
1198  * @freq: frequency to scale
1199  * @scale_up: True if scaling up and false if scaling down
1200  *
1201  * Return: true if scaling is required, false otherwise.
1202  */
ufshcd_is_devfreq_scaling_required(struct ufs_hba * hba,unsigned long freq,bool scale_up)1203 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1204 					       unsigned long freq, bool scale_up)
1205 {
1206 	struct ufs_clk_info *clki;
1207 	struct list_head *head = &hba->clk_list_head;
1208 
1209 	if (list_empty(head))
1210 		return false;
1211 
1212 	if (hba->use_pm_opp)
1213 		return freq != hba->clk_scaling.target_freq;
1214 
1215 	list_for_each_entry(clki, head, list) {
1216 		if (!IS_ERR_OR_NULL(clki->clk)) {
1217 			if (scale_up && clki->max_freq) {
1218 				if (clki->curr_freq == clki->max_freq)
1219 					continue;
1220 				return true;
1221 			} else if (!scale_up && clki->min_freq) {
1222 				if (clki->curr_freq == clki->min_freq)
1223 					continue;
1224 				return true;
1225 			}
1226 		}
1227 	}
1228 
1229 	return false;
1230 }
1231 
1232 /*
1233  * Determine the number of pending commands by counting the bits in the SCSI
1234  * device budget maps. This approach has been selected because a bit is set in
1235  * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1236  * flag. The host_self_blocked flag can be modified by calling
1237  * scsi_block_requests() or scsi_unblock_requests().
1238  */
ufshcd_pending_cmds(struct ufs_hba * hba)1239 static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1240 {
1241 	const struct scsi_device *sdev;
1242 	unsigned long flags;
1243 	u32 pending = 0;
1244 
1245 	spin_lock_irqsave(hba->host->host_lock, flags);
1246 	__shost_for_each_device(sdev, hba->host)
1247 		pending += sbitmap_weight(&sdev->budget_map);
1248 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1249 
1250 	return pending;
1251 }
1252 
1253 /*
1254  * Wait until all pending SCSI commands and TMFs have finished or the timeout
1255  * has expired.
1256  *
1257  * Return: 0 upon success; -EBUSY upon timeout.
1258  */
ufshcd_wait_for_doorbell_clr(struct ufs_hba * hba,u64 wait_timeout_us)1259 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1260 					u64 wait_timeout_us)
1261 {
1262 	int ret = 0;
1263 	u32 tm_doorbell;
1264 	u32 tr_pending;
1265 	bool timeout = false, do_last_check = false;
1266 	ktime_t start;
1267 
1268 	ufshcd_hold(hba);
1269 	/*
1270 	 * Wait for all the outstanding tasks/transfer requests.
1271 	 * Verify by checking the doorbell registers are clear.
1272 	 */
1273 	start = ktime_get();
1274 	do {
1275 		if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1276 			ret = -EBUSY;
1277 			goto out;
1278 		}
1279 
1280 		tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1281 		tr_pending = ufshcd_pending_cmds(hba);
1282 		if (!tm_doorbell && !tr_pending) {
1283 			timeout = false;
1284 			break;
1285 		} else if (do_last_check) {
1286 			break;
1287 		}
1288 
1289 		io_schedule_timeout(msecs_to_jiffies(20));
1290 		if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1291 		    wait_timeout_us) {
1292 			timeout = true;
1293 			/*
1294 			 * We might have scheduled out for long time so make
1295 			 * sure to check if doorbells are cleared by this time
1296 			 * or not.
1297 			 */
1298 			do_last_check = true;
1299 		}
1300 	} while (tm_doorbell || tr_pending);
1301 
1302 	if (timeout) {
1303 		dev_err(hba->dev,
1304 			"%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1305 			__func__, tm_doorbell, tr_pending);
1306 		ret = -EBUSY;
1307 	}
1308 out:
1309 	ufshcd_release(hba);
1310 	return ret;
1311 }
1312 
1313 /**
1314  * ufshcd_scale_gear - scale up/down UFS gear
1315  * @hba: per adapter instance
1316  * @scale_up: True for scaling up gear and false for scaling down
1317  *
1318  * Return: 0 for success; -EBUSY if scaling can't happen at this time;
1319  * non-zero for any other errors.
1320  */
ufshcd_scale_gear(struct ufs_hba * hba,bool scale_up)1321 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1322 {
1323 	int ret = 0;
1324 	struct ufs_pa_layer_attr new_pwr_info;
1325 
1326 	if (scale_up) {
1327 		memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info,
1328 		       sizeof(struct ufs_pa_layer_attr));
1329 	} else {
1330 		memcpy(&new_pwr_info, &hba->pwr_info,
1331 		       sizeof(struct ufs_pa_layer_attr));
1332 
1333 		if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1334 		    hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1335 			/* save the current power mode */
1336 			memcpy(&hba->clk_scaling.saved_pwr_info,
1337 				&hba->pwr_info,
1338 				sizeof(struct ufs_pa_layer_attr));
1339 
1340 			/* scale down gear */
1341 			new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1342 			new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1343 		}
1344 	}
1345 
1346 	/* check if the power mode needs to be changed or not? */
1347 	ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1348 	if (ret)
1349 		dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1350 			__func__, ret,
1351 			hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1352 			new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1353 
1354 	return ret;
1355 }
1356 
1357 /*
1358  * Wait until all pending SCSI commands and TMFs have finished or the timeout
1359  * has expired.
1360  *
1361  * Return: 0 upon success; -EBUSY upon timeout.
1362  */
ufshcd_clock_scaling_prepare(struct ufs_hba * hba,u64 timeout_us)1363 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
1364 {
1365 	int ret = 0;
1366 	/*
1367 	 * make sure that there are no outstanding requests when
1368 	 * clock scaling is in progress
1369 	 */
1370 	blk_mq_quiesce_tagset(&hba->host->tag_set);
1371 	mutex_lock(&hba->wb_mutex);
1372 	down_write(&hba->clk_scaling_lock);
1373 
1374 	if (!hba->clk_scaling.is_allowed ||
1375 	    ufshcd_wait_for_doorbell_clr(hba, timeout_us)) {
1376 		ret = -EBUSY;
1377 		up_write(&hba->clk_scaling_lock);
1378 		mutex_unlock(&hba->wb_mutex);
1379 		blk_mq_unquiesce_tagset(&hba->host->tag_set);
1380 		goto out;
1381 	}
1382 
1383 	/* let's not get into low power until clock scaling is completed */
1384 	ufshcd_hold(hba);
1385 
1386 out:
1387 	return ret;
1388 }
1389 
ufshcd_clock_scaling_unprepare(struct ufs_hba * hba,int err,bool scale_up)1390 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up)
1391 {
1392 	up_write(&hba->clk_scaling_lock);
1393 
1394 	/* Enable Write Booster if we have scaled up else disable it */
1395 	if (ufshcd_enable_wb_if_scaling_up(hba) && !err)
1396 		ufshcd_wb_toggle(hba, scale_up);
1397 
1398 	mutex_unlock(&hba->wb_mutex);
1399 
1400 	blk_mq_unquiesce_tagset(&hba->host->tag_set);
1401 	ufshcd_release(hba);
1402 }
1403 
1404 /**
1405  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1406  * @hba: per adapter instance
1407  * @freq: frequency to scale
1408  * @scale_up: True for scaling up and false for scalin down
1409  *
1410  * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero
1411  * for any other errors.
1412  */
ufshcd_devfreq_scale(struct ufs_hba * hba,unsigned long freq,bool scale_up)1413 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq,
1414 				bool scale_up)
1415 {
1416 	int ret = 0;
1417 
1418 	ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
1419 	if (ret)
1420 		return ret;
1421 
1422 	/* scale down the gear before scaling down clocks */
1423 	if (!scale_up) {
1424 		ret = ufshcd_scale_gear(hba, false);
1425 		if (ret)
1426 			goto out_unprepare;
1427 	}
1428 
1429 	ret = ufshcd_scale_clks(hba, freq, scale_up);
1430 	if (ret) {
1431 		if (!scale_up)
1432 			ufshcd_scale_gear(hba, true);
1433 		goto out_unprepare;
1434 	}
1435 
1436 	/* scale up the gear after scaling up clocks */
1437 	if (scale_up) {
1438 		ret = ufshcd_scale_gear(hba, true);
1439 		if (ret) {
1440 			ufshcd_scale_clks(hba, hba->devfreq->previous_freq,
1441 					  false);
1442 			goto out_unprepare;
1443 		}
1444 	}
1445 
1446 out_unprepare:
1447 	ufshcd_clock_scaling_unprepare(hba, ret, scale_up);
1448 	return ret;
1449 }
1450 
ufshcd_clk_scaling_suspend_work(struct work_struct * work)1451 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1452 {
1453 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1454 					   clk_scaling.suspend_work);
1455 
1456 	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1457 	{
1458 		if (hba->clk_scaling.active_reqs ||
1459 		    hba->clk_scaling.is_suspended)
1460 			return;
1461 
1462 		hba->clk_scaling.is_suspended = true;
1463 		hba->clk_scaling.window_start_t = 0;
1464 	}
1465 
1466 	devfreq_suspend_device(hba->devfreq);
1467 }
1468 
ufshcd_clk_scaling_resume_work(struct work_struct * work)1469 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1470 {
1471 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1472 					   clk_scaling.resume_work);
1473 
1474 	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1475 	{
1476 		if (!hba->clk_scaling.is_suspended)
1477 			return;
1478 		hba->clk_scaling.is_suspended = false;
1479 	}
1480 
1481 	devfreq_resume_device(hba->devfreq);
1482 }
1483 
ufshcd_devfreq_target(struct device * dev,unsigned long * freq,u32 flags)1484 static int ufshcd_devfreq_target(struct device *dev,
1485 				unsigned long *freq, u32 flags)
1486 {
1487 	int ret = 0;
1488 	struct ufs_hba *hba = dev_get_drvdata(dev);
1489 	ktime_t start;
1490 	bool scale_up = false, sched_clk_scaling_suspend_work = false;
1491 	struct list_head *clk_list = &hba->clk_list_head;
1492 	struct ufs_clk_info *clki;
1493 
1494 	if (!ufshcd_is_clkscaling_supported(hba))
1495 		return -EINVAL;
1496 
1497 	if (hba->use_pm_opp) {
1498 		struct dev_pm_opp *opp;
1499 
1500 		/* Get the recommended frequency from OPP framework */
1501 		opp = devfreq_recommended_opp(dev, freq, flags);
1502 		if (IS_ERR(opp))
1503 			return PTR_ERR(opp);
1504 
1505 		dev_pm_opp_put(opp);
1506 	} else {
1507 		/* Override with the closest supported frequency */
1508 		clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info,
1509 					list);
1510 		*freq =	(unsigned long) clk_round_rate(clki->clk, *freq);
1511 	}
1512 
1513 	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1514 	{
1515 		if (ufshcd_eh_in_progress(hba))
1516 			return 0;
1517 
1518 		/* Skip scaling clock when clock scaling is suspended */
1519 		if (hba->clk_scaling.is_suspended) {
1520 			dev_warn(hba->dev, "clock scaling is suspended, skip");
1521 			return 0;
1522 		}
1523 
1524 		if (!hba->clk_scaling.active_reqs)
1525 			sched_clk_scaling_suspend_work = true;
1526 
1527 		if (list_empty(clk_list))
1528 			goto out;
1529 
1530 		/* Decide based on the target or rounded-off frequency and update */
1531 		if (hba->use_pm_opp)
1532 			scale_up = *freq > hba->clk_scaling.target_freq;
1533 		else
1534 			scale_up = *freq == clki->max_freq;
1535 
1536 		if (!hba->use_pm_opp && !scale_up)
1537 			*freq = clki->min_freq;
1538 
1539 		/* Update the frequency */
1540 		if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) {
1541 			ret = 0;
1542 			goto out; /* no state change required */
1543 		}
1544 	}
1545 
1546 	start = ktime_get();
1547 	ret = ufshcd_devfreq_scale(hba, *freq, scale_up);
1548 	if (!ret)
1549 		hba->clk_scaling.target_freq = *freq;
1550 
1551 	trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1552 		(scale_up ? "up" : "down"),
1553 		ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1554 
1555 out:
1556 	if (sched_clk_scaling_suspend_work &&
1557 			(!scale_up || hba->clk_scaling.suspend_on_no_request))
1558 		queue_work(hba->clk_scaling.workq,
1559 			   &hba->clk_scaling.suspend_work);
1560 
1561 	return ret;
1562 }
1563 
ufshcd_devfreq_get_dev_status(struct device * dev,struct devfreq_dev_status * stat)1564 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1565 		struct devfreq_dev_status *stat)
1566 {
1567 	struct ufs_hba *hba = dev_get_drvdata(dev);
1568 	struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1569 	ktime_t curr_t;
1570 
1571 	if (!ufshcd_is_clkscaling_supported(hba))
1572 		return -EINVAL;
1573 
1574 	memset(stat, 0, sizeof(*stat));
1575 
1576 	guard(spinlock_irqsave)(&hba->clk_scaling.lock);
1577 
1578 	curr_t = ktime_get();
1579 	if (!scaling->window_start_t)
1580 		goto start_window;
1581 
1582 	/*
1583 	 * If current frequency is 0, then the ondemand governor considers
1584 	 * there's no initial frequency set. And it always requests to set
1585 	 * to max. frequency.
1586 	 */
1587 	if (hba->use_pm_opp) {
1588 		stat->current_frequency = hba->clk_scaling.target_freq;
1589 	} else {
1590 		struct list_head *clk_list = &hba->clk_list_head;
1591 		struct ufs_clk_info *clki;
1592 
1593 		clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1594 		stat->current_frequency = clki->curr_freq;
1595 	}
1596 
1597 	if (scaling->is_busy_started)
1598 		scaling->tot_busy_t += ktime_us_delta(curr_t,
1599 				scaling->busy_start_t);
1600 	stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1601 	stat->busy_time = scaling->tot_busy_t;
1602 start_window:
1603 	scaling->window_start_t = curr_t;
1604 	scaling->tot_busy_t = 0;
1605 
1606 	if (scaling->active_reqs) {
1607 		scaling->busy_start_t = curr_t;
1608 		scaling->is_busy_started = true;
1609 	} else {
1610 		scaling->busy_start_t = 0;
1611 		scaling->is_busy_started = false;
1612 	}
1613 
1614 	return 0;
1615 }
1616 
ufshcd_devfreq_init(struct ufs_hba * hba)1617 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1618 {
1619 	struct list_head *clk_list = &hba->clk_list_head;
1620 	struct ufs_clk_info *clki;
1621 	struct devfreq *devfreq;
1622 	int ret;
1623 
1624 	/* Skip devfreq if we don't have any clocks in the list */
1625 	if (list_empty(clk_list))
1626 		return 0;
1627 
1628 	if (!hba->use_pm_opp) {
1629 		clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1630 		dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1631 		dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1632 	}
1633 
1634 	ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1635 					 &hba->vps->ondemand_data);
1636 	devfreq = devfreq_add_device(hba->dev,
1637 			&hba->vps->devfreq_profile,
1638 			DEVFREQ_GOV_SIMPLE_ONDEMAND,
1639 			&hba->vps->ondemand_data);
1640 	if (IS_ERR(devfreq)) {
1641 		ret = PTR_ERR(devfreq);
1642 		dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1643 
1644 		if (!hba->use_pm_opp) {
1645 			dev_pm_opp_remove(hba->dev, clki->min_freq);
1646 			dev_pm_opp_remove(hba->dev, clki->max_freq);
1647 		}
1648 		return ret;
1649 	}
1650 
1651 	hba->devfreq = devfreq;
1652 
1653 	return 0;
1654 }
1655 
ufshcd_devfreq_remove(struct ufs_hba * hba)1656 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1657 {
1658 	struct list_head *clk_list = &hba->clk_list_head;
1659 
1660 	if (!hba->devfreq)
1661 		return;
1662 
1663 	devfreq_remove_device(hba->devfreq);
1664 	hba->devfreq = NULL;
1665 
1666 	if (!hba->use_pm_opp) {
1667 		struct ufs_clk_info *clki;
1668 
1669 		clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1670 		dev_pm_opp_remove(hba->dev, clki->min_freq);
1671 		dev_pm_opp_remove(hba->dev, clki->max_freq);
1672 	}
1673 }
1674 
ufshcd_suspend_clkscaling(struct ufs_hba * hba)1675 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1676 {
1677 	bool suspend = false;
1678 
1679 	cancel_work_sync(&hba->clk_scaling.suspend_work);
1680 	cancel_work_sync(&hba->clk_scaling.resume_work);
1681 
1682 	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1683 	{
1684 		if (!hba->clk_scaling.is_suspended) {
1685 			suspend = true;
1686 			hba->clk_scaling.is_suspended = true;
1687 			hba->clk_scaling.window_start_t = 0;
1688 		}
1689 	}
1690 
1691 	if (suspend)
1692 		devfreq_suspend_device(hba->devfreq);
1693 }
1694 
ufshcd_resume_clkscaling(struct ufs_hba * hba)1695 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1696 {
1697 	bool resume = false;
1698 
1699 	scoped_guard(spinlock_irqsave, &hba->clk_scaling.lock)
1700 	{
1701 		if (hba->clk_scaling.is_suspended) {
1702 			resume = true;
1703 			hba->clk_scaling.is_suspended = false;
1704 		}
1705 	}
1706 
1707 	if (resume)
1708 		devfreq_resume_device(hba->devfreq);
1709 }
1710 
ufshcd_clkscale_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1711 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1712 		struct device_attribute *attr, char *buf)
1713 {
1714 	struct ufs_hba *hba = dev_get_drvdata(dev);
1715 
1716 	return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1717 }
1718 
ufshcd_clkscale_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1719 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1720 		struct device_attribute *attr, const char *buf, size_t count)
1721 {
1722 	struct ufs_hba *hba = dev_get_drvdata(dev);
1723 	u32 value;
1724 	int err = 0;
1725 
1726 	if (kstrtou32(buf, 0, &value))
1727 		return -EINVAL;
1728 
1729 	down(&hba->host_sem);
1730 	if (!ufshcd_is_user_access_allowed(hba)) {
1731 		err = -EBUSY;
1732 		goto out;
1733 	}
1734 
1735 	value = !!value;
1736 	if (value == hba->clk_scaling.is_enabled)
1737 		goto out;
1738 
1739 	ufshcd_rpm_get_sync(hba);
1740 	ufshcd_hold(hba);
1741 
1742 	hba->clk_scaling.is_enabled = value;
1743 
1744 	if (value) {
1745 		ufshcd_resume_clkscaling(hba);
1746 	} else {
1747 		ufshcd_suspend_clkscaling(hba);
1748 		err = ufshcd_devfreq_scale(hba, ULONG_MAX, true);
1749 		if (err)
1750 			dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1751 					__func__, err);
1752 	}
1753 
1754 	ufshcd_release(hba);
1755 	ufshcd_rpm_put_sync(hba);
1756 out:
1757 	up(&hba->host_sem);
1758 	return err ? err : count;
1759 }
1760 
ufshcd_init_clk_scaling_sysfs(struct ufs_hba * hba)1761 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1762 {
1763 	hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1764 	hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1765 	sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1766 	hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1767 	hba->clk_scaling.enable_attr.attr.mode = 0644;
1768 	if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1769 		dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1770 }
1771 
ufshcd_remove_clk_scaling_sysfs(struct ufs_hba * hba)1772 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1773 {
1774 	if (hba->clk_scaling.enable_attr.attr.name)
1775 		device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1776 }
1777 
ufshcd_init_clk_scaling(struct ufs_hba * hba)1778 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1779 {
1780 	if (!ufshcd_is_clkscaling_supported(hba))
1781 		return;
1782 
1783 	if (!hba->clk_scaling.min_gear)
1784 		hba->clk_scaling.min_gear = UFS_HS_G1;
1785 
1786 	INIT_WORK(&hba->clk_scaling.suspend_work,
1787 		  ufshcd_clk_scaling_suspend_work);
1788 	INIT_WORK(&hba->clk_scaling.resume_work,
1789 		  ufshcd_clk_scaling_resume_work);
1790 
1791 	spin_lock_init(&hba->clk_scaling.lock);
1792 
1793 	hba->clk_scaling.workq = alloc_ordered_workqueue(
1794 		"ufs_clkscaling_%d", WQ_MEM_RECLAIM, hba->host->host_no);
1795 
1796 	hba->clk_scaling.is_initialized = true;
1797 }
1798 
ufshcd_exit_clk_scaling(struct ufs_hba * hba)1799 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1800 {
1801 	if (!hba->clk_scaling.is_initialized)
1802 		return;
1803 
1804 	ufshcd_remove_clk_scaling_sysfs(hba);
1805 	destroy_workqueue(hba->clk_scaling.workq);
1806 	ufshcd_devfreq_remove(hba);
1807 	hba->clk_scaling.is_initialized = false;
1808 }
1809 
ufshcd_ungate_work(struct work_struct * work)1810 static void ufshcd_ungate_work(struct work_struct *work)
1811 {
1812 	int ret;
1813 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1814 			clk_gating.ungate_work);
1815 
1816 	cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1817 
1818 	scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) {
1819 		if (hba->clk_gating.state == CLKS_ON)
1820 			return;
1821 	}
1822 
1823 	ufshcd_hba_vreg_set_hpm(hba);
1824 	ufshcd_setup_clocks(hba, true);
1825 
1826 	ufshcd_enable_irq(hba);
1827 
1828 	/* Exit from hibern8 */
1829 	if (ufshcd_can_hibern8_during_gating(hba)) {
1830 		/* Prevent gating in this path */
1831 		hba->clk_gating.is_suspended = true;
1832 		if (ufshcd_is_link_hibern8(hba)) {
1833 			ret = ufshcd_uic_hibern8_exit(hba);
1834 			if (ret)
1835 				dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1836 					__func__, ret);
1837 			else
1838 				ufshcd_set_link_active(hba);
1839 		}
1840 		hba->clk_gating.is_suspended = false;
1841 	}
1842 }
1843 
1844 /**
1845  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1846  * Also, exit from hibern8 mode and set the link as active.
1847  * @hba: per adapter instance
1848  */
ufshcd_hold(struct ufs_hba * hba)1849 void ufshcd_hold(struct ufs_hba *hba)
1850 {
1851 	bool flush_result;
1852 	unsigned long flags;
1853 
1854 	if (!ufshcd_is_clkgating_allowed(hba) ||
1855 	    !hba->clk_gating.is_initialized)
1856 		return;
1857 	spin_lock_irqsave(&hba->clk_gating.lock, flags);
1858 	hba->clk_gating.active_reqs++;
1859 
1860 start:
1861 	switch (hba->clk_gating.state) {
1862 	case CLKS_ON:
1863 		/*
1864 		 * Wait for the ungate work to complete if in progress.
1865 		 * Though the clocks may be in ON state, the link could
1866 		 * still be in hibner8 state if hibern8 is allowed
1867 		 * during clock gating.
1868 		 * Make sure we exit hibern8 state also in addition to
1869 		 * clocks being ON.
1870 		 */
1871 		if (ufshcd_can_hibern8_during_gating(hba) &&
1872 		    ufshcd_is_link_hibern8(hba)) {
1873 			spin_unlock_irqrestore(&hba->clk_gating.lock, flags);
1874 			flush_result = flush_work(&hba->clk_gating.ungate_work);
1875 			if (hba->clk_gating.is_suspended && !flush_result)
1876 				return;
1877 			spin_lock_irqsave(&hba->clk_gating.lock, flags);
1878 			goto start;
1879 		}
1880 		break;
1881 	case REQ_CLKS_OFF:
1882 		if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1883 			hba->clk_gating.state = CLKS_ON;
1884 			trace_ufshcd_clk_gating(dev_name(hba->dev),
1885 						hba->clk_gating.state);
1886 			break;
1887 		}
1888 		/*
1889 		 * If we are here, it means gating work is either done or
1890 		 * currently running. Hence, fall through to cancel gating
1891 		 * work and to enable clocks.
1892 		 */
1893 		fallthrough;
1894 	case CLKS_OFF:
1895 		hba->clk_gating.state = REQ_CLKS_ON;
1896 		trace_ufshcd_clk_gating(dev_name(hba->dev),
1897 					hba->clk_gating.state);
1898 		queue_work(hba->clk_gating.clk_gating_workq,
1899 			   &hba->clk_gating.ungate_work);
1900 		/*
1901 		 * fall through to check if we should wait for this
1902 		 * work to be done or not.
1903 		 */
1904 		fallthrough;
1905 	case REQ_CLKS_ON:
1906 		spin_unlock_irqrestore(&hba->clk_gating.lock, flags);
1907 		flush_work(&hba->clk_gating.ungate_work);
1908 		/* Make sure state is CLKS_ON before returning */
1909 		spin_lock_irqsave(&hba->clk_gating.lock, flags);
1910 		goto start;
1911 	default:
1912 		dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1913 				__func__, hba->clk_gating.state);
1914 		break;
1915 	}
1916 	spin_unlock_irqrestore(&hba->clk_gating.lock, flags);
1917 }
1918 EXPORT_SYMBOL_GPL(ufshcd_hold);
1919 
ufshcd_gate_work(struct work_struct * work)1920 static void ufshcd_gate_work(struct work_struct *work)
1921 {
1922 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1923 			clk_gating.gate_work.work);
1924 	int ret;
1925 
1926 	scoped_guard(spinlock_irqsave, &hba->clk_gating.lock) {
1927 		/*
1928 		 * In case you are here to cancel this work the gating state
1929 		 * would be marked as REQ_CLKS_ON. In this case save time by
1930 		 * skipping the gating work and exit after changing the clock
1931 		 * state to CLKS_ON.
1932 		 */
1933 		if (hba->clk_gating.is_suspended ||
1934 		    hba->clk_gating.state != REQ_CLKS_OFF) {
1935 			hba->clk_gating.state = CLKS_ON;
1936 			trace_ufshcd_clk_gating(dev_name(hba->dev),
1937 						hba->clk_gating.state);
1938 			return;
1939 		}
1940 
1941 		if (hba->clk_gating.active_reqs)
1942 			return;
1943 	}
1944 
1945 	scoped_guard(spinlock_irqsave, hba->host->host_lock) {
1946 		if (ufshcd_is_ufs_dev_busy(hba) ||
1947 		    hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
1948 			return;
1949 	}
1950 
1951 	/* put the link into hibern8 mode before turning off clocks */
1952 	if (ufshcd_can_hibern8_during_gating(hba)) {
1953 		ret = ufshcd_uic_hibern8_enter(hba);
1954 		if (ret) {
1955 			hba->clk_gating.state = CLKS_ON;
1956 			dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1957 					__func__, ret);
1958 			trace_ufshcd_clk_gating(dev_name(hba->dev),
1959 						hba->clk_gating.state);
1960 			return;
1961 		}
1962 		ufshcd_set_link_hibern8(hba);
1963 	}
1964 
1965 	ufshcd_disable_irq(hba);
1966 
1967 	ufshcd_setup_clocks(hba, false);
1968 
1969 	/* Put the host controller in low power mode if possible */
1970 	ufshcd_hba_vreg_set_lpm(hba);
1971 	/*
1972 	 * In case you are here to cancel this work the gating state
1973 	 * would be marked as REQ_CLKS_ON. In this case keep the state
1974 	 * as REQ_CLKS_ON which would anyway imply that clocks are off
1975 	 * and a request to turn them on is pending. By doing this way,
1976 	 * we keep the state machine in tact and this would ultimately
1977 	 * prevent from doing cancel work multiple times when there are
1978 	 * new requests arriving before the current cancel work is done.
1979 	 */
1980 	guard(spinlock_irqsave)(&hba->clk_gating.lock);
1981 	if (hba->clk_gating.state == REQ_CLKS_OFF) {
1982 		hba->clk_gating.state = CLKS_OFF;
1983 		trace_ufshcd_clk_gating(dev_name(hba->dev),
1984 					hba->clk_gating.state);
1985 	}
1986 }
1987 
__ufshcd_release(struct ufs_hba * hba)1988 static void __ufshcd_release(struct ufs_hba *hba)
1989 {
1990 	lockdep_assert_held(&hba->clk_gating.lock);
1991 
1992 	if (!ufshcd_is_clkgating_allowed(hba))
1993 		return;
1994 
1995 	hba->clk_gating.active_reqs--;
1996 
1997 	if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1998 	    !hba->clk_gating.is_initialized ||
1999 	    hba->clk_gating.state == CLKS_OFF)
2000 		return;
2001 
2002 	scoped_guard(spinlock_irqsave, hba->host->host_lock) {
2003 		if (ufshcd_has_pending_tasks(hba) ||
2004 		    hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
2005 			return;
2006 	}
2007 
2008 	hba->clk_gating.state = REQ_CLKS_OFF;
2009 	trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
2010 	queue_delayed_work(hba->clk_gating.clk_gating_workq,
2011 			   &hba->clk_gating.gate_work,
2012 			   msecs_to_jiffies(hba->clk_gating.delay_ms));
2013 }
2014 
ufshcd_release(struct ufs_hba * hba)2015 void ufshcd_release(struct ufs_hba *hba)
2016 {
2017 	guard(spinlock_irqsave)(&hba->clk_gating.lock);
2018 	__ufshcd_release(hba);
2019 }
2020 EXPORT_SYMBOL_GPL(ufshcd_release);
2021 
ufshcd_clkgate_delay_show(struct device * dev,struct device_attribute * attr,char * buf)2022 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
2023 		struct device_attribute *attr, char *buf)
2024 {
2025 	struct ufs_hba *hba = dev_get_drvdata(dev);
2026 
2027 	return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
2028 }
2029 
ufshcd_clkgate_delay_set(struct device * dev,unsigned long value)2030 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
2031 {
2032 	struct ufs_hba *hba = dev_get_drvdata(dev);
2033 
2034 	guard(spinlock_irqsave)(&hba->clk_gating.lock);
2035 	hba->clk_gating.delay_ms = value;
2036 }
2037 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
2038 
ufshcd_clkgate_delay_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2039 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
2040 		struct device_attribute *attr, const char *buf, size_t count)
2041 {
2042 	unsigned long value;
2043 
2044 	if (kstrtoul(buf, 0, &value))
2045 		return -EINVAL;
2046 
2047 	ufshcd_clkgate_delay_set(dev, value);
2048 	return count;
2049 }
2050 
ufshcd_clkgate_enable_show(struct device * dev,struct device_attribute * attr,char * buf)2051 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
2052 		struct device_attribute *attr, char *buf)
2053 {
2054 	struct ufs_hba *hba = dev_get_drvdata(dev);
2055 
2056 	return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
2057 }
2058 
ufshcd_clkgate_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2059 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
2060 		struct device_attribute *attr, const char *buf, size_t count)
2061 {
2062 	struct ufs_hba *hba = dev_get_drvdata(dev);
2063 	u32 value;
2064 
2065 	if (kstrtou32(buf, 0, &value))
2066 		return -EINVAL;
2067 
2068 	value = !!value;
2069 
2070 	guard(spinlock_irqsave)(&hba->clk_gating.lock);
2071 
2072 	if (value == hba->clk_gating.is_enabled)
2073 		return count;
2074 
2075 	if (value)
2076 		__ufshcd_release(hba);
2077 	else
2078 		hba->clk_gating.active_reqs++;
2079 
2080 	hba->clk_gating.is_enabled = value;
2081 
2082 	return count;
2083 }
2084 
ufshcd_init_clk_gating_sysfs(struct ufs_hba * hba)2085 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
2086 {
2087 	hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
2088 	hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
2089 	sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
2090 	hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
2091 	hba->clk_gating.delay_attr.attr.mode = 0644;
2092 	if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
2093 		dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
2094 
2095 	hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
2096 	hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
2097 	sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
2098 	hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
2099 	hba->clk_gating.enable_attr.attr.mode = 0644;
2100 	if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
2101 		dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
2102 }
2103 
ufshcd_remove_clk_gating_sysfs(struct ufs_hba * hba)2104 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
2105 {
2106 	if (hba->clk_gating.delay_attr.attr.name)
2107 		device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
2108 	if (hba->clk_gating.enable_attr.attr.name)
2109 		device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
2110 }
2111 
ufshcd_init_clk_gating(struct ufs_hba * hba)2112 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
2113 {
2114 	if (!ufshcd_is_clkgating_allowed(hba))
2115 		return;
2116 
2117 	hba->clk_gating.state = CLKS_ON;
2118 
2119 	hba->clk_gating.delay_ms = 150;
2120 	INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2121 	INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2122 
2123 	hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(
2124 		"ufs_clk_gating_%d", WQ_MEM_RECLAIM | WQ_HIGHPRI,
2125 		hba->host->host_no);
2126 
2127 	ufshcd_init_clk_gating_sysfs(hba);
2128 
2129 	hba->clk_gating.is_enabled = true;
2130 	hba->clk_gating.is_initialized = true;
2131 }
2132 
ufshcd_exit_clk_gating(struct ufs_hba * hba)2133 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2134 {
2135 	if (!hba->clk_gating.is_initialized)
2136 		return;
2137 
2138 	ufshcd_remove_clk_gating_sysfs(hba);
2139 
2140 	/* Ungate the clock if necessary. */
2141 	ufshcd_hold(hba);
2142 	hba->clk_gating.is_initialized = false;
2143 	ufshcd_release(hba);
2144 
2145 	destroy_workqueue(hba->clk_gating.clk_gating_workq);
2146 }
2147 
ufshcd_clk_scaling_start_busy(struct ufs_hba * hba)2148 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2149 {
2150 	bool queue_resume_work = false;
2151 	ktime_t curr_t = ktime_get();
2152 
2153 	if (!ufshcd_is_clkscaling_supported(hba))
2154 		return;
2155 
2156 	guard(spinlock_irqsave)(&hba->clk_scaling.lock);
2157 
2158 	if (!hba->clk_scaling.active_reqs++)
2159 		queue_resume_work = true;
2160 
2161 	if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress)
2162 		return;
2163 
2164 	if (queue_resume_work)
2165 		queue_work(hba->clk_scaling.workq,
2166 			   &hba->clk_scaling.resume_work);
2167 
2168 	if (!hba->clk_scaling.window_start_t) {
2169 		hba->clk_scaling.window_start_t = curr_t;
2170 		hba->clk_scaling.tot_busy_t = 0;
2171 		hba->clk_scaling.is_busy_started = false;
2172 	}
2173 
2174 	if (!hba->clk_scaling.is_busy_started) {
2175 		hba->clk_scaling.busy_start_t = curr_t;
2176 		hba->clk_scaling.is_busy_started = true;
2177 	}
2178 }
2179 
ufshcd_clk_scaling_update_busy(struct ufs_hba * hba)2180 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2181 {
2182 	struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2183 
2184 	if (!ufshcd_is_clkscaling_supported(hba))
2185 		return;
2186 
2187 	guard(spinlock_irqsave)(&hba->clk_scaling.lock);
2188 
2189 	hba->clk_scaling.active_reqs--;
2190 	if (!scaling->active_reqs && scaling->is_busy_started) {
2191 		scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2192 					scaling->busy_start_t));
2193 		scaling->busy_start_t = 0;
2194 		scaling->is_busy_started = false;
2195 	}
2196 }
2197 
ufshcd_monitor_opcode2dir(u8 opcode)2198 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2199 {
2200 	if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2201 		return READ;
2202 	else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2203 		return WRITE;
2204 	else
2205 		return -EINVAL;
2206 }
2207 
ufshcd_should_inform_monitor(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2208 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2209 						struct ufshcd_lrb *lrbp)
2210 {
2211 	const struct ufs_hba_monitor *m = &hba->monitor;
2212 
2213 	return (m->enabled && lrbp && lrbp->cmd &&
2214 		(!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2215 		ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2216 }
2217 
ufshcd_start_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2218 static void ufshcd_start_monitor(struct ufs_hba *hba,
2219 				 const struct ufshcd_lrb *lrbp)
2220 {
2221 	int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2222 	unsigned long flags;
2223 
2224 	spin_lock_irqsave(hba->host->host_lock, flags);
2225 	if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2226 		hba->monitor.busy_start_ts[dir] = ktime_get();
2227 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2228 }
2229 
ufshcd_update_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2230 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp)
2231 {
2232 	int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2233 	unsigned long flags;
2234 
2235 	spin_lock_irqsave(hba->host->host_lock, flags);
2236 	if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2237 		const struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2238 		struct ufs_hba_monitor *m = &hba->monitor;
2239 		ktime_t now, inc, lat;
2240 
2241 		now = lrbp->compl_time_stamp;
2242 		inc = ktime_sub(now, m->busy_start_ts[dir]);
2243 		m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2244 		m->nr_sec_rw[dir] += blk_rq_sectors(req);
2245 
2246 		/* Update latencies */
2247 		m->nr_req[dir]++;
2248 		lat = ktime_sub(now, lrbp->issue_time_stamp);
2249 		m->lat_sum[dir] += lat;
2250 		if (m->lat_max[dir] < lat || !m->lat_max[dir])
2251 			m->lat_max[dir] = lat;
2252 		if (m->lat_min[dir] > lat || !m->lat_min[dir])
2253 			m->lat_min[dir] = lat;
2254 
2255 		m->nr_queued[dir]--;
2256 		/* Push forward the busy start of monitor */
2257 		m->busy_start_ts[dir] = now;
2258 	}
2259 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2260 }
2261 
2262 /**
2263  * ufshcd_send_command - Send SCSI or device management commands
2264  * @hba: per adapter instance
2265  * @task_tag: Task tag of the command
2266  * @hwq: pointer to hardware queue instance
2267  */
2268 static inline
ufshcd_send_command(struct ufs_hba * hba,unsigned int task_tag,struct ufs_hw_queue * hwq)2269 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag,
2270 			 struct ufs_hw_queue *hwq)
2271 {
2272 	struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2273 	unsigned long flags;
2274 
2275 	lrbp->issue_time_stamp = ktime_get();
2276 	lrbp->issue_time_stamp_local_clock = local_clock();
2277 	lrbp->compl_time_stamp = ktime_set(0, 0);
2278 	lrbp->compl_time_stamp_local_clock = 0;
2279 	ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2280 	if (lrbp->cmd)
2281 		ufshcd_clk_scaling_start_busy(hba);
2282 	if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2283 		ufshcd_start_monitor(hba, lrbp);
2284 
2285 	if (hba->mcq_enabled) {
2286 		int utrd_size = sizeof(struct utp_transfer_req_desc);
2287 		struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr;
2288 		struct utp_transfer_req_desc *dest;
2289 
2290 		spin_lock(&hwq->sq_lock);
2291 		dest = hwq->sqe_base_addr + hwq->sq_tail_slot;
2292 		memcpy(dest, src, utrd_size);
2293 		ufshcd_inc_sq_tail(hwq);
2294 		spin_unlock(&hwq->sq_lock);
2295 	} else {
2296 		spin_lock_irqsave(&hba->outstanding_lock, flags);
2297 		if (hba->vops && hba->vops->setup_xfer_req)
2298 			hba->vops->setup_xfer_req(hba, lrbp->task_tag,
2299 						  !!lrbp->cmd);
2300 		__set_bit(lrbp->task_tag, &hba->outstanding_reqs);
2301 		ufshcd_writel(hba, 1 << lrbp->task_tag,
2302 			      REG_UTP_TRANSFER_REQ_DOOR_BELL);
2303 		spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2304 	}
2305 }
2306 
2307 /**
2308  * ufshcd_copy_sense_data - Copy sense data in case of check condition
2309  * @lrbp: pointer to local reference block
2310  */
ufshcd_copy_sense_data(struct ufshcd_lrb * lrbp)2311 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2312 {
2313 	u8 *const sense_buffer = lrbp->cmd->sense_buffer;
2314 	u16 resp_len;
2315 	int len;
2316 
2317 	resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length);
2318 	if (sense_buffer && resp_len) {
2319 		int len_to_copy;
2320 
2321 		len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2322 		len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2323 
2324 		memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2325 		       len_to_copy);
2326 	}
2327 }
2328 
2329 /**
2330  * ufshcd_copy_query_response() - Copy the Query Response and the data
2331  * descriptor
2332  * @hba: per adapter instance
2333  * @lrbp: pointer to local reference block
2334  *
2335  * Return: 0 upon success; < 0 upon failure.
2336  */
2337 static
ufshcd_copy_query_response(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2338 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2339 {
2340 	struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2341 
2342 	memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2343 
2344 	/* Get the descriptor */
2345 	if (hba->dev_cmd.query.descriptor &&
2346 	    lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2347 		u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2348 				GENERAL_UPIU_REQUEST_SIZE;
2349 		u16 resp_len;
2350 		u16 buf_len;
2351 
2352 		/* data segment length */
2353 		resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
2354 				       .data_segment_length);
2355 		buf_len = be16_to_cpu(
2356 				hba->dev_cmd.query.request.upiu_req.length);
2357 		if (likely(buf_len >= resp_len)) {
2358 			memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2359 		} else {
2360 			dev_warn(hba->dev,
2361 				 "%s: rsp size %d is bigger than buffer size %d",
2362 				 __func__, resp_len, buf_len);
2363 			return -EINVAL;
2364 		}
2365 	}
2366 
2367 	return 0;
2368 }
2369 
2370 /**
2371  * ufshcd_hba_capabilities - Read controller capabilities
2372  * @hba: per adapter instance
2373  *
2374  * Return: 0 on success, negative on error.
2375  */
ufshcd_hba_capabilities(struct ufs_hba * hba)2376 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2377 {
2378 	int err;
2379 
2380 	hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2381 
2382 	/* nutrs and nutmrs are 0 based values */
2383 	hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1;
2384 	hba->nutmrs =
2385 	((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2386 	hba->reserved_slot = hba->nutrs - 1;
2387 
2388 	hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1;
2389 
2390 	/* Read crypto capabilities */
2391 	err = ufshcd_hba_init_crypto_capabilities(hba);
2392 	if (err) {
2393 		dev_err(hba->dev, "crypto setup failed\n");
2394 		return err;
2395 	}
2396 
2397 	/*
2398 	 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and
2399 	 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which
2400 	 * means we can simply read values regardless of version.
2401 	 */
2402 	hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities);
2403 	/*
2404 	 * 0h: legacy single doorbell support is available
2405 	 * 1h: indicate that legacy single doorbell support has been removed
2406 	 */
2407 	if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_LSDBS_CAP))
2408 		hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities);
2409 	else
2410 		hba->lsdb_sup = true;
2411 
2412 	hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2413 
2414 	return 0;
2415 }
2416 
2417 /**
2418  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2419  *                            to accept UIC commands
2420  * @hba: per adapter instance
2421  *
2422  * Return: true on success, else false.
2423  */
ufshcd_ready_for_uic_cmd(struct ufs_hba * hba)2424 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2425 {
2426 	u32 val;
2427 	int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
2428 				    500, uic_cmd_timeout * 1000, false, hba,
2429 				    REG_CONTROLLER_STATUS);
2430 	return ret == 0;
2431 }
2432 
2433 /**
2434  * ufshcd_get_upmcrs - Get the power mode change request status
2435  * @hba: Pointer to adapter instance
2436  *
2437  * This function gets the UPMCRS field of HCS register
2438  *
2439  * Return: value of UPMCRS field.
2440  */
ufshcd_get_upmcrs(struct ufs_hba * hba)2441 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2442 {
2443 	return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2444 }
2445 
2446 /**
2447  * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2448  * @hba: per adapter instance
2449  * @uic_cmd: UIC command
2450  */
2451 static inline void
ufshcd_dispatch_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2452 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2453 {
2454 	lockdep_assert_held(&hba->uic_cmd_mutex);
2455 
2456 	WARN_ON(hba->active_uic_cmd);
2457 
2458 	hba->active_uic_cmd = uic_cmd;
2459 
2460 	/* Write Args */
2461 	ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2462 	ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2463 	ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2464 
2465 	ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2466 
2467 	/* Write UIC Cmd */
2468 	ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2469 		      REG_UIC_COMMAND);
2470 }
2471 
2472 /**
2473  * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2474  * @hba: per adapter instance
2475  * @uic_cmd: UIC command
2476  *
2477  * Return: 0 only if success.
2478  */
2479 static int
ufshcd_wait_for_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2480 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2481 {
2482 	int ret;
2483 	unsigned long flags;
2484 
2485 	lockdep_assert_held(&hba->uic_cmd_mutex);
2486 
2487 	if (wait_for_completion_timeout(&uic_cmd->done,
2488 					msecs_to_jiffies(uic_cmd_timeout))) {
2489 		ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2490 	} else {
2491 		ret = -ETIMEDOUT;
2492 		dev_err(hba->dev,
2493 			"uic cmd 0x%x with arg3 0x%x completion timeout\n",
2494 			uic_cmd->command, uic_cmd->argument3);
2495 
2496 		if (!uic_cmd->cmd_active) {
2497 			dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2498 				__func__);
2499 			ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2500 		}
2501 	}
2502 
2503 	spin_lock_irqsave(hba->host->host_lock, flags);
2504 	hba->active_uic_cmd = NULL;
2505 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2506 
2507 	return ret;
2508 }
2509 
2510 /**
2511  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2512  * @hba: per adapter instance
2513  * @uic_cmd: UIC command
2514  *
2515  * Return: 0 only if success.
2516  */
2517 static int
__ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2518 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2519 {
2520 	lockdep_assert_held(&hba->uic_cmd_mutex);
2521 
2522 	if (!ufshcd_ready_for_uic_cmd(hba)) {
2523 		dev_err(hba->dev,
2524 			"Controller not ready to accept UIC commands\n");
2525 		return -EIO;
2526 	}
2527 
2528 	init_completion(&uic_cmd->done);
2529 
2530 	uic_cmd->cmd_active = 1;
2531 	ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2532 
2533 	return 0;
2534 }
2535 
2536 /**
2537  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2538  * @hba: per adapter instance
2539  * @uic_cmd: UIC command
2540  *
2541  * Return: 0 only if success.
2542  */
ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2543 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2544 {
2545 	int ret;
2546 
2547 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2548 		return 0;
2549 
2550 	ufshcd_hold(hba);
2551 	mutex_lock(&hba->uic_cmd_mutex);
2552 	ufshcd_add_delay_before_dme_cmd(hba);
2553 
2554 	ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
2555 	if (!ret)
2556 		ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2557 
2558 	mutex_unlock(&hba->uic_cmd_mutex);
2559 
2560 	ufshcd_release(hba);
2561 	return ret;
2562 }
2563 
2564 /**
2565  * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2566  * @hba:	per-adapter instance
2567  * @lrbp:	pointer to local reference block
2568  * @sg_entries:	The number of sg lists actually used
2569  * @sg_list:	Pointer to SG list
2570  */
ufshcd_sgl_to_prdt(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int sg_entries,struct scatterlist * sg_list)2571 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2572 			       struct scatterlist *sg_list)
2573 {
2574 	struct ufshcd_sg_entry *prd;
2575 	struct scatterlist *sg;
2576 	int i;
2577 
2578 	if (sg_entries) {
2579 
2580 		if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2581 			lrbp->utr_descriptor_ptr->prd_table_length =
2582 				cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
2583 		else
2584 			lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
2585 
2586 		prd = lrbp->ucd_prdt_ptr;
2587 
2588 		for_each_sg(sg_list, sg, sg_entries, i) {
2589 			const unsigned int len = sg_dma_len(sg);
2590 
2591 			/*
2592 			 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2593 			 * based value that indicates the length, in bytes, of
2594 			 * the data block. A maximum of length of 256KB may
2595 			 * exist for any entry. Bits 1:0 of this field shall be
2596 			 * 11b to indicate Dword granularity. A value of '3'
2597 			 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2598 			 */
2599 			WARN_ONCE(len > SZ_256K, "len = %#x\n", len);
2600 			prd->size = cpu_to_le32(len - 1);
2601 			prd->addr = cpu_to_le64(sg->dma_address);
2602 			prd->reserved = 0;
2603 			prd = (void *)prd + ufshcd_sg_entry_size(hba);
2604 		}
2605 	} else {
2606 		lrbp->utr_descriptor_ptr->prd_table_length = 0;
2607 	}
2608 }
2609 
2610 /**
2611  * ufshcd_map_sg - Map scatter-gather list to prdt
2612  * @hba: per adapter instance
2613  * @lrbp: pointer to local reference block
2614  *
2615  * Return: 0 in case of success, non-zero value in case of failure.
2616  */
ufshcd_map_sg(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2617 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2618 {
2619 	struct scsi_cmnd *cmd = lrbp->cmd;
2620 	int sg_segments = scsi_dma_map(cmd);
2621 
2622 	if (sg_segments < 0)
2623 		return sg_segments;
2624 
2625 	ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd));
2626 
2627 	return ufshcd_crypto_fill_prdt(hba, lrbp);
2628 }
2629 
2630 /**
2631  * ufshcd_enable_intr - enable interrupts
2632  * @hba: per adapter instance
2633  * @intrs: interrupt bits
2634  */
ufshcd_enable_intr(struct ufs_hba * hba,u32 intrs)2635 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2636 {
2637 	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2638 
2639 	set |= intrs;
2640 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2641 }
2642 
2643 /**
2644  * ufshcd_disable_intr - disable interrupts
2645  * @hba: per adapter instance
2646  * @intrs: interrupt bits
2647  */
ufshcd_disable_intr(struct ufs_hba * hba,u32 intrs)2648 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2649 {
2650 	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2651 
2652 	set &= ~intrs;
2653 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2654 }
2655 
2656 /**
2657  * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
2658  * descriptor according to request
2659  * @hba: per adapter instance
2660  * @lrbp: pointer to local reference block
2661  * @upiu_flags: flags required in the header
2662  * @cmd_dir: requests data direction
2663  * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
2664  */
2665 static void
ufshcd_prepare_req_desc_hdr(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,u8 * upiu_flags,enum dma_data_direction cmd_dir,int ehs_length)2666 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
2667 			    u8 *upiu_flags, enum dma_data_direction cmd_dir,
2668 			    int ehs_length)
2669 {
2670 	struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2671 	struct request_desc_header *h = &req_desc->header;
2672 	enum utp_data_direction data_direction;
2673 
2674 	lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2675 
2676 	*h = (typeof(*h)){ };
2677 
2678 	if (cmd_dir == DMA_FROM_DEVICE) {
2679 		data_direction = UTP_DEVICE_TO_HOST;
2680 		*upiu_flags = UPIU_CMD_FLAGS_READ;
2681 	} else if (cmd_dir == DMA_TO_DEVICE) {
2682 		data_direction = UTP_HOST_TO_DEVICE;
2683 		*upiu_flags = UPIU_CMD_FLAGS_WRITE;
2684 	} else {
2685 		data_direction = UTP_NO_DATA_TRANSFER;
2686 		*upiu_flags = UPIU_CMD_FLAGS_NONE;
2687 	}
2688 
2689 	h->command_type = lrbp->command_type;
2690 	h->data_direction = data_direction;
2691 	h->ehs_length = ehs_length;
2692 
2693 	if (lrbp->intr_cmd)
2694 		h->interrupt = 1;
2695 
2696 	/* Prepare crypto related dwords */
2697 	ufshcd_prepare_req_desc_hdr_crypto(lrbp, h);
2698 
2699 	/*
2700 	 * assigning invalid value for command status. Controller
2701 	 * updates OCS on command completion, with the command
2702 	 * status
2703 	 */
2704 	h->ocs = OCS_INVALID_COMMAND_STATUS;
2705 
2706 	req_desc->prd_table_length = 0;
2707 }
2708 
2709 /**
2710  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2711  * for scsi commands
2712  * @lrbp: local reference block pointer
2713  * @upiu_flags: flags
2714  */
2715 static
ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb * lrbp,u8 upiu_flags)2716 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2717 {
2718 	struct scsi_cmnd *cmd = lrbp->cmd;
2719 	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2720 	unsigned short cdb_len;
2721 
2722 	ucd_req_ptr->header = (struct utp_upiu_header){
2723 		.transaction_code = UPIU_TRANSACTION_COMMAND,
2724 		.flags = upiu_flags,
2725 		.lun = lrbp->lun,
2726 		.task_tag = lrbp->task_tag,
2727 		.command_set_type = UPIU_COMMAND_SET_TYPE_SCSI,
2728 	};
2729 
2730 	WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag);
2731 
2732 	ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2733 
2734 	cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2735 	memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2736 
2737 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2738 }
2739 
2740 /**
2741  * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
2742  * @hba: UFS hba
2743  * @lrbp: local reference block pointer
2744  * @upiu_flags: flags
2745  */
ufshcd_prepare_utp_query_req_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,u8 upiu_flags)2746 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2747 				struct ufshcd_lrb *lrbp, u8 upiu_flags)
2748 {
2749 	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2750 	struct ufs_query *query = &hba->dev_cmd.query;
2751 	u16 len = be16_to_cpu(query->request.upiu_req.length);
2752 
2753 	/* Query request header */
2754 	ucd_req_ptr->header = (struct utp_upiu_header){
2755 		.transaction_code = UPIU_TRANSACTION_QUERY_REQ,
2756 		.flags = upiu_flags,
2757 		.lun = lrbp->lun,
2758 		.task_tag = lrbp->task_tag,
2759 		.query_function = query->request.query_func,
2760 		/* Data segment length only need for WRITE_DESC */
2761 		.data_segment_length =
2762 			query->request.upiu_req.opcode ==
2763 					UPIU_QUERY_OPCODE_WRITE_DESC ?
2764 				cpu_to_be16(len) :
2765 				0,
2766 	};
2767 
2768 	/* Copy the Query Request buffer as is */
2769 	memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2770 			QUERY_OSF_SIZE);
2771 
2772 	/* Copy the Descriptor */
2773 	if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2774 		memcpy(ucd_req_ptr + 1, query->descriptor, len);
2775 
2776 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2777 }
2778 
ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb * lrbp)2779 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2780 {
2781 	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2782 
2783 	memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2784 
2785 	ucd_req_ptr->header = (struct utp_upiu_header){
2786 		.transaction_code = UPIU_TRANSACTION_NOP_OUT,
2787 		.task_tag = lrbp->task_tag,
2788 	};
2789 
2790 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2791 }
2792 
2793 /**
2794  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2795  *			     for Device Management Purposes
2796  * @hba: per adapter instance
2797  * @lrbp: pointer to local reference block
2798  *
2799  * Return: 0 upon success; < 0 upon failure.
2800  */
ufshcd_compose_devman_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2801 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2802 				      struct ufshcd_lrb *lrbp)
2803 {
2804 	u8 upiu_flags;
2805 	int ret = 0;
2806 
2807 	ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0);
2808 
2809 	if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2810 		ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2811 	else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2812 		ufshcd_prepare_utp_nop_upiu(lrbp);
2813 	else
2814 		ret = -EINVAL;
2815 
2816 	return ret;
2817 }
2818 
2819 /**
2820  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2821  *			   for SCSI Purposes
2822  * @hba: per adapter instance
2823  * @lrbp: pointer to local reference block
2824  */
ufshcd_comp_scsi_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2825 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2826 {
2827 	struct request *rq = scsi_cmd_to_rq(lrbp->cmd);
2828 	unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq));
2829 	u8 upiu_flags;
2830 
2831 	ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0);
2832 	if (ioprio_class == IOPRIO_CLASS_RT)
2833 		upiu_flags |= UPIU_CMD_FLAGS_CP;
2834 	ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2835 }
2836 
__ufshcd_setup_cmd(struct ufshcd_lrb * lrbp,struct scsi_cmnd * cmd,u8 lun,int tag)2837 static void __ufshcd_setup_cmd(struct ufshcd_lrb *lrbp, struct scsi_cmnd *cmd, u8 lun, int tag)
2838 {
2839 	memset(lrbp->ucd_req_ptr, 0, sizeof(*lrbp->ucd_req_ptr));
2840 
2841 	lrbp->cmd = cmd;
2842 	lrbp->task_tag = tag;
2843 	lrbp->lun = lun;
2844 	ufshcd_prepare_lrbp_crypto(cmd ? scsi_cmd_to_rq(cmd) : NULL, lrbp);
2845 }
2846 
ufshcd_setup_scsi_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,struct scsi_cmnd * cmd,u8 lun,int tag)2847 static void ufshcd_setup_scsi_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
2848 				  struct scsi_cmnd *cmd, u8 lun, int tag)
2849 {
2850 	__ufshcd_setup_cmd(lrbp, cmd, lun, tag);
2851 	lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
2852 	lrbp->req_abort_skip = false;
2853 
2854 	ufshcd_comp_scsi_upiu(hba, lrbp);
2855 }
2856 
2857 /**
2858  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2859  * @upiu_wlun_id: UPIU W-LUN id
2860  *
2861  * Return: SCSI W-LUN id.
2862  */
ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)2863 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2864 {
2865 	return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2866 }
2867 
is_device_wlun(struct scsi_device * sdev)2868 static inline bool is_device_wlun(struct scsi_device *sdev)
2869 {
2870 	return sdev->lun ==
2871 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2872 }
2873 
2874 /*
2875  * Associate the UFS controller queue with the default and poll HCTX types.
2876  * Initialize the mq_map[] arrays.
2877  */
ufshcd_map_queues(struct Scsi_Host * shost)2878 static void ufshcd_map_queues(struct Scsi_Host *shost)
2879 {
2880 	struct ufs_hba *hba = shost_priv(shost);
2881 	int i, queue_offset = 0;
2882 
2883 	if (!is_mcq_supported(hba)) {
2884 		hba->nr_queues[HCTX_TYPE_DEFAULT] = 1;
2885 		hba->nr_queues[HCTX_TYPE_READ] = 0;
2886 		hba->nr_queues[HCTX_TYPE_POLL] = 1;
2887 		hba->nr_hw_queues = 1;
2888 	}
2889 
2890 	for (i = 0; i < shost->nr_maps; i++) {
2891 		struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2892 
2893 		map->nr_queues = hba->nr_queues[i];
2894 		if (!map->nr_queues)
2895 			continue;
2896 		map->queue_offset = queue_offset;
2897 		if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba))
2898 			map->queue_offset = 0;
2899 
2900 		blk_mq_map_queues(map);
2901 		queue_offset += map->nr_queues;
2902 	}
2903 }
2904 
ufshcd_init_lrb(struct ufs_hba * hba,struct ufshcd_lrb * lrb,int i)2905 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2906 {
2907 	struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
2908 		i * ufshcd_get_ucd_size(hba);
2909 	struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2910 	dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2911 		i * ufshcd_get_ucd_size(hba);
2912 	u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset);
2913 	u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset);
2914 
2915 	lrb->utr_descriptor_ptr = utrdlp + i;
2916 	lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2917 		i * sizeof(struct utp_transfer_req_desc);
2918 	lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
2919 	lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2920 	lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
2921 	lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2922 	lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
2923 	lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2924 }
2925 
2926 /**
2927  * ufshcd_queuecommand - main entry point for SCSI requests
2928  * @host: SCSI host pointer
2929  * @cmd: command from SCSI Midlayer
2930  *
2931  * Return: 0 for success, non-zero in case of failure.
2932  */
ufshcd_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)2933 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2934 {
2935 	struct ufs_hba *hba = shost_priv(host);
2936 	int tag = scsi_cmd_to_rq(cmd)->tag;
2937 	struct ufshcd_lrb *lrbp;
2938 	int err = 0;
2939 	struct ufs_hw_queue *hwq = NULL;
2940 
2941 	switch (hba->ufshcd_state) {
2942 	case UFSHCD_STATE_OPERATIONAL:
2943 		break;
2944 	case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2945 		/*
2946 		 * SCSI error handler can call ->queuecommand() while UFS error
2947 		 * handler is in progress. Error interrupts could change the
2948 		 * state from UFSHCD_STATE_RESET to
2949 		 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2950 		 * being issued in that case.
2951 		 */
2952 		if (ufshcd_eh_in_progress(hba)) {
2953 			err = SCSI_MLQUEUE_HOST_BUSY;
2954 			goto out;
2955 		}
2956 		break;
2957 	case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2958 		/*
2959 		 * pm_runtime_get_sync() is used at error handling preparation
2960 		 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2961 		 * PM ops, it can never be finished if we let SCSI layer keep
2962 		 * retrying it, which gets err handler stuck forever. Neither
2963 		 * can we let the scsi cmd pass through, because UFS is in bad
2964 		 * state, the scsi cmd may eventually time out, which will get
2965 		 * err handler blocked for too long. So, just fail the scsi cmd
2966 		 * sent from PM ops, err handler can recover PM error anyways.
2967 		 */
2968 		if (hba->pm_op_in_progress) {
2969 			hba->force_reset = true;
2970 			set_host_byte(cmd, DID_BAD_TARGET);
2971 			scsi_done(cmd);
2972 			goto out;
2973 		}
2974 		fallthrough;
2975 	case UFSHCD_STATE_RESET:
2976 		err = SCSI_MLQUEUE_HOST_BUSY;
2977 		goto out;
2978 	case UFSHCD_STATE_ERROR:
2979 		set_host_byte(cmd, DID_ERROR);
2980 		scsi_done(cmd);
2981 		goto out;
2982 	}
2983 
2984 	hba->req_abort_count = 0;
2985 
2986 	ufshcd_hold(hba);
2987 
2988 	lrbp = &hba->lrb[tag];
2989 
2990 	ufshcd_setup_scsi_cmd(hba, lrbp, cmd, ufshcd_scsi_to_upiu_lun(cmd->device->lun), tag);
2991 
2992 	err = ufshcd_map_sg(hba, lrbp);
2993 	if (err) {
2994 		ufshcd_release(hba);
2995 		goto out;
2996 	}
2997 
2998 	if (hba->mcq_enabled)
2999 		hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
3000 
3001 	ufshcd_send_command(hba, tag, hwq);
3002 
3003 out:
3004 	if (ufs_trigger_eh(hba)) {
3005 		unsigned long flags;
3006 
3007 		spin_lock_irqsave(hba->host->host_lock, flags);
3008 		ufshcd_schedule_eh_work(hba);
3009 		spin_unlock_irqrestore(hba->host->host_lock, flags);
3010 	}
3011 
3012 	return err;
3013 }
3014 
ufshcd_setup_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,enum dev_cmd_type cmd_type,u8 lun,int tag)3015 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
3016 			     enum dev_cmd_type cmd_type, u8 lun, int tag)
3017 {
3018 	__ufshcd_setup_cmd(lrbp, NULL, lun, tag);
3019 	lrbp->intr_cmd = true; /* No interrupt aggregation */
3020 	hba->dev_cmd.type = cmd_type;
3021 }
3022 
ufshcd_compose_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,enum dev_cmd_type cmd_type,int tag)3023 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
3024 		struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
3025 {
3026 	ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag);
3027 
3028 	return ufshcd_compose_devman_upiu(hba, lrbp);
3029 }
3030 
3031 /*
3032  * Check with the block layer if the command is inflight
3033  * @cmd: command to check.
3034  *
3035  * Return: true if command is inflight; false if not.
3036  */
ufshcd_cmd_inflight(struct scsi_cmnd * cmd)3037 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd)
3038 {
3039 	return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT;
3040 }
3041 
3042 /*
3043  * Clear the pending command in the controller and wait until
3044  * the controller confirms that the command has been cleared.
3045  * @hba: per adapter instance
3046  * @task_tag: The tag number of the command to be cleared.
3047  */
ufshcd_clear_cmd(struct ufs_hba * hba,u32 task_tag)3048 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag)
3049 {
3050 	u32 mask;
3051 	int err;
3052 
3053 	if (hba->mcq_enabled) {
3054 		/*
3055 		 * MCQ mode. Clean up the MCQ resources similar to
3056 		 * what the ufshcd_utrl_clear() does for SDB mode.
3057 		 */
3058 		err = ufshcd_mcq_sq_cleanup(hba, task_tag);
3059 		if (err) {
3060 			dev_err(hba->dev, "%s: failed tag=%d. err=%d\n",
3061 				__func__, task_tag, err);
3062 			return err;
3063 		}
3064 		return 0;
3065 	}
3066 
3067 	mask = 1U << task_tag;
3068 
3069 	/* clear outstanding transaction before retry */
3070 	ufshcd_utrl_clear(hba, mask);
3071 
3072 	/*
3073 	 * wait for h/w to clear corresponding bit in door-bell.
3074 	 * max. wait is 1 sec.
3075 	 */
3076 	return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
3077 					mask, ~mask, 1000, 1000);
3078 }
3079 
3080 /**
3081  * ufshcd_dev_cmd_completion() - handles device management command responses
3082  * @hba: per adapter instance
3083  * @lrbp: pointer to local reference block
3084  *
3085  * Return: 0 upon success; < 0 upon failure.
3086  */
3087 static int
ufshcd_dev_cmd_completion(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)3088 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3089 {
3090 	enum upiu_response_transaction resp;
3091 	int err = 0;
3092 
3093 	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
3094 	resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
3095 
3096 	switch (resp) {
3097 	case UPIU_TRANSACTION_NOP_IN:
3098 		if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
3099 			err = -EINVAL;
3100 			dev_err(hba->dev, "%s: unexpected response %x\n",
3101 					__func__, resp);
3102 		}
3103 		break;
3104 	case UPIU_TRANSACTION_QUERY_RSP: {
3105 		u8 response = lrbp->ucd_rsp_ptr->header.response;
3106 
3107 		if (response == 0) {
3108 			err = ufshcd_copy_query_response(hba, lrbp);
3109 		} else {
3110 			err = -EINVAL;
3111 			dev_err(hba->dev, "%s: unexpected response in Query RSP: %x\n",
3112 					__func__, response);
3113 		}
3114 		break;
3115 	}
3116 	case UPIU_TRANSACTION_REJECT_UPIU:
3117 		/* TODO: handle Reject UPIU Response */
3118 		err = -EPERM;
3119 		dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
3120 				__func__);
3121 		break;
3122 	case UPIU_TRANSACTION_RESPONSE:
3123 		if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
3124 			err = -EINVAL;
3125 			dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
3126 		}
3127 		break;
3128 	default:
3129 		err = -EINVAL;
3130 		dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
3131 				__func__, resp);
3132 		break;
3133 	}
3134 
3135 	return err;
3136 }
3137 
ufshcd_wait_for_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int max_timeout)3138 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
3139 		struct ufshcd_lrb *lrbp, int max_timeout)
3140 {
3141 	unsigned long time_left = msecs_to_jiffies(max_timeout);
3142 	unsigned long flags;
3143 	bool pending;
3144 	int err;
3145 
3146 retry:
3147 	time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
3148 						time_left);
3149 
3150 	if (likely(time_left)) {
3151 		/*
3152 		 * The completion handler called complete() and the caller of
3153 		 * this function still owns the @lrbp tag so the code below does
3154 		 * not trigger any race conditions.
3155 		 */
3156 		hba->dev_cmd.complete = NULL;
3157 		err = ufshcd_get_tr_ocs(lrbp, NULL);
3158 		if (!err)
3159 			err = ufshcd_dev_cmd_completion(hba, lrbp);
3160 	} else {
3161 		err = -ETIMEDOUT;
3162 		dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
3163 			__func__, lrbp->task_tag);
3164 
3165 		/* MCQ mode */
3166 		if (hba->mcq_enabled) {
3167 			/* successfully cleared the command, retry if needed */
3168 			if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0)
3169 				err = -EAGAIN;
3170 			hba->dev_cmd.complete = NULL;
3171 			return err;
3172 		}
3173 
3174 		/* SDB mode */
3175 		if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) {
3176 			/* successfully cleared the command, retry if needed */
3177 			err = -EAGAIN;
3178 			/*
3179 			 * Since clearing the command succeeded we also need to
3180 			 * clear the task tag bit from the outstanding_reqs
3181 			 * variable.
3182 			 */
3183 			spin_lock_irqsave(&hba->outstanding_lock, flags);
3184 			pending = test_bit(lrbp->task_tag,
3185 					   &hba->outstanding_reqs);
3186 			if (pending) {
3187 				hba->dev_cmd.complete = NULL;
3188 				__clear_bit(lrbp->task_tag,
3189 					    &hba->outstanding_reqs);
3190 			}
3191 			spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3192 
3193 			if (!pending) {
3194 				/*
3195 				 * The completion handler ran while we tried to
3196 				 * clear the command.
3197 				 */
3198 				time_left = 1;
3199 				goto retry;
3200 			}
3201 		} else {
3202 			dev_err(hba->dev, "%s: failed to clear tag %d\n",
3203 				__func__, lrbp->task_tag);
3204 
3205 			spin_lock_irqsave(&hba->outstanding_lock, flags);
3206 			pending = test_bit(lrbp->task_tag,
3207 					   &hba->outstanding_reqs);
3208 			if (pending)
3209 				hba->dev_cmd.complete = NULL;
3210 			spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3211 
3212 			if (!pending) {
3213 				/*
3214 				 * The completion handler ran while we tried to
3215 				 * clear the command.
3216 				 */
3217 				time_left = 1;
3218 				goto retry;
3219 			}
3220 		}
3221 	}
3222 
3223 	return err;
3224 }
3225 
ufshcd_dev_man_lock(struct ufs_hba * hba)3226 static void ufshcd_dev_man_lock(struct ufs_hba *hba)
3227 {
3228 	ufshcd_hold(hba);
3229 	mutex_lock(&hba->dev_cmd.lock);
3230 	down_read(&hba->clk_scaling_lock);
3231 }
3232 
ufshcd_dev_man_unlock(struct ufs_hba * hba)3233 static void ufshcd_dev_man_unlock(struct ufs_hba *hba)
3234 {
3235 	up_read(&hba->clk_scaling_lock);
3236 	mutex_unlock(&hba->dev_cmd.lock);
3237 	ufshcd_release(hba);
3238 }
3239 
ufshcd_issue_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,const u32 tag,int timeout)3240 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
3241 			  const u32 tag, int timeout)
3242 {
3243 	DECLARE_COMPLETION_ONSTACK(wait);
3244 	int err;
3245 
3246 	hba->dev_cmd.complete = &wait;
3247 
3248 	ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
3249 
3250 	ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
3251 	err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
3252 
3253 	ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3254 				    (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
3255 
3256 	return err;
3257 }
3258 
3259 /**
3260  * ufshcd_exec_dev_cmd - API for sending device management requests
3261  * @hba: UFS hba
3262  * @cmd_type: specifies the type (NOP, Query...)
3263  * @timeout: timeout in milliseconds
3264  *
3265  * Return: 0 upon success; < 0 upon failure.
3266  *
3267  * NOTE: Since there is only one available tag for device management commands,
3268  * it is expected you hold the hba->dev_cmd.lock mutex.
3269  */
ufshcd_exec_dev_cmd(struct ufs_hba * hba,enum dev_cmd_type cmd_type,int timeout)3270 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3271 		enum dev_cmd_type cmd_type, int timeout)
3272 {
3273 	const u32 tag = hba->reserved_slot;
3274 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
3275 	int err;
3276 
3277 	/* Protects use of hba->reserved_slot. */
3278 	lockdep_assert_held(&hba->dev_cmd.lock);
3279 
3280 	err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3281 	if (unlikely(err))
3282 		return err;
3283 
3284 	return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout);
3285 }
3286 
3287 /**
3288  * ufshcd_init_query() - init the query response and request parameters
3289  * @hba: per-adapter instance
3290  * @request: address of the request pointer to be initialized
3291  * @response: address of the response pointer to be initialized
3292  * @opcode: operation to perform
3293  * @idn: flag idn to access
3294  * @index: LU number to access
3295  * @selector: query/flag/descriptor further identification
3296  */
ufshcd_init_query(struct ufs_hba * hba,struct ufs_query_req ** request,struct ufs_query_res ** response,enum query_opcode opcode,u8 idn,u8 index,u8 selector)3297 static inline void ufshcd_init_query(struct ufs_hba *hba,
3298 		struct ufs_query_req **request, struct ufs_query_res **response,
3299 		enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3300 {
3301 	*request = &hba->dev_cmd.query.request;
3302 	*response = &hba->dev_cmd.query.response;
3303 	memset(*request, 0, sizeof(struct ufs_query_req));
3304 	memset(*response, 0, sizeof(struct ufs_query_res));
3305 	(*request)->upiu_req.opcode = opcode;
3306 	(*request)->upiu_req.idn = idn;
3307 	(*request)->upiu_req.index = index;
3308 	(*request)->upiu_req.selector = selector;
3309 }
3310 
ufshcd_query_flag_retry(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3311 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3312 	enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3313 {
3314 	int ret;
3315 	int retries;
3316 
3317 	for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3318 		ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3319 		if (ret)
3320 			dev_dbg(hba->dev,
3321 				"%s: failed with error %d, retries %d\n",
3322 				__func__, ret, retries);
3323 		else
3324 			break;
3325 	}
3326 
3327 	if (ret)
3328 		dev_err(hba->dev,
3329 			"%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
3330 			__func__, opcode, idn, ret, retries);
3331 	return ret;
3332 }
3333 
3334 /**
3335  * ufshcd_query_flag() - API function for sending flag query requests
3336  * @hba: per-adapter instance
3337  * @opcode: flag query to perform
3338  * @idn: flag idn to access
3339  * @index: flag index to access
3340  * @flag_res: the flag value after the query request completes
3341  *
3342  * Return: 0 for success, non-zero in case of failure.
3343  */
ufshcd_query_flag(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3344 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3345 			enum flag_idn idn, u8 index, bool *flag_res)
3346 {
3347 	struct ufs_query_req *request = NULL;
3348 	struct ufs_query_res *response = NULL;
3349 	int err, selector = 0;
3350 	int timeout = QUERY_REQ_TIMEOUT;
3351 
3352 	BUG_ON(!hba);
3353 
3354 	ufshcd_dev_man_lock(hba);
3355 
3356 	ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3357 			selector);
3358 
3359 	switch (opcode) {
3360 	case UPIU_QUERY_OPCODE_SET_FLAG:
3361 	case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3362 	case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3363 		request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3364 		break;
3365 	case UPIU_QUERY_OPCODE_READ_FLAG:
3366 		request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3367 		if (!flag_res) {
3368 			/* No dummy reads */
3369 			dev_err(hba->dev, "%s: Invalid argument for read request\n",
3370 					__func__);
3371 			err = -EINVAL;
3372 			goto out_unlock;
3373 		}
3374 		break;
3375 	default:
3376 		dev_err(hba->dev,
3377 			"%s: Expected query flag opcode but got = %d\n",
3378 			__func__, opcode);
3379 		err = -EINVAL;
3380 		goto out_unlock;
3381 	}
3382 
3383 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3384 
3385 	if (err) {
3386 		dev_err(hba->dev,
3387 			"%s: Sending flag query for idn %d failed, err = %d\n",
3388 			__func__, idn, err);
3389 		goto out_unlock;
3390 	}
3391 
3392 	if (flag_res)
3393 		*flag_res = (be32_to_cpu(response->upiu_res.value) &
3394 				MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3395 
3396 out_unlock:
3397 	ufshcd_dev_man_unlock(hba);
3398 	return err;
3399 }
3400 
3401 /**
3402  * ufshcd_query_attr - API function for sending attribute requests
3403  * @hba: per-adapter instance
3404  * @opcode: attribute opcode
3405  * @idn: attribute idn to access
3406  * @index: index field
3407  * @selector: selector field
3408  * @attr_val: the attribute value after the query request completes
3409  *
3410  * Return: 0 for success, non-zero in case of failure.
3411 */
ufshcd_query_attr(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3412 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3413 		      enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3414 {
3415 	struct ufs_query_req *request = NULL;
3416 	struct ufs_query_res *response = NULL;
3417 	int err;
3418 
3419 	BUG_ON(!hba);
3420 
3421 	if (!attr_val) {
3422 		dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3423 				__func__, opcode);
3424 		return -EINVAL;
3425 	}
3426 
3427 	ufshcd_dev_man_lock(hba);
3428 
3429 	ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3430 			selector);
3431 
3432 	switch (opcode) {
3433 	case UPIU_QUERY_OPCODE_WRITE_ATTR:
3434 		request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3435 		request->upiu_req.value = cpu_to_be32(*attr_val);
3436 		break;
3437 	case UPIU_QUERY_OPCODE_READ_ATTR:
3438 		request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3439 		break;
3440 	default:
3441 		dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3442 				__func__, opcode);
3443 		err = -EINVAL;
3444 		goto out_unlock;
3445 	}
3446 
3447 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3448 
3449 	if (err) {
3450 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3451 				__func__, opcode, idn, index, err);
3452 		goto out_unlock;
3453 	}
3454 
3455 	*attr_val = be32_to_cpu(response->upiu_res.value);
3456 
3457 out_unlock:
3458 	ufshcd_dev_man_unlock(hba);
3459 	return err;
3460 }
3461 
3462 /**
3463  * ufshcd_query_attr_retry() - API function for sending query
3464  * attribute with retries
3465  * @hba: per-adapter instance
3466  * @opcode: attribute opcode
3467  * @idn: attribute idn to access
3468  * @index: index field
3469  * @selector: selector field
3470  * @attr_val: the attribute value after the query request
3471  * completes
3472  *
3473  * Return: 0 for success, non-zero in case of failure.
3474 */
ufshcd_query_attr_retry(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3475 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3476 	enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3477 	u32 *attr_val)
3478 {
3479 	int ret = 0;
3480 	u32 retries;
3481 
3482 	for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3483 		ret = ufshcd_query_attr(hba, opcode, idn, index,
3484 						selector, attr_val);
3485 		if (ret)
3486 			dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3487 				__func__, ret, retries);
3488 		else
3489 			break;
3490 	}
3491 
3492 	if (ret)
3493 		dev_err(hba->dev,
3494 			"%s: query attribute, idn %d, failed with error %d after %d retries\n",
3495 			__func__, idn, ret, QUERY_REQ_RETRIES);
3496 	return ret;
3497 }
3498 
__ufshcd_query_descriptor(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3499 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3500 			enum query_opcode opcode, enum desc_idn idn, u8 index,
3501 			u8 selector, u8 *desc_buf, int *buf_len)
3502 {
3503 	struct ufs_query_req *request = NULL;
3504 	struct ufs_query_res *response = NULL;
3505 	int err;
3506 
3507 	BUG_ON(!hba);
3508 
3509 	if (!desc_buf) {
3510 		dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3511 				__func__, opcode);
3512 		return -EINVAL;
3513 	}
3514 
3515 	if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3516 		dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3517 				__func__, *buf_len);
3518 		return -EINVAL;
3519 	}
3520 
3521 	ufshcd_dev_man_lock(hba);
3522 
3523 	ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3524 			selector);
3525 	hba->dev_cmd.query.descriptor = desc_buf;
3526 	request->upiu_req.length = cpu_to_be16(*buf_len);
3527 
3528 	switch (opcode) {
3529 	case UPIU_QUERY_OPCODE_WRITE_DESC:
3530 		request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3531 		break;
3532 	case UPIU_QUERY_OPCODE_READ_DESC:
3533 		request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3534 		break;
3535 	default:
3536 		dev_err(hba->dev,
3537 				"%s: Expected query descriptor opcode but got = 0x%.2x\n",
3538 				__func__, opcode);
3539 		err = -EINVAL;
3540 		goto out_unlock;
3541 	}
3542 
3543 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3544 
3545 	if (err) {
3546 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3547 				__func__, opcode, idn, index, err);
3548 		goto out_unlock;
3549 	}
3550 
3551 	*buf_len = be16_to_cpu(response->upiu_res.length);
3552 
3553 out_unlock:
3554 	hba->dev_cmd.query.descriptor = NULL;
3555 	ufshcd_dev_man_unlock(hba);
3556 	return err;
3557 }
3558 
3559 /**
3560  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3561  * @hba: per-adapter instance
3562  * @opcode: attribute opcode
3563  * @idn: attribute idn to access
3564  * @index: index field
3565  * @selector: selector field
3566  * @desc_buf: the buffer that contains the descriptor
3567  * @buf_len: length parameter passed to the device
3568  *
3569  * The buf_len parameter will contain, on return, the length parameter
3570  * received on the response.
3571  *
3572  * Return: 0 for success, non-zero in case of failure.
3573  */
ufshcd_query_descriptor_retry(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3574 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3575 				  enum query_opcode opcode,
3576 				  enum desc_idn idn, u8 index,
3577 				  u8 selector,
3578 				  u8 *desc_buf, int *buf_len)
3579 {
3580 	int err;
3581 	int retries;
3582 
3583 	for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3584 		err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3585 						selector, desc_buf, buf_len);
3586 		if (!err || err == -EINVAL)
3587 			break;
3588 	}
3589 
3590 	return err;
3591 }
3592 
3593 /**
3594  * ufshcd_read_desc_param - read the specified descriptor parameter
3595  * @hba: Pointer to adapter instance
3596  * @desc_id: descriptor idn value
3597  * @desc_index: descriptor index
3598  * @param_offset: offset of the parameter to read
3599  * @param_read_buf: pointer to buffer where parameter would be read
3600  * @param_size: sizeof(param_read_buf)
3601  *
3602  * Return: 0 in case of success, non-zero otherwise.
3603  */
ufshcd_read_desc_param(struct ufs_hba * hba,enum desc_idn desc_id,int desc_index,u8 param_offset,u8 * param_read_buf,u8 param_size)3604 int ufshcd_read_desc_param(struct ufs_hba *hba,
3605 			   enum desc_idn desc_id,
3606 			   int desc_index,
3607 			   u8 param_offset,
3608 			   u8 *param_read_buf,
3609 			   u8 param_size)
3610 {
3611 	int ret;
3612 	u8 *desc_buf;
3613 	int buff_len = QUERY_DESC_MAX_SIZE;
3614 	bool is_kmalloc = true;
3615 
3616 	/* Safety check */
3617 	if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3618 		return -EINVAL;
3619 
3620 	/* Check whether we need temp memory */
3621 	if (param_offset != 0 || param_size < buff_len) {
3622 		desc_buf = kzalloc(buff_len, GFP_KERNEL);
3623 		if (!desc_buf)
3624 			return -ENOMEM;
3625 	} else {
3626 		desc_buf = param_read_buf;
3627 		is_kmalloc = false;
3628 	}
3629 
3630 	/* Request for full descriptor */
3631 	ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3632 					    desc_id, desc_index, 0,
3633 					    desc_buf, &buff_len);
3634 	if (ret) {
3635 		dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3636 			__func__, desc_id, desc_index, param_offset, ret);
3637 		goto out;
3638 	}
3639 
3640 	/* Update descriptor length */
3641 	buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3642 
3643 	if (param_offset >= buff_len) {
3644 		dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3645 			__func__, param_offset, desc_id, buff_len);
3646 		ret = -EINVAL;
3647 		goto out;
3648 	}
3649 
3650 	/* Sanity check */
3651 	if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3652 		dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3653 			__func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3654 		ret = -EINVAL;
3655 		goto out;
3656 	}
3657 
3658 	if (is_kmalloc) {
3659 		/* Make sure we don't copy more data than available */
3660 		if (param_offset >= buff_len)
3661 			ret = -EINVAL;
3662 		else
3663 			memcpy(param_read_buf, &desc_buf[param_offset],
3664 			       min_t(u32, param_size, buff_len - param_offset));
3665 	}
3666 out:
3667 	if (is_kmalloc)
3668 		kfree(desc_buf);
3669 	return ret;
3670 }
3671 
3672 /**
3673  * struct uc_string_id - unicode string
3674  *
3675  * @len: size of this descriptor inclusive
3676  * @type: descriptor type
3677  * @uc: unicode string character
3678  */
3679 struct uc_string_id {
3680 	u8 len;
3681 	u8 type;
3682 	wchar_t uc[];
3683 } __packed;
3684 
3685 /* replace non-printable or non-ASCII characters with spaces */
ufshcd_remove_non_printable(u8 ch)3686 static inline char ufshcd_remove_non_printable(u8 ch)
3687 {
3688 	return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3689 }
3690 
3691 /**
3692  * ufshcd_read_string_desc - read string descriptor
3693  * @hba: pointer to adapter instance
3694  * @desc_index: descriptor index
3695  * @buf: pointer to buffer where descriptor would be read,
3696  *       the caller should free the memory.
3697  * @ascii: if true convert from unicode to ascii characters
3698  *         null terminated string.
3699  *
3700  * Return:
3701  * *      string size on success.
3702  * *      -ENOMEM: on allocation failure
3703  * *      -EINVAL: on a wrong parameter
3704  */
ufshcd_read_string_desc(struct ufs_hba * hba,u8 desc_index,u8 ** buf,bool ascii)3705 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3706 			    u8 **buf, bool ascii)
3707 {
3708 	struct uc_string_id *uc_str;
3709 	u8 *str;
3710 	int ret;
3711 
3712 	if (!buf)
3713 		return -EINVAL;
3714 
3715 	uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3716 	if (!uc_str)
3717 		return -ENOMEM;
3718 
3719 	ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3720 				     (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3721 	if (ret < 0) {
3722 		dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3723 			QUERY_REQ_RETRIES, ret);
3724 		str = NULL;
3725 		goto out;
3726 	}
3727 
3728 	if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3729 		dev_dbg(hba->dev, "String Desc is of zero length\n");
3730 		str = NULL;
3731 		ret = 0;
3732 		goto out;
3733 	}
3734 
3735 	if (ascii) {
3736 		ssize_t ascii_len;
3737 		int i;
3738 		/* remove header and divide by 2 to move from UTF16 to UTF8 */
3739 		ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3740 		str = kzalloc(ascii_len, GFP_KERNEL);
3741 		if (!str) {
3742 			ret = -ENOMEM;
3743 			goto out;
3744 		}
3745 
3746 		/*
3747 		 * the descriptor contains string in UTF16 format
3748 		 * we need to convert to utf-8 so it can be displayed
3749 		 */
3750 		ret = utf16s_to_utf8s(uc_str->uc,
3751 				      uc_str->len - QUERY_DESC_HDR_SIZE,
3752 				      UTF16_BIG_ENDIAN, str, ascii_len - 1);
3753 
3754 		/* replace non-printable or non-ASCII characters with spaces */
3755 		for (i = 0; i < ret; i++)
3756 			str[i] = ufshcd_remove_non_printable(str[i]);
3757 
3758 		str[ret++] = '\0';
3759 
3760 	} else {
3761 		str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3762 		if (!str) {
3763 			ret = -ENOMEM;
3764 			goto out;
3765 		}
3766 		ret = uc_str->len;
3767 	}
3768 out:
3769 	*buf = str;
3770 	kfree(uc_str);
3771 	return ret;
3772 }
3773 
3774 /**
3775  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3776  * @hba: Pointer to adapter instance
3777  * @lun: lun id
3778  * @param_offset: offset of the parameter to read
3779  * @param_read_buf: pointer to buffer where parameter would be read
3780  * @param_size: sizeof(param_read_buf)
3781  *
3782  * Return: 0 in case of success, non-zero otherwise.
3783  */
ufshcd_read_unit_desc_param(struct ufs_hba * hba,int lun,enum unit_desc_param param_offset,u8 * param_read_buf,u32 param_size)3784 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3785 					      int lun,
3786 					      enum unit_desc_param param_offset,
3787 					      u8 *param_read_buf,
3788 					      u32 param_size)
3789 {
3790 	/*
3791 	 * Unit descriptors are only available for general purpose LUs (LUN id
3792 	 * from 0 to 7) and RPMB Well known LU.
3793 	 */
3794 	if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
3795 		return -EOPNOTSUPP;
3796 
3797 	return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3798 				      param_offset, param_read_buf, param_size);
3799 }
3800 
ufshcd_get_ref_clk_gating_wait(struct ufs_hba * hba)3801 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3802 {
3803 	int err = 0;
3804 	u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3805 
3806 	if (hba->dev_info.wspecversion >= 0x300) {
3807 		err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3808 				QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3809 				&gating_wait);
3810 		if (err)
3811 			dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3812 					 err, gating_wait);
3813 
3814 		if (gating_wait == 0) {
3815 			gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3816 			dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3817 					 gating_wait);
3818 		}
3819 
3820 		hba->dev_info.clk_gating_wait_us = gating_wait;
3821 	}
3822 
3823 	return err;
3824 }
3825 
3826 /**
3827  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3828  * @hba: per adapter instance
3829  *
3830  * 1. Allocate DMA memory for Command Descriptor array
3831  *	Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3832  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3833  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3834  *	(UTMRDL)
3835  * 4. Allocate memory for local reference block(lrb).
3836  *
3837  * Return: 0 for success, non-zero in case of failure.
3838  */
ufshcd_memory_alloc(struct ufs_hba * hba)3839 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3840 {
3841 	size_t utmrdl_size, utrdl_size, ucdl_size;
3842 
3843 	/* Allocate memory for UTP command descriptors */
3844 	ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs;
3845 	hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3846 						  ucdl_size,
3847 						  &hba->ucdl_dma_addr,
3848 						  GFP_KERNEL);
3849 
3850 	/*
3851 	 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3852 	 */
3853 	if (!hba->ucdl_base_addr ||
3854 	    WARN_ON(hba->ucdl_dma_addr & (128 - 1))) {
3855 		dev_err(hba->dev,
3856 			"Command Descriptor Memory allocation failed\n");
3857 		goto out;
3858 	}
3859 
3860 	/*
3861 	 * Allocate memory for UTP Transfer descriptors
3862 	 * UFSHCI requires 1KB alignment of UTRD
3863 	 */
3864 	utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3865 	hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3866 						   utrdl_size,
3867 						   &hba->utrdl_dma_addr,
3868 						   GFP_KERNEL);
3869 	if (!hba->utrdl_base_addr ||
3870 	    WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) {
3871 		dev_err(hba->dev,
3872 			"Transfer Descriptor Memory allocation failed\n");
3873 		goto out;
3874 	}
3875 
3876 	/*
3877 	 * Skip utmrdl allocation; it may have been
3878 	 * allocated during first pass and not released during
3879 	 * MCQ memory allocation.
3880 	 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq()
3881 	 */
3882 	if (hba->utmrdl_base_addr)
3883 		goto skip_utmrdl;
3884 	/*
3885 	 * Allocate memory for UTP Task Management descriptors
3886 	 * UFSHCI requires 1KB alignment of UTMRD
3887 	 */
3888 	utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3889 	hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3890 						    utmrdl_size,
3891 						    &hba->utmrdl_dma_addr,
3892 						    GFP_KERNEL);
3893 	if (!hba->utmrdl_base_addr ||
3894 	    WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) {
3895 		dev_err(hba->dev,
3896 		"Task Management Descriptor Memory allocation failed\n");
3897 		goto out;
3898 	}
3899 
3900 skip_utmrdl:
3901 	/* Allocate memory for local reference block */
3902 	hba->lrb = devm_kcalloc(hba->dev,
3903 				hba->nutrs, sizeof(struct ufshcd_lrb),
3904 				GFP_KERNEL);
3905 	if (!hba->lrb) {
3906 		dev_err(hba->dev, "LRB Memory allocation failed\n");
3907 		goto out;
3908 	}
3909 	return 0;
3910 out:
3911 	return -ENOMEM;
3912 }
3913 
3914 /**
3915  * ufshcd_host_memory_configure - configure local reference block with
3916  *				memory offsets
3917  * @hba: per adapter instance
3918  *
3919  * Configure Host memory space
3920  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3921  * address.
3922  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3923  * and PRDT offset.
3924  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3925  * into local reference block.
3926  */
ufshcd_host_memory_configure(struct ufs_hba * hba)3927 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3928 {
3929 	struct utp_transfer_req_desc *utrdlp;
3930 	dma_addr_t cmd_desc_dma_addr;
3931 	dma_addr_t cmd_desc_element_addr;
3932 	u16 response_offset;
3933 	u16 prdt_offset;
3934 	int cmd_desc_size;
3935 	int i;
3936 
3937 	utrdlp = hba->utrdl_base_addr;
3938 
3939 	response_offset =
3940 		offsetof(struct utp_transfer_cmd_desc, response_upiu);
3941 	prdt_offset =
3942 		offsetof(struct utp_transfer_cmd_desc, prd_table);
3943 
3944 	cmd_desc_size = ufshcd_get_ucd_size(hba);
3945 	cmd_desc_dma_addr = hba->ucdl_dma_addr;
3946 
3947 	for (i = 0; i < hba->nutrs; i++) {
3948 		/* Configure UTRD with command descriptor base address */
3949 		cmd_desc_element_addr =
3950 				(cmd_desc_dma_addr + (cmd_desc_size * i));
3951 		utrdlp[i].command_desc_base_addr =
3952 				cpu_to_le64(cmd_desc_element_addr);
3953 
3954 		/* Response upiu and prdt offset should be in double words */
3955 		if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3956 			utrdlp[i].response_upiu_offset =
3957 				cpu_to_le16(response_offset);
3958 			utrdlp[i].prd_table_offset =
3959 				cpu_to_le16(prdt_offset);
3960 			utrdlp[i].response_upiu_length =
3961 				cpu_to_le16(ALIGNED_UPIU_SIZE);
3962 		} else {
3963 			utrdlp[i].response_upiu_offset =
3964 				cpu_to_le16(response_offset >> 2);
3965 			utrdlp[i].prd_table_offset =
3966 				cpu_to_le16(prdt_offset >> 2);
3967 			utrdlp[i].response_upiu_length =
3968 				cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3969 		}
3970 
3971 		ufshcd_init_lrb(hba, &hba->lrb[i], i);
3972 	}
3973 }
3974 
3975 /**
3976  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3977  * @hba: per adapter instance
3978  *
3979  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3980  * in order to initialize the Unipro link startup procedure.
3981  * Once the Unipro links are up, the device connected to the controller
3982  * is detected.
3983  *
3984  * Return: 0 on success, non-zero value on failure.
3985  */
ufshcd_dme_link_startup(struct ufs_hba * hba)3986 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3987 {
3988 	struct uic_command uic_cmd = {
3989 		.command = UIC_CMD_DME_LINK_STARTUP,
3990 	};
3991 	int ret;
3992 
3993 	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3994 	if (ret)
3995 		dev_dbg(hba->dev,
3996 			"dme-link-startup: error code %d\n", ret);
3997 	return ret;
3998 }
3999 /**
4000  * ufshcd_dme_reset - UIC command for DME_RESET
4001  * @hba: per adapter instance
4002  *
4003  * DME_RESET command is issued in order to reset UniPro stack.
4004  * This function now deals with cold reset.
4005  *
4006  * Return: 0 on success, non-zero value on failure.
4007  */
ufshcd_dme_reset(struct ufs_hba * hba)4008 static int ufshcd_dme_reset(struct ufs_hba *hba)
4009 {
4010 	struct uic_command uic_cmd = {
4011 		.command = UIC_CMD_DME_RESET,
4012 	};
4013 	int ret;
4014 
4015 	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4016 	if (ret)
4017 		dev_err(hba->dev,
4018 			"dme-reset: error code %d\n", ret);
4019 
4020 	return ret;
4021 }
4022 
ufshcd_dme_configure_adapt(struct ufs_hba * hba,int agreed_gear,int adapt_val)4023 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
4024 			       int agreed_gear,
4025 			       int adapt_val)
4026 {
4027 	int ret;
4028 
4029 	if (agreed_gear < UFS_HS_G4)
4030 		adapt_val = PA_NO_ADAPT;
4031 
4032 	ret = ufshcd_dme_set(hba,
4033 			     UIC_ARG_MIB(PA_TXHSADAPTTYPE),
4034 			     adapt_val);
4035 	return ret;
4036 }
4037 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
4038 
4039 /**
4040  * ufshcd_dme_enable - UIC command for DME_ENABLE
4041  * @hba: per adapter instance
4042  *
4043  * DME_ENABLE command is issued in order to enable UniPro stack.
4044  *
4045  * Return: 0 on success, non-zero value on failure.
4046  */
ufshcd_dme_enable(struct ufs_hba * hba)4047 static int ufshcd_dme_enable(struct ufs_hba *hba)
4048 {
4049 	struct uic_command uic_cmd = {
4050 		.command = UIC_CMD_DME_ENABLE,
4051 	};
4052 	int ret;
4053 
4054 	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4055 	if (ret)
4056 		dev_err(hba->dev,
4057 			"dme-enable: error code %d\n", ret);
4058 
4059 	return ret;
4060 }
4061 
ufshcd_add_delay_before_dme_cmd(struct ufs_hba * hba)4062 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
4063 {
4064 	#define MIN_DELAY_BEFORE_DME_CMDS_US	1000
4065 	unsigned long min_sleep_time_us;
4066 
4067 	if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
4068 		return;
4069 
4070 	/*
4071 	 * last_dme_cmd_tstamp will be 0 only for 1st call to
4072 	 * this function
4073 	 */
4074 	if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
4075 		min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
4076 	} else {
4077 		unsigned long delta =
4078 			(unsigned long) ktime_to_us(
4079 				ktime_sub(ktime_get(),
4080 				hba->last_dme_cmd_tstamp));
4081 
4082 		if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
4083 			min_sleep_time_us =
4084 				MIN_DELAY_BEFORE_DME_CMDS_US - delta;
4085 		else
4086 			min_sleep_time_us = 0; /* no more delay required */
4087 	}
4088 
4089 	if (min_sleep_time_us > 0) {
4090 		/* allow sleep for extra 50us if needed */
4091 		usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
4092 	}
4093 
4094 	/* update the last_dme_cmd_tstamp */
4095 	hba->last_dme_cmd_tstamp = ktime_get();
4096 }
4097 
4098 /**
4099  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
4100  * @hba: per adapter instance
4101  * @attr_sel: uic command argument1
4102  * @attr_set: attribute set type as uic command argument2
4103  * @mib_val: setting value as uic command argument3
4104  * @peer: indicate whether peer or local
4105  *
4106  * Return: 0 on success, non-zero value on failure.
4107  */
ufshcd_dme_set_attr(struct ufs_hba * hba,u32 attr_sel,u8 attr_set,u32 mib_val,u8 peer)4108 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
4109 			u8 attr_set, u32 mib_val, u8 peer)
4110 {
4111 	struct uic_command uic_cmd = {
4112 		.command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET,
4113 		.argument1 = attr_sel,
4114 		.argument2 = UIC_ARG_ATTR_TYPE(attr_set),
4115 		.argument3 = mib_val,
4116 	};
4117 	static const char *const action[] = {
4118 		"dme-set",
4119 		"dme-peer-set"
4120 	};
4121 	const char *set = action[!!peer];
4122 	int ret;
4123 	int retries = UFS_UIC_COMMAND_RETRIES;
4124 
4125 	do {
4126 		/* for peer attributes we retry upon failure */
4127 		ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4128 		if (ret)
4129 			dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
4130 				set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
4131 	} while (ret && peer && --retries);
4132 
4133 	if (ret)
4134 		dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
4135 			set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4136 			UFS_UIC_COMMAND_RETRIES - retries);
4137 
4138 	return ret;
4139 }
4140 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
4141 
4142 /**
4143  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
4144  * @hba: per adapter instance
4145  * @attr_sel: uic command argument1
4146  * @mib_val: the value of the attribute as returned by the UIC command
4147  * @peer: indicate whether peer or local
4148  *
4149  * Return: 0 on success, non-zero value on failure.
4150  */
ufshcd_dme_get_attr(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val,u8 peer)4151 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
4152 			u32 *mib_val, u8 peer)
4153 {
4154 	struct uic_command uic_cmd = {
4155 		.command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET,
4156 		.argument1 = attr_sel,
4157 	};
4158 	static const char *const action[] = {
4159 		"dme-get",
4160 		"dme-peer-get"
4161 	};
4162 	const char *get = action[!!peer];
4163 	int ret;
4164 	int retries = UFS_UIC_COMMAND_RETRIES;
4165 	struct ufs_pa_layer_attr orig_pwr_info;
4166 	struct ufs_pa_layer_attr temp_pwr_info;
4167 	bool pwr_mode_change = false;
4168 
4169 	if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
4170 		orig_pwr_info = hba->pwr_info;
4171 		temp_pwr_info = orig_pwr_info;
4172 
4173 		if (orig_pwr_info.pwr_tx == FAST_MODE ||
4174 		    orig_pwr_info.pwr_rx == FAST_MODE) {
4175 			temp_pwr_info.pwr_tx = FASTAUTO_MODE;
4176 			temp_pwr_info.pwr_rx = FASTAUTO_MODE;
4177 			pwr_mode_change = true;
4178 		} else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
4179 		    orig_pwr_info.pwr_rx == SLOW_MODE) {
4180 			temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
4181 			temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
4182 			pwr_mode_change = true;
4183 		}
4184 		if (pwr_mode_change) {
4185 			ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
4186 			if (ret)
4187 				goto out;
4188 		}
4189 	}
4190 
4191 	do {
4192 		/* for peer attributes we retry upon failure */
4193 		ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4194 		if (ret)
4195 			dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4196 				get, UIC_GET_ATTR_ID(attr_sel), ret);
4197 	} while (ret && peer && --retries);
4198 
4199 	if (ret)
4200 		dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4201 			get, UIC_GET_ATTR_ID(attr_sel),
4202 			UFS_UIC_COMMAND_RETRIES - retries);
4203 
4204 	if (mib_val && !ret)
4205 		*mib_val = uic_cmd.argument3;
4206 
4207 	if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4208 	    && pwr_mode_change)
4209 		ufshcd_change_power_mode(hba, &orig_pwr_info);
4210 out:
4211 	return ret;
4212 }
4213 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4214 
4215 /**
4216  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4217  * state) and waits for it to take effect.
4218  *
4219  * @hba: per adapter instance
4220  * @cmd: UIC command to execute
4221  *
4222  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4223  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4224  * and device UniPro link and hence it's final completion would be indicated by
4225  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4226  * addition to normal UIC command completion Status (UCCS). This function only
4227  * returns after the relevant status bits indicate the completion.
4228  *
4229  * Return: 0 on success, non-zero value on failure.
4230  */
ufshcd_uic_pwr_ctrl(struct ufs_hba * hba,struct uic_command * cmd)4231 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4232 {
4233 	DECLARE_COMPLETION_ONSTACK(uic_async_done);
4234 	unsigned long flags;
4235 	u8 status;
4236 	int ret;
4237 	bool reenable_intr = false;
4238 
4239 	mutex_lock(&hba->uic_cmd_mutex);
4240 	ufshcd_add_delay_before_dme_cmd(hba);
4241 
4242 	spin_lock_irqsave(hba->host->host_lock, flags);
4243 	if (ufshcd_is_link_broken(hba)) {
4244 		ret = -ENOLINK;
4245 		goto out_unlock;
4246 	}
4247 	hba->uic_async_done = &uic_async_done;
4248 	if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4249 		ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4250 		/*
4251 		 * Make sure UIC command completion interrupt is disabled before
4252 		 * issuing UIC command.
4253 		 */
4254 		ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
4255 		reenable_intr = true;
4256 	}
4257 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4258 	ret = __ufshcd_send_uic_cmd(hba, cmd);
4259 	if (ret) {
4260 		dev_err(hba->dev,
4261 			"pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4262 			cmd->command, cmd->argument3, ret);
4263 		goto out;
4264 	}
4265 
4266 	if (!wait_for_completion_timeout(hba->uic_async_done,
4267 					 msecs_to_jiffies(uic_cmd_timeout))) {
4268 		dev_err(hba->dev,
4269 			"pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4270 			cmd->command, cmd->argument3);
4271 
4272 		if (!cmd->cmd_active) {
4273 			dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4274 				__func__);
4275 			goto check_upmcrs;
4276 		}
4277 
4278 		ret = -ETIMEDOUT;
4279 		goto out;
4280 	}
4281 
4282 check_upmcrs:
4283 	status = ufshcd_get_upmcrs(hba);
4284 	if (status != PWR_LOCAL) {
4285 		dev_err(hba->dev,
4286 			"pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4287 			cmd->command, status);
4288 		ret = (status != PWR_OK) ? status : -1;
4289 	}
4290 out:
4291 	if (ret) {
4292 		ufshcd_print_host_state(hba);
4293 		ufshcd_print_pwr_info(hba);
4294 		ufshcd_print_evt_hist(hba);
4295 	}
4296 
4297 	spin_lock_irqsave(hba->host->host_lock, flags);
4298 	hba->active_uic_cmd = NULL;
4299 	hba->uic_async_done = NULL;
4300 	if (reenable_intr)
4301 		ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4302 	if (ret) {
4303 		ufshcd_set_link_broken(hba);
4304 		ufshcd_schedule_eh_work(hba);
4305 	}
4306 out_unlock:
4307 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4308 	mutex_unlock(&hba->uic_cmd_mutex);
4309 
4310 	return ret;
4311 }
4312 
4313 /**
4314  * ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result
4315  * @hba: per adapter instance
4316  * @uic_cmd: UIC command
4317  *
4318  * Return: 0 only if success.
4319  */
ufshcd_send_bsg_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)4320 int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
4321 {
4322 	int ret;
4323 
4324 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
4325 		return 0;
4326 
4327 	ufshcd_hold(hba);
4328 
4329 	if (uic_cmd->argument1 == UIC_ARG_MIB(PA_PWRMODE) &&
4330 	    uic_cmd->command == UIC_CMD_DME_SET) {
4331 		ret = ufshcd_uic_pwr_ctrl(hba, uic_cmd);
4332 		goto out;
4333 	}
4334 
4335 	mutex_lock(&hba->uic_cmd_mutex);
4336 	ufshcd_add_delay_before_dme_cmd(hba);
4337 
4338 	ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
4339 	if (!ret)
4340 		ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
4341 
4342 	mutex_unlock(&hba->uic_cmd_mutex);
4343 
4344 out:
4345 	ufshcd_release(hba);
4346 	return ret;
4347 }
4348 
4349 /**
4350  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4351  *				using DME_SET primitives.
4352  * @hba: per adapter instance
4353  * @mode: powr mode value
4354  *
4355  * Return: 0 on success, non-zero value on failure.
4356  */
ufshcd_uic_change_pwr_mode(struct ufs_hba * hba,u8 mode)4357 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4358 {
4359 	struct uic_command uic_cmd = {
4360 		.command = UIC_CMD_DME_SET,
4361 		.argument1 = UIC_ARG_MIB(PA_PWRMODE),
4362 		.argument3 = mode,
4363 	};
4364 	int ret;
4365 
4366 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4367 		ret = ufshcd_dme_set(hba,
4368 				UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4369 		if (ret) {
4370 			dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4371 						__func__, ret);
4372 			goto out;
4373 		}
4374 	}
4375 
4376 	ufshcd_hold(hba);
4377 	ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4378 	ufshcd_release(hba);
4379 
4380 out:
4381 	return ret;
4382 }
4383 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
4384 
ufshcd_link_recovery(struct ufs_hba * hba)4385 int ufshcd_link_recovery(struct ufs_hba *hba)
4386 {
4387 	int ret;
4388 	unsigned long flags;
4389 
4390 	spin_lock_irqsave(hba->host->host_lock, flags);
4391 	hba->ufshcd_state = UFSHCD_STATE_RESET;
4392 	ufshcd_set_eh_in_progress(hba);
4393 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4394 
4395 	/* Reset the attached device */
4396 	ufshcd_device_reset(hba);
4397 
4398 	ret = ufshcd_host_reset_and_restore(hba);
4399 
4400 	spin_lock_irqsave(hba->host->host_lock, flags);
4401 	if (ret)
4402 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
4403 	ufshcd_clear_eh_in_progress(hba);
4404 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4405 
4406 	if (ret)
4407 		dev_err(hba->dev, "%s: link recovery failed, err %d",
4408 			__func__, ret);
4409 
4410 	return ret;
4411 }
4412 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4413 
ufshcd_uic_hibern8_enter(struct ufs_hba * hba)4414 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4415 {
4416 	struct uic_command uic_cmd = {
4417 		.command = UIC_CMD_DME_HIBER_ENTER,
4418 	};
4419 	ktime_t start = ktime_get();
4420 	int ret;
4421 
4422 	ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4423 
4424 	ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4425 	trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4426 			     ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4427 
4428 	if (ret)
4429 		dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4430 			__func__, ret);
4431 	else
4432 		ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4433 								POST_CHANGE);
4434 
4435 	return ret;
4436 }
4437 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4438 
ufshcd_uic_hibern8_exit(struct ufs_hba * hba)4439 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4440 {
4441 	struct uic_command uic_cmd = {
4442 		.command = UIC_CMD_DME_HIBER_EXIT,
4443 	};
4444 	int ret;
4445 	ktime_t start = ktime_get();
4446 
4447 	ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4448 
4449 	ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4450 	trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4451 			     ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4452 
4453 	if (ret) {
4454 		dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4455 			__func__, ret);
4456 	} else {
4457 		ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4458 								POST_CHANGE);
4459 		hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
4460 		hba->ufs_stats.hibern8_exit_cnt++;
4461 	}
4462 
4463 	return ret;
4464 }
4465 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4466 
ufshcd_configure_auto_hibern8(struct ufs_hba * hba)4467 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba)
4468 {
4469 	if (!ufshcd_is_auto_hibern8_supported(hba))
4470 		return;
4471 
4472 	ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4473 }
4474 
ufshcd_auto_hibern8_update(struct ufs_hba * hba,u32 ahit)4475 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4476 {
4477 	const u32 cur_ahit = READ_ONCE(hba->ahit);
4478 
4479 	if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit)
4480 		return;
4481 
4482 	WRITE_ONCE(hba->ahit, ahit);
4483 	if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
4484 		ufshcd_rpm_get_sync(hba);
4485 		ufshcd_hold(hba);
4486 		ufshcd_configure_auto_hibern8(hba);
4487 		ufshcd_release(hba);
4488 		ufshcd_rpm_put_sync(hba);
4489 	}
4490 }
4491 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4492 
4493  /**
4494  * ufshcd_init_pwr_info - setting the POR (power on reset)
4495  * values in hba power info
4496  * @hba: per-adapter instance
4497  */
ufshcd_init_pwr_info(struct ufs_hba * hba)4498 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4499 {
4500 	hba->pwr_info.gear_rx = UFS_PWM_G1;
4501 	hba->pwr_info.gear_tx = UFS_PWM_G1;
4502 	hba->pwr_info.lane_rx = UFS_LANE_1;
4503 	hba->pwr_info.lane_tx = UFS_LANE_1;
4504 	hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4505 	hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4506 	hba->pwr_info.hs_rate = 0;
4507 }
4508 
4509 /**
4510  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4511  * @hba: per-adapter instance
4512  *
4513  * Return: 0 upon success; < 0 upon failure.
4514  */
ufshcd_get_max_pwr_mode(struct ufs_hba * hba)4515 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4516 {
4517 	struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4518 
4519 	if (hba->max_pwr_info.is_valid)
4520 		return 0;
4521 
4522 	if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4523 		pwr_info->pwr_tx = FASTAUTO_MODE;
4524 		pwr_info->pwr_rx = FASTAUTO_MODE;
4525 	} else {
4526 		pwr_info->pwr_tx = FAST_MODE;
4527 		pwr_info->pwr_rx = FAST_MODE;
4528 	}
4529 	pwr_info->hs_rate = PA_HS_MODE_B;
4530 
4531 	/* Get the connected lane count */
4532 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4533 			&pwr_info->lane_rx);
4534 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4535 			&pwr_info->lane_tx);
4536 
4537 	if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4538 		dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4539 				__func__,
4540 				pwr_info->lane_rx,
4541 				pwr_info->lane_tx);
4542 		return -EINVAL;
4543 	}
4544 
4545 	if (pwr_info->lane_rx != pwr_info->lane_tx) {
4546 		dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n",
4547 			__func__,
4548 				pwr_info->lane_rx,
4549 				pwr_info->lane_tx);
4550 		return -EINVAL;
4551 	}
4552 
4553 	/*
4554 	 * First, get the maximum gears of HS speed.
4555 	 * If a zero value, it means there is no HSGEAR capability.
4556 	 * Then, get the maximum gears of PWM speed.
4557 	 */
4558 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4559 	if (!pwr_info->gear_rx) {
4560 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4561 				&pwr_info->gear_rx);
4562 		if (!pwr_info->gear_rx) {
4563 			dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4564 				__func__, pwr_info->gear_rx);
4565 			return -EINVAL;
4566 		}
4567 		pwr_info->pwr_rx = SLOW_MODE;
4568 	}
4569 
4570 	ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4571 			&pwr_info->gear_tx);
4572 	if (!pwr_info->gear_tx) {
4573 		ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4574 				&pwr_info->gear_tx);
4575 		if (!pwr_info->gear_tx) {
4576 			dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4577 				__func__, pwr_info->gear_tx);
4578 			return -EINVAL;
4579 		}
4580 		pwr_info->pwr_tx = SLOW_MODE;
4581 	}
4582 
4583 	hba->max_pwr_info.is_valid = true;
4584 	return 0;
4585 }
4586 
ufshcd_change_power_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_mode)4587 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4588 			     struct ufs_pa_layer_attr *pwr_mode)
4589 {
4590 	int ret;
4591 
4592 	/* if already configured to the requested pwr_mode */
4593 	if (!hba->force_pmc &&
4594 	    pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4595 	    pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4596 	    pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4597 	    pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4598 	    pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4599 	    pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4600 	    pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4601 		dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4602 		return 0;
4603 	}
4604 
4605 	/*
4606 	 * Configure attributes for power mode change with below.
4607 	 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4608 	 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4609 	 * - PA_HSSERIES
4610 	 */
4611 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4612 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4613 			pwr_mode->lane_rx);
4614 	if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4615 			pwr_mode->pwr_rx == FAST_MODE)
4616 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
4617 	else
4618 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
4619 
4620 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4621 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4622 			pwr_mode->lane_tx);
4623 	if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4624 			pwr_mode->pwr_tx == FAST_MODE)
4625 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
4626 	else
4627 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
4628 
4629 	if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4630 	    pwr_mode->pwr_tx == FASTAUTO_MODE ||
4631 	    pwr_mode->pwr_rx == FAST_MODE ||
4632 	    pwr_mode->pwr_tx == FAST_MODE)
4633 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4634 						pwr_mode->hs_rate);
4635 
4636 	if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4637 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4638 				DL_FC0ProtectionTimeOutVal_Default);
4639 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4640 				DL_TC0ReplayTimeOutVal_Default);
4641 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4642 				DL_AFC0ReqTimeOutVal_Default);
4643 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4644 				DL_FC1ProtectionTimeOutVal_Default);
4645 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4646 				DL_TC1ReplayTimeOutVal_Default);
4647 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4648 				DL_AFC1ReqTimeOutVal_Default);
4649 
4650 		ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4651 				DL_FC0ProtectionTimeOutVal_Default);
4652 		ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4653 				DL_TC0ReplayTimeOutVal_Default);
4654 		ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4655 				DL_AFC0ReqTimeOutVal_Default);
4656 	}
4657 
4658 	ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4659 			| pwr_mode->pwr_tx);
4660 
4661 	if (ret) {
4662 		dev_err(hba->dev,
4663 			"%s: power mode change failed %d\n", __func__, ret);
4664 	} else {
4665 		memcpy(&hba->pwr_info, pwr_mode,
4666 			sizeof(struct ufs_pa_layer_attr));
4667 	}
4668 
4669 	return ret;
4670 }
4671 
4672 /**
4673  * ufshcd_config_pwr_mode - configure a new power mode
4674  * @hba: per-adapter instance
4675  * @desired_pwr_mode: desired power configuration
4676  *
4677  * Return: 0 upon success; < 0 upon failure.
4678  */
ufshcd_config_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * desired_pwr_mode)4679 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4680 		struct ufs_pa_layer_attr *desired_pwr_mode)
4681 {
4682 	struct ufs_pa_layer_attr final_params = { 0 };
4683 	int ret;
4684 
4685 	ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4686 					desired_pwr_mode, &final_params);
4687 
4688 	if (ret)
4689 		memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4690 
4691 	ret = ufshcd_change_power_mode(hba, &final_params);
4692 
4693 	if (!ret)
4694 		ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4695 					&final_params);
4696 
4697 	return ret;
4698 }
4699 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4700 
4701 /**
4702  * ufshcd_complete_dev_init() - checks device readiness
4703  * @hba: per-adapter instance
4704  *
4705  * Set fDeviceInit flag and poll until device toggles it.
4706  *
4707  * Return: 0 upon success; < 0 upon failure.
4708  */
ufshcd_complete_dev_init(struct ufs_hba * hba)4709 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4710 {
4711 	int err;
4712 	bool flag_res = true;
4713 	ktime_t timeout;
4714 
4715 	err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4716 		QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4717 	if (err) {
4718 		dev_err(hba->dev,
4719 			"%s: setting fDeviceInit flag failed with error %d\n",
4720 			__func__, err);
4721 		goto out;
4722 	}
4723 
4724 	/* Poll fDeviceInit flag to be cleared */
4725 	timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4726 	do {
4727 		err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4728 					QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4729 		if (!flag_res)
4730 			break;
4731 		usleep_range(500, 1000);
4732 	} while (ktime_before(ktime_get(), timeout));
4733 
4734 	if (err) {
4735 		dev_err(hba->dev,
4736 				"%s: reading fDeviceInit flag failed with error %d\n",
4737 				__func__, err);
4738 	} else if (flag_res) {
4739 		dev_err(hba->dev,
4740 				"%s: fDeviceInit was not cleared by the device\n",
4741 				__func__);
4742 		err = -EBUSY;
4743 	}
4744 out:
4745 	return err;
4746 }
4747 
4748 /**
4749  * ufshcd_make_hba_operational - Make UFS controller operational
4750  * @hba: per adapter instance
4751  *
4752  * To bring UFS host controller to operational state,
4753  * 1. Enable required interrupts
4754  * 2. Configure interrupt aggregation
4755  * 3. Program UTRL and UTMRL base address
4756  * 4. Configure run-stop-registers
4757  *
4758  * Return: 0 on success, non-zero value on failure.
4759  */
ufshcd_make_hba_operational(struct ufs_hba * hba)4760 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4761 {
4762 	int err = 0;
4763 	u32 reg;
4764 
4765 	/* Enable required interrupts */
4766 	ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4767 
4768 	/* Configure interrupt aggregation */
4769 	if (ufshcd_is_intr_aggr_allowed(hba))
4770 		ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4771 	else
4772 		ufshcd_disable_intr_aggr(hba);
4773 
4774 	/* Configure UTRL and UTMRL base address registers */
4775 	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4776 			REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4777 	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4778 			REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4779 	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4780 			REG_UTP_TASK_REQ_LIST_BASE_L);
4781 	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4782 			REG_UTP_TASK_REQ_LIST_BASE_H);
4783 
4784 	/*
4785 	 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4786 	 */
4787 	reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4788 	if (!(ufshcd_get_lists_status(reg))) {
4789 		ufshcd_enable_run_stop_reg(hba);
4790 	} else {
4791 		dev_err(hba->dev,
4792 			"Host controller not ready to process requests");
4793 		err = -EIO;
4794 	}
4795 
4796 	return err;
4797 }
4798 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4799 
4800 /**
4801  * ufshcd_hba_stop - Send controller to reset state
4802  * @hba: per adapter instance
4803  */
ufshcd_hba_stop(struct ufs_hba * hba)4804 void ufshcd_hba_stop(struct ufs_hba *hba)
4805 {
4806 	int err;
4807 
4808 	ufshcd_disable_irq(hba);
4809 	ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4810 	err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4811 					CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4812 					10, 1);
4813 	ufshcd_enable_irq(hba);
4814 	if (err)
4815 		dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4816 }
4817 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4818 
4819 /**
4820  * ufshcd_hba_execute_hce - initialize the controller
4821  * @hba: per adapter instance
4822  *
4823  * The controller resets itself and controller firmware initialization
4824  * sequence kicks off. When controller is ready it will set
4825  * the Host Controller Enable bit to 1.
4826  *
4827  * Return: 0 on success, non-zero value on failure.
4828  */
ufshcd_hba_execute_hce(struct ufs_hba * hba)4829 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4830 {
4831 	int retry;
4832 
4833 	for (retry = 3; retry > 0; retry--) {
4834 		if (ufshcd_is_hba_active(hba))
4835 			/* change controller state to "reset state" */
4836 			ufshcd_hba_stop(hba);
4837 
4838 		/* UniPro link is disabled at this point */
4839 		ufshcd_set_link_off(hba);
4840 
4841 		ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4842 
4843 		/* start controller initialization sequence */
4844 		ufshcd_hba_start(hba);
4845 
4846 		/*
4847 		 * To initialize a UFS host controller HCE bit must be set to 1.
4848 		 * During initialization the HCE bit value changes from 1->0->1.
4849 		 * When the host controller completes initialization sequence
4850 		 * it sets the value of HCE bit to 1. The same HCE bit is read back
4851 		 * to check if the controller has completed initialization sequence.
4852 		 * So without this delay the value HCE = 1, set in the previous
4853 		 * instruction might be read back.
4854 		 * This delay can be changed based on the controller.
4855 		 */
4856 		ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4857 
4858 		/* wait for the host controller to complete initialization */
4859 		if (!ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, CONTROLLER_ENABLE,
4860 					      CONTROLLER_ENABLE, 1000, 50))
4861 			break;
4862 
4863 		dev_err(hba->dev, "Enabling the controller failed\n");
4864 	}
4865 
4866 	if (!retry)
4867 		return -EIO;
4868 
4869 	/* enable UIC related interrupts */
4870 	ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4871 
4872 	ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4873 
4874 	return 0;
4875 }
4876 
ufshcd_hba_enable(struct ufs_hba * hba)4877 int ufshcd_hba_enable(struct ufs_hba *hba)
4878 {
4879 	int ret;
4880 
4881 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4882 		ufshcd_set_link_off(hba);
4883 		ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4884 
4885 		/* enable UIC related interrupts */
4886 		ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4887 		ret = ufshcd_dme_reset(hba);
4888 		if (ret) {
4889 			dev_err(hba->dev, "DME_RESET failed\n");
4890 			return ret;
4891 		}
4892 
4893 		ret = ufshcd_dme_enable(hba);
4894 		if (ret) {
4895 			dev_err(hba->dev, "Enabling DME failed\n");
4896 			return ret;
4897 		}
4898 
4899 		ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4900 	} else {
4901 		ret = ufshcd_hba_execute_hce(hba);
4902 	}
4903 
4904 	return ret;
4905 }
4906 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4907 
ufshcd_disable_tx_lcc(struct ufs_hba * hba,bool peer)4908 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4909 {
4910 	int tx_lanes = 0, i, err = 0;
4911 
4912 	if (!peer)
4913 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4914 			       &tx_lanes);
4915 	else
4916 		ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4917 				    &tx_lanes);
4918 	for (i = 0; i < tx_lanes; i++) {
4919 		if (!peer)
4920 			err = ufshcd_dme_set(hba,
4921 				UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4922 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4923 					0);
4924 		else
4925 			err = ufshcd_dme_peer_set(hba,
4926 				UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4927 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4928 					0);
4929 		if (err) {
4930 			dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4931 				__func__, peer, i, err);
4932 			break;
4933 		}
4934 	}
4935 
4936 	return err;
4937 }
4938 
ufshcd_disable_device_tx_lcc(struct ufs_hba * hba)4939 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4940 {
4941 	return ufshcd_disable_tx_lcc(hba, true);
4942 }
4943 
ufshcd_update_evt_hist(struct ufs_hba * hba,u32 id,u32 val)4944 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4945 {
4946 	struct ufs_event_hist *e;
4947 
4948 	if (id >= UFS_EVT_CNT)
4949 		return;
4950 
4951 	e = &hba->ufs_stats.event[id];
4952 	e->val[e->pos] = val;
4953 	e->tstamp[e->pos] = local_clock();
4954 	e->cnt += 1;
4955 	e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4956 
4957 	ufshcd_vops_event_notify(hba, id, &val);
4958 }
4959 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4960 
4961 /**
4962  * ufshcd_link_startup - Initialize unipro link startup
4963  * @hba: per adapter instance
4964  *
4965  * Return: 0 for success, non-zero in case of failure.
4966  */
ufshcd_link_startup(struct ufs_hba * hba)4967 static int ufshcd_link_startup(struct ufs_hba *hba)
4968 {
4969 	int ret;
4970 	int retries = DME_LINKSTARTUP_RETRIES;
4971 	bool link_startup_again = false;
4972 
4973 	/*
4974 	 * If UFS device isn't active then we will have to issue link startup
4975 	 * 2 times to make sure the device state move to active.
4976 	 */
4977 	if (!ufshcd_is_ufs_dev_active(hba))
4978 		link_startup_again = true;
4979 
4980 link_startup:
4981 	do {
4982 		ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4983 
4984 		ret = ufshcd_dme_link_startup(hba);
4985 
4986 		/* check if device is detected by inter-connect layer */
4987 		if (!ret && !ufshcd_is_device_present(hba)) {
4988 			ufshcd_update_evt_hist(hba,
4989 					       UFS_EVT_LINK_STARTUP_FAIL,
4990 					       0);
4991 			dev_err(hba->dev, "%s: Device not present\n", __func__);
4992 			ret = -ENXIO;
4993 			goto out;
4994 		}
4995 
4996 		/*
4997 		 * DME link lost indication is only received when link is up,
4998 		 * but we can't be sure if the link is up until link startup
4999 		 * succeeds. So reset the local Uni-Pro and try again.
5000 		 */
5001 		if (ret && retries && ufshcd_hba_enable(hba)) {
5002 			ufshcd_update_evt_hist(hba,
5003 					       UFS_EVT_LINK_STARTUP_FAIL,
5004 					       (u32)ret);
5005 			goto out;
5006 		}
5007 	} while (ret && retries--);
5008 
5009 	if (ret) {
5010 		/* failed to get the link up... retire */
5011 		ufshcd_update_evt_hist(hba,
5012 				       UFS_EVT_LINK_STARTUP_FAIL,
5013 				       (u32)ret);
5014 		goto out;
5015 	}
5016 
5017 	if (link_startup_again) {
5018 		link_startup_again = false;
5019 		retries = DME_LINKSTARTUP_RETRIES;
5020 		goto link_startup;
5021 	}
5022 
5023 	/* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
5024 	ufshcd_init_pwr_info(hba);
5025 	ufshcd_print_pwr_info(hba);
5026 
5027 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
5028 		ret = ufshcd_disable_device_tx_lcc(hba);
5029 		if (ret)
5030 			goto out;
5031 	}
5032 
5033 	/* Include any host controller configuration via UIC commands */
5034 	ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
5035 	if (ret)
5036 		goto out;
5037 
5038 	/* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
5039 	ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5040 	ret = ufshcd_make_hba_operational(hba);
5041 out:
5042 	if (ret) {
5043 		dev_err(hba->dev, "link startup failed %d\n", ret);
5044 		ufshcd_print_host_state(hba);
5045 		ufshcd_print_pwr_info(hba);
5046 		ufshcd_print_evt_hist(hba);
5047 	}
5048 	return ret;
5049 }
5050 
5051 /**
5052  * ufshcd_verify_dev_init() - Verify device initialization
5053  * @hba: per-adapter instance
5054  *
5055  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
5056  * device Transport Protocol (UTP) layer is ready after a reset.
5057  * If the UTP layer at the device side is not initialized, it may
5058  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
5059  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
5060  *
5061  * Return: 0 upon success; < 0 upon failure.
5062  */
ufshcd_verify_dev_init(struct ufs_hba * hba)5063 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
5064 {
5065 	int err = 0;
5066 	int retries;
5067 
5068 	ufshcd_dev_man_lock(hba);
5069 
5070 	for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
5071 		err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
5072 					  hba->nop_out_timeout);
5073 
5074 		if (!err || err == -ETIMEDOUT)
5075 			break;
5076 
5077 		dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
5078 	}
5079 
5080 	ufshcd_dev_man_unlock(hba);
5081 
5082 	if (err)
5083 		dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
5084 	return err;
5085 }
5086 
5087 /**
5088  * ufshcd_setup_links - associate link b/w device wlun and other luns
5089  * @sdev: pointer to SCSI device
5090  * @hba: pointer to ufs hba
5091  */
ufshcd_setup_links(struct ufs_hba * hba,struct scsi_device * sdev)5092 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
5093 {
5094 	struct device_link *link;
5095 
5096 	/*
5097 	 * Device wlun is the supplier & rest of the luns are consumers.
5098 	 * This ensures that device wlun suspends after all other luns.
5099 	 */
5100 	if (hba->ufs_device_wlun) {
5101 		link = device_link_add(&sdev->sdev_gendev,
5102 				       &hba->ufs_device_wlun->sdev_gendev,
5103 				       DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
5104 		if (!link) {
5105 			dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
5106 				dev_name(&hba->ufs_device_wlun->sdev_gendev));
5107 			return;
5108 		}
5109 		hba->luns_avail--;
5110 		/* Ignore REPORT_LUN wlun probing */
5111 		if (hba->luns_avail == 1) {
5112 			ufshcd_rpm_put(hba);
5113 			return;
5114 		}
5115 	} else {
5116 		/*
5117 		 * Device wlun is probed. The assumption is that WLUNs are
5118 		 * scanned before other LUNs.
5119 		 */
5120 		hba->luns_avail--;
5121 	}
5122 }
5123 
5124 /**
5125  * ufshcd_lu_init - Initialize the relevant parameters of the LU
5126  * @hba: per-adapter instance
5127  * @sdev: pointer to SCSI device
5128  */
ufshcd_lu_init(struct ufs_hba * hba,struct scsi_device * sdev)5129 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
5130 {
5131 	int len = QUERY_DESC_MAX_SIZE;
5132 	u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun);
5133 	u8 lun_qdepth = hba->nutrs;
5134 	u8 *desc_buf;
5135 	int ret;
5136 
5137 	desc_buf = kzalloc(len, GFP_KERNEL);
5138 	if (!desc_buf)
5139 		goto set_qdepth;
5140 
5141 	ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len);
5142 	if (ret < 0) {
5143 		if (ret == -EOPNOTSUPP)
5144 			/* If LU doesn't support unit descriptor, its queue depth is set to 1 */
5145 			lun_qdepth = 1;
5146 		kfree(desc_buf);
5147 		goto set_qdepth;
5148 	}
5149 
5150 	if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
5151 		/*
5152 		 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
5153 		 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
5154 		 */
5155 		lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
5156 	}
5157 	/*
5158 	 * According to UFS device specification, the write protection mode is only supported by
5159 	 * normal LU, not supported by WLUN.
5160 	 */
5161 	if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
5162 	    !hba->dev_info.is_lu_power_on_wp &&
5163 	    desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
5164 		hba->dev_info.is_lu_power_on_wp = true;
5165 
5166 	/* In case of RPMB LU, check if advanced RPMB mode is enabled */
5167 	if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN &&
5168 	    desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
5169 		hba->dev_info.b_advanced_rpmb_en = true;
5170 
5171 
5172 	kfree(desc_buf);
5173 set_qdepth:
5174 	/*
5175 	 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
5176 	 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
5177 	 */
5178 	dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
5179 	scsi_change_queue_depth(sdev, lun_qdepth);
5180 }
5181 
5182 /**
5183  * ufshcd_sdev_init - handle initial SCSI device configurations
5184  * @sdev: pointer to SCSI device
5185  *
5186  * Return: success.
5187  */
ufshcd_sdev_init(struct scsi_device * sdev)5188 static int ufshcd_sdev_init(struct scsi_device *sdev)
5189 {
5190 	struct ufs_hba *hba;
5191 
5192 	hba = shost_priv(sdev->host);
5193 
5194 	/* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
5195 	sdev->use_10_for_ms = 1;
5196 
5197 	/* DBD field should be set to 1 in mode sense(10) */
5198 	sdev->set_dbd_for_ms = 1;
5199 
5200 	/* allow SCSI layer to restart the device in case of errors */
5201 	sdev->allow_restart = 1;
5202 
5203 	/* REPORT SUPPORTED OPERATION CODES is not supported */
5204 	sdev->no_report_opcodes = 1;
5205 
5206 	/* WRITE_SAME command is not supported */
5207 	sdev->no_write_same = 1;
5208 
5209 	ufshcd_lu_init(hba, sdev);
5210 
5211 	ufshcd_setup_links(hba, sdev);
5212 
5213 	return 0;
5214 }
5215 
5216 /**
5217  * ufshcd_change_queue_depth - change queue depth
5218  * @sdev: pointer to SCSI device
5219  * @depth: required depth to set
5220  *
5221  * Change queue depth and make sure the max. limits are not crossed.
5222  *
5223  * Return: new queue depth.
5224  */
ufshcd_change_queue_depth(struct scsi_device * sdev,int depth)5225 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5226 {
5227 	return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5228 }
5229 
5230 /**
5231  * ufshcd_sdev_configure - adjust SCSI device configurations
5232  * @sdev: pointer to SCSI device
5233  * @lim: queue limits
5234  *
5235  * Return: 0 (success).
5236  */
ufshcd_sdev_configure(struct scsi_device * sdev,struct queue_limits * lim)5237 static int ufshcd_sdev_configure(struct scsi_device *sdev,
5238 				 struct queue_limits *lim)
5239 {
5240 	struct ufs_hba *hba = shost_priv(sdev->host);
5241 	struct request_queue *q = sdev->request_queue;
5242 
5243 	lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1;
5244 
5245 	/*
5246 	 * Block runtime-pm until all consumers are added.
5247 	 * Refer ufshcd_setup_links().
5248 	 */
5249 	if (is_device_wlun(sdev))
5250 		pm_runtime_get_noresume(&sdev->sdev_gendev);
5251 	else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5252 		sdev->rpm_autosuspend = 1;
5253 	/*
5254 	 * Do not print messages during runtime PM to avoid never-ending cycles
5255 	 * of messages written back to storage by user space causing runtime
5256 	 * resume, causing more messages and so on.
5257 	 */
5258 	sdev->silence_suspend = 1;
5259 
5260 	if (hba->vops && hba->vops->config_scsi_dev)
5261 		hba->vops->config_scsi_dev(sdev);
5262 
5263 	ufshcd_crypto_register(hba, q);
5264 
5265 	return 0;
5266 }
5267 
5268 /**
5269  * ufshcd_sdev_destroy - remove SCSI device configurations
5270  * @sdev: pointer to SCSI device
5271  */
ufshcd_sdev_destroy(struct scsi_device * sdev)5272 static void ufshcd_sdev_destroy(struct scsi_device *sdev)
5273 {
5274 	struct ufs_hba *hba;
5275 	unsigned long flags;
5276 
5277 	hba = shost_priv(sdev->host);
5278 
5279 	/* Drop the reference as it won't be needed anymore */
5280 	if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5281 		spin_lock_irqsave(hba->host->host_lock, flags);
5282 		hba->ufs_device_wlun = NULL;
5283 		spin_unlock_irqrestore(hba->host->host_lock, flags);
5284 	} else if (hba->ufs_device_wlun) {
5285 		struct device *supplier = NULL;
5286 
5287 		/* Ensure UFS Device WLUN exists and does not disappear */
5288 		spin_lock_irqsave(hba->host->host_lock, flags);
5289 		if (hba->ufs_device_wlun) {
5290 			supplier = &hba->ufs_device_wlun->sdev_gendev;
5291 			get_device(supplier);
5292 		}
5293 		spin_unlock_irqrestore(hba->host->host_lock, flags);
5294 
5295 		if (supplier) {
5296 			/*
5297 			 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5298 			 * device will not have been registered but can still
5299 			 * have a device link holding a reference to the device.
5300 			 */
5301 			device_link_remove(&sdev->sdev_gendev, supplier);
5302 			put_device(supplier);
5303 		}
5304 	}
5305 }
5306 
5307 /**
5308  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5309  * @lrbp: pointer to local reference block of completed command
5310  * @scsi_status: SCSI command status
5311  *
5312  * Return: value base on SCSI command status.
5313  */
5314 static inline int
ufshcd_scsi_cmd_status(struct ufshcd_lrb * lrbp,int scsi_status)5315 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5316 {
5317 	int result = 0;
5318 
5319 	switch (scsi_status) {
5320 	case SAM_STAT_CHECK_CONDITION:
5321 		ufshcd_copy_sense_data(lrbp);
5322 		fallthrough;
5323 	case SAM_STAT_GOOD:
5324 		result |= DID_OK << 16 | scsi_status;
5325 		break;
5326 	case SAM_STAT_TASK_SET_FULL:
5327 	case SAM_STAT_BUSY:
5328 	case SAM_STAT_TASK_ABORTED:
5329 		ufshcd_copy_sense_data(lrbp);
5330 		result |= scsi_status;
5331 		break;
5332 	default:
5333 		result |= DID_ERROR << 16;
5334 		break;
5335 	} /* end of switch */
5336 
5337 	return result;
5338 }
5339 
5340 /**
5341  * ufshcd_transfer_rsp_status - Get overall status of the response
5342  * @hba: per adapter instance
5343  * @lrbp: pointer to local reference block of completed command
5344  * @cqe: pointer to the completion queue entry
5345  *
5346  * Return: result of the command to notify SCSI midlayer.
5347  */
5348 static inline int
ufshcd_transfer_rsp_status(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,struct cq_entry * cqe)5349 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
5350 			   struct cq_entry *cqe)
5351 {
5352 	int result = 0;
5353 	int scsi_status;
5354 	enum utp_ocs ocs;
5355 	u8 upiu_flags;
5356 	u32 resid;
5357 
5358 	upiu_flags = lrbp->ucd_rsp_ptr->header.flags;
5359 	resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count);
5360 	/*
5361 	 * Test !overflow instead of underflow to support UFS devices that do
5362 	 * not set either flag.
5363 	 */
5364 	if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW))
5365 		scsi_set_resid(lrbp->cmd, resid);
5366 
5367 	/* overall command status of utrd */
5368 	ocs = ufshcd_get_tr_ocs(lrbp, cqe);
5369 
5370 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5371 		if (lrbp->ucd_rsp_ptr->header.response ||
5372 		    lrbp->ucd_rsp_ptr->header.status)
5373 			ocs = OCS_SUCCESS;
5374 	}
5375 
5376 	switch (ocs) {
5377 	case OCS_SUCCESS:
5378 		hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5379 		switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) {
5380 		case UPIU_TRANSACTION_RESPONSE:
5381 			/*
5382 			 * get the result based on SCSI status response
5383 			 * to notify the SCSI midlayer of the command status
5384 			 */
5385 			scsi_status = lrbp->ucd_rsp_ptr->header.status;
5386 			result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5387 
5388 			/*
5389 			 * Currently we are only supporting BKOPs exception
5390 			 * events hence we can ignore BKOPs exception event
5391 			 * during power management callbacks. BKOPs exception
5392 			 * event is not expected to be raised in runtime suspend
5393 			 * callback as it allows the urgent bkops.
5394 			 * During system suspend, we are anyway forcefully
5395 			 * disabling the bkops and if urgent bkops is needed
5396 			 * it will be enabled on system resume. Long term
5397 			 * solution could be to abort the system suspend if
5398 			 * UFS device needs urgent BKOPs.
5399 			 */
5400 			if (!hba->pm_op_in_progress &&
5401 			    !ufshcd_eh_in_progress(hba) &&
5402 			    ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5403 				/* Flushed in suspend */
5404 				schedule_work(&hba->eeh_work);
5405 			break;
5406 		case UPIU_TRANSACTION_REJECT_UPIU:
5407 			/* TODO: handle Reject UPIU Response */
5408 			result = DID_ERROR << 16;
5409 			dev_err(hba->dev,
5410 				"Reject UPIU not fully implemented\n");
5411 			break;
5412 		default:
5413 			dev_err(hba->dev,
5414 				"Unexpected request response code = %x\n",
5415 				result);
5416 			result = DID_ERROR << 16;
5417 			break;
5418 		}
5419 		break;
5420 	case OCS_ABORTED:
5421 	case OCS_INVALID_COMMAND_STATUS:
5422 		result |= DID_REQUEUE << 16;
5423 		dev_warn(hba->dev,
5424 				"OCS %s from controller for tag %d\n",
5425 				(ocs == OCS_ABORTED ? "aborted" : "invalid"),
5426 				lrbp->task_tag);
5427 		break;
5428 	case OCS_INVALID_CMD_TABLE_ATTR:
5429 	case OCS_INVALID_PRDT_ATTR:
5430 	case OCS_MISMATCH_DATA_BUF_SIZE:
5431 	case OCS_MISMATCH_RESP_UPIU_SIZE:
5432 	case OCS_PEER_COMM_FAILURE:
5433 	case OCS_FATAL_ERROR:
5434 	case OCS_DEVICE_FATAL_ERROR:
5435 	case OCS_INVALID_CRYPTO_CONFIG:
5436 	case OCS_GENERAL_CRYPTO_ERROR:
5437 	default:
5438 		result |= DID_ERROR << 16;
5439 		dev_err(hba->dev,
5440 				"OCS error from controller = %x for tag %d\n",
5441 				ocs, lrbp->task_tag);
5442 		ufshcd_print_evt_hist(hba);
5443 		ufshcd_print_host_state(hba);
5444 		break;
5445 	} /* end of switch */
5446 
5447 	if ((host_byte(result) != DID_OK) &&
5448 	    (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5449 		ufshcd_print_tr(hba, lrbp->task_tag, true);
5450 	return result;
5451 }
5452 
ufshcd_is_auto_hibern8_error(struct ufs_hba * hba,u32 intr_mask)5453 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5454 					 u32 intr_mask)
5455 {
5456 	if (!ufshcd_is_auto_hibern8_supported(hba) ||
5457 	    !ufshcd_is_auto_hibern8_enabled(hba))
5458 		return false;
5459 
5460 	if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5461 		return false;
5462 
5463 	if (hba->active_uic_cmd &&
5464 	    (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5465 	    hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5466 		return false;
5467 
5468 	return true;
5469 }
5470 
5471 /**
5472  * ufshcd_uic_cmd_compl - handle completion of uic command
5473  * @hba: per adapter instance
5474  * @intr_status: interrupt status generated by the controller
5475  *
5476  * Return:
5477  *  IRQ_HANDLED - If interrupt is valid
5478  *  IRQ_NONE    - If invalid interrupt
5479  */
ufshcd_uic_cmd_compl(struct ufs_hba * hba,u32 intr_status)5480 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5481 {
5482 	irqreturn_t retval = IRQ_NONE;
5483 	struct uic_command *cmd;
5484 
5485 	spin_lock(hba->host->host_lock);
5486 	cmd = hba->active_uic_cmd;
5487 	if (WARN_ON_ONCE(!cmd))
5488 		goto unlock;
5489 
5490 	if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5491 		hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5492 
5493 	if (intr_status & UIC_COMMAND_COMPL) {
5494 		cmd->argument2 |= ufshcd_get_uic_cmd_result(hba);
5495 		cmd->argument3 = ufshcd_get_dme_attr_val(hba);
5496 		if (!hba->uic_async_done)
5497 			cmd->cmd_active = 0;
5498 		complete(&cmd->done);
5499 		retval = IRQ_HANDLED;
5500 	}
5501 
5502 	if (intr_status & UFSHCD_UIC_PWR_MASK && hba->uic_async_done) {
5503 		cmd->cmd_active = 0;
5504 		complete(hba->uic_async_done);
5505 		retval = IRQ_HANDLED;
5506 	}
5507 
5508 	if (retval == IRQ_HANDLED)
5509 		ufshcd_add_uic_command_trace(hba, cmd, UFS_CMD_COMP);
5510 
5511 unlock:
5512 	spin_unlock(hba->host->host_lock);
5513 
5514 	return retval;
5515 }
5516 
5517 /* Release the resources allocated for processing a SCSI command. */
ufshcd_release_scsi_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)5518 void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5519 			     struct ufshcd_lrb *lrbp)
5520 {
5521 	struct scsi_cmnd *cmd = lrbp->cmd;
5522 
5523 	scsi_dma_unmap(cmd);
5524 	ufshcd_crypto_clear_prdt(hba, lrbp);
5525 	ufshcd_release(hba);
5526 	ufshcd_clk_scaling_update_busy(hba);
5527 }
5528 
5529 /**
5530  * ufshcd_compl_one_cqe - handle a completion queue entry
5531  * @hba: per adapter instance
5532  * @task_tag: the task tag of the request to be completed
5533  * @cqe: pointer to the completion queue entry
5534  */
ufshcd_compl_one_cqe(struct ufs_hba * hba,int task_tag,struct cq_entry * cqe)5535 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag,
5536 			  struct cq_entry *cqe)
5537 {
5538 	struct ufshcd_lrb *lrbp;
5539 	struct scsi_cmnd *cmd;
5540 	enum utp_ocs ocs;
5541 
5542 	lrbp = &hba->lrb[task_tag];
5543 	lrbp->compl_time_stamp = ktime_get();
5544 	lrbp->compl_time_stamp_local_clock = local_clock();
5545 	cmd = lrbp->cmd;
5546 	if (cmd) {
5547 		if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5548 			ufshcd_update_monitor(hba, lrbp);
5549 		ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP);
5550 		cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe);
5551 		ufshcd_release_scsi_cmd(hba, lrbp);
5552 		/* Do not touch lrbp after scsi done */
5553 		scsi_done(cmd);
5554 	} else if (hba->dev_cmd.complete) {
5555 		if (cqe) {
5556 			ocs = le32_to_cpu(cqe->status) & MASK_OCS;
5557 			lrbp->utr_descriptor_ptr->header.ocs = ocs;
5558 		}
5559 		complete(hba->dev_cmd.complete);
5560 	}
5561 }
5562 
5563 /**
5564  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5565  * @hba: per adapter instance
5566  * @completed_reqs: bitmask that indicates which requests to complete
5567  */
__ufshcd_transfer_req_compl(struct ufs_hba * hba,unsigned long completed_reqs)5568 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5569 					unsigned long completed_reqs)
5570 {
5571 	int tag;
5572 
5573 	for_each_set_bit(tag, &completed_reqs, hba->nutrs)
5574 		ufshcd_compl_one_cqe(hba, tag, NULL);
5575 }
5576 
5577 /* Any value that is not an existing queue number is fine for this constant. */
5578 enum {
5579 	UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5580 };
5581 
ufshcd_clear_polled(struct ufs_hba * hba,unsigned long * completed_reqs)5582 static void ufshcd_clear_polled(struct ufs_hba *hba,
5583 				unsigned long *completed_reqs)
5584 {
5585 	int tag;
5586 
5587 	for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5588 		struct scsi_cmnd *cmd = hba->lrb[tag].cmd;
5589 
5590 		if (!cmd)
5591 			continue;
5592 		if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED)
5593 			__clear_bit(tag, completed_reqs);
5594 	}
5595 }
5596 
5597 /*
5598  * Return: > 0 if one or more commands have been completed or 0 if no
5599  * requests have been completed.
5600  */
ufshcd_poll(struct Scsi_Host * shost,unsigned int queue_num)5601 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5602 {
5603 	struct ufs_hba *hba = shost_priv(shost);
5604 	unsigned long completed_reqs, flags;
5605 	u32 tr_doorbell;
5606 	struct ufs_hw_queue *hwq;
5607 
5608 	if (hba->mcq_enabled) {
5609 		hwq = &hba->uhq[queue_num];
5610 
5611 		return ufshcd_mcq_poll_cqe_lock(hba, hwq);
5612 	}
5613 
5614 	spin_lock_irqsave(&hba->outstanding_lock, flags);
5615 	tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5616 	completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5617 	WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5618 		  "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5619 		  hba->outstanding_reqs);
5620 	if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5621 		/* Do not complete polled requests from interrupt context. */
5622 		ufshcd_clear_polled(hba, &completed_reqs);
5623 	}
5624 	hba->outstanding_reqs &= ~completed_reqs;
5625 	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5626 
5627 	if (completed_reqs)
5628 		__ufshcd_transfer_req_compl(hba, completed_reqs);
5629 
5630 	return completed_reqs != 0;
5631 }
5632 
5633 /**
5634  * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is
5635  * invoked from the error handler context or ufshcd_host_reset_and_restore()
5636  * to complete the pending transfers and free the resources associated with
5637  * the scsi command.
5638  *
5639  * @hba: per adapter instance
5640  * @force_compl: This flag is set to true when invoked
5641  * from ufshcd_host_reset_and_restore() in which case it requires special
5642  * handling because the host controller has been reset by ufshcd_hba_stop().
5643  */
ufshcd_mcq_compl_pending_transfer(struct ufs_hba * hba,bool force_compl)5644 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba,
5645 					      bool force_compl)
5646 {
5647 	struct ufs_hw_queue *hwq;
5648 	struct ufshcd_lrb *lrbp;
5649 	struct scsi_cmnd *cmd;
5650 	unsigned long flags;
5651 	int tag;
5652 
5653 	for (tag = 0; tag < hba->nutrs; tag++) {
5654 		lrbp = &hba->lrb[tag];
5655 		cmd = lrbp->cmd;
5656 		if (!ufshcd_cmd_inflight(cmd) ||
5657 		    test_bit(SCMD_STATE_COMPLETE, &cmd->state))
5658 			continue;
5659 
5660 		hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
5661 
5662 		if (force_compl) {
5663 			ufshcd_mcq_compl_all_cqes_lock(hba, hwq);
5664 			/*
5665 			 * For those cmds of which the cqes are not present
5666 			 * in the cq, complete them explicitly.
5667 			 */
5668 			spin_lock_irqsave(&hwq->cq_lock, flags);
5669 			if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) {
5670 				set_host_byte(cmd, DID_REQUEUE);
5671 				ufshcd_release_scsi_cmd(hba, lrbp);
5672 				scsi_done(cmd);
5673 			}
5674 			spin_unlock_irqrestore(&hwq->cq_lock, flags);
5675 		} else {
5676 			ufshcd_mcq_poll_cqe_lock(hba, hwq);
5677 		}
5678 	}
5679 }
5680 
5681 /**
5682  * ufshcd_transfer_req_compl - handle SCSI and query command completion
5683  * @hba: per adapter instance
5684  *
5685  * Return:
5686  *  IRQ_HANDLED - If interrupt is valid
5687  *  IRQ_NONE    - If invalid interrupt
5688  */
ufshcd_transfer_req_compl(struct ufs_hba * hba)5689 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5690 {
5691 	/* Resetting interrupt aggregation counters first and reading the
5692 	 * DOOR_BELL afterward allows us to handle all the completed requests.
5693 	 * In order to prevent other interrupts starvation the DB is read once
5694 	 * after reset. The down side of this solution is the possibility of
5695 	 * false interrupt if device completes another request after resetting
5696 	 * aggregation and before reading the DB.
5697 	 */
5698 	if (ufshcd_is_intr_aggr_allowed(hba) &&
5699 	    !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5700 		ufshcd_reset_intr_aggr(hba);
5701 
5702 	if (ufs_fail_completion(hba))
5703 		return IRQ_HANDLED;
5704 
5705 	/*
5706 	 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5707 	 * do not want polling to trigger spurious interrupt complaints.
5708 	 */
5709 	ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
5710 
5711 	return IRQ_HANDLED;
5712 }
5713 
__ufshcd_write_ee_control(struct ufs_hba * hba,u32 ee_ctrl_mask)5714 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5715 {
5716 	return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5717 				       QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5718 				       &ee_ctrl_mask);
5719 }
5720 
ufshcd_write_ee_control(struct ufs_hba * hba)5721 int ufshcd_write_ee_control(struct ufs_hba *hba)
5722 {
5723 	int err;
5724 
5725 	mutex_lock(&hba->ee_ctrl_mutex);
5726 	err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5727 	mutex_unlock(&hba->ee_ctrl_mutex);
5728 	if (err)
5729 		dev_err(hba->dev, "%s: failed to write ee control %d\n",
5730 			__func__, err);
5731 	return err;
5732 }
5733 
ufshcd_update_ee_control(struct ufs_hba * hba,u16 * mask,const u16 * other_mask,u16 set,u16 clr)5734 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5735 			     const u16 *other_mask, u16 set, u16 clr)
5736 {
5737 	u16 new_mask, ee_ctrl_mask;
5738 	int err = 0;
5739 
5740 	mutex_lock(&hba->ee_ctrl_mutex);
5741 	new_mask = (*mask & ~clr) | set;
5742 	ee_ctrl_mask = new_mask | *other_mask;
5743 	if (ee_ctrl_mask != hba->ee_ctrl_mask)
5744 		err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5745 	/* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5746 	if (!err) {
5747 		hba->ee_ctrl_mask = ee_ctrl_mask;
5748 		*mask = new_mask;
5749 	}
5750 	mutex_unlock(&hba->ee_ctrl_mutex);
5751 	return err;
5752 }
5753 
5754 /**
5755  * ufshcd_disable_ee - disable exception event
5756  * @hba: per-adapter instance
5757  * @mask: exception event to disable
5758  *
5759  * Disables exception event in the device so that the EVENT_ALERT
5760  * bit is not set.
5761  *
5762  * Return: zero on success, non-zero error value on failure.
5763  */
ufshcd_disable_ee(struct ufs_hba * hba,u16 mask)5764 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5765 {
5766 	return ufshcd_update_ee_drv_mask(hba, 0, mask);
5767 }
5768 
5769 /**
5770  * ufshcd_enable_ee - enable exception event
5771  * @hba: per-adapter instance
5772  * @mask: exception event to enable
5773  *
5774  * Enable corresponding exception event in the device to allow
5775  * device to alert host in critical scenarios.
5776  *
5777  * Return: zero on success, non-zero error value on failure.
5778  */
ufshcd_enable_ee(struct ufs_hba * hba,u16 mask)5779 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5780 {
5781 	return ufshcd_update_ee_drv_mask(hba, mask, 0);
5782 }
5783 
5784 /**
5785  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5786  * @hba: per-adapter instance
5787  *
5788  * Allow device to manage background operations on its own. Enabling
5789  * this might lead to inconsistent latencies during normal data transfers
5790  * as the device is allowed to manage its own way of handling background
5791  * operations.
5792  *
5793  * Return: zero on success, non-zero on failure.
5794  */
ufshcd_enable_auto_bkops(struct ufs_hba * hba)5795 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5796 {
5797 	int err = 0;
5798 
5799 	if (hba->auto_bkops_enabled)
5800 		goto out;
5801 
5802 	err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5803 			QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5804 	if (err) {
5805 		dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5806 				__func__, err);
5807 		goto out;
5808 	}
5809 
5810 	hba->auto_bkops_enabled = true;
5811 	trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5812 
5813 	/* No need of URGENT_BKOPS exception from the device */
5814 	err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5815 	if (err)
5816 		dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5817 				__func__, err);
5818 out:
5819 	return err;
5820 }
5821 
5822 /**
5823  * ufshcd_disable_auto_bkops - block device in doing background operations
5824  * @hba: per-adapter instance
5825  *
5826  * Disabling background operations improves command response latency but
5827  * has drawback of device moving into critical state where the device is
5828  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5829  * host is idle so that BKOPS are managed effectively without any negative
5830  * impacts.
5831  *
5832  * Return: zero on success, non-zero on failure.
5833  */
ufshcd_disable_auto_bkops(struct ufs_hba * hba)5834 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5835 {
5836 	int err = 0;
5837 
5838 	if (!hba->auto_bkops_enabled)
5839 		goto out;
5840 
5841 	/*
5842 	 * If host assisted BKOPs is to be enabled, make sure
5843 	 * urgent bkops exception is allowed.
5844 	 */
5845 	err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5846 	if (err) {
5847 		dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5848 				__func__, err);
5849 		goto out;
5850 	}
5851 
5852 	err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5853 			QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5854 	if (err) {
5855 		dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5856 				__func__, err);
5857 		ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5858 		goto out;
5859 	}
5860 
5861 	hba->auto_bkops_enabled = false;
5862 	trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5863 	hba->is_urgent_bkops_lvl_checked = false;
5864 out:
5865 	return err;
5866 }
5867 
5868 /**
5869  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5870  * @hba: per adapter instance
5871  *
5872  * After a device reset the device may toggle the BKOPS_EN flag
5873  * to default value. The s/w tracking variables should be updated
5874  * as well. This function would change the auto-bkops state based on
5875  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5876  */
ufshcd_force_reset_auto_bkops(struct ufs_hba * hba)5877 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5878 {
5879 	if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5880 		hba->auto_bkops_enabled = false;
5881 		hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5882 		ufshcd_enable_auto_bkops(hba);
5883 	} else {
5884 		hba->auto_bkops_enabled = true;
5885 		hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5886 		ufshcd_disable_auto_bkops(hba);
5887 	}
5888 	hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5889 	hba->is_urgent_bkops_lvl_checked = false;
5890 }
5891 
ufshcd_get_bkops_status(struct ufs_hba * hba,u32 * status)5892 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5893 {
5894 	return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5895 			QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5896 }
5897 
5898 /**
5899  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5900  * @hba: per-adapter instance
5901  *
5902  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5903  * flag in the device to permit background operations if the device
5904  * bkops_status is greater than or equal to the "hba->urgent_bkops_lvl",
5905  * disable otherwise.
5906  *
5907  * Return: 0 for success, non-zero in case of failure.
5908  *
5909  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5910  * to know whether auto bkops is enabled or disabled after this function
5911  * returns control to it.
5912  */
ufshcd_bkops_ctrl(struct ufs_hba * hba)5913 static int ufshcd_bkops_ctrl(struct ufs_hba *hba)
5914 {
5915 	enum bkops_status status = hba->urgent_bkops_lvl;
5916 	u32 curr_status = 0;
5917 	int err;
5918 
5919 	err = ufshcd_get_bkops_status(hba, &curr_status);
5920 	if (err) {
5921 		dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5922 				__func__, err);
5923 		goto out;
5924 	} else if (curr_status > BKOPS_STATUS_MAX) {
5925 		dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5926 				__func__, curr_status);
5927 		err = -EINVAL;
5928 		goto out;
5929 	}
5930 
5931 	if (curr_status >= status)
5932 		err = ufshcd_enable_auto_bkops(hba);
5933 	else
5934 		err = ufshcd_disable_auto_bkops(hba);
5935 out:
5936 	return err;
5937 }
5938 
ufshcd_get_ee_status(struct ufs_hba * hba,u32 * status)5939 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5940 {
5941 	return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5942 			QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5943 }
5944 
ufshcd_bkops_exception_event_handler(struct ufs_hba * hba)5945 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5946 {
5947 	int err;
5948 	u32 curr_status = 0;
5949 
5950 	if (hba->is_urgent_bkops_lvl_checked)
5951 		goto enable_auto_bkops;
5952 
5953 	err = ufshcd_get_bkops_status(hba, &curr_status);
5954 	if (err) {
5955 		dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5956 				__func__, err);
5957 		goto out;
5958 	}
5959 
5960 	/*
5961 	 * We are seeing that some devices are raising the urgent bkops
5962 	 * exception events even when BKOPS status doesn't indicate performace
5963 	 * impacted or critical. Handle these device by determining their urgent
5964 	 * bkops status at runtime.
5965 	 */
5966 	if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5967 		dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5968 				__func__, curr_status);
5969 		/* update the current status as the urgent bkops level */
5970 		hba->urgent_bkops_lvl = curr_status;
5971 		hba->is_urgent_bkops_lvl_checked = true;
5972 	}
5973 
5974 enable_auto_bkops:
5975 	err = ufshcd_enable_auto_bkops(hba);
5976 out:
5977 	if (err < 0)
5978 		dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5979 				__func__, err);
5980 }
5981 
__ufshcd_wb_toggle(struct ufs_hba * hba,bool set,enum flag_idn idn)5982 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5983 {
5984 	u8 index;
5985 	enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5986 				   UPIU_QUERY_OPCODE_CLEAR_FLAG;
5987 
5988 	index = ufshcd_wb_get_query_index(hba);
5989 	return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5990 }
5991 
ufshcd_wb_toggle(struct ufs_hba * hba,bool enable)5992 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5993 {
5994 	int ret;
5995 
5996 	if (!ufshcd_is_wb_allowed(hba) ||
5997 	    hba->dev_info.wb_enabled == enable)
5998 		return 0;
5999 
6000 	ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
6001 	if (ret) {
6002 		dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
6003 			__func__, enable ? "enabling" : "disabling", ret);
6004 		return ret;
6005 	}
6006 
6007 	hba->dev_info.wb_enabled = enable;
6008 	dev_dbg(hba->dev, "%s: Write Booster %s\n",
6009 			__func__, enable ? "enabled" : "disabled");
6010 
6011 	return ret;
6012 }
6013 
ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba * hba,bool enable)6014 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
6015 						 bool enable)
6016 {
6017 	int ret;
6018 
6019 	ret = __ufshcd_wb_toggle(hba, enable,
6020 			QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
6021 	if (ret) {
6022 		dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
6023 			__func__, enable ? "enabling" : "disabling", ret);
6024 		return;
6025 	}
6026 	dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
6027 			__func__, enable ? "enabled" : "disabled");
6028 }
6029 
ufshcd_wb_toggle_buf_flush(struct ufs_hba * hba,bool enable)6030 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
6031 {
6032 	int ret;
6033 
6034 	if (!ufshcd_is_wb_allowed(hba) ||
6035 	    hba->dev_info.wb_buf_flush_enabled == enable)
6036 		return 0;
6037 
6038 	ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
6039 	if (ret) {
6040 		dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
6041 			__func__, enable ? "enabling" : "disabling", ret);
6042 		return ret;
6043 	}
6044 
6045 	hba->dev_info.wb_buf_flush_enabled = enable;
6046 	dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
6047 			__func__, enable ? "enabled" : "disabled");
6048 
6049 	return ret;
6050 }
6051 
ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba * hba,u32 avail_buf)6052 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
6053 						u32 avail_buf)
6054 {
6055 	u32 cur_buf;
6056 	int ret;
6057 	u8 index;
6058 
6059 	index = ufshcd_wb_get_query_index(hba);
6060 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6061 					      QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
6062 					      index, 0, &cur_buf);
6063 	if (ret) {
6064 		dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
6065 			__func__, ret);
6066 		return false;
6067 	}
6068 
6069 	if (!cur_buf) {
6070 		dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
6071 			 cur_buf);
6072 		return false;
6073 	}
6074 	/* Let it continue to flush when available buffer exceeds threshold */
6075 	return avail_buf < hba->vps->wb_flush_threshold;
6076 }
6077 
ufshcd_wb_force_disable(struct ufs_hba * hba)6078 static void ufshcd_wb_force_disable(struct ufs_hba *hba)
6079 {
6080 	if (ufshcd_is_wb_buf_flush_allowed(hba))
6081 		ufshcd_wb_toggle_buf_flush(hba, false);
6082 
6083 	ufshcd_wb_toggle_buf_flush_during_h8(hba, false);
6084 	ufshcd_wb_toggle(hba, false);
6085 	hba->caps &= ~UFSHCD_CAP_WB_EN;
6086 
6087 	dev_info(hba->dev, "%s: WB force disabled\n", __func__);
6088 }
6089 
ufshcd_is_wb_buf_lifetime_available(struct ufs_hba * hba)6090 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
6091 {
6092 	u32 lifetime;
6093 	int ret;
6094 	u8 index;
6095 
6096 	index = ufshcd_wb_get_query_index(hba);
6097 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6098 				      QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
6099 				      index, 0, &lifetime);
6100 	if (ret) {
6101 		dev_err(hba->dev,
6102 			"%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
6103 			__func__, ret);
6104 		return false;
6105 	}
6106 
6107 	if (lifetime == UFS_WB_EXCEED_LIFETIME) {
6108 		dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
6109 			__func__, lifetime);
6110 		return false;
6111 	}
6112 
6113 	dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
6114 		__func__, lifetime);
6115 
6116 	return true;
6117 }
6118 
ufshcd_wb_need_flush(struct ufs_hba * hba)6119 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
6120 {
6121 	int ret;
6122 	u32 avail_buf;
6123 	u8 index;
6124 
6125 	if (!ufshcd_is_wb_allowed(hba))
6126 		return false;
6127 
6128 	if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
6129 		ufshcd_wb_force_disable(hba);
6130 		return false;
6131 	}
6132 
6133 	/*
6134 	 * The ufs device needs the vcc to be ON to flush.
6135 	 * With user-space reduction enabled, it's enough to enable flush
6136 	 * by checking only the available buffer. The threshold
6137 	 * defined here is > 90% full.
6138 	 * With user-space preserved enabled, the current-buffer
6139 	 * should be checked too because the wb buffer size can reduce
6140 	 * when disk tends to be full. This info is provided by current
6141 	 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
6142 	 * keeping vcc on when current buffer is empty.
6143 	 */
6144 	index = ufshcd_wb_get_query_index(hba);
6145 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6146 				      QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
6147 				      index, 0, &avail_buf);
6148 	if (ret) {
6149 		dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
6150 			 __func__, ret);
6151 		return false;
6152 	}
6153 
6154 	if (!hba->dev_info.b_presrv_uspc_en)
6155 		return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
6156 
6157 	return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
6158 }
6159 
ufshcd_rpm_dev_flush_recheck_work(struct work_struct * work)6160 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
6161 {
6162 	struct ufs_hba *hba = container_of(to_delayed_work(work),
6163 					   struct ufs_hba,
6164 					   rpm_dev_flush_recheck_work);
6165 	/*
6166 	 * To prevent unnecessary VCC power drain after device finishes
6167 	 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
6168 	 * after a certain delay to recheck the threshold by next runtime
6169 	 * suspend.
6170 	 */
6171 	ufshcd_rpm_get_sync(hba);
6172 	ufshcd_rpm_put_sync(hba);
6173 }
6174 
6175 /**
6176  * ufshcd_exception_event_handler - handle exceptions raised by device
6177  * @work: pointer to work data
6178  *
6179  * Read bExceptionEventStatus attribute from the device and handle the
6180  * exception event accordingly.
6181  */
ufshcd_exception_event_handler(struct work_struct * work)6182 static void ufshcd_exception_event_handler(struct work_struct *work)
6183 {
6184 	struct ufs_hba *hba;
6185 	int err;
6186 	u32 status = 0;
6187 	hba = container_of(work, struct ufs_hba, eeh_work);
6188 
6189 	err = ufshcd_get_ee_status(hba, &status);
6190 	if (err) {
6191 		dev_err(hba->dev, "%s: failed to get exception status %d\n",
6192 				__func__, err);
6193 		return;
6194 	}
6195 
6196 	trace_ufshcd_exception_event(dev_name(hba->dev), status);
6197 
6198 	if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
6199 		ufshcd_bkops_exception_event_handler(hba);
6200 
6201 	if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
6202 		ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
6203 
6204 	ufs_debugfs_exception_event(hba, status);
6205 }
6206 
6207 /* Complete requests that have door-bell cleared */
ufshcd_complete_requests(struct ufs_hba * hba,bool force_compl)6208 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl)
6209 {
6210 	if (hba->mcq_enabled)
6211 		ufshcd_mcq_compl_pending_transfer(hba, force_compl);
6212 	else
6213 		ufshcd_transfer_req_compl(hba);
6214 
6215 	ufshcd_tmc_handler(hba);
6216 }
6217 
6218 /**
6219  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
6220  *				to recover from the DL NAC errors or not.
6221  * @hba: per-adapter instance
6222  *
6223  * Return: true if error handling is required, false otherwise.
6224  */
ufshcd_quirk_dl_nac_errors(struct ufs_hba * hba)6225 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
6226 {
6227 	unsigned long flags;
6228 	bool err_handling = true;
6229 
6230 	spin_lock_irqsave(hba->host->host_lock, flags);
6231 	/*
6232 	 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
6233 	 * device fatal error and/or DL NAC & REPLAY timeout errors.
6234 	 */
6235 	if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
6236 		goto out;
6237 
6238 	if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
6239 	    ((hba->saved_err & UIC_ERROR) &&
6240 	     (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
6241 		goto out;
6242 
6243 	if ((hba->saved_err & UIC_ERROR) &&
6244 	    (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
6245 		int err;
6246 		/*
6247 		 * wait for 50ms to see if we can get any other errors or not.
6248 		 */
6249 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6250 		msleep(50);
6251 		spin_lock_irqsave(hba->host->host_lock, flags);
6252 
6253 		/*
6254 		 * now check if we have got any other severe errors other than
6255 		 * DL NAC error?
6256 		 */
6257 		if ((hba->saved_err & INT_FATAL_ERRORS) ||
6258 		    ((hba->saved_err & UIC_ERROR) &&
6259 		    (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6260 			goto out;
6261 
6262 		/*
6263 		 * As DL NAC is the only error received so far, send out NOP
6264 		 * command to confirm if link is still active or not.
6265 		 *   - If we don't get any response then do error recovery.
6266 		 *   - If we get response then clear the DL NAC error bit.
6267 		 */
6268 
6269 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6270 		err = ufshcd_verify_dev_init(hba);
6271 		spin_lock_irqsave(hba->host->host_lock, flags);
6272 
6273 		if (err)
6274 			goto out;
6275 
6276 		/* Link seems to be alive hence ignore the DL NAC errors */
6277 		if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6278 			hba->saved_err &= ~UIC_ERROR;
6279 		/* clear NAC error */
6280 		hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6281 		if (!hba->saved_uic_err)
6282 			err_handling = false;
6283 	}
6284 out:
6285 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6286 	return err_handling;
6287 }
6288 
6289 /* host lock must be held before calling this func */
ufshcd_is_saved_err_fatal(struct ufs_hba * hba)6290 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6291 {
6292 	return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6293 	       (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6294 }
6295 
ufshcd_schedule_eh_work(struct ufs_hba * hba)6296 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6297 {
6298 	lockdep_assert_held(hba->host->host_lock);
6299 
6300 	/* handle fatal errors only when link is not in error state */
6301 	if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6302 		if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6303 		    ufshcd_is_saved_err_fatal(hba))
6304 			hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6305 		else
6306 			hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6307 		queue_work(hba->eh_wq, &hba->eh_work);
6308 	}
6309 }
6310 
ufshcd_force_error_recovery(struct ufs_hba * hba)6311 static void ufshcd_force_error_recovery(struct ufs_hba *hba)
6312 {
6313 	spin_lock_irq(hba->host->host_lock);
6314 	hba->force_reset = true;
6315 	ufshcd_schedule_eh_work(hba);
6316 	spin_unlock_irq(hba->host->host_lock);
6317 }
6318 
ufshcd_clk_scaling_allow(struct ufs_hba * hba,bool allow)6319 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6320 {
6321 	mutex_lock(&hba->wb_mutex);
6322 	down_write(&hba->clk_scaling_lock);
6323 	hba->clk_scaling.is_allowed = allow;
6324 	up_write(&hba->clk_scaling_lock);
6325 	mutex_unlock(&hba->wb_mutex);
6326 }
6327 
ufshcd_clk_scaling_suspend(struct ufs_hba * hba,bool suspend)6328 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6329 {
6330 	if (suspend) {
6331 		if (hba->clk_scaling.is_enabled)
6332 			ufshcd_suspend_clkscaling(hba);
6333 		ufshcd_clk_scaling_allow(hba, false);
6334 	} else {
6335 		ufshcd_clk_scaling_allow(hba, true);
6336 		if (hba->clk_scaling.is_enabled)
6337 			ufshcd_resume_clkscaling(hba);
6338 	}
6339 }
6340 
ufshcd_err_handling_prepare(struct ufs_hba * hba)6341 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6342 {
6343 	ufshcd_rpm_get_sync(hba);
6344 	if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
6345 	    hba->is_sys_suspended) {
6346 		enum ufs_pm_op pm_op;
6347 
6348 		/*
6349 		 * Don't assume anything of resume, if
6350 		 * resume fails, irq and clocks can be OFF, and powers
6351 		 * can be OFF or in LPM.
6352 		 */
6353 		ufshcd_setup_hba_vreg(hba, true);
6354 		ufshcd_enable_irq(hba);
6355 		ufshcd_setup_vreg(hba, true);
6356 		ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6357 		ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6358 		ufshcd_hold(hba);
6359 		if (!ufshcd_is_clkgating_allowed(hba))
6360 			ufshcd_setup_clocks(hba, true);
6361 		pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6362 		ufshcd_vops_resume(hba, pm_op);
6363 	} else {
6364 		ufshcd_hold(hba);
6365 		if (ufshcd_is_clkscaling_supported(hba) &&
6366 		    hba->clk_scaling.is_enabled)
6367 			ufshcd_suspend_clkscaling(hba);
6368 		ufshcd_clk_scaling_allow(hba, false);
6369 	}
6370 	/* Wait for ongoing ufshcd_queuecommand() calls to finish. */
6371 	blk_mq_quiesce_tagset(&hba->host->tag_set);
6372 	cancel_work_sync(&hba->eeh_work);
6373 }
6374 
ufshcd_err_handling_unprepare(struct ufs_hba * hba)6375 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6376 {
6377 	blk_mq_unquiesce_tagset(&hba->host->tag_set);
6378 	ufshcd_release(hba);
6379 	if (ufshcd_is_clkscaling_supported(hba))
6380 		ufshcd_clk_scaling_suspend(hba, false);
6381 	ufshcd_rpm_put(hba);
6382 }
6383 
ufshcd_err_handling_should_stop(struct ufs_hba * hba)6384 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6385 {
6386 	return (!hba->is_powered || hba->shutting_down ||
6387 		!hba->ufs_device_wlun ||
6388 		hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6389 		(!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6390 		   ufshcd_is_link_broken(hba))));
6391 }
6392 
6393 #ifdef CONFIG_PM
ufshcd_recover_pm_error(struct ufs_hba * hba)6394 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6395 {
6396 	struct Scsi_Host *shost = hba->host;
6397 	struct scsi_device *sdev;
6398 	struct request_queue *q;
6399 	int ret;
6400 
6401 	hba->is_sys_suspended = false;
6402 	/*
6403 	 * Set RPM status of wlun device to RPM_ACTIVE,
6404 	 * this also clears its runtime error.
6405 	 */
6406 	ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
6407 
6408 	/* hba device might have a runtime error otherwise */
6409 	if (ret)
6410 		ret = pm_runtime_set_active(hba->dev);
6411 	/*
6412 	 * If wlun device had runtime error, we also need to resume those
6413 	 * consumer scsi devices in case any of them has failed to be
6414 	 * resumed due to supplier runtime resume failure. This is to unblock
6415 	 * blk_queue_enter in case there are bios waiting inside it.
6416 	 */
6417 	if (!ret) {
6418 		shost_for_each_device(sdev, shost) {
6419 			q = sdev->request_queue;
6420 			if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6421 				       q->rpm_status == RPM_SUSPENDING))
6422 				pm_request_resume(q->dev);
6423 		}
6424 	}
6425 }
6426 #else
ufshcd_recover_pm_error(struct ufs_hba * hba)6427 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6428 {
6429 }
6430 #endif
6431 
ufshcd_is_pwr_mode_restore_needed(struct ufs_hba * hba)6432 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6433 {
6434 	struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6435 	u32 mode;
6436 
6437 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6438 
6439 	if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6440 		return true;
6441 
6442 	if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6443 		return true;
6444 
6445 	return false;
6446 }
6447 
ufshcd_abort_one(struct request * rq,void * priv)6448 static bool ufshcd_abort_one(struct request *rq, void *priv)
6449 {
6450 	int *ret = priv;
6451 	u32 tag = rq->tag;
6452 	struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq);
6453 	struct scsi_device *sdev = cmd->device;
6454 	struct Scsi_Host *shost = sdev->host;
6455 	struct ufs_hba *hba = shost_priv(shost);
6456 
6457 	*ret = ufshcd_try_to_abort_task(hba, tag);
6458 	dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6459 		hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1,
6460 		*ret ? "failed" : "succeeded");
6461 
6462 	return *ret == 0;
6463 }
6464 
6465 /**
6466  * ufshcd_abort_all - Abort all pending commands.
6467  * @hba: Host bus adapter pointer.
6468  *
6469  * Return: true if and only if the host controller needs to be reset.
6470  */
ufshcd_abort_all(struct ufs_hba * hba)6471 static bool ufshcd_abort_all(struct ufs_hba *hba)
6472 {
6473 	int tag, ret = 0;
6474 
6475 	blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret);
6476 	if (ret)
6477 		goto out;
6478 
6479 	/* Clear pending task management requests */
6480 	for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6481 		ret = ufshcd_clear_tm_cmd(hba, tag);
6482 		if (ret)
6483 			goto out;
6484 	}
6485 
6486 out:
6487 	/* Complete the requests that are cleared by s/w */
6488 	ufshcd_complete_requests(hba, false);
6489 
6490 	return ret != 0;
6491 }
6492 
6493 /**
6494  * ufshcd_err_handler - handle UFS errors that require s/w attention
6495  * @work: pointer to work structure
6496  */
ufshcd_err_handler(struct work_struct * work)6497 static void ufshcd_err_handler(struct work_struct *work)
6498 {
6499 	int retries = MAX_ERR_HANDLER_RETRIES;
6500 	struct ufs_hba *hba;
6501 	unsigned long flags;
6502 	bool needs_restore;
6503 	bool needs_reset;
6504 	int pmc_err;
6505 
6506 	hba = container_of(work, struct ufs_hba, eh_work);
6507 
6508 	dev_info(hba->dev,
6509 		 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6510 		 __func__, ufshcd_state_name[hba->ufshcd_state],
6511 		 hba->is_powered, hba->shutting_down, hba->saved_err,
6512 		 hba->saved_uic_err, hba->force_reset,
6513 		 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6514 
6515 	down(&hba->host_sem);
6516 	spin_lock_irqsave(hba->host->host_lock, flags);
6517 	if (ufshcd_err_handling_should_stop(hba)) {
6518 		if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6519 			hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6520 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6521 		up(&hba->host_sem);
6522 		return;
6523 	}
6524 	ufshcd_set_eh_in_progress(hba);
6525 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6526 	ufshcd_err_handling_prepare(hba);
6527 	/* Complete requests that have door-bell cleared by h/w */
6528 	ufshcd_complete_requests(hba, false);
6529 	spin_lock_irqsave(hba->host->host_lock, flags);
6530 again:
6531 	needs_restore = false;
6532 	needs_reset = false;
6533 
6534 	if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6535 		hba->ufshcd_state = UFSHCD_STATE_RESET;
6536 	/*
6537 	 * A full reset and restore might have happened after preparation
6538 	 * is finished, double check whether we should stop.
6539 	 */
6540 	if (ufshcd_err_handling_should_stop(hba))
6541 		goto skip_err_handling;
6542 
6543 	if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) &&
6544 	    !hba->force_reset) {
6545 		bool ret;
6546 
6547 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6548 		/* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6549 		ret = ufshcd_quirk_dl_nac_errors(hba);
6550 		spin_lock_irqsave(hba->host->host_lock, flags);
6551 		if (!ret && ufshcd_err_handling_should_stop(hba))
6552 			goto skip_err_handling;
6553 	}
6554 
6555 	if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6556 	    (hba->saved_uic_err &&
6557 	     (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6558 		bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6559 
6560 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6561 		ufshcd_print_host_state(hba);
6562 		ufshcd_print_pwr_info(hba);
6563 		ufshcd_print_evt_hist(hba);
6564 		ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6565 		ufshcd_print_trs_all(hba, pr_prdt);
6566 		spin_lock_irqsave(hba->host->host_lock, flags);
6567 	}
6568 
6569 	/*
6570 	 * if host reset is required then skip clearing the pending
6571 	 * transfers forcefully because they will get cleared during
6572 	 * host reset and restore
6573 	 */
6574 	if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6575 	    ufshcd_is_saved_err_fatal(hba) ||
6576 	    ((hba->saved_err & UIC_ERROR) &&
6577 	     (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6578 				    UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6579 		needs_reset = true;
6580 		goto do_reset;
6581 	}
6582 
6583 	/*
6584 	 * If LINERESET was caught, UFS might have been put to PWM mode,
6585 	 * check if power mode restore is needed.
6586 	 */
6587 	if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6588 		hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6589 		if (!hba->saved_uic_err)
6590 			hba->saved_err &= ~UIC_ERROR;
6591 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6592 		if (ufshcd_is_pwr_mode_restore_needed(hba))
6593 			needs_restore = true;
6594 		spin_lock_irqsave(hba->host->host_lock, flags);
6595 		if (!hba->saved_err && !needs_restore)
6596 			goto skip_err_handling;
6597 	}
6598 
6599 	hba->silence_err_logs = true;
6600 	/* release lock as clear command might sleep */
6601 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6602 
6603 	needs_reset = ufshcd_abort_all(hba);
6604 
6605 	spin_lock_irqsave(hba->host->host_lock, flags);
6606 	hba->silence_err_logs = false;
6607 	if (needs_reset)
6608 		goto do_reset;
6609 
6610 	/*
6611 	 * After all reqs and tasks are cleared from doorbell,
6612 	 * now it is safe to retore power mode.
6613 	 */
6614 	if (needs_restore) {
6615 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6616 		/*
6617 		 * Hold the scaling lock just in case dev cmds
6618 		 * are sent via bsg and/or sysfs.
6619 		 */
6620 		down_write(&hba->clk_scaling_lock);
6621 		hba->force_pmc = true;
6622 		pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6623 		if (pmc_err) {
6624 			needs_reset = true;
6625 			dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6626 					__func__, pmc_err);
6627 		}
6628 		hba->force_pmc = false;
6629 		ufshcd_print_pwr_info(hba);
6630 		up_write(&hba->clk_scaling_lock);
6631 		spin_lock_irqsave(hba->host->host_lock, flags);
6632 	}
6633 
6634 do_reset:
6635 	/* Fatal errors need reset */
6636 	if (needs_reset) {
6637 		int err;
6638 
6639 		hba->force_reset = false;
6640 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6641 		err = ufshcd_reset_and_restore(hba);
6642 		if (err)
6643 			dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6644 					__func__, err);
6645 		else
6646 			ufshcd_recover_pm_error(hba);
6647 		spin_lock_irqsave(hba->host->host_lock, flags);
6648 	}
6649 
6650 skip_err_handling:
6651 	if (!needs_reset) {
6652 		if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6653 			hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6654 		if (hba->saved_err || hba->saved_uic_err)
6655 			dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6656 			    __func__, hba->saved_err, hba->saved_uic_err);
6657 	}
6658 	/* Exit in an operational state or dead */
6659 	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6660 	    hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6661 		if (--retries)
6662 			goto again;
6663 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
6664 	}
6665 	ufshcd_clear_eh_in_progress(hba);
6666 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6667 	ufshcd_err_handling_unprepare(hba);
6668 	up(&hba->host_sem);
6669 
6670 	dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6671 		 ufshcd_state_name[hba->ufshcd_state]);
6672 }
6673 
6674 /**
6675  * ufshcd_update_uic_error - check and set fatal UIC error flags.
6676  * @hba: per-adapter instance
6677  *
6678  * Return:
6679  *  IRQ_HANDLED - If interrupt is valid
6680  *  IRQ_NONE    - If invalid interrupt
6681  */
ufshcd_update_uic_error(struct ufs_hba * hba)6682 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6683 {
6684 	u32 reg;
6685 	irqreturn_t retval = IRQ_NONE;
6686 
6687 	/* PHY layer error */
6688 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6689 	if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6690 	    (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6691 		ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6692 		/*
6693 		 * To know whether this error is fatal or not, DB timeout
6694 		 * must be checked but this error is handled separately.
6695 		 */
6696 		if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6697 			dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6698 					__func__);
6699 
6700 		/* Got a LINERESET indication. */
6701 		if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6702 			struct uic_command *cmd = NULL;
6703 
6704 			hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6705 			if (hba->uic_async_done && hba->active_uic_cmd)
6706 				cmd = hba->active_uic_cmd;
6707 			/*
6708 			 * Ignore the LINERESET during power mode change
6709 			 * operation via DME_SET command.
6710 			 */
6711 			if (cmd && (cmd->command == UIC_CMD_DME_SET))
6712 				hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6713 		}
6714 		retval |= IRQ_HANDLED;
6715 	}
6716 
6717 	/* PA_INIT_ERROR is fatal and needs UIC reset */
6718 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6719 	if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6720 	    (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6721 		ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6722 
6723 		if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6724 			hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6725 		else if (hba->dev_quirks &
6726 				UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6727 			if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6728 				hba->uic_error |=
6729 					UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6730 			else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6731 				hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6732 		}
6733 		retval |= IRQ_HANDLED;
6734 	}
6735 
6736 	/* UIC NL/TL/DME errors needs software retry */
6737 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6738 	if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6739 	    (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6740 		ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6741 		hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6742 		retval |= IRQ_HANDLED;
6743 	}
6744 
6745 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6746 	if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6747 	    (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6748 		ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6749 		hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6750 		retval |= IRQ_HANDLED;
6751 	}
6752 
6753 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6754 	if ((reg & UIC_DME_ERROR) &&
6755 	    (reg & UIC_DME_ERROR_CODE_MASK)) {
6756 		ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6757 		hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6758 		retval |= IRQ_HANDLED;
6759 	}
6760 
6761 	dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6762 			__func__, hba->uic_error);
6763 	return retval;
6764 }
6765 
6766 /**
6767  * ufshcd_check_errors - Check for errors that need s/w attention
6768  * @hba: per-adapter instance
6769  * @intr_status: interrupt status generated by the controller
6770  *
6771  * Return:
6772  *  IRQ_HANDLED - If interrupt is valid
6773  *  IRQ_NONE    - If invalid interrupt
6774  */
ufshcd_check_errors(struct ufs_hba * hba,u32 intr_status)6775 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6776 {
6777 	bool queue_eh_work = false;
6778 	irqreturn_t retval = IRQ_NONE;
6779 
6780 	spin_lock(hba->host->host_lock);
6781 	hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6782 
6783 	if (hba->errors & INT_FATAL_ERRORS) {
6784 		ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6785 				       hba->errors);
6786 		queue_eh_work = true;
6787 	}
6788 
6789 	if (hba->errors & UIC_ERROR) {
6790 		hba->uic_error = 0;
6791 		retval = ufshcd_update_uic_error(hba);
6792 		if (hba->uic_error)
6793 			queue_eh_work = true;
6794 	}
6795 
6796 	if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6797 		dev_err(hba->dev,
6798 			"%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6799 			__func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6800 			"Enter" : "Exit",
6801 			hba->errors, ufshcd_get_upmcrs(hba));
6802 		ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6803 				       hba->errors);
6804 		ufshcd_set_link_broken(hba);
6805 		queue_eh_work = true;
6806 	}
6807 
6808 	if (queue_eh_work) {
6809 		/*
6810 		 * update the transfer error masks to sticky bits, let's do this
6811 		 * irrespective of current ufshcd_state.
6812 		 */
6813 		hba->saved_err |= hba->errors;
6814 		hba->saved_uic_err |= hba->uic_error;
6815 
6816 		/* dump controller state before resetting */
6817 		if ((hba->saved_err &
6818 		     (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6819 		    (hba->saved_uic_err &&
6820 		     (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6821 			dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6822 					__func__, hba->saved_err,
6823 					hba->saved_uic_err);
6824 			ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6825 					 "host_regs: ");
6826 			ufshcd_print_pwr_info(hba);
6827 		}
6828 		ufshcd_schedule_eh_work(hba);
6829 		retval |= IRQ_HANDLED;
6830 	}
6831 	/*
6832 	 * if (!queue_eh_work) -
6833 	 * Other errors are either non-fatal where host recovers
6834 	 * itself without s/w intervention or errors that will be
6835 	 * handled by the SCSI core layer.
6836 	 */
6837 	hba->errors = 0;
6838 	hba->uic_error = 0;
6839 	spin_unlock(hba->host->host_lock);
6840 	return retval;
6841 }
6842 
6843 /**
6844  * ufshcd_tmc_handler - handle task management function completion
6845  * @hba: per adapter instance
6846  *
6847  * Return:
6848  *  IRQ_HANDLED - If interrupt is valid
6849  *  IRQ_NONE    - If invalid interrupt
6850  */
ufshcd_tmc_handler(struct ufs_hba * hba)6851 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6852 {
6853 	unsigned long flags, pending, issued;
6854 	irqreturn_t ret = IRQ_NONE;
6855 	int tag;
6856 
6857 	spin_lock_irqsave(hba->host->host_lock, flags);
6858 	pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6859 	issued = hba->outstanding_tasks & ~pending;
6860 	for_each_set_bit(tag, &issued, hba->nutmrs) {
6861 		struct request *req = hba->tmf_rqs[tag];
6862 		struct completion *c = req->end_io_data;
6863 
6864 		complete(c);
6865 		ret = IRQ_HANDLED;
6866 	}
6867 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6868 
6869 	return ret;
6870 }
6871 
6872 /**
6873  * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events
6874  * @hba: per adapter instance
6875  *
6876  * Return: IRQ_HANDLED if interrupt is handled.
6877  */
ufshcd_handle_mcq_cq_events(struct ufs_hba * hba)6878 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba)
6879 {
6880 	struct ufs_hw_queue *hwq;
6881 	unsigned long outstanding_cqs;
6882 	unsigned int nr_queues;
6883 	int i, ret;
6884 	u32 events;
6885 
6886 	ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs);
6887 	if (ret)
6888 		outstanding_cqs = (1U << hba->nr_hw_queues) - 1;
6889 
6890 	/* Exclude the poll queues */
6891 	nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
6892 	for_each_set_bit(i, &outstanding_cqs, nr_queues) {
6893 		hwq = &hba->uhq[i];
6894 
6895 		events = ufshcd_mcq_read_cqis(hba, i);
6896 		if (events)
6897 			ufshcd_mcq_write_cqis(hba, events, i);
6898 
6899 		if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
6900 			ufshcd_mcq_poll_cqe_lock(hba, hwq);
6901 	}
6902 
6903 	return IRQ_HANDLED;
6904 }
6905 
6906 /**
6907  * ufshcd_sl_intr - Interrupt service routine
6908  * @hba: per adapter instance
6909  * @intr_status: contains interrupts generated by the controller
6910  *
6911  * Return:
6912  *  IRQ_HANDLED - If interrupt is valid
6913  *  IRQ_NONE    - If invalid interrupt
6914  */
ufshcd_sl_intr(struct ufs_hba * hba,u32 intr_status)6915 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6916 {
6917 	irqreturn_t retval = IRQ_NONE;
6918 
6919 	if (intr_status & UFSHCD_UIC_MASK)
6920 		retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6921 
6922 	if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6923 		retval |= ufshcd_check_errors(hba, intr_status);
6924 
6925 	if (intr_status & UTP_TASK_REQ_COMPL)
6926 		retval |= ufshcd_tmc_handler(hba);
6927 
6928 	if (intr_status & UTP_TRANSFER_REQ_COMPL)
6929 		retval |= ufshcd_transfer_req_compl(hba);
6930 
6931 	if (intr_status & MCQ_CQ_EVENT_STATUS)
6932 		retval |= ufshcd_handle_mcq_cq_events(hba);
6933 
6934 	return retval;
6935 }
6936 
6937 /**
6938  * ufshcd_intr - Main interrupt service routine
6939  * @irq: irq number
6940  * @__hba: pointer to adapter instance
6941  *
6942  * Return:
6943  *  IRQ_HANDLED - If interrupt is valid
6944  *  IRQ_NONE    - If invalid interrupt
6945  */
ufshcd_intr(int irq,void * __hba)6946 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6947 {
6948 	u32 intr_status, enabled_intr_status = 0;
6949 	irqreturn_t retval = IRQ_NONE;
6950 	struct ufs_hba *hba = __hba;
6951 	int retries = hba->nutrs;
6952 
6953 	intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6954 	hba->ufs_stats.last_intr_status = intr_status;
6955 	hba->ufs_stats.last_intr_ts = local_clock();
6956 
6957 	/*
6958 	 * There could be max of hba->nutrs reqs in flight and in worst case
6959 	 * if the reqs get finished 1 by 1 after the interrupt status is
6960 	 * read, make sure we handle them by checking the interrupt status
6961 	 * again in a loop until we process all of the reqs before returning.
6962 	 */
6963 	while (intr_status && retries--) {
6964 		enabled_intr_status =
6965 			intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6966 		ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6967 		if (enabled_intr_status)
6968 			retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6969 
6970 		intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6971 	}
6972 
6973 	if (enabled_intr_status && retval == IRQ_NONE &&
6974 	    (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6975 	     hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6976 		dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6977 					__func__,
6978 					intr_status,
6979 					hba->ufs_stats.last_intr_status,
6980 					enabled_intr_status);
6981 		ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6982 	}
6983 
6984 	return retval;
6985 }
6986 
ufshcd_clear_tm_cmd(struct ufs_hba * hba,int tag)6987 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6988 {
6989 	int err = 0;
6990 	u32 mask = 1 << tag;
6991 
6992 	if (!test_bit(tag, &hba->outstanding_tasks))
6993 		goto out;
6994 
6995 	ufshcd_utmrl_clear(hba, tag);
6996 
6997 	/* poll for max. 1 sec to clear door bell register by h/w */
6998 	err = ufshcd_wait_for_register(hba,
6999 			REG_UTP_TASK_REQ_DOOR_BELL,
7000 			mask, 0, 1000, 1000);
7001 
7002 	dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
7003 		tag, err < 0 ? "failed" : "succeeded");
7004 
7005 out:
7006 	return err;
7007 }
7008 
__ufshcd_issue_tm_cmd(struct ufs_hba * hba,struct utp_task_req_desc * treq,u8 tm_function)7009 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
7010 		struct utp_task_req_desc *treq, u8 tm_function)
7011 {
7012 	struct request_queue *q = hba->tmf_queue;
7013 	struct Scsi_Host *host = hba->host;
7014 	DECLARE_COMPLETION_ONSTACK(wait);
7015 	struct request *req;
7016 	unsigned long flags;
7017 	int task_tag, err;
7018 
7019 	/*
7020 	 * blk_mq_alloc_request() is used here only to get a free tag.
7021 	 */
7022 	req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
7023 	if (IS_ERR(req))
7024 		return PTR_ERR(req);
7025 
7026 	req->end_io_data = &wait;
7027 	ufshcd_hold(hba);
7028 
7029 	spin_lock_irqsave(host->host_lock, flags);
7030 
7031 	task_tag = req->tag;
7032 	hba->tmf_rqs[req->tag] = req;
7033 	treq->upiu_req.req_header.task_tag = task_tag;
7034 
7035 	memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
7036 	ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
7037 
7038 	__set_bit(task_tag, &hba->outstanding_tasks);
7039 
7040 	spin_unlock_irqrestore(host->host_lock, flags);
7041 
7042 	/* send command to the controller */
7043 	ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
7044 
7045 	ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
7046 
7047 	/* wait until the task management command is completed */
7048 	err = wait_for_completion_io_timeout(&wait,
7049 			msecs_to_jiffies(TM_CMD_TIMEOUT));
7050 	if (!err) {
7051 		ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
7052 		dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
7053 				__func__, tm_function);
7054 		if (ufshcd_clear_tm_cmd(hba, task_tag))
7055 			dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
7056 					__func__, task_tag);
7057 		err = -ETIMEDOUT;
7058 	} else {
7059 		err = 0;
7060 		memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
7061 
7062 		ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
7063 	}
7064 
7065 	spin_lock_irqsave(hba->host->host_lock, flags);
7066 	hba->tmf_rqs[req->tag] = NULL;
7067 	__clear_bit(task_tag, &hba->outstanding_tasks);
7068 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7069 
7070 	ufshcd_release(hba);
7071 	blk_mq_free_request(req);
7072 
7073 	return err;
7074 }
7075 
7076 /**
7077  * ufshcd_issue_tm_cmd - issues task management commands to controller
7078  * @hba: per adapter instance
7079  * @lun_id: LUN ID to which TM command is sent
7080  * @task_id: task ID to which the TM command is applicable
7081  * @tm_function: task management function opcode
7082  * @tm_response: task management service response return value
7083  *
7084  * Return: non-zero value on error, zero on success.
7085  */
ufshcd_issue_tm_cmd(struct ufs_hba * hba,int lun_id,int task_id,u8 tm_function,u8 * tm_response)7086 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
7087 		u8 tm_function, u8 *tm_response)
7088 {
7089 	struct utp_task_req_desc treq = { };
7090 	enum utp_ocs ocs_value;
7091 	int err;
7092 
7093 	/* Configure task request descriptor */
7094 	treq.header.interrupt = 1;
7095 	treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7096 
7097 	/* Configure task request UPIU */
7098 	treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ;
7099 	treq.upiu_req.req_header.lun = lun_id;
7100 	treq.upiu_req.req_header.tm_function = tm_function;
7101 
7102 	/*
7103 	 * The host shall provide the same value for LUN field in the basic
7104 	 * header and for Input Parameter.
7105 	 */
7106 	treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
7107 	treq.upiu_req.input_param2 = cpu_to_be32(task_id);
7108 
7109 	err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
7110 	if (err == -ETIMEDOUT)
7111 		return err;
7112 
7113 	ocs_value = treq.header.ocs & MASK_OCS;
7114 	if (ocs_value != OCS_SUCCESS)
7115 		dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
7116 				__func__, ocs_value);
7117 	else if (tm_response)
7118 		*tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
7119 				MASK_TM_SERVICE_RESP;
7120 	return err;
7121 }
7122 
7123 /**
7124  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
7125  * @hba:	per-adapter instance
7126  * @req_upiu:	upiu request
7127  * @rsp_upiu:	upiu reply
7128  * @desc_buff:	pointer to descriptor buffer, NULL if NA
7129  * @buff_len:	descriptor size, 0 if NA
7130  * @cmd_type:	specifies the type (NOP, Query...)
7131  * @desc_op:	descriptor operation
7132  *
7133  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
7134  * Therefore, it "rides" the device management infrastructure: uses its tag and
7135  * tasks work queues.
7136  *
7137  * Since there is only one available tag for device management commands,
7138  * the caller is expected to hold the hba->dev_cmd.lock mutex.
7139  *
7140  * Return: 0 upon success; < 0 upon failure.
7141  */
ufshcd_issue_devman_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,u8 * desc_buff,int * buff_len,enum dev_cmd_type cmd_type,enum query_opcode desc_op)7142 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
7143 					struct utp_upiu_req *req_upiu,
7144 					struct utp_upiu_req *rsp_upiu,
7145 					u8 *desc_buff, int *buff_len,
7146 					enum dev_cmd_type cmd_type,
7147 					enum query_opcode desc_op)
7148 {
7149 	const u32 tag = hba->reserved_slot;
7150 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7151 	int err = 0;
7152 	u8 upiu_flags;
7153 
7154 	/* Protects use of hba->reserved_slot. */
7155 	lockdep_assert_held(&hba->dev_cmd.lock);
7156 
7157 	ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag);
7158 
7159 	ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0);
7160 
7161 	/* update the task tag in the request upiu */
7162 	req_upiu->header.task_tag = tag;
7163 
7164 	/* just copy the upiu request as it is */
7165 	memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7166 	if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
7167 		/* The Data Segment Area is optional depending upon the query
7168 		 * function value. for WRITE DESCRIPTOR, the data segment
7169 		 * follows right after the tsf.
7170 		 */
7171 		memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
7172 		*buff_len = 0;
7173 	}
7174 
7175 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7176 
7177 	/*
7178 	 * ignore the returning value here - ufshcd_check_query_response is
7179 	 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
7180 	 * read the response directly ignoring all errors.
7181 	 */
7182 	ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT);
7183 
7184 	/* just copy the upiu response as it is */
7185 	memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7186 	if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
7187 		u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
7188 		u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
7189 					   .data_segment_length);
7190 
7191 		if (*buff_len >= resp_len) {
7192 			memcpy(desc_buff, descp, resp_len);
7193 			*buff_len = resp_len;
7194 		} else {
7195 			dev_warn(hba->dev,
7196 				 "%s: rsp size %d is bigger than buffer size %d",
7197 				 __func__, resp_len, *buff_len);
7198 			*buff_len = 0;
7199 			err = -EINVAL;
7200 		}
7201 	}
7202 	ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
7203 				    (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
7204 
7205 	return err;
7206 }
7207 
7208 /**
7209  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
7210  * @hba:	per-adapter instance
7211  * @req_upiu:	upiu request
7212  * @rsp_upiu:	upiu reply - only 8 DW as we do not support scsi commands
7213  * @msgcode:	message code, one of UPIU Transaction Codes Initiator to Target
7214  * @desc_buff:	pointer to descriptor buffer, NULL if NA
7215  * @buff_len:	descriptor size, 0 if NA
7216  * @desc_op:	descriptor operation
7217  *
7218  * Supports UTP Transfer requests (nop and query), and UTP Task
7219  * Management requests.
7220  * It is up to the caller to fill the upiu conent properly, as it will
7221  * be copied without any further input validations.
7222  *
7223  * Return: 0 upon success; < 0 upon failure.
7224  */
ufshcd_exec_raw_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,enum upiu_request_transaction msgcode,u8 * desc_buff,int * buff_len,enum query_opcode desc_op)7225 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
7226 			     struct utp_upiu_req *req_upiu,
7227 			     struct utp_upiu_req *rsp_upiu,
7228 			     enum upiu_request_transaction msgcode,
7229 			     u8 *desc_buff, int *buff_len,
7230 			     enum query_opcode desc_op)
7231 {
7232 	int err;
7233 	enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
7234 	struct utp_task_req_desc treq = { };
7235 	enum utp_ocs ocs_value;
7236 	u8 tm_f = req_upiu->header.tm_function;
7237 
7238 	switch (msgcode) {
7239 	case UPIU_TRANSACTION_NOP_OUT:
7240 		cmd_type = DEV_CMD_TYPE_NOP;
7241 		fallthrough;
7242 	case UPIU_TRANSACTION_QUERY_REQ:
7243 		ufshcd_dev_man_lock(hba);
7244 		err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
7245 						   desc_buff, buff_len,
7246 						   cmd_type, desc_op);
7247 		ufshcd_dev_man_unlock(hba);
7248 
7249 		break;
7250 	case UPIU_TRANSACTION_TASK_REQ:
7251 		treq.header.interrupt = 1;
7252 		treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7253 
7254 		memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
7255 
7256 		err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
7257 		if (err == -ETIMEDOUT)
7258 			break;
7259 
7260 		ocs_value = treq.header.ocs & MASK_OCS;
7261 		if (ocs_value != OCS_SUCCESS) {
7262 			dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
7263 				ocs_value);
7264 			break;
7265 		}
7266 
7267 		memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
7268 
7269 		break;
7270 	default:
7271 		err = -EINVAL;
7272 
7273 		break;
7274 	}
7275 
7276 	return err;
7277 }
7278 
7279 /**
7280  * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
7281  * @hba:	per adapter instance
7282  * @req_upiu:	upiu request
7283  * @rsp_upiu:	upiu reply
7284  * @req_ehs:	EHS field which contains Advanced RPMB Request Message
7285  * @rsp_ehs:	EHS field which returns Advanced RPMB Response Message
7286  * @sg_cnt:	The number of sg lists actually used
7287  * @sg_list:	Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7288  * @dir:	DMA direction
7289  *
7290  * Return: zero on success, non-zero on failure.
7291  */
ufshcd_advanced_rpmb_req_handler(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,struct ufs_ehs * req_ehs,struct ufs_ehs * rsp_ehs,int sg_cnt,struct scatterlist * sg_list,enum dma_data_direction dir)7292 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7293 			 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7294 			 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7295 			 enum dma_data_direction dir)
7296 {
7297 	const u32 tag = hba->reserved_slot;
7298 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7299 	int err = 0;
7300 	int result;
7301 	u8 upiu_flags;
7302 	u8 *ehs_data;
7303 	u16 ehs_len;
7304 	int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0;
7305 
7306 	/* Protects use of hba->reserved_slot. */
7307 	ufshcd_dev_man_lock(hba);
7308 
7309 	ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag);
7310 
7311 	ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs);
7312 
7313 	/* update the task tag */
7314 	req_upiu->header.task_tag = tag;
7315 
7316 	/* copy the UPIU(contains CDB) request as it is */
7317 	memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7318 	/* Copy EHS, starting with byte32, immediately after the CDB package */
7319 	memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7320 
7321 	if (dir != DMA_NONE && sg_list)
7322 		ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list);
7323 
7324 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7325 
7326 	err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT);
7327 
7328 	if (!err) {
7329 		/* Just copy the upiu response as it is */
7330 		memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7331 		/* Get the response UPIU result */
7332 		result = (lrbp->ucd_rsp_ptr->header.response << 8) |
7333 			lrbp->ucd_rsp_ptr->header.status;
7334 
7335 		ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length;
7336 		/*
7337 		 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7338 		 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7339 		 * Message is 02h
7340 		 */
7341 		if (ehs_len == 2 && rsp_ehs) {
7342 			/*
7343 			 * ucd_rsp_ptr points to a buffer with a length of 512 bytes
7344 			 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7345 			 */
7346 			ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7347 			memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7348 		}
7349 	}
7350 
7351 	ufshcd_dev_man_unlock(hba);
7352 
7353 	return err ? : result;
7354 }
7355 
7356 /**
7357  * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7358  * @cmd: SCSI command pointer
7359  *
7360  * Return: SUCCESS or FAILED.
7361  */
ufshcd_eh_device_reset_handler(struct scsi_cmnd * cmd)7362 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7363 {
7364 	unsigned long flags, pending_reqs = 0, not_cleared = 0;
7365 	struct Scsi_Host *host;
7366 	struct ufs_hba *hba;
7367 	struct ufs_hw_queue *hwq;
7368 	struct ufshcd_lrb *lrbp;
7369 	u32 pos, not_cleared_mask = 0;
7370 	int err;
7371 	u8 resp = 0xF, lun;
7372 
7373 	host = cmd->device->host;
7374 	hba = shost_priv(host);
7375 
7376 	lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7377 	err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
7378 	if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7379 		if (!err)
7380 			err = resp;
7381 		goto out;
7382 	}
7383 
7384 	if (hba->mcq_enabled) {
7385 		for (pos = 0; pos < hba->nutrs; pos++) {
7386 			lrbp = &hba->lrb[pos];
7387 			if (ufshcd_cmd_inflight(lrbp->cmd) &&
7388 			    lrbp->lun == lun) {
7389 				ufshcd_clear_cmd(hba, pos);
7390 				hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
7391 				ufshcd_mcq_poll_cqe_lock(hba, hwq);
7392 			}
7393 		}
7394 		err = 0;
7395 		goto out;
7396 	}
7397 
7398 	/* clear the commands that were pending for corresponding LUN */
7399 	spin_lock_irqsave(&hba->outstanding_lock, flags);
7400 	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7401 		if (hba->lrb[pos].lun == lun)
7402 			__set_bit(pos, &pending_reqs);
7403 	hba->outstanding_reqs &= ~pending_reqs;
7404 	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7405 
7406 	for_each_set_bit(pos, &pending_reqs, hba->nutrs) {
7407 		if (ufshcd_clear_cmd(hba, pos) < 0) {
7408 			spin_lock_irqsave(&hba->outstanding_lock, flags);
7409 			not_cleared = 1U << pos &
7410 				ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7411 			hba->outstanding_reqs |= not_cleared;
7412 			not_cleared_mask |= not_cleared;
7413 			spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7414 
7415 			dev_err(hba->dev, "%s: failed to clear request %d\n",
7416 				__func__, pos);
7417 		}
7418 	}
7419 	__ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask);
7420 
7421 out:
7422 	hba->req_abort_count = 0;
7423 	ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7424 	if (!err) {
7425 		err = SUCCESS;
7426 	} else {
7427 		dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7428 		err = FAILED;
7429 	}
7430 	return err;
7431 }
7432 
ufshcd_set_req_abort_skip(struct ufs_hba * hba,unsigned long bitmap)7433 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7434 {
7435 	struct ufshcd_lrb *lrbp;
7436 	int tag;
7437 
7438 	for_each_set_bit(tag, &bitmap, hba->nutrs) {
7439 		lrbp = &hba->lrb[tag];
7440 		lrbp->req_abort_skip = true;
7441 	}
7442 }
7443 
7444 /**
7445  * ufshcd_try_to_abort_task - abort a specific task
7446  * @hba: Pointer to adapter instance
7447  * @tag: Task tag/index to be aborted
7448  *
7449  * Abort the pending command in device by sending UFS_ABORT_TASK task management
7450  * command, and in host controller by clearing the door-bell register. There can
7451  * be race between controller sending the command to the device while abort is
7452  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7453  * really issued and then try to abort it.
7454  *
7455  * Return: zero on success, non-zero on failure.
7456  */
ufshcd_try_to_abort_task(struct ufs_hba * hba,int tag)7457 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7458 {
7459 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7460 	int err;
7461 	int poll_cnt;
7462 	u8 resp = 0xF;
7463 
7464 	for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7465 		err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7466 				UFS_QUERY_TASK, &resp);
7467 		if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7468 			/* cmd pending in the device */
7469 			dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7470 				__func__, tag);
7471 			break;
7472 		} else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7473 			/*
7474 			 * cmd not pending in the device, check if it is
7475 			 * in transition.
7476 			 */
7477 			dev_info(
7478 				hba->dev,
7479 				"%s: cmd with tag %d not pending in the device.\n",
7480 				__func__, tag);
7481 			if (!ufshcd_cmd_inflight(lrbp->cmd)) {
7482 				dev_info(hba->dev,
7483 					 "%s: cmd with tag=%d completed.\n",
7484 					 __func__, tag);
7485 				return 0;
7486 			}
7487 			usleep_range(100, 200);
7488 		} else {
7489 			dev_err(hba->dev,
7490 				"%s: no response from device. tag = %d, err %d\n",
7491 				__func__, tag, err);
7492 			return err ? : resp;
7493 		}
7494 	}
7495 
7496 	if (!poll_cnt)
7497 		return -EBUSY;
7498 
7499 	err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7500 			UFS_ABORT_TASK, &resp);
7501 	if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7502 		if (!err) {
7503 			err = resp; /* service response error */
7504 			dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7505 				__func__, tag, err);
7506 		}
7507 		return err;
7508 	}
7509 
7510 	err = ufshcd_clear_cmd(hba, tag);
7511 	if (err)
7512 		dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7513 			__func__, tag, err);
7514 
7515 	return err;
7516 }
7517 
7518 /**
7519  * ufshcd_abort - scsi host template eh_abort_handler callback
7520  * @cmd: SCSI command pointer
7521  *
7522  * Return: SUCCESS or FAILED.
7523  */
ufshcd_abort(struct scsi_cmnd * cmd)7524 static int ufshcd_abort(struct scsi_cmnd *cmd)
7525 {
7526 	struct Scsi_Host *host = cmd->device->host;
7527 	struct ufs_hba *hba = shost_priv(host);
7528 	int tag = scsi_cmd_to_rq(cmd)->tag;
7529 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7530 	unsigned long flags;
7531 	int err = FAILED;
7532 	bool outstanding;
7533 	u32 reg;
7534 
7535 	ufshcd_hold(hba);
7536 
7537 	if (!hba->mcq_enabled) {
7538 		reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7539 		if (!test_bit(tag, &hba->outstanding_reqs)) {
7540 			/* If command is already aborted/completed, return FAILED. */
7541 			dev_err(hba->dev,
7542 				"%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7543 				__func__, tag, hba->outstanding_reqs, reg);
7544 			goto release;
7545 		}
7546 	}
7547 
7548 	/* Print Transfer Request of aborted task */
7549 	dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7550 
7551 	/*
7552 	 * Print detailed info about aborted request.
7553 	 * As more than one request might get aborted at the same time,
7554 	 * print full information only for the first aborted request in order
7555 	 * to reduce repeated printouts. For other aborted requests only print
7556 	 * basic details.
7557 	 */
7558 	scsi_print_command(cmd);
7559 	if (!hba->req_abort_count) {
7560 		ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7561 		ufshcd_print_evt_hist(hba);
7562 		ufshcd_print_host_state(hba);
7563 		ufshcd_print_pwr_info(hba);
7564 		ufshcd_print_tr(hba, tag, true);
7565 	} else {
7566 		ufshcd_print_tr(hba, tag, false);
7567 	}
7568 	hba->req_abort_count++;
7569 
7570 	if (!hba->mcq_enabled && !(reg & (1 << tag))) {
7571 		/* only execute this code in single doorbell mode */
7572 		dev_err(hba->dev,
7573 		"%s: cmd was completed, but without a notifying intr, tag = %d",
7574 		__func__, tag);
7575 		__ufshcd_transfer_req_compl(hba, 1UL << tag);
7576 		goto release;
7577 	}
7578 
7579 	/*
7580 	 * Task abort to the device W-LUN is illegal. When this command
7581 	 * will fail, due to spec violation, scsi err handling next step
7582 	 * will be to send LU reset which, again, is a spec violation.
7583 	 * To avoid these unnecessary/illegal steps, first we clean up
7584 	 * the lrb taken by this cmd and re-set it in outstanding_reqs,
7585 	 * then queue the eh_work and bail.
7586 	 */
7587 	if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7588 		ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7589 
7590 		spin_lock_irqsave(host->host_lock, flags);
7591 		hba->force_reset = true;
7592 		ufshcd_schedule_eh_work(hba);
7593 		spin_unlock_irqrestore(host->host_lock, flags);
7594 		goto release;
7595 	}
7596 
7597 	if (hba->mcq_enabled) {
7598 		/* MCQ mode. Branch off to handle abort for mcq mode */
7599 		err = ufshcd_mcq_abort(cmd);
7600 		goto release;
7601 	}
7602 
7603 	/* Skip task abort in case previous aborts failed and report failure */
7604 	if (lrbp->req_abort_skip) {
7605 		dev_err(hba->dev, "%s: skipping abort\n", __func__);
7606 		ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7607 		goto release;
7608 	}
7609 
7610 	err = ufshcd_try_to_abort_task(hba, tag);
7611 	if (err) {
7612 		dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7613 		ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7614 		err = FAILED;
7615 		goto release;
7616 	}
7617 
7618 	/*
7619 	 * Clear the corresponding bit from outstanding_reqs since the command
7620 	 * has been aborted successfully.
7621 	 */
7622 	spin_lock_irqsave(&hba->outstanding_lock, flags);
7623 	outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7624 	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7625 
7626 	if (outstanding)
7627 		ufshcd_release_scsi_cmd(hba, lrbp);
7628 
7629 	err = SUCCESS;
7630 
7631 release:
7632 	/* Matches the ufshcd_hold() call at the start of this function. */
7633 	ufshcd_release(hba);
7634 	return err;
7635 }
7636 
7637 /**
7638  * ufshcd_process_probe_result - Process the ufshcd_probe_hba() result.
7639  * @hba: UFS host controller instance.
7640  * @probe_start: time when the ufshcd_probe_hba() call started.
7641  * @ret: ufshcd_probe_hba() return value.
7642  */
ufshcd_process_probe_result(struct ufs_hba * hba,ktime_t probe_start,int ret)7643 static void ufshcd_process_probe_result(struct ufs_hba *hba,
7644 					ktime_t probe_start, int ret)
7645 {
7646 	unsigned long flags;
7647 
7648 	spin_lock_irqsave(hba->host->host_lock, flags);
7649 	if (ret)
7650 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
7651 	else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
7652 		hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
7653 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7654 
7655 	trace_ufshcd_init(dev_name(hba->dev), ret,
7656 			  ktime_to_us(ktime_sub(ktime_get(), probe_start)),
7657 			  hba->curr_dev_pwr_mode, hba->uic_link_state);
7658 }
7659 
7660 /**
7661  * ufshcd_host_reset_and_restore - reset and restore host controller
7662  * @hba: per-adapter instance
7663  *
7664  * Note that host controller reset may issue DME_RESET to
7665  * local and remote (device) Uni-Pro stack and the attributes
7666  * are reset to default state.
7667  *
7668  * Return: zero on success, non-zero on failure.
7669  */
ufshcd_host_reset_and_restore(struct ufs_hba * hba)7670 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7671 {
7672 	int err;
7673 
7674 	/*
7675 	 * Stop the host controller and complete the requests
7676 	 * cleared by h/w
7677 	 */
7678 	ufshcd_hba_stop(hba);
7679 	hba->silence_err_logs = true;
7680 	ufshcd_complete_requests(hba, true);
7681 	hba->silence_err_logs = false;
7682 
7683 	/* scale up clocks to max frequency before full reinitialization */
7684 	ufshcd_scale_clks(hba, ULONG_MAX, true);
7685 
7686 	err = ufshcd_hba_enable(hba);
7687 
7688 	/* Establish the link again and restore the device */
7689 	if (!err) {
7690 		ktime_t probe_start = ktime_get();
7691 
7692 		err = ufshcd_device_init(hba, /*init_dev_params=*/false);
7693 		if (!err)
7694 			err = ufshcd_probe_hba(hba, false);
7695 		ufshcd_process_probe_result(hba, probe_start, err);
7696 	}
7697 
7698 	if (err)
7699 		dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7700 	ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7701 	return err;
7702 }
7703 
7704 /**
7705  * ufshcd_reset_and_restore - reset and re-initialize host/device
7706  * @hba: per-adapter instance
7707  *
7708  * Reset and recover device, host and re-establish link. This
7709  * is helpful to recover the communication in fatal error conditions.
7710  *
7711  * Return: zero on success, non-zero on failure.
7712  */
ufshcd_reset_and_restore(struct ufs_hba * hba)7713 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7714 {
7715 	u32 saved_err = 0;
7716 	u32 saved_uic_err = 0;
7717 	int err = 0;
7718 	unsigned long flags;
7719 	int retries = MAX_HOST_RESET_RETRIES;
7720 
7721 	spin_lock_irqsave(hba->host->host_lock, flags);
7722 	do {
7723 		/*
7724 		 * This is a fresh start, cache and clear saved error first,
7725 		 * in case new error generated during reset and restore.
7726 		 */
7727 		saved_err |= hba->saved_err;
7728 		saved_uic_err |= hba->saved_uic_err;
7729 		hba->saved_err = 0;
7730 		hba->saved_uic_err = 0;
7731 		hba->force_reset = false;
7732 		hba->ufshcd_state = UFSHCD_STATE_RESET;
7733 		spin_unlock_irqrestore(hba->host->host_lock, flags);
7734 
7735 		/* Reset the attached device */
7736 		ufshcd_device_reset(hba);
7737 
7738 		err = ufshcd_host_reset_and_restore(hba);
7739 
7740 		spin_lock_irqsave(hba->host->host_lock, flags);
7741 		if (err)
7742 			continue;
7743 		/* Do not exit unless operational or dead */
7744 		if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7745 		    hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7746 		    hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7747 			err = -EAGAIN;
7748 	} while (err && --retries);
7749 
7750 	/*
7751 	 * Inform scsi mid-layer that we did reset and allow to handle
7752 	 * Unit Attention properly.
7753 	 */
7754 	scsi_report_bus_reset(hba->host, 0);
7755 	if (err) {
7756 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
7757 		hba->saved_err |= saved_err;
7758 		hba->saved_uic_err |= saved_uic_err;
7759 	}
7760 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7761 
7762 	return err;
7763 }
7764 
7765 /**
7766  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7767  * @cmd: SCSI command pointer
7768  *
7769  * Return: SUCCESS or FAILED.
7770  */
ufshcd_eh_host_reset_handler(struct scsi_cmnd * cmd)7771 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7772 {
7773 	int err = SUCCESS;
7774 	unsigned long flags;
7775 	struct ufs_hba *hba;
7776 
7777 	hba = shost_priv(cmd->device->host);
7778 
7779 	/*
7780 	 * If runtime PM sent SSU and got a timeout, scsi_error_handler is
7781 	 * stuck in this function waiting for flush_work(&hba->eh_work). And
7782 	 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do
7783 	 * ufshcd_link_recovery instead of eh_work to prevent deadlock.
7784 	 */
7785 	if (hba->pm_op_in_progress) {
7786 		if (ufshcd_link_recovery(hba))
7787 			err = FAILED;
7788 
7789 		return err;
7790 	}
7791 
7792 	spin_lock_irqsave(hba->host->host_lock, flags);
7793 	hba->force_reset = true;
7794 	ufshcd_schedule_eh_work(hba);
7795 	dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7796 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7797 
7798 	flush_work(&hba->eh_work);
7799 
7800 	spin_lock_irqsave(hba->host->host_lock, flags);
7801 	if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7802 		err = FAILED;
7803 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7804 
7805 	return err;
7806 }
7807 
7808 /**
7809  * ufshcd_get_max_icc_level - calculate the ICC level
7810  * @sup_curr_uA: max. current supported by the regulator
7811  * @start_scan: row at the desc table to start scan from
7812  * @buff: power descriptor buffer
7813  *
7814  * Return: calculated max ICC level for specific regulator.
7815  */
ufshcd_get_max_icc_level(int sup_curr_uA,u32 start_scan,const char * buff)7816 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
7817 				    const char *buff)
7818 {
7819 	int i;
7820 	int curr_uA;
7821 	u16 data;
7822 	u16 unit;
7823 
7824 	for (i = start_scan; i >= 0; i--) {
7825 		data = get_unaligned_be16(&buff[2 * i]);
7826 		unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7827 						ATTR_ICC_LVL_UNIT_OFFSET;
7828 		curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7829 		switch (unit) {
7830 		case UFSHCD_NANO_AMP:
7831 			curr_uA = curr_uA / 1000;
7832 			break;
7833 		case UFSHCD_MILI_AMP:
7834 			curr_uA = curr_uA * 1000;
7835 			break;
7836 		case UFSHCD_AMP:
7837 			curr_uA = curr_uA * 1000 * 1000;
7838 			break;
7839 		case UFSHCD_MICRO_AMP:
7840 		default:
7841 			break;
7842 		}
7843 		if (sup_curr_uA >= curr_uA)
7844 			break;
7845 	}
7846 	if (i < 0) {
7847 		i = 0;
7848 		pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7849 	}
7850 
7851 	return (u32)i;
7852 }
7853 
7854 /**
7855  * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7856  * In case regulators are not initialized we'll return 0
7857  * @hba: per-adapter instance
7858  * @desc_buf: power descriptor buffer to extract ICC levels from.
7859  *
7860  * Return: calculated ICC level.
7861  */
ufshcd_find_max_sup_active_icc_level(struct ufs_hba * hba,const u8 * desc_buf)7862 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7863 						const u8 *desc_buf)
7864 {
7865 	u32 icc_level = 0;
7866 
7867 	if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7868 						!hba->vreg_info.vccq2) {
7869 		/*
7870 		 * Using dev_dbg to avoid messages during runtime PM to avoid
7871 		 * never-ending cycles of messages written back to storage by
7872 		 * user space causing runtime resume, causing more messages and
7873 		 * so on.
7874 		 */
7875 		dev_dbg(hba->dev,
7876 			"%s: Regulator capability was not set, actvIccLevel=%d",
7877 							__func__, icc_level);
7878 		goto out;
7879 	}
7880 
7881 	if (hba->vreg_info.vcc->max_uA)
7882 		icc_level = ufshcd_get_max_icc_level(
7883 				hba->vreg_info.vcc->max_uA,
7884 				POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7885 				&desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7886 
7887 	if (hba->vreg_info.vccq->max_uA)
7888 		icc_level = ufshcd_get_max_icc_level(
7889 				hba->vreg_info.vccq->max_uA,
7890 				icc_level,
7891 				&desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7892 
7893 	if (hba->vreg_info.vccq2->max_uA)
7894 		icc_level = ufshcd_get_max_icc_level(
7895 				hba->vreg_info.vccq2->max_uA,
7896 				icc_level,
7897 				&desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7898 out:
7899 	return icc_level;
7900 }
7901 
ufshcd_set_active_icc_lvl(struct ufs_hba * hba)7902 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7903 {
7904 	int ret;
7905 	u8 *desc_buf;
7906 	u32 icc_level;
7907 
7908 	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7909 	if (!desc_buf)
7910 		return;
7911 
7912 	ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7913 				     desc_buf, QUERY_DESC_MAX_SIZE);
7914 	if (ret) {
7915 		dev_err(hba->dev,
7916 			"%s: Failed reading power descriptor ret = %d",
7917 			__func__, ret);
7918 		goto out;
7919 	}
7920 
7921 	icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
7922 	dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7923 
7924 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7925 		QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7926 
7927 	if (ret)
7928 		dev_err(hba->dev,
7929 			"%s: Failed configuring bActiveICCLevel = %d ret = %d",
7930 			__func__, icc_level, ret);
7931 
7932 out:
7933 	kfree(desc_buf);
7934 }
7935 
ufshcd_blk_pm_runtime_init(struct scsi_device * sdev)7936 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7937 {
7938 	struct Scsi_Host *shost = sdev->host;
7939 
7940 	scsi_autopm_get_device(sdev);
7941 	blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7942 	if (sdev->rpm_autosuspend)
7943 		pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7944 						 shost->rpm_autosuspend_delay);
7945 	scsi_autopm_put_device(sdev);
7946 }
7947 
7948 /**
7949  * ufshcd_scsi_add_wlus - Adds required W-LUs
7950  * @hba: per-adapter instance
7951  *
7952  * UFS device specification requires the UFS devices to support 4 well known
7953  * logical units:
7954  *	"REPORT_LUNS" (address: 01h)
7955  *	"UFS Device" (address: 50h)
7956  *	"RPMB" (address: 44h)
7957  *	"BOOT" (address: 30h)
7958  * UFS device's power management needs to be controlled by "POWER CONDITION"
7959  * field of SSU (START STOP UNIT) command. But this "power condition" field
7960  * will take effect only when its sent to "UFS device" well known logical unit
7961  * hence we require the scsi_device instance to represent this logical unit in
7962  * order for the UFS host driver to send the SSU command for power management.
7963  *
7964  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7965  * Block) LU so user space process can control this LU. User space may also
7966  * want to have access to BOOT LU.
7967  *
7968  * This function adds scsi device instances for each of all well known LUs
7969  * (except "REPORT LUNS" LU).
7970  *
7971  * Return: zero on success (all required W-LUs are added successfully),
7972  * non-zero error value on failure (if failed to add any of the required W-LU).
7973  */
ufshcd_scsi_add_wlus(struct ufs_hba * hba)7974 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7975 {
7976 	int ret = 0;
7977 	struct scsi_device *sdev_boot, *sdev_rpmb;
7978 
7979 	hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
7980 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7981 	if (IS_ERR(hba->ufs_device_wlun)) {
7982 		ret = PTR_ERR(hba->ufs_device_wlun);
7983 		hba->ufs_device_wlun = NULL;
7984 		goto out;
7985 	}
7986 	scsi_device_put(hba->ufs_device_wlun);
7987 
7988 	sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7989 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7990 	if (IS_ERR(sdev_rpmb)) {
7991 		ret = PTR_ERR(sdev_rpmb);
7992 		goto remove_ufs_device_wlun;
7993 	}
7994 	ufshcd_blk_pm_runtime_init(sdev_rpmb);
7995 	scsi_device_put(sdev_rpmb);
7996 
7997 	sdev_boot = __scsi_add_device(hba->host, 0, 0,
7998 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7999 	if (IS_ERR(sdev_boot)) {
8000 		dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
8001 	} else {
8002 		ufshcd_blk_pm_runtime_init(sdev_boot);
8003 		scsi_device_put(sdev_boot);
8004 	}
8005 	goto out;
8006 
8007 remove_ufs_device_wlun:
8008 	scsi_remove_device(hba->ufs_device_wlun);
8009 out:
8010 	return ret;
8011 }
8012 
ufshcd_wb_probe(struct ufs_hba * hba,const u8 * desc_buf)8013 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
8014 {
8015 	struct ufs_dev_info *dev_info = &hba->dev_info;
8016 	u8 lun;
8017 	u32 d_lu_wb_buf_alloc;
8018 	u32 ext_ufs_feature;
8019 
8020 	if (!ufshcd_is_wb_allowed(hba))
8021 		return;
8022 
8023 	/*
8024 	 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
8025 	 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
8026 	 * enabled
8027 	 */
8028 	if (!(dev_info->wspecversion >= 0x310 ||
8029 	      dev_info->wspecversion == 0x220 ||
8030 	     (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
8031 		goto wb_disabled;
8032 
8033 	ext_ufs_feature = get_unaligned_be32(desc_buf +
8034 					DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8035 
8036 	if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
8037 		goto wb_disabled;
8038 
8039 	/*
8040 	 * WB may be supported but not configured while provisioning. The spec
8041 	 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
8042 	 * buffer configured.
8043 	 */
8044 	dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
8045 
8046 	dev_info->b_presrv_uspc_en =
8047 		desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
8048 
8049 	if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
8050 		if (!get_unaligned_be32(desc_buf +
8051 				   DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
8052 			goto wb_disabled;
8053 	} else {
8054 		for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
8055 			d_lu_wb_buf_alloc = 0;
8056 			ufshcd_read_unit_desc_param(hba,
8057 					lun,
8058 					UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
8059 					(u8 *)&d_lu_wb_buf_alloc,
8060 					sizeof(d_lu_wb_buf_alloc));
8061 			if (d_lu_wb_buf_alloc) {
8062 				dev_info->wb_dedicated_lu = lun;
8063 				break;
8064 			}
8065 		}
8066 
8067 		if (!d_lu_wb_buf_alloc)
8068 			goto wb_disabled;
8069 	}
8070 
8071 	if (!ufshcd_is_wb_buf_lifetime_available(hba))
8072 		goto wb_disabled;
8073 
8074 	return;
8075 
8076 wb_disabled:
8077 	hba->caps &= ~UFSHCD_CAP_WB_EN;
8078 }
8079 
ufshcd_temp_notif_probe(struct ufs_hba * hba,const u8 * desc_buf)8080 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
8081 {
8082 	struct ufs_dev_info *dev_info = &hba->dev_info;
8083 	u32 ext_ufs_feature;
8084 	u8 mask = 0;
8085 
8086 	if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
8087 		return;
8088 
8089 	ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8090 
8091 	if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
8092 		mask |= MASK_EE_TOO_LOW_TEMP;
8093 
8094 	if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
8095 		mask |= MASK_EE_TOO_HIGH_TEMP;
8096 
8097 	if (mask) {
8098 		ufshcd_enable_ee(hba, mask);
8099 		ufs_hwmon_probe(hba, mask);
8100 	}
8101 }
8102 
ufshcd_set_rtt(struct ufs_hba * hba)8103 static void ufshcd_set_rtt(struct ufs_hba *hba)
8104 {
8105 	struct ufs_dev_info *dev_info = &hba->dev_info;
8106 	u32 rtt = 0;
8107 	u32 dev_rtt = 0;
8108 	int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ?
8109 			   hba->vops->max_num_rtt : hba->nortt;
8110 
8111 	/* RTT override makes sense only for UFS-4.0 and above */
8112 	if (dev_info->wspecversion < 0x400)
8113 		return;
8114 
8115 	if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8116 				    QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) {
8117 		dev_err(hba->dev, "failed reading bMaxNumOfRTT\n");
8118 		return;
8119 	}
8120 
8121 	/* do not override if it was already written */
8122 	if (dev_rtt != DEFAULT_MAX_NUM_RTT)
8123 		return;
8124 
8125 	rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap);
8126 
8127 	if (rtt == dev_rtt)
8128 		return;
8129 
8130 	if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8131 				    QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt))
8132 		dev_err(hba->dev, "failed writing bMaxNumOfRTT\n");
8133 }
8134 
ufshcd_fixup_dev_quirks(struct ufs_hba * hba,const struct ufs_dev_quirk * fixups)8135 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
8136 			     const struct ufs_dev_quirk *fixups)
8137 {
8138 	const struct ufs_dev_quirk *f;
8139 	struct ufs_dev_info *dev_info = &hba->dev_info;
8140 
8141 	if (!fixups)
8142 		return;
8143 
8144 	for (f = fixups; f->quirk; f++) {
8145 		if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
8146 		     f->wmanufacturerid == UFS_ANY_VENDOR) &&
8147 		     ((dev_info->model &&
8148 		       STR_PRFX_EQUAL(f->model, dev_info->model)) ||
8149 		      !strcmp(f->model, UFS_ANY_MODEL)))
8150 			hba->dev_quirks |= f->quirk;
8151 	}
8152 }
8153 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
8154 
ufs_fixup_device_setup(struct ufs_hba * hba)8155 static void ufs_fixup_device_setup(struct ufs_hba *hba)
8156 {
8157 	/* fix by general quirk table */
8158 	ufshcd_fixup_dev_quirks(hba, ufs_fixups);
8159 
8160 	/* allow vendors to fix quirks */
8161 	ufshcd_vops_fixup_dev_quirks(hba);
8162 }
8163 
ufshcd_update_rtc(struct ufs_hba * hba)8164 static void ufshcd_update_rtc(struct ufs_hba *hba)
8165 {
8166 	struct timespec64 ts64;
8167 	int err;
8168 	u32 val;
8169 
8170 	ktime_get_real_ts64(&ts64);
8171 
8172 	if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) {
8173 		dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__);
8174 		return;
8175 	}
8176 
8177 	/*
8178 	 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond
8179 	 * 2146 is required, it is recommended to choose the relative RTC mode.
8180 	 */
8181 	val = ts64.tv_sec - hba->dev_info.rtc_time_baseline;
8182 
8183 	/* Skip update RTC if RPM state is not RPM_ACTIVE */
8184 	if (ufshcd_rpm_get_if_active(hba) <= 0)
8185 		return;
8186 
8187 	err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED,
8188 				0, 0, &val);
8189 	ufshcd_rpm_put(hba);
8190 
8191 	if (err)
8192 		dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err);
8193 	else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE)
8194 		hba->dev_info.rtc_time_baseline = ts64.tv_sec;
8195 }
8196 
ufshcd_rtc_work(struct work_struct * work)8197 static void ufshcd_rtc_work(struct work_struct *work)
8198 {
8199 	struct ufs_hba *hba;
8200 
8201 	hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work);
8202 
8203 	 /* Update RTC only when there are no requests in progress and UFSHCI is operational */
8204 	if (!ufshcd_is_ufs_dev_busy(hba) &&
8205 	    hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL &&
8206 	    !hba->clk_gating.active_reqs)
8207 		ufshcd_update_rtc(hba);
8208 
8209 	if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period)
8210 		schedule_delayed_work(&hba->ufs_rtc_update_work,
8211 				      msecs_to_jiffies(hba->dev_info.rtc_update_period));
8212 }
8213 
ufs_init_rtc(struct ufs_hba * hba,u8 * desc_buf)8214 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf)
8215 {
8216 	u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]);
8217 	struct ufs_dev_info *dev_info = &hba->dev_info;
8218 
8219 	if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) {
8220 		dev_info->rtc_type = UFS_RTC_ABSOLUTE;
8221 
8222 		/*
8223 		 * The concept of measuring time in Linux as the number of seconds elapsed since
8224 		 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st
8225 		 * 2010 00:00, here we need to adjust ABS baseline.
8226 		 */
8227 		dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) -
8228 							mktime64(1970, 1, 1, 0, 0, 0);
8229 	} else {
8230 		dev_info->rtc_type = UFS_RTC_RELATIVE;
8231 		dev_info->rtc_time_baseline = 0;
8232 	}
8233 
8234 	/*
8235 	 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state
8236 	 * how to calculate the specific update period for each time unit. And we disable periodic
8237 	 * RTC update work, let user configure by sysfs node according to specific circumstance.
8238 	 */
8239 	dev_info->rtc_update_period = 0;
8240 }
8241 
ufs_get_device_desc(struct ufs_hba * hba)8242 static int ufs_get_device_desc(struct ufs_hba *hba)
8243 {
8244 	int err;
8245 	u8 model_index;
8246 	u8 *desc_buf;
8247 	struct ufs_dev_info *dev_info = &hba->dev_info;
8248 
8249 	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8250 	if (!desc_buf) {
8251 		err = -ENOMEM;
8252 		goto out;
8253 	}
8254 
8255 	err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
8256 				     QUERY_DESC_MAX_SIZE);
8257 	if (err) {
8258 		dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
8259 			__func__, err);
8260 		goto out;
8261 	}
8262 
8263 	/*
8264 	 * getting vendor (manufacturerID) and Bank Index in big endian
8265 	 * format
8266 	 */
8267 	dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
8268 				     desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
8269 
8270 	/* getting Specification Version in big endian format */
8271 	dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
8272 				      desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
8273 	dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
8274 
8275 	dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP];
8276 
8277 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
8278 
8279 	err = ufshcd_read_string_desc(hba, model_index,
8280 				      &dev_info->model, SD_ASCII_STD);
8281 	if (err < 0) {
8282 		dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
8283 			__func__, err);
8284 		goto out;
8285 	}
8286 
8287 	hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
8288 		desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
8289 
8290 	ufs_fixup_device_setup(hba);
8291 
8292 	ufshcd_wb_probe(hba, desc_buf);
8293 
8294 	ufshcd_temp_notif_probe(hba, desc_buf);
8295 
8296 	ufs_init_rtc(hba, desc_buf);
8297 
8298 	/*
8299 	 * ufshcd_read_string_desc returns size of the string
8300 	 * reset the error value
8301 	 */
8302 	err = 0;
8303 
8304 out:
8305 	kfree(desc_buf);
8306 	return err;
8307 }
8308 
ufs_put_device_desc(struct ufs_hba * hba)8309 static void ufs_put_device_desc(struct ufs_hba *hba)
8310 {
8311 	struct ufs_dev_info *dev_info = &hba->dev_info;
8312 
8313 	kfree(dev_info->model);
8314 	dev_info->model = NULL;
8315 }
8316 
8317 /**
8318  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
8319  * less than device PA_TACTIVATE time.
8320  * @hba: per-adapter instance
8321  *
8322  * Some UFS devices require host PA_TACTIVATE to be lower than device
8323  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8324  * for such devices.
8325  *
8326  * Return: zero on success, non-zero error value on failure.
8327  */
ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba * hba)8328 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8329 {
8330 	int ret = 0;
8331 	u32 granularity, peer_granularity;
8332 	u32 pa_tactivate, peer_pa_tactivate;
8333 	u32 pa_tactivate_us, peer_pa_tactivate_us;
8334 	static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
8335 
8336 	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8337 				  &granularity);
8338 	if (ret)
8339 		goto out;
8340 
8341 	ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8342 				  &peer_granularity);
8343 	if (ret)
8344 		goto out;
8345 
8346 	if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8347 	    (granularity > PA_GRANULARITY_MAX_VAL)) {
8348 		dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8349 			__func__, granularity);
8350 		return -EINVAL;
8351 	}
8352 
8353 	if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8354 	    (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8355 		dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8356 			__func__, peer_granularity);
8357 		return -EINVAL;
8358 	}
8359 
8360 	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
8361 	if (ret)
8362 		goto out;
8363 
8364 	ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8365 				  &peer_pa_tactivate);
8366 	if (ret)
8367 		goto out;
8368 
8369 	pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8370 	peer_pa_tactivate_us = peer_pa_tactivate *
8371 			     gran_to_us_table[peer_granularity - 1];
8372 
8373 	if (pa_tactivate_us >= peer_pa_tactivate_us) {
8374 		u32 new_peer_pa_tactivate;
8375 
8376 		new_peer_pa_tactivate = pa_tactivate_us /
8377 				      gran_to_us_table[peer_granularity - 1];
8378 		new_peer_pa_tactivate++;
8379 		ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8380 					  new_peer_pa_tactivate);
8381 	}
8382 
8383 out:
8384 	return ret;
8385 }
8386 
ufshcd_tune_unipro_params(struct ufs_hba * hba)8387 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
8388 {
8389 	ufshcd_vops_apply_dev_quirks(hba);
8390 
8391 	if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8392 		/* set 1ms timeout for PA_TACTIVATE */
8393 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
8394 
8395 	if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8396 		ufshcd_quirk_tune_host_pa_tactivate(hba);
8397 }
8398 
ufshcd_clear_dbg_ufs_stats(struct ufs_hba * hba)8399 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8400 {
8401 	hba->ufs_stats.hibern8_exit_cnt = 0;
8402 	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
8403 	hba->req_abort_count = 0;
8404 }
8405 
ufshcd_device_geo_params_init(struct ufs_hba * hba)8406 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8407 {
8408 	int err;
8409 	u8 *desc_buf;
8410 
8411 	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8412 	if (!desc_buf) {
8413 		err = -ENOMEM;
8414 		goto out;
8415 	}
8416 
8417 	err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
8418 				     desc_buf, QUERY_DESC_MAX_SIZE);
8419 	if (err) {
8420 		dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8421 				__func__, err);
8422 		goto out;
8423 	}
8424 
8425 	if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8426 		hba->dev_info.max_lu_supported = 32;
8427 	else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8428 		hba->dev_info.max_lu_supported = 8;
8429 
8430 out:
8431 	kfree(desc_buf);
8432 	return err;
8433 }
8434 
8435 struct ufs_ref_clk {
8436 	unsigned long freq_hz;
8437 	enum ufs_ref_clk_freq val;
8438 };
8439 
8440 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8441 	{19200000, REF_CLK_FREQ_19_2_MHZ},
8442 	{26000000, REF_CLK_FREQ_26_MHZ},
8443 	{38400000, REF_CLK_FREQ_38_4_MHZ},
8444 	{52000000, REF_CLK_FREQ_52_MHZ},
8445 	{0, REF_CLK_FREQ_INVAL},
8446 };
8447 
8448 static enum ufs_ref_clk_freq
ufs_get_bref_clk_from_hz(unsigned long freq)8449 ufs_get_bref_clk_from_hz(unsigned long freq)
8450 {
8451 	int i;
8452 
8453 	for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8454 		if (ufs_ref_clk_freqs[i].freq_hz == freq)
8455 			return ufs_ref_clk_freqs[i].val;
8456 
8457 	return REF_CLK_FREQ_INVAL;
8458 }
8459 
ufshcd_parse_dev_ref_clk_freq(struct ufs_hba * hba,struct clk * refclk)8460 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8461 {
8462 	unsigned long freq;
8463 
8464 	freq = clk_get_rate(refclk);
8465 
8466 	hba->dev_ref_clk_freq =
8467 		ufs_get_bref_clk_from_hz(freq);
8468 
8469 	if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8470 		dev_err(hba->dev,
8471 		"invalid ref_clk setting = %ld\n", freq);
8472 }
8473 
ufshcd_set_dev_ref_clk(struct ufs_hba * hba)8474 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8475 {
8476 	int err;
8477 	u32 ref_clk;
8478 	u32 freq = hba->dev_ref_clk_freq;
8479 
8480 	err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8481 			QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8482 
8483 	if (err) {
8484 		dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8485 			err);
8486 		goto out;
8487 	}
8488 
8489 	if (ref_clk == freq)
8490 		goto out; /* nothing to update */
8491 
8492 	err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8493 			QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8494 
8495 	if (err) {
8496 		dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8497 			ufs_ref_clk_freqs[freq].freq_hz);
8498 		goto out;
8499 	}
8500 
8501 	dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8502 			ufs_ref_clk_freqs[freq].freq_hz);
8503 
8504 out:
8505 	return err;
8506 }
8507 
ufshcd_device_params_init(struct ufs_hba * hba)8508 static int ufshcd_device_params_init(struct ufs_hba *hba)
8509 {
8510 	bool flag;
8511 	int ret;
8512 
8513 	/* Init UFS geometry descriptor related parameters */
8514 	ret = ufshcd_device_geo_params_init(hba);
8515 	if (ret)
8516 		goto out;
8517 
8518 	/* Check and apply UFS device quirks */
8519 	ret = ufs_get_device_desc(hba);
8520 	if (ret) {
8521 		dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8522 			__func__, ret);
8523 		goto out;
8524 	}
8525 
8526 	ufshcd_set_rtt(hba);
8527 
8528 	ufshcd_get_ref_clk_gating_wait(hba);
8529 
8530 	if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
8531 			QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
8532 		hba->dev_info.f_power_on_wp_en = flag;
8533 
8534 	/* Probe maximum power mode co-supported by both UFS host and device */
8535 	if (ufshcd_get_max_pwr_mode(hba))
8536 		dev_err(hba->dev,
8537 			"%s: Failed getting max supported power mode\n",
8538 			__func__);
8539 out:
8540 	return ret;
8541 }
8542 
ufshcd_set_timestamp_attr(struct ufs_hba * hba)8543 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
8544 {
8545 	int err;
8546 	struct ufs_query_req *request = NULL;
8547 	struct ufs_query_res *response = NULL;
8548 	struct ufs_dev_info *dev_info = &hba->dev_info;
8549 	struct utp_upiu_query_v4_0 *upiu_data;
8550 
8551 	if (dev_info->wspecversion < 0x400)
8552 		return;
8553 
8554 	ufshcd_dev_man_lock(hba);
8555 
8556 	ufshcd_init_query(hba, &request, &response,
8557 			  UPIU_QUERY_OPCODE_WRITE_ATTR,
8558 			  QUERY_ATTR_IDN_TIMESTAMP, 0, 0);
8559 
8560 	request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
8561 
8562 	upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req;
8563 
8564 	put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3);
8565 
8566 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
8567 
8568 	if (err)
8569 		dev_err(hba->dev, "%s: failed to set timestamp %d\n",
8570 			__func__, err);
8571 
8572 	ufshcd_dev_man_unlock(hba);
8573 }
8574 
8575 /**
8576  * ufshcd_add_lus - probe and add UFS logical units
8577  * @hba: per-adapter instance
8578  *
8579  * Return: 0 upon success; < 0 upon failure.
8580  */
ufshcd_add_lus(struct ufs_hba * hba)8581 static int ufshcd_add_lus(struct ufs_hba *hba)
8582 {
8583 	int ret;
8584 
8585 	/* Add required well known logical units to scsi mid layer */
8586 	ret = ufshcd_scsi_add_wlus(hba);
8587 	if (ret)
8588 		goto out;
8589 
8590 	/* Initialize devfreq after UFS device is detected */
8591 	if (ufshcd_is_clkscaling_supported(hba)) {
8592 		memcpy(&hba->clk_scaling.saved_pwr_info,
8593 			&hba->pwr_info,
8594 			sizeof(struct ufs_pa_layer_attr));
8595 		hba->clk_scaling.is_allowed = true;
8596 
8597 		ret = ufshcd_devfreq_init(hba);
8598 		if (ret)
8599 			goto out;
8600 
8601 		hba->clk_scaling.is_enabled = true;
8602 		ufshcd_init_clk_scaling_sysfs(hba);
8603 	}
8604 
8605 	/*
8606 	 * The RTC update code accesses the hba->ufs_device_wlun->sdev_gendev
8607 	 * pointer and hence must only be started after the WLUN pointer has
8608 	 * been initialized by ufshcd_scsi_add_wlus().
8609 	 */
8610 	schedule_delayed_work(&hba->ufs_rtc_update_work,
8611 			      msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS));
8612 
8613 	ufs_bsg_probe(hba);
8614 	scsi_scan_host(hba->host);
8615 
8616 out:
8617 	return ret;
8618 }
8619 
8620 /* SDB - Single Doorbell */
ufshcd_release_sdb_queue(struct ufs_hba * hba,int nutrs)8621 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs)
8622 {
8623 	size_t ucdl_size, utrdl_size;
8624 
8625 	ucdl_size = ufshcd_get_ucd_size(hba) * nutrs;
8626 	dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr,
8627 			   hba->ucdl_dma_addr);
8628 
8629 	utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs;
8630 	dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr,
8631 			   hba->utrdl_dma_addr);
8632 
8633 	devm_kfree(hba->dev, hba->lrb);
8634 }
8635 
ufshcd_alloc_mcq(struct ufs_hba * hba)8636 static int ufshcd_alloc_mcq(struct ufs_hba *hba)
8637 {
8638 	int ret;
8639 	int old_nutrs = hba->nutrs;
8640 
8641 	ret = ufshcd_mcq_decide_queue_depth(hba);
8642 	if (ret < 0)
8643 		return ret;
8644 
8645 	hba->nutrs = ret;
8646 	ret = ufshcd_mcq_init(hba);
8647 	if (ret)
8648 		goto err;
8649 
8650 	/*
8651 	 * Previously allocated memory for nutrs may not be enough in MCQ mode.
8652 	 * Number of supported tags in MCQ mode may be larger than SDB mode.
8653 	 */
8654 	if (hba->nutrs != old_nutrs) {
8655 		ufshcd_release_sdb_queue(hba, old_nutrs);
8656 		ret = ufshcd_memory_alloc(hba);
8657 		if (ret)
8658 			goto err;
8659 		ufshcd_host_memory_configure(hba);
8660 	}
8661 
8662 	ret = ufshcd_mcq_memory_alloc(hba);
8663 	if (ret)
8664 		goto err;
8665 
8666 	hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
8667 	hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED;
8668 
8669 	return 0;
8670 err:
8671 	hba->nutrs = old_nutrs;
8672 	return ret;
8673 }
8674 
ufshcd_config_mcq(struct ufs_hba * hba)8675 static void ufshcd_config_mcq(struct ufs_hba *hba)
8676 {
8677 	int ret;
8678 	u32 intrs;
8679 
8680 	ret = ufshcd_mcq_vops_config_esi(hba);
8681 	dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
8682 
8683 	intrs = UFSHCD_ENABLE_MCQ_INTRS;
8684 	if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
8685 		intrs &= ~MCQ_CQ_EVENT_STATUS;
8686 	ufshcd_enable_intr(hba, intrs);
8687 	ufshcd_mcq_make_queues_operational(hba);
8688 	ufshcd_mcq_config_mac(hba, hba->nutrs);
8689 
8690 	dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
8691 		 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT],
8692 		 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL],
8693 		 hba->nutrs);
8694 }
8695 
ufshcd_post_device_init(struct ufs_hba * hba)8696 static int ufshcd_post_device_init(struct ufs_hba *hba)
8697 {
8698 	int ret;
8699 
8700 	ufshcd_tune_unipro_params(hba);
8701 
8702 	/* UFS device is also active now */
8703 	ufshcd_set_ufs_dev_active(hba);
8704 	ufshcd_force_reset_auto_bkops(hba);
8705 
8706 	ufshcd_set_timestamp_attr(hba);
8707 
8708 	if (!hba->max_pwr_info.is_valid)
8709 		return 0;
8710 
8711 	/*
8712 	 * Set the right value to bRefClkFreq before attempting to
8713 	 * switch to HS gears.
8714 	 */
8715 	if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8716 		ufshcd_set_dev_ref_clk(hba);
8717 	/* Gear up to HS gear. */
8718 	ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8719 	if (ret) {
8720 		dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8721 			__func__, ret);
8722 		return ret;
8723 	}
8724 
8725 	return 0;
8726 }
8727 
ufshcd_device_init(struct ufs_hba * hba,bool init_dev_params)8728 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
8729 {
8730 	int ret;
8731 
8732 	WARN_ON_ONCE(!hba->scsi_host_added);
8733 
8734 	hba->ufshcd_state = UFSHCD_STATE_RESET;
8735 
8736 	ret = ufshcd_link_startup(hba);
8737 	if (ret)
8738 		return ret;
8739 
8740 	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8741 		return ret;
8742 
8743 	/* Debug counters initialization */
8744 	ufshcd_clear_dbg_ufs_stats(hba);
8745 
8746 	/* UniPro link is active now */
8747 	ufshcd_set_link_active(hba);
8748 
8749 	/* Reconfigure MCQ upon reset */
8750 	if (hba->mcq_enabled && !init_dev_params) {
8751 		ufshcd_config_mcq(hba);
8752 		ufshcd_mcq_enable(hba);
8753 	}
8754 
8755 	/* Verify device initialization by sending NOP OUT UPIU */
8756 	ret = ufshcd_verify_dev_init(hba);
8757 	if (ret)
8758 		return ret;
8759 
8760 	/* Initiate UFS initialization, and waiting until completion */
8761 	ret = ufshcd_complete_dev_init(hba);
8762 	if (ret)
8763 		return ret;
8764 
8765 	/*
8766 	 * Initialize UFS device parameters used by driver, these
8767 	 * parameters are associated with UFS descriptors.
8768 	 */
8769 	if (init_dev_params) {
8770 		ret = ufshcd_device_params_init(hba);
8771 		if (ret)
8772 			return ret;
8773 		if (is_mcq_supported(hba) &&
8774 		    hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) {
8775 			ufshcd_config_mcq(hba);
8776 			ufshcd_mcq_enable(hba);
8777 		}
8778 	}
8779 
8780 	return ufshcd_post_device_init(hba);
8781 }
8782 
8783 /**
8784  * ufshcd_probe_hba - probe hba to detect device and initialize it
8785  * @hba: per-adapter instance
8786  * @init_dev_params: whether or not to call ufshcd_device_params_init().
8787  *
8788  * Execute link-startup and verify device initialization
8789  *
8790  * Return: 0 upon success; < 0 upon failure.
8791  */
ufshcd_probe_hba(struct ufs_hba * hba,bool init_dev_params)8792 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8793 {
8794 	int ret;
8795 
8796 	if (!hba->pm_op_in_progress &&
8797 	    (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) {
8798 		/* Reset the device and controller before doing reinit */
8799 		ufshcd_device_reset(hba);
8800 		ufs_put_device_desc(hba);
8801 		ufshcd_hba_stop(hba);
8802 		ret = ufshcd_hba_enable(hba);
8803 		if (ret) {
8804 			dev_err(hba->dev, "Host controller enable failed\n");
8805 			ufshcd_print_evt_hist(hba);
8806 			ufshcd_print_host_state(hba);
8807 			return ret;
8808 		}
8809 
8810 		/* Reinit the device */
8811 		ret = ufshcd_device_init(hba, init_dev_params);
8812 		if (ret)
8813 			return ret;
8814 	}
8815 
8816 	ufshcd_print_pwr_info(hba);
8817 
8818 	/*
8819 	 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8820 	 * and for removable UFS card as well, hence always set the parameter.
8821 	 * Note: Error handler may issue the device reset hence resetting
8822 	 * bActiveICCLevel as well so it is always safe to set this here.
8823 	 */
8824 	ufshcd_set_active_icc_lvl(hba);
8825 
8826 	/* Enable UFS Write Booster if supported */
8827 	ufshcd_configure_wb(hba);
8828 
8829 	if (hba->ee_usr_mask)
8830 		ufshcd_write_ee_control(hba);
8831 	ufshcd_configure_auto_hibern8(hba);
8832 
8833 	return 0;
8834 }
8835 
8836 /**
8837  * ufshcd_async_scan - asynchronous execution for probing hba
8838  * @data: data pointer to pass to this function
8839  * @cookie: cookie data
8840  */
ufshcd_async_scan(void * data,async_cookie_t cookie)8841 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8842 {
8843 	struct ufs_hba *hba = (struct ufs_hba *)data;
8844 	ktime_t probe_start;
8845 	int ret;
8846 
8847 	down(&hba->host_sem);
8848 	/* Initialize hba, detect and initialize UFS device */
8849 	probe_start = ktime_get();
8850 	ret = ufshcd_probe_hba(hba, true);
8851 	ufshcd_process_probe_result(hba, probe_start, ret);
8852 	up(&hba->host_sem);
8853 	if (ret)
8854 		goto out;
8855 
8856 	/* Probe and add UFS logical units  */
8857 	ret = ufshcd_add_lus(hba);
8858 
8859 out:
8860 	pm_runtime_put_sync(hba->dev);
8861 
8862 	if (ret)
8863 		dev_err(hba->dev, "%s failed: %d\n", __func__, ret);
8864 }
8865 
ufshcd_eh_timed_out(struct scsi_cmnd * scmd)8866 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
8867 {
8868 	struct ufs_hba *hba = shost_priv(scmd->device->host);
8869 
8870 	if (!hba->system_suspending) {
8871 		/* Activate the error handler in the SCSI core. */
8872 		return SCSI_EH_NOT_HANDLED;
8873 	}
8874 
8875 	/*
8876 	 * If we get here we know that no TMFs are outstanding and also that
8877 	 * the only pending command is a START STOP UNIT command. Handle the
8878 	 * timeout of that command directly to prevent a deadlock between
8879 	 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
8880 	 */
8881 	ufshcd_link_recovery(hba);
8882 	dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
8883 		 __func__, hba->outstanding_tasks);
8884 
8885 	return scsi_host_busy(hba->host) ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
8886 }
8887 
8888 static const struct attribute_group *ufshcd_driver_groups[] = {
8889 	&ufs_sysfs_unit_descriptor_group,
8890 	&ufs_sysfs_lun_attributes_group,
8891 	NULL,
8892 };
8893 
8894 static struct ufs_hba_variant_params ufs_hba_vps = {
8895 	.hba_enable_delay_us		= 1000,
8896 	.wb_flush_threshold		= UFS_WB_BUF_REMAIN_PERCENT(40),
8897 	.devfreq_profile.polling_ms	= 100,
8898 	.devfreq_profile.target		= ufshcd_devfreq_target,
8899 	.devfreq_profile.get_dev_status	= ufshcd_devfreq_get_dev_status,
8900 	.ondemand_data.upthreshold	= 70,
8901 	.ondemand_data.downdifferential	= 5,
8902 };
8903 
8904 static const struct scsi_host_template ufshcd_driver_template = {
8905 	.module			= THIS_MODULE,
8906 	.name			= UFSHCD,
8907 	.proc_name		= UFSHCD,
8908 	.map_queues		= ufshcd_map_queues,
8909 	.queuecommand		= ufshcd_queuecommand,
8910 	.mq_poll		= ufshcd_poll,
8911 	.sdev_init		= ufshcd_sdev_init,
8912 	.sdev_configure		= ufshcd_sdev_configure,
8913 	.sdev_destroy		= ufshcd_sdev_destroy,
8914 	.change_queue_depth	= ufshcd_change_queue_depth,
8915 	.eh_abort_handler	= ufshcd_abort,
8916 	.eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8917 	.eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
8918 	.eh_timed_out		= ufshcd_eh_timed_out,
8919 	.this_id		= -1,
8920 	.sg_tablesize		= SG_ALL,
8921 	.max_segment_size	= PRDT_DATA_BYTE_COUNT_MAX,
8922 	.max_sectors		= SZ_1M / SECTOR_SIZE,
8923 	.max_host_blocked	= 1,
8924 	.track_queue_depth	= 1,
8925 	.skip_settle_delay	= 1,
8926 	.sdev_groups		= ufshcd_driver_groups,
8927 };
8928 
ufshcd_config_vreg_load(struct device * dev,struct ufs_vreg * vreg,int ua)8929 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8930 				   int ua)
8931 {
8932 	int ret;
8933 
8934 	if (!vreg)
8935 		return 0;
8936 
8937 	/*
8938 	 * "set_load" operation shall be required on those regulators
8939 	 * which specifically configured current limitation. Otherwise
8940 	 * zero max_uA may cause unexpected behavior when regulator is
8941 	 * enabled or set as high power mode.
8942 	 */
8943 	if (!vreg->max_uA)
8944 		return 0;
8945 
8946 	ret = regulator_set_load(vreg->reg, ua);
8947 	if (ret < 0) {
8948 		dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8949 				__func__, vreg->name, ua, ret);
8950 	}
8951 
8952 	return ret;
8953 }
8954 
ufshcd_config_vreg_lpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8955 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8956 					 struct ufs_vreg *vreg)
8957 {
8958 	return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8959 }
8960 
ufshcd_config_vreg_hpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8961 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8962 					 struct ufs_vreg *vreg)
8963 {
8964 	if (!vreg)
8965 		return 0;
8966 
8967 	return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8968 }
8969 
ufshcd_config_vreg(struct device * dev,struct ufs_vreg * vreg,bool on)8970 static int ufshcd_config_vreg(struct device *dev,
8971 		struct ufs_vreg *vreg, bool on)
8972 {
8973 	if (regulator_count_voltages(vreg->reg) <= 0)
8974 		return 0;
8975 
8976 	return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
8977 }
8978 
ufshcd_enable_vreg(struct device * dev,struct ufs_vreg * vreg)8979 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8980 {
8981 	int ret = 0;
8982 
8983 	if (!vreg || vreg->enabled)
8984 		goto out;
8985 
8986 	ret = ufshcd_config_vreg(dev, vreg, true);
8987 	if (!ret)
8988 		ret = regulator_enable(vreg->reg);
8989 
8990 	if (!ret)
8991 		vreg->enabled = true;
8992 	else
8993 		dev_err(dev, "%s: %s enable failed, err=%d\n",
8994 				__func__, vreg->name, ret);
8995 out:
8996 	return ret;
8997 }
8998 
ufshcd_disable_vreg(struct device * dev,struct ufs_vreg * vreg)8999 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
9000 {
9001 	int ret = 0;
9002 
9003 	if (!vreg || !vreg->enabled || vreg->always_on)
9004 		goto out;
9005 
9006 	ret = regulator_disable(vreg->reg);
9007 
9008 	if (!ret) {
9009 		/* ignore errors on applying disable config */
9010 		ufshcd_config_vreg(dev, vreg, false);
9011 		vreg->enabled = false;
9012 	} else {
9013 		dev_err(dev, "%s: %s disable failed, err=%d\n",
9014 				__func__, vreg->name, ret);
9015 	}
9016 out:
9017 	return ret;
9018 }
9019 
ufshcd_setup_vreg(struct ufs_hba * hba,bool on)9020 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
9021 {
9022 	int ret = 0;
9023 	struct device *dev = hba->dev;
9024 	struct ufs_vreg_info *info = &hba->vreg_info;
9025 
9026 	ret = ufshcd_toggle_vreg(dev, info->vcc, on);
9027 	if (ret)
9028 		goto out;
9029 
9030 	ret = ufshcd_toggle_vreg(dev, info->vccq, on);
9031 	if (ret)
9032 		goto out;
9033 
9034 	ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
9035 
9036 out:
9037 	if (ret) {
9038 		ufshcd_toggle_vreg(dev, info->vccq2, false);
9039 		ufshcd_toggle_vreg(dev, info->vccq, false);
9040 		ufshcd_toggle_vreg(dev, info->vcc, false);
9041 	}
9042 	return ret;
9043 }
9044 
ufshcd_setup_hba_vreg(struct ufs_hba * hba,bool on)9045 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
9046 {
9047 	struct ufs_vreg_info *info = &hba->vreg_info;
9048 
9049 	return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
9050 }
9051 
ufshcd_get_vreg(struct device * dev,struct ufs_vreg * vreg)9052 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
9053 {
9054 	int ret = 0;
9055 
9056 	if (!vreg)
9057 		goto out;
9058 
9059 	vreg->reg = devm_regulator_get(dev, vreg->name);
9060 	if (IS_ERR(vreg->reg)) {
9061 		ret = PTR_ERR(vreg->reg);
9062 		dev_err(dev, "%s: %s get failed, err=%d\n",
9063 				__func__, vreg->name, ret);
9064 	}
9065 out:
9066 	return ret;
9067 }
9068 EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
9069 
ufshcd_init_vreg(struct ufs_hba * hba)9070 static int ufshcd_init_vreg(struct ufs_hba *hba)
9071 {
9072 	int ret = 0;
9073 	struct device *dev = hba->dev;
9074 	struct ufs_vreg_info *info = &hba->vreg_info;
9075 
9076 	ret = ufshcd_get_vreg(dev, info->vcc);
9077 	if (ret)
9078 		goto out;
9079 
9080 	ret = ufshcd_get_vreg(dev, info->vccq);
9081 	if (!ret)
9082 		ret = ufshcd_get_vreg(dev, info->vccq2);
9083 out:
9084 	return ret;
9085 }
9086 
ufshcd_init_hba_vreg(struct ufs_hba * hba)9087 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
9088 {
9089 	struct ufs_vreg_info *info = &hba->vreg_info;
9090 
9091 	return ufshcd_get_vreg(hba->dev, info->vdd_hba);
9092 }
9093 
ufshcd_setup_clocks(struct ufs_hba * hba,bool on)9094 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
9095 {
9096 	int ret = 0;
9097 	struct ufs_clk_info *clki;
9098 	struct list_head *head = &hba->clk_list_head;
9099 	ktime_t start = ktime_get();
9100 	bool clk_state_changed = false;
9101 
9102 	if (list_empty(head))
9103 		goto out;
9104 
9105 	ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
9106 	if (ret)
9107 		return ret;
9108 
9109 	list_for_each_entry(clki, head, list) {
9110 		if (!IS_ERR_OR_NULL(clki->clk)) {
9111 			/*
9112 			 * Don't disable clocks which are needed
9113 			 * to keep the link active.
9114 			 */
9115 			if (ufshcd_is_link_active(hba) &&
9116 			    clki->keep_link_active)
9117 				continue;
9118 
9119 			clk_state_changed = on ^ clki->enabled;
9120 			if (on && !clki->enabled) {
9121 				ret = clk_prepare_enable(clki->clk);
9122 				if (ret) {
9123 					dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
9124 						__func__, clki->name, ret);
9125 					goto out;
9126 				}
9127 			} else if (!on && clki->enabled) {
9128 				clk_disable_unprepare(clki->clk);
9129 			}
9130 			clki->enabled = on;
9131 			dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
9132 					clki->name, on ? "en" : "dis");
9133 		}
9134 	}
9135 
9136 	ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
9137 	if (ret)
9138 		return ret;
9139 
9140 	if (!ufshcd_is_clkscaling_supported(hba))
9141 		ufshcd_pm_qos_update(hba, on);
9142 out:
9143 	if (ret) {
9144 		list_for_each_entry(clki, head, list) {
9145 			if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
9146 				clk_disable_unprepare(clki->clk);
9147 		}
9148 	} else if (!ret && on && hba->clk_gating.is_initialized) {
9149 		scoped_guard(spinlock_irqsave, &hba->clk_gating.lock)
9150 			hba->clk_gating.state = CLKS_ON;
9151 		trace_ufshcd_clk_gating(dev_name(hba->dev),
9152 					hba->clk_gating.state);
9153 	}
9154 
9155 	if (clk_state_changed)
9156 		trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
9157 			(on ? "on" : "off"),
9158 			ktime_to_us(ktime_sub(ktime_get(), start)), ret);
9159 	return ret;
9160 }
9161 
ufshcd_parse_ref_clk_property(struct ufs_hba * hba)9162 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
9163 {
9164 	u32 freq;
9165 	int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq);
9166 
9167 	if (ret) {
9168 		dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
9169 		return REF_CLK_FREQ_INVAL;
9170 	}
9171 
9172 	return ufs_get_bref_clk_from_hz(freq);
9173 }
9174 
ufshcd_init_clocks(struct ufs_hba * hba)9175 static int ufshcd_init_clocks(struct ufs_hba *hba)
9176 {
9177 	int ret = 0;
9178 	struct ufs_clk_info *clki;
9179 	struct device *dev = hba->dev;
9180 	struct list_head *head = &hba->clk_list_head;
9181 
9182 	if (list_empty(head))
9183 		goto out;
9184 
9185 	list_for_each_entry(clki, head, list) {
9186 		if (!clki->name)
9187 			continue;
9188 
9189 		clki->clk = devm_clk_get(dev, clki->name);
9190 		if (IS_ERR(clki->clk)) {
9191 			ret = PTR_ERR(clki->clk);
9192 			dev_err(dev, "%s: %s clk get failed, %d\n",
9193 					__func__, clki->name, ret);
9194 			goto out;
9195 		}
9196 
9197 		/*
9198 		 * Parse device ref clk freq as per device tree "ref_clk".
9199 		 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
9200 		 * in ufshcd_alloc_host().
9201 		 */
9202 		if (!strcmp(clki->name, "ref_clk"))
9203 			ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
9204 
9205 		if (clki->max_freq) {
9206 			ret = clk_set_rate(clki->clk, clki->max_freq);
9207 			if (ret) {
9208 				dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
9209 					__func__, clki->name,
9210 					clki->max_freq, ret);
9211 				goto out;
9212 			}
9213 			clki->curr_freq = clki->max_freq;
9214 		}
9215 		dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
9216 				clki->name, clk_get_rate(clki->clk));
9217 	}
9218 
9219 	/* Set Max. frequency for all clocks */
9220 	if (hba->use_pm_opp) {
9221 		ret = ufshcd_opp_set_rate(hba, ULONG_MAX);
9222 		if (ret) {
9223 			dev_err(hba->dev, "%s: failed to set OPP: %d", __func__,
9224 				ret);
9225 			goto out;
9226 		}
9227 	}
9228 
9229 out:
9230 	return ret;
9231 }
9232 
ufshcd_variant_hba_init(struct ufs_hba * hba)9233 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
9234 {
9235 	int err = 0;
9236 
9237 	if (!hba->vops)
9238 		goto out;
9239 
9240 	err = ufshcd_vops_init(hba);
9241 	if (err)
9242 		dev_err_probe(hba->dev, err,
9243 			      "%s: variant %s init failed with err %d\n",
9244 			      __func__, ufshcd_get_var_name(hba), err);
9245 out:
9246 	return err;
9247 }
9248 
ufshcd_variant_hba_exit(struct ufs_hba * hba)9249 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
9250 {
9251 	if (!hba->vops)
9252 		return;
9253 
9254 	ufshcd_vops_exit(hba);
9255 }
9256 
ufshcd_hba_init(struct ufs_hba * hba)9257 static int ufshcd_hba_init(struct ufs_hba *hba)
9258 {
9259 	int err;
9260 
9261 	/*
9262 	 * Handle host controller power separately from the UFS device power
9263 	 * rails as it will help controlling the UFS host controller power
9264 	 * collapse easily which is different than UFS device power collapse.
9265 	 * Also, enable the host controller power before we go ahead with rest
9266 	 * of the initialization here.
9267 	 */
9268 	err = ufshcd_init_hba_vreg(hba);
9269 	if (err)
9270 		goto out;
9271 
9272 	err = ufshcd_setup_hba_vreg(hba, true);
9273 	if (err)
9274 		goto out;
9275 
9276 	err = ufshcd_init_clocks(hba);
9277 	if (err)
9278 		goto out_disable_hba_vreg;
9279 
9280 	if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
9281 		hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
9282 
9283 	err = ufshcd_setup_clocks(hba, true);
9284 	if (err)
9285 		goto out_disable_hba_vreg;
9286 
9287 	err = ufshcd_init_vreg(hba);
9288 	if (err)
9289 		goto out_disable_clks;
9290 
9291 	err = ufshcd_setup_vreg(hba, true);
9292 	if (err)
9293 		goto out_disable_clks;
9294 
9295 	err = ufshcd_variant_hba_init(hba);
9296 	if (err)
9297 		goto out_disable_vreg;
9298 
9299 	ufs_debugfs_hba_init(hba);
9300 	ufs_fault_inject_hba_init(hba);
9301 
9302 	hba->is_powered = true;
9303 	goto out;
9304 
9305 out_disable_vreg:
9306 	ufshcd_setup_vreg(hba, false);
9307 out_disable_clks:
9308 	ufshcd_setup_clocks(hba, false);
9309 out_disable_hba_vreg:
9310 	ufshcd_setup_hba_vreg(hba, false);
9311 out:
9312 	return err;
9313 }
9314 
ufshcd_hba_exit(struct ufs_hba * hba)9315 static void ufshcd_hba_exit(struct ufs_hba *hba)
9316 {
9317 	if (hba->is_powered) {
9318 		ufshcd_pm_qos_exit(hba);
9319 		ufshcd_exit_clk_scaling(hba);
9320 		ufshcd_exit_clk_gating(hba);
9321 		if (hba->eh_wq)
9322 			destroy_workqueue(hba->eh_wq);
9323 		ufs_debugfs_hba_exit(hba);
9324 		ufshcd_variant_hba_exit(hba);
9325 		ufshcd_setup_vreg(hba, false);
9326 		ufshcd_setup_clocks(hba, false);
9327 		ufshcd_setup_hba_vreg(hba, false);
9328 		hba->is_powered = false;
9329 		ufs_put_device_desc(hba);
9330 	}
9331 }
9332 
ufshcd_execute_start_stop(struct scsi_device * sdev,enum ufs_dev_pwr_mode pwr_mode,struct scsi_sense_hdr * sshdr)9333 static int ufshcd_execute_start_stop(struct scsi_device *sdev,
9334 				     enum ufs_dev_pwr_mode pwr_mode,
9335 				     struct scsi_sense_hdr *sshdr)
9336 {
9337 	const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
9338 	struct scsi_failure failure_defs[] = {
9339 		{
9340 			.allowed = 2,
9341 			.result = SCMD_FAILURE_RESULT_ANY,
9342 		},
9343 	};
9344 	struct scsi_failures failures = {
9345 		.failure_definitions = failure_defs,
9346 	};
9347 	const struct scsi_exec_args args = {
9348 		.failures = &failures,
9349 		.sshdr = sshdr,
9350 		.req_flags = BLK_MQ_REQ_PM,
9351 		.scmd_flags = SCMD_FAIL_IF_RECOVERING,
9352 	};
9353 
9354 	return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL,
9355 			/*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0,
9356 			&args);
9357 }
9358 
9359 /**
9360  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
9361  *			     power mode
9362  * @hba: per adapter instance
9363  * @pwr_mode: device power mode to set
9364  *
9365  * Return: 0 if requested power mode is set successfully;
9366  *         < 0 if failed to set the requested power mode.
9367  */
ufshcd_set_dev_pwr_mode(struct ufs_hba * hba,enum ufs_dev_pwr_mode pwr_mode)9368 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
9369 				     enum ufs_dev_pwr_mode pwr_mode)
9370 {
9371 	struct scsi_sense_hdr sshdr;
9372 	struct scsi_device *sdp;
9373 	unsigned long flags;
9374 	int ret;
9375 
9376 	spin_lock_irqsave(hba->host->host_lock, flags);
9377 	sdp = hba->ufs_device_wlun;
9378 	if (sdp && scsi_device_online(sdp))
9379 		ret = scsi_device_get(sdp);
9380 	else
9381 		ret = -ENODEV;
9382 	spin_unlock_irqrestore(hba->host->host_lock, flags);
9383 
9384 	if (ret)
9385 		return ret;
9386 
9387 	/*
9388 	 * If scsi commands fail, the scsi mid-layer schedules scsi error-
9389 	 * handling, which would wait for host to be resumed. Since we know
9390 	 * we are functional while we are here, skip host resume in error
9391 	 * handling context.
9392 	 */
9393 	hba->host->eh_noresume = 1;
9394 
9395 	/*
9396 	 * Current function would be generally called from the power management
9397 	 * callbacks hence set the RQF_PM flag so that it doesn't resume the
9398 	 * already suspended childs.
9399 	 */
9400 	ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr);
9401 	if (ret) {
9402 		sdev_printk(KERN_WARNING, sdp,
9403 			    "START_STOP failed for power mode: %d, result %x\n",
9404 			    pwr_mode, ret);
9405 		if (ret > 0) {
9406 			if (scsi_sense_valid(&sshdr))
9407 				scsi_print_sense_hdr(sdp, NULL, &sshdr);
9408 			ret = -EIO;
9409 		}
9410 	} else {
9411 		hba->curr_dev_pwr_mode = pwr_mode;
9412 	}
9413 
9414 	scsi_device_put(sdp);
9415 	hba->host->eh_noresume = 0;
9416 	return ret;
9417 }
9418 
ufshcd_link_state_transition(struct ufs_hba * hba,enum uic_link_state req_link_state,bool check_for_bkops)9419 static int ufshcd_link_state_transition(struct ufs_hba *hba,
9420 					enum uic_link_state req_link_state,
9421 					bool check_for_bkops)
9422 {
9423 	int ret = 0;
9424 
9425 	if (req_link_state == hba->uic_link_state)
9426 		return 0;
9427 
9428 	if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9429 		ret = ufshcd_uic_hibern8_enter(hba);
9430 		if (!ret) {
9431 			ufshcd_set_link_hibern8(hba);
9432 		} else {
9433 			dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9434 					__func__, ret);
9435 			goto out;
9436 		}
9437 	}
9438 	/*
9439 	 * If autobkops is enabled, link can't be turned off because
9440 	 * turning off the link would also turn off the device, except in the
9441 	 * case of DeepSleep where the device is expected to remain powered.
9442 	 */
9443 	else if ((req_link_state == UIC_LINK_OFF_STATE) &&
9444 		 (!check_for_bkops || !hba->auto_bkops_enabled)) {
9445 		/*
9446 		 * Let's make sure that link is in low power mode, we are doing
9447 		 * this currently by putting the link in Hibern8. Otherway to
9448 		 * put the link in low power mode is to send the DME end point
9449 		 * to device and then send the DME reset command to local
9450 		 * unipro. But putting the link in hibern8 is much faster.
9451 		 *
9452 		 * Note also that putting the link in Hibern8 is a requirement
9453 		 * for entering DeepSleep.
9454 		 */
9455 		ret = ufshcd_uic_hibern8_enter(hba);
9456 		if (ret) {
9457 			dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9458 					__func__, ret);
9459 			goto out;
9460 		}
9461 		/*
9462 		 * Change controller state to "reset state" which
9463 		 * should also put the link in off/reset state
9464 		 */
9465 		ufshcd_hba_stop(hba);
9466 		/*
9467 		 * TODO: Check if we need any delay to make sure that
9468 		 * controller is reset
9469 		 */
9470 		ufshcd_set_link_off(hba);
9471 	}
9472 
9473 out:
9474 	return ret;
9475 }
9476 
ufshcd_vreg_set_lpm(struct ufs_hba * hba)9477 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9478 {
9479 	bool vcc_off = false;
9480 
9481 	/*
9482 	 * It seems some UFS devices may keep drawing more than sleep current
9483 	 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
9484 	 * To avoid this situation, add 2ms delay before putting these UFS
9485 	 * rails in LPM mode.
9486 	 */
9487 	if (!ufshcd_is_link_active(hba) &&
9488 	    hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9489 		usleep_range(2000, 2100);
9490 
9491 	/*
9492 	 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
9493 	 * power.
9494 	 *
9495 	 * If UFS device and link is in OFF state, all power supplies (VCC,
9496 	 * VCCQ, VCCQ2) can be turned off if power on write protect is not
9497 	 * required. If UFS link is inactive (Hibern8 or OFF state) and device
9498 	 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9499 	 *
9500 	 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9501 	 * in low power state which would save some power.
9502 	 *
9503 	 * If Write Booster is enabled and the device needs to flush the WB
9504 	 * buffer OR if bkops status is urgent for WB, keep Vcc on.
9505 	 */
9506 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9507 	    !hba->dev_info.is_lu_power_on_wp) {
9508 		ufshcd_setup_vreg(hba, false);
9509 		vcc_off = true;
9510 	} else if (!ufshcd_is_ufs_dev_active(hba)) {
9511 		ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9512 		vcc_off = true;
9513 		if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
9514 			ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9515 			ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
9516 		}
9517 	}
9518 
9519 	/*
9520 	 * Some UFS devices require delay after VCC power rail is turned-off.
9521 	 */
9522 	if (vcc_off && hba->vreg_info.vcc &&
9523 		hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
9524 		usleep_range(5000, 5100);
9525 }
9526 
9527 #ifdef CONFIG_PM
ufshcd_vreg_set_hpm(struct ufs_hba * hba)9528 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9529 {
9530 	int ret = 0;
9531 
9532 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9533 	    !hba->dev_info.is_lu_power_on_wp) {
9534 		ret = ufshcd_setup_vreg(hba, true);
9535 	} else if (!ufshcd_is_ufs_dev_active(hba)) {
9536 		if (!ufshcd_is_link_active(hba)) {
9537 			ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
9538 			if (ret)
9539 				goto vcc_disable;
9540 			ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
9541 			if (ret)
9542 				goto vccq_lpm;
9543 		}
9544 		ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
9545 	}
9546 	goto out;
9547 
9548 vccq_lpm:
9549 	ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9550 vcc_disable:
9551 	ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9552 out:
9553 	return ret;
9554 }
9555 #endif /* CONFIG_PM */
9556 
ufshcd_hba_vreg_set_lpm(struct ufs_hba * hba)9557 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9558 {
9559 	if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9560 		ufshcd_setup_hba_vreg(hba, false);
9561 }
9562 
ufshcd_hba_vreg_set_hpm(struct ufs_hba * hba)9563 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9564 {
9565 	if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9566 		ufshcd_setup_hba_vreg(hba, true);
9567 }
9568 
__ufshcd_wl_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)9569 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9570 {
9571 	int ret = 0;
9572 	bool check_for_bkops;
9573 	enum ufs_pm_level pm_lvl;
9574 	enum ufs_dev_pwr_mode req_dev_pwr_mode;
9575 	enum uic_link_state req_link_state;
9576 
9577 	hba->pm_op_in_progress = true;
9578 	if (pm_op != UFS_SHUTDOWN_PM) {
9579 		pm_lvl = pm_op == UFS_RUNTIME_PM ?
9580 			 hba->rpm_lvl : hba->spm_lvl;
9581 		req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
9582 		req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
9583 	} else {
9584 		req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9585 		req_link_state = UIC_LINK_OFF_STATE;
9586 	}
9587 
9588 	/*
9589 	 * If we can't transition into any of the low power modes
9590 	 * just gate the clocks.
9591 	 */
9592 	ufshcd_hold(hba);
9593 	hba->clk_gating.is_suspended = true;
9594 
9595 	if (ufshcd_is_clkscaling_supported(hba))
9596 		ufshcd_clk_scaling_suspend(hba, true);
9597 
9598 	if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9599 			req_link_state == UIC_LINK_ACTIVE_STATE) {
9600 		goto vops_suspend;
9601 	}
9602 
9603 	if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
9604 	    (req_link_state == hba->uic_link_state))
9605 		goto enable_scaling;
9606 
9607 	/* UFS device & link must be active before we enter in this function */
9608 	if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
9609 		/*  Wait err handler finish or trigger err recovery */
9610 		if (!ufshcd_eh_in_progress(hba))
9611 			ufshcd_force_error_recovery(hba);
9612 		ret = -EBUSY;
9613 		goto enable_scaling;
9614 	}
9615 
9616 	if (pm_op == UFS_RUNTIME_PM) {
9617 		if (ufshcd_can_autobkops_during_suspend(hba)) {
9618 			/*
9619 			 * The device is idle with no requests in the queue,
9620 			 * allow background operations if bkops status shows
9621 			 * that performance might be impacted.
9622 			 */
9623 			ret = ufshcd_bkops_ctrl(hba);
9624 			if (ret) {
9625 				/*
9626 				 * If return err in suspend flow, IO will hang.
9627 				 * Trigger error handler and break suspend for
9628 				 * error recovery.
9629 				 */
9630 				ufshcd_force_error_recovery(hba);
9631 				ret = -EBUSY;
9632 				goto enable_scaling;
9633 			}
9634 		} else {
9635 			/* make sure that auto bkops is disabled */
9636 			ufshcd_disable_auto_bkops(hba);
9637 		}
9638 		/*
9639 		 * If device needs to do BKOP or WB buffer flush during
9640 		 * Hibern8, keep device power mode as "active power mode"
9641 		 * and VCC supply.
9642 		 */
9643 		hba->dev_info.b_rpm_dev_flush_capable =
9644 			hba->auto_bkops_enabled ||
9645 			(((req_link_state == UIC_LINK_HIBERN8_STATE) ||
9646 			((req_link_state == UIC_LINK_ACTIVE_STATE) &&
9647 			ufshcd_is_auto_hibern8_enabled(hba))) &&
9648 			ufshcd_wb_need_flush(hba));
9649 	}
9650 
9651 	flush_work(&hba->eeh_work);
9652 
9653 	ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9654 	if (ret)
9655 		goto enable_scaling;
9656 
9657 	if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
9658 		if (pm_op != UFS_RUNTIME_PM)
9659 			/* ensure that bkops is disabled */
9660 			ufshcd_disable_auto_bkops(hba);
9661 
9662 		if (!hba->dev_info.b_rpm_dev_flush_capable) {
9663 			ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9664 			if (ret && pm_op != UFS_SHUTDOWN_PM) {
9665 				/*
9666 				 * If return err in suspend flow, IO will hang.
9667 				 * Trigger error handler and break suspend for
9668 				 * error recovery.
9669 				 */
9670 				ufshcd_force_error_recovery(hba);
9671 				ret = -EBUSY;
9672 			}
9673 			if (ret)
9674 				goto enable_scaling;
9675 		}
9676 	}
9677 
9678 	/*
9679 	 * In the case of DeepSleep, the device is expected to remain powered
9680 	 * with the link off, so do not check for bkops.
9681 	 */
9682 	check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9683 	ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
9684 	if (ret && pm_op != UFS_SHUTDOWN_PM) {
9685 		/*
9686 		 * If return err in suspend flow, IO will hang.
9687 		 * Trigger error handler and break suspend for
9688 		 * error recovery.
9689 		 */
9690 		ufshcd_force_error_recovery(hba);
9691 		ret = -EBUSY;
9692 	}
9693 	if (ret)
9694 		goto set_dev_active;
9695 
9696 vops_suspend:
9697 	/*
9698 	 * Call vendor specific suspend callback. As these callbacks may access
9699 	 * vendor specific host controller register space call them before the
9700 	 * host clocks are ON.
9701 	 */
9702 	ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9703 	if (ret)
9704 		goto set_link_active;
9705 
9706 	cancel_delayed_work_sync(&hba->ufs_rtc_update_work);
9707 	goto out;
9708 
9709 set_link_active:
9710 	/*
9711 	 * Device hardware reset is required to exit DeepSleep. Also, for
9712 	 * DeepSleep, the link is off so host reset and restore will be done
9713 	 * further below.
9714 	 */
9715 	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9716 		ufshcd_device_reset(hba);
9717 		WARN_ON(!ufshcd_is_link_off(hba));
9718 	}
9719 	if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9720 		ufshcd_set_link_active(hba);
9721 	else if (ufshcd_is_link_off(hba))
9722 		ufshcd_host_reset_and_restore(hba);
9723 set_dev_active:
9724 	/* Can also get here needing to exit DeepSleep */
9725 	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9726 		ufshcd_device_reset(hba);
9727 		ufshcd_host_reset_and_restore(hba);
9728 	}
9729 	if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9730 		ufshcd_disable_auto_bkops(hba);
9731 enable_scaling:
9732 	if (ufshcd_is_clkscaling_supported(hba))
9733 		ufshcd_clk_scaling_suspend(hba, false);
9734 
9735 	hba->dev_info.b_rpm_dev_flush_capable = false;
9736 out:
9737 	if (hba->dev_info.b_rpm_dev_flush_capable) {
9738 		schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9739 			msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9740 	}
9741 
9742 	if (ret) {
9743 		ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9744 		hba->clk_gating.is_suspended = false;
9745 		ufshcd_release(hba);
9746 	}
9747 	hba->pm_op_in_progress = false;
9748 	return ret;
9749 }
9750 
9751 #ifdef CONFIG_PM
__ufshcd_wl_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)9752 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9753 {
9754 	int ret;
9755 	enum uic_link_state old_link_state = hba->uic_link_state;
9756 
9757 	hba->pm_op_in_progress = true;
9758 
9759 	/*
9760 	 * Call vendor specific resume callback. As these callbacks may access
9761 	 * vendor specific host controller register space call them when the
9762 	 * host clocks are ON.
9763 	 */
9764 	ret = ufshcd_vops_resume(hba, pm_op);
9765 	if (ret)
9766 		goto out;
9767 
9768 	/* For DeepSleep, the only supported option is to have the link off */
9769 	WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9770 
9771 	if (ufshcd_is_link_hibern8(hba)) {
9772 		ret = ufshcd_uic_hibern8_exit(hba);
9773 		if (!ret) {
9774 			ufshcd_set_link_active(hba);
9775 		} else {
9776 			dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9777 					__func__, ret);
9778 			goto vendor_suspend;
9779 		}
9780 	} else if (ufshcd_is_link_off(hba)) {
9781 		/*
9782 		 * A full initialization of the host and the device is
9783 		 * required since the link was put to off during suspend.
9784 		 * Note, in the case of DeepSleep, the device will exit
9785 		 * DeepSleep due to device reset.
9786 		 */
9787 		ret = ufshcd_reset_and_restore(hba);
9788 		/*
9789 		 * ufshcd_reset_and_restore() should have already
9790 		 * set the link state as active
9791 		 */
9792 		if (ret || !ufshcd_is_link_active(hba))
9793 			goto vendor_suspend;
9794 	}
9795 
9796 	if (!ufshcd_is_ufs_dev_active(hba)) {
9797 		ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9798 		if (ret)
9799 			goto set_old_link_state;
9800 		ufshcd_set_timestamp_attr(hba);
9801 		schedule_delayed_work(&hba->ufs_rtc_update_work,
9802 				      msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS));
9803 	}
9804 
9805 	if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9806 		ufshcd_enable_auto_bkops(hba);
9807 	else
9808 		/*
9809 		 * If BKOPs operations are urgently needed at this moment then
9810 		 * keep auto-bkops enabled or else disable it.
9811 		 */
9812 		ufshcd_bkops_ctrl(hba);
9813 
9814 	if (hba->ee_usr_mask)
9815 		ufshcd_write_ee_control(hba);
9816 
9817 	if (ufshcd_is_clkscaling_supported(hba))
9818 		ufshcd_clk_scaling_suspend(hba, false);
9819 
9820 	if (hba->dev_info.b_rpm_dev_flush_capable) {
9821 		hba->dev_info.b_rpm_dev_flush_capable = false;
9822 		cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9823 	}
9824 
9825 	ufshcd_configure_auto_hibern8(hba);
9826 
9827 	goto out;
9828 
9829 set_old_link_state:
9830 	ufshcd_link_state_transition(hba, old_link_state, 0);
9831 vendor_suspend:
9832 	ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9833 	ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9834 out:
9835 	if (ret)
9836 		ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9837 	hba->clk_gating.is_suspended = false;
9838 	ufshcd_release(hba);
9839 	hba->pm_op_in_progress = false;
9840 	return ret;
9841 }
9842 
ufshcd_wl_runtime_suspend(struct device * dev)9843 static int ufshcd_wl_runtime_suspend(struct device *dev)
9844 {
9845 	struct scsi_device *sdev = to_scsi_device(dev);
9846 	struct ufs_hba *hba;
9847 	int ret;
9848 	ktime_t start = ktime_get();
9849 
9850 	hba = shost_priv(sdev->host);
9851 
9852 	ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9853 	if (ret)
9854 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9855 
9856 	trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9857 		ktime_to_us(ktime_sub(ktime_get(), start)),
9858 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9859 
9860 	return ret;
9861 }
9862 
ufshcd_wl_runtime_resume(struct device * dev)9863 static int ufshcd_wl_runtime_resume(struct device *dev)
9864 {
9865 	struct scsi_device *sdev = to_scsi_device(dev);
9866 	struct ufs_hba *hba;
9867 	int ret = 0;
9868 	ktime_t start = ktime_get();
9869 
9870 	hba = shost_priv(sdev->host);
9871 
9872 	ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9873 	if (ret)
9874 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9875 
9876 	trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9877 		ktime_to_us(ktime_sub(ktime_get(), start)),
9878 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9879 
9880 	return ret;
9881 }
9882 #endif
9883 
9884 #ifdef CONFIG_PM_SLEEP
ufshcd_wl_suspend(struct device * dev)9885 static int ufshcd_wl_suspend(struct device *dev)
9886 {
9887 	struct scsi_device *sdev = to_scsi_device(dev);
9888 	struct ufs_hba *hba;
9889 	int ret = 0;
9890 	ktime_t start = ktime_get();
9891 
9892 	hba = shost_priv(sdev->host);
9893 	down(&hba->host_sem);
9894 	hba->system_suspending = true;
9895 
9896 	if (pm_runtime_suspended(dev))
9897 		goto out;
9898 
9899 	ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9900 	if (ret) {
9901 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__,  ret);
9902 		up(&hba->host_sem);
9903 	}
9904 
9905 out:
9906 	if (!ret)
9907 		hba->is_sys_suspended = true;
9908 	trace_ufshcd_wl_suspend(dev_name(dev), ret,
9909 		ktime_to_us(ktime_sub(ktime_get(), start)),
9910 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9911 
9912 	return ret;
9913 }
9914 
ufshcd_wl_resume(struct device * dev)9915 static int ufshcd_wl_resume(struct device *dev)
9916 {
9917 	struct scsi_device *sdev = to_scsi_device(dev);
9918 	struct ufs_hba *hba;
9919 	int ret = 0;
9920 	ktime_t start = ktime_get();
9921 
9922 	hba = shost_priv(sdev->host);
9923 
9924 	if (pm_runtime_suspended(dev))
9925 		goto out;
9926 
9927 	ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9928 	if (ret)
9929 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9930 out:
9931 	trace_ufshcd_wl_resume(dev_name(dev), ret,
9932 		ktime_to_us(ktime_sub(ktime_get(), start)),
9933 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9934 	if (!ret)
9935 		hba->is_sys_suspended = false;
9936 	hba->system_suspending = false;
9937 	up(&hba->host_sem);
9938 	return ret;
9939 }
9940 #endif
9941 
9942 /**
9943  * ufshcd_suspend - helper function for suspend operations
9944  * @hba: per adapter instance
9945  *
9946  * This function will put disable irqs, turn off clocks
9947  * and set vreg and hba-vreg in lpm mode.
9948  *
9949  * Return: 0 upon success; < 0 upon failure.
9950  */
ufshcd_suspend(struct ufs_hba * hba)9951 static int ufshcd_suspend(struct ufs_hba *hba)
9952 {
9953 	int ret;
9954 
9955 	if (!hba->is_powered)
9956 		return 0;
9957 	/*
9958 	 * Disable the host irq as host controller as there won't be any
9959 	 * host controller transaction expected till resume.
9960 	 */
9961 	ufshcd_disable_irq(hba);
9962 	ret = ufshcd_setup_clocks(hba, false);
9963 	if (ret) {
9964 		ufshcd_enable_irq(hba);
9965 		return ret;
9966 	}
9967 	if (ufshcd_is_clkgating_allowed(hba)) {
9968 		hba->clk_gating.state = CLKS_OFF;
9969 		trace_ufshcd_clk_gating(dev_name(hba->dev),
9970 					hba->clk_gating.state);
9971 	}
9972 
9973 	ufshcd_vreg_set_lpm(hba);
9974 	/* Put the host controller in low power mode if possible */
9975 	ufshcd_hba_vreg_set_lpm(hba);
9976 	ufshcd_pm_qos_update(hba, false);
9977 	return ret;
9978 }
9979 
9980 #ifdef CONFIG_PM
9981 /**
9982  * ufshcd_resume - helper function for resume operations
9983  * @hba: per adapter instance
9984  *
9985  * This function basically turns on the regulators, clocks and
9986  * irqs of the hba.
9987  *
9988  * Return: 0 for success and non-zero for failure.
9989  */
ufshcd_resume(struct ufs_hba * hba)9990 static int ufshcd_resume(struct ufs_hba *hba)
9991 {
9992 	int ret;
9993 
9994 	if (!hba->is_powered)
9995 		return 0;
9996 
9997 	ufshcd_hba_vreg_set_hpm(hba);
9998 	ret = ufshcd_vreg_set_hpm(hba);
9999 	if (ret)
10000 		goto out;
10001 
10002 	/* Make sure clocks are enabled before accessing controller */
10003 	ret = ufshcd_setup_clocks(hba, true);
10004 	if (ret)
10005 		goto disable_vreg;
10006 
10007 	/* enable the host irq as host controller would be active soon */
10008 	ufshcd_enable_irq(hba);
10009 
10010 	goto out;
10011 
10012 disable_vreg:
10013 	ufshcd_vreg_set_lpm(hba);
10014 out:
10015 	if (ret)
10016 		ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
10017 	return ret;
10018 }
10019 #endif /* CONFIG_PM */
10020 
10021 #ifdef CONFIG_PM_SLEEP
10022 /**
10023  * ufshcd_system_suspend - system suspend callback
10024  * @dev: Device associated with the UFS controller.
10025  *
10026  * Executed before putting the system into a sleep state in which the contents
10027  * of main memory are preserved.
10028  *
10029  * Return: 0 for success and non-zero for failure.
10030  */
ufshcd_system_suspend(struct device * dev)10031 int ufshcd_system_suspend(struct device *dev)
10032 {
10033 	struct ufs_hba *hba = dev_get_drvdata(dev);
10034 	int ret = 0;
10035 	ktime_t start = ktime_get();
10036 
10037 	if (pm_runtime_suspended(hba->dev))
10038 		goto out;
10039 
10040 	ret = ufshcd_suspend(hba);
10041 out:
10042 	trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
10043 		ktime_to_us(ktime_sub(ktime_get(), start)),
10044 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10045 	return ret;
10046 }
10047 EXPORT_SYMBOL(ufshcd_system_suspend);
10048 
10049 /**
10050  * ufshcd_system_resume - system resume callback
10051  * @dev: Device associated with the UFS controller.
10052  *
10053  * Executed after waking the system up from a sleep state in which the contents
10054  * of main memory were preserved.
10055  *
10056  * Return: 0 for success and non-zero for failure.
10057  */
ufshcd_system_resume(struct device * dev)10058 int ufshcd_system_resume(struct device *dev)
10059 {
10060 	struct ufs_hba *hba = dev_get_drvdata(dev);
10061 	ktime_t start = ktime_get();
10062 	int ret = 0;
10063 
10064 	if (pm_runtime_suspended(hba->dev))
10065 		goto out;
10066 
10067 	ret = ufshcd_resume(hba);
10068 
10069 out:
10070 	trace_ufshcd_system_resume(dev_name(hba->dev), ret,
10071 		ktime_to_us(ktime_sub(ktime_get(), start)),
10072 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10073 
10074 	return ret;
10075 }
10076 EXPORT_SYMBOL(ufshcd_system_resume);
10077 #endif /* CONFIG_PM_SLEEP */
10078 
10079 #ifdef CONFIG_PM
10080 /**
10081  * ufshcd_runtime_suspend - runtime suspend callback
10082  * @dev: Device associated with the UFS controller.
10083  *
10084  * Check the description of ufshcd_suspend() function for more details.
10085  *
10086  * Return: 0 for success and non-zero for failure.
10087  */
ufshcd_runtime_suspend(struct device * dev)10088 int ufshcd_runtime_suspend(struct device *dev)
10089 {
10090 	struct ufs_hba *hba = dev_get_drvdata(dev);
10091 	int ret;
10092 	ktime_t start = ktime_get();
10093 
10094 	ret = ufshcd_suspend(hba);
10095 
10096 	trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
10097 		ktime_to_us(ktime_sub(ktime_get(), start)),
10098 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10099 	return ret;
10100 }
10101 EXPORT_SYMBOL(ufshcd_runtime_suspend);
10102 
10103 /**
10104  * ufshcd_runtime_resume - runtime resume routine
10105  * @dev: Device associated with the UFS controller.
10106  *
10107  * This function basically brings controller
10108  * to active state. Following operations are done in this function:
10109  *
10110  * 1. Turn on all the controller related clocks
10111  * 2. Turn ON VCC rail
10112  *
10113  * Return: 0 upon success; < 0 upon failure.
10114  */
ufshcd_runtime_resume(struct device * dev)10115 int ufshcd_runtime_resume(struct device *dev)
10116 {
10117 	struct ufs_hba *hba = dev_get_drvdata(dev);
10118 	int ret;
10119 	ktime_t start = ktime_get();
10120 
10121 	ret = ufshcd_resume(hba);
10122 
10123 	trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
10124 		ktime_to_us(ktime_sub(ktime_get(), start)),
10125 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10126 	return ret;
10127 }
10128 EXPORT_SYMBOL(ufshcd_runtime_resume);
10129 #endif /* CONFIG_PM */
10130 
ufshcd_wl_shutdown(struct device * dev)10131 static void ufshcd_wl_shutdown(struct device *dev)
10132 {
10133 	struct scsi_device *sdev = to_scsi_device(dev);
10134 	struct ufs_hba *hba = shost_priv(sdev->host);
10135 
10136 	down(&hba->host_sem);
10137 	hba->shutting_down = true;
10138 	up(&hba->host_sem);
10139 
10140 	/* Turn on everything while shutting down */
10141 	ufshcd_rpm_get_sync(hba);
10142 	scsi_device_quiesce(sdev);
10143 	shost_for_each_device(sdev, hba->host) {
10144 		if (sdev == hba->ufs_device_wlun)
10145 			continue;
10146 		mutex_lock(&sdev->state_mutex);
10147 		scsi_device_set_state(sdev, SDEV_OFFLINE);
10148 		mutex_unlock(&sdev->state_mutex);
10149 	}
10150 	__ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10151 
10152 	/*
10153 	 * Next, turn off the UFS controller and the UFS regulators. Disable
10154 	 * clocks.
10155 	 */
10156 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
10157 		ufshcd_suspend(hba);
10158 
10159 	hba->is_powered = false;
10160 }
10161 
10162 /**
10163  * ufshcd_remove - de-allocate SCSI host and host memory space
10164  *		data structure memory
10165  * @hba: per adapter instance
10166  */
ufshcd_remove(struct ufs_hba * hba)10167 void ufshcd_remove(struct ufs_hba *hba)
10168 {
10169 	if (hba->ufs_device_wlun)
10170 		ufshcd_rpm_get_sync(hba);
10171 	ufs_hwmon_remove(hba);
10172 	ufs_bsg_remove(hba);
10173 	ufs_sysfs_remove_nodes(hba->dev);
10174 	cancel_delayed_work_sync(&hba->ufs_rtc_update_work);
10175 	blk_mq_destroy_queue(hba->tmf_queue);
10176 	blk_put_queue(hba->tmf_queue);
10177 	blk_mq_free_tag_set(&hba->tmf_tag_set);
10178 	if (hba->scsi_host_added)
10179 		scsi_remove_host(hba->host);
10180 	/* disable interrupts */
10181 	ufshcd_disable_intr(hba, hba->intr_mask);
10182 	ufshcd_hba_stop(hba);
10183 	ufshcd_hba_exit(hba);
10184 }
10185 EXPORT_SYMBOL_GPL(ufshcd_remove);
10186 
10187 #ifdef CONFIG_PM_SLEEP
ufshcd_system_freeze(struct device * dev)10188 int ufshcd_system_freeze(struct device *dev)
10189 {
10190 
10191 	return ufshcd_system_suspend(dev);
10192 
10193 }
10194 EXPORT_SYMBOL_GPL(ufshcd_system_freeze);
10195 
ufshcd_system_restore(struct device * dev)10196 int ufshcd_system_restore(struct device *dev)
10197 {
10198 
10199 	struct ufs_hba *hba = dev_get_drvdata(dev);
10200 	int ret;
10201 
10202 	ret = ufshcd_system_resume(dev);
10203 	if (ret)
10204 		return ret;
10205 
10206 	/* Configure UTRL and UTMRL base address registers */
10207 	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
10208 			REG_UTP_TRANSFER_REQ_LIST_BASE_L);
10209 	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
10210 			REG_UTP_TRANSFER_REQ_LIST_BASE_H);
10211 	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
10212 			REG_UTP_TASK_REQ_LIST_BASE_L);
10213 	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
10214 			REG_UTP_TASK_REQ_LIST_BASE_H);
10215 	/*
10216 	 * Make sure that UTRL and UTMRL base address registers
10217 	 * are updated with the latest queue addresses. Only after
10218 	 * updating these addresses, we can queue the new commands.
10219 	 */
10220 	ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H);
10221 
10222 	return 0;
10223 
10224 }
10225 EXPORT_SYMBOL_GPL(ufshcd_system_restore);
10226 
ufshcd_system_thaw(struct device * dev)10227 int ufshcd_system_thaw(struct device *dev)
10228 {
10229 	return ufshcd_system_resume(dev);
10230 }
10231 EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
10232 #endif /* CONFIG_PM_SLEEP  */
10233 
10234 /**
10235  * ufshcd_set_dma_mask - Set dma mask based on the controller
10236  *			 addressing capability
10237  * @hba: per adapter instance
10238  *
10239  * Return: 0 for success, non-zero for failure.
10240  */
ufshcd_set_dma_mask(struct ufs_hba * hba)10241 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
10242 {
10243 	if (hba->vops && hba->vops->set_dma_mask)
10244 		return hba->vops->set_dma_mask(hba);
10245 	if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
10246 		if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
10247 			return 0;
10248 	}
10249 	return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
10250 }
10251 
10252 /**
10253  * ufshcd_devres_release - devres cleanup handler, invoked during release of
10254  *			   hba->dev
10255  * @host: pointer to SCSI host
10256  */
ufshcd_devres_release(void * host)10257 static void ufshcd_devres_release(void *host)
10258 {
10259 	scsi_host_put(host);
10260 }
10261 
10262 /**
10263  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
10264  * @dev: pointer to device handle
10265  * @hba_handle: driver private handle
10266  *
10267  * Return: 0 on success, non-zero value on failure.
10268  *
10269  * NOTE: There is no corresponding ufshcd_dealloc_host() because this function
10270  * keeps track of its allocations using devres and deallocates everything on
10271  * device removal automatically.
10272  */
ufshcd_alloc_host(struct device * dev,struct ufs_hba ** hba_handle)10273 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
10274 {
10275 	struct Scsi_Host *host;
10276 	struct ufs_hba *hba;
10277 	int err = 0;
10278 
10279 	if (!dev) {
10280 		dev_err(dev,
10281 		"Invalid memory reference for dev is NULL\n");
10282 		err = -ENODEV;
10283 		goto out_error;
10284 	}
10285 
10286 	host = scsi_host_alloc(&ufshcd_driver_template,
10287 				sizeof(struct ufs_hba));
10288 	if (!host) {
10289 		dev_err(dev, "scsi_host_alloc failed\n");
10290 		err = -ENOMEM;
10291 		goto out_error;
10292 	}
10293 
10294 	err = devm_add_action_or_reset(dev, ufshcd_devres_release,
10295 				       host);
10296 	if (err)
10297 		return dev_err_probe(dev, err,
10298 				     "failed to add ufshcd dealloc action\n");
10299 
10300 	host->nr_maps = HCTX_TYPE_POLL + 1;
10301 	hba = shost_priv(host);
10302 	hba->host = host;
10303 	hba->dev = dev;
10304 	hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
10305 	hba->nop_out_timeout = NOP_OUT_TIMEOUT;
10306 	ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry));
10307 	INIT_LIST_HEAD(&hba->clk_list_head);
10308 	spin_lock_init(&hba->outstanding_lock);
10309 
10310 	*hba_handle = hba;
10311 
10312 out_error:
10313 	return err;
10314 }
10315 EXPORT_SYMBOL(ufshcd_alloc_host);
10316 
10317 /* This function exists because blk_mq_alloc_tag_set() requires this. */
ufshcd_queue_tmf(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * qd)10318 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
10319 				     const struct blk_mq_queue_data *qd)
10320 {
10321 	WARN_ON_ONCE(true);
10322 	return BLK_STS_NOTSUPP;
10323 }
10324 
10325 static const struct blk_mq_ops ufshcd_tmf_ops = {
10326 	.queue_rq = ufshcd_queue_tmf,
10327 };
10328 
ufshcd_add_scsi_host(struct ufs_hba * hba)10329 static int ufshcd_add_scsi_host(struct ufs_hba *hba)
10330 {
10331 	int err;
10332 
10333 	if (is_mcq_supported(hba)) {
10334 		ufshcd_mcq_enable(hba);
10335 		err = ufshcd_alloc_mcq(hba);
10336 		if (!err) {
10337 			ufshcd_config_mcq(hba);
10338 		} else {
10339 			/* Continue with SDB mode */
10340 			ufshcd_mcq_disable(hba);
10341 			use_mcq_mode = false;
10342 			dev_err(hba->dev, "MCQ mode is disabled, err=%d\n",
10343 				err);
10344 		}
10345 	}
10346 	if (!is_mcq_supported(hba) && !hba->lsdb_sup) {
10347 		dev_err(hba->dev,
10348 			"%s: failed to initialize (legacy doorbell mode not supported)\n",
10349 			__func__);
10350 		return -EINVAL;
10351 	}
10352 
10353 	err = scsi_add_host(hba->host, hba->dev);
10354 	if (err) {
10355 		dev_err(hba->dev, "scsi_add_host failed\n");
10356 		return err;
10357 	}
10358 	hba->scsi_host_added = true;
10359 
10360 	hba->tmf_tag_set = (struct blk_mq_tag_set) {
10361 		.nr_hw_queues	= 1,
10362 		.queue_depth	= hba->nutmrs,
10363 		.ops		= &ufshcd_tmf_ops,
10364 	};
10365 	err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
10366 	if (err < 0)
10367 		goto remove_scsi_host;
10368 	hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL);
10369 	if (IS_ERR(hba->tmf_queue)) {
10370 		err = PTR_ERR(hba->tmf_queue);
10371 		goto free_tmf_tag_set;
10372 	}
10373 	hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
10374 				    sizeof(*hba->tmf_rqs), GFP_KERNEL);
10375 	if (!hba->tmf_rqs) {
10376 		err = -ENOMEM;
10377 		goto free_tmf_queue;
10378 	}
10379 
10380 	return 0;
10381 
10382 free_tmf_queue:
10383 	blk_mq_destroy_queue(hba->tmf_queue);
10384 	blk_put_queue(hba->tmf_queue);
10385 
10386 free_tmf_tag_set:
10387 	blk_mq_free_tag_set(&hba->tmf_tag_set);
10388 
10389 remove_scsi_host:
10390 	if (hba->scsi_host_added)
10391 		scsi_remove_host(hba->host);
10392 
10393 	return err;
10394 }
10395 
10396 /**
10397  * ufshcd_init - Driver initialization routine
10398  * @hba: per-adapter instance
10399  * @mmio_base: base register address
10400  * @irq: Interrupt line of device
10401  *
10402  * Return: 0 on success, non-zero value on failure.
10403  */
ufshcd_init(struct ufs_hba * hba,void __iomem * mmio_base,unsigned int irq)10404 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
10405 {
10406 	int err;
10407 	struct Scsi_Host *host = hba->host;
10408 	struct device *dev = hba->dev;
10409 
10410 	/*
10411 	 * dev_set_drvdata() must be called before any callbacks are registered
10412 	 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
10413 	 * sysfs).
10414 	 */
10415 	dev_set_drvdata(dev, hba);
10416 
10417 	if (!mmio_base) {
10418 		dev_err(hba->dev,
10419 		"Invalid memory reference for mmio_base is NULL\n");
10420 		err = -ENODEV;
10421 		goto out_error;
10422 	}
10423 
10424 	hba->mmio_base = mmio_base;
10425 	hba->irq = irq;
10426 	hba->vps = &ufs_hba_vps;
10427 
10428 	/*
10429 	 * Initialize clk_gating.lock early since it is being used in
10430 	 * ufshcd_setup_clocks()
10431 	 */
10432 	spin_lock_init(&hba->clk_gating.lock);
10433 
10434 	/*
10435 	 * Set the default power management level for runtime and system PM.
10436 	 * Host controller drivers can override them in their
10437 	 * 'ufs_hba_variant_ops::init' callback.
10438 	 *
10439 	 * Default power saving mode is to keep UFS link in Hibern8 state
10440 	 * and UFS device in sleep state.
10441 	 */
10442 	hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10443 						UFS_SLEEP_PWR_MODE,
10444 						UIC_LINK_HIBERN8_STATE);
10445 	hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10446 						UFS_SLEEP_PWR_MODE,
10447 						UIC_LINK_HIBERN8_STATE);
10448 
10449 	err = ufshcd_hba_init(hba);
10450 	if (err)
10451 		goto out_error;
10452 
10453 	/* Read capabilities registers */
10454 	err = ufshcd_hba_capabilities(hba);
10455 	if (err)
10456 		goto out_disable;
10457 
10458 	/* Get UFS version supported by the controller */
10459 	hba->ufs_version = ufshcd_get_ufs_version(hba);
10460 
10461 	/* Get Interrupt bit mask per version */
10462 	hba->intr_mask = ufshcd_get_intr_mask(hba);
10463 
10464 	err = ufshcd_set_dma_mask(hba);
10465 	if (err) {
10466 		dev_err(hba->dev, "set dma mask failed\n");
10467 		goto out_disable;
10468 	}
10469 
10470 	/* Allocate memory for host memory space */
10471 	err = ufshcd_memory_alloc(hba);
10472 	if (err) {
10473 		dev_err(hba->dev, "Memory allocation failed\n");
10474 		goto out_disable;
10475 	}
10476 
10477 	/* Configure LRB */
10478 	ufshcd_host_memory_configure(hba);
10479 
10480 	host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
10481 	host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
10482 	host->max_id = UFSHCD_MAX_ID;
10483 	host->max_lun = UFS_MAX_LUNS;
10484 	host->max_channel = UFSHCD_MAX_CHANNEL;
10485 	host->unique_id = host->host_no;
10486 	host->max_cmd_len = UFS_CDB_SIZE;
10487 	host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING);
10488 
10489 	/* Use default RPM delay if host not set */
10490 	if (host->rpm_autosuspend_delay == 0)
10491 		host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS;
10492 
10493 	hba->max_pwr_info.is_valid = false;
10494 
10495 	/* Initialize work queues */
10496 	hba->eh_wq = alloc_ordered_workqueue("ufs_eh_wq_%d", WQ_MEM_RECLAIM,
10497 					     hba->host->host_no);
10498 	if (!hba->eh_wq) {
10499 		dev_err(hba->dev, "%s: failed to create eh workqueue\n",
10500 			__func__);
10501 		err = -ENOMEM;
10502 		goto out_disable;
10503 	}
10504 	INIT_WORK(&hba->eh_work, ufshcd_err_handler);
10505 	INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
10506 
10507 	sema_init(&hba->host_sem, 1);
10508 
10509 	/* Initialize UIC command mutex */
10510 	mutex_init(&hba->uic_cmd_mutex);
10511 
10512 	/* Initialize mutex for device management commands */
10513 	mutex_init(&hba->dev_cmd.lock);
10514 
10515 	/* Initialize mutex for exception event control */
10516 	mutex_init(&hba->ee_ctrl_mutex);
10517 
10518 	mutex_init(&hba->wb_mutex);
10519 	init_rwsem(&hba->clk_scaling_lock);
10520 
10521 	ufshcd_init_clk_gating(hba);
10522 
10523 	ufshcd_init_clk_scaling(hba);
10524 
10525 	/*
10526 	 * In order to avoid any spurious interrupt immediately after
10527 	 * registering UFS controller interrupt handler, clear any pending UFS
10528 	 * interrupt status and disable all the UFS interrupts.
10529 	 */
10530 	ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
10531 		      REG_INTERRUPT_STATUS);
10532 	ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
10533 	/*
10534 	 * Make sure that UFS interrupts are disabled and any pending interrupt
10535 	 * status is cleared before registering UFS interrupt handler.
10536 	 */
10537 	ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
10538 
10539 	/* IRQ registration */
10540 	err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
10541 	if (err) {
10542 		dev_err(hba->dev, "request irq failed\n");
10543 		goto out_disable;
10544 	} else {
10545 		hba->is_irq_enabled = true;
10546 	}
10547 
10548 	/* Reset the attached device */
10549 	ufshcd_device_reset(hba);
10550 
10551 	ufshcd_init_crypto(hba);
10552 
10553 	/* Host controller enable */
10554 	err = ufshcd_hba_enable(hba);
10555 	if (err) {
10556 		dev_err(hba->dev, "Host controller enable failed\n");
10557 		ufshcd_print_evt_hist(hba);
10558 		ufshcd_print_host_state(hba);
10559 		goto out_disable;
10560 	}
10561 
10562 	INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work);
10563 	INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work);
10564 
10565 	/* Set the default auto-hiberate idle timer value to 150 ms */
10566 	if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
10567 		hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10568 			    FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10569 	}
10570 
10571 	/* Hold auto suspend until async scan completes */
10572 	pm_runtime_get_sync(dev);
10573 
10574 	/*
10575 	 * We are assuming that device wasn't put in sleep/power-down
10576 	 * state exclusively during the boot stage before kernel.
10577 	 * This assumption helps avoid doing link startup twice during
10578 	 * ufshcd_probe_hba().
10579 	 */
10580 	ufshcd_set_ufs_dev_active(hba);
10581 
10582 	/* Initialize hba, detect and initialize UFS device */
10583 	ktime_t probe_start = ktime_get();
10584 
10585 	hba->ufshcd_state = UFSHCD_STATE_RESET;
10586 
10587 	err = ufshcd_link_startup(hba);
10588 	if (err)
10589 		goto out_disable;
10590 
10591 	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
10592 		goto initialized;
10593 
10594 	/* Debug counters initialization */
10595 	ufshcd_clear_dbg_ufs_stats(hba);
10596 
10597 	/* UniPro link is active now */
10598 	ufshcd_set_link_active(hba);
10599 
10600 	/* Verify device initialization by sending NOP OUT UPIU */
10601 	err = ufshcd_verify_dev_init(hba);
10602 	if (err)
10603 		goto out_disable;
10604 
10605 	/* Initiate UFS initialization, and waiting until completion */
10606 	err = ufshcd_complete_dev_init(hba);
10607 	if (err)
10608 		goto out_disable;
10609 
10610 	err = ufshcd_device_params_init(hba);
10611 	if (err)
10612 		goto out_disable;
10613 
10614 	err = ufshcd_post_device_init(hba);
10615 
10616 initialized:
10617 	ufshcd_process_probe_result(hba, probe_start, err);
10618 	if (err)
10619 		goto out_disable;
10620 
10621 	err = ufshcd_add_scsi_host(hba);
10622 	if (err)
10623 		goto out_disable;
10624 
10625 	async_schedule(ufshcd_async_scan, hba);
10626 	ufs_sysfs_add_nodes(hba->dev);
10627 
10628 	device_enable_async_suspend(dev);
10629 	ufshcd_pm_qos_init(hba);
10630 	return 0;
10631 
10632 out_disable:
10633 	hba->is_irq_enabled = false;
10634 	ufshcd_hba_exit(hba);
10635 out_error:
10636 	return err;
10637 }
10638 EXPORT_SYMBOL_GPL(ufshcd_init);
10639 
ufshcd_resume_complete(struct device * dev)10640 void ufshcd_resume_complete(struct device *dev)
10641 {
10642 	struct ufs_hba *hba = dev_get_drvdata(dev);
10643 
10644 	if (hba->complete_put) {
10645 		ufshcd_rpm_put(hba);
10646 		hba->complete_put = false;
10647 	}
10648 }
10649 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
10650 
ufshcd_rpm_ok_for_spm(struct ufs_hba * hba)10651 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
10652 {
10653 	struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
10654 	enum ufs_dev_pwr_mode dev_pwr_mode;
10655 	enum uic_link_state link_state;
10656 	unsigned long flags;
10657 	bool res;
10658 
10659 	spin_lock_irqsave(&dev->power.lock, flags);
10660 	dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
10661 	link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
10662 	res = pm_runtime_suspended(dev) &&
10663 	      hba->curr_dev_pwr_mode == dev_pwr_mode &&
10664 	      hba->uic_link_state == link_state &&
10665 	      !hba->dev_info.b_rpm_dev_flush_capable;
10666 	spin_unlock_irqrestore(&dev->power.lock, flags);
10667 
10668 	return res;
10669 }
10670 
__ufshcd_suspend_prepare(struct device * dev,bool rpm_ok_for_spm)10671 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
10672 {
10673 	struct ufs_hba *hba = dev_get_drvdata(dev);
10674 	int ret;
10675 
10676 	/*
10677 	 * SCSI assumes that runtime-pm and system-pm for scsi drivers
10678 	 * are same. And it doesn't wake up the device for system-suspend
10679 	 * if it's runtime suspended. But ufs doesn't follow that.
10680 	 * Refer ufshcd_resume_complete()
10681 	 */
10682 	if (hba->ufs_device_wlun) {
10683 		/* Prevent runtime suspend */
10684 		ufshcd_rpm_get_noresume(hba);
10685 		/*
10686 		 * Check if already runtime suspended in same state as system
10687 		 * suspend would be.
10688 		 */
10689 		if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
10690 			/* RPM state is not ok for SPM, so runtime resume */
10691 			ret = ufshcd_rpm_resume(hba);
10692 			if (ret < 0 && ret != -EACCES) {
10693 				ufshcd_rpm_put(hba);
10694 				return ret;
10695 			}
10696 		}
10697 		hba->complete_put = true;
10698 	}
10699 	return 0;
10700 }
10701 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
10702 
ufshcd_suspend_prepare(struct device * dev)10703 int ufshcd_suspend_prepare(struct device *dev)
10704 {
10705 	return __ufshcd_suspend_prepare(dev, true);
10706 }
10707 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
10708 
10709 #ifdef CONFIG_PM_SLEEP
ufshcd_wl_poweroff(struct device * dev)10710 static int ufshcd_wl_poweroff(struct device *dev)
10711 {
10712 	struct scsi_device *sdev = to_scsi_device(dev);
10713 	struct ufs_hba *hba = shost_priv(sdev->host);
10714 
10715 	__ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10716 	return 0;
10717 }
10718 #endif
10719 
ufshcd_wl_probe(struct device * dev)10720 static int ufshcd_wl_probe(struct device *dev)
10721 {
10722 	struct scsi_device *sdev = to_scsi_device(dev);
10723 
10724 	if (!is_device_wlun(sdev))
10725 		return -ENODEV;
10726 
10727 	blk_pm_runtime_init(sdev->request_queue, dev);
10728 	pm_runtime_set_autosuspend_delay(dev, 0);
10729 	pm_runtime_allow(dev);
10730 
10731 	return  0;
10732 }
10733 
ufshcd_wl_remove(struct device * dev)10734 static int ufshcd_wl_remove(struct device *dev)
10735 {
10736 	pm_runtime_forbid(dev);
10737 	return 0;
10738 }
10739 
10740 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
10741 #ifdef CONFIG_PM_SLEEP
10742 	.suspend = ufshcd_wl_suspend,
10743 	.resume = ufshcd_wl_resume,
10744 	.freeze = ufshcd_wl_suspend,
10745 	.thaw = ufshcd_wl_resume,
10746 	.poweroff = ufshcd_wl_poweroff,
10747 	.restore = ufshcd_wl_resume,
10748 #endif
10749 	SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
10750 };
10751 
ufshcd_check_header_layout(void)10752 static void ufshcd_check_header_layout(void)
10753 {
10754 	/*
10755 	 * gcc compilers before version 10 cannot do constant-folding for
10756 	 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and
10757 	 * before.
10758 	 */
10759 	if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000)
10760 		return;
10761 
10762 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10763 				.cci = 3})[0] != 3);
10764 
10765 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10766 				.ehs_length = 2})[1] != 2);
10767 
10768 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10769 				.enable_crypto = 1})[2]
10770 		     != 0x80);
10771 
10772 	BUILD_BUG_ON((((u8 *)&(struct request_desc_header){
10773 					.command_type = 5,
10774 					.data_direction = 3,
10775 					.interrupt = 1,
10776 				})[3]) != ((5 << 4) | (3 << 1) | 1));
10777 
10778 	BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10779 				.dunl = cpu_to_le32(0xdeadbeef)})[1] !=
10780 		cpu_to_le32(0xdeadbeef));
10781 
10782 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10783 				.ocs = 4})[8] != 4);
10784 
10785 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10786 				.cds = 5})[9] != 5);
10787 
10788 	BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10789 				.dunu = cpu_to_le32(0xbadcafe)})[3] !=
10790 		cpu_to_le32(0xbadcafe));
10791 
10792 	BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10793 			     .iid = 0xf })[4] != 0xf0);
10794 
10795 	BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10796 			     .command_set_type = 0xf })[4] != 0xf);
10797 }
10798 
10799 /*
10800  * ufs_dev_wlun_template - describes ufs device wlun
10801  * ufs-device wlun - used to send pm commands
10802  * All luns are consumers of ufs-device wlun.
10803  *
10804  * Currently, no sd driver is present for wluns.
10805  * Hence the no specific pm operations are performed.
10806  * With ufs design, SSU should be sent to ufs-device wlun.
10807  * Hence register a scsi driver for ufs wluns only.
10808  */
10809 static struct scsi_driver ufs_dev_wlun_template = {
10810 	.gendrv = {
10811 		.name = "ufs_device_wlun",
10812 		.probe = ufshcd_wl_probe,
10813 		.remove = ufshcd_wl_remove,
10814 		.pm = &ufshcd_wl_pm_ops,
10815 		.shutdown = ufshcd_wl_shutdown,
10816 	},
10817 };
10818 
ufshcd_core_init(void)10819 static int __init ufshcd_core_init(void)
10820 {
10821 	int ret;
10822 
10823 	ufshcd_check_header_layout();
10824 
10825 	ufs_debugfs_init();
10826 
10827 	ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
10828 	if (ret)
10829 		ufs_debugfs_exit();
10830 	return ret;
10831 }
10832 
ufshcd_core_exit(void)10833 static void __exit ufshcd_core_exit(void)
10834 {
10835 	ufs_debugfs_exit();
10836 	scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
10837 }
10838 
10839 module_init(ufshcd_core_init);
10840 module_exit(ufshcd_core_exit);
10841 
10842 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
10843 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
10844 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
10845 MODULE_SOFTDEP("pre: governor_simpleondemand");
10846 MODULE_LICENSE("GPL");
10847