1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/counter.h>
37 #include <sys/rman.h>
38 #include <sys/types.h>
39 #include <sys/lock.h>
40 #include <sys/malloc.h>
41 #include <sys/rwlock.h>
42 #include <sys/seqc.h>
43 #include <sys/sx.h>
44 #include <sys/vmem.h>
45 #include <vm/uma.h>
46
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <machine/bus.h>
50 #include <sys/socket.h>
51 #include <sys/sysctl.h>
52 #include <sys/taskqueue.h>
53 #include <net/ethernet.h>
54 #include <net/if.h>
55 #include <net/if_var.h>
56 #include <net/if_media.h>
57 #include <net/pfil.h>
58 #include <netinet/in.h>
59 #include <netinet/tcp_lro.h>
60
61 #include "offload.h"
62 #include "t4_ioctl.h"
63 #include "common/t4_msg.h"
64 #include "firmware/t4fw_interface.h"
65
66 #define KTR_CXGBE KTR_SPARE3
67 MALLOC_DECLARE(M_CXGBE);
68 #define CXGBE_UNIMPLEMENTED(s) \
69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
70
71 /*
72 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's
73 * LIST_HEAD when building iw_cxgbe.
74 */
75 #define CXGBE_LIST_HEAD(name, type) \
76 struct name { \
77 struct type *lh_first; /* first element */ \
78 }
79
80 #ifndef SYSCTL_ADD_UQUAD
81 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
82 #define sysctl_handle_64 sysctl_handle_quad
83 #define CTLTYPE_U64 CTLTYPE_QUAD
84 #endif
85
86 SYSCTL_DECL(_hw_cxgbe);
87
88 struct adapter;
89 typedef struct adapter adapter_t;
90
91 enum {
92 /*
93 * All ingress queues use this entry size. Note that the firmware event
94 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
95 * be at least 64.
96 */
97 IQ_ESIZE = 64,
98
99 /* Default queue sizes for all kinds of ingress queues */
100 FW_IQ_QSIZE = 256,
101 RX_IQ_QSIZE = 1024,
102
103 /* All egress queues use this entry size */
104 EQ_ESIZE = 64,
105
106 /* Default queue sizes for all kinds of egress queues */
107 CTRL_EQ_QSIZE = 1024,
108 TX_EQ_QSIZE = 1024,
109
110 #if MJUMPAGESIZE != MCLBYTES
111 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
112 #else
113 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
114 #endif
115 CL_METADATA_SIZE = CACHE_LINE_SIZE,
116
117 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
118 TX_SGL_SEGS = 39,
119 TX_SGL_SEGS_TSO = 38,
120 TX_SGL_SEGS_VM = 38,
121 TX_SGL_SEGS_VM_TSO = 37,
122 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
123 TX_SGL_SEGS_VXLAN_TSO = 37,
124 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
125 };
126
127 enum {
128 /* adapter intr_type */
129 INTR_INTX = (1 << 0),
130 INTR_MSI = (1 << 1),
131 INTR_MSIX = (1 << 2)
132 };
133
134 enum {
135 XGMAC_MTU = (1 << 0),
136 XGMAC_PROMISC = (1 << 1),
137 XGMAC_ALLMULTI = (1 << 2),
138 XGMAC_VLANEX = (1 << 3),
139 XGMAC_UCADDR = (1 << 4),
140 XGMAC_MCADDRS = (1 << 5),
141
142 XGMAC_ALL = 0xffff
143 };
144
145 enum {
146 /* flags understood by begin_synchronized_op */
147 HOLD_LOCK = (1 << 0),
148 SLEEP_OK = (1 << 1),
149 INTR_OK = (1 << 2),
150
151 /* flags understood by end_synchronized_op */
152 LOCK_HELD = HOLD_LOCK,
153 };
154
155 enum {
156 /* adapter flags. synch_op or adapter_lock. */
157 FULL_INIT_DONE = (1 << 0),
158 FW_OK = (1 << 1),
159 CHK_MBOX_ACCESS = (1 << 2),
160 MASTER_PF = (1 << 3),
161 BUF_PACKING_OK = (1 << 6),
162 IS_VF = (1 << 7),
163 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */
164 CXGBE_BUSY = (1 << 9),
165
166 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */
167 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */
168 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */
169 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */
170 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */
171
172 /* port flags */
173 HAS_TRACEQ = (1 << 3),
174 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
175
176 /* VI flags */
177 VI_DETACHING = (1 << 0),
178 VI_INIT_DONE = (1 << 1),
179 /* 1 << 2 is unused, was VI_SYSCTL_CTX */
180 TX_USES_VM_WR = (1 << 3),
181 VI_SKIP_STATS = (1 << 4),
182
183 /* adapter debug_flags */
184 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
185 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
186 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
187 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
188 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
189 };
190
191 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING)
192 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0)
193 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0)
194 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
195 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
196 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
197
198 struct vi_info {
199 device_t dev;
200 struct port_info *pi;
201 struct adapter *adapter;
202
203 if_t ifp;
204 struct pfil_head *pfil;
205
206 unsigned long flags;
207 int if_flags;
208
209 uint16_t *rss, *nm_rss;
210 uint16_t viid; /* opaque VI identifier */
211 uint16_t smt_idx;
212 uint16_t vin;
213 uint8_t vfvld;
214 int16_t xact_addr_filt;/* index of exact MAC address filter */
215 uint16_t rss_size; /* size of VI's RSS table slice */
216 uint16_t rss_base; /* start of VI's RSS table slice */
217 int hashen;
218
219 int nintr;
220 int first_intr;
221
222 /* These need to be int as they are used in sysctl */
223 int ntxq; /* # of tx queues */
224 int first_txq; /* index of first tx queue */
225 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
226 int nrxq; /* # of rx queues */
227 int first_rxq; /* index of first rx queue */
228 int nofldtxq; /* # of offload tx queues */
229 int first_ofld_txq; /* index of first offload tx queue */
230 int nofldrxq; /* # of offload rx queues */
231 int first_ofld_rxq; /* index of first offload rx queue */
232 int nnmtxq;
233 int first_nm_txq;
234 int nnmrxq;
235 int first_nm_rxq;
236 int tmr_idx;
237 int ofld_tmr_idx;
238 int pktc_idx;
239 int ofld_pktc_idx;
240 int qsize_rxq;
241 int qsize_txq;
242
243 struct timeval last_refreshed;
244 struct fw_vi_stats_vf stats;
245 struct mtx tick_mtx;
246 struct callout tick;
247
248 struct sysctl_ctx_list ctx;
249 struct sysctl_oid *rxq_oid;
250 struct sysctl_oid *txq_oid;
251 struct sysctl_oid *nm_rxq_oid;
252 struct sysctl_oid *nm_txq_oid;
253 struct sysctl_oid *ofld_rxq_oid;
254 struct sysctl_oid *ofld_txq_oid;
255
256 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
257 u_int txq_rr;
258 u_int rxq_rr;
259 };
260
261 struct tx_ch_rl_params {
262 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
263 uint32_t maxrate;
264 };
265
266 /* CLRL state */
267 enum clrl_state {
268 CS_UNINITIALIZED = 0,
269 CS_PARAMS_SET, /* sw parameters have been set. */
270 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */
271 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */
272 CS_HW_CONFIGURED /* configured in the hardware. */
273 };
274
275 /* CLRL flags */
276 enum {
277 CF_USER = (1 << 0), /* was configured by driver ioctl. */
278 };
279
280 struct tx_cl_rl_params {
281 enum clrl_state state;
282 int refcount;
283 uint8_t flags;
284 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
285 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
286 enum fw_sched_params_mode mode; /* aggr or per-flow */
287 uint32_t maxrate;
288 uint16_t pktsize;
289 uint16_t burstsize;
290 };
291
292 /* Tx scheduler parameters for a channel/port */
293 struct tx_sched_params {
294 /* Channel Rate Limiter */
295 struct tx_ch_rl_params ch_rl;
296
297 /* Class WRR */
298 /* XXX */
299
300 /* Class Rate Limiter (including the default pktsize and burstsize). */
301 int pktsize;
302 int burstsize;
303 struct tx_cl_rl_params cl_rl[];
304 };
305
306 struct port_info {
307 device_t dev;
308 struct adapter *adapter;
309
310 struct vi_info *vi;
311 int nvi;
312 int up_vis;
313 int uld_vis;
314 bool vxlan_tcam_entry;
315
316 struct tx_sched_params *sched_params;
317
318 struct mtx pi_lock;
319 char lockname[16];
320 unsigned long flags;
321
322 uint8_t lport; /* associated offload logical port */
323 int8_t mdio_addr;
324 uint8_t port_type;
325 uint8_t mod_type;
326 uint8_t port_id;
327 uint8_t tx_chan; /* tx TP c-channel */
328 uint8_t rx_chan; /* rx TP c-channel */
329 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
330 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
331
332 struct link_config link_cfg;
333 struct ifmedia media;
334
335 struct port_stats stats;
336 u_int tnl_cong_drops;
337 u_int tx_parse_error;
338 int fcs_reg;
339 uint64_t fcs_base;
340
341 struct sysctl_ctx_list ctx;
342 };
343
344 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
345
346 struct cluster_metadata {
347 uma_zone_t zone;
348 caddr_t cl;
349 u_int refcount;
350 };
351
352 struct fl_sdesc {
353 caddr_t cl;
354 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
355 int16_t moff; /* offset of metadata from cl */
356 uint8_t zidx;
357 };
358
359 struct tx_desc {
360 __be64 flit[8];
361 };
362
363 struct tx_sdesc {
364 struct mbuf *m; /* m_nextpkt linked chain of frames */
365 uint8_t desc_used; /* # of hardware descriptors used by the WR */
366 };
367
368
369 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
370 struct iq_desc {
371 struct rss_header rss;
372 uint8_t cpl[IQ_PAD];
373 struct rsp_ctrl rsp;
374 };
375 #undef IQ_PAD
376 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
377
378 enum {
379 /* iq type */
380 IQ_OTHER = FW_IQ_IQTYPE_OTHER,
381 IQ_ETH = FW_IQ_IQTYPE_NIC,
382 IQ_OFLD = FW_IQ_IQTYPE_OFLD,
383
384 /* iq flags */
385 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
386 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
387 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
388 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
389 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
390 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */
391
392 /* iq state */
393 IQS_DISABLED = 0,
394 IQS_BUSY = 1,
395 IQS_IDLE = 2,
396
397 /* netmap related flags */
398 NM_OFF = 0,
399 NM_ON = 1,
400 NM_BUSY = 2,
401 };
402
403 enum {
404 CPL_COOKIE_RESERVED = 0,
405 CPL_COOKIE_FILTER,
406 CPL_COOKIE_DDP0,
407 CPL_COOKIE_DDP1,
408 CPL_COOKIE_TOM,
409 CPL_COOKIE_HASHFILTER,
410 CPL_COOKIE_ETHOFLD,
411 CPL_COOKIE_KERN_TLS,
412
413 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
414 };
415
416 struct sge_iq;
417 struct rss_header;
418 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
419 struct mbuf *);
420 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
421 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
422
423 /*
424 * Ingress Queue: T4 is producer, driver is consumer.
425 */
426 struct sge_iq {
427 uint16_t flags;
428 uint8_t qtype;
429 volatile int state;
430 struct adapter *adapter;
431 struct iq_desc *desc; /* KVA of descriptor ring */
432 int8_t intr_pktc_idx; /* packet count threshold index */
433 uint8_t gen; /* generation bit */
434 uint8_t intr_params; /* interrupt holdoff parameters */
435 int8_t cong_drop; /* congestion drop settings for the queue */
436 uint16_t qsize; /* size (# of entries) of the queue */
437 uint16_t sidx; /* index of the entry with the status page */
438 uint16_t cidx; /* consumer index */
439 uint16_t cntxt_id; /* SGE context id for the iq */
440 uint16_t abs_id; /* absolute SGE id for the iq */
441 int16_t intr_idx; /* interrupt used by the queue */
442
443 STAILQ_ENTRY(sge_iq) link;
444
445 bus_dma_tag_t desc_tag;
446 bus_dmamap_t desc_map;
447 bus_addr_t ba; /* bus address of descriptor ring */
448 };
449
450 enum {
451 /* eq type */
452 EQ_CTRL = 1,
453 EQ_ETH = 2,
454 EQ_OFLD = 3,
455
456 /* eq flags */
457 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
458 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */
459 EQ_ENABLED = (1 << 3), /* open for business */
460 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
461 };
462
463 /* Listed in order of preference. Update t4_sysctls too if you change these */
464 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
465
466 /*
467 * Egress Queue: driver is producer, T4 is consumer.
468 *
469 * Note: A free list is an egress queue (driver produces the buffers and T4
470 * consumes them) but it's special enough to have its own struct (see sge_fl).
471 */
472 struct sge_eq {
473 unsigned int flags; /* MUST be first */
474 unsigned int cntxt_id; /* SGE context id for the eq */
475 unsigned int abs_id; /* absolute SGE id for the eq */
476 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */
477 uint8_t doorbells;
478 uint8_t port_id; /* port_id of the port associated with the eq */
479 uint8_t tx_chan; /* tx channel used by the eq */
480 struct mtx eq_lock;
481
482 struct tx_desc *desc; /* KVA of descriptor ring */
483 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
484 u_int udb_qid; /* relative qid within the doorbell page */
485 uint16_t sidx; /* index of the entry with the status page */
486 uint16_t cidx; /* consumer idx (desc idx) */
487 uint16_t pidx; /* producer idx (desc idx) */
488 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
489 uint16_t dbidx; /* pidx of the most recent doorbell */
490 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */
491 volatile u_int equiq; /* EQUIQ outstanding */
492 struct sge_iq *iq; /* iq that receives egr_update for the eq */
493
494 bus_dma_tag_t desc_tag;
495 bus_dmamap_t desc_map;
496 bus_addr_t ba; /* bus address of descriptor ring */
497 char lockname[16];
498 };
499
500 struct rx_buf_info {
501 uma_zone_t zone; /* zone that this cluster comes from */
502 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K.
503 * hwsize[hwidx1] = size1. No spare. */
504 uint16_t size2; /* hwsize[hwidx2] = size2.
505 * spare in cluster = size1 - size2. */
506 int8_t hwidx1; /* SGE bufsize idx for size1 */
507 int8_t hwidx2; /* SGE bufsize idx for size2 */
508 uint8_t type; /* EXT_xxx type of the cluster */
509 };
510
511 enum {
512 NUM_MEMWIN = 3,
513
514 MEMWIN0_APERTURE = 2048,
515 MEMWIN0_BASE = 0x1b800,
516
517 MEMWIN1_APERTURE = 32768,
518 MEMWIN1_BASE = 0x28000,
519
520 MEMWIN2_APERTURE_T4 = 65536,
521 MEMWIN2_BASE_T4 = 0x30000,
522
523 MEMWIN2_APERTURE_T5 = 128 * 1024,
524 MEMWIN2_BASE_T5 = 0x60000,
525 };
526
527 struct memwin {
528 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
529 uint32_t mw_base; /* constant after setup_memwin */
530 uint32_t mw_aperture; /* ditto */
531 uint32_t mw_curpos; /* protected by mw_lock */
532 };
533
534 enum {
535 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
536 FL_DOOMED = (1 << 1), /* about to be destroyed */
537 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
538 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
539 };
540
541 #define FL_RUNNING_LOW(fl) \
542 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
543 #define FL_NOT_RUNNING_LOW(fl) \
544 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
545
546 struct sge_fl {
547 struct mtx fl_lock;
548 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
549 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
550 uint16_t zidx; /* refill zone idx */
551 uint16_t safe_zidx;
552 uint16_t lowat; /* # of buffers <= this means fl needs help */
553 int flags;
554 uint16_t buf_boundary;
555
556 /* The 16b idx all deal with hw descriptors */
557 uint16_t dbidx; /* hw pidx after last doorbell */
558 uint16_t sidx; /* index of status page */
559 volatile uint16_t hw_cidx;
560
561 /* The 32b idx are all buffer idx, not hardware descriptor idx */
562 uint32_t cidx; /* consumer index */
563 uint32_t pidx; /* producer index */
564
565 uint32_t dbval;
566 u_int rx_offset; /* offset in fl buf (when buffer packing) */
567 volatile uint32_t *udb;
568
569 uint64_t cl_allocated; /* # of clusters allocated */
570 uint64_t cl_recycled; /* # of clusters recycled */
571 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
572
573 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
574 struct mbuf *m0;
575 struct mbuf **pnext;
576 u_int remaining;
577
578 uint16_t qsize; /* # of hw descriptors (status page included) */
579 uint16_t cntxt_id; /* SGE context id for the freelist */
580 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
581 bus_dma_tag_t desc_tag;
582 bus_dmamap_t desc_map;
583 char lockname[16];
584 bus_addr_t ba; /* bus address of descriptor ring */
585 };
586
587 struct mp_ring;
588
589 struct txpkts {
590 uint8_t wr_type; /* type 0 or type 1 */
591 uint8_t npkt; /* # of packets in this work request */
592 uint8_t len16; /* # of 16B pieces used by this work request */
593 uint8_t score;
594 uint8_t max_npkt; /* maximum number of packets allowed */
595 uint16_t plen; /* total payload (sum of all packets) */
596
597 /* straight from fw_eth_tx_pkts_vm_wr. */
598 __u8 ethmacdst[6];
599 __u8 ethmacsrc[6];
600 __be16 ethtype;
601 __be16 vlantci;
602
603 struct mbuf *mb[15];
604 };
605
606 /* txq: SGE egress queue + what's needed for Ethernet NIC */
607 struct sge_txq {
608 struct sge_eq eq; /* MUST be first */
609
610 if_t ifp; /* the interface this txq belongs to */
611 struct mp_ring *r; /* tx software ring */
612 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
613 struct sglist *gl;
614 __be32 cpl_ctrl0; /* for convenience */
615 int tc_idx; /* traffic class */
616 uint64_t last_tx; /* cycle count when eth_tx was last called */
617 struct txpkts txp;
618
619 struct task tx_reclaim_task;
620 /* stats for common events first */
621
622 uint64_t txcsum; /* # of times hardware assisted with checksum */
623 uint64_t tso_wrs; /* # of TSO work requests */
624 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
625 uint64_t imm_wrs; /* # of work requests with immediate data */
626 uint64_t sgl_wrs; /* # of work requests with direct SGL */
627 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
628 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
629 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
630 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
631 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
632 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */
633 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
634 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */
635 uint64_t vxlan_txcsum;
636
637 uint64_t kern_tls_records;
638 uint64_t kern_tls_short;
639 uint64_t kern_tls_partial;
640 uint64_t kern_tls_full;
641 uint64_t kern_tls_octets;
642 uint64_t kern_tls_waste;
643 uint64_t kern_tls_options;
644 uint64_t kern_tls_header;
645 uint64_t kern_tls_fin;
646 uint64_t kern_tls_fin_short;
647 uint64_t kern_tls_cbc;
648 uint64_t kern_tls_gcm;
649
650 /* stats for not-that-common events */
651
652 /* Optional scratch space for constructing work requests. */
653 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
654 } __aligned(CACHE_LINE_SIZE);
655
656 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
657 struct sge_rxq {
658 struct sge_iq iq; /* MUST be first */
659 struct sge_fl fl; /* MUST follow iq */
660
661 if_t ifp; /* the interface this rxq belongs to */
662 struct lro_ctrl lro; /* LRO state */
663
664 /* stats for common events first */
665
666 uint64_t rxcsum; /* # of times hardware assisted with checksum */
667 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
668 uint64_t vxlan_rxcsum;
669
670 /* stats for not-that-common events */
671
672 } __aligned(CACHE_LINE_SIZE);
673
674 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)675 iq_to_rxq(struct sge_iq *iq)
676 {
677
678 return (__containerof(iq, struct sge_rxq, iq));
679 }
680
681 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
682 struct sge_ofld_rxq {
683 struct sge_iq iq; /* MUST be first */
684 struct sge_fl fl; /* MUST follow iq */
685 counter_u64_t rx_iscsi_ddp_setup_ok;
686 counter_u64_t rx_iscsi_ddp_setup_error;
687 uint64_t rx_iscsi_ddp_pdus;
688 uint64_t rx_iscsi_ddp_octets;
689 uint64_t rx_iscsi_fl_pdus;
690 uint64_t rx_iscsi_fl_octets;
691 uint64_t rx_iscsi_padding_errors;
692 uint64_t rx_iscsi_header_digest_errors;
693 uint64_t rx_iscsi_data_digest_errors;
694 uint64_t rx_aio_ddp_jobs;
695 uint64_t rx_aio_ddp_octets;
696 u_long rx_toe_tls_records;
697 u_long rx_toe_tls_octets;
698 u_long rx_toe_ddp_octets;
699 counter_u64_t ddp_buffer_alloc;
700 counter_u64_t ddp_buffer_reuse;
701 counter_u64_t ddp_buffer_free;
702 } __aligned(CACHE_LINE_SIZE);
703
704 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)705 iq_to_ofld_rxq(struct sge_iq *iq)
706 {
707
708 return (__containerof(iq, struct sge_ofld_rxq, iq));
709 }
710
711 struct wrqe {
712 STAILQ_ENTRY(wrqe) link;
713 struct sge_wrq *wrq;
714 int wr_len;
715 char wr[] __aligned(16);
716 };
717
718 struct wrq_cookie {
719 TAILQ_ENTRY(wrq_cookie) link;
720 int ndesc;
721 int pidx;
722 };
723
724 /*
725 * wrq: SGE egress queue that is given prebuilt work requests. Control queues
726 * are of this type.
727 */
728 struct sge_wrq {
729 struct sge_eq eq; /* MUST be first */
730
731 struct adapter *adapter;
732 struct task wrq_tx_task;
733
734 /* Tx desc reserved but WR not "committed" yet. */
735 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
736
737 /* List of WRs ready to go out as soon as descriptors are available. */
738 STAILQ_HEAD(, wrqe) wr_list;
739 u_int nwr_pending;
740 u_int ndesc_needed;
741
742 /* stats for common events first */
743
744 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
745 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
746 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
747
748 /* stats for not-that-common events */
749
750 /*
751 * Scratch space for work requests that wrap around after reaching the
752 * status page, and some information about the last WR that used it.
753 */
754 uint16_t ss_pidx;
755 uint16_t ss_len;
756 uint8_t ss[SGE_MAX_WR_LEN];
757
758 } __aligned(CACHE_LINE_SIZE);
759
760 /* ofld_txq: SGE egress queue + miscellaneous items */
761 struct sge_ofld_txq {
762 struct sge_wrq wrq;
763 counter_u64_t tx_iscsi_pdus;
764 counter_u64_t tx_iscsi_octets;
765 counter_u64_t tx_iscsi_iso_wrs;
766 counter_u64_t tx_aio_jobs;
767 counter_u64_t tx_aio_octets;
768 counter_u64_t tx_toe_tls_records;
769 counter_u64_t tx_toe_tls_octets;
770 } __aligned(CACHE_LINE_SIZE);
771
772 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
773 struct sge_nm_rxq {
774 /* Items used by the driver rx ithread are in this cacheline. */
775 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */
776 u_int nid; /* netmap ring # for this queue */
777 struct vi_info *vi;
778
779 struct iq_desc *iq_desc;
780 uint16_t iq_abs_id;
781 uint16_t iq_cntxt_id;
782 uint16_t iq_cidx;
783 uint16_t iq_sidx;
784 uint8_t iq_gen;
785 uint32_t fl_sidx;
786
787 /* Items used by netmap rxsync are in this cacheline. */
788 __be64 *fl_desc __aligned(CACHE_LINE_SIZE);
789 uint16_t fl_cntxt_id;
790 uint32_t fl_pidx;
791 uint32_t fl_sidx2; /* copy of fl_sidx */
792 uint32_t fl_db_val;
793 u_int fl_db_saved;
794 u_int fl_db_threshold; /* in descriptors */
795 u_int fl_hwidx:4;
796
797 /*
798 * fl_cidx is used by both the ithread and rxsync, the rest are not used
799 * in the rx fast path.
800 */
801 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
802
803 bus_dma_tag_t iq_desc_tag;
804 bus_dmamap_t iq_desc_map;
805 bus_addr_t iq_ba;
806 int intr_idx;
807
808 bus_dma_tag_t fl_desc_tag;
809 bus_dmamap_t fl_desc_map;
810 bus_addr_t fl_ba;
811 };
812
813 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
814 struct sge_nm_txq {
815 struct tx_desc *desc;
816 uint16_t cidx;
817 uint16_t pidx;
818 uint16_t sidx;
819 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
820 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
821 uint16_t dbidx; /* pidx of the most recent doorbell */
822 uint8_t doorbells;
823 volatile uint32_t *udb;
824 u_int udb_qid;
825 u_int cntxt_id;
826 __be32 cpl_ctrl0; /* for convenience */
827 __be32 op_pkd; /* ditto */
828 u_int nid; /* netmap ring # for this queue */
829
830 /* infrequently used items after this */
831
832 bus_dma_tag_t desc_tag;
833 bus_dmamap_t desc_map;
834 bus_addr_t ba;
835 int iqidx;
836 } __aligned(CACHE_LINE_SIZE);
837
838 struct sge {
839 int nrxq; /* total # of Ethernet rx queues */
840 int ntxq; /* total # of Ethernet tx queues */
841 int nofldrxq; /* total # of TOE rx queues */
842 int nofldtxq; /* total # of TOE tx queues */
843 int nnmrxq; /* total # of netmap rx queues */
844 int nnmtxq; /* total # of netmap tx queues */
845 int niq; /* total # of ingress queues */
846 int neq; /* total # of egress queues */
847
848 struct sge_iq fwq; /* Firmware event queue */
849 struct sge_wrq *ctrlq; /* Control queues */
850 struct sge_txq *txq; /* NIC tx queues */
851 struct sge_rxq *rxq; /* NIC rx queues */
852 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */
853 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
854 struct sge_nm_txq *nm_txq; /* netmap tx queues */
855 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
856
857 uint16_t iq_start; /* first cntxt_id */
858 uint16_t iq_base; /* first abs_id */
859 int eq_start; /* first cntxt_id */
860 int eq_base; /* first abs_id */
861 int iqmap_sz;
862 int eqmap_sz;
863 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
864 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
865
866 int8_t safe_zidx;
867 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
868 };
869
870 struct devnames {
871 const char *nexus_name;
872 const char *ifnet_name;
873 const char *vi_ifnet_name;
874 const char *pf03_drv_name;
875 const char *vf_nexus_name;
876 const char *vf_ifnet_name;
877 };
878
879 struct clip_entry;
880
881 #define CNT_CAL_INFO 3
882 struct clock_sync {
883 uint64_t hw_cur;
884 uint64_t hw_prev;
885 sbintime_t sbt_cur;
886 sbintime_t sbt_prev;
887 seqc_t gen;
888 };
889
890 struct adapter {
891 SLIST_ENTRY(adapter) link;
892 device_t dev;
893 struct cdev *cdev;
894 const struct devnames *names;
895
896 /* PCIe register resources */
897 int regs_rid;
898 struct resource *regs_res;
899 int msix_rid;
900 struct resource *msix_res;
901 bus_space_handle_t bh;
902 bus_space_tag_t bt;
903 bus_size_t mmio_len;
904 int udbs_rid;
905 struct resource *udbs_res;
906 volatile uint8_t *udbs_base;
907
908 unsigned int pf;
909 unsigned int mbox;
910 unsigned int vpd_busy;
911 unsigned int vpd_flag;
912
913 /* Interrupt information */
914 int intr_type;
915 int intr_count;
916 struct irq {
917 struct resource *res;
918 int rid;
919 void *tag;
920 struct sge_rxq *rxq;
921 struct sge_nm_rxq *nm_rxq;
922 } __aligned(CACHE_LINE_SIZE) *irq;
923 int sge_gts_reg;
924 int sge_kdoorbell_reg;
925
926 bus_dma_tag_t dmat; /* Parent DMA tag */
927
928 struct sge sge;
929 int lro_timeout;
930 int sc_do_rxcopy;
931
932 int vxlan_port;
933 u_int vxlan_refcount;
934 int rawf_base;
935 int nrawf;
936 u_int vlan_id;
937
938 struct taskqueue *tq[MAX_NPORTS]; /* General purpose taskqueues */
939 struct port_info *port[MAX_NPORTS];
940 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
941
942 CXGBE_LIST_HEAD(, clip_entry) *clip_table;
943 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */
944 u_long clip_mask;
945 int clip_gen;
946 struct timeout_task clip_task;
947
948 void *tom_softc; /* (struct tom_data *) */
949 struct tom_tunables tt;
950 struct t4_offload_policy *policy;
951 struct rwlock policy_lock;
952
953 void *iwarp_softc; /* (struct c4iw_dev *) */
954 struct iw_tunables iwt;
955 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
956 struct l2t_data *l2t; /* L2 table */
957 struct smt_data *smt; /* Source MAC Table */
958 struct tid_info tids;
959 vmem_t *key_map;
960 struct tls_tunables tlst;
961
962 uint8_t doorbells;
963 int offload_map; /* port_id's with IFCAP_TOE enabled */
964 int bt_map; /* tx_chan's with BASE-T */
965 int active_ulds; /* ULDs activated on this adapter */
966 int flags;
967 int debug_flags;
968 int error_flags; /* Used by error handler and live reset. */
969
970 char ifp_lockname[16];
971 struct mtx ifp_lock;
972 if_t ifp; /* tracer ifp */
973 struct ifmedia media;
974 int traceq; /* iq used by all tracers, -1 if none */
975 int tracer_valid; /* bitmap of valid tracers */
976 int tracer_enabled; /* bitmap of enabled tracers */
977
978 char fw_version[16];
979 char tp_version[16];
980 char er_version[16];
981 char bs_version[16];
982 char cfg_file[32];
983 u_int cfcsum;
984 struct adapter_params params;
985 const struct chip_params *chip_params;
986 struct t4_virt_res vres;
987
988 uint16_t nbmcaps;
989 uint16_t linkcaps;
990 uint16_t switchcaps;
991 uint16_t niccaps;
992 uint16_t toecaps;
993 uint16_t rdmacaps;
994 uint16_t cryptocaps;
995 uint16_t iscsicaps;
996 uint16_t fcoecaps;
997
998 struct sysctl_ctx_list ctx;
999 struct sysctl_oid *ctrlq_oid;
1000 struct sysctl_oid *fwq_oid;
1001
1002 struct mtx sc_lock;
1003 char lockname[16];
1004
1005 /* Starving free lists */
1006 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
1007 TAILQ_HEAD(, sge_fl) sfl;
1008 struct callout sfl_callout;
1009 struct callout cal_callout;
1010 struct clock_sync cal_info[CNT_CAL_INFO];
1011 int cal_current;
1012 int cal_count;
1013 uint32_t cal_gen;
1014
1015 /*
1016 * Driver code that can run when the adapter is suspended must use this
1017 * lock or a synchronized_op and check for HW_OFF_LIMITS before
1018 * accessing hardware.
1019 *
1020 * XXX: could be changed to rwlock. wlock in suspend/resume and for
1021 * indirect register access, rlock everywhere else.
1022 */
1023 struct mtx reg_lock;
1024
1025 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
1026
1027 struct mtx tc_lock;
1028 struct task tc_task;
1029
1030 struct task fatal_error_task;
1031 struct task reset_task;
1032 const void *reset_thread;
1033 int num_resets;
1034 int incarnation;
1035
1036 const char *last_op;
1037 const void *last_op_thr;
1038 int last_op_flags;
1039
1040 int swintr;
1041 int sensor_resets;
1042
1043 struct callout ktls_tick;
1044 };
1045
1046 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
1047 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
1048 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
1049 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
1050
1051 #define ASSERT_SYNCHRONIZED_OP(sc) \
1052 KASSERT(IS_BUSY(sc) && \
1053 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
1054 ("%s: operation not synchronized.", __func__))
1055
1056 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
1057 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
1058 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
1059 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
1060
1061 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
1062 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
1063 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
1064 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
1065 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
1066
1067 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
1068 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
1069 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
1070 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
1071
1072 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
1073 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
1074 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
1075 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
1076 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
1077
1078 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
1079 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
1080 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
1081 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
1082 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
1083
1084 #define for_each_txq(vi, iter, q) \
1085 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
1086 iter < vi->ntxq; ++iter, ++q)
1087 #define for_each_rxq(vi, iter, q) \
1088 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
1089 iter < vi->nrxq; ++iter, ++q)
1090 #define for_each_ofld_txq(vi, iter, q) \
1091 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
1092 iter < vi->nofldtxq; ++iter, ++q)
1093 #define for_each_ofld_rxq(vi, iter, q) \
1094 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
1095 iter < vi->nofldrxq; ++iter, ++q)
1096 #define for_each_nm_txq(vi, iter, q) \
1097 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
1098 iter < vi->nnmtxq; ++iter, ++q)
1099 #define for_each_nm_rxq(vi, iter, q) \
1100 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
1101 iter < vi->nnmrxq; ++iter, ++q)
1102 #define for_each_vi(_pi, _iter, _vi) \
1103 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
1104 ++(_iter), ++(_vi))
1105
1106 #define IDXINCR(idx, incr, wrap) do { \
1107 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
1108 } while (0)
1109 #define IDXDIFF(head, tail, wrap) \
1110 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1111
1112 /* One for errors, one for firmware events */
1113 #define T4_EXTRA_INTR 2
1114
1115 /* One for firmware events */
1116 #define T4VF_EXTRA_INTR 1
1117
1118 static inline int
forwarding_intr_to_fwq(struct adapter * sc)1119 forwarding_intr_to_fwq(struct adapter *sc)
1120 {
1121
1122 return (sc->intr_count == 1);
1123 }
1124
1125 /* Works reliably inside a synch_op or with reg_lock held. */
1126 static inline bool
hw_off_limits(struct adapter * sc)1127 hw_off_limits(struct adapter *sc)
1128 {
1129 const int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS;
1130
1131 return (__predict_false(off_limits != 0));
1132 }
1133
1134 /* Works reliably inside a synch_op or with reg_lock held. */
1135 static inline bool
hw_all_ok(struct adapter * sc)1136 hw_all_ok(struct adapter *sc)
1137 {
1138 const int not_ok = atomic_load_int(&sc->error_flags) &
1139 (ADAP_STOPPED | HW_OFF_LIMITS);
1140
1141 return (__predict_true(not_ok == 0));
1142 }
1143
1144 static inline int
mbuf_nsegs(struct mbuf * m)1145 mbuf_nsegs(struct mbuf *m)
1146 {
1147 M_ASSERTPKTHDR(m);
1148 KASSERT(m->m_pkthdr.inner_l5hlen > 0,
1149 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1150
1151 return (m->m_pkthdr.inner_l5hlen);
1152 }
1153
1154 static inline void
set_mbuf_nsegs(struct mbuf * m,uint8_t nsegs)1155 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1156 {
1157 M_ASSERTPKTHDR(m);
1158 m->m_pkthdr.inner_l5hlen = nsegs;
1159 }
1160
1161 /* Internal mbuf flags stored in PH_loc.eight[1]. */
1162 #define MC_NOMAP 0x01
1163 #define MC_RAW_WR 0x02
1164 #define MC_TLS 0x04
1165
1166 static inline int
mbuf_cflags(struct mbuf * m)1167 mbuf_cflags(struct mbuf *m)
1168 {
1169 M_ASSERTPKTHDR(m);
1170 return (m->m_pkthdr.PH_loc.eight[4]);
1171 }
1172
1173 static inline void
set_mbuf_cflags(struct mbuf * m,uint8_t flags)1174 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
1175 {
1176 M_ASSERTPKTHDR(m);
1177 m->m_pkthdr.PH_loc.eight[4] = flags;
1178 }
1179
1180 static inline int
mbuf_len16(struct mbuf * m)1181 mbuf_len16(struct mbuf *m)
1182 {
1183 int n;
1184
1185 M_ASSERTPKTHDR(m);
1186 n = m->m_pkthdr.PH_loc.eight[0];
1187 if (!(mbuf_cflags(m) & MC_TLS))
1188 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1189
1190 return (n);
1191 }
1192
1193 static inline void
set_mbuf_len16(struct mbuf * m,uint8_t len16)1194 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1195 {
1196 M_ASSERTPKTHDR(m);
1197 if (!(mbuf_cflags(m) & MC_TLS))
1198 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
1199 m->m_pkthdr.PH_loc.eight[0] = len16;
1200 }
1201
1202 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)1203 t4_read_reg(struct adapter *sc, uint32_t reg)
1204 {
1205 if (hw_off_limits(sc))
1206 MPASS(curthread == sc->reset_thread);
1207 return bus_space_read_4(sc->bt, sc->bh, reg);
1208 }
1209
1210 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)1211 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1212 {
1213 if (hw_off_limits(sc))
1214 MPASS(curthread == sc->reset_thread);
1215 bus_space_write_4(sc->bt, sc->bh, reg, val);
1216 }
1217
1218 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)1219 t4_read_reg64(struct adapter *sc, uint32_t reg)
1220 {
1221 if (hw_off_limits(sc))
1222 MPASS(curthread == sc->reset_thread);
1223 #ifdef __LP64__
1224 return bus_space_read_8(sc->bt, sc->bh, reg);
1225 #else
1226 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1227 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1228
1229 #endif
1230 }
1231
1232 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)1233 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1234 {
1235 if (hw_off_limits(sc))
1236 MPASS(curthread == sc->reset_thread);
1237 #ifdef __LP64__
1238 bus_space_write_8(sc->bt, sc->bh, reg, val);
1239 #else
1240 bus_space_write_4(sc->bt, sc->bh, reg, val);
1241 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1242 #endif
1243 }
1244
1245 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)1246 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1247 {
1248 if (hw_off_limits(sc))
1249 MPASS(curthread == sc->reset_thread);
1250 *val = pci_read_config(sc->dev, reg, 1);
1251 }
1252
1253 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)1254 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1255 {
1256 if (hw_off_limits(sc))
1257 MPASS(curthread == sc->reset_thread);
1258 pci_write_config(sc->dev, reg, val, 1);
1259 }
1260
1261 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)1262 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1263 {
1264
1265 if (hw_off_limits(sc))
1266 MPASS(curthread == sc->reset_thread);
1267 *val = pci_read_config(sc->dev, reg, 2);
1268 }
1269
1270 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)1271 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1272 {
1273 if (hw_off_limits(sc))
1274 MPASS(curthread == sc->reset_thread);
1275 pci_write_config(sc->dev, reg, val, 2);
1276 }
1277
1278 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)1279 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1280 {
1281 if (hw_off_limits(sc))
1282 MPASS(curthread == sc->reset_thread);
1283 *val = pci_read_config(sc->dev, reg, 4);
1284 }
1285
1286 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)1287 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1288 {
1289 if (hw_off_limits(sc))
1290 MPASS(curthread == sc->reset_thread);
1291 pci_write_config(sc->dev, reg, val, 4);
1292 }
1293
1294 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)1295 adap2pinfo(struct adapter *sc, int idx)
1296 {
1297
1298 return (sc->port[idx]);
1299 }
1300
1301 static inline void
t4_os_set_hw_addr(struct port_info * pi,uint8_t hw_addr[])1302 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1303 {
1304
1305 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1306 }
1307
1308 static inline int
tx_resume_threshold(struct sge_eq * eq)1309 tx_resume_threshold(struct sge_eq *eq)
1310 {
1311
1312 /* not quite the same as qsize / 4, but this will do. */
1313 return (eq->sidx / 4);
1314 }
1315
1316 static inline int
t4_use_ldst(struct adapter * sc)1317 t4_use_ldst(struct adapter *sc)
1318 {
1319
1320 #ifdef notyet
1321 return (sc->flags & FW_OK || !sc->use_bd);
1322 #else
1323 return (0);
1324 #endif
1325 }
1326
1327 static inline void
CH_DUMP_MBOX(struct adapter * sc,int mbox,const int reg,const char * msg,const __be64 * const p,const bool err)1328 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1329 const char *msg, const __be64 *const p, const bool err)
1330 {
1331
1332 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1333 return;
1334 if (p != NULL) {
1335 log(err ? LOG_ERR : LOG_DEBUG,
1336 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1337 "%016llx %016llx %016llx %016llx\n",
1338 device_get_nameunit(sc->dev), mbox, msg,
1339 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1340 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1341 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1342 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1343 } else {
1344 log(err ? LOG_ERR : LOG_DEBUG,
1345 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1346 "%016llx %016llx %016llx %016llx\n",
1347 device_get_nameunit(sc->dev), mbox, msg,
1348 (long long)t4_read_reg64(sc, reg),
1349 (long long)t4_read_reg64(sc, reg + 8),
1350 (long long)t4_read_reg64(sc, reg + 16),
1351 (long long)t4_read_reg64(sc, reg + 24),
1352 (long long)t4_read_reg64(sc, reg + 32),
1353 (long long)t4_read_reg64(sc, reg + 40),
1354 (long long)t4_read_reg64(sc, reg + 48),
1355 (long long)t4_read_reg64(sc, reg + 56));
1356 }
1357 }
1358
1359 /* t4_main.c */
1360 extern int t4_ntxq;
1361 extern int t4_nrxq;
1362 extern int t4_intr_types;
1363 extern int t4_tmr_idx;
1364 extern int t4_pktc_idx;
1365 extern unsigned int t4_qsize_rxq;
1366 extern unsigned int t4_qsize_txq;
1367 extern int t4_ddp_rcvbuf_len;
1368 extern unsigned int t4_ddp_rcvbuf_cache;
1369 extern device_method_t cxgbe_methods[];
1370
1371 int t4_os_find_pci_capability(struct adapter *, int);
1372 void t4_os_portmod_changed(struct port_info *);
1373 void t4_os_link_changed(struct port_info *);
1374 void t4_iterate(void (*)(struct adapter *, void *), void *);
1375 void t4_init_devnames(struct adapter *);
1376 void t4_add_adapter(struct adapter *);
1377 int t4_detach_common(device_t);
1378 int t4_map_bars_0_and_4(struct adapter *);
1379 int t4_map_bar_2(struct adapter *);
1380 int t4_adj_doorbells(struct adapter *);
1381 int t4_setup_intr_handlers(struct adapter *);
1382 void t4_sysctls(struct adapter *);
1383 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1384 void end_synchronized_op(struct adapter *, int);
1385 void begin_vi_detach(struct adapter *, struct vi_info *);
1386 void end_vi_detach(struct adapter *, struct vi_info *);
1387 int update_mac_settings(if_t, int);
1388 int adapter_init(struct adapter *);
1389 int vi_init(struct vi_info *);
1390 void vi_sysctls(struct vi_info *);
1391 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1392 int alloc_atid(struct adapter *, void *);
1393 void *lookup_atid(struct adapter *, int);
1394 void free_atid(struct adapter *, int);
1395 void release_tid(struct adapter *, int, struct sge_wrq *);
1396 int cxgbe_media_change(if_t);
1397 void cxgbe_media_status(if_t, struct ifmediareq *);
1398 void t4_os_cim_err(struct adapter *);
1399 int suspend_adapter(struct adapter *);
1400 int resume_adapter(struct adapter *);
1401 int toe_capability(struct vi_info *, bool);
1402
1403 #ifdef KERN_TLS
1404 /* t6_kern_tls.c */
1405 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *,
1406 struct m_snd_tag **);
1407 void t6_ktls_modload(void);
1408 void t6_ktls_modunload(void);
1409 int t6_ktls_try(if_t, struct socket *, struct ktls_session *);
1410 int t6_ktls_parse_pkt(struct mbuf *);
1411 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int);
1412 #endif
1413
1414 /* t4_keyctx.c */
1415 struct auth_hash;
1416 union authctx;
1417 #ifdef KERN_TLS
1418 struct ktls_session;
1419 struct tls_key_req;
1420 struct tls_keyctx;
1421 #endif
1422
1423 void t4_aes_getdeckey(void *, const void *, unsigned int);
1424 void t4_copy_partial_hash(int, union authctx *, void *);
1425 void t4_init_gmac_hash(const char *, int, char *);
1426 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int,
1427 char *);
1428 #ifdef KERN_TLS
1429 u_int t4_tls_key_info_size(const struct ktls_session *);
1430 int t4_tls_proto_ver(const struct ktls_session *);
1431 int t4_tls_cipher_mode(const struct ktls_session *);
1432 int t4_tls_auth_mode(const struct ktls_session *);
1433 int t4_tls_hmac_ctrl(const struct ktls_session *);
1434 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *);
1435 int t4_alloc_tls_keyid(struct adapter *);
1436 void t4_free_tls_keyid(struct adapter *, int);
1437 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int,
1438 struct tls_key_req *);
1439 #endif
1440
1441 #ifdef DEV_NETMAP
1442 /* t4_netmap.c */
1443 struct sge_nm_rxq;
1444 void cxgbe_nm_attach(struct vi_info *);
1445 void cxgbe_nm_detach(struct vi_info *);
1446 void service_nm_rxq(struct sge_nm_rxq *);
1447 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int);
1448 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
1449 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int);
1450 int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
1451 #endif
1452
1453 /* t4_sge.c */
1454 void t4_sge_modload(void);
1455 void t4_sge_modunload(void);
1456 uint64_t t4_sge_extfree_refs(void);
1457 void t4_tweak_chip_settings(struct adapter *);
1458 int t4_verify_chip_settings(struct adapter *);
1459 void t4_init_rx_buf_info(struct adapter *);
1460 int t4_create_dma_tag(struct adapter *);
1461 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1462 struct sysctl_oid_list *);
1463 int t4_destroy_dma_tag(struct adapter *);
1464 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
1465 bus_addr_t *, void **);
1466 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1467 void *);
1468 void free_fl_buffers(struct adapter *, struct sge_fl *);
1469 int t4_setup_adapter_queues(struct adapter *);
1470 int t4_teardown_adapter_queues(struct adapter *);
1471 int t4_setup_vi_queues(struct vi_info *);
1472 int t4_teardown_vi_queues(struct vi_info *);
1473 void t4_intr_all(void *);
1474 void t4_intr(void *);
1475 #ifdef DEV_NETMAP
1476 void t4_nm_intr(void *);
1477 void t4_vi_intr(void *);
1478 #endif
1479 void t4_intr_err(void *);
1480 void t4_intr_evt(void *);
1481 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1482 void t4_update_fl_bufsize(if_t);
1483 struct mbuf *alloc_wr_mbuf(int, int);
1484 int parse_pkt(struct mbuf **, bool);
1485 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1486 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1487 int t4_sge_set_conm_context(struct adapter *, int, int, int);
1488 void t4_register_an_handler(an_handler_t);
1489 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1490 void t4_register_cpl_handler(int, cpl_handler_t);
1491 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1492 #ifdef RATELIMIT
1493 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1494 #endif
1495
1496 /* t4_tracer.c */
1497 struct t4_tracer;
1498 void t4_tracer_modload(void);
1499 void t4_tracer_modunload(void);
1500 void t4_tracer_port_detach(struct adapter *);
1501 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1502 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1503 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1504 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1505
1506 /* t4_sched.c */
1507 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1508 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1509 int t4_init_tx_sched(struct adapter *);
1510 int t4_free_tx_sched(struct adapter *);
1511 void t4_update_tx_sched(struct adapter *);
1512 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1513 void t4_release_cl_rl(struct adapter *, int, int);
1514 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1515 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1516 #ifdef RATELIMIT
1517 void t4_init_etid_table(struct adapter *);
1518 void t4_free_etid_table(struct adapter *);
1519 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1520 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *,
1521 struct m_snd_tag **);
1522 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1523 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *);
1524 #endif
1525
1526 /* t4_filter.c */
1527 int get_filter_mode(struct adapter *, uint32_t *);
1528 int set_filter_mode(struct adapter *, uint32_t);
1529 int set_filter_mask(struct adapter *, uint32_t);
1530 int get_filter(struct adapter *, struct t4_filter *);
1531 int set_filter(struct adapter *, struct t4_filter *);
1532 int del_filter(struct adapter *, struct t4_filter *);
1533 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1534 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1535 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1536 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1537 void free_hftid_hash(struct tid_info *);
1538
1539 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1540 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1541 {
1542 int len = offsetof(struct wrqe, wr) + wr_len;
1543 struct wrqe *wr;
1544
1545 wr = malloc(len, M_CXGBE, M_NOWAIT);
1546 if (__predict_false(wr == NULL))
1547 return (NULL);
1548 wr->wr_len = wr_len;
1549 wr->wrq = wrq;
1550 return (wr);
1551 }
1552
1553 static inline void *
wrtod(struct wrqe * wr)1554 wrtod(struct wrqe *wr)
1555 {
1556 return (&wr->wr[0]);
1557 }
1558
1559 static inline void
free_wrqe(struct wrqe * wr)1560 free_wrqe(struct wrqe *wr)
1561 {
1562 free(wr, M_CXGBE);
1563 }
1564
1565 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1566 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1567 {
1568 struct sge_wrq *wrq = wr->wrq;
1569
1570 TXQ_LOCK(wrq);
1571 if (__predict_true(wrq->eq.flags & EQ_HW_ALLOCATED))
1572 t4_wrq_tx_locked(sc, wrq, wr);
1573 else
1574 free(wr, M_CXGBE);
1575 TXQ_UNLOCK(wrq);
1576 }
1577
1578 static inline int
read_via_memwin(struct adapter * sc,int idx,uint32_t addr,uint32_t * val,int len)1579 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1580 int len)
1581 {
1582
1583 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1584 }
1585
1586 static inline int
write_via_memwin(struct adapter * sc,int idx,uint32_t addr,const uint32_t * val,int len)1587 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1588 const uint32_t *val, int len)
1589 {
1590
1591 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1592 }
1593
1594 /* Number of len16 -> number of descriptors */
1595 static inline int
tx_len16_to_desc(int len16)1596 tx_len16_to_desc(int len16)
1597 {
1598
1599 return (howmany(len16, EQ_ESIZE / 16));
1600 }
1601 #endif
1602