1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2021 Intel Corporation */
3 #include "adf_accel_devices.h"
4 #include "adf_common_drv.h"
5 #include "adf_gen4_hw_data.h"
6
7 #define ADF_RPRESET_TIMEOUT_MS 5000
8 #define ADF_RPRESET_POLLING_INTERVAL 20
9
10 static u64
build_csr_ring_base_addr(bus_addr_t addr,u32 size)11 build_csr_ring_base_addr(bus_addr_t addr, u32 size)
12 {
13 return BUILD_RING_BASE_ADDR(addr, size);
14 }
15
16 static u32
read_csr_ring_head(struct resource * csr_base_addr,u32 bank,u32 ring)17 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring)
18 {
19 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
20 }
21
22 static void
write_csr_ring_head(struct resource * csr_base_addr,u32 bank,u32 ring,u32 value)23 write_csr_ring_head(struct resource *csr_base_addr,
24 u32 bank,
25 u32 ring,
26 u32 value)
27 {
28 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
29 }
30
31 static u32
read_csr_ring_tail(struct resource * csr_base_addr,u32 bank,u32 ring)32 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring)
33 {
34 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
35 }
36
37 static void
write_csr_ring_tail(struct resource * csr_base_addr,u32 bank,u32 ring,u32 value)38 write_csr_ring_tail(struct resource *csr_base_addr,
39 u32 bank,
40 u32 ring,
41 u32 value)
42 {
43 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
44 }
45
46 static u32
read_csr_e_stat(struct resource * csr_base_addr,u32 bank)47 read_csr_e_stat(struct resource *csr_base_addr, u32 bank)
48 {
49 return READ_CSR_E_STAT(csr_base_addr, bank);
50 }
51
52 static void
write_csr_ring_config(struct resource * csr_base_addr,u32 bank,u32 ring,u32 value)53 write_csr_ring_config(struct resource *csr_base_addr,
54 u32 bank,
55 u32 ring,
56 u32 value)
57 {
58 WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
59 }
60
61 static bus_addr_t
read_csr_ring_base(struct resource * csr_base_addr,u32 bank,u32 ring)62 read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring)
63 {
64 return READ_CSR_RING_BASE(csr_base_addr, bank, ring);
65 }
66
67 static void
write_csr_ring_base(struct resource * csr_base_addr,u32 bank,u32 ring,bus_addr_t addr)68 write_csr_ring_base(struct resource *csr_base_addr,
69 u32 bank,
70 u32 ring,
71 bus_addr_t addr)
72 {
73 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
74 }
75
76 static void
write_csr_int_flag(struct resource * csr_base_addr,u32 bank,u32 value)77 write_csr_int_flag(struct resource *csr_base_addr, u32 bank, u32 value)
78 {
79 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
80 }
81
82 static void
write_csr_int_srcsel(struct resource * csr_base_addr,u32 bank)83 write_csr_int_srcsel(struct resource *csr_base_addr, u32 bank)
84 {
85 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
86 }
87
88 static void
write_csr_int_col_en(struct resource * csr_base_addr,u32 bank,u32 value)89 write_csr_int_col_en(struct resource *csr_base_addr, u32 bank, u32 value)
90 {
91 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
92 }
93
94 static void
write_csr_int_col_ctl(struct resource * csr_base_addr,u32 bank,u32 value)95 write_csr_int_col_ctl(struct resource *csr_base_addr, u32 bank, u32 value)
96 {
97 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
98 }
99
100 static void
write_csr_int_flag_and_col(struct resource * csr_base_addr,u32 bank,u32 value)101 write_csr_int_flag_and_col(struct resource *csr_base_addr, u32 bank, u32 value)
102 {
103 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
104 }
105
106 static u32
read_csr_ring_srv_arb_en(struct resource * csr_base_addr,u32 bank)107 read_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank)
108 {
109 return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);
110 }
111
112 static void
write_csr_ring_srv_arb_en(struct resource * csr_base_addr,u32 bank,u32 value)113 write_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank, u32 value)
114 {
115 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
116 }
117
118 static u32
get_int_col_ctl_enable_mask(void)119 get_int_col_ctl_enable_mask(void)
120 {
121 return ADF_RING_CSR_INT_COL_CTL_ENABLE;
122 }
123
124 void
adf_gen4_init_hw_csr_info(struct adf_hw_csr_info * csr_info)125 adf_gen4_init_hw_csr_info(struct adf_hw_csr_info *csr_info)
126 {
127 struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops;
128
129 csr_info->arb_enable_mask = 0x1;
130
131 csr_info->csr_addr_offset = ADF_RING_CSR_ADDR_OFFSET;
132 csr_info->ring_bundle_size = ADF_RING_BUNDLE_SIZE;
133
134 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
135 csr_ops->read_csr_ring_head = read_csr_ring_head;
136 csr_ops->write_csr_ring_head = write_csr_ring_head;
137 csr_ops->read_csr_ring_tail = read_csr_ring_tail;
138 csr_ops->write_csr_ring_tail = write_csr_ring_tail;
139 csr_ops->read_csr_e_stat = read_csr_e_stat;
140 csr_ops->write_csr_ring_config = write_csr_ring_config;
141 csr_ops->read_csr_ring_base = read_csr_ring_base;
142 csr_ops->write_csr_ring_base = write_csr_ring_base;
143 csr_ops->write_csr_int_flag = write_csr_int_flag;
144 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
145 csr_ops->write_csr_int_col_en = write_csr_int_col_en;
146 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
147 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
148 csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en;
149 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
150 csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask;
151 }
152
153 static int
reset_ring_pair(struct resource * csr,u32 bank_number)154 reset_ring_pair(struct resource *csr, u32 bank_number)
155 {
156 int reset_timeout = ADF_RPRESET_TIMEOUT_MS;
157 const int timeout_step = ADF_RPRESET_POLLING_INTERVAL;
158 u32 val;
159
160 /* Write rpresetctl register bit#0 as 1
161 * As rpresetctl registers have no RW bits, no need to preserve
162 * values for other bits, just write bit#0
163 * NOTE: bit#12-bit#31 are WO, the write operation only takes
164 * effect when bit#1 is written 1 for pasid level reset
165 */
166 ADF_CSR_WR(csr,
167 ADF_WQM_CSR_RPRESETCTL(bank_number),
168 BIT(ADF_WQM_CSR_RPRESETCTL_SHIFT));
169
170 /* Read rpresetsts register to wait for rp reset complete */
171 while (reset_timeout > 0) {
172 val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number));
173 if (val & ADF_WQM_CSR_RPRESETSTS_MASK)
174 break;
175 pause_ms("adfstop", timeout_step);
176 reset_timeout -= timeout_step;
177 }
178 if (reset_timeout <= 0)
179 return EFAULT;
180
181 /* When rp reset is done, clear rpresetsts bit0 */
182 ADF_CSR_WR(csr,
183 ADF_WQM_CSR_RPRESETSTS(bank_number),
184 BIT(ADF_WQM_CSR_RPRESETSTS_SHIFT));
185 return 0;
186 }
187
188 int
adf_gen4_ring_pair_reset(struct adf_accel_dev * accel_dev,u32 bank_number)189 adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number)
190 {
191 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
192 u32 etr_bar_id = hw_data->get_etr_bar_id(hw_data);
193 struct resource *csr;
194 int ret;
195
196 if (bank_number >= hw_data->num_banks)
197 return -EINVAL;
198
199 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr;
200
201 ret = reset_ring_pair(csr, bank_number);
202 if (ret)
203 device_printf(GET_DEV(accel_dev),
204 "ring pair reset failure (timeout)\n");
205
206 return ret;
207 }
208
209 static inline void
adf_gen4_unpack_ssm_wdtimer(u64 value,u32 * upper,u32 * lower)210 adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper, u32 *lower)
211 {
212 *lower = lower_32_bits(value);
213 *upper = upper_32_bits(value);
214 }
215
216 int
adf_gen4_set_ssm_wdtimer(struct adf_accel_dev * accel_dev)217 adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
218 {
219 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
220 u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
221 u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
222 u32 ssm_wdt_pke_high = 0;
223 u32 ssm_wdt_pke_low = 0;
224 u32 ssm_wdt_high = 0;
225 u32 ssm_wdt_low = 0;
226 struct resource *pmisc_addr;
227 struct adf_bar *pmisc;
228 int pmisc_id;
229
230 pmisc_id = hw_data->get_misc_bar_id(hw_data);
231 pmisc = &GET_BARS(accel_dev)[pmisc_id];
232 pmisc_addr = pmisc->virt_addr;
233
234 /* Convert 64bit WDT timer value into 32bit values for
235 * mmio write to 32bit CSRs.
236 */
237 adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low);
238 adf_gen4_unpack_ssm_wdtimer(timer_val_pke,
239 &ssm_wdt_pke_high,
240 &ssm_wdt_pke_low);
241
242 /* Enable WDT for sym and dc */
243 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low);
244 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high);
245 /* Enable WDT for pke */
246 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low);
247 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high);
248
249 return 0;
250 }
251
252 int
adf_pfvf_comms_disabled(struct adf_accel_dev * accel_dev)253 adf_pfvf_comms_disabled(struct adf_accel_dev *accel_dev)
254 {
255 return 0;
256 }
257