1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Timberdale FPGA GPIO driver
4 * Author: Mocean Laboratories
5 * Copyright (c) 2009 Intel Corporation
6 */
7
8 /* Supports:
9 * Timberdale FPGA GPIO
10 */
11
12 #include <linux/init.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/platform_device.h>
15 #include <linux/irq.h>
16 #include <linux/io.h>
17 #include <linux/timb_gpio.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20
21 #define DRIVER_NAME "timb-gpio"
22
23 #define TGPIOVAL 0x00
24 #define TGPIODIR 0x04
25 #define TGPIO_IER 0x08
26 #define TGPIO_ISR 0x0c
27 #define TGPIO_IPR 0x10
28 #define TGPIO_ICR 0x14
29 #define TGPIO_FLR 0x18
30 #define TGPIO_LVR 0x1c
31 #define TGPIO_VER 0x20
32 #define TGPIO_BFLR 0x24
33
34 struct timbgpio {
35 void __iomem *membase;
36 spinlock_t lock; /* mutual exclusion */
37 struct gpio_chip gpio;
38 int irq_base;
39 unsigned long last_ier;
40 };
41
timbgpio_update_bit(struct gpio_chip * gpio,unsigned index,unsigned offset,bool enabled)42 static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
43 unsigned offset, bool enabled)
44 {
45 struct timbgpio *tgpio = gpiochip_get_data(gpio);
46 unsigned long flags;
47 u32 reg;
48
49 spin_lock_irqsave(&tgpio->lock, flags);
50 reg = ioread32(tgpio->membase + offset);
51
52 if (enabled)
53 reg |= (1 << index);
54 else
55 reg &= ~(1 << index);
56
57 iowrite32(reg, tgpio->membase + offset);
58 spin_unlock_irqrestore(&tgpio->lock, flags);
59
60 return 0;
61 }
62
timbgpio_gpio_direction_input(struct gpio_chip * gpio,unsigned nr)63 static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
64 {
65 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
66 }
67
timbgpio_gpio_get(struct gpio_chip * gpio,unsigned nr)68 static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
69 {
70 struct timbgpio *tgpio = gpiochip_get_data(gpio);
71 u32 value;
72
73 value = ioread32(tgpio->membase + TGPIOVAL);
74 return (value & (1 << nr)) ? 1 : 0;
75 }
76
timbgpio_gpio_direction_output(struct gpio_chip * gpio,unsigned nr,int val)77 static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
78 unsigned nr, int val)
79 {
80 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
81 }
82
timbgpio_gpio_set(struct gpio_chip * gpio,unsigned nr,int val)83 static void timbgpio_gpio_set(struct gpio_chip *gpio,
84 unsigned nr, int val)
85 {
86 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
87 }
88
timbgpio_to_irq(struct gpio_chip * gpio,unsigned offset)89 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
90 {
91 struct timbgpio *tgpio = gpiochip_get_data(gpio);
92
93 if (tgpio->irq_base <= 0)
94 return -EINVAL;
95
96 return tgpio->irq_base + offset;
97 }
98
99 /*
100 * GPIO IRQ
101 */
timbgpio_irq_disable(struct irq_data * d)102 static void timbgpio_irq_disable(struct irq_data *d)
103 {
104 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
105 int offset = d->irq - tgpio->irq_base;
106 irq_hw_number_t hwirq = irqd_to_hwirq(d);
107 unsigned long flags;
108
109 spin_lock_irqsave(&tgpio->lock, flags);
110 tgpio->last_ier &= ~(1UL << offset);
111 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
112 spin_unlock_irqrestore(&tgpio->lock, flags);
113
114 gpiochip_disable_irq(&tgpio->gpio, hwirq);
115 }
116
timbgpio_irq_enable(struct irq_data * d)117 static void timbgpio_irq_enable(struct irq_data *d)
118 {
119 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
120 int offset = d->irq - tgpio->irq_base;
121 irq_hw_number_t hwirq = irqd_to_hwirq(d);
122 unsigned long flags;
123
124 gpiochip_enable_irq(&tgpio->gpio, hwirq);
125
126 spin_lock_irqsave(&tgpio->lock, flags);
127 tgpio->last_ier |= 1UL << offset;
128 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
129 spin_unlock_irqrestore(&tgpio->lock, flags);
130 }
131
timbgpio_irq_type(struct irq_data * d,unsigned trigger)132 static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
133 {
134 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
135 int offset = d->irq - tgpio->irq_base;
136 unsigned long flags;
137 u32 lvr, flr, bflr = 0;
138 u32 ver;
139 int ret = 0;
140
141 if (offset < 0 || offset > tgpio->gpio.ngpio)
142 return -EINVAL;
143
144 ver = ioread32(tgpio->membase + TGPIO_VER);
145
146 spin_lock_irqsave(&tgpio->lock, flags);
147
148 lvr = ioread32(tgpio->membase + TGPIO_LVR);
149 flr = ioread32(tgpio->membase + TGPIO_FLR);
150 if (ver > 2)
151 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
152
153 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
154 bflr &= ~(1 << offset);
155 flr &= ~(1 << offset);
156 if (trigger & IRQ_TYPE_LEVEL_HIGH)
157 lvr |= 1 << offset;
158 else
159 lvr &= ~(1 << offset);
160 }
161
162 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
163 if (ver < 3) {
164 ret = -EINVAL;
165 goto out;
166 } else {
167 flr |= 1 << offset;
168 bflr |= 1 << offset;
169 }
170 } else {
171 bflr &= ~(1 << offset);
172 flr |= 1 << offset;
173 if (trigger & IRQ_TYPE_EDGE_FALLING)
174 lvr &= ~(1 << offset);
175 else
176 lvr |= 1 << offset;
177 }
178
179 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
180 iowrite32(flr, tgpio->membase + TGPIO_FLR);
181 if (ver > 2)
182 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
183
184 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
185
186 out:
187 spin_unlock_irqrestore(&tgpio->lock, flags);
188 return ret;
189 }
190
timbgpio_irq(struct irq_desc * desc)191 static void timbgpio_irq(struct irq_desc *desc)
192 {
193 struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
194 struct irq_data *data = irq_desc_get_irq_data(desc);
195 unsigned long ipr;
196 int offset;
197
198 data->chip->irq_ack(data);
199 ipr = ioread32(tgpio->membase + TGPIO_IPR);
200 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
201
202 /*
203 * Some versions of the hardware trash the IER register if more than
204 * one interrupt is received simultaneously.
205 */
206 iowrite32(0, tgpio->membase + TGPIO_IER);
207
208 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
209 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
210
211 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
212 }
213
214 static const struct irq_chip timbgpio_irqchip = {
215 .name = "GPIO",
216 .irq_enable = timbgpio_irq_enable,
217 .irq_disable = timbgpio_irq_disable,
218 .irq_set_type = timbgpio_irq_type,
219 .flags = IRQCHIP_IMMUTABLE,
220 GPIOCHIP_IRQ_RESOURCE_HELPERS,
221 };
222
timbgpio_probe(struct platform_device * pdev)223 static int timbgpio_probe(struct platform_device *pdev)
224 {
225 int err, i;
226 struct device *dev = &pdev->dev;
227 struct gpio_chip *gc;
228 struct timbgpio *tgpio;
229 struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
230 int irq = platform_get_irq(pdev, 0);
231
232 if (!pdata || pdata->nr_pins > 32) {
233 dev_err(dev, "Invalid platform data\n");
234 return -EINVAL;
235 }
236
237 tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
238 if (!tgpio)
239 return -EINVAL;
240
241 tgpio->irq_base = pdata->irq_base;
242
243 spin_lock_init(&tgpio->lock);
244
245 tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
246 if (IS_ERR(tgpio->membase))
247 return PTR_ERR(tgpio->membase);
248
249 gc = &tgpio->gpio;
250
251 gc->label = dev_name(&pdev->dev);
252 gc->owner = THIS_MODULE;
253 gc->parent = &pdev->dev;
254 gc->direction_input = timbgpio_gpio_direction_input;
255 gc->get = timbgpio_gpio_get;
256 gc->direction_output = timbgpio_gpio_direction_output;
257 gc->set = timbgpio_gpio_set;
258 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
259 gc->dbg_show = NULL;
260 gc->base = pdata->gpio_base;
261 gc->ngpio = pdata->nr_pins;
262 gc->can_sleep = false;
263
264 err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
265 if (err)
266 return err;
267
268 /* make sure to disable interrupts */
269 iowrite32(0x0, tgpio->membase + TGPIO_IER);
270
271 if (irq < 0 || tgpio->irq_base <= 0)
272 return 0;
273
274 for (i = 0; i < pdata->nr_pins; i++) {
275 irq_set_chip_and_handler(tgpio->irq_base + i,
276 &timbgpio_irqchip, handle_simple_irq);
277 irq_set_chip_data(tgpio->irq_base + i, tgpio);
278 irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
279 }
280
281 irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
282
283 return 0;
284 }
285
286 static struct platform_driver timbgpio_platform_driver = {
287 .driver = {
288 .name = DRIVER_NAME,
289 .suppress_bind_attrs = true,
290 },
291 .probe = timbgpio_probe,
292 };
293
294 /*--------------------------------------------------------------------------*/
295
296 builtin_platform_driver(timbgpio_platform_driver);
297