1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/gpio.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
42 #include <sys/lock.h>
43 #include <sys/mutex.h>
44
45 #include <arm/ti/ti_cpuid.h>
46 #include <arm/ti/ti_sysc.h>
47 #include "gpio_if.h"
48
49 #include <dev/clk/clk.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52
53 #include <dev/mmc/bridge.h>
54 #include <dev/mmc/mmcreg.h>
55 #include <dev/mmc/mmcbrvar.h>
56
57 #include <dev/sdhci/sdhci.h>
58 #include <dev/sdhci/sdhci_fdt_gpio.h>
59 #include "sdhci_if.h"
60
61 #include <machine/bus.h>
62 #include <machine/resource.h>
63 #include <machine/intr.h>
64
65 #include "opt_mmccam.h"
66
67 struct ti_sdhci_softc {
68 device_t dev;
69 struct sdhci_fdt_gpio * gpio;
70 struct resource * mem_res;
71 struct resource * irq_res;
72 void * intr_cookie;
73 struct sdhci_slot slot;
74 uint32_t mmchs_reg_off;
75 uint32_t sdhci_reg_off;
76 uint64_t baseclk_hz;
77 uint32_t cmd_and_mode;
78 uint32_t sdhci_clkdiv;
79 boolean_t disable_highspeed;
80 boolean_t force_card_present;
81 boolean_t disable_readonly;
82 };
83
84 /*
85 * Table of supported FDT compat strings.
86 *
87 * Note that "ti,mmchs" is our own invention, and should be phased out in favor
88 * of the documented names.
89 *
90 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
91 */
92 static struct ofw_compat_data compat_data[] = {
93 {"ti,am335-sdhci", 1},
94 {"ti,omap3-hsmmc", 1},
95 {"ti,omap4-hsmmc", 1},
96 {"ti,mmchs", 1},
97 {NULL, 0},
98 };
99
100 /*
101 * The MMCHS hardware has a few control and status registers at the beginning of
102 * the device's memory map, followed by the standard sdhci register block.
103 * Different SoCs have the register blocks at different offsets from the
104 * beginning of the device. Define some constants to map out the registers we
105 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
106 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
107 */
108 #define OMAP3_MMCHS_REG_OFFSET 0x000
109 #define OMAP4_MMCHS_REG_OFFSET 0x100
110 #define AM335X_MMCHS_REG_OFFSET 0x100
111 #define SDHCI_REG_OFFSET 0x100
112
113 #define MMCHS_SYSCONFIG 0x010
114 #define MMCHS_SYSCONFIG_RESET (1 << 1)
115 #define MMCHS_SYSSTATUS 0x014
116 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
117 #define MMCHS_CON 0x02C
118 #define MMCHS_CON_DW8 (1 << 5)
119 #define MMCHS_CON_DVAL_8_4MS (3 << 9)
120 #define MMCHS_CON_OD (1 << 0)
121 #define MMCHS_SYSCTL 0x12C
122 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF
123 #define MMCHS_SYSCTL_CLKD_SHIFT 6
124 #define MMCHS_SD_CAPA 0x140
125 #define MMCHS_SD_CAPA_VS18 (1 << 26)
126 #define MMCHS_SD_CAPA_VS30 (1 << 25)
127 #define MMCHS_SD_CAPA_VS33 (1 << 24)
128
129 /* Forward declarations, CAM-relataed */
130 // static void ti_sdhci_cam_poll(struct cam_sim *);
131 // static void ti_sdhci_cam_action(struct cam_sim *, union ccb *);
132 // static int ti_sdhci_cam_settran_settings(struct ti_sdhci_softc *sc, union ccb *);
133
134 static inline uint32_t
ti_mmchs_read_4(struct ti_sdhci_softc * sc,bus_size_t off)135 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
136 {
137
138 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
139 }
140
141 static inline void
ti_mmchs_write_4(struct ti_sdhci_softc * sc,bus_size_t off,uint32_t val)142 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
143 {
144
145 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
146 }
147
148 static inline uint32_t
RD4(struct ti_sdhci_softc * sc,bus_size_t off)149 RD4(struct ti_sdhci_softc *sc, bus_size_t off)
150 {
151
152 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
153 }
154
155 static inline void
WR4(struct ti_sdhci_softc * sc,bus_size_t off,uint32_t val)156 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
157 {
158
159 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
160 }
161
162 static uint8_t
ti_sdhci_read_1(device_t dev,struct sdhci_slot * slot,bus_size_t off)163 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
164 {
165 struct ti_sdhci_softc *sc = device_get_softc(dev);
166
167 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
168 }
169
170 static uint16_t
ti_sdhci_read_2(device_t dev,struct sdhci_slot * slot,bus_size_t off)171 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
172 {
173 struct ti_sdhci_softc *sc = device_get_softc(dev);
174 uint32_t clkdiv, val32;
175
176 /*
177 * The MMCHS hardware has a non-standard interpretation of the sdclock
178 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6)
179 * but doesn't split them into low:high fields. Instead they're a
180 * single number in the range 0..1023 and the number is exactly the
181 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
182 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking
183 * here extracts the MMCHS representation from the hardware word, cleans
184 * those bits out, applies the 2N adjustment, and plugs the result into
185 * the bit positions for the 2.0 or 3.0 divisor in the returned register
186 * value. The ti_sdhci_write_2() routine performs the opposite
187 * transformation when the SDHCI driver writes to the register.
188 */
189 if (off == SDHCI_CLOCK_CONTROL) {
190 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
191 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
192 MMCHS_SYSCTL_CLKD_MASK) / 2;
193 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
194 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
195 if (slot->version >= SDHCI_SPEC_300)
196 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
197 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
198 return (val32 & 0xffff);
199 }
200
201 /*
202 * Standard 32-bit handling of command and transfer mode.
203 */
204 if (off == SDHCI_TRANSFER_MODE) {
205 return (sc->cmd_and_mode >> 16);
206 } else if (off == SDHCI_COMMAND_FLAGS) {
207 return (sc->cmd_and_mode & 0x0000ffff);
208 }
209
210 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
211 }
212
213 static uint32_t
ti_sdhci_read_4(device_t dev,struct sdhci_slot * slot,bus_size_t off)214 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
215 {
216 struct ti_sdhci_softc *sc = device_get_softc(dev);
217 uint32_t val32;
218
219 val32 = RD4(sc, off);
220
221 /*
222 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip
223 * that flag from the returned capabilities.
224 */
225 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
226 val32 &= ~SDHCI_CAN_DO_HISPD;
227
228 /*
229 * Force the card-present state if necessary.
230 */
231 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
232 val32 |= SDHCI_CARD_PRESENT;
233
234 return (val32);
235 }
236
237 static void
ti_sdhci_read_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)238 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
239 uint32_t *data, bus_size_t count)
240 {
241 struct ti_sdhci_softc *sc = device_get_softc(dev);
242
243 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
244 }
245
246 static void
ti_sdhci_write_1(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint8_t val)247 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
248 uint8_t val)
249 {
250 struct ti_sdhci_softc *sc = device_get_softc(dev);
251 uint32_t val32;
252
253 #ifdef MMCCAM
254 uint32_t newval32;
255 if (off == SDHCI_HOST_CONTROL) {
256 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
257 newval32 = val32;
258 if (val & SDHCI_CTRL_8BITBUS) {
259 device_printf(dev, "Custom-enabling 8-bit bus\n");
260 newval32 |= MMCHS_CON_DW8;
261 } else {
262 device_printf(dev, "Custom-disabling 8-bit bus\n");
263 newval32 &= ~MMCHS_CON_DW8;
264 }
265 if (newval32 != val32)
266 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
267 }
268 #endif
269 val32 = RD4(sc, off & ~3);
270 val32 &= ~(0xff << (off & 3) * 8);
271 val32 |= (val << (off & 3) * 8);
272
273 WR4(sc, off & ~3, val32);
274 }
275
276 static void
ti_sdhci_write_2(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint16_t val)277 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
278 uint16_t val)
279 {
280 struct ti_sdhci_softc *sc = device_get_softc(dev);
281 uint32_t clkdiv, val32;
282
283 /*
284 * Translate between the hardware and SDHCI 2.0 or 3.0 representations
285 * of the clock divisor. See the comments in ti_sdhci_read_2() for
286 * details.
287 */
288 if (off == SDHCI_CLOCK_CONTROL) {
289 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
290 if (slot->version >= SDHCI_SPEC_300)
291 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
292 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
293 clkdiv *= 2;
294 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
295 clkdiv = MMCHS_SYSCTL_CLKD_MASK;
296 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
297 val32 &= 0xffff0000;
298 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
299 MMCHS_SYSCTL_CLKD_SHIFT);
300 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
301 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
302 return;
303 }
304
305 /*
306 * Standard 32-bit handling of command and transfer mode.
307 */
308 if (off == SDHCI_TRANSFER_MODE) {
309 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
310 ((uint32_t)val & 0x0000ffff);
311 return;
312 } else if (off == SDHCI_COMMAND_FLAGS) {
313 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
314 ((uint32_t)val << 16);
315 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
316 return;
317 }
318
319 val32 = RD4(sc, off & ~3);
320 val32 &= ~(0xffff << (off & 3) * 8);
321 val32 |= ((val & 0xffff) << (off & 3) * 8);
322 WR4(sc, off & ~3, val32);
323 }
324
325 static void
ti_sdhci_write_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t val)326 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
327 uint32_t val)
328 {
329 struct ti_sdhci_softc *sc = device_get_softc(dev);
330
331 WR4(sc, off, val);
332 }
333
334 static void
ti_sdhci_write_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)335 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
336 uint32_t *data, bus_size_t count)
337 {
338 struct ti_sdhci_softc *sc = device_get_softc(dev);
339
340 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
341 }
342
343 static void
ti_sdhci_intr(void * arg)344 ti_sdhci_intr(void *arg)
345 {
346 struct ti_sdhci_softc *sc = arg;
347
348 sdhci_generic_intr(&sc->slot);
349 }
350
351 static int
ti_sdhci_update_ios(device_t brdev,device_t reqdev)352 ti_sdhci_update_ios(device_t brdev, device_t reqdev)
353 {
354 struct ti_sdhci_softc *sc = device_get_softc(brdev);
355 struct sdhci_slot *slot;
356 struct mmc_ios *ios;
357 uint32_t val32, newval32;
358
359 slot = device_get_ivars(reqdev);
360 ios = &slot->host.ios;
361
362 /*
363 * There is an 8-bit-bus bit in the MMCHS control register which, when
364 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
365 * registers. Set that bit first according to whether an 8-bit bus is
366 * requested, then let the standard driver handle everything else.
367 */
368 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
369 newval32 = val32;
370
371 if (ios->bus_width == bus_width_8)
372 newval32 |= MMCHS_CON_DW8;
373 else
374 newval32 &= ~MMCHS_CON_DW8;
375
376 if (ios->bus_mode == opendrain)
377 newval32 |= MMCHS_CON_OD;
378 else /* if (ios->bus_mode == pushpull) */
379 newval32 &= ~MMCHS_CON_OD;
380
381 if (newval32 != val32)
382 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
383
384 return (sdhci_generic_update_ios(brdev, reqdev));
385 }
386
387 static int
ti_sdhci_get_ro(device_t brdev,device_t reqdev)388 ti_sdhci_get_ro(device_t brdev, device_t reqdev)
389 {
390 struct ti_sdhci_softc *sc = device_get_softc(brdev);
391
392 if (sc->disable_readonly)
393 return (0);
394
395 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
396 }
397
398 static bool
ti_sdhci_get_card_present(device_t dev,struct sdhci_slot * slot)399 ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
400 {
401 struct ti_sdhci_softc *sc = device_get_softc(dev);
402
403 return (sdhci_fdt_gpio_get_present(sc->gpio));
404 }
405
406 static int
ti_sdhci_detach(device_t dev)407 ti_sdhci_detach(device_t dev)
408 {
409
410 /* sdhci_fdt_gpio_teardown(sc->gpio); */
411
412 return (EBUSY);
413 }
414
415 static int
ti_sdhci_hw_init(device_t dev)416 ti_sdhci_hw_init(device_t dev)
417 {
418 struct ti_sdhci_softc *sc = device_get_softc(dev);
419 uint32_t regval;
420 unsigned long timeout;
421 clk_t mmc_clk;
422 int err;
423
424 /* Enable the controller and interface/functional clocks */
425 if (ti_sysc_clock_enable(device_get_parent(dev)) != 0) {
426 device_printf(dev, "Error: failed to enable MMC clock\n");
427 return (ENXIO);
428 }
429
430 /* FIXME: Devicetree dosent have any reference to mmc_clk */
431 err = clk_get_by_name(dev, "mmc_clk", &mmc_clk);
432 if (err) {
433 device_printf(dev, "Can not find mmc_clk\n");
434 return (ENXIO);
435 }
436 err = clk_get_freq(mmc_clk, &sc->baseclk_hz);
437 if (err) {
438 device_printf(dev, "Cant get mmc_clk frequency\n");
439 /* AM335x TRM 8.1.6.8 table 8-24 96MHz @ OPP100 */
440 sc->baseclk_hz = 96000000;
441 }
442
443 /* Issue a softreset to the controller */
444 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
445 timeout = 1000;
446 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
447 MMCHS_SYSSTATUS_RESETDONE)) {
448 if (--timeout == 0) {
449 device_printf(dev,
450 "Error: Controller reset operation timed out\n");
451 break;
452 }
453 DELAY(100);
454 }
455
456 /*
457 * Reset the command and data state machines and also other aspects of
458 * the controller such as bus clock and power.
459 *
460 * If we read the software reset register too fast after writing it we
461 * can get back a zero that means the reset hasn't started yet rather
462 * than that the reset is complete. Per TI recommendations, work around
463 * it by reading until we see the reset bit asserted, then read until
464 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
465 * so that the main sdhci driver uses this same logic in its resets.
466 */
467 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
468 timeout = 10000;
469 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
470 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
471 if (--timeout == 0) {
472 break;
473 }
474 DELAY(1);
475 }
476 timeout = 10000;
477 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
478 SDHCI_RESET_ALL)) {
479 if (--timeout == 0) {
480 device_printf(dev,
481 "Error: Software reset operation timed out\n");
482 break;
483 }
484 DELAY(100);
485 }
486
487 /*
488 * The attach() routine has examined fdt data and set flags in
489 * slot.host.caps to reflect what voltages we can handle. Set those
490 * values in the CAPA register. Empirical testing shows that the
491 * values in this register can be overwritten at any time, but the
492 * manual says that these values should only be set once, "before
493 * initialization" whatever that means, and that they survive a reset.
494 */
495 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
496 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
497 regval |= MMCHS_SD_CAPA_VS18;
498 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
499 regval |= MMCHS_SD_CAPA_VS30;
500 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
501
502 /* Set initial host configuration (1-bit, std speed, pwr off). */
503 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
504 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
505
506 /* Set the initial controller configuration. */
507 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
508
509 return (0);
510 }
511
512 static int
ti_sdhci_attach(device_t dev)513 ti_sdhci_attach(device_t dev)
514 {
515 struct ti_sdhci_softc *sc = device_get_softc(dev);
516 int rid, err;
517 pcell_t prop;
518 phandle_t node;
519
520 sc->dev = dev;
521
522 /*
523 * Get the MMCHS device id from FDT. Use rev address to identify the unit.
524 */
525 node = ofw_bus_get_node(dev);
526
527 /*
528 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
529 * device, and only 1p8v on other devices unless an external transceiver
530 * is used. The only way we could know about a transceiver is fdt data.
531 * Note that we have to do this before calling ti_sdhci_hw_init() so
532 * that it can set the right values in the CAPA register.
533 */
534 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
535
536 if (OF_hasprop(node, "ti,dual-volt")) {
537 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
538 }
539
540 /*
541 * Set the offset from the device's memory start to the MMCHS registers.
542 * Also for OMAP4 disable high speed mode due to erratum ID i626.
543 */
544 switch (ti_chip()) {
545 #ifdef SOC_OMAP4
546 case CHIP_OMAP_4:
547 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
548 sc->disable_highspeed = true;
549 break;
550 #endif
551 #ifdef SOC_TI_AM335X
552 case CHIP_AM335X:
553 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
554 break;
555 #endif
556 default:
557 panic("Unknown OMAP device\n");
558 }
559
560 /*
561 * The standard SDHCI registers are at a fixed offset (the same on all
562 * SoCs) beyond the MMCHS registers.
563 */
564 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
565
566 /* Resource setup. */
567 rid = 0;
568 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
569 RF_ACTIVE);
570 if (!sc->mem_res) {
571 device_printf(dev, "cannot allocate memory window\n");
572 err = ENXIO;
573 goto fail;
574 }
575
576 rid = 0;
577 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
578 RF_ACTIVE);
579 if (!sc->irq_res) {
580 device_printf(dev, "cannot allocate interrupt\n");
581 err = ENXIO;
582 goto fail;
583 }
584
585 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
586 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
587 device_printf(dev, "cannot setup interrupt handler\n");
588 err = ENXIO;
589 goto fail;
590 }
591
592 /*
593 * Set up handling of card-detect and write-protect gpio lines.
594 *
595 * If there is no write protect info in the fdt data, fall back to the
596 * historical practice of assuming that the card is writable. This
597 * works around bad fdt data from the upstream source. The alternative
598 * would be to trust the sdhci controller's PRESENT_STATE register WP
599 * bit, but it may say write protect is in effect when it's not if the
600 * pinmux setup doesn't route the WP signal into the sdchi block.
601 */
602 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
603
604 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable"))
605 sc->disable_readonly = true;
606
607 /* Initialise the MMCHS hardware. */
608 err = ti_sdhci_hw_init(dev);
609 if (err != 0) {
610 /* err should already contain ENXIO from ti_sdhci_hw_init() */
611 goto fail;
612 }
613
614 /*
615 * The capabilities register can only express base clock frequencies in
616 * the range of 0-63MHz for a v2.0 controller. Since our clock runs
617 * faster than that, the hardware sets the frequency to zero in the
618 * register. When the register contains zero, the sdhci driver expects
619 * slot.max_clk to already have the right value in it.
620 */
621 sc->slot.max_clk = sc->baseclk_hz;
622
623 /*
624 * The MMCHS timeout counter is based on the output sdclock. Tell the
625 * sdhci driver to recalculate the timeout clock whenever the output
626 * sdclock frequency changes.
627 */
628 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
629
630 /*
631 * The MMCHS hardware shifts the 136-bit response data (in violation of
632 * the spec), so tell the sdhci driver not to do the same in software.
633 */
634 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
635
636 /*
637 * Reset bits are broken, have to wait to see the bits asserted
638 * before waiting to see them de-asserted.
639 */
640 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
641
642 /*
643 * The controller waits for busy responses.
644 */
645 sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
646
647 /*
648 * DMA is not really broken, I just haven't implemented it yet.
649 */
650 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
651
652 /*
653 * Set up the hardware and go. Note that this sets many of the
654 * slot.host.* fields, so we have to do this before overriding any of
655 * those values based on fdt data, below.
656 */
657 sdhci_init_slot(dev, &sc->slot, 0);
658
659 /*
660 * The SDHCI controller doesn't realize it, but we can support 8-bit
661 * even though we're not a v3.0 controller. If there's an fdt bus-width
662 * property, honor it.
663 */
664 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
665 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA |
666 MMC_CAP_8_BIT_DATA);
667 switch (prop) {
668 case 8:
669 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
670 /* FALLTHROUGH */
671 case 4:
672 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
673 break;
674 case 1:
675 break;
676 default:
677 device_printf(dev, "Bad bus-width value %u\n", prop);
678 break;
679 }
680 }
681
682 /*
683 * If the slot is flagged with the non-removable property, set our flag
684 * to always force the SDHCI_CARD_PRESENT bit on.
685 */
686 node = ofw_bus_get_node(dev);
687 if (OF_hasprop(node, "non-removable"))
688 sc->force_card_present = true;
689
690 bus_generic_probe(dev);
691 bus_generic_attach(dev);
692
693 sdhci_start_slot(&sc->slot);
694 return (0);
695
696 fail:
697 if (sc->intr_cookie)
698 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
699 if (sc->irq_res)
700 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
701 if (sc->mem_res)
702 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
703
704 return (err);
705 }
706
707 static int
ti_sdhci_probe(device_t dev)708 ti_sdhci_probe(device_t dev)
709 {
710
711 if (!ofw_bus_status_okay(dev))
712 return (ENXIO);
713
714 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
715 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
716 return (BUS_PROBE_DEFAULT);
717 }
718
719 return (ENXIO);
720 }
721
722 static device_method_t ti_sdhci_methods[] = {
723 /* Device interface */
724 DEVMETHOD(device_probe, ti_sdhci_probe),
725 DEVMETHOD(device_attach, ti_sdhci_attach),
726 DEVMETHOD(device_detach, ti_sdhci_detach),
727
728 /* Bus interface */
729 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
730 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
731
732 /* MMC bridge interface */
733 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios),
734 DEVMETHOD(mmcbr_request, sdhci_generic_request),
735 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro),
736 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
737 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
738
739 /* SDHCI registers accessors */
740 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1),
741 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2),
742 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4),
743 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4),
744 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1),
745 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2),
746 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4),
747 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4),
748 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present),
749
750 DEVMETHOD_END
751 };
752
753 static driver_t ti_sdhci_driver = {
754 "sdhci_ti",
755 ti_sdhci_methods,
756 sizeof(struct ti_sdhci_softc),
757 };
758
759 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, NULL, NULL);
760 MODULE_DEPEND(sdhci_ti, ti_sysc, 1, 1, 1);
761 SDHCI_DEPEND(sdhci_ti);
762
763 #ifndef MMCCAM
764 MMC_DECLARE_BRIDGE(sdhci_ti);
765 #endif
766