1 /*-
2 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org>
3 *
4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/fbio.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/queue.h>
35 #include <sys/rman.h>
36 #include <sys/resource.h>
37 #include <machine/bus.h>
38 #include <vm/vm.h>
39 #include <vm/vm_extern.h>
40 #include <vm/vm_kern.h>
41 #include <vm/pmap.h>
42
43 #include <dev/fdt/simplebus.h>
44
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47
48 #include <dev/clk/clk.h>
49
50 #include <arm/ti/ti_sysc.h>
51 #include <arm/ti/clk/clock_common.h>
52
53 #define DEBUG_SYSC 0
54
55 #if DEBUG_SYSC
56 #define DPRINTF(dev, msg...) device_printf(dev, msg)
57 #else
58 #define DPRINTF(dev, msg...)
59 #endif
60
61 /* Documentation/devicetree/bindings/bus/ti-sysc.txt
62 *
63 * Documentation/devicetree/clock/clock-bindings.txt
64 * Defines phandle + optional pair
65 * Documentation/devicetree/clock/ti-clkctl.txt
66 */
67
68 static int ti_sysc_probe(device_t dev);
69 static int ti_sysc_attach(device_t dev);
70 static int ti_sysc_detach(device_t dev);
71
72 #define TI_SYSC_DRA7_MCAN 15
73 #define TI_SYSC_USB_HOST_FS 14
74 #define TI_SYSC_DRA7_MCASP 13
75 #define TI_SYSC_MCASP 12
76 #define TI_SYSC_OMAP_AES 11
77 #define TI_SYSC_OMAP3_SHAM 10
78 #define TI_SYSC_OMAP4_SR 9
79 #define TI_SYSC_OMAP3630_SR 8
80 #define TI_SYSC_OMAP3430_SR 7
81 #define TI_SYSC_OMAP4_TIMER 6
82 #define TI_SYSC_OMAP2_TIMER 5
83 /* Above needs special workarounds */
84 #define TI_SYSC_OMAP4_SIMPLE 4
85 #define TI_SYSC_OMAP4 3
86 #define TI_SYSC_OMAP2 2
87 #define TI_SYSC 1
88 #define TI_SYSC_END 0
89
90 static struct ofw_compat_data compat_data[] = {
91 { "ti,sysc-dra7-mcan", TI_SYSC_DRA7_MCAN },
92 { "ti,sysc-usb-host-fs", TI_SYSC_USB_HOST_FS },
93 { "ti,sysc-dra7-mcasp", TI_SYSC_DRA7_MCASP },
94 { "ti,sysc-mcasp", TI_SYSC_MCASP },
95 { "ti,sysc-omap-aes", TI_SYSC_OMAP_AES },
96 { "ti,sysc-omap3-sham", TI_SYSC_OMAP3_SHAM },
97 { "ti,sysc-omap4-sr", TI_SYSC_OMAP4_SR },
98 { "ti,sysc-omap3630-sr", TI_SYSC_OMAP3630_SR },
99 { "ti,sysc-omap3430-sr", TI_SYSC_OMAP3430_SR },
100 { "ti,sysc-omap4-timer", TI_SYSC_OMAP4_TIMER },
101 { "ti,sysc-omap2-timer", TI_SYSC_OMAP2_TIMER },
102 /* Above needs special workarounds */
103 { "ti,sysc-omap4-simple", TI_SYSC_OMAP4_SIMPLE },
104 { "ti,sysc-omap4", TI_SYSC_OMAP4 },
105 { "ti,sysc-omap2", TI_SYSC_OMAP2 },
106 { "ti,sysc", TI_SYSC },
107 { NULL, TI_SYSC_END }
108 };
109
110 /* reg-names can be "rev", "sysc" and "syss" */
111 static const char * reg_names[] = { "rev", "sysc", "syss" };
112 #define REG_REV 0
113 #define REG_SYSC 1
114 #define REG_SYSS 2
115 #define REG_MAX 3
116
117 /* master idle / slave idle mode defined in 8.1.3.2.1 / 8.1.3.2.2 */
118 #include <dt-bindings/bus/ti-sysc.h>
119 #define SYSC_IDLE_MAX 4
120
121 struct sysc_reg {
122 uint64_t address;
123 uint64_t size;
124 };
125
126 struct clk_list {
127 TAILQ_ENTRY(clk_list) next;
128 clk_t clk;
129 };
130
131 struct ti_sysc_softc {
132 struct simplebus_softc sc;
133 bool attach_done;
134
135 device_t dev;
136 int device_type;
137
138 struct sysc_reg reg[REG_MAX];
139 /* Offset from host base address */
140 uint64_t offset_reg[REG_MAX];
141
142 uint32_t ti_sysc_mask;
143 int32_t ti_sysc_midle[SYSC_IDLE_MAX];
144 int32_t ti_sysc_sidle[SYSC_IDLE_MAX];
145 uint32_t ti_sysc_delay_us;
146 uint32_t ti_syss_mask;
147
148 int num_clocks;
149 TAILQ_HEAD(, clk_list) clk_list;
150
151 /* deprecated ti_hwmods */
152 bool ti_no_reset_on_init;
153 bool ti_no_idle_on_init;
154 bool ti_no_idle;
155 };
156
157 /*
158 * All sysc seems to have a reg["rev"] register.
159 * Lets use that for identification of which module the driver are connected to.
160 */
161 uint64_t
ti_sysc_get_rev_address(device_t dev)162 ti_sysc_get_rev_address(device_t dev) {
163 struct ti_sysc_softc *sc = device_get_softc(dev);
164
165 return (sc->reg[REG_REV].address);
166 }
167
168 uint64_t
ti_sysc_get_rev_address_offset_host(device_t dev)169 ti_sysc_get_rev_address_offset_host(device_t dev) {
170 struct ti_sysc_softc *sc = device_get_softc(dev);
171
172 return (sc->offset_reg[REG_REV]);
173 }
174
175 uint64_t
ti_sysc_get_sysc_address(device_t dev)176 ti_sysc_get_sysc_address(device_t dev) {
177 struct ti_sysc_softc *sc = device_get_softc(dev);
178
179 return (sc->reg[REG_SYSC].address);
180 }
181
182 uint64_t
ti_sysc_get_sysc_address_offset_host(device_t dev)183 ti_sysc_get_sysc_address_offset_host(device_t dev) {
184 struct ti_sysc_softc *sc = device_get_softc(dev);
185
186 return (sc->offset_reg[REG_SYSC]);
187 }
188
189 uint64_t
ti_sysc_get_syss_address(device_t dev)190 ti_sysc_get_syss_address(device_t dev) {
191 struct ti_sysc_softc *sc = device_get_softc(dev);
192
193 return (sc->reg[REG_SYSS].address);
194 }
195
196 uint64_t
ti_sysc_get_syss_address_offset_host(device_t dev)197 ti_sysc_get_syss_address_offset_host(device_t dev) {
198 struct ti_sysc_softc *sc = device_get_softc(dev);
199
200 return (sc->offset_reg[REG_SYSS]);
201 }
202
203 /*
204 * Due no memory region is assigned the sysc driver the children needs to
205 * handle the practical read/writes to the registers.
206 * Check if sysc has reset bit.
207 */
208 uint32_t
ti_sysc_get_soft_reset_bit(device_t dev)209 ti_sysc_get_soft_reset_bit(device_t dev) {
210 struct ti_sysc_softc *sc = device_get_softc(dev);
211 switch (sc->device_type) {
212 case TI_SYSC_OMAP4_TIMER:
213 case TI_SYSC_OMAP4_SIMPLE:
214 case TI_SYSC_OMAP4:
215 if (sc->ti_sysc_mask & SYSC_OMAP4_SOFTRESET) {
216 return (SYSC_OMAP4_SOFTRESET);
217 }
218 break;
219
220 case TI_SYSC_OMAP2_TIMER:
221 case TI_SYSC_OMAP2:
222 case TI_SYSC:
223 if (sc->ti_sysc_mask & SYSC_OMAP2_SOFTRESET) {
224 return (SYSC_OMAP2_SOFTRESET);
225 }
226 break;
227 default:
228 break;
229 }
230
231 return (0);
232 }
233
234 int
ti_sysc_clock_enable(device_t dev)235 ti_sysc_clock_enable(device_t dev) {
236 struct clk_list *clkp, *clkp_tmp;
237 struct ti_sysc_softc *sc = device_get_softc(dev);
238 int err;
239
240 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
241 err = clk_enable(clkp->clk);
242
243 if (err) {
244 DPRINTF(sc->dev, "clk_enable %s failed %d\n",
245 clk_get_name(clkp->clk), err);
246 break;
247 }
248 }
249 return (err);
250 }
251
252 int
ti_sysc_clock_disable(device_t dev)253 ti_sysc_clock_disable(device_t dev) {
254 struct clk_list *clkp, *clkp_tmp;
255 struct ti_sysc_softc *sc = device_get_softc(dev);
256 int err = 0;
257
258 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
259 err = clk_disable(clkp->clk);
260
261 if (err) {
262 DPRINTF(sc->dev, "clk_enable %s failed %d\n",
263 clk_get_name(clkp->clk), err);
264 break;
265 }
266 }
267 return (err);
268 }
269
270 static int
parse_regfields(struct ti_sysc_softc * sc)271 parse_regfields(struct ti_sysc_softc *sc) {
272 phandle_t node;
273 uint32_t parent_address_cells;
274 uint32_t parent_size_cells;
275 cell_t *reg;
276 ssize_t nreg;
277 int err, k, reg_i, prop_idx;
278 uint32_t idx;
279
280 node = ofw_bus_get_node(sc->dev);
281
282 /* Get parents address and size properties */
283 err = OF_searchencprop(OF_parent(node), "#address-cells",
284 &parent_address_cells, sizeof(parent_address_cells));
285 if (err == -1)
286 return (ENXIO);
287 if (!(parent_address_cells == 1 || parent_address_cells == 2)) {
288 DPRINTF(sc->dev, "Expect parent #address-cells=[1||2]\n");
289 return (ENXIO);
290 }
291
292 err = OF_searchencprop(OF_parent(node), "#size-cells",
293 &parent_size_cells, sizeof(parent_size_cells));
294 if (err == -1)
295 return (ENXIO);
296
297 if (!(parent_size_cells == 1 || parent_size_cells == 2)) {
298 DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n");
299 return (ENXIO);
300 }
301
302 /* Grab the content of reg properties */
303 nreg = OF_getproplen(node, "reg");
304 if (nreg <= 0)
305 return (ENXIO);
306
307 reg = malloc(nreg, M_DEVBUF, M_WAITOK);
308 OF_getencprop(node, "reg", reg, nreg);
309
310 /* Make sure address & size are 0 */
311 for (idx = 0; idx < REG_MAX; idx++) {
312 sc->reg[idx].address = 0;
313 sc->reg[idx].size = 0;
314 }
315
316 /* Loop through reg-names and figure out which reg-name corresponds to
317 * index populate the values into the reg array.
318 */
319 for (idx = 0, reg_i = 0; idx < REG_MAX && reg_i < nreg; idx++) {
320 err = ofw_bus_find_string_index(node, "reg-names",
321 reg_names[idx], &prop_idx);
322 if (err != 0)
323 continue;
324
325 for (k = 0; k < parent_address_cells; k++) {
326 sc->reg[prop_idx].address <<= 32;
327 sc->reg[prop_idx].address |= reg[reg_i++];
328 }
329
330 for (k = 0; k < parent_size_cells; k++) {
331 sc->reg[prop_idx].size <<= 32;
332 sc->reg[prop_idx].size |= reg[reg_i++];
333 }
334
335 if (sc->sc.nranges == 0)
336 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address;
337 else
338 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address -
339 sc->sc.ranges[REG_REV].host;
340
341 DPRINTF(sc->dev, "reg[%s] address %#jx size %#jx\n",
342 reg_names[idx],
343 sc->reg[prop_idx].address,
344 sc->reg[prop_idx].size);
345 }
346 free(reg, M_DEVBUF);
347 return (0);
348 }
349
350 static void
parse_idle(struct ti_sysc_softc * sc,const char * name,uint32_t * idle)351 parse_idle(struct ti_sysc_softc *sc, const char *name, uint32_t *idle) {
352 phandle_t node;
353 cell_t value[SYSC_IDLE_MAX];
354 int len, no, i;
355
356 node = ofw_bus_get_node(sc->dev);
357
358 if (!OF_hasprop(node, name)) {
359 return;
360 }
361
362 len = OF_getproplen(node, name);
363 no = len / sizeof(cell_t);
364 if (no >= SYSC_IDLE_MAX) {
365 DPRINTF(sc->dev, "Limit %s\n", name);
366 no = SYSC_IDLE_MAX-1;
367 len = no * sizeof(cell_t);
368 }
369
370 OF_getencprop(node, name, value, len);
371 for (i = 0; i < no; i++) {
372 idle[i] = value[i];
373 #if DEBUG_SYSC
374 DPRINTF(sc->dev, "%s[%d] = %d ",
375 name, i, value[i]);
376 switch(value[i]) {
377 case SYSC_IDLE_FORCE:
378 DPRINTF(sc->dev, "SYSC_IDLE_FORCE\n");
379 break;
380 case SYSC_IDLE_NO:
381 DPRINTF(sc->dev, "SYSC_IDLE_NO\n");
382 break;
383 case SYSC_IDLE_SMART:
384 DPRINTF(sc->dev, "SYSC_IDLE_SMART\n");
385 break;
386 case SYSC_IDLE_SMART_WKUP:
387 DPRINTF(sc->dev, "SYSC_IDLE_SMART_WKUP\n");
388 break;
389 }
390 #endif
391 }
392 for ( ; i < SYSC_IDLE_MAX; i++)
393 idle[i] = -1;
394 }
395
396 static int
ti_sysc_attach_clocks(struct ti_sysc_softc * sc)397 ti_sysc_attach_clocks(struct ti_sysc_softc *sc) {
398 clk_t *clk;
399 struct clk_list *clkp;
400 int index, err;
401
402 clk = malloc(sc->num_clocks*sizeof(clk_t), M_DEVBUF, M_WAITOK | M_ZERO);
403
404 /* Check if all clocks can be found */
405 for (index = 0; index < sc->num_clocks; index++) {
406 err = clk_get_by_ofw_index(sc->dev, 0, index, &clk[index]);
407
408 if (err != 0) {
409 free(clk, M_DEVBUF);
410 return (1);
411 }
412 }
413
414 /* All clocks are found, add to list */
415 for (index = 0; index < sc->num_clocks; index++) {
416 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
417 clkp->clk = clk[index];
418 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
419 }
420
421 /* Release the clk array */
422 free(clk, M_DEVBUF);
423 return (0);
424 }
425
426 static int
ti_sysc_simplebus_attach_child(device_t dev)427 ti_sysc_simplebus_attach_child(device_t dev) {
428 device_t cdev;
429 phandle_t node, child;
430 struct ti_sysc_softc *sc = device_get_softc(dev);
431
432 node = ofw_bus_get_node(sc->dev);
433
434 for (child = OF_child(node); child > 0; child = OF_peer(child)) {
435 cdev = simplebus_add_device(sc->dev, child, 0, NULL, -1, NULL);
436 if (cdev != NULL)
437 device_probe_and_attach(cdev);
438 }
439 return (0);
440 }
441
442 /* Device interface */
443 static int
ti_sysc_probe(device_t dev)444 ti_sysc_probe(device_t dev)
445 {
446 if (!ofw_bus_status_okay(dev))
447 return (ENXIO);
448
449 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
450 return (ENXIO);
451
452 device_set_desc(dev, "TI SYSC Interconnect");
453
454 return (BUS_PROBE_DEFAULT);
455 }
456
457 static int
ti_sysc_attach(device_t dev)458 ti_sysc_attach(device_t dev)
459 {
460 struct ti_sysc_softc *sc;
461 phandle_t node;
462 int err;
463 cell_t value;
464
465 sc = device_get_softc(dev);
466 sc->dev = dev;
467 sc->device_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
468
469 node = ofw_bus_get_node(sc->dev);
470 /* ranges - use simplebus */
471 simplebus_init(sc->dev, node);
472 if (simplebus_fill_ranges(node, &sc->sc) < 0) {
473 DPRINTF(sc->dev, "could not get ranges\n");
474 return (ENXIO);
475 }
476
477 if (sc->sc.nranges == 0) {
478 DPRINTF(sc->dev, "nranges == 0\n");
479 return (ENXIO);
480 }
481
482 /* Required field reg & reg-names - assume at least "rev" exists */
483 err = parse_regfields(sc);
484 if (err) {
485 DPRINTF(sc->dev, "parse_regfields failed %d\n", err);
486 return (ENXIO);
487 }
488
489 /* Optional */
490 if (OF_hasprop(node, "ti,sysc-mask")) {
491 OF_getencprop(node, "ti,sysc-mask", &value, sizeof(cell_t));
492 sc->ti_sysc_mask = value;
493 }
494 if (OF_hasprop(node, "ti,syss-mask")) {
495 OF_getencprop(node, "ti,syss-mask", &value, sizeof(cell_t));
496 sc->ti_syss_mask = value;
497 }
498 if (OF_hasprop(node, "ti,sysc-delay-us")) {
499 OF_getencprop(node, "ti,sysc-delay-us", &value, sizeof(cell_t));
500 sc->ti_sysc_delay_us = value;
501 }
502
503 DPRINTF(sc->dev, "sysc_mask %x syss_mask %x delay_us %x\n",
504 sc->ti_sysc_mask, sc->ti_syss_mask, sc->ti_sysc_delay_us);
505
506 parse_idle(sc, "ti,sysc-midle", sc->ti_sysc_midle);
507 parse_idle(sc, "ti,sysc-sidle", sc->ti_sysc_sidle);
508
509 if (OF_hasprop(node, "ti,no-reset-on-init"))
510 sc->ti_no_reset_on_init = true;
511 else
512 sc->ti_no_reset_on_init = false;
513
514 if (OF_hasprop(node, "ti,no-idle-on-init"))
515 sc->ti_no_idle_on_init = true;
516 else
517 sc->ti_no_idle_on_init = false;
518
519 if (OF_hasprop(node, "ti,no-idle"))
520 sc->ti_no_idle = true;
521 else
522 sc->ti_no_idle = false;
523
524 DPRINTF(sc->dev,
525 "no-reset-on-init %d, no-idle-on-init %d, no-idle %d\n",
526 sc->ti_no_reset_on_init,
527 sc->ti_no_idle_on_init,
528 sc->ti_no_idle);
529
530 if (OF_hasprop(node, "clocks")) {
531 struct clock_cell_info cell_info;
532 read_clock_cells(sc->dev, &cell_info);
533 free(cell_info.clock_cells, M_DEVBUF);
534 free(cell_info.clock_cells_ncells, M_DEVBUF);
535
536 sc->num_clocks = cell_info.num_real_clocks;
537 TAILQ_INIT(&sc->clk_list);
538
539 err = ti_sysc_attach_clocks(sc);
540 if (err) {
541 DPRINTF(sc->dev, "Failed to attach clocks\n");
542 return (bus_generic_attach(sc->dev));
543 }
544 }
545
546 err = ti_sysc_simplebus_attach_child(sc->dev);
547 if (err) {
548 DPRINTF(sc->dev, "ti_sysc_simplebus_attach_child %d\n",
549 err);
550 return (err);
551 }
552
553 sc->attach_done = true;
554
555 return (bus_generic_attach(sc->dev));
556 }
557
558 static int
ti_sysc_detach(device_t dev)559 ti_sysc_detach(device_t dev)
560 {
561 return (EBUSY);
562 }
563
564 /* Bus interface */
565 static void
ti_sysc_new_pass(device_t dev)566 ti_sysc_new_pass(device_t dev)
567 {
568 struct ti_sysc_softc *sc;
569 int err;
570 phandle_t node;
571
572 sc = device_get_softc(dev);
573
574 if (sc->attach_done) {
575 bus_generic_new_pass(sc->dev);
576 return;
577 }
578
579 node = ofw_bus_get_node(sc->dev);
580 if (OF_hasprop(node, "clocks")) {
581 err = ti_sysc_attach_clocks(sc);
582 if (err) {
583 DPRINTF(sc->dev, "Failed to attach clocks\n");
584 return;
585 }
586 }
587
588 err = ti_sysc_simplebus_attach_child(sc->dev);
589 if (err) {
590 DPRINTF(sc->dev,
591 "ti_sysc_simplebus_attach_child failed %d\n", err);
592 return;
593 }
594 sc->attach_done = true;
595
596 bus_generic_attach(sc->dev);
597 }
598
599 static device_method_t ti_sysc_methods[] = {
600 /* Device interface */
601 DEVMETHOD(device_probe, ti_sysc_probe),
602 DEVMETHOD(device_attach, ti_sysc_attach),
603 DEVMETHOD(device_detach, ti_sysc_detach),
604
605 /* Bus interface */
606 DEVMETHOD(bus_new_pass, ti_sysc_new_pass),
607
608 DEVMETHOD_END
609 };
610
611 DEFINE_CLASS_1(ti_sysc, ti_sysc_driver, ti_sysc_methods,
612 sizeof(struct ti_sysc_softc), simplebus_driver);
613
614 EARLY_DRIVER_MODULE(ti_sysc, simplebus, ti_sysc_driver, 0, 0,
615 BUS_PASS_BUS + BUS_PASS_ORDER_FIRST);
616