1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /**
31 * Driver for the I2C module on the TI SoC.
32 *
33 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
34 *
35 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
36 * 32 bit data access is not allowed and can corrupt register content.
37 *
38 * This driver currently doesn't use DMA for the transfer, although I hope to
39 * incorporate that sometime in the future. The idea being that for transaction
40 * larger than a certain size the DMA engine is used, for anything less the
41 * normal interrupt/fifo driven option is used.
42 */
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/conf.h>
48 #include <sys/kernel.h>
49 #include <sys/lock.h>
50 #include <sys/mbuf.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/rman.h>
55 #include <sys/sysctl.h>
56 #include <machine/bus.h>
57
58 #include <dev/ofw/openfirm.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61
62 #include <arm/ti/ti_cpuid.h>
63 #include <arm/ti/ti_sysc.h>
64 #include <arm/ti/ti_i2c.h>
65
66 #include <dev/iicbus/iiconf.h>
67 #include <dev/iicbus/iicbus.h>
68
69 #include "iicbus_if.h"
70
71 /**
72 * I2C device driver context, a pointer to this is stored in the device
73 * driver structure.
74 */
75 struct ti_i2c_softc
76 {
77 device_t sc_dev;
78 struct resource* sc_irq_res;
79 struct resource* sc_mem_res;
80 device_t sc_iicbus;
81
82 void* sc_irq_h;
83
84 struct mtx sc_mtx;
85
86 struct iic_msg* sc_buffer;
87 int sc_bus_inuse;
88 int sc_buffer_pos;
89 int sc_error;
90 int sc_fifo_trsh;
91 int sc_timeout;
92
93 uint16_t sc_con_reg;
94 uint16_t sc_rev;
95 };
96
97 struct ti_i2c_clock_config
98 {
99 u_int frequency; /* Bus frequency in Hz */
100 uint8_t psc; /* Fast/Standard mode prescale divider */
101 uint8_t scll; /* Fast/Standard mode SCL low time */
102 uint8_t sclh; /* Fast/Standard mode SCL high time */
103 uint8_t hsscll; /* High Speed mode SCL low time */
104 uint8_t hssclh; /* High Speed mode SCL high time */
105 };
106
107 #if defined(SOC_TI_AM335X)
108 /*
109 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
110 * In all cases we prescale the clock to 24MHz as recommended in the manual.
111 */
112 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
113 { 100000, 1, 111, 117, 0, 0},
114 { 400000, 1, 23, 25, 0, 0},
115 { 1000000, 1, 5, 7, 0, 0},
116 { 0 /* Table terminator */ }
117 };
118 #endif
119
120 /**
121 * Locking macros used throughout the driver
122 */
123 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
124 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
125 #define TI_I2C_LOCK_INIT(_sc) \
126 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
127 "ti_i2c", MTX_DEF)
128 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
129 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
130 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
131
132 #ifdef DEBUG
133 #define ti_i2c_dbg(_sc, fmt, args...) \
134 device_printf((_sc)->sc_dev, fmt, ##args)
135 #else
136 #define ti_i2c_dbg(_sc, fmt, args...)
137 #endif
138
139 /**
140 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
141 * @sc: I2C device context
142 * @off: the byte offset within the register bank to read from.
143 *
144 *
145 * LOCKING:
146 * No locking required
147 *
148 * RETURNS:
149 * 16-bit value read from the register.
150 */
151 static inline uint16_t
ti_i2c_read_2(struct ti_i2c_softc * sc,bus_size_t off)152 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
153 {
154
155 return (bus_read_2(sc->sc_mem_res, off));
156 }
157
158 /**
159 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
160 * @sc: I2C device context
161 * @off: the byte offset within the register bank to read from.
162 * @val: the value to write into the register
163 *
164 * LOCKING:
165 * No locking required
166 *
167 * RETURNS:
168 * 16-bit value read from the register.
169 */
170 static inline void
ti_i2c_write_2(struct ti_i2c_softc * sc,bus_size_t off,uint16_t val)171 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
172 {
173
174 bus_write_2(sc->sc_mem_res, off, val);
175 }
176
177 static int
ti_i2c_transfer_intr(struct ti_i2c_softc * sc,uint16_t status)178 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
179 {
180 int amount, done, i;
181
182 done = 0;
183 amount = 0;
184 /* Check for the error conditions. */
185 if (status & I2C_STAT_NACK) {
186 /* No ACK from slave. */
187 ti_i2c_dbg(sc, "NACK\n");
188 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
189 sc->sc_error = ENXIO;
190 } else if (status & I2C_STAT_AL) {
191 /* Arbitration lost. */
192 ti_i2c_dbg(sc, "Arbitration lost\n");
193 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
194 sc->sc_error = ENXIO;
195 }
196
197 /* Check if we have finished. */
198 if (status & I2C_STAT_ARDY) {
199 /* Register access ready - transaction complete basically. */
200 ti_i2c_dbg(sc, "ARDY transaction complete\n");
201 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
202 ti_i2c_write_2(sc, I2C_REG_CON,
203 sc->sc_con_reg | I2C_CON_STP);
204 }
205 ti_i2c_write_2(sc, I2C_REG_STATUS,
206 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
207 I2C_STAT_XDR | I2C_STAT_XRDY);
208 return (1);
209 }
210
211 if (sc->sc_buffer->flags & IIC_M_RD) {
212 /* Read some data. */
213 if (status & I2C_STAT_RDR) {
214 /*
215 * Receive draining interrupt - last data received.
216 * The set FIFO threshold won't be reached to trigger
217 * RRDY.
218 */
219 ti_i2c_dbg(sc, "Receive draining interrupt\n");
220
221 /*
222 * Drain the FIFO. Read the pending data in the FIFO.
223 */
224 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
225 } else if (status & I2C_STAT_RRDY) {
226 /*
227 * Receive data ready interrupt - FIFO has reached the
228 * set threshold.
229 */
230 ti_i2c_dbg(sc, "Receive data ready interrupt\n");
231
232 amount = min(sc->sc_fifo_trsh,
233 sc->sc_buffer->len - sc->sc_buffer_pos);
234 }
235
236 /* Read the bytes from the fifo. */
237 for (i = 0; i < amount; i++)
238 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
239 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
240
241 if (status & I2C_STAT_RDR)
242 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
243 if (status & I2C_STAT_RRDY)
244 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
245
246 } else {
247 /* Write some data. */
248 if (status & I2C_STAT_XDR) {
249 /*
250 * Transmit draining interrupt - FIFO level is below
251 * the set threshold and the amount of data still to
252 * be transferred won't reach the set FIFO threshold.
253 */
254 ti_i2c_dbg(sc, "Transmit draining interrupt\n");
255
256 /*
257 * Drain the TX data. Write the pending data in the
258 * FIFO.
259 */
260 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
261 } else if (status & I2C_STAT_XRDY) {
262 /*
263 * Transmit data ready interrupt - the FIFO level
264 * is below the set threshold.
265 */
266 ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
267
268 amount = min(sc->sc_fifo_trsh,
269 sc->sc_buffer->len - sc->sc_buffer_pos);
270 }
271
272 /* Write the bytes from the fifo. */
273 for (i = 0; i < amount; i++)
274 ti_i2c_write_2(sc, I2C_REG_DATA,
275 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
276
277 if (status & I2C_STAT_XDR)
278 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
279 if (status & I2C_STAT_XRDY)
280 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
281 }
282
283 return (done);
284 }
285
286 /**
287 * ti_i2c_intr - interrupt handler for the I2C module
288 * @dev: i2c device handle
289 *
290 *
291 *
292 * LOCKING:
293 * Called from timer context
294 *
295 * RETURNS:
296 * EH_HANDLED or EH_NOT_HANDLED
297 */
298 static void
ti_i2c_intr(void * arg)299 ti_i2c_intr(void *arg)
300 {
301 int done;
302 struct ti_i2c_softc *sc;
303 uint16_t events, status;
304
305 sc = (struct ti_i2c_softc *)arg;
306
307 TI_I2C_LOCK(sc);
308
309 status = ti_i2c_read_2(sc, I2C_REG_STATUS);
310 if (status == 0) {
311 TI_I2C_UNLOCK(sc);
312 return;
313 }
314
315 /* Save enabled interrupts. */
316 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
317
318 /* We only care about enabled interrupts. */
319 status &= events;
320
321 done = 0;
322
323 if (sc->sc_buffer != NULL)
324 done = ti_i2c_transfer_intr(sc, status);
325 else {
326 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
327 sc->sc_error = EINVAL;
328 done = 1;
329 }
330
331 if (done)
332 /* Wakeup the process that started the transaction. */
333 wakeup(sc);
334
335 TI_I2C_UNLOCK(sc);
336 }
337
338 /**
339 * ti_i2c_transfer - called to perform the transfer
340 * @dev: i2c device handle
341 * @msgs: the messages to send/receive
342 * @nmsgs: the number of messages in the msgs array
343 *
344 *
345 * LOCKING:
346 * Internally locked
347 *
348 * RETURNS:
349 * 0 on function succeeded
350 * EINVAL if invalid message is passed as an arg
351 */
352 static int
ti_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)353 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
354 {
355 int err, i, repstart, timeout;
356 struct ti_i2c_softc *sc;
357 uint16_t reg;
358
359 sc = device_get_softc(dev);
360 TI_I2C_LOCK(sc);
361
362 /* If the controller is busy wait until it is available. */
363 while (sc->sc_bus_inuse == 1)
364 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
365
366 /* Now we have control over the I2C controller. */
367 sc->sc_bus_inuse = 1;
368
369 err = 0;
370 repstart = 0;
371 for (i = 0; i < nmsgs; i++) {
372 sc->sc_buffer = &msgs[i];
373 sc->sc_buffer_pos = 0;
374 sc->sc_error = 0;
375
376 /* Zero byte transfers aren't allowed. */
377 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
378 sc->sc_buffer->len == 0) {
379 err = EINVAL;
380 break;
381 }
382
383 /* Check if the i2c bus is free. */
384 if (repstart == 0) {
385 /*
386 * On repeated start we send the START condition while
387 * the bus _is_ busy.
388 */
389 timeout = 0;
390 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
391 if (timeout++ > 100) {
392 err = EBUSY;
393 goto out;
394 }
395 DELAY(1000);
396 }
397 timeout = 0;
398 } else
399 repstart = 0;
400
401 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
402 repstart = 1;
403
404 /* Set the slave address. */
405 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
406
407 /* Write the data length. */
408 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
409
410 /* Clear the RX and the TX FIFO. */
411 reg = ti_i2c_read_2(sc, I2C_REG_BUF);
412 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
413 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
414
415 reg = sc->sc_con_reg | I2C_CON_STT;
416 if (repstart == 0)
417 reg |= I2C_CON_STP;
418 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
419 reg |= I2C_CON_TRX;
420 ti_i2c_write_2(sc, I2C_REG_CON, reg);
421
422 /* Wait for an event. */
423 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
424 if (err == 0)
425 err = sc->sc_error;
426
427 if (err)
428 break;
429 }
430
431 out:
432 if (timeout == 0) {
433 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
434 if (timeout++ > 100)
435 break;
436 DELAY(1000);
437 }
438 }
439 /* Put the controller in master mode again. */
440 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
441 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
442
443 sc->sc_buffer = NULL;
444 sc->sc_bus_inuse = 0;
445
446 /* Wake up the processes that are waiting for the bus. */
447 wakeup(sc);
448
449 TI_I2C_UNLOCK(sc);
450
451 return (err);
452 }
453
454 static int
ti_i2c_reset(struct ti_i2c_softc * sc,u_char speed)455 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
456 {
457 int timeout;
458 struct ti_i2c_clock_config *clkcfg;
459 u_int busfreq;
460 uint16_t fifo_trsh, reg, scll, sclh;
461
462 switch (ti_chip()) {
463 #ifdef SOC_TI_AM335X
464 case CHIP_AM335X:
465 clkcfg = ti_am335x_i2c_clock_configs;
466 break;
467 #endif
468 default:
469 panic("Unknown TI SoC, unable to reset the i2c");
470 }
471
472 /*
473 * If we haven't attached the bus yet, just init at the default slow
474 * speed. This lets us get the hardware initialized enough to attach
475 * the bus which is where the real speed configuration is handled. After
476 * the bus is attached, get the configured speed from it. Search the
477 * configuration table for the best speed we can do that doesn't exceed
478 * the requested speed.
479 */
480 if (sc->sc_iicbus == NULL)
481 busfreq = 100000;
482 else
483 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
484 for (;;) {
485 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
486 break;
487 clkcfg++;
488 }
489
490 /*
491 * 23.1.4.3 - HS I2C Software Reset
492 * From OMAP4 TRM at page 4068.
493 *
494 * 1. Ensure that the module is disabled.
495 */
496 sc->sc_con_reg = 0;
497 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
498
499 /* 2. Issue a softreset to the controller. */
500 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
501
502 /*
503 * 3. Enable the module.
504 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
505 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
506 */
507 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
508
509 /* 4. Wait for the software reset to complete. */
510 timeout = 0;
511 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
512 if (timeout++ > 100)
513 return (EBUSY);
514 DELAY(100);
515 }
516
517 /*
518 * Disable the I2C controller once again, now that the reset has
519 * finished.
520 */
521 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
522
523 /*
524 * The following sequence is taken from the OMAP4 TRM at page 4077.
525 *
526 * 1. Enable the functional and interface clocks (see Section
527 * 23.1.5.1.1.1.1). Done at ti_i2c_activate().
528 *
529 * 2. Program the prescaler to obtain an approximately 12MHz internal
530 * sampling clock (I2Ci_INTERNAL_CLK) by programming the
531 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
532 * This value depends on the frequency of the functional clock
533 * (I2Ci_FCLK). Because this frequency is 96MHz, the
534 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
535 */
536 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
537
538 /*
539 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
540 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
541 * These values depend on the internal sampling clock frequency
542 * (see Table 23-8).
543 */
544 scll = clkcfg->scll & I2C_SCLL_MASK;
545 sclh = clkcfg->sclh & I2C_SCLH_MASK;
546
547 /*
548 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
549 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
550 * 400K bps or 3.4M bps (for the second phase of HS mode). These
551 * values depend on the internal sampling clock frequency (see
552 * Table 23-8).
553 *
554 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
555 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
556 * Multiplexing and Configuration).
557 */
558
559 /* Write the selected bit rate. */
560 ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
561 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
562
563 /*
564 * 6. Configure the Own Address of the I2C controller by storing it in
565 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
566 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
567 * for each I2C controller.
568 *
569 * Note: For a 10-bit address, set the corresponding expand Own Address
570 * bit in the I2Ci.I2C_CON register.
571 *
572 * Driver currently always in single master mode so ignore this step.
573 */
574
575 /*
576 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
577 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
578 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
579 * threshold - 1), where the TX and RX thresholds are greater than
580 * or equal to 1.
581 *
582 * The threshold is set to 5 for now.
583 */
584 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
585 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
586 ti_i2c_write_2(sc, I2C_REG_BUF, reg);
587
588 /*
589 * 8. Take the I2C controller out of reset by setting the
590 * I2Ci.I2C_CON[15] I2C_EN bit to 1.
591 *
592 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
593 *
594 * To initialize the I2C controller, perform the following steps:
595 *
596 * 1. Configure the I2Ci.I2C_CON register:
597 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
598 * (0: slave, 1: master).
599 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
600 * bit (0: receiver, 1: transmitter).
601 */
602
603 /* Enable the I2C controller in master mode. */
604 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
605 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
606
607 /*
608 * 2. If using an interrupt to transmit/receive data, set the
609 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
610 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
611 * bit for the receive interrupt).
612 */
613
614 /* Set the interrupts we want to be notified. */
615 reg = I2C_IE_XDR | /* Transmit draining interrupt. */
616 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
617 I2C_IE_RDR | /* Receive draining interrupt. */
618 I2C_IE_RRDY | /* Receive Data Ready interrupt. */
619 I2C_IE_ARDY | /* Register Access Ready interrupt. */
620 I2C_IE_NACK | /* No Acknowledgment interrupt. */
621 I2C_IE_AL; /* Arbitration lost interrupt. */
622
623 /* Enable the interrupts. */
624 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
625
626 /*
627 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
628 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
629 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
630 * for the transmit DMA channel).
631 *
632 * Not using DMA for now, so ignore this.
633 */
634
635 return (0);
636 }
637
638 static int
ti_i2c_iicbus_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)639 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
640 {
641 struct ti_i2c_softc *sc;
642 int err;
643
644 sc = device_get_softc(dev);
645 TI_I2C_LOCK(sc);
646 err = ti_i2c_reset(sc, speed);
647 TI_I2C_UNLOCK(sc);
648 if (err)
649 return (err);
650
651 return (IIC_ENOADDR);
652 }
653
654 static int
ti_i2c_activate(device_t dev)655 ti_i2c_activate(device_t dev)
656 {
657 int err;
658 struct ti_i2c_softc *sc;
659
660 sc = (struct ti_i2c_softc*)device_get_softc(dev);
661
662 /*
663 * 1. Enable the functional and interface clocks (see Section
664 * 23.1.5.1.1.1.1).
665 */
666 err = ti_sysc_clock_enable(device_get_parent(dev));
667 if (err)
668 return (err);
669
670 return (ti_i2c_reset(sc, IIC_UNKNOWN));
671 }
672
673 /**
674 * ti_i2c_deactivate - deactivates the controller and releases resources
675 * @dev: i2c device handle
676 *
677 *
678 *
679 * LOCKING:
680 * Assumed called in an atomic context.
681 *
682 * RETURNS:
683 * nothing
684 */
685 static void
ti_i2c_deactivate(device_t dev)686 ti_i2c_deactivate(device_t dev)
687 {
688 struct ti_i2c_softc *sc = device_get_softc(dev);
689
690 /* Disable the controller - cancel all transactions. */
691 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
692 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
693 ti_i2c_write_2(sc, I2C_REG_CON, 0);
694
695 /* Release the interrupt handler. */
696 if (sc->sc_irq_h != NULL) {
697 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
698 sc->sc_irq_h = NULL;
699 }
700
701 /* Unmap the I2C controller registers. */
702 if (sc->sc_mem_res != NULL) {
703 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
704 sc->sc_mem_res = NULL;
705 }
706
707 /* Release the IRQ resource. */
708 if (sc->sc_irq_res != NULL) {
709 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
710 sc->sc_irq_res = NULL;
711 }
712
713 /* Finally disable the functional and interface clocks. */
714 ti_sysc_clock_disable(device_get_parent(dev));
715 }
716
717 static int
ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)718 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
719 {
720 int clk, psc, sclh, scll;
721 struct ti_i2c_softc *sc;
722
723 sc = arg1;
724
725 TI_I2C_LOCK(sc);
726 /* Get the system prescaler value. */
727 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
728
729 /* Get the bitrate. */
730 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
731 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
732
733 clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
734 TI_I2C_UNLOCK(sc);
735
736 return (sysctl_handle_int(oidp, &clk, 0, req));
737 }
738
739 static int
ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)740 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)
741 {
742 struct ti_i2c_softc *sc;
743 unsigned int val;
744 int err;
745
746 sc = arg1;
747
748 /*
749 * MTX_DEF lock can't be held while doing uimove in
750 * sysctl_handle_int
751 */
752 TI_I2C_LOCK(sc);
753 val = sc->sc_timeout;
754 TI_I2C_UNLOCK(sc);
755
756 err = sysctl_handle_int(oidp, &val, 0, req);
757 /* Write request? */
758 if ((err == 0) && (req->newptr != NULL)) {
759 TI_I2C_LOCK(sc);
760 sc->sc_timeout = val;
761 TI_I2C_UNLOCK(sc);
762 }
763
764 return (err);
765 }
766
767 static int
ti_i2c_probe(device_t dev)768 ti_i2c_probe(device_t dev)
769 {
770
771 if (!ofw_bus_status_okay(dev))
772 return (ENXIO);
773 if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))
774 return (ENXIO);
775 device_set_desc(dev, "TI I2C Controller");
776
777 return (0);
778 }
779
780 static int
ti_i2c_attach(device_t dev)781 ti_i2c_attach(device_t dev)
782 {
783 int err, rid;
784 struct ti_i2c_softc *sc;
785 struct sysctl_ctx_list *ctx;
786 struct sysctl_oid_list *tree;
787 uint16_t fifosz;
788
789 sc = device_get_softc(dev);
790 sc->sc_dev = dev;
791
792 /* Get the memory resource for the register mapping. */
793 rid = 0;
794 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
795 RF_ACTIVE);
796 if (sc->sc_mem_res == NULL) {
797 device_printf(dev, "Cannot map registers.\n");
798 return (ENXIO);
799 }
800
801 /* Allocate our IRQ resource. */
802 rid = 0;
803 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
804 RF_ACTIVE | RF_SHAREABLE);
805 if (sc->sc_irq_res == NULL) {
806 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
807 device_printf(dev, "Cannot allocate interrupt.\n");
808 return (ENXIO);
809 }
810
811 TI_I2C_LOCK_INIT(sc);
812
813 /* First of all, we _must_ activate the H/W. */
814 err = ti_i2c_activate(dev);
815 if (err) {
816 device_printf(dev, "ti_i2c_activate failed\n");
817 goto out;
818 }
819
820 /* Read the version number of the I2C module */
821 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
822
823 /* Get the fifo size. */
824 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
825 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
826 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
827
828 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
829 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
830
831 /* Set the FIFO threshold to 5 for now. */
832 sc->sc_fifo_trsh = 5;
833
834 /* Set I2C bus timeout */
835 sc->sc_timeout = 5*hz;
836
837 ctx = device_get_sysctl_ctx(dev);
838 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
839 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
840 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
841 ti_i2c_sysctl_clk, "IU", "I2C bus clock");
842
843 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout",
844 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
845 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)");
846
847 /* Activate the interrupt. */
848 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
849 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
850 if (err)
851 goto out;
852
853 /* Attach the iicbus. */
854 if ((sc->sc_iicbus = device_add_child(dev, "iicbus",
855 DEVICE_UNIT_ANY)) == NULL) {
856 device_printf(dev, "could not allocate iicbus instance\n");
857 err = ENXIO;
858 goto out;
859 }
860
861 /* Probe and attach the iicbus when interrupts are available. */
862 bus_delayed_attach_children(dev);
863
864 out:
865 if (err) {
866 ti_i2c_deactivate(dev);
867 TI_I2C_LOCK_DESTROY(sc);
868 }
869
870 return (err);
871 }
872
873 static int
ti_i2c_detach(device_t dev)874 ti_i2c_detach(device_t dev)
875 {
876 struct ti_i2c_softc *sc;
877 int rv;
878
879 sc = device_get_softc(dev);
880
881 if ((rv = bus_generic_detach(dev)) != 0) {
882 device_printf(dev, "cannot detach child devices\n");
883 return (rv);
884 }
885
886 ti_i2c_deactivate(dev);
887 TI_I2C_LOCK_DESTROY(sc);
888
889 return (0);
890 }
891
892 static phandle_t
ti_i2c_get_node(device_t bus,device_t dev)893 ti_i2c_get_node(device_t bus, device_t dev)
894 {
895
896 /* Share controller node with iibus device. */
897 return (ofw_bus_get_node(bus));
898 }
899
900 static device_method_t ti_i2c_methods[] = {
901 /* Device interface */
902 DEVMETHOD(device_probe, ti_i2c_probe),
903 DEVMETHOD(device_attach, ti_i2c_attach),
904 DEVMETHOD(device_detach, ti_i2c_detach),
905
906 /* Bus interface */
907 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
908 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
909 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
910 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
911 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
912 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
913 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
914 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
915 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
916
917 /* OFW methods */
918 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
919
920 /* iicbus interface */
921 DEVMETHOD(iicbus_callback, iicbus_null_callback),
922 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
923 DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
924
925 DEVMETHOD_END
926 };
927
928 static driver_t ti_i2c_driver = {
929 "iichb",
930 ti_i2c_methods,
931 sizeof(struct ti_i2c_softc),
932 };
933
934 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, 0, 0);
935 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, 0, 0);
936
937 MODULE_DEPEND(ti_iic, ti_sysc, 1, 1, 1);
938 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);
939