1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "opt_platform.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/proc.h>
40 #include <sys/rman.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/gpio.h>
44 #include <sys/interrupt.h>
45
46 #include <machine/bus.h>
47 #include <machine/intr.h>
48 #include <machine/resource.h>
49
50 #include <arm/ti/ti_cpuid.h>
51 #include <arm/ti/ti_gpio.h>
52 #include <arm/ti/ti_scm.h>
53 #include <arm/ti/ti_sysc.h>
54
55 #include <dev/gpio/gpiobusvar.h>
56 #include <dev/ofw/openfirm.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
59
60 #include "gpio_if.h"
61 #include "ti_gpio_if.h"
62 #include "pic_if.h"
63
64 #if !defined(SOC_TI_AM335X)
65 #error "Unknown SoC"
66 #endif
67
68 /* Register definitions */
69 #define TI_GPIO_REVISION 0x0000
70 #define TI_GPIO_SYSCONFIG 0x0010
71 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
72 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
73 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */
74 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */
75 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */
76 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */
77 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */
78 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */
79 #define TI_GPIO_IRQWAKEN_0 0x0044
80 #define TI_GPIO_IRQWAKEN_1 0x0048
81 #define TI_GPIO_SYSSTATUS 0x0114
82 #define TI_GPIO_IRQSTATUS1 0x0118
83 #define TI_GPIO_IRQENABLE1 0x011C
84 #define TI_GPIO_WAKEUPENABLE 0x0120
85 #define TI_GPIO_IRQSTATUS2 0x0128
86 #define TI_GPIO_IRQENABLE2 0x012C
87 #define TI_GPIO_CTRL 0x0130
88 #define TI_GPIO_OE 0x0134
89 #define TI_GPIO_DATAIN 0x0138
90 #define TI_GPIO_DATAOUT 0x013C
91 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */
92 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */
93 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */
94 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */
95 #define TI_GPIO_DEBOUNCENABLE 0x0150
96 #define TI_GPIO_DEBOUNCINGTIME 0x0154
97 #define TI_GPIO_CLEARWKUPENA 0x0180
98 #define TI_GPIO_SETWKUENA 0x0184
99 #define TI_GPIO_CLEARDATAOUT 0x0190
100 #define TI_GPIO_SETDATAOUT 0x0194
101
102 /* Other SoC Specific definitions */
103 #define AM335X_FIRST_GPIO_BANK 0
104 #define AM335X_INTR_PER_BANK 2
105 #define AM335X_GPIO_REV 0x50600801
106 #define PINS_PER_BANK 32
107 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
108
109 #define AM335X_GPIO0_REV 0x07000
110 #define AM335X_GPIO1_REV 0x4C000
111 #define AM335X_GPIO2_REV 0xAC000
112 #define AM335X_GPIO3_REV 0xAE000
113
114 static int ti_gpio_intr(void *arg);
115 static int ti_gpio_detach(device_t);
116
117 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc);
118 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc);
119
120 static uint32_t
ti_gpio_rev(void)121 ti_gpio_rev(void)
122 {
123 switch(ti_chip()) {
124 #ifdef SOC_TI_AM335X
125 case CHIP_AM335X:
126 return (AM335X_GPIO_REV);
127 #endif
128 }
129 return (0);
130 }
131
132 /**
133 * Macros for driver mutex locking
134 */
135 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
136 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
137 #define TI_GPIO_LOCK_INIT(_sc) \
138 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
139 "ti_gpio", MTX_SPIN)
140 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
141 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
142 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
143
144 /**
145 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
146 * @sc: GPIO device context
147 * @bank: The bank to read from
148 * @off: The offset of a register from the GPIO register address range
149 *
150 *
151 * RETURNS:
152 * 32-bit value read from the register.
153 */
154 static inline uint32_t
ti_gpio_read_4(struct ti_gpio_softc * sc,bus_size_t off)155 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
156 {
157 return (bus_read_4(sc->sc_mem_res, off));
158 }
159
160 /**
161 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
162 * @sc: GPIO device context
163 * @bank: The bank to write to
164 * @off: The offset of a register from the GPIO register address range
165 * @val: The value to write into the register
166 *
167 * RETURNS:
168 * nothing
169 */
170 static inline void
ti_gpio_write_4(struct ti_gpio_softc * sc,bus_size_t off,uint32_t val)171 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
172 uint32_t val)
173 {
174 bus_write_4(sc->sc_mem_res, off, val);
175 }
176
177 static inline void
ti_gpio_intr_clr(struct ti_gpio_softc * sc,uint32_t mask)178 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
179 {
180
181 /* We clear both set of registers. */
182 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
183 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
184 }
185
186 static inline void
ti_gpio_intr_set(struct ti_gpio_softc * sc,uint32_t mask)187 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
188 {
189
190 /*
191 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
192 * also activate only the first interrupt.
193 */
194 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
195 }
196
197 static inline void
ti_gpio_intr_ack(struct ti_gpio_softc * sc,uint32_t mask)198 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
199 {
200
201 /*
202 * Acknowledge the interrupt on both registers even if we use only
203 * the first one.
204 */
205 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
206 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
207 }
208
209 static inline uint32_t
ti_gpio_intr_status(struct ti_gpio_softc * sc)210 ti_gpio_intr_status(struct ti_gpio_softc *sc)
211 {
212 uint32_t reg;
213
214 /* Get the status from both registers. */
215 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
216 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
217
218 return (reg);
219 }
220
221 static device_t
ti_gpio_get_bus(device_t dev)222 ti_gpio_get_bus(device_t dev)
223 {
224 struct ti_gpio_softc *sc;
225
226 sc = device_get_softc(dev);
227
228 return (sc->sc_busdev);
229 }
230
231 /**
232 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
233 * @dev: gpio device handle
234 * @maxpin: pointer to a value that upon return will contain the maximum number
235 * of pins in the device.
236 *
237 *
238 * LOCKING:
239 * No locking required, returns static data.
240 *
241 * RETURNS:
242 * Returns 0 on success otherwise an error code
243 */
244 static int
ti_gpio_pin_max(device_t dev,int * maxpin)245 ti_gpio_pin_max(device_t dev, int *maxpin)
246 {
247
248 *maxpin = PINS_PER_BANK - 1;
249
250 return (0);
251 }
252
253 static int
ti_gpio_valid_pin(struct ti_gpio_softc * sc,int pin)254 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
255 {
256
257 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
258 return (EINVAL);
259
260 return (0);
261 }
262
263 /**
264 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin
265 * @dev: gpio device handle
266 * @pin: the number of the pin
267 * @caps: pointer to a value that upon return will contain the capabilities
268 *
269 * Currently all pins have the same capability, notably:
270 * - GPIO_PIN_INPUT
271 * - GPIO_PIN_OUTPUT
272 * - GPIO_PIN_PULLUP
273 * - GPIO_PIN_PULLDOWN
274 * - GPIO_INTR_LEVEL_LOW
275 * - GPIO_INTR_LEVEL_HIGH
276 * - GPIO_INTR_EDGE_RISING
277 * - GPIO_INTR_EDGE_FALLING
278 * - GPIO_INTR_EDGE_BOTH
279 *
280 * LOCKING:
281 * No locking required, returns static data.
282 *
283 * RETURNS:
284 * Returns 0 on success otherwise an error code
285 */
286 static int
ti_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)287 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
288 {
289 struct ti_gpio_softc *sc;
290
291 sc = device_get_softc(dev);
292 if (ti_gpio_valid_pin(sc, pin) != 0)
293 return (EINVAL);
294
295 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
296 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
297 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
298 GPIO_INTR_EDGE_BOTH);
299
300 return (0);
301 }
302
303 /**
304 * ti_gpio_pin_getflags - Gets the current flags of a given pin
305 * @dev: gpio device handle
306 * @pin: the number of the pin
307 * @flags: upon return will contain the current flags of the pin
308 *
309 * Reads the current flags of a given pin, here we actually read the H/W
310 * registers to determine the flags, rather than storing the value in the
311 * setflags call.
312 *
313 * LOCKING:
314 * Internally locks the context
315 *
316 * RETURNS:
317 * Returns 0 on success otherwise an error code
318 */
319 static int
ti_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)320 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
321 {
322 struct ti_gpio_softc *sc;
323
324 sc = device_get_softc(dev);
325 if (ti_gpio_valid_pin(sc, pin) != 0)
326 return (EINVAL);
327
328 /* Get the current pin state */
329 TI_GPIO_LOCK(sc);
330 TI_GPIO_GET_FLAGS(dev, pin, flags);
331 TI_GPIO_UNLOCK(sc);
332
333 return (0);
334 }
335
336 /**
337 * ti_gpio_pin_getname - Gets the name of a given pin
338 * @dev: gpio device handle
339 * @pin: the number of the pin
340 * @name: buffer to put the name in
341 *
342 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
343 * of the pin.
344 *
345 * LOCKING:
346 * No locking required, returns static data.
347 *
348 * RETURNS:
349 * Returns 0 on success otherwise an error code
350 */
351 static int
ti_gpio_pin_getname(device_t dev,uint32_t pin,char * name)352 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
353 {
354 struct ti_gpio_softc *sc;
355
356 sc = device_get_softc(dev);
357 if (ti_gpio_valid_pin(sc, pin) != 0)
358 return (EINVAL);
359
360 /* Set a very simple name */
361 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
362 name[GPIOMAXNAME - 1] = '\0';
363
364 return (0);
365 }
366
367 /**
368 * ti_gpio_pin_setflags - Sets the flags for a given pin
369 * @dev: gpio device handle
370 * @pin: the number of the pin
371 * @flags: the flags to set
372 *
373 * The flags of the pin correspond to things like input/output mode, pull-ups,
374 * pull-downs, etc. This driver doesn't support all flags, only the following:
375 * - GPIO_PIN_INPUT
376 * - GPIO_PIN_OUTPUT
377 * - GPIO_PIN_PULLUP
378 * - GPIO_PIN_PULLDOWN
379 *
380 * LOCKING:
381 * Internally locks the context
382 *
383 * RETURNS:
384 * Returns 0 on success otherwise an error code
385 */
386 static int
ti_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)387 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
388 {
389 struct ti_gpio_softc *sc;
390 uint32_t oe;
391
392 sc = device_get_softc(dev);
393 if (ti_gpio_valid_pin(sc, pin) != 0)
394 return (EINVAL);
395
396 /* Set the GPIO mode and state */
397 TI_GPIO_LOCK(sc);
398 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
399 TI_GPIO_UNLOCK(sc);
400 return (EINVAL);
401 }
402
403 /* If configuring as an output set the "output enable" bit */
404 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
405 if (flags & GPIO_PIN_INPUT)
406 oe |= TI_GPIO_MASK(pin);
407 else
408 oe &= ~TI_GPIO_MASK(pin);
409 ti_gpio_write_4(sc, TI_GPIO_OE, oe);
410 TI_GPIO_UNLOCK(sc);
411
412 return (0);
413 }
414
415 /**
416 * ti_gpio_pin_set - Sets the current level on a GPIO pin
417 * @dev: gpio device handle
418 * @pin: the number of the pin
419 * @value: non-zero value will drive the pin high, otherwise the pin is
420 * driven low.
421 *
422 *
423 * LOCKING:
424 * Internally locks the context
425 *
426 * RETURNS:
427 * Returns 0 on success otherwise a error code
428 */
429 static int
ti_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)430 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
431 {
432 struct ti_gpio_softc *sc;
433 uint32_t reg;
434
435 sc = device_get_softc(dev);
436 if (ti_gpio_valid_pin(sc, pin) != 0)
437 return (EINVAL);
438
439 TI_GPIO_LOCK(sc);
440 if (value == GPIO_PIN_LOW)
441 reg = TI_GPIO_CLEARDATAOUT;
442 else
443 reg = TI_GPIO_SETDATAOUT;
444 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
445 TI_GPIO_UNLOCK(sc);
446
447 return (0);
448 }
449
450 /**
451 * ti_gpio_pin_get - Gets the current level on a GPIO pin
452 * @dev: gpio device handle
453 * @pin: the number of the pin
454 * @value: pointer to a value that upond return will contain the pin value
455 *
456 * The pin must be configured as an input pin beforehand, otherwise this
457 * function will fail.
458 *
459 * LOCKING:
460 * Internally locks the context
461 *
462 * RETURNS:
463 * Returns 0 on success otherwise a error code
464 */
465 static int
ti_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * value)466 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
467 {
468 struct ti_gpio_softc *sc;
469 uint32_t oe, reg, val;
470
471 sc = device_get_softc(dev);
472 if (ti_gpio_valid_pin(sc, pin) != 0)
473 return (EINVAL);
474
475 /*
476 * Return data from output latch when set as output and from the
477 * input register otherwise.
478 */
479 TI_GPIO_LOCK(sc);
480 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
481 if (oe & TI_GPIO_MASK(pin))
482 reg = TI_GPIO_DATAIN;
483 else
484 reg = TI_GPIO_DATAOUT;
485 val = ti_gpio_read_4(sc, reg);
486 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
487 TI_GPIO_UNLOCK(sc);
488
489 return (0);
490 }
491
492 /**
493 * ti_gpio_pin_toggle - Toggles a given GPIO pin
494 * @dev: gpio device handle
495 * @pin: the number of the pin
496 *
497 *
498 * LOCKING:
499 * Internally locks the context
500 *
501 * RETURNS:
502 * Returns 0 on success otherwise a error code
503 */
504 static int
ti_gpio_pin_toggle(device_t dev,uint32_t pin)505 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
506 {
507 struct ti_gpio_softc *sc;
508 uint32_t reg, val;
509
510 sc = device_get_softc(dev);
511 if (ti_gpio_valid_pin(sc, pin) != 0)
512 return (EINVAL);
513
514 /* Toggle the pin */
515 TI_GPIO_LOCK(sc);
516 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
517 if (val & TI_GPIO_MASK(pin))
518 reg = TI_GPIO_CLEARDATAOUT;
519 else
520 reg = TI_GPIO_SETDATAOUT;
521 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
522 TI_GPIO_UNLOCK(sc);
523
524 return (0);
525 }
526
527 static int
ti_gpio_bank_init(device_t dev)528 ti_gpio_bank_init(device_t dev)
529 {
530 int pin, err;
531 struct ti_gpio_softc *sc;
532 uint32_t flags, reg_oe, reg_set, rev;
533 uint64_t rev_address;
534
535 sc = device_get_softc(dev);
536
537 /* Enable the interface and functional clocks for the module. */
538 rev_address = ti_sysc_get_rev_address(device_get_parent(dev));
539 /* AM335x
540 * sc->sc_bank used in am335x/am335x_gpio.c and omap4/omap4_gpio.c */
541 switch(ti_chip()) {
542 #ifdef SOC_TI_AM335X
543 case CHIP_AM335X:
544 switch (rev_address) {
545 case AM335X_GPIO0_REV:
546 sc->sc_bank = 0;
547 break;
548 case AM335X_GPIO1_REV:
549 sc->sc_bank = 1;
550 break;
551 case AM335X_GPIO2_REV:
552 sc->sc_bank = 2;
553 break;
554 case AM335X_GPIO3_REV:
555 sc->sc_bank = 3;
556 break;
557 }
558 #endif
559 }
560 err = ti_sysc_clock_enable(device_get_parent(dev));
561 if (err) {
562 device_printf(dev, "Failed to enable clock\n");
563 return (EINVAL);
564 }
565
566 /*
567 * Read the revision number of the module. TI don't publish the
568 * actual revision numbers, so instead the values have been
569 * determined by experimentation.
570 */
571 rev = ti_gpio_read_4(sc,
572 ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));
573
574 /* Check the revision. */
575 if (rev != ti_gpio_rev()) {
576 device_printf(dev, "Warning: could not determine the revision "
577 "of GPIO module (revision:0x%08x)\n", rev);
578 return (EINVAL);
579 }
580
581 /* Disable interrupts for all pins. */
582 ti_gpio_intr_clr(sc, 0xffffffff);
583
584 /* Init OE register based on pads configuration. */
585 reg_oe = 0xffffffff;
586 reg_set = 0;
587 for (pin = 0; pin < PINS_PER_BANK; pin++) {
588 TI_GPIO_GET_FLAGS(dev, pin, &flags);
589 if (flags & GPIO_PIN_OUTPUT) {
590 reg_oe &= ~(1UL << pin);
591 if (flags & GPIO_PIN_PULLUP)
592 reg_set |= (1UL << pin);
593 }
594 }
595 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
596 if (reg_set)
597 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set);
598
599 return (0);
600 }
601
602 /**
603 * ti_gpio_attach - attach function for the driver
604 * @dev: gpio device handle
605 *
606 * Allocates and sets up the driver context for all GPIO banks. This function
607 * expects the memory ranges and IRQs to already be allocated to the driver.
608 *
609 * LOCKING:
610 * None
611 *
612 * RETURNS:
613 * Always returns 0
614 */
615 static int
ti_gpio_attach(device_t dev)616 ti_gpio_attach(device_t dev)
617 {
618 struct ti_gpio_softc *sc;
619 int err;
620
621 sc = device_get_softc(dev);
622 sc->sc_dev = dev;
623 TI_GPIO_LOCK_INIT(sc);
624 ti_gpio_pin_max(dev, &sc->sc_maxpin);
625 sc->sc_maxpin++;
626
627 sc->sc_mem_rid = 0;
628 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
629 &sc->sc_mem_rid, RF_ACTIVE);
630 if (!sc->sc_mem_res) {
631 device_printf(dev, "Error: could not allocate mem resources\n");
632 ti_gpio_detach(dev);
633 return (ENXIO);
634 }
635
636 sc->sc_irq_rid = 0;
637 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
638 &sc->sc_irq_rid, RF_ACTIVE);
639 if (!sc->sc_irq_res) {
640 device_printf(dev, "Error: could not allocate irq resources\n");
641 ti_gpio_detach(dev);
642 return (ENXIO);
643 }
644
645 /*
646 * Register our interrupt filter for each of the IRQ resources.
647 */
648 if (bus_setup_intr(dev, sc->sc_irq_res,
649 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
650 &sc->sc_irq_hdl) != 0) {
651 device_printf(dev,
652 "WARNING: unable to register interrupt filter\n");
653 ti_gpio_detach(dev);
654 return (ENXIO);
655 }
656
657 if (ti_gpio_pic_attach(sc) != 0) {
658 device_printf(dev, "WARNING: unable to attach PIC\n");
659 ti_gpio_detach(dev);
660 return (ENXIO);
661 }
662
663 /* We need to go through each block and ensure the clocks are running and
664 * the module is enabled. It might be better to do this only when the
665 * pins are configured which would result in less power used if the GPIO
666 * pins weren't used ...
667 */
668 if (sc->sc_mem_res != NULL) {
669 /* Initialize the GPIO module. */
670 err = ti_gpio_bank_init(dev);
671 if (err != 0) {
672 ti_gpio_detach(dev);
673 return (err);
674 }
675 }
676
677 sc->sc_busdev = gpiobus_add_bus(dev);
678 if (sc->sc_busdev == NULL) {
679 ti_gpio_detach(dev);
680 return (ENXIO);
681 }
682
683 bus_attach_children(dev);
684 return (0);
685 }
686
687 /**
688 * ti_gpio_detach - detach function for the driver
689 * @dev: scm device handle
690 *
691 * Allocates and sets up the driver context, this simply entails creating a
692 * bus mappings for the SCM register set.
693 *
694 * LOCKING:
695 * None
696 *
697 * RETURNS:
698 * Always returns 0
699 */
700 static int
ti_gpio_detach(device_t dev)701 ti_gpio_detach(device_t dev)
702 {
703 struct ti_gpio_softc *sc = device_get_softc(dev);
704
705 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
706
707 /* Disable all interrupts */
708 if (sc->sc_mem_res != NULL)
709 ti_gpio_intr_clr(sc, 0xffffffff);
710 if (sc->sc_busdev != NULL)
711 gpiobus_detach_bus(dev);
712 if (sc->sc_isrcs != NULL)
713 ti_gpio_pic_detach(sc);
714 /* Release the memory and IRQ resources. */
715 if (sc->sc_irq_hdl) {
716 bus_teardown_intr(dev, sc->sc_irq_res,
717 sc->sc_irq_hdl);
718 }
719 if (sc->sc_irq_res)
720 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
721 sc->sc_irq_res);
722 if (sc->sc_mem_res)
723 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
724 sc->sc_mem_res);
725 TI_GPIO_LOCK_DESTROY(sc);
726
727 return (0);
728 }
729
730 static inline void
ti_gpio_rwreg_modify(struct ti_gpio_softc * sc,uint32_t reg,uint32_t mask,bool set_bits)731 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask,
732 bool set_bits)
733 {
734 uint32_t value;
735
736 value = ti_gpio_read_4(sc, reg);
737 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask);
738 }
739
740 static inline void
ti_gpio_isrc_mask(struct ti_gpio_softc * sc,struct ti_gpio_irqsrc * tgi)741 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
742 {
743
744 /* Writing a 0 has no effect. */
745 ti_gpio_intr_clr(sc, tgi->tgi_mask);
746 }
747
748 static inline void
ti_gpio_isrc_unmask(struct ti_gpio_softc * sc,struct ti_gpio_irqsrc * tgi)749 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
750 {
751
752 /* Writing a 0 has no effect. */
753 ti_gpio_intr_set(sc, tgi->tgi_mask);
754 }
755
756 static inline void
ti_gpio_isrc_eoi(struct ti_gpio_softc * sc,struct ti_gpio_irqsrc * tgi)757 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
758 {
759
760 /* Writing a 0 has no effect. */
761 ti_gpio_intr_ack(sc, tgi->tgi_mask);
762 }
763
764 static inline bool
ti_gpio_isrc_is_level(struct ti_gpio_irqsrc * tgi)765 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi)
766 {
767
768 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW ||
769 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH);
770 }
771
772 static int
ti_gpio_intr(void * arg)773 ti_gpio_intr(void *arg)
774 {
775 u_int irq;
776 uint32_t reg;
777 struct ti_gpio_softc *sc;
778 struct trapframe *tf;
779 struct ti_gpio_irqsrc *tgi;
780
781 sc = (struct ti_gpio_softc *)arg;
782 tf = curthread->td_intr_frame;
783
784 reg = ti_gpio_intr_status(sc);
785 for (irq = 0; irq < sc->sc_maxpin; irq++) {
786 tgi = &sc->sc_isrcs[irq];
787 if ((reg & tgi->tgi_mask) == 0)
788 continue;
789 if (!ti_gpio_isrc_is_level(tgi))
790 ti_gpio_isrc_eoi(sc, tgi);
791 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {
792 ti_gpio_isrc_mask(sc, tgi);
793 if (ti_gpio_isrc_is_level(tgi))
794 ti_gpio_isrc_eoi(sc, tgi);
795 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
796 irq);
797 }
798 }
799 return (FILTER_HANDLED);
800 }
801
802 static int
ti_gpio_pic_attach(struct ti_gpio_softc * sc)803 ti_gpio_pic_attach(struct ti_gpio_softc *sc)
804 {
805 int error;
806 uint32_t irq;
807 const char *name;
808
809 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF,
810 M_WAITOK | M_ZERO);
811
812 name = device_get_nameunit(sc->sc_dev);
813 for (irq = 0; irq < sc->sc_maxpin; irq++) {
814 sc->sc_isrcs[irq].tgi_irq = irq;
815 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq);
816 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM;
817
818 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc,
819 sc->sc_dev, 0, "%s,%u", name, irq);
820 if (error != 0)
821 return (error); /* XXX deregister ISRCs */
822 }
823 if (intr_pic_register(sc->sc_dev,
824 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL)
825 return (ENXIO);
826
827 return (0);
828 }
829
830 static int
ti_gpio_pic_detach(struct ti_gpio_softc * sc)831 ti_gpio_pic_detach(struct ti_gpio_softc *sc)
832 {
833
834 /*
835 * There has not been established any procedure yet
836 * how to detach PIC from living system correctly.
837 */
838 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
839 return (EBUSY);
840 }
841
842 static void
ti_gpio_pic_config_intr(struct ti_gpio_softc * sc,struct ti_gpio_irqsrc * tgi,uint32_t mode)843 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi,
844 uint32_t mode)
845 {
846
847 TI_GPIO_LOCK(sc);
848 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask,
849 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH);
850 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask,
851 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH);
852 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask,
853 mode == GPIO_INTR_LEVEL_HIGH);
854 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask,
855 mode == GPIO_INTR_LEVEL_LOW);
856 tgi->tgi_mode = mode;
857 TI_GPIO_UNLOCK(sc);
858 }
859
860 static void
ti_gpio_pic_disable_intr(device_t dev,struct intr_irqsrc * isrc)861 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
862 {
863 struct ti_gpio_softc *sc = device_get_softc(dev);
864 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
865
866 ti_gpio_isrc_mask(sc, tgi);
867 }
868
869 static void
ti_gpio_pic_enable_intr(device_t dev,struct intr_irqsrc * isrc)870 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
871 {
872 struct ti_gpio_softc *sc = device_get_softc(dev);
873 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
874
875 arm_irq_memory_barrier(tgi->tgi_irq);
876 ti_gpio_isrc_unmask(sc, tgi);
877 }
878
879 static int
ti_gpio_pic_map_fdt(struct ti_gpio_softc * sc,struct intr_map_data_fdt * daf,u_int * irqp,uint32_t * modep)880 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf,
881 u_int *irqp, uint32_t *modep)
882 {
883 uint32_t mode;
884
885 /*
886 * The first cell is the interrupt number.
887 * The second cell is used to specify flags:
888 * bits[3:0] trigger type and level flags:
889 * 1 = low-to-high edge triggered.
890 * 2 = high-to-low edge triggered.
891 * 4 = active high level-sensitive.
892 * 8 = active low level-sensitive.
893 */
894 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin)
895 return (EINVAL);
896
897 /* Only reasonable modes are supported. */
898 if (daf->cells[1] == 1)
899 mode = GPIO_INTR_EDGE_RISING;
900 else if (daf->cells[1] == 2)
901 mode = GPIO_INTR_EDGE_FALLING;
902 else if (daf->cells[1] == 3)
903 mode = GPIO_INTR_EDGE_BOTH;
904 else if (daf->cells[1] == 4)
905 mode = GPIO_INTR_LEVEL_HIGH;
906 else if (daf->cells[1] == 8)
907 mode = GPIO_INTR_LEVEL_LOW;
908 else
909 return (EINVAL);
910
911 *irqp = daf->cells[0];
912 if (modep != NULL)
913 *modep = mode;
914 return (0);
915 }
916
917 static int
ti_gpio_pic_map_gpio(struct ti_gpio_softc * sc,struct intr_map_data_gpio * dag,u_int * irqp,uint32_t * modep)918 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag,
919 u_int *irqp, uint32_t *modep)
920 {
921 uint32_t mode;
922
923 if (dag->gpio_pin_num >= sc->sc_maxpin)
924 return (EINVAL);
925
926 mode = dag->gpio_intr_mode;
927 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH &&
928 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING &&
929 mode != GPIO_INTR_EDGE_BOTH)
930 return (EINVAL);
931
932 *irqp = dag->gpio_pin_num;
933 if (modep != NULL)
934 *modep = mode;
935 return (0);
936 }
937
938 static int
ti_gpio_pic_map(struct ti_gpio_softc * sc,struct intr_map_data * data,u_int * irqp,uint32_t * modep)939 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data,
940 u_int *irqp, uint32_t *modep)
941 {
942
943 switch (data->type) {
944 case INTR_MAP_DATA_FDT:
945 return (ti_gpio_pic_map_fdt(sc,
946 (struct intr_map_data_fdt *)data, irqp, modep));
947 case INTR_MAP_DATA_GPIO:
948 return (ti_gpio_pic_map_gpio(sc,
949 (struct intr_map_data_gpio *)data, irqp, modep));
950 default:
951 return (ENOTSUP);
952 }
953 }
954
955 static int
ti_gpio_pic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)956 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
957 struct intr_irqsrc **isrcp)
958 {
959 int error;
960 u_int irq;
961 struct ti_gpio_softc *sc = device_get_softc(dev);
962
963 error = ti_gpio_pic_map(sc, data, &irq, NULL);
964 if (error == 0)
965 *isrcp = &sc->sc_isrcs[irq].tgi_isrc;
966 return (error);
967 }
968
969 static void
ti_gpio_pic_post_filter(device_t dev,struct intr_irqsrc * isrc)970 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
971 {
972 struct ti_gpio_softc *sc = device_get_softc(dev);
973 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
974
975 if (ti_gpio_isrc_is_level(tgi))
976 ti_gpio_isrc_eoi(sc, tgi);
977 }
978
979 static void
ti_gpio_pic_post_ithread(device_t dev,struct intr_irqsrc * isrc)980 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
981 {
982
983 ti_gpio_pic_enable_intr(dev, isrc);
984 }
985
986 static void
ti_gpio_pic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)987 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
988 {
989 struct ti_gpio_softc *sc = device_get_softc(dev);
990 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
991
992 ti_gpio_isrc_mask(sc, tgi);
993 if (ti_gpio_isrc_is_level(tgi))
994 ti_gpio_isrc_eoi(sc, tgi);
995 }
996
997 static int
ti_gpio_pic_setup_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)998 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
999 struct resource *res, struct intr_map_data *data)
1000 {
1001 u_int irq;
1002 uint32_t mode;
1003 struct ti_gpio_softc *sc;
1004 struct ti_gpio_irqsrc *tgi;
1005
1006 if (data == NULL)
1007 return (ENOTSUP);
1008
1009 sc = device_get_softc(dev);
1010 tgi = (struct ti_gpio_irqsrc *)isrc;
1011
1012 /* Get and check config for an interrupt. */
1013 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq)
1014 return (EINVAL);
1015
1016 /*
1017 * If this is a setup for another handler,
1018 * only check that its configuration match.
1019 */
1020 if (isrc->isrc_handlers != 0)
1021 return (tgi->tgi_mode == mode ? 0 : EINVAL);
1022
1023 ti_gpio_pic_config_intr(sc, tgi, mode);
1024 return (0);
1025 }
1026
1027 static int
ti_gpio_pic_teardown_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1028 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1029 struct resource *res, struct intr_map_data *data)
1030 {
1031 struct ti_gpio_softc *sc = device_get_softc(dev);
1032 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
1033
1034 if (isrc->isrc_handlers == 0)
1035 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM);
1036 return (0);
1037 }
1038
1039 static phandle_t
ti_gpio_get_node(device_t bus,device_t dev)1040 ti_gpio_get_node(device_t bus, device_t dev)
1041 {
1042
1043 /* We only have one child, the GPIO bus, which needs our own node. */
1044 return (ofw_bus_get_node(bus));
1045 }
1046
1047 static device_method_t ti_gpio_methods[] = {
1048 DEVMETHOD(device_attach, ti_gpio_attach),
1049 DEVMETHOD(device_detach, ti_gpio_detach),
1050
1051 /* GPIO protocol */
1052 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
1053 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
1054 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
1055 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
1056 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
1057 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
1058 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
1059 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
1060 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
1061
1062 /* Interrupt controller interface */
1063 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr),
1064 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr),
1065 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr),
1066 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr),
1067 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr),
1068 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter),
1069 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread),
1070 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread),
1071
1072 /* ofw_bus interface */
1073 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
1074
1075 {0, 0},
1076 };
1077
1078 driver_t ti_gpio_driver = {
1079 "gpio",
1080 ti_gpio_methods,
1081 sizeof(struct ti_gpio_softc),
1082 };
1083