1 /*
2 * Copyright (C) 2016 Cavium Inc.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28 #include "opt_platform.h"
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 #include <sys/types.h>
34 #include <sys/sysctl.h>
35 #include <sys/kernel.h>
36 #include <sys/rman.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/endian.h>
40 #include <sys/cpuset.h>
41
42 #include <dev/ofw/openfirm.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pci_host_generic.h>
49 #include <dev/pci/pci_host_generic_fdt.h>
50 #include <dev/pci/pcib_private.h>
51
52 #include "thunder_pcie_common.h"
53
54 #include "pcib_if.h"
55
56 #ifdef THUNDERX_PASS_1_1_ERRATA
57 static struct resource * thunder_pcie_fdt_alloc_resource(device_t, device_t,
58 int, int *, rman_res_t, rman_res_t, rman_res_t, u_int);
59 static int thunder_pcie_fdt_release_resource(device_t, device_t,
60 struct resource*);
61 #endif
62 static int thunder_pcie_fdt_attach(device_t);
63 static int thunder_pcie_fdt_probe(device_t);
64 static int thunder_pcie_fdt_get_id(device_t, device_t, enum pci_id_type,
65 uintptr_t *);
66
67 static const struct ofw_bus_devinfo *thunder_pcie_ofw_get_devinfo(device_t,
68 device_t);
69
70 /* OFW bus interface */
71 struct thunder_pcie_ofw_devinfo {
72 struct ofw_bus_devinfo di_dinfo;
73 struct resource_list di_rl;
74 };
75
76 static device_method_t thunder_pcie_fdt_methods[] = {
77 /* Device interface */
78 DEVMETHOD(device_probe, thunder_pcie_fdt_probe),
79 DEVMETHOD(device_attach, thunder_pcie_fdt_attach),
80 #ifdef THUNDERX_PASS_1_1_ERRATA
81 DEVMETHOD(bus_alloc_resource, thunder_pcie_fdt_alloc_resource),
82 DEVMETHOD(bus_release_resource, thunder_pcie_fdt_release_resource),
83 #endif
84
85 /* pcib interface */
86 DEVMETHOD(pcib_get_id, thunder_pcie_fdt_get_id),
87
88 /* ofw interface */
89 DEVMETHOD(ofw_bus_get_devinfo, thunder_pcie_ofw_get_devinfo),
90 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
91 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
92 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
93 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
94 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
95
96 /* End */
97 DEVMETHOD_END
98 };
99
100 DEFINE_CLASS_1(pcib, thunder_pcie_fdt_driver, thunder_pcie_fdt_methods,
101 sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver);
102
103 DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_fdt_driver, 0, 0);
104 DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_fdt_driver, 0, 0);
105
106 static const struct ofw_bus_devinfo *
thunder_pcie_ofw_get_devinfo(device_t bus __unused,device_t child)107 thunder_pcie_ofw_get_devinfo(device_t bus __unused, device_t child)
108 {
109 struct thunder_pcie_ofw_devinfo *di;
110
111 di = device_get_ivars(child);
112 return (&di->di_dinfo);
113 }
114
115 static void
get_addr_size_cells(phandle_t node,pcell_t * addr_cells,pcell_t * size_cells)116 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells)
117 {
118
119 *addr_cells = 2;
120 /* Find address cells if present */
121 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells));
122
123 *size_cells = 2;
124 /* Find size cells if present */
125 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells));
126 }
127
128 static int
thunder_pcie_ofw_bus_attach(device_t dev)129 thunder_pcie_ofw_bus_attach(device_t dev)
130 {
131 struct thunder_pcie_ofw_devinfo *di;
132 device_t child;
133 phandle_t parent, node;
134 pcell_t addr_cells, size_cells;
135
136 parent = ofw_bus_get_node(dev);
137 if (parent > 0) {
138 get_addr_size_cells(parent, &addr_cells, &size_cells);
139 /* Iterate through all bus subordinates */
140 for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
141 /* Allocate and populate devinfo. */
142 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
143 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {
144 free(di, M_DEVBUF);
145 continue;
146 }
147
148 /* Initialize and populate resource list. */
149 resource_list_init(&di->di_rl);
150 ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells,
151 &di->di_rl);
152 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL);
153
154 /* Add newbus device for this FDT node */
155 child = device_add_child(dev, NULL, -1);
156 if (child == NULL) {
157 resource_list_free(&di->di_rl);
158 ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
159 free(di, M_DEVBUF);
160 continue;
161 }
162
163 device_set_ivars(child, di);
164 }
165 }
166
167 return (0);
168 }
169
170 static int
thunder_pcie_fdt_probe(device_t dev)171 thunder_pcie_fdt_probe(device_t dev)
172 {
173
174 /* Check if we're running on Cavium ThunderX */
175 if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
176 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0))
177 return (ENXIO);
178
179 if (!ofw_bus_status_okay(dev))
180 return (ENXIO);
181
182 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic") ||
183 ofw_bus_is_compatible(dev, "cavium,thunder-pcie") ||
184 ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) {
185 device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller");
186 return (BUS_PROBE_DEFAULT);
187 }
188
189 return (ENXIO);
190 }
191
192 static int
thunder_pcie_fdt_attach(device_t dev)193 thunder_pcie_fdt_attach(device_t dev)
194 {
195 struct generic_pcie_fdt_softc *sc;
196
197 sc = device_get_softc(dev);
198 thunder_pcie_identify_ecam(dev, &sc->base.ecam);
199 sc->base.coherent = 1;
200
201 /* Attach OFW bus */
202 if (thunder_pcie_ofw_bus_attach(dev) != 0)
203 return (ENXIO);
204
205 return (pci_host_generic_fdt_attach(dev));
206 }
207
208 static int
thunder_pcie_fdt_get_id(device_t pci,device_t child,enum pci_id_type type,uintptr_t * id)209 thunder_pcie_fdt_get_id(device_t pci, device_t child, enum pci_id_type type,
210 uintptr_t *id)
211 {
212 phandle_t node;
213 int bsf;
214
215 if (type != PCI_ID_MSI)
216 return (pcib_get_id(pci, child, type, id));
217
218 node = ofw_bus_get_node(pci);
219 if (OF_hasprop(node, "msi-map"))
220 return (generic_pcie_get_id(pci, child, type, id));
221
222 bsf = pci_get_rid(child);
223 *id = (pci_get_domain(child) << PCI_RID_DOMAIN_SHIFT) | bsf;
224
225 return (0);
226 }
227
228 #ifdef THUNDERX_PASS_1_1_ERRATA
229 struct resource *
thunder_pcie_fdt_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)230 thunder_pcie_fdt_alloc_resource(device_t dev, device_t child, int type,
231 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
232 {
233 struct generic_pcie_fdt_softc *sc;
234 struct thunder_pcie_ofw_devinfo *di;
235 struct resource_list_entry *rle;
236 int i;
237
238 /*
239 * For PCIe devices that do not have FDT nodes pass
240 * the request to the core driver.
241 */
242 if ((int)ofw_bus_get_node(child) <= 0)
243 return (thunder_pcie_alloc_resource(dev, child, type,
244 rid, start, end, count, flags));
245
246 /* For other devices use OFW method */
247 sc = device_get_softc(dev);
248
249 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
250 if ((di = device_get_ivars(child)) == NULL)
251 return (NULL);
252 if (type == SYS_RES_IOPORT)
253 type = SYS_RES_MEMORY;
254
255 /* Find defaults for this rid */
256 rle = resource_list_find(&di->di_rl, type, *rid);
257 if (rle == NULL)
258 return (NULL);
259
260 start = rle->start;
261 end = rle->end;
262 count = rle->count;
263 }
264
265 if (type == SYS_RES_MEMORY) {
266 /* Remap through ranges property */
267 for (i = 0; i < MAX_RANGES_TUPLES; i++) {
268 if (start >= sc->base.ranges[i].phys_base &&
269 end < (sc->base.ranges[i].pci_base +
270 sc->base.ranges[i].size)) {
271 start -= sc->base.ranges[i].phys_base;
272 start += sc->base.ranges[i].pci_base;
273 end -= sc->base.ranges[i].phys_base;
274 end += sc->base.ranges[i].pci_base;
275 break;
276 }
277 }
278
279 if (i == MAX_RANGES_TUPLES) {
280 device_printf(dev, "Could not map resource "
281 "%#jx-%#jx\n", start, end);
282 return (NULL);
283 }
284 }
285
286 return (bus_generic_alloc_resource(dev, child, type, rid, start,
287 end, count, flags));
288 }
289
290 static int
thunder_pcie_fdt_release_resource(device_t dev,device_t child,struct resource * res)291 thunder_pcie_fdt_release_resource(device_t dev, device_t child,
292 struct resource *res)
293 {
294
295 if ((int)ofw_bus_get_node(child) <= 0)
296 return (pci_host_generic_core_release_resource(dev, child,
297 res));
298
299 return (bus_generic_release_resource(dev, child, res));
300 }
301 #endif
302