1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14
15 #include <linux/bits.h>
16
17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
18 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */
19 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */
20 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
21
22 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
23 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
24 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
25 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
26
27 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
28
29 #ifndef __ASSEMBLER__
30
31 #include <linux/cpumask.h>
32 #include <linux/linkage.h>
33 #include <linux/irqflags.h>
34 #include <linux/instruction_pointer.h>
35 #include <linux/bitops.h>
36 #include <asm/fpu-types.h>
37 #include <asm/cpu.h>
38 #include <asm/page.h>
39 #include <asm/ptrace.h>
40 #include <asm/setup.h>
41 #include <asm/runtime_instr.h>
42 #include <asm/irqflags.h>
43 #include <asm/alternative.h>
44 #include <asm/fault.h>
45
46 struct pcpu {
47 unsigned long ec_mask; /* bit mask for ec_xxx functions */
48 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
49 unsigned long flags; /* per CPU flags */
50 unsigned long capacity; /* cpu capacity for scheduler */
51 signed char state; /* physical cpu state */
52 signed char polarization; /* physical polarization */
53 u16 address; /* physical cpu address */
54 };
55
56 DECLARE_PER_CPU(struct pcpu, pcpu_devices);
57
58 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
59
this_pcpu(void)60 static __always_inline struct pcpu *this_pcpu(void)
61 {
62 return (struct pcpu *)(get_lowcore()->pcpu);
63 }
64
set_cpu_flag(int flag)65 static __always_inline void set_cpu_flag(int flag)
66 {
67 set_bit(flag, &this_pcpu()->flags);
68 }
69
clear_cpu_flag(int flag)70 static __always_inline void clear_cpu_flag(int flag)
71 {
72 clear_bit(flag, &this_pcpu()->flags);
73 }
74
test_cpu_flag(int flag)75 static __always_inline bool test_cpu_flag(int flag)
76 {
77 return test_bit(flag, &this_pcpu()->flags);
78 }
79
test_and_set_cpu_flag(int flag)80 static __always_inline bool test_and_set_cpu_flag(int flag)
81 {
82 return test_and_set_bit(flag, &this_pcpu()->flags);
83 }
84
test_and_clear_cpu_flag(int flag)85 static __always_inline bool test_and_clear_cpu_flag(int flag)
86 {
87 return test_and_clear_bit(flag, &this_pcpu()->flags);
88 }
89
90 /*
91 * Test CIF flag of another CPU. The caller needs to ensure that
92 * CPU hotplug can not happen, e.g. by disabling preemption.
93 */
test_cpu_flag_of(int flag,int cpu)94 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
95 {
96 return test_bit(flag, &per_cpu(pcpu_devices, cpu).flags);
97 }
98
99 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
100
get_cpu_id(struct cpuid * ptr)101 static inline void get_cpu_id(struct cpuid *ptr)
102 {
103 asm volatile("stidp %0" : "=Q" (*ptr));
104 }
105
get_cpu_timer(void)106 static __always_inline unsigned long get_cpu_timer(void)
107 {
108 unsigned long timer;
109
110 asm volatile("stpt %[timer]" : [timer] "=Q" (timer));
111 return timer;
112 }
113
114 void s390_adjust_jiffies(void);
115 void s390_update_cpu_mhz(void);
116 void cpu_detect_mhz_feature(void);
117
118 extern const struct seq_operations cpuinfo_op;
119 extern void execve_tail(void);
120 unsigned long vdso_text_size(void);
121 unsigned long vdso_size(void);
122
123 #define TASK_SIZE (TASK_SIZE_MAX)
124 #define TASK_UNMAPPED_BASE (_REGION2_SIZE >> 1)
125 #define TASK_SIZE_MAX (-PAGE_SIZE)
126
127 #define VDSO_BASE (STACK_TOP + PAGE_SIZE)
128 #define VDSO_LIMIT (_REGION2_SIZE)
129 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
130 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
131
132 #define HAVE_ARCH_PICK_MMAP_LAYOUT
133
134 #define __stackleak_poison __stackleak_poison
__stackleak_poison(unsigned long erase_low,unsigned long erase_high,unsigned long poison)135 static __always_inline void __stackleak_poison(unsigned long erase_low,
136 unsigned long erase_high,
137 unsigned long poison)
138 {
139 unsigned long tmp, count;
140
141 count = erase_high - erase_low;
142 if (!count)
143 return;
144 asm volatile(
145 " cghi %[count],8\n"
146 " je 2f\n"
147 " aghi %[count],-(8+1)\n"
148 " srlg %[tmp],%[count],8\n"
149 " ltgr %[tmp],%[tmp]\n"
150 " jz 1f\n"
151 "0: stg %[poison],0(%[addr])\n"
152 " mvc 8(256-8,%[addr]),0(%[addr])\n"
153 " la %[addr],256(%[addr])\n"
154 " brctg %[tmp],0b\n"
155 "1: stg %[poison],0(%[addr])\n"
156 " exrl %[count],3f\n"
157 " j 4f\n"
158 "2: stg %[poison],0(%[addr])\n"
159 " j 4f\n"
160 "3: mvc 8(1,%[addr]),0(%[addr])\n"
161 "4:"
162 : [addr] "+&a" (erase_low), [count] "+&a" (count), [tmp] "=&a" (tmp)
163 : [poison] "d" (poison)
164 : "memory", "cc"
165 );
166 }
167
168 /*
169 * Thread structure
170 */
171 struct thread_struct {
172 unsigned int acrs[NUM_ACRS];
173 unsigned long ksp; /* kernel stack pointer */
174 unsigned long user_timer; /* task cputime in user space */
175 unsigned long guest_timer; /* task cputime in kvm guest */
176 unsigned long system_timer; /* task cputime in kernel space */
177 unsigned long hardirq_timer; /* task cputime in hardirq context */
178 unsigned long softirq_timer; /* task cputime in softirq context */
179 union teid gmap_teid; /* address and flags of last gmap fault */
180 unsigned int gmap_int_code; /* int code of last gmap fault */
181 int ufpu_flags; /* user fpu flags */
182 int kfpu_flags; /* kernel fpu flags */
183
184 /* Per-thread information related to debugging */
185 struct per_regs per_user; /* User specified PER registers */
186 struct per_event per_event; /* Cause of the last PER trap */
187 unsigned long per_flags; /* Flags to control debug behavior */
188 unsigned int system_call; /* system call number in signal */
189 unsigned long last_break; /* last breaking-event-address. */
190 /* pfault_wait is used to block the process on a pfault event */
191 unsigned long pfault_wait;
192 struct list_head list;
193 /* cpu runtime instrumentation */
194 struct runtime_instr_cb *ri_cb;
195 struct gs_cb *gs_cb; /* Current guarded storage cb */
196 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
197 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
198 struct fpu ufpu; /* User FP and VX register save area */
199 struct fpu kfpu; /* Kernel FP and VX register save area */
200 };
201
202 /* Flag to disable transactions. */
203 #define PER_FLAG_NO_TE 1UL
204 /* Flag to enable random transaction aborts. */
205 #define PER_FLAG_TE_ABORT_RAND 2UL
206 /* Flag to specify random transaction abort mode:
207 * - abort each transaction at a random instruction before TEND if set.
208 * - abort random transactions at a random instruction if cleared.
209 */
210 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
211
212 typedef struct thread_struct thread_struct;
213
214 #define ARCH_MIN_TASKALIGN 8
215
216 #define INIT_THREAD { \
217 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
218 .last_break = 1, \
219 }
220
221 /*
222 * Do necessary setup to start up a new thread.
223 */
224 #define start_thread(regs, new_psw, new_stackp) do { \
225 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
226 regs->psw.addr = new_psw; \
227 regs->gprs[15] = new_stackp; \
228 execve_tail(); \
229 } while (0)
230
231 #define start_thread31(regs, new_psw, new_stackp) do { \
232 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
233 regs->psw.addr = new_psw; \
234 regs->gprs[15] = new_stackp; \
235 execve_tail(); \
236 } while (0)
237
238 struct task_struct;
239 struct mm_struct;
240 struct seq_file;
241 struct pt_regs;
242
243 void show_registers(struct pt_regs *regs);
244 void show_cacheinfo(struct seq_file *m);
245
246 /* Free guarded storage control block */
247 void guarded_storage_release(struct task_struct *tsk);
248 void gs_load_bc_cb(struct pt_regs *regs);
249
250 unsigned long __get_wchan(struct task_struct *p);
251 #define task_pt_regs(tsk) ((struct pt_regs *) \
252 (task_stack_page(tsk) + THREAD_SIZE) - 1)
253 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
254 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
255
256 /* Has task runtime instrumentation enabled ? */
257 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
258
259 /* avoid using global register due to gcc bug in versions < 8.4 */
260 #define current_stack_pointer (__current_stack_pointer())
261
__current_stack_pointer(void)262 static __always_inline unsigned long __current_stack_pointer(void)
263 {
264 unsigned long sp;
265
266 asm volatile("lgr %0,15" : "=d" (sp));
267 return sp;
268 }
269
on_thread_stack(void)270 static __always_inline bool on_thread_stack(void)
271 {
272 unsigned long ksp = get_lowcore()->kernel_stack;
273
274 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
275 }
276
stap(void)277 static __always_inline unsigned short stap(void)
278 {
279 unsigned short cpu_address;
280
281 asm volatile("stap %0" : "=Q" (cpu_address));
282 return cpu_address;
283 }
284
285 #define cpu_relax() barrier()
286
287 #define ECAG_CACHE_ATTRIBUTE 0
288 #define ECAG_CPU_ATTRIBUTE 1
289
__ecag(unsigned int asi,unsigned char parm)290 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
291 {
292 unsigned long val;
293
294 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
295 return val;
296 }
297
psw_set_key(unsigned int key)298 static inline void psw_set_key(unsigned int key)
299 {
300 asm volatile("spka 0(%0)" : : "d" (key));
301 }
302
303 /*
304 * Set PSW to specified value.
305 */
__load_psw(psw_t psw)306 static inline void __load_psw(psw_t psw)
307 {
308 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
309 }
310
311 /*
312 * Set PSW mask to specified value, while leaving the
313 * PSW addr pointing to the next instruction.
314 */
__load_psw_mask(unsigned long mask)315 static __always_inline void __load_psw_mask(unsigned long mask)
316 {
317 psw_t psw __uninitialized;
318 unsigned long addr;
319
320 psw.mask = mask;
321
322 asm volatile(
323 " larl %0,1f\n"
324 " stg %0,%1\n"
325 " lpswe %2\n"
326 "1:"
327 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
328 }
329
330 /*
331 * Extract current PSW mask
332 */
__extract_psw(void)333 static inline unsigned long __extract_psw(void)
334 {
335 unsigned int reg1, reg2;
336
337 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
338 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
339 }
340
__local_mcck_save(void)341 static inline unsigned long __local_mcck_save(void)
342 {
343 unsigned long mask = __extract_psw();
344
345 __load_psw_mask(mask & ~PSW_MASK_MCHECK);
346 return mask & PSW_MASK_MCHECK;
347 }
348
349 #define local_mcck_save(mflags) \
350 do { \
351 typecheck(unsigned long, mflags); \
352 mflags = __local_mcck_save(); \
353 } while (0)
354
local_mcck_restore(unsigned long mflags)355 static inline void local_mcck_restore(unsigned long mflags)
356 {
357 unsigned long mask = __extract_psw();
358
359 mask &= ~PSW_MASK_MCHECK;
360 __load_psw_mask(mask | mflags);
361 }
362
local_mcck_disable(void)363 static inline void local_mcck_disable(void)
364 {
365 __local_mcck_save();
366 }
367
local_mcck_enable(void)368 static inline void local_mcck_enable(void)
369 {
370 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
371 }
372
373 /*
374 * Rewind PSW instruction address by specified number of bytes.
375 */
__rewind_psw(psw_t psw,long ilen)376 static inline unsigned long __rewind_psw(psw_t psw, long ilen)
377 {
378 unsigned long mask;
379
380 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
381 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
382 (1UL << 24) - 1;
383 return (psw.addr - ilen) & mask;
384 }
385
__forward_psw(psw_t psw,long ilen)386 static inline unsigned long __forward_psw(psw_t psw, long ilen)
387 {
388 return __rewind_psw(psw, -ilen);
389 }
390
391 /*
392 * Function to drop a processor into disabled wait state
393 */
disabled_wait(void)394 static __always_inline void __noreturn disabled_wait(void)
395 {
396 psw_t psw;
397
398 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
399 psw.addr = _THIS_IP_;
400 __load_psw(psw);
401 while (1);
402 }
403
404 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
405
regs_irqs_disabled(struct pt_regs * regs)406 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
407 {
408 return arch_irqs_disabled_flags(regs->psw.mask);
409 }
410
bpon(void)411 static __always_inline void bpon(void)
412 {
413 asm_inline volatile(
414 ALTERNATIVE(" nop\n",
415 " .insn rrf,0xb2e80000,0,0,13,0\n",
416 ALT_SPEC(82))
417 );
418 }
419
420 #endif /* __ASSEMBLER__ */
421
422 #endif /* __ASM_S390_PROCESSOR_H */
423