xref: /linux/drivers/gpu/drm/i915/display/intel_bios.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright © 2016-2019 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  */
23 
24 /*
25  * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
26  * the VBT from the rest of the driver. Add the parsed, clean data to struct
27  * intel_vbt_data within struct drm_i915_private.
28  */
29 
30 #ifndef _INTEL_BIOS_H_
31 #define _INTEL_BIOS_H_
32 
33 #include <linux/types.h>
34 
35 struct drm_edid;
36 struct intel_bios_encoder_data;
37 struct intel_crtc_state;
38 struct intel_display;
39 struct intel_encoder;
40 struct intel_panel;
41 enum aux_ch;
42 enum port;
43 
44 enum intel_backlight_type {
45 	INTEL_BACKLIGHT_PMIC,
46 	INTEL_BACKLIGHT_LPSS,
47 	INTEL_BACKLIGHT_DISPLAY_DDI,
48 	INTEL_BACKLIGHT_DSI_DCS,
49 	INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
50 	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
51 };
52 
53 /*
54  * MIPI Sequence Block definitions
55  *
56  * Note the VBT spec has AssertReset / DeassertReset swapped from their
57  * usual naming, we use the proper names here to avoid confusion when
58  * reading the code.
59  */
60 enum mipi_seq {
61 	MIPI_SEQ_END = 0,
62 	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
63 	MIPI_SEQ_INIT_OTP,
64 	MIPI_SEQ_DISPLAY_ON,
65 	MIPI_SEQ_DISPLAY_OFF,
66 	MIPI_SEQ_ASSERT_RESET,		/* Spec says MipiDeassertResetPin */
67 	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
68 	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
69 	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
70 	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
71 	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
72 	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
73 	MIPI_SEQ_MAX
74 };
75 
76 enum mipi_seq_element {
77 	MIPI_SEQ_ELEM_END = 0,
78 	MIPI_SEQ_ELEM_SEND_PKT,
79 	MIPI_SEQ_ELEM_DELAY,
80 	MIPI_SEQ_ELEM_GPIO,
81 	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
82 	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
83 	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
84 	MIPI_SEQ_ELEM_MAX
85 };
86 
87 #define MIPI_DSI_UNDEFINED_PANEL_ID	0
88 #define MIPI_DSI_GENERIC_PANEL_ID	1
89 
90 struct mipi_config {
91 	u16 panel_id;
92 
93 	/* General Params */
94 	u32 enable_dithering:1;
95 	u32 rsvd1:1;
96 	u32 is_bridge:1;
97 
98 	u32 panel_arch_type:2;
99 	u32 is_cmd_mode:1;
100 
101 #define NON_BURST_SYNC_PULSE	0x1
102 #define NON_BURST_SYNC_EVENTS	0x2
103 #define BURST_MODE		0x3
104 	u32 video_transfer_mode:2;
105 
106 	u32 cabc_supported:1;
107 #define PPS_BLC_PMIC   0
108 #define PPS_BLC_SOC    1
109 	u32 pwm_blc:1;
110 
111 	/* Bit 13:10 */
112 #define PIXEL_FORMAT_RGB565			0x1
113 #define PIXEL_FORMAT_RGB666			0x2
114 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
115 #define PIXEL_FORMAT_RGB888			0x4
116 	u32 videomode_color_format:4;
117 
118 	/* Bit 15:14 */
119 #define ENABLE_ROTATION_0	0x0
120 #define ENABLE_ROTATION_90	0x1
121 #define ENABLE_ROTATION_180	0x2
122 #define ENABLE_ROTATION_270	0x3
123 	u32 rotation:2;
124 	u32 bta_enabled:1;
125 	u32 rsvd2:15;
126 
127 	/* 2 byte Port Description */
128 #define DUAL_LINK_NOT_SUPPORTED	0
129 #define DUAL_LINK_FRONT_BACK	1
130 #define DUAL_LINK_PIXEL_ALT	2
131 	u16 dual_link:2;
132 	u16 lane_cnt:2;
133 	u16 pixel_overlap:3;
134 	u16 rgb_flip:1;
135 #define DL_DCS_PORT_A			0x00
136 #define DL_DCS_PORT_C			0x01
137 #define DL_DCS_PORT_A_AND_C		0x02
138 	u16 dl_dcs_cabc_ports:2;
139 	u16 dl_dcs_backlight_ports:2;
140 	u16 rsvd3:4;
141 
142 	u16 rsvd4;
143 
144 	u8 rsvd5;
145 	u32 target_burst_mode_freq;
146 	u32 dsi_ddr_clk;
147 	u32 bridge_ref_clk;
148 
149 #define  BYTE_CLK_SEL_20MHZ		0
150 #define  BYTE_CLK_SEL_10MHZ		1
151 #define  BYTE_CLK_SEL_5MHZ		2
152 	u8 byte_clk_sel:2;
153 
154 	u8 rsvd6:6;
155 
156 	/* DPHY Flags */
157 	u16 dphy_param_valid:1;
158 	u16 eot_pkt_disabled:1;
159 	u16 enable_clk_stop:1;
160 	u16 rsvd7:13;
161 
162 	u32 hs_tx_timeout;
163 	u32 lp_rx_timeout;
164 	u32 turn_around_timeout;
165 	u32 device_reset_timer;
166 	u32 master_init_timer;
167 	u32 dbi_bw_timer;
168 	u32 lp_byte_clk_val;
169 
170 	/*  4 byte Dphy Params */
171 	u32 prepare_cnt:6;
172 	u32 rsvd8:2;
173 	u32 clk_zero_cnt:8;
174 	u32 trail_cnt:5;
175 	u32 rsvd9:3;
176 	u32 exit_zero_cnt:6;
177 	u32 rsvd10:2;
178 
179 	u32 clk_lane_switch_cnt;
180 	u32 hl_switch_cnt;
181 
182 	u32 rsvd11[6];
183 
184 	/* timings based on dphy spec */
185 	u8 tclk_miss;
186 	u8 tclk_post;
187 	u8 rsvd12;
188 	u8 tclk_pre;
189 	u8 tclk_prepare;
190 	u8 tclk_settle;
191 	u8 tclk_term_enable;
192 	u8 tclk_trail;
193 	u16 tclk_prepare_clkzero;
194 	u8 rsvd13;
195 	u8 td_term_enable;
196 	u8 teot;
197 	u8 ths_exit;
198 	u8 ths_prepare;
199 	u16 ths_prepare_hszero;
200 	u8 rsvd14;
201 	u8 ths_settle;
202 	u8 ths_skip;
203 	u8 ths_trail;
204 	u8 tinit;
205 	u8 tlpx;
206 	u8 rsvd15[3];
207 
208 	/* GPIOs */
209 	u8 panel_enable;
210 	u8 bl_enable;
211 	u8 pwm_enable;
212 	u8 reset_r_n;
213 	u8 pwr_down_r;
214 	u8 stdby_r_n;
215 
216 } __packed;
217 
218 /* all delays have a unit of 100us */
219 struct mipi_pps_data {
220 	u16 panel_on_delay;
221 	u16 bl_enable_delay;
222 	u16 bl_disable_delay;
223 	u16 panel_off_delay;
224 	u16 panel_power_cycle_delay;
225 } __packed;
226 
227 void intel_bios_init(struct intel_display *display);
228 void intel_bios_init_panel_early(struct intel_display *display,
229 				 struct intel_panel *panel,
230 				 const struct intel_bios_encoder_data *devdata);
231 void intel_bios_init_panel_late(struct intel_display *display,
232 				struct intel_panel *panel,
233 				const struct intel_bios_encoder_data *devdata,
234 				const struct drm_edid *drm_edid);
235 void intel_bios_fini_panel(struct intel_panel *panel);
236 void intel_bios_driver_remove(struct intel_display *display);
237 bool intel_bios_is_valid_vbt(struct intel_display *display,
238 			     const void *buf, size_t size);
239 bool intel_bios_is_tv_present(struct intel_display *display);
240 bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);
241 bool intel_bios_is_port_present(struct intel_display *display, enum port port);
242 bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port);
243 bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
244 			       struct intel_crtc_state *crtc_state,
245 			       int dsc_max_bpc);
246 
247 const struct intel_bios_encoder_data *
248 intel_bios_encoder_data_lookup(struct intel_display *display, enum port port);
249 
250 bool intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata);
251 bool intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata);
252 bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata);
253 bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
254 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
255 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
256 bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
257 bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
258 bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
259 bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata);
260 bool intel_bios_encoder_hpd_invert(const struct intel_bios_encoder_data *devdata);
261 enum port intel_bios_encoder_port(const struct intel_bios_encoder_data *devdata);
262 enum aux_ch intel_bios_dp_aux_ch(const struct intel_bios_encoder_data *devdata);
263 int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata);
264 int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata);
265 int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata);
266 bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata);
267 int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
268 int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata);
269 int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata);
270 int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata);
271 
272 void intel_bios_for_each_encoder(struct intel_display *display,
273 				 void (*func)(struct intel_display *display,
274 					      const struct intel_bios_encoder_data *devdata));
275 
276 void intel_bios_debugfs_register(struct intel_display *display);
277 
278 #endif /* _INTEL_BIOS_H_ */
279