1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/lock.h>
31 #include <sys/mutex.h>
32 #include <sys/rman.h>
33
34 #include <machine/bus.h>
35
36 #include <dev/clk/clk.h>
37
38 #include <dt-bindings/clock/tegra124-car.h>
39 #include "tegra124_car.h"
40
41 /* #define TEGRA_PLL_DEBUG */
42 #ifdef TEGRA_PLL_DEBUG
43 #define dprintf(...) printf(__VA_ARGS__)
44 #else
45 #define dprintf(...)
46 #endif
47
48 /* All PLLs. */
49 enum pll_type {
50 PLL_M,
51 PLL_X,
52 PLL_C,
53 PLL_C2,
54 PLL_C3,
55 PLL_C4,
56 PLL_P,
57 PLL_A,
58 PLL_U,
59 PLL_D,
60 PLL_D2,
61 PLL_DP,
62 PLL_E,
63 PLL_REFE};
64
65 /* Common base register bits. */
66 #define PLL_BASE_BYPASS (1U << 31)
67 #define PLL_BASE_ENABLE (1 << 30)
68 #define PLL_BASE_REFDISABLE (1 << 29)
69 #define PLL_BASE_LOCK (1 << 27)
70 #define PLL_BASE_DIVM_SHIFT 0
71 #define PLL_BASE_DIVN_SHIFT 8
72
73 #define PLLRE_MISC_LOCK (1 << 24)
74
75 #define PLL_MISC_LOCK_ENABLE (1 << 18)
76 #define PLLC_MISC_LOCK_ENABLE (1 << 24)
77 #define PLLDU_MISC_LOCK_ENABLE (1 << 22)
78 #define PLLRE_MISC_LOCK_ENABLE (1 << 30)
79 #define PLLSS_MISC_LOCK_ENABLE (1 << 30)
80
81 #define PLLC_IDDQ_BIT 26
82 #define PLLX_IDDQ_BIT 3
83 #define PLLRE_IDDQ_BIT 16
84 #define PLLSS_IDDQ_BIT 19
85
86 #define PLL_LOCK_TIMEOUT 5000
87
88 /* Post divider <-> register value mapping. */
89 struct pdiv_table {
90 uint32_t divider; /* real divider */
91 uint32_t value; /* register value */
92 };
93
94 /* Bits definition of M, N and P fields. */
95 struct mnp_bits {
96 uint32_t m_width;
97 uint32_t n_width;
98 uint32_t p_width;
99 uint32_t p_shift;
100 };
101
102 struct clk_pll_def {
103 struct clknode_init_def clkdef;
104 enum pll_type type;
105 uint32_t base_reg;
106 uint32_t misc_reg;
107 uint32_t lock_mask;
108 uint32_t lock_enable;
109 uint32_t iddq_reg;
110 uint32_t iddq_mask;
111 uint32_t flags;
112 struct pdiv_table *pdiv_table;
113 struct mnp_bits mnp_bits;
114 };
115
116 #define PLL(_id, cname, pname) \
117 .clkdef.id = _id, \
118 .clkdef.name = cname, \
119 .clkdef.parent_names = (const char *[]){pname}, \
120 .clkdef.parent_cnt = 1, \
121 .clkdef.flags = CLK_NODE_STATIC_STRINGS
122
123 /* Tegra K1 PLLs
124 PLLM: Clock source for EMC 2x clock
125 PLLX: Clock source for the fast CPU cluster and the shadow CPU
126 PLLC: Clock source for general use
127 PLLC2: Clock source for engine scaling
128 PLLC3: Clock source for engine scaling
129 PLLC4: Clock source for ISP/VI units
130 PLLP: Clock source for most peripherals
131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
133 PLLD: Clock sources for the DSI and display subsystem
134 PLLD2: Clock sources for the DSI and display subsystem
135 refPLLe:
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
137 PLLDP: Clock source for eDP/LVDS (spread spectrum)
138
139 DFLLCPU: DFLL clock source for the fast CPU cluster
140 GPCPLL: Clock source for the GPU
141 */
142
143 static struct pdiv_table pllm_map[] = {
144 {1, 0},
145 {2, 1},
146 {0, 0}
147 };
148
149 static struct pdiv_table pllxc_map[] = {
150 { 1, 0},
151 { 2, 1},
152 { 3, 2},
153 { 4, 3},
154 { 5, 4},
155 { 6, 5},
156 { 8, 6},
157 {10, 7},
158 {12, 8},
159 {16, 9},
160 {12, 10},
161 {16, 11},
162 {20, 12},
163 {24, 13},
164 {32, 14},
165 { 0, 0}
166 };
167
168 static struct pdiv_table pllc_map[] = {
169 { 1, 0},
170 { 2, 1},
171 { 3, 2},
172 { 4, 3},
173 { 6, 4},
174 { 8, 5},
175 {12, 6},
176 {16, 7},
177 { 0, 0}
178 };
179
180 static struct pdiv_table pll12g_ssd_esd_map[] = {
181 { 1, 0},
182 { 2, 1},
183 { 3, 2},
184 { 4, 3},
185 { 5, 4},
186 { 6, 5},
187 { 8, 6},
188 {10, 7},
189 {12, 8},
190 {16, 9},
191 {12, 10},
192 {16, 11},
193 {20, 12},
194 {24, 13},
195 {32, 14},
196 { 0, 0}
197 };
198
199 static struct pdiv_table pllu_map[] = {
200 {1, 1},
201 {2, 0},
202 {0, 0}
203 };
204
205 static struct pdiv_table pllrefe_map[] = {
206 {1, 0},
207 {2, 1},
208 {3, 2},
209 {4, 3},
210 {5, 4},
211 {6, 5},
212 {0, 0},
213 };
214
215 static struct clk_pll_def pll_clks[] = {
216 /* PLLM: 880 MHz Clock source for EMC 2x clock */
217 {
218 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
219 .type = PLL_M,
220 .base_reg = PLLM_BASE,
221 .misc_reg = PLLM_MISC,
222 .lock_mask = PLL_BASE_LOCK,
223 .lock_enable = PLL_MISC_LOCK_ENABLE,
224 .pdiv_table = pllm_map,
225 .mnp_bits = {8, 8, 1, 20},
226 },
227 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
228 {
229 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
230 .type = PLL_X,
231 .base_reg = PLLX_BASE,
232 .misc_reg = PLLX_MISC,
233 .lock_mask = PLL_BASE_LOCK,
234 .lock_enable = PLL_MISC_LOCK_ENABLE,
235 .iddq_reg = PLLX_MISC3,
236 .iddq_mask = 1 << PLLX_IDDQ_BIT,
237 .pdiv_table = pllxc_map,
238 .mnp_bits = {8, 8, 4, 20},
239 },
240 /* PLLC: 600 MHz Clock source for general use */
241 {
242 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
243 .type = PLL_C,
244 .base_reg = PLLC_BASE,
245 .misc_reg = PLLC_MISC,
246 .lock_mask = PLL_BASE_LOCK,
247 .lock_enable = PLLC_MISC_LOCK_ENABLE,
248 .iddq_reg = PLLC_MISC,
249 .iddq_mask = 1 << PLLC_IDDQ_BIT,
250 .pdiv_table = pllc_map,
251 .mnp_bits = {8, 8, 4, 20},
252 },
253 /* PLLC2: 600 MHz Clock source for engine scaling */
254 {
255 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
256 .type = PLL_C2,
257 .base_reg = PLLC2_BASE,
258 .misc_reg = PLLC2_MISC,
259 .lock_mask = PLL_BASE_LOCK,
260 .lock_enable = PLL_MISC_LOCK_ENABLE,
261 .pdiv_table = pllc_map,
262 .mnp_bits = {2, 8, 3, 20},
263 },
264 /* PLLC3: 600 MHz Clock source for engine scaling */
265 {
266 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
267 .type = PLL_C3,
268 .base_reg = PLLC3_BASE,
269 .misc_reg = PLLC3_MISC,
270 .lock_mask = PLL_BASE_LOCK,
271 .lock_enable = PLL_MISC_LOCK_ENABLE,
272 .pdiv_table = pllc_map,
273 .mnp_bits = {2, 8, 3, 20},
274 },
275 /* PLLC4: 600 MHz Clock source for ISP/VI units */
276 {
277 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
278 .type = PLL_C4,
279 .base_reg = PLLC4_BASE,
280 .misc_reg = PLLC4_MISC,
281 .lock_mask = PLL_BASE_LOCK,
282 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
283 .iddq_reg = PLLC4_BASE,
284 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
285 .pdiv_table = pll12g_ssd_esd_map,
286 .mnp_bits = {8, 8, 4, 20},
287 },
288 /* PLLP: 408 MHz Clock source for most peripherals */
289 {
290 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
291 .type = PLL_P,
292 .base_reg = PLLP_BASE,
293 .misc_reg = PLLP_MISC,
294 .lock_mask = PLL_BASE_LOCK,
295 .lock_enable = PLL_MISC_LOCK_ENABLE,
296 .mnp_bits = {5, 10, 3, 20},
297 },
298 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
299 {
300 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
301 .type = PLL_A,
302 .base_reg = PLLA_BASE,
303 .misc_reg = PLLA_MISC,
304 .lock_mask = PLL_BASE_LOCK,
305 .lock_enable = PLL_MISC_LOCK_ENABLE,
306 .mnp_bits = {5, 10, 3, 20},
307 },
308 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
309 {
310 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
311 .type = PLL_U,
312 .base_reg = PLLU_BASE,
313 .misc_reg = PLLU_MISC,
314 .lock_mask = PLL_BASE_LOCK,
315 .lock_enable = PLLDU_MISC_LOCK_ENABLE,
316 .pdiv_table = pllu_map,
317 .mnp_bits = {5, 10, 1, 20},
318 },
319 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */
320 {
321 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
322 .type = PLL_D,
323 .base_reg = PLLD_BASE,
324 .misc_reg = PLLD_MISC,
325 .lock_mask = PLL_BASE_LOCK,
326 .lock_enable = PLL_MISC_LOCK_ENABLE,
327 .mnp_bits = {5, 11, 3, 20},
328 },
329 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */
330 {
331 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
332 .type = PLL_D2,
333 .base_reg = PLLD2_BASE,
334 .misc_reg = PLLD2_MISC,
335 .lock_mask = PLL_BASE_LOCK,
336 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
337 .iddq_reg = PLLD2_BASE,
338 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
339 .pdiv_table = pll12g_ssd_esd_map,
340 .mnp_bits = {8, 8, 4, 20},
341 },
342 /* refPLLe: */
343 {
344 PLL(0, "pllREFE_out", "osc_div_clk"),
345 .type = PLL_REFE,
346 .base_reg = PLLRE_BASE,
347 .misc_reg = PLLRE_MISC,
348 .lock_mask = PLLRE_MISC_LOCK,
349 .lock_enable = PLLRE_MISC_LOCK_ENABLE,
350 .iddq_reg = PLLRE_MISC,
351 .iddq_mask = 1 << PLLRE_IDDQ_BIT,
352 .pdiv_table = pllrefe_map,
353 .mnp_bits = {8, 8, 4, 16},
354 },
355 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
356 {
357 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
358 .type = PLL_E,
359 .base_reg = PLLE_BASE,
360 .misc_reg = PLLE_MISC,
361 .lock_mask = PLLE_MISC_LOCK,
362 .lock_enable = PLLE_MISC_LOCK_ENABLE,
363 .mnp_bits = {8, 8, 4, 24},
364 },
365 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */
366 {
367 PLL(0, "pllDP_out0", "pllDP_src"),
368 .type = PLL_DP,
369 .base_reg = PLLDP_BASE,
370 .misc_reg = PLLDP_MISC,
371 .lock_mask = PLL_BASE_LOCK,
372 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
373 .iddq_reg = PLLDP_BASE,
374 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
375 .pdiv_table = pll12g_ssd_esd_map,
376 .mnp_bits = {8, 8, 4, 20},
377 },
378 };
379
380 static int tegra124_pll_init(struct clknode *clk, device_t dev);
381 static int tegra124_pll_set_gate(struct clknode *clk, bool enable);
382 static int tegra124_pll_get_gate(struct clknode *clk, bool *enabled);
383 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq);
384 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin,
385 uint64_t *fout, int flags, int *stop);
386 struct pll_sc {
387 device_t clkdev;
388 enum pll_type type;
389 uint32_t base_reg;
390 uint32_t misc_reg;
391 uint32_t lock_mask;
392 uint32_t lock_enable;
393 uint32_t iddq_reg;
394 uint32_t iddq_mask;
395 uint32_t flags;
396 struct pdiv_table *pdiv_table;
397 struct mnp_bits mnp_bits;
398 };
399
400 static clknode_method_t tegra124_pll_methods[] = {
401 /* Device interface */
402 CLKNODEMETHOD(clknode_init, tegra124_pll_init),
403 CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate),
404 CLKNODEMETHOD(clknode_get_gate, tegra124_pll_get_gate),
405 CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc),
406 CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq),
407 CLKNODEMETHOD_END
408 };
409 DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods,
410 sizeof(struct pll_sc), clknode_class);
411
412 static int
pll_enable(struct pll_sc * sc)413 pll_enable(struct pll_sc *sc)
414 {
415 uint32_t reg;
416
417 RD4(sc, sc->base_reg, ®);
418 if (sc->type != PLL_E)
419 reg &= ~PLL_BASE_BYPASS;
420 reg |= PLL_BASE_ENABLE;
421 WR4(sc, sc->base_reg, reg);
422 return (0);
423 }
424
425 static int
pll_disable(struct pll_sc * sc)426 pll_disable(struct pll_sc *sc)
427 {
428 uint32_t reg;
429
430 RD4(sc, sc->base_reg, ®);
431 if (sc->type != PLL_E)
432 reg |= PLL_BASE_BYPASS;
433 reg &= ~PLL_BASE_ENABLE;
434 WR4(sc, sc->base_reg, reg);
435 return (0);
436 }
437
438 static uint32_t
pdiv_to_reg(struct pll_sc * sc,uint32_t p_div)439 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
440 {
441 struct pdiv_table *tbl;
442
443 tbl = sc->pdiv_table;
444 if (tbl == NULL)
445 return (ffs(p_div) - 1);
446
447 while (tbl->divider != 0) {
448 if (p_div <= tbl->divider)
449 return (tbl->value);
450 tbl++;
451 }
452 return (0xFFFFFFFF);
453 }
454
455 static uint32_t
reg_to_pdiv(struct pll_sc * sc,uint32_t reg)456 reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
457 {
458 struct pdiv_table *tbl;
459
460 tbl = sc->pdiv_table;
461 if (tbl == NULL)
462 return (1 << reg);
463
464 while (tbl->divider) {
465 if (reg == tbl->value)
466 return (tbl->divider);
467 tbl++;
468 }
469 return (0);
470 }
471
472 static uint32_t
get_masked(uint32_t val,uint32_t shift,uint32_t width)473 get_masked(uint32_t val, uint32_t shift, uint32_t width)
474 {
475
476 return ((val >> shift) & ((1 << width) - 1));
477 }
478
479 static uint32_t
set_masked(uint32_t val,uint32_t v,uint32_t shift,uint32_t width)480 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width)
481 {
482
483 val &= ~(((1 << width) - 1) << shift);
484 val |= (v & ((1 << width) - 1)) << shift;
485 return (val);
486 }
487
488 static void
get_divisors(struct pll_sc * sc,uint32_t * m,uint32_t * n,uint32_t * p)489 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)
490 {
491 uint32_t val;
492 struct mnp_bits *mnp_bits;
493
494 mnp_bits = &sc->mnp_bits;
495 RD4(sc, sc->base_reg, &val);
496 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
497 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
498 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
499 }
500
501 static uint32_t
set_divisors(struct pll_sc * sc,uint32_t val,uint32_t m,uint32_t n,uint32_t p)502 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,
503 uint32_t p)
504 {
505 struct mnp_bits *mnp_bits;
506
507 mnp_bits = &sc->mnp_bits;
508 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
509 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
510 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
511 return (val);
512 }
513
514 static bool
is_locked(struct pll_sc * sc)515 is_locked(struct pll_sc *sc)
516 {
517 uint32_t reg;
518
519 switch (sc->type) {
520 case PLL_REFE:
521 RD4(sc, sc->misc_reg, ®);
522 reg &= PLLRE_MISC_LOCK;
523 break;
524
525 case PLL_E:
526 RD4(sc, sc->misc_reg, ®);
527 reg &= PLLE_MISC_LOCK;
528 break;
529
530 default:
531 RD4(sc, sc->base_reg, ®);
532 reg &= PLL_BASE_LOCK;
533 break;
534 }
535 return (reg != 0);
536 }
537
538 static int
wait_for_lock(struct pll_sc * sc)539 wait_for_lock(struct pll_sc *sc)
540 {
541 int i;
542
543 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
544 if (is_locked(sc))
545 break;
546 DELAY(10);
547 }
548 if (i <= 0) {
549 printf("PLL lock timeout\n");
550 return (ETIMEDOUT);
551 }
552 return (0);
553 }
554
555 static int
plle_enable(struct pll_sc * sc)556 plle_enable(struct pll_sc *sc)
557 {
558 uint32_t reg;
559 int rv;
560 uint32_t pll_m = 1;
561 uint32_t pll_n = 200;
562 uint32_t pll_p = 13;
563 uint32_t pll_cml = 13;
564
565 /* Disable lock override. */
566 RD4(sc, sc->base_reg, ®);
567 reg &= ~PLLE_BASE_LOCK_OVERRIDE;
568 WR4(sc, sc->base_reg, reg);
569
570 RD4(sc, PLLE_AUX, ®);
571 reg |= PLLE_AUX_ENABLE_SWCTL;
572 reg &= ~PLLE_AUX_SEQ_ENABLE;
573 WR4(sc, PLLE_AUX, reg);
574 DELAY(10);
575
576 RD4(sc, sc->misc_reg, ®);
577 reg |= PLLE_MISC_LOCK_ENABLE;
578 reg |= PLLE_MISC_IDDQ_SWCTL;
579 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
580 reg |= PLLE_MISC_PTS;
581 reg |= PLLE_MISC_VREG_BG_CTRL_MASK;
582 reg |= PLLE_MISC_VREG_CTRL_MASK;
583 WR4(sc, sc->misc_reg, reg);
584 DELAY(10);
585
586 RD4(sc, PLLE_SS_CNTL, ®);
587 reg |= PLLE_SS_CNTL_DISABLE;
588 WR4(sc, PLLE_SS_CNTL, reg);
589
590 RD4(sc, sc->base_reg, ®);
591 reg = set_divisors(sc, reg, pll_m, pll_n, pll_p);
592 reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
593 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT;
594 WR4(sc, sc->base_reg, reg);
595 DELAY(10);
596
597 pll_enable(sc);
598 rv = wait_for_lock(sc);
599 if (rv != 0)
600 return (rv);
601
602 RD4(sc, PLLE_SS_CNTL, ®);
603 reg &= ~PLLE_SS_CNTL_SSCCENTER;
604 reg &= ~PLLE_SS_CNTL_SSCINVERT;
605 reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK;
606 reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL;
607 WR4(sc, PLLE_SS_CNTL, reg);
608 reg &= ~PLLE_SS_CNTL_SSCBYP;
609 reg &= ~PLLE_SS_CNTL_BYPASS_SS;
610 WR4(sc, PLLE_SS_CNTL, reg);
611 DELAY(10);
612
613 reg &= ~PLLE_SS_CNTL_INTERP_RESET;
614 WR4(sc, PLLE_SS_CNTL, reg);
615 DELAY(10);
616
617 /* HW control of brick pll. */
618 RD4(sc, sc->misc_reg, ®);
619 reg &= ~PLLE_MISC_IDDQ_SWCTL;
620 WR4(sc, sc->misc_reg, reg);
621
622 RD4(sc, PLLE_AUX, ®);
623 reg |= PLLE_AUX_USE_LOCKDET;
624 reg |= PLLE_AUX_SEQ_START_STATE;
625 reg &= ~PLLE_AUX_ENABLE_SWCTL;
626 reg &= ~PLLE_AUX_SS_SWCTL;
627 WR4(sc, PLLE_AUX, reg);
628 reg |= PLLE_AUX_SEQ_START_STATE;
629 DELAY(10);
630 reg |= PLLE_AUX_SEQ_ENABLE;
631 WR4(sc, PLLE_AUX, reg);
632
633 RD4(sc, XUSBIO_PLL_CFG0, ®);
634 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
635 reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE;
636 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
637 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
638 WR4(sc, XUSBIO_PLL_CFG0, reg);
639 DELAY(10);
640
641 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
642 WR4(sc, XUSBIO_PLL_CFG0, reg);
643
644 /* Enable HW control and unreset SATA PLL. */
645 RD4(sc, SATA_PLL_CFG0, ®);
646 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
647 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;
648 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
649 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;
650 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;
651 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;
652 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;
653 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;
654 reg |= SATA_PLL_CFG0_SEQ_START_STATE;
655 WR4(sc, SATA_PLL_CFG0, reg);
656 DELAY(10);
657 reg |= SATA_PLL_CFG0_SEQ_ENABLE;
658 WR4(sc, SATA_PLL_CFG0, reg);
659
660 /* Enable HW control of PCIe PLL. */
661 RD4(sc, PCIE_PLL_CFG0, ®);
662 reg |= PCIE_PLL_CFG0_SEQ_ENABLE;
663 WR4(sc, PCIE_PLL_CFG0, reg);
664
665 return (0);
666 }
667
668 static int
tegra124_pll_set_gate(struct clknode * clknode,bool enable)669 tegra124_pll_set_gate(struct clknode *clknode, bool enable)
670 {
671 int rv;
672 struct pll_sc *sc;
673
674 sc = clknode_get_softc(clknode);
675 if (enable == 0) {
676 rv = pll_disable(sc);
677 return(rv);
678 }
679
680 if (sc->type == PLL_E)
681 rv = plle_enable(sc);
682 else
683 rv = pll_enable(sc);
684 return (rv);
685 }
686
687 static int
tegra124_pll_get_gate(struct clknode * clknode,bool * enabled)688 tegra124_pll_get_gate(struct clknode *clknode, bool *enabled)
689 {
690 uint32_t reg;
691 struct pll_sc *sc;
692
693 sc = clknode_get_softc(clknode);
694 RD4(sc, sc->base_reg, ®);
695 *enabled = reg & PLL_BASE_ENABLE ? true: false;
696 WR4(sc, sc->base_reg, reg);
697 return (0);
698 }
699
700 static int
pll_set_std(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags,uint32_t m,uint32_t n,uint32_t p)701 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
702 uint32_t m, uint32_t n, uint32_t p)
703 {
704 uint32_t reg;
705 struct mnp_bits *mnp_bits;
706 int rv;
707
708 mnp_bits = &sc->mnp_bits;
709 if (m >= (1 << mnp_bits->m_width))
710 return (ERANGE);
711 if (n >= (1 << mnp_bits->n_width))
712 return (ERANGE);
713 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
714 return (ERANGE);
715
716 if (flags & CLK_SET_DRYRUN) {
717 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
718 (*fout != (((fin / m) * n) /p)))
719 return (ERANGE);
720
721 *fout = ((fin / m) * n) /p;
722
723 return (0);
724 }
725
726 pll_disable(sc);
727
728 /* take pll out of IDDQ */
729 if (sc->iddq_reg != 0)
730 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);
731
732 RD4(sc, sc->base_reg, ®);
733 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
734 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
735 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
736 mnp_bits->p_width);
737 WR4(sc, sc->base_reg, reg);
738
739 /* Enable PLL. */
740 RD4(sc, sc->base_reg, ®);
741 reg |= PLL_BASE_ENABLE;
742 WR4(sc, sc->base_reg, reg);
743
744 /* Enable lock detection. */
745 RD4(sc, sc->misc_reg, ®);
746 reg |= sc->lock_enable;
747 WR4(sc, sc->misc_reg, reg);
748
749 rv = wait_for_lock(sc);
750 if (rv != 0) {
751 /* Disable PLL */
752 RD4(sc, sc->base_reg, ®);
753 reg &= ~PLL_BASE_ENABLE;
754 WR4(sc, sc->base_reg, reg);
755 return (rv);
756 }
757 RD4(sc, sc->misc_reg, ®);
758
759 pll_enable(sc);
760 *fout = ((fin / m) * n) / p;
761 return 0;
762 }
763
764 static int
plla_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)765 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
766 {
767 uint32_t m, n, p;
768
769 p = 1;
770 m = 5;
771 n = (*fout * p * m + fin / 2)/ fin;
772 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
773 return (pll_set_std(sc, fin, fout, flags, m, n, p));
774 }
775
776 static int
pllc_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)777 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
778 {
779 uint32_t m, n, p;
780
781 p = 2;
782 m = 1;
783 n = (*fout * p * m + fin / 2)/ fin;
784 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
785 return (pll_set_std( sc, fin, fout, flags, m, n, p));
786 }
787
788 /*
789 * PLLD2 is used as source for pixel clock for HDMI.
790 * We must be able to set it frequency very flexibly and
791 * precisely (within 5% tolerance limit allowed by HDMI specs).
792 *
793 * For this reason, it is necessary to search the full state space.
794 * Fortunately, thanks to early cycle terminations, performance
795 * is within acceptable limits.
796 */
797 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
798 #define PLLD2_PFD_MAX 38000000 /* 38 MHz */
799 #define PLLD2_VCO_MIN 600000000 /* 600 MHz */
800 #define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */
801
802 static int
plld2_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)803 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
804 {
805 uint32_t m, n, p;
806 uint32_t best_m, best_n, best_p;
807 uint64_t vco, pfd;
808 int64_t err, best_err;
809 struct mnp_bits *mnp_bits;
810 struct pdiv_table *tbl;
811 int p_idx, rv;
812
813 mnp_bits = &sc->mnp_bits;
814 tbl = sc->pdiv_table;
815 best_err = INT64_MAX;
816
817 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
818 p = tbl[p_idx].divider;
819
820 /* Check constraints */
821 vco = *fout * p;
822 if (vco < PLLD2_VCO_MIN)
823 continue;
824 if (vco > PLLD2_VCO_MAX)
825 break;
826
827 for (m = 1; m < (1 << mnp_bits->m_width); m++) {
828 n = (*fout * p * m + fin / 2) / fin;
829
830 /* Check constraints */
831 if (n == 0)
832 continue;
833 if (n >= (1 << mnp_bits->n_width))
834 break;
835 vco = (fin * n) / m;
836 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
837 continue;
838 pfd = fin / m;
839 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
840 continue;
841
842 /* Constraints passed, save best result */
843 err = *fout - vco / p;
844 if (err < 0)
845 err = -err;
846 if (err < best_err) {
847 best_err = err;
848 best_p = p;
849 best_m = m;
850 best_n = n;
851 }
852 if (err == 0)
853 goto done;
854 }
855 }
856 done:
857 /*
858 * HDMI specification allows 5% pixel clock tolerance,
859 * we will by a slightly stricter
860 */
861 if (best_err > ((*fout * 100) / 4))
862 return (ERANGE);
863
864 if (flags & CLK_SET_DRYRUN)
865 return (0);
866 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
867 /* XXXX Panic for rv == ERANGE ? */
868 return (rv);
869 }
870
871 static int
pllrefe_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)872 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
873 {
874 uint32_t m, n, p;
875
876 m = 1;
877 p = 1;
878 n = *fout * p * m / fin;
879 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
880 return (pll_set_std(sc, fin, fout, flags, m, n, p));
881 }
882
883 static int
pllx_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)884 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
885 {
886 uint32_t reg;
887 uint32_t m, n, p;
888 struct mnp_bits *mnp_bits;
889 int rv;
890
891 mnp_bits = &sc->mnp_bits;
892
893 p = 1;
894 m = 1;
895 n = (*fout * p * m + fin / 2)/ fin;
896 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
897
898 if (m >= (1 << mnp_bits->m_width))
899 return (ERANGE);
900 if (n >= (1 << mnp_bits->n_width))
901 return (ERANGE);
902 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
903 return (ERANGE);
904
905 if (flags & CLK_SET_DRYRUN) {
906 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
907 (*fout != (((fin / m) * n) /p)))
908 return (ERANGE);
909 *fout = ((fin / m) * n) /p;
910 return (0);
911 }
912
913 /* PLLX doesn't have bypass, disable it first. */
914 RD4(sc, sc->base_reg, ®);
915 reg &= ~PLL_BASE_ENABLE;
916 WR4(sc, sc->base_reg, reg);
917
918 /* Set PLL. */
919 RD4(sc, sc->base_reg, ®);
920 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
921 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
922 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
923 mnp_bits->p_width);
924 WR4(sc, sc->base_reg, reg);
925 RD4(sc, sc->base_reg, ®);
926 DELAY(100);
927
928 /* Enable lock detection. */
929 RD4(sc, sc->misc_reg, ®);
930 reg |= sc->lock_enable;
931 WR4(sc, sc->misc_reg, reg);
932
933 /* Enable PLL. */
934 RD4(sc, sc->base_reg, ®);
935 reg |= PLL_BASE_ENABLE;
936 WR4(sc, sc->base_reg, reg);
937
938 rv = wait_for_lock(sc);
939 if (rv != 0) {
940 /* Disable PLL */
941 RD4(sc, sc->base_reg, ®);
942 reg &= ~PLL_BASE_ENABLE;
943 WR4(sc, sc->base_reg, reg);
944 return (rv);
945 }
946 RD4(sc, sc->misc_reg, ®);
947
948 *fout = ((fin / m) * n) / p;
949 return (0);
950 }
951
952 static int
tegra124_pll_set_freq(struct clknode * clknode,uint64_t fin,uint64_t * fout,int flags,int * stop)953 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
954 int flags, int *stop)
955 {
956 *stop = 1;
957 int rv;
958 struct pll_sc *sc;
959
960 sc = clknode_get_softc(clknode);
961 dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__,
962 clknode_get_name(clknode), *fout, fin);
963 switch (sc->type) {
964 case PLL_A:
965 rv = plla_set_freq(sc, fin, fout, flags);
966 break;
967 case PLL_C:
968 rv = pllc_set_freq(sc, fin, fout, flags);
969 break;
970 case PLL_D2:
971 rv = plld2_set_freq(sc, fin, fout, flags);
972 break;
973
974 case PLL_REFE:
975 rv = pllrefe_set_freq(sc, fin, fout, flags);
976 break;
977
978 case PLL_X:
979 rv = pllx_set_freq(sc, fin, fout, flags);
980 break;
981
982 case PLL_U:
983 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */
984 rv = 0;
985 else
986 rv = ERANGE;
987 break;
988 default:
989 rv = ENXIO;
990 break;
991 }
992
993 return (rv);
994 }
995
996 static int
tegra124_pll_init(struct clknode * clk,device_t dev)997 tegra124_pll_init(struct clknode *clk, device_t dev)
998 {
999 struct pll_sc *sc;
1000 uint32_t reg;
1001
1002 sc = clknode_get_softc(clk);
1003
1004 /* If PLL is enabled, enable lock detect too. */
1005 RD4(sc, sc->base_reg, ®);
1006 if (reg & PLL_BASE_ENABLE) {
1007 RD4(sc, sc->misc_reg, ®);
1008 reg |= sc->lock_enable;
1009 WR4(sc, sc->misc_reg, reg);
1010 }
1011 if (sc->type == PLL_REFE) {
1012 RD4(sc, sc->misc_reg, ®);
1013 reg &= ~(1 << 29); /* Diasble lock override */
1014 WR4(sc, sc->misc_reg, reg);
1015 }
1016
1017 clknode_init_parent_idx(clk, 0);
1018 return(0);
1019 }
1020
1021 static int
tegra124_pll_recalc(struct clknode * clk,uint64_t * freq)1022 tegra124_pll_recalc(struct clknode *clk, uint64_t *freq)
1023 {
1024 struct pll_sc *sc;
1025 uint32_t m, n, p, pr;
1026 uint32_t reg, misc_reg;
1027
1028 sc = clknode_get_softc(clk);
1029
1030 RD4(sc, sc->base_reg, ®);
1031 RD4(sc, sc->misc_reg, &misc_reg);
1032
1033 get_divisors(sc, &m, &n, &pr);
1034 if (sc->type != PLL_E)
1035 p = reg_to_pdiv(sc, pr);
1036 else
1037 p = 2 * (pr - 1);
1038
1039 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "
1040 "e: %d, r: %d, o: %d - %s\n", __func__,
1041 clknode_get_name(clk), reg, misc_reg, m, n, p, pr,
1042 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,
1043 is_locked(sc) ? "locked" : "unlocked");
1044
1045 if ((m == 0) || (n == 0) || (p == 0)) {
1046 *freq = 0;
1047 return (EINVAL);
1048 }
1049 *freq = ((*freq / m) * n) / p;
1050 return (0);
1051 }
1052
1053 static int
pll_register(struct clkdom * clkdom,struct clk_pll_def * clkdef)1054 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef)
1055 {
1056 struct clknode *clk;
1057 struct pll_sc *sc;
1058
1059 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef);
1060 if (clk == NULL)
1061 return (ENXIO);
1062
1063 sc = clknode_get_softc(clk);
1064 sc->clkdev = clknode_get_device(clk);
1065 sc->type = clkdef->type;
1066 sc->base_reg = clkdef->base_reg;
1067 sc->misc_reg = clkdef->misc_reg;
1068 sc->lock_mask = clkdef->lock_mask;
1069 sc->lock_enable = clkdef->lock_enable;
1070 sc->iddq_reg = clkdef->iddq_reg;
1071 sc->iddq_mask = clkdef->iddq_mask;
1072 sc->flags = clkdef->flags;
1073 sc->pdiv_table = clkdef->pdiv_table;
1074 sc->mnp_bits = clkdef->mnp_bits;
1075 clknode_register(clkdom, clk);
1076 return (0);
1077 }
1078
config_utmi_pll(struct tegra124_car_softc * sc)1079 static void config_utmi_pll(struct tegra124_car_softc *sc)
1080 {
1081 uint32_t reg;
1082 /*
1083 * XXX Simplified UTMIP settings for 12MHz base clock.
1084 */
1085 #define ENABLE_DELAY_COUNT 0x02
1086 #define STABLE_COUNT 0x2F
1087 #define ACTIVE_DELAY_COUNT 0x04
1088 #define XTAL_FREQ_COUNT 0x76
1089
1090 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1091 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1092 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);
1093 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1094 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);
1095 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1096 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1097 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1098 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1099
1100 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1101 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1102 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);
1103 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1104 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);
1105 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1106 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1107 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1108 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1109 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1110
1111 /* Prepare UTMIP requencer. */
1112 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1113 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1114 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1115 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1116 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1117
1118 /* Powerup UTMIP. */
1119 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1120 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1121 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1122 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1123 DELAY(10);
1124
1125 /* SW override for UTMIPLL */
1126 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1127 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1128 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1129 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1130 DELAY(10);
1131
1132 /* HW control of UTMIPLL. */
1133 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1134 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1135 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1136 }
1137
1138 void
tegra124_init_plls(struct tegra124_car_softc * sc)1139 tegra124_init_plls(struct tegra124_car_softc *sc)
1140 {
1141 int i, rv;
1142
1143 for (i = 0; i < nitems(pll_clks); i++) {
1144 rv = pll_register(sc->clkdom, pll_clks + i);
1145 if (rv != 0)
1146 panic("pll_register failed");
1147 }
1148 config_utmi_pll(sc);
1149
1150 }
1151