1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 #define RS64_FW_UC_START_ADDR_LO 0x3000 29 30 struct common_firmware_header { 31 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 32 uint32_t header_size_bytes; /* size of just the header in bytes */ 33 uint16_t header_version_major; /* header version */ 34 uint16_t header_version_minor; /* header version */ 35 uint16_t ip_version_major; /* IP version */ 36 uint16_t ip_version_minor; /* IP version */ 37 uint32_t ucode_version; 38 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 39 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 40 uint32_t crc32; /* crc32 checksum of the payload */ 41 }; 42 43 /* version_major=1, version_minor=0 */ 44 struct mc_firmware_header_v1_0 { 45 struct common_firmware_header header; 46 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 47 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 48 }; 49 50 /* version_major=1, version_minor=0 */ 51 struct smc_firmware_header_v1_0 { 52 struct common_firmware_header header; 53 uint32_t ucode_start_addr; 54 }; 55 56 /* version_major=2, version_minor=0 */ 57 struct smc_firmware_header_v2_0 { 58 struct smc_firmware_header_v1_0 v1_0; 59 uint32_t ppt_offset_bytes; /* soft pptable offset */ 60 uint32_t ppt_size_bytes; /* soft pptable size */ 61 }; 62 63 struct smc_soft_pptable_entry { 64 uint32_t id; 65 uint32_t ppt_offset_bytes; 66 uint32_t ppt_size_bytes; 67 }; 68 69 /* version_major=2, version_minor=1 */ 70 struct smc_firmware_header_v2_1 { 71 struct smc_firmware_header_v1_0 v1_0; 72 uint32_t pptable_count; 73 uint32_t pptable_entry_offset; 74 }; 75 76 struct psp_fw_legacy_bin_desc { 77 uint32_t fw_version; 78 uint32_t offset_bytes; 79 uint32_t size_bytes; 80 }; 81 82 /* version_major=1, version_minor=0 */ 83 struct psp_firmware_header_v1_0 { 84 struct common_firmware_header header; 85 struct psp_fw_legacy_bin_desc sos; 86 }; 87 88 /* version_major=1, version_minor=1 */ 89 struct psp_firmware_header_v1_1 { 90 struct psp_firmware_header_v1_0 v1_0; 91 struct psp_fw_legacy_bin_desc toc; 92 struct psp_fw_legacy_bin_desc kdb; 93 }; 94 95 /* version_major=1, version_minor=2 */ 96 struct psp_firmware_header_v1_2 { 97 struct psp_firmware_header_v1_0 v1_0; 98 struct psp_fw_legacy_bin_desc res; 99 struct psp_fw_legacy_bin_desc kdb; 100 }; 101 102 /* version_major=1, version_minor=3 */ 103 struct psp_firmware_header_v1_3 { 104 struct psp_firmware_header_v1_1 v1_1; 105 struct psp_fw_legacy_bin_desc spl; 106 struct psp_fw_legacy_bin_desc rl; 107 struct psp_fw_legacy_bin_desc sys_drv_aux; 108 struct psp_fw_legacy_bin_desc sos_aux; 109 }; 110 111 struct psp_fw_bin_desc { 112 uint32_t fw_type; 113 uint32_t fw_version; 114 uint32_t offset_bytes; 115 uint32_t size_bytes; 116 }; 117 118 enum psp_fw_type { 119 PSP_FW_TYPE_UNKOWN, 120 PSP_FW_TYPE_PSP_SOS, 121 PSP_FW_TYPE_PSP_SYS_DRV, 122 PSP_FW_TYPE_PSP_KDB, 123 PSP_FW_TYPE_PSP_TOC, 124 PSP_FW_TYPE_PSP_SPL, 125 PSP_FW_TYPE_PSP_RL, 126 PSP_FW_TYPE_PSP_SOC_DRV, 127 PSP_FW_TYPE_PSP_INTF_DRV, 128 PSP_FW_TYPE_PSP_DBG_DRV, 129 PSP_FW_TYPE_PSP_RAS_DRV, 130 PSP_FW_TYPE_PSP_IPKEYMGR_DRV, 131 PSP_FW_TYPE_PSP_SPDM_DRV, 132 PSP_FW_TYPE_MAX_INDEX, 133 }; 134 135 /* version_major=2, version_minor=0 */ 136 struct psp_firmware_header_v2_0 { 137 struct common_firmware_header header; 138 uint32_t psp_fw_bin_count; 139 struct psp_fw_bin_desc psp_fw_bin[]; 140 }; 141 142 /* version_major=2, version_minor=1 */ 143 struct psp_firmware_header_v2_1 { 144 struct common_firmware_header header; 145 uint32_t psp_fw_bin_count; 146 uint32_t psp_aux_fw_bin_index; 147 struct psp_fw_bin_desc psp_fw_bin[]; 148 }; 149 150 /* version_major=1, version_minor=0 */ 151 struct ta_firmware_header_v1_0 { 152 struct common_firmware_header header; 153 struct psp_fw_legacy_bin_desc xgmi; 154 struct psp_fw_legacy_bin_desc ras; 155 struct psp_fw_legacy_bin_desc hdcp; 156 struct psp_fw_legacy_bin_desc dtm; 157 struct psp_fw_legacy_bin_desc securedisplay; 158 }; 159 160 enum ta_fw_type { 161 TA_FW_TYPE_UNKOWN, 162 TA_FW_TYPE_PSP_ASD, 163 TA_FW_TYPE_PSP_XGMI, 164 TA_FW_TYPE_PSP_RAS, 165 TA_FW_TYPE_PSP_HDCP, 166 TA_FW_TYPE_PSP_DTM, 167 TA_FW_TYPE_PSP_RAP, 168 TA_FW_TYPE_PSP_SECUREDISPLAY, 169 TA_FW_TYPE_PSP_XGMI_AUX, 170 TA_FW_TYPE_MAX_INDEX, 171 }; 172 173 /* version_major=2, version_minor=0 */ 174 struct ta_firmware_header_v2_0 { 175 struct common_firmware_header header; 176 uint32_t ta_fw_bin_count; 177 struct psp_fw_bin_desc ta_fw_bin[]; 178 }; 179 180 /* version_major=1, version_minor=0 */ 181 struct gfx_firmware_header_v1_0 { 182 struct common_firmware_header header; 183 uint32_t ucode_feature_version; 184 uint32_t jt_offset; /* jt location */ 185 uint32_t jt_size; /* size of jt */ 186 }; 187 188 /* version_major=2, version_minor=0 */ 189 struct gfx_firmware_header_v2_0 { 190 struct common_firmware_header header; 191 uint32_t ucode_feature_version; 192 uint32_t ucode_size_bytes; 193 uint32_t ucode_offset_bytes; 194 uint32_t data_size_bytes; 195 uint32_t data_offset_bytes; 196 uint32_t ucode_start_addr_lo; 197 uint32_t ucode_start_addr_hi; 198 }; 199 200 /* version_major=1, version_minor=0 */ 201 struct mes_firmware_header_v1_0 { 202 struct common_firmware_header header; 203 uint32_t mes_ucode_version; 204 uint32_t mes_ucode_size_bytes; 205 uint32_t mes_ucode_offset_bytes; 206 uint32_t mes_ucode_data_version; 207 uint32_t mes_ucode_data_size_bytes; 208 uint32_t mes_ucode_data_offset_bytes; 209 uint32_t mes_uc_start_addr_lo; 210 uint32_t mes_uc_start_addr_hi; 211 uint32_t mes_data_start_addr_lo; 212 uint32_t mes_data_start_addr_hi; 213 }; 214 215 /* version_major=1, version_minor=0 */ 216 struct rlc_firmware_header_v1_0 { 217 struct common_firmware_header header; 218 uint32_t ucode_feature_version; 219 uint32_t save_and_restore_offset; 220 uint32_t clear_state_descriptor_offset; 221 uint32_t avail_scratch_ram_locations; 222 uint32_t master_pkt_description_offset; 223 }; 224 225 /* version_major=2, version_minor=0 */ 226 struct rlc_firmware_header_v2_0 { 227 struct common_firmware_header header; 228 uint32_t ucode_feature_version; 229 uint32_t jt_offset; /* jt location */ 230 uint32_t jt_size; /* size of jt */ 231 uint32_t save_and_restore_offset; 232 uint32_t clear_state_descriptor_offset; 233 uint32_t avail_scratch_ram_locations; 234 uint32_t reg_restore_list_size; 235 uint32_t reg_list_format_start; 236 uint32_t reg_list_format_separate_start; 237 uint32_t starting_offsets_start; 238 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 239 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 240 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 241 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 242 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 243 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 244 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 245 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 246 }; 247 248 /* version_major=2, version_minor=1 */ 249 struct rlc_firmware_header_v2_1 { 250 struct rlc_firmware_header_v2_0 v2_0; 251 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 252 uint32_t save_restore_list_cntl_ucode_ver; 253 uint32_t save_restore_list_cntl_feature_ver; 254 uint32_t save_restore_list_cntl_size_bytes; 255 uint32_t save_restore_list_cntl_offset_bytes; 256 uint32_t save_restore_list_gpm_ucode_ver; 257 uint32_t save_restore_list_gpm_feature_ver; 258 uint32_t save_restore_list_gpm_size_bytes; 259 uint32_t save_restore_list_gpm_offset_bytes; 260 uint32_t save_restore_list_srm_ucode_ver; 261 uint32_t save_restore_list_srm_feature_ver; 262 uint32_t save_restore_list_srm_size_bytes; 263 uint32_t save_restore_list_srm_offset_bytes; 264 }; 265 266 /* version_major=2, version_minor=2 */ 267 struct rlc_firmware_header_v2_2 { 268 struct rlc_firmware_header_v2_1 v2_1; 269 uint32_t rlc_iram_ucode_size_bytes; 270 uint32_t rlc_iram_ucode_offset_bytes; 271 uint32_t rlc_dram_ucode_size_bytes; 272 uint32_t rlc_dram_ucode_offset_bytes; 273 }; 274 275 /* version_major=2, version_minor=3 */ 276 struct rlc_firmware_header_v2_3 { 277 struct rlc_firmware_header_v2_2 v2_2; 278 uint32_t rlcp_ucode_version; 279 uint32_t rlcp_ucode_feature_version; 280 uint32_t rlcp_ucode_size_bytes; 281 uint32_t rlcp_ucode_offset_bytes; 282 uint32_t rlcv_ucode_version; 283 uint32_t rlcv_ucode_feature_version; 284 uint32_t rlcv_ucode_size_bytes; 285 uint32_t rlcv_ucode_offset_bytes; 286 }; 287 288 /* version_major=2, version_minor=4 */ 289 struct rlc_firmware_header_v2_4 { 290 struct rlc_firmware_header_v2_3 v2_3; 291 uint32_t global_tap_delays_ucode_size_bytes; 292 uint32_t global_tap_delays_ucode_offset_bytes; 293 uint32_t se0_tap_delays_ucode_size_bytes; 294 uint32_t se0_tap_delays_ucode_offset_bytes; 295 uint32_t se1_tap_delays_ucode_size_bytes; 296 uint32_t se1_tap_delays_ucode_offset_bytes; 297 uint32_t se2_tap_delays_ucode_size_bytes; 298 uint32_t se2_tap_delays_ucode_offset_bytes; 299 uint32_t se3_tap_delays_ucode_size_bytes; 300 uint32_t se3_tap_delays_ucode_offset_bytes; 301 }; 302 303 /* version_major=2, version_minor=5 */ 304 struct rlc_firmware_header_v2_5 { 305 struct rlc_firmware_header_v2_2 v2_2; 306 uint32_t rlc_1_iram_ucode_size_bytes; 307 uint32_t rlc_1_iram_ucode_offset_bytes; 308 uint32_t rlc_1_dram_ucode_size_bytes; 309 uint32_t rlc_1_dram_ucode_offset_bytes; 310 }; 311 312 /* version_major=1, version_minor=0 */ 313 struct sdma_firmware_header_v1_0 { 314 struct common_firmware_header header; 315 uint32_t ucode_feature_version; 316 uint32_t ucode_change_version; 317 uint32_t jt_offset; /* jt location */ 318 uint32_t jt_size; /* size of jt */ 319 }; 320 321 /* version_major=1, version_minor=1 */ 322 struct sdma_firmware_header_v1_1 { 323 struct sdma_firmware_header_v1_0 v1_0; 324 uint32_t digest_size; 325 }; 326 327 /* version_major=2, version_minor=0 */ 328 struct sdma_firmware_header_v2_0 { 329 struct common_firmware_header header; 330 uint32_t ucode_feature_version; 331 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 332 uint32_t ctx_jt_offset; /* context thread jt location */ 333 uint32_t ctx_jt_size; /* context thread size of jt */ 334 uint32_t ctl_ucode_offset; 335 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 336 uint32_t ctl_jt_offset; /* control thread jt location */ 337 uint32_t ctl_jt_size; /* control thread size of jt */ 338 }; 339 340 /* version_major=1, version_minor=0 */ 341 struct vpe_firmware_header_v1_0 { 342 struct common_firmware_header header; 343 uint32_t ucode_feature_version; 344 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 345 uint32_t ctx_jt_offset; /* context thread jt location */ 346 uint32_t ctx_jt_size; /* context thread size of jt */ 347 uint32_t ctl_ucode_offset; 348 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 349 uint32_t ctl_jt_offset; /* control thread jt location */ 350 uint32_t ctl_jt_size; /* control thread size of jt */ 351 }; 352 353 /* version_major=1, version_minor=0 */ 354 struct umsch_mm_firmware_header_v1_0 { 355 struct common_firmware_header header; 356 uint32_t umsch_mm_ucode_version; 357 uint32_t umsch_mm_ucode_size_bytes; 358 uint32_t umsch_mm_ucode_offset_bytes; 359 uint32_t umsch_mm_ucode_data_version; 360 uint32_t umsch_mm_ucode_data_size_bytes; 361 uint32_t umsch_mm_ucode_data_offset_bytes; 362 uint32_t umsch_mm_irq_start_addr_lo; 363 uint32_t umsch_mm_irq_start_addr_hi; 364 uint32_t umsch_mm_uc_start_addr_lo; 365 uint32_t umsch_mm_uc_start_addr_hi; 366 uint32_t umsch_mm_data_start_addr_lo; 367 uint32_t umsch_mm_data_start_addr_hi; 368 }; 369 370 /* version_major=3, version_minor=0 */ 371 struct sdma_firmware_header_v3_0 { 372 struct common_firmware_header header; 373 uint32_t ucode_feature_version; 374 uint32_t ucode_offset_bytes; 375 uint32_t ucode_size_bytes; 376 }; 377 378 /* gpu info payload */ 379 struct gpu_info_firmware_v1_0 { 380 uint32_t gc_num_se; 381 uint32_t gc_num_cu_per_sh; 382 uint32_t gc_num_sh_per_se; 383 uint32_t gc_num_rb_per_se; 384 uint32_t gc_num_tccs; 385 uint32_t gc_num_gprs; 386 uint32_t gc_num_max_gs_thds; 387 uint32_t gc_gs_table_depth; 388 uint32_t gc_gsprim_buff_depth; 389 uint32_t gc_parameter_cache_depth; 390 uint32_t gc_double_offchip_lds_buffer; 391 uint32_t gc_wave_size; 392 uint32_t gc_max_waves_per_simd; 393 uint32_t gc_max_scratch_slots_per_cu; 394 uint32_t gc_lds_size; 395 }; 396 397 struct gpu_info_firmware_v1_1 { 398 struct gpu_info_firmware_v1_0 v1_0; 399 uint32_t num_sc_per_sh; 400 uint32_t num_packer_per_sc; 401 }; 402 403 /* gpu info payload 404 * version_major=1, version_minor=1 */ 405 struct gpu_info_firmware_v1_2 { 406 struct gpu_info_firmware_v1_1 v1_1; 407 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 408 }; 409 410 /* version_major=1, version_minor=0 */ 411 struct gpu_info_firmware_header_v1_0 { 412 struct common_firmware_header header; 413 uint16_t version_major; /* version */ 414 uint16_t version_minor; /* version */ 415 }; 416 417 /* version_major=1, version_minor=0 */ 418 struct dmcu_firmware_header_v1_0 { 419 struct common_firmware_header header; 420 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 421 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 422 }; 423 424 /* version_major=1, version_minor=0 */ 425 struct dmcub_firmware_header_v1_0 { 426 struct common_firmware_header header; 427 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 428 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 429 }; 430 431 /* version_major=1, version_minor=0 */ 432 struct imu_firmware_header_v1_0 { 433 struct common_firmware_header header; 434 uint32_t imu_iram_ucode_size_bytes; 435 uint32_t imu_iram_ucode_offset_bytes; 436 uint32_t imu_dram_ucode_size_bytes; 437 uint32_t imu_dram_ucode_offset_bytes; 438 }; 439 440 /* header is fixed size */ 441 union amdgpu_firmware_header { 442 struct common_firmware_header common; 443 struct mc_firmware_header_v1_0 mc; 444 struct smc_firmware_header_v1_0 smc; 445 struct smc_firmware_header_v2_0 smc_v2_0; 446 struct psp_firmware_header_v1_0 psp; 447 struct psp_firmware_header_v1_1 psp_v1_1; 448 struct psp_firmware_header_v1_3 psp_v1_3; 449 struct psp_firmware_header_v2_0 psp_v2_0; 450 struct psp_firmware_header_v2_0 psp_v2_1; 451 struct ta_firmware_header_v1_0 ta; 452 struct ta_firmware_header_v2_0 ta_v2_0; 453 struct gfx_firmware_header_v1_0 gfx; 454 struct gfx_firmware_header_v2_0 gfx_v2_0; 455 struct rlc_firmware_header_v1_0 rlc; 456 struct rlc_firmware_header_v2_0 rlc_v2_0; 457 struct rlc_firmware_header_v2_1 rlc_v2_1; 458 struct rlc_firmware_header_v2_2 rlc_v2_2; 459 struct rlc_firmware_header_v2_3 rlc_v2_3; 460 struct rlc_firmware_header_v2_4 rlc_v2_4; 461 struct rlc_firmware_header_v2_5 rlc_v2_5; 462 struct sdma_firmware_header_v1_0 sdma; 463 struct sdma_firmware_header_v1_1 sdma_v1_1; 464 struct sdma_firmware_header_v2_0 sdma_v2_0; 465 struct sdma_firmware_header_v3_0 sdma_v3_0; 466 struct gpu_info_firmware_header_v1_0 gpu_info; 467 struct dmcu_firmware_header_v1_0 dmcu; 468 struct dmcub_firmware_header_v1_0 dmcub; 469 struct imu_firmware_header_v1_0 imu; 470 uint8_t raw[0x100]; 471 }; 472 473 #define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2) 474 475 /* 476 * fw loading support 477 */ 478 enum AMDGPU_UCODE_ID { 479 AMDGPU_UCODE_ID_CAP = 0, 480 AMDGPU_UCODE_ID_SDMA0, 481 AMDGPU_UCODE_ID_SDMA1, 482 AMDGPU_UCODE_ID_SDMA2, 483 AMDGPU_UCODE_ID_SDMA3, 484 AMDGPU_UCODE_ID_SDMA4, 485 AMDGPU_UCODE_ID_SDMA5, 486 AMDGPU_UCODE_ID_SDMA6, 487 AMDGPU_UCODE_ID_SDMA7, 488 AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 489 AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 490 AMDGPU_UCODE_ID_SDMA_RS64, 491 AMDGPU_UCODE_ID_CP_CE, 492 AMDGPU_UCODE_ID_CP_PFP, 493 AMDGPU_UCODE_ID_CP_ME, 494 AMDGPU_UCODE_ID_CP_RS64_PFP, 495 AMDGPU_UCODE_ID_CP_RS64_ME, 496 AMDGPU_UCODE_ID_CP_RS64_MEC, 497 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 498 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 499 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 500 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 501 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 502 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 503 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 504 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 505 AMDGPU_UCODE_ID_CP_MEC1, 506 AMDGPU_UCODE_ID_CP_MEC1_JT, 507 AMDGPU_UCODE_ID_CP_MEC2, 508 AMDGPU_UCODE_ID_CP_MEC2_JT, 509 AMDGPU_UCODE_ID_CP_MES, 510 AMDGPU_UCODE_ID_CP_MES_DATA, 511 AMDGPU_UCODE_ID_CP_MES1, 512 AMDGPU_UCODE_ID_CP_MES1_DATA, 513 AMDGPU_UCODE_ID_IMU_I, 514 AMDGPU_UCODE_ID_IMU_D, 515 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, 516 AMDGPU_UCODE_ID_SE0_TAP_DELAYS, 517 AMDGPU_UCODE_ID_SE1_TAP_DELAYS, 518 AMDGPU_UCODE_ID_SE2_TAP_DELAYS, 519 AMDGPU_UCODE_ID_SE3_TAP_DELAYS, 520 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 521 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 522 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 523 AMDGPU_UCODE_ID_RLC_IRAM, 524 AMDGPU_UCODE_ID_RLC_DRAM, 525 AMDGPU_UCODE_ID_RLC_IRAM_1, 526 AMDGPU_UCODE_ID_RLC_DRAM_1, 527 AMDGPU_UCODE_ID_RLC_P, 528 AMDGPU_UCODE_ID_RLC_V, 529 AMDGPU_UCODE_ID_RLC_G, 530 AMDGPU_UCODE_ID_STORAGE, 531 AMDGPU_UCODE_ID_SMC, 532 AMDGPU_UCODE_ID_PPTABLE, 533 AMDGPU_UCODE_ID_UVD, 534 AMDGPU_UCODE_ID_UVD1, 535 AMDGPU_UCODE_ID_VCE, 536 AMDGPU_UCODE_ID_VCN, 537 AMDGPU_UCODE_ID_VCN1, 538 AMDGPU_UCODE_ID_DMCU_ERAM, 539 AMDGPU_UCODE_ID_DMCU_INTV, 540 AMDGPU_UCODE_ID_VCN0_RAM, 541 AMDGPU_UCODE_ID_VCN1_RAM, 542 AMDGPU_UCODE_ID_DMCUB, 543 AMDGPU_UCODE_ID_VPE_CTX, 544 AMDGPU_UCODE_ID_VPE_CTL, 545 AMDGPU_UCODE_ID_VPE, 546 AMDGPU_UCODE_ID_UMSCH_MM_UCODE, 547 AMDGPU_UCODE_ID_UMSCH_MM_DATA, 548 AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER, 549 AMDGPU_UCODE_ID_P2S_TABLE, 550 AMDGPU_UCODE_ID_JPEG_RAM, 551 AMDGPU_UCODE_ID_ISP, 552 AMDGPU_UCODE_ID_MAXIMUM, 553 }; 554 555 /* engine firmware status */ 556 enum AMDGPU_UCODE_STATUS { 557 AMDGPU_UCODE_STATUS_INVALID, 558 AMDGPU_UCODE_STATUS_NOT_LOADED, 559 AMDGPU_UCODE_STATUS_LOADED, 560 }; 561 562 enum amdgpu_firmware_load_type { 563 AMDGPU_FW_LOAD_DIRECT = 0, 564 AMDGPU_FW_LOAD_PSP, 565 AMDGPU_FW_LOAD_SMU, 566 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 567 }; 568 569 enum amdgpu_ucode_required { 570 AMDGPU_UCODE_OPTIONAL, 571 AMDGPU_UCODE_REQUIRED, 572 }; 573 574 /* conform to smu_ucode_xfer_cz.h */ 575 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 576 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 577 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 578 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 579 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 580 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 581 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 582 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 583 584 /* amdgpu firmware info */ 585 struct amdgpu_firmware_info { 586 /* ucode ID */ 587 enum AMDGPU_UCODE_ID ucode_id; 588 /* request_firmware */ 589 const struct firmware *fw; 590 /* starting mc address */ 591 uint64_t mc_addr; 592 /* kernel linear address */ 593 void *kaddr; 594 /* ucode_size_bytes */ 595 uint32_t ucode_size; 596 /* starting tmr mc address */ 597 uint32_t tmr_mc_addr_lo; 598 uint32_t tmr_mc_addr_hi; 599 }; 600 601 struct amdgpu_firmware { 602 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 603 enum amdgpu_firmware_load_type load_type; 604 struct amdgpu_bo *fw_buf; 605 unsigned int fw_size; 606 unsigned int max_ucodes; 607 /* firmwares are loaded by psp instead of smu from vega10 */ 608 const struct amdgpu_psp_funcs *funcs; 609 struct amdgpu_bo *rbuf; 610 struct mutex mutex; 611 612 /* gpu info firmware data pointer */ 613 const struct firmware *gpu_info_fw; 614 615 void *fw_buf_ptr; 616 uint64_t fw_buf_mc; 617 uint32_t pldm_version; 618 }; 619 620 struct kicker_device{ 621 unsigned short device; 622 u8 revision; 623 }; 624 625 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 626 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 627 void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); 628 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 629 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 630 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 631 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 632 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 633 __printf(4, 5) 634 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 635 enum amdgpu_ucode_required required, const char *fmt, ...); 636 void amdgpu_ucode_release(const struct firmware **fw); 637 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 638 uint16_t hdr_major, uint16_t hdr_minor); 639 640 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 641 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 642 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 643 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 644 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 645 646 enum amdgpu_firmware_load_type 647 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 648 649 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 650 651 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 652 bool amdgpu_is_kicker_fw(struct amdgpu_device *adev); 653 654 #endif 655