1 /*-
2 * Copyright (c) 2015-2016 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/kernel.h>
31 #include <sys/module.h>
32 #include <sys/socket.h>
33 #include <sys/systm.h>
34 #include <sys/iov.h>
35 #include <dev/pci/pcivar.h>
36 #include <net/if.h>
37 #include <net/if_vlan_var.h>
38
39 #ifdef PCI_IOV
40 #include <sys/nv.h>
41 #include <sys/iov_schema.h>
42 #include <dev/pci/pci_iov.h>
43 #endif
44
45 #include "common/common.h"
46 #include "common/t4_regs.h"
47 #include "t4_if.h"
48
49 struct t4iov_softc {
50 device_t sc_dev;
51 device_t sc_main;
52 bool sc_attached;
53
54 int pf;
55 int regs_rid;
56 struct resource *regs_res;
57 };
58
59 struct {
60 uint16_t device;
61 char *desc;
62 } t4iov_pciids[] = {
63 {0x4000, "Chelsio T440-dbg"},
64 {0x4001, "Chelsio T420-CR"},
65 {0x4002, "Chelsio T422-CR"},
66 {0x4003, "Chelsio T440-CR"},
67 {0x4004, "Chelsio T420-BCH"},
68 {0x4005, "Chelsio T440-BCH"},
69 {0x4006, "Chelsio T440-CH"},
70 {0x4007, "Chelsio T420-SO"},
71 {0x4008, "Chelsio T420-CX"},
72 {0x4009, "Chelsio T420-BT"},
73 {0x400a, "Chelsio T404-BT"},
74 {0x400e, "Chelsio T440-LP-CR"},
75 }, t5iov_pciids[] = {
76 {0x5000, "Chelsio T580-dbg"},
77 {0x5001, "Chelsio T520-CR"}, /* 2 x 10G */
78 {0x5002, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
79 {0x5003, "Chelsio T540-CR"}, /* 4 x 10G */
80 {0x5007, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
81 {0x5009, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
82 {0x500a, "Chelsio T504-BT"}, /* 4 x 1G */
83 {0x500d, "Chelsio T580-CR"}, /* 2 x 40G */
84 {0x500e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
85 {0x5010, "Chelsio T580-LP-CR"}, /* 2 x 40G */
86 {0x5011, "Chelsio T520-LL-CR"}, /* 2 x 10G */
87 {0x5012, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
88 {0x5014, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
89 {0x5015, "Chelsio T502-BT"}, /* 2 x 1G */
90 {0x5018, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
91 {0x5019, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
92 {0x501a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
93 {0x501b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
94 }, t6iov_pciids[] = {
95 {0x6000, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
96 {0x6001, "Chelsio T6225-CR"}, /* 2 x 10/25G */
97 {0x6002, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
98 {0x6003, "Chelsio T6425-CR"}, /* 4 x 10/25G */
99 {0x6004, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
100 {0x6005, "Chelsio T6225-SO-OCP3"}, /* 2 x 10/25G, nomem */
101 {0x6006, "Chelsio T6225-OCP3"}, /* 2 x 10/25G */
102 {0x6007, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
103 {0x6008, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
104 {0x6009, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
105 {0x600d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
106 {0x6010, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
107 {0x6011, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
108 {0x6014, "Chelsio T62100-SO-OCP3"}, /* 2 x 40/50/100G, nomem */
109 {0x6015, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
110
111 /* Custom */
112 {0x6080, "Chelsio T6225 80"},
113 {0x6081, "Chelsio T62100 81"},
114 {0x6082, "Chelsio T6225-CR 82"},
115 {0x6083, "Chelsio T62100-CR 83"},
116 {0x6084, "Chelsio T64100-CR 84"},
117 {0x6085, "Chelsio T6240-SO 85"},
118 {0x6086, "Chelsio T6225-SO-CR 86"},
119 {0x6087, "Chelsio T6225-CR 87"},
120 }, t7iov_pciids[] = {
121 {0xd000, "Chelsio Terminator 7 FPGA"}, /* T7 PE12K FPGA */
122 {0x7000, "Chelsio T72200-DBG"}, /* 2 x 200G, debug */
123 {0x7001, "Chelsio T7250"}, /* 2 x 10/25/50G, 1 mem */
124 {0x7002, "Chelsio S7250"}, /* 2 x 10/25/50G, nomem */
125 {0x7003, "Chelsio T7450"}, /* 4 x 10/25/50G, 1 mem */
126 {0x7004, "Chelsio S7450"}, /* 4 x 10/25/50G, nomem */
127 {0x7005, "Chelsio T72200"}, /* 2 x 40/100/200G, 1 mem */
128 {0x7006, "Chelsio S72200"}, /* 2 x 40/100/200G, nomem */
129 {0x7007, "Chelsio T72200-FH"}, /* 2 x 40/100/200G, 2 mem */
130 {0x7008, "Chelsio T71400"}, /* 1 x 400G, nomem */
131 {0x7009, "Chelsio S7210-BT"}, /* 2 x 10GBASE-T, nomem */
132 {0x700a, "Chelsio T7450-RC"}, /* 4 x 10/25/50G, 1 mem, RC */
133 {0x700b, "Chelsio T72200-RC"}, /* 2 x 40/100/200G, 1 mem, RC */
134 {0x700c, "Chelsio T72200-FH-RC"}, /* 2 x 40/100/200G, 2 mem, RC */
135 {0x700d, "Chelsio S72200-OCP3"}, /* 2 x 40/100/200G OCP3 */
136 {0x700e, "Chelsio S7450-OCP3"}, /* 4 x 1/20/25/50G OCP3 */
137 {0x700f, "Chelsio S7410-BT-OCP3"}, /* 4 x 10GBASE-T OCP3 */
138 {0x7010, "Chelsio S7210-BT-A"}, /* 2 x 10GBASE-T */
139 {0x7011, "Chelsio T7_MAYRA_7"}, /* Motherboard */
140
141 {0x7080, "Custom T7"},
142 };
143
144 static inline uint32_t
t4iov_read_reg(struct t4iov_softc * sc,uint32_t reg)145 t4iov_read_reg(struct t4iov_softc *sc, uint32_t reg)
146 {
147
148 return bus_read_4(sc->regs_res, reg);
149 }
150
151 static int t4iov_attach_child(device_t dev);
152
153 static int
t4iov_probe(device_t dev)154 t4iov_probe(device_t dev)
155 {
156 uint16_t d;
157 size_t i;
158
159 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO)
160 return (ENXIO);
161
162 d = pci_get_device(dev);
163 for (i = 0; i < nitems(t4iov_pciids); i++) {
164 if (d == t4iov_pciids[i].device) {
165 device_set_desc(dev, t4iov_pciids[i].desc);
166 device_quiet(dev);
167 return (BUS_PROBE_DEFAULT);
168 }
169 }
170 return (ENXIO);
171 }
172
173 static int
t5iov_probe(device_t dev)174 t5iov_probe(device_t dev)
175 {
176 uint16_t d;
177 size_t i;
178
179 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO)
180 return (ENXIO);
181
182 d = pci_get_device(dev);
183 for (i = 0; i < nitems(t5iov_pciids); i++) {
184 if (d == t5iov_pciids[i].device) {
185 device_set_desc(dev, t5iov_pciids[i].desc);
186 device_quiet(dev);
187 return (BUS_PROBE_DEFAULT);
188 }
189 }
190 return (ENXIO);
191 }
192
193 static int
t6iov_probe(device_t dev)194 t6iov_probe(device_t dev)
195 {
196 uint16_t d;
197 size_t i;
198
199 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO)
200 return (ENXIO);
201
202 d = pci_get_device(dev);
203 for (i = 0; i < nitems(t6iov_pciids); i++) {
204 if (d == t6iov_pciids[i].device) {
205 device_set_desc(dev, t6iov_pciids[i].desc);
206 device_quiet(dev);
207 return (BUS_PROBE_DEFAULT);
208 }
209 }
210 return (ENXIO);
211 }
212
213 static int
chiov_probe(device_t dev)214 chiov_probe(device_t dev)
215 {
216 uint16_t d;
217 size_t i;
218
219 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO)
220 return (ENXIO);
221
222 d = pci_get_device(dev);
223 for (i = 0; i < nitems(t7iov_pciids); i++) {
224 if (d == t7iov_pciids[i].device) {
225 device_set_desc(dev, t7iov_pciids[i].desc);
226 device_quiet(dev);
227 return (BUS_PROBE_DEFAULT);
228 }
229 }
230 return (ENXIO);
231 }
232
233 static int
t4iov_attach(device_t dev)234 t4iov_attach(device_t dev)
235 {
236 struct t4iov_softc *sc;
237 uint32_t pl_rev, whoami;
238 int error;
239
240 sc = device_get_softc(dev);
241 sc->sc_dev = dev;
242
243 sc->regs_rid = PCIR_BAR(0);
244 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
245 &sc->regs_rid, RF_ACTIVE);
246 if (sc->regs_res == NULL) {
247 device_printf(dev, "cannot map registers.\n");
248 return (ENXIO);
249 }
250
251 pl_rev = t4iov_read_reg(sc, A_PL_REV);
252 whoami = t4iov_read_reg(sc, A_PL_WHOAMI);
253 if (G_CHIPID(pl_rev) <= CHELSIO_T5)
254 sc->pf = G_SOURCEPF(whoami);
255 else
256 sc->pf = G_T6_SOURCEPF(whoami);
257
258 sc->sc_main = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
259 pci_get_slot(dev), 4);
260 if (sc->sc_main == NULL) {
261 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
262 sc->regs_res);
263 return (ENXIO);
264 }
265 if (T4_IS_MAIN_READY(sc->sc_main) == 0) {
266 error = t4iov_attach_child(dev);
267 if (error != 0)
268 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
269 sc->regs_res);
270 return (error);
271 }
272 return (0);
273 }
274
275 static int
t4iov_attach_child(device_t dev)276 t4iov_attach_child(device_t dev)
277 {
278 struct t4iov_softc *sc;
279 #ifdef PCI_IOV
280 nvlist_t *pf_schema, *vf_schema;
281 #endif
282 device_t pdev;
283 int error;
284
285 sc = device_get_softc(dev);
286 MPASS(!sc->sc_attached);
287
288 /*
289 * PF0-3 are associated with a specific port on the NIC (PF0
290 * with port 0, etc.). Ask the PF4 driver for the device for
291 * this function's associated port to determine if the port is
292 * present.
293 */
294 error = T4_READ_PORT_DEVICE(sc->sc_main, pci_get_function(dev), &pdev);
295 if (error)
296 return (0);
297
298 #ifdef PCI_IOV
299 pf_schema = pci_iov_schema_alloc_node();
300 vf_schema = pci_iov_schema_alloc_node();
301 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL);
302 pci_iov_schema_add_vlan(vf_schema, "vlan", 0, 0);
303 error = pci_iov_attach_name(dev, pf_schema, vf_schema, "%s",
304 device_get_nameunit(pdev));
305 if (error) {
306 device_printf(dev, "Failed to initialize SR-IOV: %d\n", error);
307 return (0);
308 }
309 #endif
310
311 sc->sc_attached = true;
312 return (0);
313 }
314
315 static int
t4iov_detach_child(device_t dev)316 t4iov_detach_child(device_t dev)
317 {
318 struct t4iov_softc *sc;
319 #ifdef PCI_IOV
320 int error;
321 #endif
322
323 sc = device_get_softc(dev);
324 if (!sc->sc_attached)
325 return (0);
326
327 #ifdef PCI_IOV
328 error = pci_iov_detach(dev);
329 if (error != 0) {
330 device_printf(dev, "Failed to disable SR-IOV\n");
331 return (error);
332 }
333 #endif
334
335 sc->sc_attached = false;
336 return (0);
337 }
338
339 static int
t4iov_detach(device_t dev)340 t4iov_detach(device_t dev)
341 {
342 struct t4iov_softc *sc;
343 int error;
344
345 sc = device_get_softc(dev);
346 if (sc->sc_attached) {
347 error = t4iov_detach_child(dev);
348 if (error)
349 return (error);
350 }
351 if (sc->regs_res) {
352 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
353 sc->regs_res);
354 }
355 return (0);
356 }
357
358 #ifdef PCI_IOV
359 static int
t4iov_iov_init(device_t dev,uint16_t num_vfs,const struct nvlist * config)360 t4iov_iov_init(device_t dev, uint16_t num_vfs, const struct nvlist *config)
361 {
362
363 /* XXX: The Linux driver sets up a vf_monitor task on T4 adapters. */
364 return (0);
365 }
366
367 static void
t4iov_iov_uninit(device_t dev)368 t4iov_iov_uninit(device_t dev)
369 {
370 }
371
372 static int
t4iov_add_vf(device_t dev,uint16_t vfnum,const struct nvlist * config)373 t4iov_add_vf(device_t dev, uint16_t vfnum, const struct nvlist *config)
374 {
375 const void *mac;
376 struct t4iov_softc *sc;
377 struct adapter *adap;
378 uint8_t ma[ETHER_ADDR_LEN];
379 size_t size;
380 int rc;
381
382 sc = device_get_softc(dev);
383 MPASS(sc->sc_attached);
384 MPASS(sc->sc_main != NULL);
385 adap = device_get_softc(sc->sc_main);
386
387 if (nvlist_exists_binary(config, "mac-addr")) {
388 mac = nvlist_get_binary(config, "mac-addr", &size);
389 bcopy(mac, ma, ETHER_ADDR_LEN);
390
391 if (begin_synchronized_op(adap, NULL, SLEEP_OK | INTR_OK,
392 "t4vfma") != 0)
393 return (ENXIO);
394 rc = -t4_set_vf_mac(adap, sc->pf, vfnum + 1, 1, ma);
395 end_synchronized_op(adap, 0);
396 if (rc != 0) {
397 device_printf(dev,
398 "Failed to set VF%d MAC address to "
399 "%02x:%02x:%02x:%02x:%02x:%02x, rc = %d\n", vfnum,
400 ma[0], ma[1], ma[2], ma[3], ma[4], ma[5], rc);
401 return (rc);
402 }
403 }
404
405 if (nvlist_exists_number(config, "vlan")) {
406 uint16_t vlan = nvlist_get_number(config, "vlan");
407
408 /* We can't restrict to VID 0 */
409 if (vlan == DOT1Q_VID_NULL)
410 return (ENOTSUP);
411
412 if (vlan == VF_VLAN_TRUNK)
413 vlan = DOT1Q_VID_NULL;
414
415 if (begin_synchronized_op(adap, NULL, SLEEP_OK | INTR_OK,
416 "t4vfvl") != 0)
417 return (ENXIO);
418 rc = t4_set_vlan_acl(adap, sc->pf, vfnum + 1, vlan);
419 end_synchronized_op(adap, 0);
420 if (rc != 0) {
421 device_printf(dev,
422 "Failed to set VF%d VLAN to %d, rc = %d\n",
423 vfnum, vlan, rc);
424 return (rc);
425 }
426 }
427
428 return (0);
429 }
430 #endif
431
432 static device_method_t t4iov_methods[] = {
433 DEVMETHOD(device_probe, t4iov_probe),
434 DEVMETHOD(device_attach, t4iov_attach),
435 DEVMETHOD(device_detach, t4iov_detach),
436
437 #ifdef PCI_IOV
438 DEVMETHOD(pci_iov_init, t4iov_iov_init),
439 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit),
440 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf),
441 #endif
442
443 DEVMETHOD(t4_attach_child, t4iov_attach_child),
444 DEVMETHOD(t4_detach_child, t4iov_detach_child),
445
446 DEVMETHOD_END
447 };
448
449 static driver_t t4iov_driver = {
450 "t4iov",
451 t4iov_methods,
452 sizeof(struct t4iov_softc)
453 };
454
455 static device_method_t t5iov_methods[] = {
456 DEVMETHOD(device_probe, t5iov_probe),
457 DEVMETHOD(device_attach, t4iov_attach),
458 DEVMETHOD(device_detach, t4iov_detach),
459
460 #ifdef PCI_IOV
461 DEVMETHOD(pci_iov_init, t4iov_iov_init),
462 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit),
463 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf),
464 #endif
465
466 DEVMETHOD(t4_attach_child, t4iov_attach_child),
467 DEVMETHOD(t4_detach_child, t4iov_detach_child),
468
469 DEVMETHOD_END
470 };
471
472 static driver_t t5iov_driver = {
473 "t5iov",
474 t5iov_methods,
475 sizeof(struct t4iov_softc)
476 };
477
478 static device_method_t t6iov_methods[] = {
479 DEVMETHOD(device_probe, t6iov_probe),
480 DEVMETHOD(device_attach, t4iov_attach),
481 DEVMETHOD(device_detach, t4iov_detach),
482
483 #ifdef PCI_IOV
484 DEVMETHOD(pci_iov_init, t4iov_iov_init),
485 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit),
486 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf),
487 #endif
488
489 DEVMETHOD(t4_attach_child, t4iov_attach_child),
490 DEVMETHOD(t4_detach_child, t4iov_detach_child),
491
492 DEVMETHOD_END
493 };
494
495 static driver_t t6iov_driver = {
496 "t6iov",
497 t6iov_methods,
498 sizeof(struct t4iov_softc)
499 };
500
501 static device_method_t chiov_methods[] = {
502 DEVMETHOD(device_probe, chiov_probe),
503 DEVMETHOD(device_attach, t4iov_attach),
504 DEVMETHOD(device_detach, t4iov_detach),
505
506 #ifdef PCI_IOV
507 DEVMETHOD(pci_iov_init, t4iov_iov_init),
508 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit),
509 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf),
510 #endif
511
512 DEVMETHOD(t4_attach_child, t4iov_attach_child),
513 DEVMETHOD(t4_detach_child, t4iov_detach_child),
514
515 DEVMETHOD_END
516 };
517
518 static driver_t chiov_driver = {
519 "chiov",
520 chiov_methods,
521 sizeof(struct t4iov_softc)
522 };
523 DRIVER_MODULE(t4iov, pci, t4iov_driver, 0, 0);
524 MODULE_VERSION(t4iov, 1);
525
526 DRIVER_MODULE(t5iov, pci, t5iov_driver, 0, 0);
527 MODULE_VERSION(t5iov, 1);
528
529 DRIVER_MODULE(t6iov, pci, t6iov_driver, 0, 0);
530 MODULE_VERSION(t6iov, 1);
531
532 DRIVER_MODULE(chiov, pci, chiov_driver, 0, 0);
533 MODULE_VERSION(chiov, 1);
534