1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2025 Chelsio Communications. 5 * Written by: Navdeep Parhar <np@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_inet.h" 31 #include "opt_inet6.h" 32 #include "opt_kern_tls.h" 33 #include "opt_ratelimit.h" 34 35 #include <sys/types.h> 36 #include <sys/eventhandler.h> 37 #include <sys/mbuf.h> 38 #include <sys/socket.h> 39 #include <sys/kernel.h> 40 #include <sys/ktls.h> 41 #include <sys/malloc.h> 42 #include <sys/msan.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/socketvar.h> 51 #include <sys/counter.h> 52 #include <net/bpf.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_vlan_var.h> 56 #include <net/if_vxlan.h> 57 #include <netinet/in.h> 58 #include <netinet/ip.h> 59 #include <netinet/ip6.h> 60 #include <netinet/tcp.h> 61 #include <netinet/udp.h> 62 #include <machine/in_cksum.h> 63 #include <machine/md_var.h> 64 #include <vm/vm.h> 65 #include <vm/pmap.h> 66 #ifdef DEV_NETMAP 67 #include <machine/bus.h> 68 #include <sys/selinfo.h> 69 #include <net/if_var.h> 70 #include <net/netmap.h> 71 #include <dev/netmap/netmap_kern.h> 72 #endif 73 74 #include "common/common.h" 75 #include "common/t4_regs.h" 76 #include "common/t4_regs_values.h" 77 #include "common/t4_msg.h" 78 #include "t4_l2t.h" 79 #include "t4_mp_ring.h" 80 81 #define RX_COPY_THRESHOLD MINCLSIZE 82 83 /* 84 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 85 * 0-7 are valid values. 86 */ 87 static int fl_pktshift = 0; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 89 "payload DMA offset in rx buffer (bytes)"); 90 91 /* 92 * Pad ethernet payload up to this boundary. 93 * -1: driver should figure out a good value. 94 * 0: disable padding. 95 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 96 */ 97 int fl_pad = -1; 98 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 99 "payload pad boundary (bytes)"); 100 101 /* 102 * Status page length. 103 * -1: driver should figure out a good value. 104 * 64 or 128 are the only other valid values. 105 */ 106 static int spg_len = -1; 107 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 108 "status page size (bytes)"); 109 110 /* 111 * Congestion drops. 112 * -1: no congestion feedback (not recommended). 113 * 0: backpressure the channel instead of dropping packets right away. 114 * 1: no backpressure, drop packets for the congested queue immediately. 115 * 2: both backpressure and drop. 116 */ 117 static int cong_drop = 0; 118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 119 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both"); 120 #ifdef TCP_OFFLOAD 121 static int ofld_cong_drop = 0; 122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0, 123 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both"); 124 #endif 125 126 /* 127 * Deliver multiple frames in the same free list buffer if they fit. 128 * -1: let the driver decide whether to enable buffer packing or not. 129 * 0: disable buffer packing. 130 * 1: enable buffer packing. 131 */ 132 static int buffer_packing = -1; 133 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 134 0, "Enable buffer packing"); 135 136 /* 137 * Start next frame in a packed buffer at this boundary. 138 * -1: driver should figure out a good value. 139 * T4: driver will ignore this and use the same value as fl_pad above. 140 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 141 */ 142 static int fl_pack = -1; 143 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 144 "payload pack boundary (bytes)"); 145 146 /* 147 * Largest rx cluster size that the driver is allowed to allocate. 148 */ 149 static int largest_rx_cluster = MJUM16BYTES; 150 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 151 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 152 153 /* 154 * Size of cluster allocation that's most likely to succeed. The driver will 155 * fall back to this size if it fails to allocate clusters larger than this. 156 */ 157 static int safest_rx_cluster = PAGE_SIZE; 158 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 159 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 160 161 #ifdef RATELIMIT 162 /* 163 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 164 * for rewriting. -1 and 0-3 are all valid values. 165 * -1: hardware should leave the TCP timestamps alone. 166 * 0: 1ms 167 * 1: 100us 168 * 2: 10us 169 * 3: 1us 170 */ 171 static int tsclk = -1; 172 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 173 "Control TCP timestamp rewriting when using pacing"); 174 175 static int eo_max_backlog = 1024 * 1024; 176 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 177 0, "Maximum backlog of ratelimited data per flow"); 178 #endif 179 180 /* 181 * The interrupt holdoff timers are multiplied by this value on T6+. 182 * 1 and 3-17 (both inclusive) are legal values. 183 */ 184 static int tscale = 1; 185 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 186 "Interrupt holdoff timer scale on T6+"); 187 188 /* 189 * Number of LRO entries in the lro_ctrl structure per rx queue. 190 */ 191 static int lro_entries = TCP_LRO_ENTRIES; 192 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 193 "Number of LRO entries per RX queue"); 194 195 /* 196 * This enables presorting of frames before they're fed into tcp_lro_rx. 197 */ 198 static int lro_mbufs = 0; 199 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 200 "Enable presorting of LRO frames"); 201 202 static counter_u64_t pullups; 203 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 204 "Number of mbuf pullups performed"); 205 206 static counter_u64_t defrags; 207 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 208 "Number of mbuf defrags performed"); 209 210 static int t4_tx_coalesce = 1; 211 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 212 "tx coalescing allowed"); 213 214 /* 215 * The driver will make aggressive attempts at tx coalescing if it sees these 216 * many packets eligible for coalescing in quick succession, with no more than 217 * the specified gap in between the eth_tx calls that delivered the packets. 218 */ 219 static int t4_tx_coalesce_pkts = 32; 220 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 221 &t4_tx_coalesce_pkts, 0, 222 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 223 static int t4_tx_coalesce_gap = 5; 224 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 225 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 226 227 static int service_iq(struct sge_iq *, int); 228 static int service_iq_fl(struct sge_iq *, int); 229 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 230 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 231 u_int); 232 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 233 int, int, int); 234 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 235 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 236 struct sge_iq *, char *); 237 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 238 struct sysctl_ctx_list *, struct sysctl_oid *); 239 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 240 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 241 struct sge_iq *); 242 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 243 struct sysctl_oid *, struct sge_fl *); 244 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 245 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 246 static int alloc_fwq(struct adapter *); 247 static void free_fwq(struct adapter *); 248 static int alloc_ctrlq(struct adapter *, int); 249 static void free_ctrlq(struct adapter *, int); 250 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 251 static void free_rxq(struct vi_info *, struct sge_rxq *); 252 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 253 struct sge_rxq *); 254 #ifdef TCP_OFFLOAD 255 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 256 int); 257 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 258 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 259 struct sge_ofld_rxq *); 260 #endif 261 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *, int); 262 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *, 263 int); 264 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 265 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *, 266 int); 267 #endif 268 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 269 struct sysctl_oid *); 270 static void free_eq(struct adapter *, struct sge_eq *); 271 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 272 struct sysctl_oid *, struct sge_eq *); 273 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *, 274 int); 275 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 276 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 277 struct sysctl_ctx_list *, struct sysctl_oid *); 278 static void free_wrq(struct adapter *, struct sge_wrq *); 279 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 280 struct sge_wrq *); 281 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 282 static void free_txq(struct vi_info *, struct sge_txq *); 283 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 284 struct sysctl_oid *, struct sge_txq *); 285 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 286 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 287 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 288 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 289 struct sge_ofld_txq *); 290 #endif 291 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 292 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 293 static int refill_fl(struct adapter *, struct sge_fl *, int); 294 static void refill_sfl(void *); 295 static int find_refill_source(struct adapter *, int, bool); 296 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 297 298 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 299 static inline u_int txpkt_len16(u_int, const u_int); 300 static inline u_int txpkt_vm_len16(u_int, const u_int); 301 static inline void calculate_mbuf_len16(struct mbuf *, bool); 302 static inline u_int txpkts0_len16(u_int); 303 static inline u_int txpkts1_len16(void); 304 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 305 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 306 u_int); 307 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 308 struct mbuf *); 309 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 310 int, bool *); 311 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 312 int, bool *); 313 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 314 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 315 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 316 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 317 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 318 static inline uint16_t read_hw_cidx(struct sge_eq *); 319 static inline u_int reclaimable_tx_desc(struct sge_eq *); 320 static inline u_int total_available_tx_desc(struct sge_eq *); 321 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 322 static void tx_reclaim(void *, int); 323 static __be64 get_flit(struct sglist_seg *, int, int); 324 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 325 struct mbuf *); 326 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 327 struct mbuf *); 328 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 329 static void wrq_tx_drain(void *, int); 330 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 331 332 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 333 #ifdef RATELIMIT 334 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 335 struct mbuf *); 336 #if defined(INET) || defined(INET6) 337 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 338 static int ethofld_transmit(if_t, struct mbuf *); 339 #endif 340 #endif 341 342 static counter_u64_t extfree_refs; 343 static counter_u64_t extfree_rels; 344 345 an_handler_t t4_an_handler; 346 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 347 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 348 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 349 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 350 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 351 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 352 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 353 cpl_handler_t fw6_pld_handlers[NUM_CPL_FW6_COOKIES]; 354 355 void 356 t4_register_an_handler(an_handler_t h) 357 { 358 uintptr_t *loc; 359 360 MPASS(h == NULL || t4_an_handler == NULL); 361 362 loc = (uintptr_t *)&t4_an_handler; 363 atomic_store_rel_ptr(loc, (uintptr_t)h); 364 } 365 366 void 367 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 368 { 369 uintptr_t *loc; 370 371 MPASS(type < nitems(t4_fw_msg_handler)); 372 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 373 /* 374 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 375 * handler dispatch table. Reject any attempt to install a handler for 376 * this subtype. 377 */ 378 MPASS(type != FW_TYPE_RSSCPL); 379 MPASS(type != FW6_TYPE_RSSCPL); 380 381 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 382 atomic_store_rel_ptr(loc, (uintptr_t)h); 383 } 384 385 void 386 t4_register_cpl_handler(int opcode, cpl_handler_t h) 387 { 388 uintptr_t *loc; 389 390 MPASS(opcode < nitems(t4_cpl_handler)); 391 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 392 393 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 394 atomic_store_rel_ptr(loc, (uintptr_t)h); 395 } 396 397 static int 398 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 399 struct mbuf *m) 400 { 401 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 402 u_int tid; 403 int cookie; 404 405 MPASS(m == NULL); 406 407 tid = GET_TID(cpl); 408 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 409 /* 410 * The return code for filter-write is put in the CPL cookie so 411 * we have to rely on the hardware tid (is_ftid) to determine 412 * that this is a response to a filter. 413 */ 414 cookie = CPL_COOKIE_FILTER; 415 } else { 416 cookie = G_COOKIE(cpl->cookie); 417 } 418 MPASS(cookie > CPL_COOKIE_RESERVED); 419 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 420 421 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 422 } 423 424 static int 425 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 426 struct mbuf *m) 427 { 428 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 429 unsigned int cookie; 430 431 MPASS(m == NULL); 432 433 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 434 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 435 } 436 437 static int 438 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 439 struct mbuf *m) 440 { 441 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 442 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 443 444 MPASS(m == NULL); 445 MPASS(cookie != CPL_COOKIE_RESERVED); 446 447 return (act_open_rpl_handlers[cookie](iq, rss, m)); 448 } 449 450 static int 451 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 452 struct mbuf *m) 453 { 454 struct adapter *sc = iq->adapter; 455 u_int cookie; 456 457 MPASS(m == NULL); 458 if (is_hashfilter(sc)) 459 cookie = CPL_COOKIE_HASHFILTER; 460 else 461 cookie = CPL_COOKIE_TOM; 462 463 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 464 } 465 466 static int 467 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 468 { 469 struct adapter *sc = iq->adapter; 470 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 471 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 472 u_int cookie; 473 474 MPASS(m == NULL); 475 if (is_etid(sc, tid)) 476 cookie = CPL_COOKIE_ETHOFLD; 477 else 478 cookie = CPL_COOKIE_TOM; 479 480 return (fw4_ack_handlers[cookie](iq, rss, m)); 481 } 482 483 static int 484 fw6_pld_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 485 { 486 const struct cpl_fw6_pld *cpl; 487 uint64_t cookie; 488 489 if (m != NULL) 490 cpl = mtod(m, const void *); 491 else 492 cpl = (const void *)(rss + 1); 493 cookie = be64toh(cpl->data[1]) & CPL_FW6_COOKIE_MASK; 494 495 return (fw6_pld_handlers[cookie](iq, rss, m)); 496 } 497 498 static void 499 t4_init_shared_cpl_handlers(void) 500 { 501 502 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 503 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 504 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 505 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 506 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 507 t4_register_cpl_handler(CPL_FW6_PLD, fw6_pld_handler); 508 } 509 510 void 511 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 512 { 513 uintptr_t *loc; 514 515 MPASS(opcode < nitems(t4_cpl_handler)); 516 if (opcode == CPL_FW6_PLD) { 517 MPASS(cookie < NUM_CPL_FW6_COOKIES); 518 } else { 519 MPASS(cookie > CPL_COOKIE_RESERVED); 520 MPASS(cookie < NUM_CPL_COOKIES); 521 } 522 MPASS(t4_cpl_handler[opcode] != NULL); 523 524 switch (opcode) { 525 case CPL_SET_TCB_RPL: 526 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 527 break; 528 case CPL_L2T_WRITE_RPL: 529 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 530 break; 531 case CPL_ACT_OPEN_RPL: 532 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 533 break; 534 case CPL_ABORT_RPL_RSS: 535 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 536 break; 537 case CPL_FW4_ACK: 538 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 539 break; 540 case CPL_FW6_PLD: 541 loc = (uintptr_t *)&fw6_pld_handlers[cookie]; 542 break; 543 default: 544 MPASS(0); 545 return; 546 } 547 MPASS(h == NULL || *loc == (uintptr_t)NULL); 548 atomic_store_rel_ptr(loc, (uintptr_t)h); 549 } 550 551 /* 552 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 553 */ 554 void 555 t4_sge_modload(void) 556 { 557 558 if (fl_pktshift < 0 || fl_pktshift > 7) { 559 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 560 " using 0 instead.\n", fl_pktshift); 561 fl_pktshift = 0; 562 } 563 564 if (spg_len != 64 && spg_len != 128) { 565 int len; 566 567 #if defined(__i386__) || defined(__amd64__) 568 len = cpu_clflush_line_size > 64 ? 128 : 64; 569 #else 570 len = 64; 571 #endif 572 if (spg_len != -1) { 573 printf("Invalid hw.cxgbe.spg_len value (%d)," 574 " using %d instead.\n", spg_len, len); 575 } 576 spg_len = len; 577 } 578 579 if (cong_drop < -1 || cong_drop > 2) { 580 printf("Invalid hw.cxgbe.cong_drop value (%d)," 581 " using 0 instead.\n", cong_drop); 582 cong_drop = 0; 583 } 584 #ifdef TCP_OFFLOAD 585 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) { 586 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d)," 587 " using 0 instead.\n", ofld_cong_drop); 588 ofld_cong_drop = 0; 589 } 590 #endif 591 592 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 593 printf("Invalid hw.cxgbe.tscale value (%d)," 594 " using 1 instead.\n", tscale); 595 tscale = 1; 596 } 597 598 if (largest_rx_cluster != MCLBYTES && 599 #if MJUMPAGESIZE != MCLBYTES 600 largest_rx_cluster != MJUMPAGESIZE && 601 #endif 602 largest_rx_cluster != MJUM9BYTES && 603 largest_rx_cluster != MJUM16BYTES) { 604 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 605 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 606 largest_rx_cluster = MJUM16BYTES; 607 } 608 609 if (safest_rx_cluster != MCLBYTES && 610 #if MJUMPAGESIZE != MCLBYTES 611 safest_rx_cluster != MJUMPAGESIZE && 612 #endif 613 safest_rx_cluster != MJUM9BYTES && 614 safest_rx_cluster != MJUM16BYTES) { 615 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 616 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 617 safest_rx_cluster = MJUMPAGESIZE; 618 } 619 620 extfree_refs = counter_u64_alloc(M_WAITOK); 621 extfree_rels = counter_u64_alloc(M_WAITOK); 622 pullups = counter_u64_alloc(M_WAITOK); 623 defrags = counter_u64_alloc(M_WAITOK); 624 counter_u64_zero(extfree_refs); 625 counter_u64_zero(extfree_rels); 626 counter_u64_zero(pullups); 627 counter_u64_zero(defrags); 628 629 t4_init_shared_cpl_handlers(); 630 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 631 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 632 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 633 #ifdef RATELIMIT 634 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 635 CPL_COOKIE_ETHOFLD); 636 #endif 637 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 638 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 639 } 640 641 void 642 t4_sge_modunload(void) 643 { 644 645 counter_u64_free(extfree_refs); 646 counter_u64_free(extfree_rels); 647 counter_u64_free(pullups); 648 counter_u64_free(defrags); 649 } 650 651 uint64_t 652 t4_sge_extfree_refs(void) 653 { 654 uint64_t refs, rels; 655 656 rels = counter_u64_fetch(extfree_rels); 657 refs = counter_u64_fetch(extfree_refs); 658 659 return (refs - rels); 660 } 661 662 /* max 4096 */ 663 #define MAX_PACK_BOUNDARY 512 664 665 static inline void 666 setup_pad_and_pack_boundaries(struct adapter *sc) 667 { 668 uint32_t v, m; 669 int pad, pack, pad_shift; 670 671 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 672 X_INGPADBOUNDARY_SHIFT; 673 pad = fl_pad; 674 if (fl_pad < (1 << pad_shift) || 675 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 676 !powerof2(fl_pad)) { 677 /* 678 * If there is any chance that we might use buffer packing and 679 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 680 * it to the minimum allowed in all other cases. 681 */ 682 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 683 684 /* 685 * For fl_pad = 0 we'll still write a reasonable value to the 686 * register but all the freelists will opt out of padding. 687 * We'll complain here only if the user tried to set it to a 688 * value greater than 0 that was invalid. 689 */ 690 if (fl_pad > 0) { 691 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 692 " (%d), using %d instead.\n", fl_pad, pad); 693 } 694 } 695 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 696 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 697 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 698 699 if (is_t4(sc)) { 700 if (fl_pack != -1 && fl_pack != pad) { 701 /* Complain but carry on. */ 702 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 703 " using %d instead.\n", fl_pack, pad); 704 } 705 return; 706 } 707 708 pack = fl_pack; 709 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 710 !powerof2(fl_pack)) { 711 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 712 pack = MAX_PACK_BOUNDARY; 713 else 714 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 715 MPASS(powerof2(pack)); 716 if (pack < 16) 717 pack = 16; 718 if (pack == 32) 719 pack = 64; 720 if (pack > 4096) 721 pack = 4096; 722 if (fl_pack != -1) { 723 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 724 " (%d), using %d instead.\n", fl_pack, pack); 725 } 726 } 727 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 728 if (pack == 16) 729 v = V_INGPACKBOUNDARY(0); 730 else 731 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 732 733 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 734 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 735 } 736 737 /* 738 * adap->params.vpd.cclk must be set up before this is called. 739 */ 740 void 741 t4_tweak_chip_settings(struct adapter *sc) 742 { 743 int i, reg; 744 uint32_t v, m; 745 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 746 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 747 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 748 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 749 static int sw_buf_sizes[] = { 750 MCLBYTES, 751 #if MJUMPAGESIZE != MCLBYTES 752 MJUMPAGESIZE, 753 #endif 754 MJUM9BYTES, 755 MJUM16BYTES 756 }; 757 758 KASSERT(sc->flags & MASTER_PF, 759 ("%s: trying to change chip settings when not master.", __func__)); 760 761 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 762 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 763 V_EGRSTATUSPAGESIZE(spg_len == 128); 764 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 765 766 setup_pad_and_pack_boundaries(sc); 767 768 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 769 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 770 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 771 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 772 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 773 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 774 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 775 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 776 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 777 778 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 779 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 780 reg = A_SGE_FL_BUFFER_SIZE2; 781 for (i = 0; i < nitems(sw_buf_sizes); i++) { 782 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 783 t4_write_reg(sc, reg, sw_buf_sizes[i]); 784 reg += 4; 785 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 786 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 787 reg += 4; 788 } 789 790 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 791 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 792 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 793 794 KASSERT(intr_timer[0] <= timer_max, 795 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 796 timer_max)); 797 for (i = 1; i < nitems(intr_timer); i++) { 798 KASSERT(intr_timer[i] >= intr_timer[i - 1], 799 ("%s: timers not listed in increasing order (%d)", 800 __func__, i)); 801 802 while (intr_timer[i] > timer_max) { 803 if (i == nitems(intr_timer) - 1) { 804 intr_timer[i] = timer_max; 805 break; 806 } 807 intr_timer[i] += intr_timer[i - 1]; 808 intr_timer[i] /= 2; 809 } 810 } 811 812 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 813 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 814 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 815 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 816 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 817 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 818 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 819 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 820 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 821 822 if (chip_id(sc) >= CHELSIO_T6) { 823 m = V_TSCALE(M_TSCALE); 824 if (tscale == 1) 825 v = 0; 826 else 827 v = V_TSCALE(tscale - 2); 828 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 829 830 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 831 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 832 V_WRTHRTHRESH(M_WRTHRTHRESH); 833 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 834 v &= ~m; 835 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 836 V_WRTHRTHRESH(16); 837 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 838 } 839 } 840 841 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 842 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 843 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 844 845 /* 846 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 847 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 848 * may have to deal with is MAXPHYS + 1 page. 849 */ 850 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 851 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 852 853 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 854 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 855 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 856 857 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 858 F_RESETDDPOFFSET; 859 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 860 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 861 } 862 863 /* 864 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 865 * address mut be 16B aligned. If padding is in use the buffer's start and end 866 * need to be aligned to the pad boundary as well. We'll just make sure that 867 * the size is a multiple of the pad boundary here, it is up to the buffer 868 * allocation code to make sure the start of the buffer is aligned. 869 */ 870 static inline int 871 hwsz_ok(struct adapter *sc, int hwsz) 872 { 873 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 874 875 return (hwsz >= 64 && (hwsz & mask) == 0); 876 } 877 878 /* 879 * Initialize the rx buffer sizes and figure out which zones the buffers will 880 * be allocated from. 881 */ 882 void 883 t4_init_rx_buf_info(struct adapter *sc) 884 { 885 struct sge *s = &sc->sge; 886 struct sge_params *sp = &sc->params.sge; 887 int i, j, n; 888 static int sw_buf_sizes[] = { /* Sorted by size */ 889 MCLBYTES, 890 #if MJUMPAGESIZE != MCLBYTES 891 MJUMPAGESIZE, 892 #endif 893 MJUM9BYTES, 894 MJUM16BYTES 895 }; 896 struct rx_buf_info *rxb; 897 898 s->safe_zidx = -1; 899 rxb = &s->rx_buf_info[0]; 900 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 901 rxb->size1 = sw_buf_sizes[i]; 902 rxb->zone = m_getzone(rxb->size1); 903 rxb->type = m_gettype(rxb->size1); 904 rxb->size2 = 0; 905 rxb->hwidx1 = -1; 906 rxb->hwidx2 = -1; 907 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 908 int hwsize = sp->sge_fl_buffer_size[j]; 909 910 if (!hwsz_ok(sc, hwsize)) 911 continue; 912 913 /* hwidx for size1 */ 914 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 915 rxb->hwidx1 = j; 916 917 /* hwidx for size2 (buffer packing) */ 918 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 919 continue; 920 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 921 if (n == 0) { 922 rxb->hwidx2 = j; 923 rxb->size2 = hwsize; 924 break; /* stop looking */ 925 } 926 if (rxb->hwidx2 != -1) { 927 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 928 hwsize - CL_METADATA_SIZE) { 929 rxb->hwidx2 = j; 930 rxb->size2 = hwsize; 931 } 932 } else if (n <= 2 * CL_METADATA_SIZE) { 933 rxb->hwidx2 = j; 934 rxb->size2 = hwsize; 935 } 936 } 937 if (rxb->hwidx2 != -1) 938 sc->flags |= BUF_PACKING_OK; 939 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 940 s->safe_zidx = i; 941 } 942 } 943 944 /* 945 * Verify some basic SGE settings for the PF and VF driver, and other 946 * miscellaneous settings for the PF driver. 947 */ 948 int 949 t4_verify_chip_settings(struct adapter *sc) 950 { 951 struct sge_params *sp = &sc->params.sge; 952 uint32_t m, v, r; 953 int rc = 0; 954 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 955 956 m = F_RXPKTCPLMODE; 957 v = F_RXPKTCPLMODE; 958 r = sp->sge_control; 959 if ((r & m) != v) { 960 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 961 rc = EINVAL; 962 } 963 964 /* 965 * If this changes then every single use of PAGE_SHIFT in the driver 966 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 967 */ 968 if (sp->page_shift != PAGE_SHIFT) { 969 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 970 rc = EINVAL; 971 } 972 973 if (sc->flags & IS_VF) 974 return (0); 975 976 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 977 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 978 if (r != v) { 979 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 980 if (sc->vres.ddp.size != 0) 981 rc = EINVAL; 982 } 983 984 m = v = F_TDDPTAGTCB; 985 r = t4_read_reg(sc, A_ULP_RX_CTL); 986 if ((r & m) != v) { 987 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 988 if (sc->vres.ddp.size != 0) 989 rc = EINVAL; 990 } 991 992 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 993 F_RESETDDPOFFSET; 994 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 995 r = t4_read_reg(sc, A_TP_PARA_REG5); 996 if ((r & m) != v) { 997 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 998 if (sc->vres.ddp.size != 0) 999 rc = EINVAL; 1000 } 1001 1002 return (rc); 1003 } 1004 1005 int 1006 t4_create_dma_tag(struct adapter *sc) 1007 { 1008 int rc; 1009 1010 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 1011 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 1012 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 1013 NULL, &sc->dmat); 1014 if (rc != 0) { 1015 device_printf(sc->dev, 1016 "failed to create main DMA tag: %d\n", rc); 1017 } 1018 1019 return (rc); 1020 } 1021 1022 void 1023 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1024 struct sysctl_oid_list *children) 1025 { 1026 struct sge_params *sp = &sc->params.sge; 1027 1028 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1029 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1030 sysctl_bufsizes, "A", "freelist buffer sizes"); 1031 1032 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1033 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1034 1035 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1036 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1037 1038 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1039 NULL, sp->spg_len, "status page size (bytes)"); 1040 1041 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1042 NULL, cong_drop, "congestion drop setting"); 1043 #ifdef TCP_OFFLOAD 1044 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD, 1045 NULL, ofld_cong_drop, "congestion drop setting"); 1046 #endif 1047 1048 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1049 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1050 } 1051 1052 int 1053 t4_destroy_dma_tag(struct adapter *sc) 1054 { 1055 if (sc->dmat) 1056 bus_dma_tag_destroy(sc->dmat); 1057 1058 return (0); 1059 } 1060 1061 /* 1062 * Allocate and initialize the firmware event queue, control queues, and special 1063 * purpose rx queues owned by the adapter. 1064 * 1065 * Returns errno on failure. Resources allocated up to that point may still be 1066 * allocated. Caller is responsible for cleanup in case this function fails. 1067 */ 1068 int 1069 t4_setup_adapter_queues(struct adapter *sc) 1070 { 1071 int rc, i; 1072 1073 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1074 1075 /* 1076 * Firmware event queue 1077 */ 1078 rc = alloc_fwq(sc); 1079 if (rc != 0) 1080 return (rc); 1081 1082 /* 1083 * That's all for the VF driver. 1084 */ 1085 if (sc->flags & IS_VF) 1086 return (rc); 1087 1088 /* 1089 * XXX: General purpose rx queues, one per port. 1090 */ 1091 1092 /* 1093 * Control queues. At least one per port and per internal core. 1094 */ 1095 for (i = 0; i < sc->sge.nctrlq; i++) { 1096 rc = alloc_ctrlq(sc, i); 1097 if (rc != 0) 1098 return (rc); 1099 } 1100 1101 return (rc); 1102 } 1103 1104 /* 1105 * Idempotent 1106 */ 1107 int 1108 t4_teardown_adapter_queues(struct adapter *sc) 1109 { 1110 int i; 1111 1112 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1113 1114 if (sc->sge.ctrlq != NULL) { 1115 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */ 1116 for (i = 0; i < sc->sge.nctrlq; i++) 1117 free_ctrlq(sc, i); 1118 } 1119 free_fwq(sc); 1120 1121 return (0); 1122 } 1123 1124 /* Maximum payload that could arrive with a single iq descriptor. */ 1125 static inline int 1126 max_rx_payload(struct adapter *sc, if_t ifp, const bool ofld) 1127 { 1128 int maxp; 1129 1130 /* large enough even when hw VLAN extraction is disabled */ 1131 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1132 ETHER_VLAN_ENCAP_LEN + if_getmtu(ifp); 1133 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1134 maxp < sc->params.tp.max_rx_pdu) 1135 maxp = sc->params.tp.max_rx_pdu; 1136 return (maxp); 1137 } 1138 1139 int 1140 t4_setup_vi_queues(struct vi_info *vi) 1141 { 1142 int rc = 0, i, intr_idx; 1143 struct sge_rxq *rxq; 1144 struct sge_txq *txq; 1145 #ifdef TCP_OFFLOAD 1146 struct sge_ofld_rxq *ofld_rxq; 1147 #endif 1148 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1149 struct sge_ofld_txq *ofld_txq; 1150 #endif 1151 #ifdef DEV_NETMAP 1152 int saved_idx, iqidx; 1153 struct sge_nm_rxq *nm_rxq; 1154 struct sge_nm_txq *nm_txq; 1155 #endif 1156 struct adapter *sc = vi->adapter; 1157 if_t ifp = vi->ifp; 1158 int maxp; 1159 1160 /* Interrupt vector to start from (when using multiple vectors) */ 1161 intr_idx = vi->first_intr; 1162 1163 #ifdef DEV_NETMAP 1164 saved_idx = intr_idx; 1165 if (if_getcapabilities(ifp) & IFCAP_NETMAP) { 1166 1167 /* netmap is supported with direct interrupts only. */ 1168 MPASS(!forwarding_intr_to_fwq(sc)); 1169 MPASS(vi->first_intr >= 0); 1170 1171 /* 1172 * We don't have buffers to back the netmap rx queues 1173 * right now so we create the queues in a way that 1174 * doesn't set off any congestion signal in the chip. 1175 */ 1176 for_each_nm_rxq(vi, i, nm_rxq) { 1177 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1178 if (rc != 0) 1179 goto done; 1180 intr_idx++; 1181 } 1182 1183 for_each_nm_txq(vi, i, nm_txq) { 1184 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1185 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1186 if (rc != 0) 1187 goto done; 1188 } 1189 } 1190 1191 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1192 intr_idx = saved_idx; 1193 #endif 1194 1195 /* 1196 * Allocate rx queues first because a default iqid is required when 1197 * creating a tx queue. 1198 */ 1199 maxp = max_rx_payload(sc, ifp, false); 1200 for_each_rxq(vi, i, rxq) { 1201 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1202 if (rc != 0) 1203 goto done; 1204 if (!forwarding_intr_to_fwq(sc)) 1205 intr_idx++; 1206 } 1207 #ifdef DEV_NETMAP 1208 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 1209 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1210 #endif 1211 #ifdef TCP_OFFLOAD 1212 maxp = max_rx_payload(sc, ifp, true); 1213 for_each_ofld_rxq(vi, i, ofld_rxq) { 1214 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1215 if (rc != 0) 1216 goto done; 1217 if (!forwarding_intr_to_fwq(sc)) 1218 intr_idx++; 1219 } 1220 #endif 1221 1222 /* 1223 * Now the tx queues. 1224 */ 1225 for_each_txq(vi, i, txq) { 1226 rc = alloc_txq(vi, txq, i); 1227 if (rc != 0) 1228 goto done; 1229 } 1230 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1231 for_each_ofld_txq(vi, i, ofld_txq) { 1232 rc = alloc_ofld_txq(vi, ofld_txq, i); 1233 if (rc != 0) 1234 goto done; 1235 } 1236 #endif 1237 done: 1238 if (rc) 1239 t4_teardown_vi_queues(vi); 1240 1241 return (rc); 1242 } 1243 1244 /* 1245 * Idempotent 1246 */ 1247 int 1248 t4_teardown_vi_queues(struct vi_info *vi) 1249 { 1250 int i; 1251 struct sge_rxq *rxq; 1252 struct sge_txq *txq; 1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1254 struct sge_ofld_txq *ofld_txq; 1255 #endif 1256 #ifdef TCP_OFFLOAD 1257 struct sge_ofld_rxq *ofld_rxq; 1258 #endif 1259 #ifdef DEV_NETMAP 1260 struct sge_nm_rxq *nm_rxq; 1261 struct sge_nm_txq *nm_txq; 1262 #endif 1263 1264 #ifdef DEV_NETMAP 1265 if (if_getcapabilities(vi->ifp) & IFCAP_NETMAP) { 1266 for_each_nm_txq(vi, i, nm_txq) { 1267 free_nm_txq(vi, nm_txq); 1268 } 1269 1270 for_each_nm_rxq(vi, i, nm_rxq) { 1271 free_nm_rxq(vi, nm_rxq); 1272 } 1273 } 1274 #endif 1275 1276 /* 1277 * Take down all the tx queues first, as they reference the rx queues 1278 * (for egress updates, etc.). 1279 */ 1280 1281 for_each_txq(vi, i, txq) { 1282 free_txq(vi, txq); 1283 } 1284 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1285 for_each_ofld_txq(vi, i, ofld_txq) { 1286 free_ofld_txq(vi, ofld_txq); 1287 } 1288 #endif 1289 1290 /* 1291 * Then take down the rx queues. 1292 */ 1293 1294 for_each_rxq(vi, i, rxq) { 1295 free_rxq(vi, rxq); 1296 } 1297 #ifdef TCP_OFFLOAD 1298 for_each_ofld_rxq(vi, i, ofld_rxq) { 1299 free_ofld_rxq(vi, ofld_rxq); 1300 } 1301 #endif 1302 1303 return (0); 1304 } 1305 1306 /* 1307 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1308 * unusual scenario. 1309 * 1310 * a) Deals with errors, if any. 1311 * b) Services firmware event queue, which is taking interrupts for all other 1312 * queues. 1313 */ 1314 void 1315 t4_intr_all(void *arg) 1316 { 1317 struct adapter *sc = arg; 1318 struct sge_iq *fwq = &sc->sge.fwq; 1319 1320 MPASS(sc->intr_count == 1); 1321 1322 if (sc->intr_type == INTR_INTX) 1323 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1324 1325 t4_intr_err(arg); 1326 t4_intr_evt(fwq); 1327 } 1328 1329 /* 1330 * Interrupt handler for errors (installed directly when multiple interrupts are 1331 * being used, or called by t4_intr_all). 1332 */ 1333 void 1334 t4_intr_err(void *arg) 1335 { 1336 struct adapter *sc = arg; 1337 uint32_t v; 1338 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1339 1340 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR) 1341 return; 1342 1343 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1344 if (v & F_PFSW) { 1345 sc->swintr++; 1346 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1347 } 1348 1349 if (t4_slow_intr_handler(sc, verbose)) 1350 t4_fatal_err(sc, false); 1351 } 1352 1353 /* 1354 * Interrupt handler for iq-only queues. The firmware event queue is the only 1355 * such queue right now. 1356 */ 1357 void 1358 t4_intr_evt(void *arg) 1359 { 1360 struct sge_iq *iq = arg; 1361 1362 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1363 service_iq(iq, 0); 1364 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1365 } 1366 } 1367 1368 /* 1369 * Interrupt handler for iq+fl queues. 1370 */ 1371 void 1372 t4_intr(void *arg) 1373 { 1374 struct sge_iq *iq = arg; 1375 1376 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1377 service_iq_fl(iq, 0); 1378 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1379 } 1380 } 1381 1382 #ifdef DEV_NETMAP 1383 /* 1384 * Interrupt handler for netmap rx queues. 1385 */ 1386 void 1387 t4_nm_intr(void *arg) 1388 { 1389 struct sge_nm_rxq *nm_rxq = arg; 1390 1391 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1392 service_nm_rxq(nm_rxq); 1393 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1394 } 1395 } 1396 1397 /* 1398 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1399 */ 1400 void 1401 t4_vi_intr(void *arg) 1402 { 1403 struct irq *irq = arg; 1404 1405 MPASS(irq->nm_rxq != NULL); 1406 t4_nm_intr(irq->nm_rxq); 1407 1408 MPASS(irq->rxq != NULL); 1409 t4_intr(irq->rxq); 1410 } 1411 #endif 1412 1413 /* 1414 * Deals with interrupts on an iq-only (no freelist) queue. 1415 */ 1416 static int 1417 service_iq(struct sge_iq *iq, int budget) 1418 { 1419 struct sge_iq *q; 1420 struct adapter *sc = iq->adapter; 1421 struct iq_desc *d = &iq->desc[iq->cidx]; 1422 int ndescs = 0, limit; 1423 int rsp_type; 1424 uint32_t lq; 1425 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1426 1427 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1428 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1429 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1430 iq->flags)); 1431 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1432 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1433 1434 limit = budget ? budget : iq->qsize / 16; 1435 1436 /* 1437 * We always come back and check the descriptor ring for new indirect 1438 * interrupts and other responses after running a single handler. 1439 */ 1440 for (;;) { 1441 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1442 1443 rmb(); 1444 1445 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1446 lq = be32toh(d->rsp.pldbuflen_qid); 1447 1448 switch (rsp_type) { 1449 case X_RSPD_TYPE_FLBUF: 1450 panic("%s: data for an iq (%p) with no freelist", 1451 __func__, iq); 1452 1453 /* NOTREACHED */ 1454 1455 case X_RSPD_TYPE_CPL: 1456 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1457 ("%s: bad opcode %02x.", __func__, 1458 d->rss.opcode)); 1459 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1460 break; 1461 1462 case X_RSPD_TYPE_INTR: 1463 /* 1464 * There are 1K interrupt-capable queues (qids 0 1465 * through 1023). A response type indicating a 1466 * forwarded interrupt with a qid >= 1K is an 1467 * iWARP async notification. 1468 */ 1469 if (__predict_true(lq >= 1024)) { 1470 t4_an_handler(iq, &d->rsp); 1471 break; 1472 } 1473 1474 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1475 sc->sge.iq_base]; 1476 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1477 IQS_BUSY)) { 1478 if (service_iq_fl(q, q->qsize / 16) == 0) { 1479 (void) atomic_cmpset_int(&q->state, 1480 IQS_BUSY, IQS_IDLE); 1481 } else { 1482 STAILQ_INSERT_TAIL(&iql, q, 1483 link); 1484 } 1485 } 1486 break; 1487 1488 default: 1489 KASSERT(0, 1490 ("%s: illegal response type %d on iq %p", 1491 __func__, rsp_type, iq)); 1492 log(LOG_ERR, 1493 "%s: illegal response type %d on iq %p", 1494 device_get_nameunit(sc->dev), rsp_type, iq); 1495 break; 1496 } 1497 1498 d++; 1499 if (__predict_false(++iq->cidx == iq->sidx)) { 1500 iq->cidx = 0; 1501 iq->gen ^= F_RSPD_GEN; 1502 d = &iq->desc[0]; 1503 } 1504 if (__predict_false(++ndescs == limit)) { 1505 t4_write_reg(sc, sc->sge_gts_reg, 1506 V_CIDXINC(ndescs) | 1507 V_INGRESSQID(iq->cntxt_id) | 1508 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1509 ndescs = 0; 1510 1511 if (budget) { 1512 return (EINPROGRESS); 1513 } 1514 } 1515 } 1516 1517 if (STAILQ_EMPTY(&iql)) 1518 break; 1519 1520 /* 1521 * Process the head only, and send it to the back of the list if 1522 * it's still not done. 1523 */ 1524 q = STAILQ_FIRST(&iql); 1525 STAILQ_REMOVE_HEAD(&iql, link); 1526 if (service_iq_fl(q, q->qsize / 8) == 0) 1527 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1528 else 1529 STAILQ_INSERT_TAIL(&iql, q, link); 1530 } 1531 1532 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1533 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1534 1535 return (0); 1536 } 1537 1538 #if defined(INET) || defined(INET6) 1539 static inline int 1540 sort_before_lro(struct lro_ctrl *lro) 1541 { 1542 1543 return (lro->lro_mbuf_max != 0); 1544 } 1545 #endif 1546 1547 #define CGBE_SHIFT_SCALE 10 1548 1549 static inline uint64_t 1550 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf) 1551 { 1552 struct clock_sync *cur, dcur; 1553 uint64_t hw_clocks; 1554 uint64_t hw_clk_div; 1555 sbintime_t sbt_cur_to_prev, sbt; 1556 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */ 1557 seqc_t gen; 1558 1559 for (;;) { 1560 cur = &sc->cal_info[sc->cal_current]; 1561 gen = seqc_read(&cur->gen); 1562 if (gen == 0) 1563 return (0); 1564 dcur = *cur; 1565 if (seqc_consistent(&cur->gen, gen)) 1566 break; 1567 } 1568 1569 /* 1570 * Our goal here is to have a result that is: 1571 * 1572 * ( (cur_time - prev_time) ) 1573 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time 1574 * ( (hw_cur - hw_prev) ) 1575 * 1576 * With the constraints that we cannot use float and we 1577 * don't want to overflow the uint64_t numbers we are using. 1578 */ 1579 hw_clocks = hw_tstmp - dcur.hw_prev; 1580 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev); 1581 hw_clk_div = dcur.hw_cur - dcur.hw_prev; 1582 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev; 1583 return (sbttons(sbt)); 1584 } 1585 1586 static inline void 1587 move_to_next_rxbuf(struct sge_fl *fl) 1588 { 1589 1590 fl->rx_offset = 0; 1591 if (__predict_false((++fl->cidx & 7) == 0)) { 1592 uint16_t cidx = fl->cidx >> 3; 1593 1594 if (__predict_false(cidx == fl->sidx)) 1595 fl->cidx = cidx = 0; 1596 fl->hw_cidx = cidx; 1597 } 1598 } 1599 1600 /* 1601 * Deals with interrupts on an iq+fl queue. 1602 */ 1603 static int 1604 service_iq_fl(struct sge_iq *iq, int budget) 1605 { 1606 struct sge_rxq *rxq = iq_to_rxq(iq); 1607 struct sge_fl *fl; 1608 struct adapter *sc = iq->adapter; 1609 struct iq_desc *d = &iq->desc[iq->cidx]; 1610 int ndescs, limit; 1611 int rsp_type, starved; 1612 uint32_t lq; 1613 uint16_t fl_hw_cidx; 1614 struct mbuf *m0; 1615 #if defined(INET) || defined(INET6) 1616 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1617 struct lro_ctrl *lro = &rxq->lro; 1618 #endif 1619 1620 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1621 MPASS(iq->flags & IQ_HAS_FL); 1622 1623 ndescs = 0; 1624 #if defined(INET) || defined(INET6) 1625 if (iq->flags & IQ_ADJ_CREDIT) { 1626 MPASS(sort_before_lro(lro)); 1627 iq->flags &= ~IQ_ADJ_CREDIT; 1628 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1629 tcp_lro_flush_all(lro); 1630 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1631 V_INGRESSQID((u32)iq->cntxt_id) | 1632 V_SEINTARM(iq->intr_params)); 1633 return (0); 1634 } 1635 ndescs = 1; 1636 } 1637 #else 1638 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1639 #endif 1640 1641 limit = budget ? budget : iq->qsize / 16; 1642 fl = &rxq->fl; 1643 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1644 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1645 1646 rmb(); 1647 1648 m0 = NULL; 1649 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1650 lq = be32toh(d->rsp.pldbuflen_qid); 1651 1652 switch (rsp_type) { 1653 case X_RSPD_TYPE_FLBUF: 1654 if (lq & F_RSPD_NEWBUF) { 1655 if (fl->rx_offset > 0) 1656 move_to_next_rxbuf(fl); 1657 lq = G_RSPD_LEN(lq); 1658 } 1659 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1660 FL_LOCK(fl); 1661 refill_fl(sc, fl, 64); 1662 FL_UNLOCK(fl); 1663 fl_hw_cidx = fl->hw_cidx; 1664 } 1665 1666 if (d->rss.opcode == CPL_RX_PKT) { 1667 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1668 break; 1669 goto out; 1670 } 1671 m0 = get_fl_payload(sc, fl, lq); 1672 if (__predict_false(m0 == NULL)) 1673 goto out; 1674 1675 /* fall through */ 1676 1677 case X_RSPD_TYPE_CPL: 1678 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1679 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1680 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1681 break; 1682 1683 case X_RSPD_TYPE_INTR: 1684 1685 /* 1686 * There are 1K interrupt-capable queues (qids 0 1687 * through 1023). A response type indicating a 1688 * forwarded interrupt with a qid >= 1K is an 1689 * iWARP async notification. That is the only 1690 * acceptable indirect interrupt on this queue. 1691 */ 1692 if (__predict_false(lq < 1024)) { 1693 panic("%s: indirect interrupt on iq_fl %p " 1694 "with qid %u", __func__, iq, lq); 1695 } 1696 1697 t4_an_handler(iq, &d->rsp); 1698 break; 1699 1700 default: 1701 KASSERT(0, ("%s: illegal response type %d on iq %p", 1702 __func__, rsp_type, iq)); 1703 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1704 device_get_nameunit(sc->dev), rsp_type, iq); 1705 break; 1706 } 1707 1708 d++; 1709 if (__predict_false(++iq->cidx == iq->sidx)) { 1710 iq->cidx = 0; 1711 iq->gen ^= F_RSPD_GEN; 1712 d = &iq->desc[0]; 1713 } 1714 if (__predict_false(++ndescs == limit)) { 1715 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1716 V_INGRESSQID(iq->cntxt_id) | 1717 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1718 1719 #if defined(INET) || defined(INET6) 1720 if (iq->flags & IQ_LRO_ENABLED && 1721 !sort_before_lro(lro) && 1722 sc->lro_timeout != 0) { 1723 tcp_lro_flush_inactive(lro, &lro_timeout); 1724 } 1725 #endif 1726 if (budget) 1727 return (EINPROGRESS); 1728 ndescs = 0; 1729 } 1730 } 1731 out: 1732 #if defined(INET) || defined(INET6) 1733 if (iq->flags & IQ_LRO_ENABLED) { 1734 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1735 MPASS(sort_before_lro(lro)); 1736 /* hold back one credit and don't flush LRO state */ 1737 iq->flags |= IQ_ADJ_CREDIT; 1738 ndescs--; 1739 } else { 1740 tcp_lro_flush_all(lro); 1741 } 1742 } 1743 #endif 1744 1745 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1746 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1747 1748 FL_LOCK(fl); 1749 starved = refill_fl(sc, fl, 64); 1750 FL_UNLOCK(fl); 1751 if (__predict_false(starved != 0)) 1752 add_fl_to_sfl(sc, fl); 1753 1754 return (0); 1755 } 1756 1757 static inline struct cluster_metadata * 1758 cl_metadata(struct fl_sdesc *sd) 1759 { 1760 1761 return ((void *)(sd->cl + sd->moff)); 1762 } 1763 1764 static void 1765 rxb_free(struct mbuf *m) 1766 { 1767 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1768 1769 uma_zfree(clm->zone, clm->cl); 1770 counter_u64_add(extfree_rels, 1); 1771 } 1772 1773 /* 1774 * The mbuf returned comes from zone_muf and carries the payload in one of these 1775 * ways 1776 * a) complete frame inside the mbuf 1777 * b) m_cljset (for clusters without metadata) 1778 * d) m_extaddref (cluster with metadata) 1779 */ 1780 static struct mbuf * 1781 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1782 int remaining) 1783 { 1784 struct mbuf *m; 1785 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1786 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1787 struct cluster_metadata *clm; 1788 int len, blen; 1789 caddr_t payload; 1790 1791 if (fl->flags & FL_BUF_PACKING) { 1792 u_int l, pad; 1793 1794 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1795 len = min(remaining, blen); 1796 payload = sd->cl + fl->rx_offset; 1797 1798 l = fr_offset + len; 1799 pad = roundup2(l, fl->buf_boundary) - l; 1800 if (fl->rx_offset + len + pad < rxb->size2) 1801 blen = len + pad; 1802 MPASS(fl->rx_offset + blen <= rxb->size2); 1803 } else { 1804 MPASS(fl->rx_offset == 0); /* not packing */ 1805 blen = rxb->size1; 1806 len = min(remaining, blen); 1807 payload = sd->cl; 1808 } 1809 1810 if (fr_offset == 0) { 1811 m = m_gethdr(M_NOWAIT, MT_DATA); 1812 if (__predict_false(m == NULL)) 1813 return (NULL); 1814 m->m_pkthdr.len = remaining; 1815 } else { 1816 m = m_get(M_NOWAIT, MT_DATA); 1817 if (__predict_false(m == NULL)) 1818 return (NULL); 1819 } 1820 m->m_len = len; 1821 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1822 1823 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1824 /* copy data to mbuf */ 1825 bcopy(payload, mtod(m, caddr_t), len); 1826 if (fl->flags & FL_BUF_PACKING) { 1827 fl->rx_offset += blen; 1828 MPASS(fl->rx_offset <= rxb->size2); 1829 if (fl->rx_offset < rxb->size2) 1830 return (m); /* without advancing the cidx */ 1831 } 1832 } else if (fl->flags & FL_BUF_PACKING) { 1833 clm = cl_metadata(sd); 1834 if (sd->nmbuf++ == 0) { 1835 clm->refcount = 1; 1836 clm->zone = rxb->zone; 1837 clm->cl = sd->cl; 1838 counter_u64_add(extfree_refs, 1); 1839 } 1840 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1841 NULL); 1842 1843 fl->rx_offset += blen; 1844 MPASS(fl->rx_offset <= rxb->size2); 1845 if (fl->rx_offset < rxb->size2) 1846 return (m); /* without advancing the cidx */ 1847 } else { 1848 m_cljset(m, sd->cl, rxb->type); 1849 sd->cl = NULL; /* consumed, not a recycle candidate */ 1850 } 1851 1852 move_to_next_rxbuf(fl); 1853 1854 return (m); 1855 } 1856 1857 static struct mbuf * 1858 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1859 { 1860 struct mbuf *m0, *m, **pnext; 1861 u_int remaining; 1862 1863 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1864 M_ASSERTPKTHDR(fl->m0); 1865 MPASS(fl->m0->m_pkthdr.len == plen); 1866 MPASS(fl->remaining < plen); 1867 1868 m0 = fl->m0; 1869 pnext = fl->pnext; 1870 remaining = fl->remaining; 1871 fl->flags &= ~FL_BUF_RESUME; 1872 goto get_segment; 1873 } 1874 1875 /* 1876 * Payload starts at rx_offset in the current hw buffer. Its length is 1877 * 'len' and it may span multiple hw buffers. 1878 */ 1879 1880 m0 = get_scatter_segment(sc, fl, 0, plen); 1881 if (m0 == NULL) 1882 return (NULL); 1883 remaining = plen - m0->m_len; 1884 pnext = &m0->m_next; 1885 while (remaining > 0) { 1886 get_segment: 1887 MPASS(fl->rx_offset == 0); 1888 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1889 if (__predict_false(m == NULL)) { 1890 fl->m0 = m0; 1891 fl->pnext = pnext; 1892 fl->remaining = remaining; 1893 fl->flags |= FL_BUF_RESUME; 1894 return (NULL); 1895 } 1896 *pnext = m; 1897 pnext = &m->m_next; 1898 remaining -= m->m_len; 1899 } 1900 *pnext = NULL; 1901 1902 M_ASSERTPKTHDR(m0); 1903 return (m0); 1904 } 1905 1906 static int 1907 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1908 int remaining) 1909 { 1910 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1911 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1912 int len, blen; 1913 1914 if (fl->flags & FL_BUF_PACKING) { 1915 u_int l, pad; 1916 1917 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1918 len = min(remaining, blen); 1919 1920 l = fr_offset + len; 1921 pad = roundup2(l, fl->buf_boundary) - l; 1922 if (fl->rx_offset + len + pad < rxb->size2) 1923 blen = len + pad; 1924 fl->rx_offset += blen; 1925 MPASS(fl->rx_offset <= rxb->size2); 1926 if (fl->rx_offset < rxb->size2) 1927 return (len); /* without advancing the cidx */ 1928 } else { 1929 MPASS(fl->rx_offset == 0); /* not packing */ 1930 blen = rxb->size1; 1931 len = min(remaining, blen); 1932 } 1933 move_to_next_rxbuf(fl); 1934 return (len); 1935 } 1936 1937 static inline void 1938 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1939 { 1940 int remaining, fr_offset, len; 1941 1942 fr_offset = 0; 1943 remaining = plen; 1944 while (remaining > 0) { 1945 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1946 fr_offset += len; 1947 remaining -= len; 1948 } 1949 } 1950 1951 static inline int 1952 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1953 { 1954 int len; 1955 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1956 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1957 1958 if (fl->flags & FL_BUF_PACKING) 1959 len = rxb->size2 - fl->rx_offset; 1960 else 1961 len = rxb->size1; 1962 1963 return (min(plen, len)); 1964 } 1965 1966 static int 1967 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1968 u_int plen) 1969 { 1970 struct mbuf *m0; 1971 if_t ifp = rxq->ifp; 1972 struct sge_fl *fl = &rxq->fl; 1973 struct vi_info *vi = if_getsoftc(ifp); 1974 const struct cpl_rx_pkt *cpl; 1975 #if defined(INET) || defined(INET6) 1976 struct lro_ctrl *lro = &rxq->lro; 1977 #endif 1978 uint16_t err_vec, tnl_type, tnlhdr_len; 1979 static const int sw_hashtype[4][2] = { 1980 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1981 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1982 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1983 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1984 }; 1985 static const int sw_csum_flags[2][2] = { 1986 { 1987 /* IP, inner IP */ 1988 CSUM_ENCAP_VXLAN | 1989 CSUM_L3_CALC | CSUM_L3_VALID | 1990 CSUM_L4_CALC | CSUM_L4_VALID | 1991 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1992 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1993 1994 /* IP, inner IP6 */ 1995 CSUM_ENCAP_VXLAN | 1996 CSUM_L3_CALC | CSUM_L3_VALID | 1997 CSUM_L4_CALC | CSUM_L4_VALID | 1998 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1999 }, 2000 { 2001 /* IP6, inner IP */ 2002 CSUM_ENCAP_VXLAN | 2003 CSUM_L4_CALC | CSUM_L4_VALID | 2004 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 2005 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2006 2007 /* IP6, inner IP6 */ 2008 CSUM_ENCAP_VXLAN | 2009 CSUM_L4_CALC | CSUM_L4_VALID | 2010 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2011 }, 2012 }; 2013 2014 MPASS(plen > sc->params.sge.fl_pktshift); 2015 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 2016 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 2017 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 2018 caddr_t frame; 2019 int rc, slen; 2020 2021 slen = get_segment_len(sc, fl, plen) - 2022 sc->params.sge.fl_pktshift; 2023 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 2024 CURVNET_SET_QUIET(if_getvnet(ifp)); 2025 rc = pfil_mem_in(vi->pfil, frame, slen, ifp, &m0); 2026 CURVNET_RESTORE(); 2027 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 2028 skip_fl_payload(sc, fl, plen); 2029 return (0); 2030 } 2031 if (rc == PFIL_REALLOCED) { 2032 skip_fl_payload(sc, fl, plen); 2033 goto have_mbuf; 2034 } 2035 } 2036 2037 m0 = get_fl_payload(sc, fl, plen); 2038 if (__predict_false(m0 == NULL)) 2039 return (ENOMEM); 2040 2041 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2042 m0->m_len -= sc->params.sge.fl_pktshift; 2043 m0->m_data += sc->params.sge.fl_pktshift; 2044 2045 have_mbuf: 2046 m0->m_pkthdr.rcvif = ifp; 2047 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2048 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2049 2050 cpl = (const void *)(&d->rss + 1); 2051 if (sc->params.tp.rx_pkt_encap) { 2052 const uint16_t ev = be16toh(cpl->err_vec); 2053 2054 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2055 tnl_type = G_T6_RX_TNL_TYPE(ev); 2056 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2057 } else { 2058 err_vec = be16toh(cpl->err_vec); 2059 tnl_type = 0; 2060 tnlhdr_len = 0; 2061 } 2062 if (cpl->csum_calc && err_vec == 0) { 2063 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2064 2065 /* checksum(s) calculated and found to be correct. */ 2066 2067 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2068 (cpl->l2info & htobe32(F_RXF_IP6))); 2069 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2070 if (tnl_type == 0) { 2071 if (!ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM) { 2072 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2073 CSUM_L3_VALID | CSUM_L4_CALC | 2074 CSUM_L4_VALID; 2075 } else if (ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM_IPV6) { 2076 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2077 CSUM_L4_VALID; 2078 } 2079 rxq->rxcsum++; 2080 } else { 2081 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2082 2083 M_HASHTYPE_SETINNER(m0); 2084 if (__predict_false(cpl->ip_frag)) { 2085 /* 2086 * csum_data is for the inner frame (which is an 2087 * IP fragment) and is not 0xffff. There is no 2088 * way to pass the inner csum_data to the stack. 2089 * We don't want the stack to use the inner 2090 * csum_data to validate the outer frame or it 2091 * will get rejected. So we fix csum_data here 2092 * and let sw do the checksum of inner IP 2093 * fragments. 2094 * 2095 * XXX: Need 32b for csum_data2 in an rx mbuf. 2096 * Maybe stuff it into rcv_tstmp? 2097 */ 2098 m0->m_pkthdr.csum_data = 0xffff; 2099 if (ipv6) { 2100 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2101 CSUM_L4_VALID; 2102 } else { 2103 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2104 CSUM_L3_VALID | CSUM_L4_CALC | 2105 CSUM_L4_VALID; 2106 } 2107 } else { 2108 int outer_ipv6; 2109 2110 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2111 2112 outer_ipv6 = tnlhdr_len >= 2113 sizeof(struct ether_header) + 2114 sizeof(struct ip6_hdr); 2115 m0->m_pkthdr.csum_flags = 2116 sw_csum_flags[outer_ipv6][ipv6]; 2117 } 2118 rxq->vxlan_rxcsum++; 2119 } 2120 } 2121 2122 if (cpl->vlan_ex) { 2123 if (sc->flags & IS_VF && sc->vlan_id) { 2124 /* 2125 * HW is not setup correctly if extracted vlan_id does 2126 * not match the VF's setting. 2127 */ 2128 MPASS(be16toh(cpl->vlan) == sc->vlan_id); 2129 } else { 2130 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2131 m0->m_flags |= M_VLANTAG; 2132 rxq->vlan_extraction++; 2133 } 2134 } 2135 2136 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2137 /* 2138 * Fill up rcv_tstmp but do not set M_TSTMP as 2139 * long as we get a non-zero back from t4_tstmp_to_ns(). 2140 */ 2141 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc, 2142 be64toh(d->rsp.u.last_flit)); 2143 if (m0->m_pkthdr.rcv_tstmp != 0) 2144 m0->m_flags |= M_TSTMP; 2145 } 2146 2147 #ifdef NUMA 2148 m0->m_pkthdr.numa_domain = if_getnumadomain(ifp); 2149 #endif 2150 #if defined(INET) || defined(INET6) 2151 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2152 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2153 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2154 if (sort_before_lro(lro)) { 2155 tcp_lro_queue_mbuf(lro, m0); 2156 return (0); /* queued for sort, then LRO */ 2157 } 2158 if (tcp_lro_rx(lro, m0, 0) == 0) 2159 return (0); /* queued for LRO */ 2160 } 2161 #endif 2162 if_input(ifp, m0); 2163 2164 return (0); 2165 } 2166 2167 /* 2168 * Must drain the wrq or make sure that someone else will. 2169 */ 2170 static void 2171 wrq_tx_drain(void *arg, int n) 2172 { 2173 struct sge_wrq *wrq = arg; 2174 struct sge_eq *eq = &wrq->eq; 2175 2176 EQ_LOCK(eq); 2177 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2178 drain_wrq_wr_list(wrq->adapter, wrq); 2179 EQ_UNLOCK(eq); 2180 } 2181 2182 static void 2183 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2184 { 2185 struct sge_eq *eq = &wrq->eq; 2186 u_int available, dbdiff; /* # of hardware descriptors */ 2187 u_int n; 2188 struct wrqe *wr; 2189 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2190 2191 EQ_LOCK_ASSERT_OWNED(eq); 2192 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2193 wr = STAILQ_FIRST(&wrq->wr_list); 2194 MPASS(wr != NULL); /* Must be called with something useful to do */ 2195 MPASS(eq->pidx == eq->dbidx); 2196 dbdiff = 0; 2197 2198 do { 2199 eq->cidx = read_hw_cidx(eq); 2200 if (eq->pidx == eq->cidx) 2201 available = eq->sidx - 1; 2202 else 2203 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2204 2205 MPASS(wr->wrq == wrq); 2206 n = howmany(wr->wr_len, EQ_ESIZE); 2207 if (available < n) 2208 break; 2209 2210 dst = (void *)&eq->desc[eq->pidx]; 2211 if (__predict_true(eq->sidx - eq->pidx > n)) { 2212 /* Won't wrap, won't end exactly at the status page. */ 2213 bcopy(&wr->wr[0], dst, wr->wr_len); 2214 eq->pidx += n; 2215 } else { 2216 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2217 2218 bcopy(&wr->wr[0], dst, first_portion); 2219 if (wr->wr_len > first_portion) { 2220 bcopy(&wr->wr[first_portion], &eq->desc[0], 2221 wr->wr_len - first_portion); 2222 } 2223 eq->pidx = n - (eq->sidx - eq->pidx); 2224 } 2225 wrq->tx_wrs_copied++; 2226 2227 if (available < eq->sidx / 4 && 2228 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2229 /* 2230 * XXX: This is not 100% reliable with some 2231 * types of WRs. But this is a very unusual 2232 * situation for an ofld/ctrl queue anyway. 2233 */ 2234 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2235 F_FW_WR_EQUEQ); 2236 } 2237 2238 dbdiff += n; 2239 if (dbdiff >= 16) { 2240 ring_eq_db(sc, eq, dbdiff); 2241 dbdiff = 0; 2242 } 2243 2244 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2245 free_wrqe(wr); 2246 MPASS(wrq->nwr_pending > 0); 2247 wrq->nwr_pending--; 2248 MPASS(wrq->ndesc_needed >= n); 2249 wrq->ndesc_needed -= n; 2250 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2251 2252 if (dbdiff) 2253 ring_eq_db(sc, eq, dbdiff); 2254 } 2255 2256 /* 2257 * Doesn't fail. Holds on to work requests it can't send right away. 2258 */ 2259 void 2260 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2261 { 2262 #ifdef INVARIANTS 2263 struct sge_eq *eq = &wrq->eq; 2264 #endif 2265 2266 EQ_LOCK_ASSERT_OWNED(eq); 2267 MPASS(wr != NULL); 2268 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2269 MPASS((wr->wr_len & 0x7) == 0); 2270 2271 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2272 wrq->nwr_pending++; 2273 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2274 2275 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2276 return; /* commit_wrq_wr will drain wr_list as well. */ 2277 2278 drain_wrq_wr_list(sc, wrq); 2279 2280 /* Doorbell must have caught up to the pidx. */ 2281 MPASS(eq->pidx == eq->dbidx); 2282 } 2283 2284 void 2285 t4_update_fl_bufsize(if_t ifp) 2286 { 2287 struct vi_info *vi = if_getsoftc(ifp); 2288 struct adapter *sc = vi->adapter; 2289 struct sge_rxq *rxq; 2290 #ifdef TCP_OFFLOAD 2291 struct sge_ofld_rxq *ofld_rxq; 2292 #endif 2293 struct sge_fl *fl; 2294 int i, maxp; 2295 2296 maxp = max_rx_payload(sc, ifp, false); 2297 for_each_rxq(vi, i, rxq) { 2298 fl = &rxq->fl; 2299 2300 FL_LOCK(fl); 2301 fl->zidx = find_refill_source(sc, maxp, 2302 fl->flags & FL_BUF_PACKING); 2303 FL_UNLOCK(fl); 2304 } 2305 #ifdef TCP_OFFLOAD 2306 maxp = max_rx_payload(sc, ifp, true); 2307 for_each_ofld_rxq(vi, i, ofld_rxq) { 2308 fl = &ofld_rxq->fl; 2309 2310 FL_LOCK(fl); 2311 fl->zidx = find_refill_source(sc, maxp, 2312 fl->flags & FL_BUF_PACKING); 2313 FL_UNLOCK(fl); 2314 } 2315 #endif 2316 } 2317 2318 #ifdef RATELIMIT 2319 static inline int 2320 mbuf_eo_nsegs(struct mbuf *m) 2321 { 2322 2323 M_ASSERTPKTHDR(m); 2324 return (m->m_pkthdr.PH_loc.eight[1]); 2325 } 2326 2327 #if defined(INET) || defined(INET6) 2328 static inline void 2329 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2330 { 2331 2332 M_ASSERTPKTHDR(m); 2333 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2334 } 2335 #endif 2336 2337 static inline int 2338 mbuf_eo_len16(struct mbuf *m) 2339 { 2340 int n; 2341 2342 M_ASSERTPKTHDR(m); 2343 n = m->m_pkthdr.PH_loc.eight[2]; 2344 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2345 2346 return (n); 2347 } 2348 2349 #if defined(INET) || defined(INET6) 2350 static inline void 2351 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2352 { 2353 2354 M_ASSERTPKTHDR(m); 2355 m->m_pkthdr.PH_loc.eight[2] = len16; 2356 } 2357 #endif 2358 2359 static inline int 2360 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2361 { 2362 2363 M_ASSERTPKTHDR(m); 2364 return (m->m_pkthdr.PH_loc.eight[3]); 2365 } 2366 2367 #if defined(INET) || defined(INET6) 2368 static inline void 2369 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2370 { 2371 2372 M_ASSERTPKTHDR(m); 2373 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2374 } 2375 #endif 2376 2377 static inline int 2378 needs_eo(struct m_snd_tag *mst) 2379 { 2380 2381 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2382 } 2383 #endif 2384 2385 /* 2386 * Try to allocate an mbuf to contain a raw work request. To make it 2387 * easy to construct the work request, don't allocate a chain but a 2388 * single mbuf. 2389 */ 2390 struct mbuf * 2391 alloc_wr_mbuf(int len, int how) 2392 { 2393 struct mbuf *m; 2394 2395 if (len <= MHLEN) 2396 m = m_gethdr(how, MT_DATA); 2397 else if (len <= MCLBYTES) 2398 m = m_getcl(how, MT_DATA, M_PKTHDR); 2399 else 2400 m = NULL; 2401 if (m == NULL) 2402 return (NULL); 2403 m->m_pkthdr.len = len; 2404 m->m_len = len; 2405 set_mbuf_cflags(m, MC_RAW_WR); 2406 set_mbuf_len16(m, howmany(len, 16)); 2407 return (m); 2408 } 2409 2410 static inline bool 2411 needs_hwcsum(struct mbuf *m) 2412 { 2413 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2414 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2415 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2416 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2417 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2418 2419 M_ASSERTPKTHDR(m); 2420 2421 return (m->m_pkthdr.csum_flags & csum_flags); 2422 } 2423 2424 static inline bool 2425 needs_tso(struct mbuf *m) 2426 { 2427 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2428 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2429 2430 M_ASSERTPKTHDR(m); 2431 2432 return (m->m_pkthdr.csum_flags & csum_flags); 2433 } 2434 2435 static inline bool 2436 needs_vxlan_csum(struct mbuf *m) 2437 { 2438 2439 M_ASSERTPKTHDR(m); 2440 2441 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2442 } 2443 2444 static inline bool 2445 needs_vxlan_tso(struct mbuf *m) 2446 { 2447 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2448 CSUM_INNER_IP6_TSO; 2449 2450 M_ASSERTPKTHDR(m); 2451 2452 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2453 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2454 } 2455 2456 #if defined(INET) || defined(INET6) 2457 static inline bool 2458 needs_inner_tcp_csum(struct mbuf *m) 2459 { 2460 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2461 2462 M_ASSERTPKTHDR(m); 2463 2464 return (m->m_pkthdr.csum_flags & csum_flags); 2465 } 2466 #endif 2467 2468 static inline bool 2469 needs_l3_csum(struct mbuf *m) 2470 { 2471 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2472 CSUM_INNER_IP_TSO; 2473 2474 M_ASSERTPKTHDR(m); 2475 2476 return (m->m_pkthdr.csum_flags & csum_flags); 2477 } 2478 2479 static inline bool 2480 needs_outer_tcp_csum(struct mbuf *m) 2481 { 2482 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2483 CSUM_IP6_TSO; 2484 2485 M_ASSERTPKTHDR(m); 2486 2487 return (m->m_pkthdr.csum_flags & csum_flags); 2488 } 2489 2490 #ifdef RATELIMIT 2491 static inline bool 2492 needs_outer_l4_csum(struct mbuf *m) 2493 { 2494 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2495 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2496 2497 M_ASSERTPKTHDR(m); 2498 2499 return (m->m_pkthdr.csum_flags & csum_flags); 2500 } 2501 2502 static inline bool 2503 needs_outer_udp_csum(struct mbuf *m) 2504 { 2505 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2506 2507 M_ASSERTPKTHDR(m); 2508 2509 return (m->m_pkthdr.csum_flags & csum_flags); 2510 } 2511 #endif 2512 2513 static inline bool 2514 needs_vlan_insertion(struct mbuf *m) 2515 { 2516 2517 M_ASSERTPKTHDR(m); 2518 2519 return (m->m_flags & M_VLANTAG); 2520 } 2521 2522 #if defined(INET) || defined(INET6) 2523 static void * 2524 m_advance(struct mbuf **pm, int *poffset, int len) 2525 { 2526 struct mbuf *m = *pm; 2527 int offset = *poffset; 2528 uintptr_t p = 0; 2529 2530 MPASS(len > 0); 2531 2532 for (;;) { 2533 if (offset + len < m->m_len) { 2534 offset += len; 2535 p = mtod(m, uintptr_t) + offset; 2536 break; 2537 } 2538 len -= m->m_len - offset; 2539 m = m->m_next; 2540 offset = 0; 2541 MPASS(m != NULL); 2542 } 2543 *poffset = offset; 2544 *pm = m; 2545 return ((void *)p); 2546 } 2547 #endif 2548 2549 static inline int 2550 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2551 { 2552 vm_paddr_t paddr; 2553 int i, len, off, pglen, pgoff, seglen, segoff; 2554 int nsegs = 0; 2555 2556 M_ASSERTEXTPG(m); 2557 off = mtod(m, vm_offset_t); 2558 len = m->m_len; 2559 off += skip; 2560 len -= skip; 2561 2562 if (m->m_epg_hdrlen != 0) { 2563 if (off >= m->m_epg_hdrlen) { 2564 off -= m->m_epg_hdrlen; 2565 } else { 2566 seglen = m->m_epg_hdrlen - off; 2567 segoff = off; 2568 seglen = min(seglen, len); 2569 off = 0; 2570 len -= seglen; 2571 paddr = pmap_kextract( 2572 (vm_offset_t)&m->m_epg_hdr[segoff]); 2573 if (*nextaddr != paddr) 2574 nsegs++; 2575 *nextaddr = paddr + seglen; 2576 } 2577 } 2578 pgoff = m->m_epg_1st_off; 2579 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2580 pglen = m_epg_pagelen(m, i, pgoff); 2581 if (off >= pglen) { 2582 off -= pglen; 2583 pgoff = 0; 2584 continue; 2585 } 2586 seglen = pglen - off; 2587 segoff = pgoff + off; 2588 off = 0; 2589 seglen = min(seglen, len); 2590 len -= seglen; 2591 paddr = m->m_epg_pa[i] + segoff; 2592 if (*nextaddr != paddr) 2593 nsegs++; 2594 *nextaddr = paddr + seglen; 2595 pgoff = 0; 2596 }; 2597 if (len != 0) { 2598 seglen = min(len, m->m_epg_trllen - off); 2599 len -= seglen; 2600 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2601 if (*nextaddr != paddr) 2602 nsegs++; 2603 *nextaddr = paddr + seglen; 2604 } 2605 2606 return (nsegs); 2607 } 2608 2609 2610 /* 2611 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2612 * must have at least one mbuf that's not empty. It is possible for this 2613 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2614 */ 2615 static inline int 2616 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2617 { 2618 vm_paddr_t nextaddr, paddr; 2619 vm_offset_t va; 2620 int len, nsegs; 2621 2622 M_ASSERTPKTHDR(m); 2623 MPASS(m->m_pkthdr.len > 0); 2624 MPASS(m->m_pkthdr.len >= skip); 2625 2626 nsegs = 0; 2627 nextaddr = 0; 2628 for (; m; m = m->m_next) { 2629 len = m->m_len; 2630 if (__predict_false(len == 0)) 2631 continue; 2632 if (skip >= len) { 2633 skip -= len; 2634 continue; 2635 } 2636 if ((m->m_flags & M_EXTPG) != 0) { 2637 *cflags |= MC_NOMAP; 2638 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2639 skip = 0; 2640 continue; 2641 } 2642 va = mtod(m, vm_offset_t) + skip; 2643 len -= skip; 2644 skip = 0; 2645 paddr = pmap_kextract(va); 2646 nsegs += sglist_count((void *)(uintptr_t)va, len); 2647 if (paddr == nextaddr) 2648 nsegs--; 2649 nextaddr = pmap_kextract(va + len - 1) + 1; 2650 } 2651 2652 return (nsegs); 2653 } 2654 2655 /* 2656 * The maximum number of segments that can fit in a WR. 2657 */ 2658 static int 2659 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2660 { 2661 2662 if (vm_wr) { 2663 if (needs_tso(m)) 2664 return (TX_SGL_SEGS_VM_TSO); 2665 return (TX_SGL_SEGS_VM); 2666 } 2667 2668 if (needs_tso(m)) { 2669 if (needs_vxlan_tso(m)) 2670 return (TX_SGL_SEGS_VXLAN_TSO); 2671 else 2672 return (TX_SGL_SEGS_TSO); 2673 } 2674 2675 return (TX_SGL_SEGS); 2676 } 2677 2678 static struct timeval txerr_ratecheck = {0}; 2679 static const struct timeval txerr_interval = {3, 0}; 2680 2681 /* 2682 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2683 * a) caller can assume it's been freed if this function returns with an error. 2684 * b) it may get defragged up if the gather list is too long for the hardware. 2685 */ 2686 int 2687 parse_pkt(struct mbuf **mp, bool vm_wr) 2688 { 2689 struct mbuf *m0 = *mp, *m; 2690 int rc, nsegs, defragged = 0; 2691 struct ether_header *eh; 2692 #ifdef INET 2693 void *l3hdr; 2694 #endif 2695 #if defined(INET) || defined(INET6) 2696 int offset; 2697 struct tcphdr *tcp; 2698 #endif 2699 #if defined(KERN_TLS) || defined(RATELIMIT) 2700 struct m_snd_tag *mst; 2701 #endif 2702 uint16_t eh_type; 2703 uint8_t cflags; 2704 2705 cflags = 0; 2706 M_ASSERTPKTHDR(m0); 2707 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2708 rc = EINVAL; 2709 fail: 2710 m_freem(m0); 2711 *mp = NULL; 2712 return (rc); 2713 } 2714 restart: 2715 /* 2716 * First count the number of gather list segments in the payload. 2717 * Defrag the mbuf if nsegs exceeds the hardware limit. 2718 */ 2719 M_ASSERTPKTHDR(m0); 2720 MPASS(m0->m_pkthdr.len > 0); 2721 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2722 #if defined(KERN_TLS) || defined(RATELIMIT) 2723 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2724 mst = m0->m_pkthdr.snd_tag; 2725 else 2726 mst = NULL; 2727 #endif 2728 #ifdef KERN_TLS 2729 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2730 struct vi_info *vi = if_getsoftc(mst->ifp); 2731 2732 cflags |= MC_TLS; 2733 set_mbuf_cflags(m0, cflags); 2734 if (is_t6(vi->pi->adapter)) 2735 rc = t6_ktls_parse_pkt(m0); 2736 else 2737 rc = t7_ktls_parse_pkt(m0); 2738 if (rc != 0) 2739 goto fail; 2740 return (EINPROGRESS); 2741 } 2742 #endif 2743 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2744 if (defragged++ > 0) { 2745 rc = EFBIG; 2746 goto fail; 2747 } 2748 counter_u64_add(defrags, 1); 2749 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2750 rc = ENOMEM; 2751 goto fail; 2752 } 2753 *mp = m0 = m; /* update caller's copy after defrag */ 2754 goto restart; 2755 } 2756 2757 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2758 !(cflags & MC_NOMAP))) { 2759 counter_u64_add(pullups, 1); 2760 m0 = m_pullup(m0, m0->m_pkthdr.len); 2761 if (m0 == NULL) { 2762 /* Should have left well enough alone. */ 2763 rc = EFBIG; 2764 goto fail; 2765 } 2766 *mp = m0; /* update caller's copy after pullup */ 2767 goto restart; 2768 } 2769 set_mbuf_nsegs(m0, nsegs); 2770 set_mbuf_cflags(m0, cflags); 2771 calculate_mbuf_len16(m0, vm_wr); 2772 2773 #ifdef RATELIMIT 2774 /* 2775 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2776 * checksumming is enabled. needs_outer_l4_csum happens to check for 2777 * all the right things. 2778 */ 2779 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2780 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2781 m0->m_pkthdr.snd_tag = NULL; 2782 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2783 mst = NULL; 2784 } 2785 #endif 2786 2787 if (!needs_hwcsum(m0) 2788 #ifdef RATELIMIT 2789 && !needs_eo(mst) 2790 #endif 2791 ) 2792 return (0); 2793 2794 m = m0; 2795 eh = mtod(m, struct ether_header *); 2796 eh_type = ntohs(eh->ether_type); 2797 if (eh_type == ETHERTYPE_VLAN) { 2798 struct ether_vlan_header *evh = (void *)eh; 2799 2800 eh_type = ntohs(evh->evl_proto); 2801 m0->m_pkthdr.l2hlen = sizeof(*evh); 2802 } else 2803 m0->m_pkthdr.l2hlen = sizeof(*eh); 2804 2805 #if defined(INET) || defined(INET6) 2806 offset = 0; 2807 #ifdef INET 2808 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2809 #else 2810 m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2811 #endif 2812 #endif 2813 2814 switch (eh_type) { 2815 #ifdef INET6 2816 case ETHERTYPE_IPV6: 2817 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2818 break; 2819 #endif 2820 #ifdef INET 2821 case ETHERTYPE_IP: 2822 { 2823 struct ip *ip = l3hdr; 2824 2825 if (needs_vxlan_csum(m0)) { 2826 /* Driver will do the outer IP hdr checksum. */ 2827 ip->ip_sum = 0; 2828 if (needs_vxlan_tso(m0)) { 2829 const uint16_t ipl = ip->ip_len; 2830 2831 ip->ip_len = 0; 2832 ip->ip_sum = ~in_cksum_hdr(ip); 2833 ip->ip_len = ipl; 2834 } else 2835 ip->ip_sum = in_cksum_hdr(ip); 2836 } 2837 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2838 break; 2839 } 2840 #endif 2841 default: 2842 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2843 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2844 "if_cxgbe must be compiled with the same " 2845 "INET/INET6 options as the kernel.\n", __func__, 2846 eh_type); 2847 } 2848 rc = EINVAL; 2849 goto fail; 2850 } 2851 2852 #if defined(INET) || defined(INET6) 2853 if (needs_vxlan_csum(m0)) { 2854 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2855 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2856 2857 /* Inner headers. */ 2858 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2859 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2860 eh_type = ntohs(eh->ether_type); 2861 if (eh_type == ETHERTYPE_VLAN) { 2862 struct ether_vlan_header *evh = (void *)eh; 2863 2864 eh_type = ntohs(evh->evl_proto); 2865 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2866 } else 2867 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2868 #ifdef INET 2869 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2870 #else 2871 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2872 #endif 2873 2874 switch (eh_type) { 2875 #ifdef INET6 2876 case ETHERTYPE_IPV6: 2877 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2878 break; 2879 #endif 2880 #ifdef INET 2881 case ETHERTYPE_IP: 2882 { 2883 struct ip *ip = l3hdr; 2884 2885 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2886 break; 2887 } 2888 #endif 2889 default: 2890 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2891 log(LOG_ERR, "%s: VXLAN hw offload requested" 2892 "with unknown ethertype 0x%04x. if_cxgbe " 2893 "must be compiled with the same INET/INET6 " 2894 "options as the kernel.\n", __func__, 2895 eh_type); 2896 } 2897 rc = EINVAL; 2898 goto fail; 2899 } 2900 if (needs_inner_tcp_csum(m0)) { 2901 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2902 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2903 } 2904 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2905 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2906 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2907 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2908 CSUM_ENCAP_VXLAN; 2909 } 2910 2911 if (needs_outer_tcp_csum(m0)) { 2912 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2913 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2914 #ifdef RATELIMIT 2915 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2916 set_mbuf_eo_tsclk_tsoff(m0, 2917 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2918 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2919 } else 2920 set_mbuf_eo_tsclk_tsoff(m0, 0); 2921 } else if (needs_outer_udp_csum(m0)) { 2922 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2923 #endif 2924 } 2925 #ifdef RATELIMIT 2926 if (needs_eo(mst)) { 2927 u_int immhdrs; 2928 2929 /* EO WRs have the headers in the WR and not the GL. */ 2930 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2931 m0->m_pkthdr.l4hlen; 2932 cflags = 0; 2933 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2934 MPASS(cflags == mbuf_cflags(m0)); 2935 set_mbuf_eo_nsegs(m0, nsegs); 2936 set_mbuf_eo_len16(m0, 2937 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2938 rc = ethofld_transmit(mst->ifp, m0); 2939 if (rc != 0) 2940 goto fail; 2941 return (EINPROGRESS); 2942 } 2943 #endif 2944 #endif 2945 MPASS(m0 == *mp); 2946 return (0); 2947 } 2948 2949 void * 2950 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2951 { 2952 struct sge_eq *eq = &wrq->eq; 2953 struct adapter *sc = wrq->adapter; 2954 int ndesc, available; 2955 struct wrqe *wr; 2956 void *w; 2957 2958 MPASS(len16 > 0); 2959 ndesc = tx_len16_to_desc(len16); 2960 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2961 2962 EQ_LOCK(eq); 2963 if (__predict_false((eq->flags & EQ_HW_ALLOCATED) == 0)) { 2964 EQ_UNLOCK(eq); 2965 return (NULL); 2966 } 2967 2968 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2969 drain_wrq_wr_list(sc, wrq); 2970 2971 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2972 slowpath: 2973 EQ_UNLOCK(eq); 2974 wr = alloc_wrqe(len16 * 16, wrq); 2975 if (__predict_false(wr == NULL)) 2976 return (NULL); 2977 cookie->pidx = -1; 2978 cookie->ndesc = ndesc; 2979 return (&wr->wr); 2980 } 2981 2982 eq->cidx = read_hw_cidx(eq); 2983 if (eq->pidx == eq->cidx) 2984 available = eq->sidx - 1; 2985 else 2986 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2987 if (available < ndesc) 2988 goto slowpath; 2989 2990 cookie->pidx = eq->pidx; 2991 cookie->ndesc = ndesc; 2992 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2993 2994 w = &eq->desc[eq->pidx]; 2995 IDXINCR(eq->pidx, ndesc, eq->sidx); 2996 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2997 w = &wrq->ss[0]; 2998 wrq->ss_pidx = cookie->pidx; 2999 wrq->ss_len = len16 * 16; 3000 } 3001 3002 EQ_UNLOCK(eq); 3003 3004 return (w); 3005 } 3006 3007 void 3008 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 3009 { 3010 struct sge_eq *eq = &wrq->eq; 3011 struct adapter *sc = wrq->adapter; 3012 int ndesc, pidx; 3013 struct wrq_cookie *prev, *next; 3014 3015 if (cookie->pidx == -1) { 3016 struct wrqe *wr = __containerof(w, struct wrqe, wr); 3017 3018 t4_wrq_tx(sc, wr); 3019 return; 3020 } 3021 3022 if (__predict_false(w == &wrq->ss[0])) { 3023 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3024 3025 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3026 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3027 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3028 wrq->tx_wrs_ss++; 3029 } else 3030 wrq->tx_wrs_direct++; 3031 3032 EQ_LOCK(eq); 3033 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3034 pidx = cookie->pidx; 3035 MPASS(pidx >= 0 && pidx < eq->sidx); 3036 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3037 next = TAILQ_NEXT(cookie, link); 3038 if (prev == NULL) { 3039 MPASS(pidx == eq->dbidx); 3040 if (next == NULL || ndesc >= 16) { 3041 int available; 3042 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3043 3044 /* 3045 * Note that the WR via which we'll request tx updates 3046 * is at pidx and not eq->pidx, which has moved on 3047 * already. 3048 */ 3049 dst = (void *)&eq->desc[pidx]; 3050 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3051 if (available < eq->sidx / 4 && 3052 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3053 /* 3054 * XXX: This is not 100% reliable with some 3055 * types of WRs. But this is a very unusual 3056 * situation for an ofld/ctrl queue anyway. 3057 */ 3058 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3059 F_FW_WR_EQUEQ); 3060 } 3061 3062 if (__predict_true(eq->flags & EQ_HW_ALLOCATED)) 3063 ring_eq_db(wrq->adapter, eq, ndesc); 3064 else 3065 IDXINCR(eq->dbidx, ndesc, eq->sidx); 3066 } else { 3067 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3068 next->pidx = pidx; 3069 next->ndesc += ndesc; 3070 } 3071 } else { 3072 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3073 prev->ndesc += ndesc; 3074 } 3075 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3076 3077 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3078 drain_wrq_wr_list(sc, wrq); 3079 3080 #ifdef INVARIANTS 3081 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3082 /* Doorbell must have caught up to the pidx. */ 3083 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3084 } 3085 #endif 3086 EQ_UNLOCK(eq); 3087 } 3088 3089 static u_int 3090 can_resume_eth_tx(struct mp_ring *r) 3091 { 3092 struct sge_eq *eq = r->cookie; 3093 3094 return (total_available_tx_desc(eq) > eq->sidx / 8); 3095 } 3096 3097 static inline bool 3098 cannot_use_txpkts(struct mbuf *m) 3099 { 3100 /* maybe put a GL limit too, to avoid silliness? */ 3101 3102 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3103 } 3104 3105 static inline int 3106 discard_tx(struct sge_eq *eq) 3107 { 3108 3109 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3110 } 3111 3112 static inline int 3113 wr_can_update_eq(void *p) 3114 { 3115 struct fw_eth_tx_pkts_wr *wr = p; 3116 3117 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3118 case FW_ULPTX_WR: 3119 case FW_ETH_TX_PKT_WR: 3120 case FW_ETH_TX_PKTS_WR: 3121 case FW_ETH_TX_PKTS2_WR: 3122 case FW_ETH_TX_PKT_VM_WR: 3123 case FW_ETH_TX_PKTS_VM_WR: 3124 return (1); 3125 default: 3126 return (0); 3127 } 3128 } 3129 3130 static inline void 3131 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3132 struct fw_eth_tx_pkt_wr *wr) 3133 { 3134 struct sge_eq *eq = &txq->eq; 3135 struct txpkts *txp = &txq->txp; 3136 3137 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3138 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3139 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3140 eq->equeqidx = eq->pidx; 3141 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3142 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3143 eq->equeqidx = eq->pidx; 3144 } 3145 } 3146 3147 #if defined(__i386__) || defined(__amd64__) 3148 extern uint64_t tsc_freq; 3149 #endif 3150 3151 static inline bool 3152 record_eth_tx_time(struct sge_txq *txq) 3153 { 3154 const uint64_t cycles = get_cyclecount(); 3155 const uint64_t last_tx = txq->last_tx; 3156 #if defined(__i386__) || defined(__amd64__) 3157 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3158 #else 3159 const uint64_t itg = 0; 3160 #endif 3161 3162 MPASS(cycles >= last_tx); 3163 txq->last_tx = cycles; 3164 return (cycles - last_tx < itg); 3165 } 3166 3167 /* 3168 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3169 * be consumed. Return the actual number consumed. 0 indicates a stall. 3170 */ 3171 static u_int 3172 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3173 { 3174 struct sge_txq *txq = r->cookie; 3175 if_t ifp = txq->ifp; 3176 struct sge_eq *eq = &txq->eq; 3177 struct txpkts *txp = &txq->txp; 3178 struct vi_info *vi = if_getsoftc(ifp); 3179 struct adapter *sc = vi->adapter; 3180 u_int total, remaining; /* # of packets */ 3181 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3182 int i, rc; 3183 struct mbuf *m0; 3184 bool snd, recent_tx; 3185 void *wr; /* start of the last WR written to the ring */ 3186 3187 TXQ_LOCK_ASSERT_OWNED(txq); 3188 recent_tx = record_eth_tx_time(txq); 3189 3190 remaining = IDXDIFF(pidx, cidx, r->size); 3191 if (__predict_false(discard_tx(eq))) { 3192 for (i = 0; i < txp->npkt; i++) 3193 m_freem(txp->mb[i]); 3194 txp->npkt = 0; 3195 while (cidx != pidx) { 3196 m0 = r->items[cidx]; 3197 m_freem(m0); 3198 if (++cidx == r->size) 3199 cidx = 0; 3200 } 3201 reclaim_tx_descs(txq, eq->sidx); 3202 *coalescing = false; 3203 return (remaining); /* emptied */ 3204 } 3205 3206 /* How many hardware descriptors do we have readily available. */ 3207 if (eq->pidx == eq->cidx) 3208 avail = eq->sidx - 1; 3209 else 3210 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3211 3212 total = 0; 3213 if (remaining == 0) { 3214 txp->score = 0; 3215 txq->txpkts_flush++; 3216 goto send_txpkts; 3217 } 3218 3219 dbdiff = 0; 3220 MPASS(remaining > 0); 3221 while (remaining > 0) { 3222 m0 = r->items[cidx]; 3223 M_ASSERTPKTHDR(m0); 3224 MPASS(m0->m_nextpkt == NULL); 3225 3226 if (avail < 2 * SGE_MAX_WR_NDESC) 3227 avail += reclaim_tx_descs(txq, 64); 3228 3229 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3230 goto skip_coalescing; 3231 if (cannot_use_txpkts(m0)) 3232 txp->score = 0; 3233 else if (recent_tx) { 3234 if (++txp->score == 0) 3235 txp->score = UINT8_MAX; 3236 } else 3237 txp->score = 1; 3238 if (txp->npkt > 0 || remaining > 1 || 3239 txp->score >= t4_tx_coalesce_pkts || 3240 atomic_load_int(&txq->eq.equiq) != 0) { 3241 if (vi->flags & TX_USES_VM_WR) 3242 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3243 else 3244 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3245 } else { 3246 snd = false; 3247 rc = EINVAL; 3248 } 3249 if (snd) { 3250 MPASS(txp->npkt > 0); 3251 for (i = 0; i < txp->npkt; i++) 3252 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3253 if (txp->npkt > 1) { 3254 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3255 if (vi->flags & TX_USES_VM_WR) 3256 n = write_txpkts_vm_wr(sc, txq); 3257 else 3258 n = write_txpkts_wr(sc, txq); 3259 } else { 3260 MPASS(avail >= 3261 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3262 if (vi->flags & TX_USES_VM_WR) 3263 n = write_txpkt_vm_wr(sc, txq, 3264 txp->mb[0]); 3265 else 3266 n = write_txpkt_wr(sc, txq, txp->mb[0], 3267 avail); 3268 } 3269 MPASS(n <= SGE_MAX_WR_NDESC); 3270 avail -= n; 3271 dbdiff += n; 3272 wr = &eq->desc[eq->pidx]; 3273 IDXINCR(eq->pidx, n, eq->sidx); 3274 txp->npkt = 0; /* emptied */ 3275 } 3276 if (rc == 0) { 3277 /* m0 was coalesced into txq->txpkts. */ 3278 goto next_mbuf; 3279 } 3280 if (rc == EAGAIN) { 3281 /* 3282 * m0 is suitable for tx coalescing but could not be 3283 * combined with the existing txq->txpkts, which has now 3284 * been transmitted. Start a new txpkts with m0. 3285 */ 3286 MPASS(snd); 3287 MPASS(txp->npkt == 0); 3288 continue; 3289 } 3290 3291 MPASS(rc != 0 && rc != EAGAIN); 3292 MPASS(txp->npkt == 0); 3293 skip_coalescing: 3294 n = tx_len16_to_desc(mbuf_len16(m0)); 3295 if (__predict_false(avail < n)) { 3296 avail += reclaim_tx_descs(txq, min(n, 32)); 3297 if (avail < n) 3298 break; /* out of descriptors */ 3299 } 3300 3301 wr = &eq->desc[eq->pidx]; 3302 if (mbuf_cflags(m0) & MC_RAW_WR) { 3303 n = write_raw_wr(txq, wr, m0, avail); 3304 #ifdef KERN_TLS 3305 } else if (mbuf_cflags(m0) & MC_TLS) { 3306 ETHER_BPF_MTAP(ifp, m0); 3307 if (is_t6(sc)) 3308 n = t6_ktls_write_wr(txq, wr, m0, avail); 3309 else 3310 n = t7_ktls_write_wr(txq, wr, m0, avail); 3311 #endif 3312 } else { 3313 ETHER_BPF_MTAP(ifp, m0); 3314 if (vi->flags & TX_USES_VM_WR) 3315 n = write_txpkt_vm_wr(sc, txq, m0); 3316 else 3317 n = write_txpkt_wr(sc, txq, m0, avail); 3318 } 3319 MPASS(n >= 1 && n <= avail); 3320 if (!(mbuf_cflags(m0) & MC_TLS)) 3321 MPASS(n <= SGE_MAX_WR_NDESC); 3322 3323 avail -= n; 3324 dbdiff += n; 3325 IDXINCR(eq->pidx, n, eq->sidx); 3326 3327 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3328 if (wr_can_update_eq(wr)) 3329 set_txupdate_flags(txq, avail, wr); 3330 ring_eq_db(sc, eq, dbdiff); 3331 avail += reclaim_tx_descs(txq, 32); 3332 dbdiff = 0; 3333 } 3334 next_mbuf: 3335 total++; 3336 remaining--; 3337 if (__predict_false(++cidx == r->size)) 3338 cidx = 0; 3339 } 3340 if (dbdiff != 0) { 3341 if (wr_can_update_eq(wr)) 3342 set_txupdate_flags(txq, avail, wr); 3343 ring_eq_db(sc, eq, dbdiff); 3344 reclaim_tx_descs(txq, 32); 3345 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3346 atomic_load_int(&txq->eq.equiq) == 0) { 3347 /* 3348 * If nothing was submitted to the chip for tx (it was coalesced 3349 * into txpkts instead) and there is no tx update outstanding 3350 * then we need to send txpkts now. 3351 */ 3352 send_txpkts: 3353 MPASS(txp->npkt > 0); 3354 for (i = 0; i < txp->npkt; i++) 3355 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3356 if (txp->npkt > 1) { 3357 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3358 if (vi->flags & TX_USES_VM_WR) 3359 n = write_txpkts_vm_wr(sc, txq); 3360 else 3361 n = write_txpkts_wr(sc, txq); 3362 } else { 3363 MPASS(avail >= 3364 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3365 if (vi->flags & TX_USES_VM_WR) 3366 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3367 else 3368 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3369 } 3370 MPASS(n <= SGE_MAX_WR_NDESC); 3371 wr = &eq->desc[eq->pidx]; 3372 IDXINCR(eq->pidx, n, eq->sidx); 3373 txp->npkt = 0; /* emptied */ 3374 3375 MPASS(wr_can_update_eq(wr)); 3376 set_txupdate_flags(txq, avail - n, wr); 3377 ring_eq_db(sc, eq, n); 3378 reclaim_tx_descs(txq, 32); 3379 } 3380 *coalescing = txp->npkt > 0; 3381 3382 return (total); 3383 } 3384 3385 static inline void 3386 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3387 int qsize, int intr_idx, int cong, int qtype) 3388 { 3389 3390 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3391 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3392 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3393 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3394 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3395 ("%s: bad intr_idx %d", __func__, intr_idx)); 3396 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC || 3397 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype)); 3398 3399 iq->flags = 0; 3400 iq->state = IQS_DISABLED; 3401 iq->adapter = sc; 3402 iq->qtype = qtype; 3403 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3404 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3405 if (pktc_idx >= 0) { 3406 iq->intr_params |= F_QINTR_CNT_EN; 3407 iq->intr_pktc_idx = pktc_idx; 3408 } 3409 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3410 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3411 iq->intr_idx = intr_idx; 3412 iq->cong_drop = cong; 3413 } 3414 3415 static inline void 3416 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3417 { 3418 struct sge_params *sp = &sc->params.sge; 3419 3420 fl->qsize = qsize; 3421 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3422 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3423 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3424 if (sc->flags & BUF_PACKING_OK && 3425 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3426 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3427 fl->flags |= FL_BUF_PACKING; 3428 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3429 fl->safe_zidx = sc->sge.safe_zidx; 3430 if (fl->flags & FL_BUF_PACKING) { 3431 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3432 fl->buf_boundary = sp->pack_boundary; 3433 } else { 3434 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3435 fl->buf_boundary = 16; 3436 } 3437 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3438 fl->buf_boundary = sp->pad_boundary; 3439 } 3440 3441 static inline void 3442 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3443 uint8_t port_id, struct sge_iq *iq, char *name) 3444 { 3445 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3446 ("%s: bad qtype %d", __func__, eqtype)); 3447 3448 eq->type = eqtype; 3449 eq->port_id = port_id; 3450 eq->tx_chan = sc->port[port_id]->tx_chan; 3451 eq->hw_port = sc->port[port_id]->hw_port; 3452 eq->iq = iq; 3453 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3454 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3455 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3456 } 3457 3458 int 3459 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3460 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3461 { 3462 int rc; 3463 3464 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3465 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3466 if (rc != 0) { 3467 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3468 goto done; 3469 } 3470 3471 rc = bus_dmamem_alloc(*tag, va, 3472 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3473 if (rc != 0) { 3474 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3475 goto done; 3476 } 3477 3478 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3479 if (rc != 0) { 3480 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3481 goto done; 3482 } 3483 done: 3484 if (rc) 3485 free_ring(sc, *tag, *map, *pa, *va); 3486 3487 return (rc); 3488 } 3489 3490 int 3491 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3492 bus_addr_t pa, void *va) 3493 { 3494 if (pa) 3495 bus_dmamap_unload(tag, map); 3496 if (va) 3497 bus_dmamem_free(tag, va, map); 3498 if (tag) 3499 bus_dma_tag_destroy(tag); 3500 3501 return (0); 3502 } 3503 3504 /* 3505 * Allocates the software resources (mainly memory and sysctl nodes) for an 3506 * ingress queue and an optional freelist. 3507 * 3508 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3509 */ 3510 static int 3511 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3512 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3513 { 3514 int rc; 3515 size_t len; 3516 struct adapter *sc = vi->adapter; 3517 3518 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3519 3520 len = iq->qsize * IQ_ESIZE; 3521 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3522 (void **)&iq->desc); 3523 if (rc != 0) 3524 return (rc); 3525 3526 if (fl) { 3527 len = fl->qsize * EQ_ESIZE; 3528 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3529 &fl->ba, (void **)&fl->desc); 3530 if (rc) { 3531 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3532 iq->desc); 3533 return (rc); 3534 } 3535 3536 /* Allocate space for one software descriptor per buffer. */ 3537 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3538 M_CXGBE, M_ZERO | M_WAITOK); 3539 3540 add_fl_sysctls(sc, ctx, oid, fl); 3541 iq->flags |= IQ_HAS_FL; 3542 } 3543 add_iq_sysctls(ctx, oid, iq); 3544 iq->flags |= IQ_SW_ALLOCATED; 3545 3546 return (0); 3547 } 3548 3549 /* 3550 * Frees all software resources (memory and locks) associated with an ingress 3551 * queue and an optional freelist. 3552 */ 3553 static void 3554 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3555 { 3556 MPASS(iq->flags & IQ_SW_ALLOCATED); 3557 3558 if (fl) { 3559 MPASS(iq->flags & IQ_HAS_FL); 3560 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3561 free_fl_buffers(sc, fl); 3562 free(fl->sdesc, M_CXGBE); 3563 mtx_destroy(&fl->fl_lock); 3564 bzero(fl, sizeof(*fl)); 3565 } 3566 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3567 bzero(iq, sizeof(*iq)); 3568 } 3569 3570 /* 3571 * Allocates a hardware ingress queue and an optional freelist that will be 3572 * associated with it. 3573 * 3574 * Returns errno on failure. Resources allocated up to that point may still be 3575 * allocated. Caller is responsible for cleanup in case this function fails. 3576 */ 3577 static int 3578 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3579 { 3580 int rc, cntxt_id, cong_map; 3581 struct fw_iq_cmd c; 3582 struct adapter *sc = vi->adapter; 3583 struct port_info *pi = vi->pi; 3584 __be32 v = 0; 3585 3586 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3587 3588 bzero(&c, sizeof(c)); 3589 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3590 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3591 V_FW_IQ_CMD_VFN(0)); 3592 3593 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3594 FW_LEN16(c)); 3595 3596 /* Special handling for firmware event queue */ 3597 if (iq == &sc->sge.fwq) 3598 v |= F_FW_IQ_CMD_IQASYNCH; 3599 3600 if (iq->intr_idx < 0) { 3601 /* Forwarded interrupts, all headed to fwq */ 3602 v |= F_FW_IQ_CMD_IQANDST; 3603 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3604 } else { 3605 KASSERT(iq->intr_idx < sc->intr_count, 3606 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3607 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3608 } 3609 3610 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3611 c.type_to_iqandstindex = htobe32(v | 3612 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3613 V_FW_IQ_CMD_VIID(vi->viid) | 3614 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3615 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->hw_port) | 3616 F_FW_IQ_CMD_IQGTSMODE | 3617 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3618 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3619 c.iqsize = htobe16(iq->qsize); 3620 c.iqaddr = htobe64(iq->ba); 3621 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); 3622 if (iq->cong_drop != -1) { 3623 if (iq->qtype == IQ_ETH) { 3624 if (chip_id(sc) >= CHELSIO_T7) 3625 cong_map = 1 << pi->hw_port; 3626 else 3627 cong_map = pi->rx_e_chan_map; 3628 } else 3629 cong_map = 0; 3630 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3631 } 3632 3633 if (fl) { 3634 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3635 c.iqns_to_fl0congen |= 3636 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3637 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3638 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3639 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3640 0)); 3641 if (iq->cong_drop != -1) { 3642 c.iqns_to_fl0congen |= 3643 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | 3644 F_FW_IQ_CMD_FL0CONGCIF | 3645 F_FW_IQ_CMD_FL0CONGEN); 3646 } 3647 c.fl0dcaen_to_fl0cidxfthresh = 3648 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3649 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3650 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3651 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3652 c.fl0size = htobe16(fl->qsize); 3653 c.fl0addr = htobe64(fl->ba); 3654 } 3655 3656 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3657 if (rc != 0) { 3658 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3659 return (rc); 3660 } 3661 3662 iq->cidx = 0; 3663 iq->gen = F_RSPD_GEN; 3664 iq->cntxt_id = be16toh(c.iqid); 3665 iq->abs_id = be16toh(c.physiqid); 3666 3667 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3668 if (cntxt_id >= sc->sge.iqmap_sz) { 3669 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3670 cntxt_id, sc->sge.iqmap_sz - 1); 3671 } 3672 sc->sge.iqmap[cntxt_id] = iq; 3673 3674 if (fl) { 3675 u_int qid; 3676 #ifdef INVARIANTS 3677 int i; 3678 3679 MPASS(!(fl->flags & FL_BUF_RESUME)); 3680 for (i = 0; i < fl->sidx * 8; i++) 3681 MPASS(fl->sdesc[i].cl == NULL); 3682 #endif 3683 fl->cntxt_id = be16toh(c.fl0id); 3684 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3685 fl->rx_offset = 0; 3686 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3687 3688 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3689 if (cntxt_id >= sc->sge.eqmap_sz) { 3690 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3691 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3692 } 3693 sc->sge.eqmap[cntxt_id] = (void *)fl; 3694 3695 qid = fl->cntxt_id; 3696 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3697 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3698 uint32_t mask = (1 << s_qpp) - 1; 3699 volatile uint8_t *udb; 3700 3701 udb = sc->udbs_base + UDBS_DB_OFFSET; 3702 udb += (qid >> s_qpp) << PAGE_SHIFT; 3703 qid &= mask; 3704 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3705 udb += qid << UDBS_SEG_SHIFT; 3706 qid = 0; 3707 } 3708 fl->udb = (volatile void *)udb; 3709 } 3710 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3711 3712 FL_LOCK(fl); 3713 /* Enough to make sure the SGE doesn't think it's starved */ 3714 refill_fl(sc, fl, fl->lowat); 3715 FL_UNLOCK(fl); 3716 } 3717 3718 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && 3719 iq->cong_drop != -1) { 3720 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop, 3721 cong_map); 3722 } 3723 3724 /* Enable IQ interrupts */ 3725 atomic_store_rel_int(&iq->state, IQS_IDLE); 3726 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3727 V_INGRESSQID(iq->cntxt_id)); 3728 3729 iq->flags |= IQ_HW_ALLOCATED; 3730 3731 return (0); 3732 } 3733 3734 static int 3735 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3736 { 3737 int rc; 3738 3739 MPASS(iq->flags & IQ_HW_ALLOCATED); 3740 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3741 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3742 if (rc != 0) { 3743 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3744 return (rc); 3745 } 3746 iq->flags &= ~IQ_HW_ALLOCATED; 3747 3748 return (0); 3749 } 3750 3751 static void 3752 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3753 struct sge_iq *iq) 3754 { 3755 struct sysctl_oid_list *children; 3756 3757 if (ctx == NULL || oid == NULL) 3758 return; 3759 3760 children = SYSCTL_CHILDREN(oid); 3761 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3762 "bus address of descriptor ring"); 3763 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3764 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3765 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3766 &iq->abs_id, 0, "absolute id of the queue"); 3767 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3768 &iq->cntxt_id, 0, "SGE context id of the queue"); 3769 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3770 0, "consumer index"); 3771 } 3772 3773 static void 3774 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3775 struct sysctl_oid *oid, struct sge_fl *fl) 3776 { 3777 struct sysctl_oid_list *children; 3778 3779 if (ctx == NULL || oid == NULL) 3780 return; 3781 3782 children = SYSCTL_CHILDREN(oid); 3783 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3784 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3785 children = SYSCTL_CHILDREN(oid); 3786 3787 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3788 &fl->ba, "bus address of descriptor ring"); 3789 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3790 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3791 "desc ring size in bytes"); 3792 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3793 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3794 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3795 fl_pad ? 1 : 0, "padding enabled"); 3796 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3797 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3798 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3799 0, "consumer index"); 3800 if (fl->flags & FL_BUF_PACKING) { 3801 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3802 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3803 } 3804 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3805 0, "producer index"); 3806 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3807 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3808 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3809 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3810 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3811 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3812 } 3813 3814 /* 3815 * Idempotent. 3816 */ 3817 static int 3818 alloc_fwq(struct adapter *sc) 3819 { 3820 int rc, intr_idx; 3821 struct sge_iq *fwq = &sc->sge.fwq; 3822 struct vi_info *vi = &sc->port[0]->vi[0]; 3823 3824 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3825 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3826 3827 if (sc->flags & IS_VF) 3828 intr_idx = 0; 3829 else 3830 intr_idx = sc->intr_count > 1 ? 1 : 0; 3831 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER); 3832 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3833 if (rc != 0) { 3834 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3835 return (rc); 3836 } 3837 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3838 } 3839 3840 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3841 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3842 3843 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3844 if (rc != 0) { 3845 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3846 return (rc); 3847 } 3848 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3849 } 3850 3851 return (0); 3852 } 3853 3854 /* 3855 * Idempotent. 3856 */ 3857 static void 3858 free_fwq(struct adapter *sc) 3859 { 3860 struct sge_iq *fwq = &sc->sge.fwq; 3861 3862 if (fwq->flags & IQ_HW_ALLOCATED) { 3863 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3864 free_iq_fl_hwq(sc, fwq, NULL); 3865 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3866 } 3867 3868 if (fwq->flags & IQ_SW_ALLOCATED) { 3869 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3870 free_iq_fl(sc, fwq, NULL); 3871 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3872 } 3873 } 3874 3875 /* 3876 * Idempotent. 3877 */ 3878 static int 3879 alloc_ctrlq(struct adapter *sc, int idx) 3880 { 3881 int rc; 3882 char name[16]; 3883 struct sysctl_oid *oid; 3884 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3885 3886 MPASS(idx < sc->sge.nctrlq); 3887 3888 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3889 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3890 3891 snprintf(name, sizeof(name), "%d", idx); 3892 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3893 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3894 "ctrl queue"); 3895 3896 snprintf(name, sizeof(name), "%s ctrlq%d", 3897 device_get_nameunit(sc->dev), idx); 3898 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3899 idx % sc->params.nports, &sc->sge.fwq, name); 3900 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3901 if (rc != 0) { 3902 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3903 sysctl_remove_oid(oid, 1, 1); 3904 return (rc); 3905 } 3906 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3907 } 3908 3909 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3910 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3911 MPASS(ctrlq->nwr_pending == 0); 3912 MPASS(ctrlq->ndesc_needed == 0); 3913 3914 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq, idx); 3915 if (rc != 0) { 3916 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3917 return (rc); 3918 } 3919 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3920 } 3921 3922 return (0); 3923 } 3924 3925 /* 3926 * Idempotent. 3927 */ 3928 static void 3929 free_ctrlq(struct adapter *sc, int idx) 3930 { 3931 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3932 3933 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3934 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3935 free_eq_hwq(sc, NULL, &ctrlq->eq); 3936 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3937 } 3938 3939 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3940 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3941 free_wrq(sc, ctrlq); 3942 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3943 } 3944 } 3945 3946 int 3947 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, 3948 int cong_map) 3949 { 3950 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log; 3951 uint32_t param, val; 3952 uint16_t ch_map; 3953 int cong_mode, rc, i; 3954 3955 if (chip_id(sc) < CHELSIO_T5) 3956 return (ENOTSUP); 3957 3958 /* Convert the driver knob to the mode understood by the firmware. */ 3959 switch (cong_drop) { 3960 case -1: 3961 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE; 3962 break; 3963 case 0: 3964 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL; 3965 break; 3966 case 1: 3967 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE; 3968 break; 3969 case 2: 3970 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH; 3971 break; 3972 default: 3973 MPASS(0); 3974 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n", 3975 cong_drop, cntxt_id); 3976 return (EINVAL); 3977 } 3978 3979 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3980 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3981 V_FW_PARAMS_PARAM_YZ(cntxt_id); 3982 if (chip_id(sc) >= CHELSIO_T7) { 3983 val = V_T7_DMAQ_CONM_CTXT_CNGTPMODE(cong_mode) | 3984 V_T7_DMAQ_CONM_CTXT_CH_VEC(cong_map); 3985 } else { 3986 val = V_CONMCTXT_CNGTPMODE(cong_mode); 3987 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || 3988 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { 3989 for (i = 0, ch_map = 0; i < 4; i++) { 3990 if (cong_map & (1 << i)) 3991 ch_map |= 1 << (i << cng_ch_bits_log); 3992 } 3993 val |= V_CONMCTXT_CNGCHMAP(ch_map); 3994 } 3995 } 3996 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3997 if (rc != 0) { 3998 CH_ERR(sc, "failed to set congestion manager context " 3999 "for ingress queue %d: %d\n", cntxt_id, rc); 4000 } 4001 4002 return (rc); 4003 } 4004 4005 /* 4006 * Idempotent. 4007 */ 4008 static int 4009 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 4010 int maxp) 4011 { 4012 int rc; 4013 struct adapter *sc = vi->adapter; 4014 if_t ifp = vi->ifp; 4015 struct sysctl_oid *oid; 4016 char name[16]; 4017 4018 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 4019 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4020 #if defined(INET) || defined(INET6) 4021 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 4022 if (rc != 0) 4023 return (rc); 4024 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 4025 #endif 4026 rxq->ifp = ifp; 4027 4028 snprintf(name, sizeof(name), "%d", idx); 4029 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 4030 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4031 "rx queue"); 4032 4033 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 4034 intr_idx, cong_drop, IQ_ETH); 4035 #if defined(INET) || defined(INET6) 4036 if (if_getcapenable(ifp) & IFCAP_LRO) 4037 rxq->iq.flags |= IQ_LRO_ENABLED; 4038 #endif 4039 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 4040 rxq->iq.flags |= IQ_RX_TIMESTAMP; 4041 snprintf(name, sizeof(name), "%s rxq%d-fl", 4042 device_get_nameunit(vi->dev), idx); 4043 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 4044 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 4045 if (rc != 0) { 4046 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 4047 sysctl_remove_oid(oid, 1, 1); 4048 #if defined(INET) || defined(INET6) 4049 tcp_lro_free(&rxq->lro); 4050 rxq->lro.ifp = NULL; 4051 #endif 4052 return (rc); 4053 } 4054 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4055 add_rxq_sysctls(&vi->ctx, oid, rxq); 4056 } 4057 4058 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 4059 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4060 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 4061 if (rc != 0) { 4062 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 4063 return (rc); 4064 } 4065 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 4066 4067 if (idx == 0) 4068 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 4069 else 4070 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 4071 ("iq_base mismatch")); 4072 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 4073 ("PF with non-zero iq_base")); 4074 4075 /* 4076 * The freelist is just barely above the starvation threshold 4077 * right now, fill it up a bit more. 4078 */ 4079 FL_LOCK(&rxq->fl); 4080 refill_fl(sc, &rxq->fl, 128); 4081 FL_UNLOCK(&rxq->fl); 4082 } 4083 4084 return (0); 4085 } 4086 4087 /* 4088 * Idempotent. 4089 */ 4090 static void 4091 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4092 { 4093 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4094 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4095 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4096 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4097 } 4098 4099 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4100 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4101 #if defined(INET) || defined(INET6) 4102 tcp_lro_free(&rxq->lro); 4103 #endif 4104 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4105 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4106 bzero(rxq, sizeof(*rxq)); 4107 } 4108 } 4109 4110 static void 4111 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4112 struct sge_rxq *rxq) 4113 { 4114 struct sysctl_oid_list *children; 4115 4116 if (ctx == NULL || oid == NULL) 4117 return; 4118 4119 children = SYSCTL_CHILDREN(oid); 4120 #if defined(INET) || defined(INET6) 4121 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4122 &rxq->lro.lro_queued, 0, NULL); 4123 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4124 &rxq->lro.lro_flushed, 0, NULL); 4125 #endif 4126 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4127 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4128 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4129 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4130 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4131 &rxq->vxlan_rxcsum, 4132 "# of times hardware assisted with inner checksum (VXLAN)"); 4133 } 4134 4135 #ifdef TCP_OFFLOAD 4136 /* 4137 * Idempotent. 4138 */ 4139 static int 4140 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4141 int intr_idx, int maxp) 4142 { 4143 int rc; 4144 struct adapter *sc = vi->adapter; 4145 struct sysctl_oid *oid; 4146 char name[16]; 4147 4148 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4149 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4150 4151 snprintf(name, sizeof(name), "%d", idx); 4152 oid = SYSCTL_ADD_NODE(&vi->ctx, 4153 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4154 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4155 4156 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4157 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD); 4158 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4159 device_get_nameunit(vi->dev), idx); 4160 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4161 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4162 oid); 4163 if (rc != 0) { 4164 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4165 rc); 4166 sysctl_remove_oid(oid, 1, 1); 4167 return (rc); 4168 } 4169 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4170 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4171 ofld_rxq->rx_iscsi_ddp_setup_error = 4172 counter_u64_alloc(M_WAITOK); 4173 ofld_rxq->ddp_buffer_alloc = counter_u64_alloc(M_WAITOK); 4174 ofld_rxq->ddp_buffer_reuse = counter_u64_alloc(M_WAITOK); 4175 ofld_rxq->ddp_buffer_free = counter_u64_alloc(M_WAITOK); 4176 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4177 } 4178 4179 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4180 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4181 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4182 if (rc != 0) { 4183 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4184 rc); 4185 return (rc); 4186 } 4187 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4188 } 4189 return (rc); 4190 } 4191 4192 /* 4193 * Idempotent. 4194 */ 4195 static void 4196 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4197 { 4198 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4199 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4200 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4201 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4202 } 4203 4204 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4205 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4206 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4207 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4208 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4209 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4210 counter_u64_free(ofld_rxq->ddp_buffer_alloc); 4211 counter_u64_free(ofld_rxq->ddp_buffer_reuse); 4212 counter_u64_free(ofld_rxq->ddp_buffer_free); 4213 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4214 } 4215 } 4216 4217 static void 4218 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4219 struct sge_ofld_rxq *ofld_rxq) 4220 { 4221 struct sysctl_oid_list *children; 4222 4223 if (ctx == NULL || oid == NULL) 4224 return; 4225 4226 children = SYSCTL_CHILDREN(oid); 4227 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_jobs", 4228 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_jobs, 0, 4229 "# of aio_read(2) jobs completed via DDP"); 4230 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_octets", 4231 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_octets, 0, 4232 "# of octets placed directly for aio_read(2) jobs"); 4233 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4234 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4235 "# of TOE TLS records received"); 4236 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4237 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4238 "# of payload octets in received TOE TLS records"); 4239 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4240 "rx_toe_ddp_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_ddp_octets, 4241 "# of payload octets received via TCP DDP"); 4242 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4243 "ddp_buffer_alloc", CTLFLAG_RD, &ofld_rxq->ddp_buffer_alloc, 4244 "# of DDP RCV buffers allocated"); 4245 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4246 "ddp_buffer_reuse", CTLFLAG_RD, &ofld_rxq->ddp_buffer_reuse, 4247 "# of DDP RCV buffers reused"); 4248 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4249 "ddp_buffer_free", CTLFLAG_RD, &ofld_rxq->ddp_buffer_free, 4250 "# of DDP RCV buffers freed"); 4251 4252 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4253 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4254 children = SYSCTL_CHILDREN(oid); 4255 4256 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4257 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4258 "# of times DDP buffer was setup successfully."); 4259 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4260 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4261 "# of times DDP buffer setup failed."); 4262 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4263 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4264 "# of octets placed directly"); 4265 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4266 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4267 "# of PDUs with data placed directly."); 4268 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4269 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4270 "# of data octets delivered in freelist"); 4271 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4272 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4273 "# of PDUs with data delivered in freelist"); 4274 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4275 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4276 "# of PDUs with invalid padding"); 4277 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4278 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4279 "# of PDUs with invalid header digests"); 4280 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4281 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4282 "# of PDUs with invalid data digests"); 4283 } 4284 #endif 4285 4286 /* 4287 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4288 */ 4289 static u_int 4290 qsize_to_fthresh(int qsize) 4291 { 4292 u_int fthresh; 4293 4294 fthresh = qsize == 0 ? 0 : order_base_2(qsize); 4295 if (fthresh > X_CIDXFLUSHTHRESH_128) 4296 fthresh = X_CIDXFLUSHTHRESH_128; 4297 4298 return (fthresh); 4299 } 4300 4301 static int 4302 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq, int idx) 4303 { 4304 int rc, cntxt_id, core; 4305 struct fw_eq_ctrl_cmd c; 4306 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4307 4308 core = sc->params.tid_qid_sel_mask != 0 ? idx % sc->params.ncores : 0; 4309 bzero(&c, sizeof(c)); 4310 4311 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4312 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4313 V_FW_EQ_CTRL_CMD_VFN(0)); 4314 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4315 V_FW_EQ_CTRL_CMD_COREGROUP(core) | 4316 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4317 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4318 c.physeqid_pkd = htobe32(0); 4319 c.fetchszm_to_iqid = 4320 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4321 V_FW_EQ_CTRL_CMD_PCIECHN(eq->hw_port) | 4322 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4323 c.dcaen_to_eqsize = 4324 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4325 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4326 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4327 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4328 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4329 c.eqaddr = htobe64(eq->ba); 4330 4331 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4332 if (rc != 0) { 4333 CH_ERR(sc, "failed to create hw ctrlq for port %d: %d\n", 4334 eq->port_id, rc); 4335 return (rc); 4336 } 4337 4338 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4339 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4340 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4341 if (cntxt_id >= sc->sge.eqmap_sz) 4342 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4343 cntxt_id, sc->sge.eqmap_sz - 1); 4344 sc->sge.eqmap[cntxt_id] = eq; 4345 4346 return (rc); 4347 } 4348 4349 static int 4350 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, int idx) 4351 { 4352 int rc, cntxt_id, core; 4353 struct fw_eq_eth_cmd c; 4354 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4355 4356 core = sc->params.ncores > 1 ? idx % sc->params.ncores : 0; 4357 bzero(&c, sizeof(c)); 4358 4359 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4360 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4361 V_FW_EQ_ETH_CMD_VFN(0)); 4362 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4363 V_FW_EQ_ETH_CMD_COREGROUP(core) | 4364 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4365 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4366 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4367 c.fetchszm_to_iqid = 4368 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4369 V_FW_EQ_ETH_CMD_PCIECHN(eq->hw_port) | F_FW_EQ_ETH_CMD_FETCHRO | 4370 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4371 c.dcaen_to_eqsize = 4372 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4373 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4374 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4375 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4376 c.eqaddr = htobe64(eq->ba); 4377 4378 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4379 if (rc != 0) { 4380 device_printf(vi->dev, 4381 "failed to create Ethernet egress queue: %d\n", rc); 4382 return (rc); 4383 } 4384 4385 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4386 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4387 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4388 if (cntxt_id >= sc->sge.eqmap_sz) 4389 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4390 cntxt_id, sc->sge.eqmap_sz - 1); 4391 sc->sge.eqmap[cntxt_id] = eq; 4392 4393 return (rc); 4394 } 4395 4396 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4397 /* 4398 * ncores number of uP cores. 4399 * nq number of queues for this VI 4400 * idx queue index 4401 */ 4402 static inline int 4403 qidx_to_core(int ncores, int nq, int idx) 4404 { 4405 MPASS(nq % ncores == 0); 4406 MPASS(idx >= 0 && idx < nq); 4407 4408 return (idx * ncores / nq); 4409 } 4410 4411 static int 4412 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, 4413 int idx) 4414 { 4415 int rc, cntxt_id, core; 4416 struct fw_eq_ofld_cmd c; 4417 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4418 4419 if (sc->params.tid_qid_sel_mask != 0) 4420 core = qidx_to_core(sc->params.ncores, vi->nofldtxq, idx); 4421 else 4422 core = 0; 4423 4424 bzero(&c, sizeof(c)); 4425 4426 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4427 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4428 V_FW_EQ_OFLD_CMD_VFN(0)); 4429 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4430 V_FW_EQ_OFLD_CMD_COREGROUP(core) | 4431 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4432 c.fetchszm_to_iqid = 4433 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4434 V_FW_EQ_OFLD_CMD_PCIECHN(eq->hw_port) | 4435 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4436 c.dcaen_to_eqsize = 4437 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4438 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4439 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4440 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4441 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4442 c.eqaddr = htobe64(eq->ba); 4443 4444 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4445 if (rc != 0) { 4446 device_printf(vi->dev, 4447 "failed to create egress queue for TCP offload: %d\n", rc); 4448 return (rc); 4449 } 4450 4451 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4452 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4453 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4454 if (cntxt_id >= sc->sge.eqmap_sz) 4455 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4456 cntxt_id, sc->sge.eqmap_sz - 1); 4457 sc->sge.eqmap[cntxt_id] = eq; 4458 4459 return (rc); 4460 } 4461 #endif 4462 4463 /* SW only */ 4464 static int 4465 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4466 struct sysctl_oid *oid) 4467 { 4468 int rc, qsize; 4469 size_t len; 4470 4471 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4472 4473 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4474 len = qsize * EQ_ESIZE; 4475 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4476 (void **)&eq->desc); 4477 if (rc) 4478 return (rc); 4479 if (ctx != NULL && oid != NULL) 4480 add_eq_sysctls(sc, ctx, oid, eq); 4481 eq->flags |= EQ_SW_ALLOCATED; 4482 4483 return (0); 4484 } 4485 4486 /* SW only */ 4487 static void 4488 free_eq(struct adapter *sc, struct sge_eq *eq) 4489 { 4490 MPASS(eq->flags & EQ_SW_ALLOCATED); 4491 if (eq->type == EQ_ETH) 4492 MPASS(eq->pidx == eq->cidx); 4493 4494 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4495 mtx_destroy(&eq->eq_lock); 4496 bzero(eq, sizeof(*eq)); 4497 } 4498 4499 static void 4500 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4501 struct sysctl_oid *oid, struct sge_eq *eq) 4502 { 4503 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4504 4505 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4506 "bus address of descriptor ring"); 4507 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4508 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4509 "desc ring size in bytes"); 4510 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4511 &eq->abs_id, 0, "absolute id of the queue"); 4512 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4513 &eq->cntxt_id, 0, "SGE context id of the queue"); 4514 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4515 0, "consumer index"); 4516 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4517 0, "producer index"); 4518 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4519 eq->sidx, "status page index"); 4520 } 4521 4522 static int 4523 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, int idx) 4524 { 4525 int rc; 4526 4527 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4528 4529 eq->iqid = eq->iq->cntxt_id; 4530 eq->pidx = eq->cidx = eq->dbidx = 0; 4531 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4532 eq->equeqidx = 0; 4533 eq->doorbells = sc->doorbells; 4534 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4535 4536 switch (eq->type) { 4537 case EQ_CTRL: 4538 rc = ctrl_eq_alloc(sc, eq, idx); 4539 break; 4540 4541 case EQ_ETH: 4542 rc = eth_eq_alloc(sc, vi, eq, idx); 4543 break; 4544 4545 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4546 case EQ_OFLD: 4547 rc = ofld_eq_alloc(sc, vi, eq, idx); 4548 break; 4549 #endif 4550 4551 default: 4552 panic("%s: invalid eq type %d.", __func__, eq->type); 4553 } 4554 if (rc != 0) { 4555 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4556 eq->type, rc); 4557 return (rc); 4558 } 4559 4560 if (isset(&eq->doorbells, DOORBELL_UDB) || 4561 isset(&eq->doorbells, DOORBELL_UDBWC) || 4562 isset(&eq->doorbells, DOORBELL_WCWR)) { 4563 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4564 uint32_t mask = (1 << s_qpp) - 1; 4565 volatile uint8_t *udb; 4566 4567 udb = sc->udbs_base + UDBS_DB_OFFSET; 4568 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4569 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4570 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4571 clrbit(&eq->doorbells, DOORBELL_WCWR); 4572 else { 4573 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4574 eq->udb_qid = 0; 4575 } 4576 eq->udb = (volatile void *)udb; 4577 } 4578 4579 eq->flags |= EQ_HW_ALLOCATED; 4580 return (0); 4581 } 4582 4583 static int 4584 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4585 { 4586 int rc; 4587 4588 MPASS(eq->flags & EQ_HW_ALLOCATED); 4589 4590 switch (eq->type) { 4591 case EQ_CTRL: 4592 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4593 break; 4594 case EQ_ETH: 4595 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4596 break; 4597 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4598 case EQ_OFLD: 4599 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4600 break; 4601 #endif 4602 default: 4603 panic("%s: invalid eq type %d.", __func__, eq->type); 4604 } 4605 if (rc != 0) { 4606 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4607 return (rc); 4608 } 4609 eq->flags &= ~EQ_HW_ALLOCATED; 4610 4611 return (0); 4612 } 4613 4614 static int 4615 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4616 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4617 { 4618 struct sge_eq *eq = &wrq->eq; 4619 int rc; 4620 4621 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4622 4623 rc = alloc_eq(sc, eq, ctx, oid); 4624 if (rc) 4625 return (rc); 4626 MPASS(eq->flags & EQ_SW_ALLOCATED); 4627 /* Can't fail after this. */ 4628 4629 wrq->adapter = sc; 4630 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4631 TAILQ_INIT(&wrq->incomplete_wrs); 4632 STAILQ_INIT(&wrq->wr_list); 4633 wrq->nwr_pending = 0; 4634 wrq->ndesc_needed = 0; 4635 add_wrq_sysctls(ctx, oid, wrq); 4636 4637 return (0); 4638 } 4639 4640 static void 4641 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4642 { 4643 free_eq(sc, &wrq->eq); 4644 MPASS(wrq->nwr_pending == 0); 4645 MPASS(wrq->ndesc_needed == 0); 4646 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4647 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4648 bzero(wrq, sizeof(*wrq)); 4649 } 4650 4651 static void 4652 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4653 struct sge_wrq *wrq) 4654 { 4655 struct sysctl_oid_list *children; 4656 4657 if (ctx == NULL || oid == NULL) 4658 return; 4659 4660 children = SYSCTL_CHILDREN(oid); 4661 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4662 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4663 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4664 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4665 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4666 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4667 } 4668 4669 /* 4670 * Idempotent. 4671 */ 4672 static int 4673 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4674 { 4675 int rc, iqidx; 4676 struct port_info *pi = vi->pi; 4677 struct adapter *sc = vi->adapter; 4678 struct sge_eq *eq = &txq->eq; 4679 struct txpkts *txp; 4680 char name[16]; 4681 struct sysctl_oid *oid; 4682 4683 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4684 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4685 4686 snprintf(name, sizeof(name), "%d", idx); 4687 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4688 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4689 "tx queue"); 4690 4691 iqidx = vi->first_rxq + (idx % vi->nrxq); 4692 snprintf(name, sizeof(name), "%s txq%d", 4693 device_get_nameunit(vi->dev), idx); 4694 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->port_id, 4695 &sc->sge.rxq[iqidx].iq, name); 4696 4697 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4698 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4699 if (rc != 0) { 4700 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4701 idx, rc); 4702 failed: 4703 sysctl_remove_oid(oid, 1, 1); 4704 return (rc); 4705 } 4706 4707 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4708 if (rc) { 4709 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4710 mp_ring_free(txq->r); 4711 goto failed; 4712 } 4713 MPASS(eq->flags & EQ_SW_ALLOCATED); 4714 /* Can't fail after this point. */ 4715 4716 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4717 txq->ifp = vi->ifp; 4718 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4719 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4720 M_ZERO | M_WAITOK); 4721 4722 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4723 } 4724 4725 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4726 MPASS(eq->flags & EQ_SW_ALLOCATED); 4727 rc = alloc_eq_hwq(sc, vi, eq, idx); 4728 if (rc != 0) { 4729 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4730 return (rc); 4731 } 4732 MPASS(eq->flags & EQ_HW_ALLOCATED); 4733 /* Can't fail after this point. */ 4734 4735 if (idx == 0) 4736 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4737 else 4738 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4739 ("eq_base mismatch")); 4740 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4741 ("PF with non-zero eq_base")); 4742 4743 txp = &txq->txp; 4744 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4745 txq->txp.max_npkt = min(nitems(txp->mb), 4746 sc->params.max_pkts_per_eth_tx_pkts_wr); 4747 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4748 txq->txp.max_npkt--; 4749 4750 if (vi->flags & TX_USES_VM_WR) 4751 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4752 V_TXPKT_INTF(pi->hw_port)); 4753 else 4754 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4755 V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) | 4756 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4757 4758 txq->tc_idx = -1; 4759 } 4760 4761 return (0); 4762 } 4763 4764 /* 4765 * Idempotent. 4766 */ 4767 static void 4768 free_txq(struct vi_info *vi, struct sge_txq *txq) 4769 { 4770 struct adapter *sc = vi->adapter; 4771 struct sge_eq *eq = &txq->eq; 4772 4773 if (eq->flags & EQ_HW_ALLOCATED) { 4774 MPASS(eq->flags & EQ_SW_ALLOCATED); 4775 free_eq_hwq(sc, NULL, eq); 4776 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4777 } 4778 4779 if (eq->flags & EQ_SW_ALLOCATED) { 4780 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4781 sglist_free(txq->gl); 4782 free(txq->sdesc, M_CXGBE); 4783 mp_ring_free(txq->r); 4784 free_eq(sc, eq); 4785 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4786 bzero(txq, sizeof(*txq)); 4787 } 4788 } 4789 4790 static void 4791 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4792 struct sysctl_oid *oid, struct sge_txq *txq) 4793 { 4794 struct adapter *sc; 4795 struct sysctl_oid_list *children; 4796 4797 if (ctx == NULL || oid == NULL) 4798 return; 4799 4800 sc = vi->adapter; 4801 children = SYSCTL_CHILDREN(oid); 4802 4803 mp_ring_sysctls(txq->r, ctx, children); 4804 4805 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4806 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4807 sysctl_tc, "I", "traffic class (-1 means none)"); 4808 4809 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4810 &txq->txcsum, "# of times hardware assisted with checksum"); 4811 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4812 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4813 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4814 &txq->tso_wrs, "# of TSO work requests"); 4815 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4816 &txq->imm_wrs, "# of work requests with immediate data"); 4817 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4818 &txq->sgl_wrs, "# of work requests with direct SGL"); 4819 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4820 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4821 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4822 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4823 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4824 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4825 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4826 &txq->txpkts0_pkts, 4827 "# of frames tx'd using type0 txpkts work requests"); 4828 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4829 &txq->txpkts1_pkts, 4830 "# of frames tx'd using type1 txpkts work requests"); 4831 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4832 &txq->txpkts_flush, 4833 "# of times txpkts had to be flushed out by an egress-update"); 4834 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4835 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4836 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4837 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4838 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4839 &txq->vxlan_txcsum, 4840 "# of times hardware assisted with inner checksums (VXLAN)"); 4841 4842 #ifdef KERN_TLS 4843 if (is_ktls(sc)) { 4844 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4845 CTLFLAG_RD, &txq->kern_tls_records, 4846 "# of NIC TLS records transmitted"); 4847 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4848 CTLFLAG_RD, &txq->kern_tls_short, 4849 "# of short NIC TLS records transmitted"); 4850 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4851 CTLFLAG_RD, &txq->kern_tls_partial, 4852 "# of partial NIC TLS records transmitted"); 4853 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4854 CTLFLAG_RD, &txq->kern_tls_full, 4855 "# of full NIC TLS records transmitted"); 4856 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4857 CTLFLAG_RD, &txq->kern_tls_octets, 4858 "# of payload octets in transmitted NIC TLS records"); 4859 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4860 CTLFLAG_RD, &txq->kern_tls_waste, 4861 "# of octets DMAd but not transmitted in NIC TLS records"); 4862 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4863 CTLFLAG_RD, &txq->kern_tls_header, 4864 "# of NIC TLS header-only packets transmitted"); 4865 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4866 CTLFLAG_RD, &txq->kern_tls_fin_short, 4867 "# of NIC TLS padded FIN packets on short TLS records"); 4868 if (is_t6(sc)) { 4869 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4870 "kern_tls_options", CTLFLAG_RD, 4871 &txq->kern_tls_options, 4872 "# of NIC TLS options-only packets transmitted"); 4873 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4874 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin, 4875 "# of NIC TLS FIN-only packets transmitted"); 4876 } else { 4877 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4878 "kern_tls_ghash_received", CTLFLAG_RD, 4879 &txq->kern_tls_ghash_received, 4880 "# of NIC TLS GHASHes received"); 4881 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4882 "kern_tls_ghash_requested", CTLFLAG_RD, 4883 &txq->kern_tls_ghash_requested, 4884 "# of NIC TLS GHASHes requested"); 4885 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4886 "kern_tls_lso", CTLFLAG_RD, 4887 &txq->kern_tls_lso, 4888 "# of NIC TLS records transmitted using LSO"); 4889 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4890 "kern_tls_partial_ghash", CTLFLAG_RD, 4891 &txq->kern_tls_partial_ghash, 4892 "# of NIC TLS records encrypted using a partial GHASH"); 4893 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4894 "kern_tls_splitmode", CTLFLAG_RD, 4895 &txq->kern_tls_splitmode, 4896 "# of NIC TLS records using SplitMode"); 4897 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4898 "kern_tls_trailer", CTLFLAG_RD, 4899 &txq->kern_tls_trailer, 4900 "# of NIC TLS trailer-only packets transmitted"); 4901 } 4902 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4903 CTLFLAG_RD, &txq->kern_tls_cbc, 4904 "# of NIC TLS sessions using AES-CBC"); 4905 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4906 CTLFLAG_RD, &txq->kern_tls_gcm, 4907 "# of NIC TLS sessions using AES-GCM"); 4908 } 4909 #endif 4910 } 4911 4912 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4913 /* 4914 * Idempotent. 4915 */ 4916 static int 4917 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4918 { 4919 struct sysctl_oid *oid; 4920 struct port_info *pi = vi->pi; 4921 struct adapter *sc = vi->adapter; 4922 struct sge_eq *eq = &ofld_txq->wrq.eq; 4923 int rc, iqidx; 4924 char name[16]; 4925 4926 MPASS(idx >= 0); 4927 MPASS(idx < vi->nofldtxq); 4928 4929 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4930 snprintf(name, sizeof(name), "%d", idx); 4931 oid = SYSCTL_ADD_NODE(&vi->ctx, 4932 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4933 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4934 4935 snprintf(name, sizeof(name), "%s ofld_txq%d", 4936 device_get_nameunit(vi->dev), idx); 4937 if (vi->nofldrxq > 0) { 4938 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4939 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id, 4940 &sc->sge.ofld_rxq[iqidx].iq, name); 4941 } else { 4942 iqidx = vi->first_rxq + (idx % vi->nrxq); 4943 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id, 4944 &sc->sge.rxq[iqidx].iq, name); 4945 } 4946 4947 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4948 if (rc != 0) { 4949 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4950 rc); 4951 sysctl_remove_oid(oid, 1, 1); 4952 return (rc); 4953 } 4954 MPASS(eq->flags & EQ_SW_ALLOCATED); 4955 /* Can't fail after this point. */ 4956 4957 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4958 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4959 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 4960 ofld_txq->tx_aio_jobs = counter_u64_alloc(M_WAITOK); 4961 ofld_txq->tx_aio_octets = counter_u64_alloc(M_WAITOK); 4962 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4963 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4964 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4965 } 4966 4967 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4968 MPASS(eq->flags & EQ_SW_ALLOCATED); 4969 MPASS(ofld_txq->wrq.nwr_pending == 0); 4970 MPASS(ofld_txq->wrq.ndesc_needed == 0); 4971 rc = alloc_eq_hwq(sc, vi, eq, idx); 4972 if (rc != 0) { 4973 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4974 rc); 4975 return (rc); 4976 } 4977 MPASS(eq->flags & EQ_HW_ALLOCATED); 4978 } 4979 4980 return (0); 4981 } 4982 4983 /* 4984 * Idempotent. 4985 */ 4986 static void 4987 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4988 { 4989 struct adapter *sc = vi->adapter; 4990 struct sge_eq *eq = &ofld_txq->wrq.eq; 4991 4992 if (eq->flags & EQ_HW_ALLOCATED) { 4993 MPASS(eq->flags & EQ_SW_ALLOCATED); 4994 free_eq_hwq(sc, NULL, eq); 4995 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4996 } 4997 4998 if (eq->flags & EQ_SW_ALLOCATED) { 4999 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 5000 counter_u64_free(ofld_txq->tx_iscsi_pdus); 5001 counter_u64_free(ofld_txq->tx_iscsi_octets); 5002 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 5003 counter_u64_free(ofld_txq->tx_aio_jobs); 5004 counter_u64_free(ofld_txq->tx_aio_octets); 5005 counter_u64_free(ofld_txq->tx_toe_tls_records); 5006 counter_u64_free(ofld_txq->tx_toe_tls_octets); 5007 free_wrq(sc, &ofld_txq->wrq); 5008 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 5009 bzero(ofld_txq, sizeof(*ofld_txq)); 5010 } 5011 } 5012 5013 static void 5014 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 5015 struct sge_ofld_txq *ofld_txq) 5016 { 5017 struct sysctl_oid_list *children; 5018 5019 if (ctx == NULL || oid == NULL) 5020 return; 5021 5022 children = SYSCTL_CHILDREN(oid); 5023 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 5024 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 5025 "# of iSCSI PDUs transmitted"); 5026 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 5027 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 5028 "# of payload octets in transmitted iSCSI PDUs"); 5029 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 5030 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 5031 "# of iSCSI segmentation offload work requests"); 5032 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_jobs", 5033 CTLFLAG_RD, &ofld_txq->tx_aio_jobs, 5034 "# of zero-copy aio_write(2) jobs transmitted"); 5035 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_octets", 5036 CTLFLAG_RD, &ofld_txq->tx_aio_octets, 5037 "# of payload octets in transmitted zero-copy aio_write(2) jobs"); 5038 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 5039 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 5040 "# of TOE TLS records transmitted"); 5041 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 5042 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 5043 "# of payload octets in transmitted TOE TLS records"); 5044 } 5045 #endif 5046 5047 static void 5048 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5049 { 5050 bus_addr_t *ba = arg; 5051 5052 KASSERT(nseg == 1, 5053 ("%s meant for single segment mappings only.", __func__)); 5054 5055 *ba = error ? 0 : segs->ds_addr; 5056 } 5057 5058 static inline void 5059 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 5060 { 5061 uint32_t n, v; 5062 5063 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 5064 MPASS(n > 0); 5065 5066 wmb(); 5067 v = fl->dbval | V_PIDX(n); 5068 if (fl->udb) 5069 *fl->udb = htole32(v); 5070 else 5071 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 5072 IDXINCR(fl->dbidx, n, fl->sidx); 5073 } 5074 5075 /* 5076 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 5077 * recycled do not count towards this allocation budget. 5078 * 5079 * Returns non-zero to indicate that this freelist should be added to the list 5080 * of starving freelists. 5081 */ 5082 static int 5083 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 5084 { 5085 __be64 *d; 5086 struct fl_sdesc *sd; 5087 uintptr_t pa; 5088 caddr_t cl; 5089 struct rx_buf_info *rxb; 5090 struct cluster_metadata *clm; 5091 uint16_t max_pidx, zidx = fl->zidx; 5092 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 5093 5094 FL_LOCK_ASSERT_OWNED(fl); 5095 5096 /* 5097 * We always stop at the beginning of the hardware descriptor that's just 5098 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 5099 * which would mean an empty freelist to the chip. 5100 */ 5101 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 5102 if (fl->pidx == max_pidx * 8) 5103 return (0); 5104 5105 d = &fl->desc[fl->pidx]; 5106 sd = &fl->sdesc[fl->pidx]; 5107 rxb = &sc->sge.rx_buf_info[zidx]; 5108 5109 while (n > 0) { 5110 5111 if (sd->cl != NULL) { 5112 5113 if (sd->nmbuf == 0) { 5114 /* 5115 * Fast recycle without involving any atomics on 5116 * the cluster's metadata (if the cluster has 5117 * metadata). This happens when all frames 5118 * received in the cluster were small enough to 5119 * fit within a single mbuf each. 5120 */ 5121 fl->cl_fast_recycled++; 5122 goto recycled; 5123 } 5124 5125 /* 5126 * Cluster is guaranteed to have metadata. Clusters 5127 * without metadata always take the fast recycle path 5128 * when they're recycled. 5129 */ 5130 clm = cl_metadata(sd); 5131 MPASS(clm != NULL); 5132 5133 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5134 fl->cl_recycled++; 5135 counter_u64_add(extfree_rels, 1); 5136 goto recycled; 5137 } 5138 sd->cl = NULL; /* gave up my reference */ 5139 } 5140 MPASS(sd->cl == NULL); 5141 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5142 if (__predict_false(cl == NULL)) { 5143 if (zidx != fl->safe_zidx) { 5144 zidx = fl->safe_zidx; 5145 rxb = &sc->sge.rx_buf_info[zidx]; 5146 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5147 } 5148 if (cl == NULL) 5149 break; 5150 } 5151 fl->cl_allocated++; 5152 n--; 5153 5154 pa = pmap_kextract((vm_offset_t)cl); 5155 sd->cl = cl; 5156 sd->zidx = zidx; 5157 5158 if (fl->flags & FL_BUF_PACKING) { 5159 *d = htobe64(pa | rxb->hwidx2); 5160 sd->moff = rxb->size2; 5161 } else { 5162 *d = htobe64(pa | rxb->hwidx1); 5163 sd->moff = 0; 5164 } 5165 recycled: 5166 sd->nmbuf = 0; 5167 d++; 5168 sd++; 5169 if (__predict_false((++fl->pidx & 7) == 0)) { 5170 uint16_t pidx = fl->pidx >> 3; 5171 5172 if (__predict_false(pidx == fl->sidx)) { 5173 fl->pidx = 0; 5174 pidx = 0; 5175 sd = fl->sdesc; 5176 d = fl->desc; 5177 } 5178 if (n < 8 || pidx == max_pidx) 5179 break; 5180 5181 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5182 ring_fl_db(sc, fl); 5183 } 5184 } 5185 5186 if ((fl->pidx >> 3) != fl->dbidx) 5187 ring_fl_db(sc, fl); 5188 5189 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5190 } 5191 5192 /* 5193 * Attempt to refill all starving freelists. 5194 */ 5195 static void 5196 refill_sfl(void *arg) 5197 { 5198 struct adapter *sc = arg; 5199 struct sge_fl *fl, *fl_temp; 5200 5201 mtx_assert(&sc->sfl_lock, MA_OWNED); 5202 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5203 FL_LOCK(fl); 5204 refill_fl(sc, fl, 64); 5205 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5206 TAILQ_REMOVE(&sc->sfl, fl, link); 5207 fl->flags &= ~FL_STARVING; 5208 } 5209 FL_UNLOCK(fl); 5210 } 5211 5212 if (!TAILQ_EMPTY(&sc->sfl)) 5213 callout_schedule(&sc->sfl_callout, hz / 5); 5214 } 5215 5216 /* 5217 * Release the driver's reference on all buffers in the given freelist. Buffers 5218 * with kernel references cannot be freed and will prevent the driver from being 5219 * unloaded safely. 5220 */ 5221 void 5222 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5223 { 5224 struct fl_sdesc *sd; 5225 struct cluster_metadata *clm; 5226 int i; 5227 5228 sd = fl->sdesc; 5229 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5230 if (sd->cl == NULL) 5231 continue; 5232 5233 if (sd->nmbuf == 0) 5234 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5235 else if (fl->flags & FL_BUF_PACKING) { 5236 clm = cl_metadata(sd); 5237 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5238 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5239 sd->cl); 5240 counter_u64_add(extfree_rels, 1); 5241 } 5242 } 5243 sd->cl = NULL; 5244 } 5245 5246 if (fl->flags & FL_BUF_RESUME) { 5247 m_freem(fl->m0); 5248 fl->flags &= ~FL_BUF_RESUME; 5249 } 5250 } 5251 5252 static inline void 5253 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5254 { 5255 int rc; 5256 5257 M_ASSERTPKTHDR(m); 5258 5259 sglist_reset(gl); 5260 rc = sglist_append_mbuf(gl, m); 5261 if (__predict_false(rc != 0)) { 5262 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5263 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5264 } 5265 5266 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5267 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5268 mbuf_nsegs(m), gl->sg_nseg)); 5269 #if 0 /* vm_wr not readily available here. */ 5270 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5271 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5272 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5273 #endif 5274 } 5275 5276 /* 5277 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5278 */ 5279 static inline u_int 5280 txpkt_len16(u_int nsegs, const u_int extra) 5281 { 5282 u_int n; 5283 5284 MPASS(nsegs > 0); 5285 5286 nsegs--; /* first segment is part of ulptx_sgl */ 5287 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5288 sizeof(struct cpl_tx_pkt_core) + 5289 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5290 5291 return (howmany(n, 16)); 5292 } 5293 5294 /* 5295 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5296 * request header. 5297 */ 5298 static inline u_int 5299 txpkt_vm_len16(u_int nsegs, const u_int extra) 5300 { 5301 u_int n; 5302 5303 MPASS(nsegs > 0); 5304 5305 nsegs--; /* first segment is part of ulptx_sgl */ 5306 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5307 sizeof(struct cpl_tx_pkt_core) + 5308 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5309 5310 return (howmany(n, 16)); 5311 } 5312 5313 static inline void 5314 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5315 { 5316 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5317 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5318 5319 if (vm_wr) { 5320 if (needs_tso(m)) 5321 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5322 else 5323 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5324 return; 5325 } 5326 5327 if (needs_tso(m)) { 5328 if (needs_vxlan_tso(m)) 5329 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5330 else 5331 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5332 } else 5333 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5334 } 5335 5336 /* 5337 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5338 * request header. 5339 */ 5340 static inline u_int 5341 txpkts0_len16(u_int nsegs) 5342 { 5343 u_int n; 5344 5345 MPASS(nsegs > 0); 5346 5347 nsegs--; /* first segment is part of ulptx_sgl */ 5348 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5349 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5350 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5351 5352 return (howmany(n, 16)); 5353 } 5354 5355 /* 5356 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5357 * request header. 5358 */ 5359 static inline u_int 5360 txpkts1_len16(void) 5361 { 5362 u_int n; 5363 5364 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5365 5366 return (howmany(n, 16)); 5367 } 5368 5369 static inline u_int 5370 imm_payload(u_int ndesc) 5371 { 5372 u_int n; 5373 5374 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5375 sizeof(struct cpl_tx_pkt_core); 5376 5377 return (n); 5378 } 5379 5380 static inline uint64_t 5381 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5382 { 5383 uint64_t ctrl; 5384 int csum_type, l2hlen, l3hlen; 5385 int x, y; 5386 static const int csum_types[3][2] = { 5387 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5388 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5389 {TX_CSUM_IP, 0} 5390 }; 5391 5392 M_ASSERTPKTHDR(m); 5393 5394 if (!needs_hwcsum(m)) 5395 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5396 5397 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5398 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5399 5400 if (needs_vxlan_csum(m)) { 5401 MPASS(m->m_pkthdr.l4hlen > 0); 5402 MPASS(m->m_pkthdr.l5hlen > 0); 5403 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5404 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5405 5406 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5407 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5408 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5409 l3hlen = m->m_pkthdr.inner_l3hlen; 5410 } else { 5411 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5412 l3hlen = m->m_pkthdr.l3hlen; 5413 } 5414 5415 ctrl = 0; 5416 if (!needs_l3_csum(m)) 5417 ctrl |= F_TXPKT_IPCSUM_DIS; 5418 5419 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5420 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5421 x = 0; /* TCP */ 5422 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5423 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5424 x = 1; /* UDP */ 5425 else 5426 x = 2; 5427 5428 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5429 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5430 y = 0; /* IPv4 */ 5431 else { 5432 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5433 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5434 y = 1; /* IPv6 */ 5435 } 5436 /* 5437 * needs_hwcsum returned true earlier so there must be some kind of 5438 * checksum to calculate. 5439 */ 5440 csum_type = csum_types[x][y]; 5441 MPASS(csum_type != 0); 5442 if (csum_type == TX_CSUM_IP) 5443 ctrl |= F_TXPKT_L4CSUM_DIS; 5444 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5445 if (chip_id(sc) <= CHELSIO_T5) 5446 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5447 else 5448 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5449 5450 return (ctrl); 5451 } 5452 5453 static inline void * 5454 write_lso_cpl(void *cpl, struct mbuf *m0) 5455 { 5456 struct cpl_tx_pkt_lso_core *lso; 5457 uint32_t ctrl; 5458 5459 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5460 m0->m_pkthdr.l4hlen > 0, 5461 ("%s: mbuf %p needs TSO but missing header lengths", 5462 __func__, m0)); 5463 5464 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5465 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5466 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5467 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5468 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5469 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5470 ctrl |= F_LSO_IPV6; 5471 5472 lso = cpl; 5473 lso->lso_ctrl = htobe32(ctrl); 5474 lso->ipid_ofst = htobe16(0); 5475 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5476 lso->seqno_offset = htobe32(0); 5477 lso->len = htobe32(m0->m_pkthdr.len); 5478 5479 return (lso + 1); 5480 } 5481 5482 static void * 5483 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5484 { 5485 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5486 uint32_t ctrl; 5487 5488 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5489 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5490 m0->m_pkthdr.inner_l5hlen > 0, 5491 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5492 __func__, m0)); 5493 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5494 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5495 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5496 __func__, m0)); 5497 5498 /* Outer headers. */ 5499 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5500 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5501 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5502 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5503 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5504 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5505 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5506 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5507 else { 5508 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5509 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5510 } 5511 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5512 tnl_lso->IpIdOffsetOut = 0; 5513 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5514 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5515 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5516 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5517 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5518 m0->m_pkthdr.l5hlen) | 5519 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5520 tnl_lso->ipsecen_to_rocev2 = 0; 5521 tnl_lso->roce_eth = 0; 5522 5523 /* Inner headers. */ 5524 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5525 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5526 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5527 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5528 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5529 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5530 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5531 tnl_lso->IpIdOffset = 0; 5532 tnl_lso->IpIdSplit_to_Mss = 5533 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5534 tnl_lso->TCPSeqOffset = 0; 5535 tnl_lso->EthLenOffset_Size = 5536 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5537 5538 return (tnl_lso + 1); 5539 } 5540 5541 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5542 5543 /* 5544 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5545 * software descriptor, and advance the pidx. It is guaranteed that enough 5546 * descriptors are available. 5547 * 5548 * The return value is the # of hardware descriptors used. 5549 */ 5550 static u_int 5551 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5552 { 5553 struct sge_eq *eq; 5554 struct fw_eth_tx_pkt_vm_wr *wr; 5555 struct tx_sdesc *txsd; 5556 struct cpl_tx_pkt_core *cpl; 5557 uint32_t ctrl; /* used in many unrelated places */ 5558 uint64_t ctrl1; 5559 int len16, ndesc, pktlen; 5560 caddr_t dst; 5561 5562 TXQ_LOCK_ASSERT_OWNED(txq); 5563 M_ASSERTPKTHDR(m0); 5564 5565 len16 = mbuf_len16(m0); 5566 pktlen = m0->m_pkthdr.len; 5567 ctrl = sizeof(struct cpl_tx_pkt_core); 5568 if (needs_tso(m0)) 5569 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5570 ndesc = tx_len16_to_desc(len16); 5571 5572 /* Firmware work request header */ 5573 eq = &txq->eq; 5574 wr = (void *)&eq->desc[eq->pidx]; 5575 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5576 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5577 5578 ctrl = V_FW_WR_LEN16(len16); 5579 wr->equiq_to_len16 = htobe32(ctrl); 5580 wr->r3[0] = 0; 5581 wr->r3[1] = 0; 5582 5583 /* 5584 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5585 * vlantci is ignored unless the ethtype is 0x8100, so it's 5586 * simpler to always copy it rather than making it 5587 * conditional. Also, it seems that we do not have to set 5588 * vlantci or fake the ethtype when doing VLAN tag insertion. 5589 */ 5590 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5591 5592 if (needs_tso(m0)) { 5593 cpl = write_lso_cpl(wr + 1, m0); 5594 txq->tso_wrs++; 5595 } else 5596 cpl = (void *)(wr + 1); 5597 5598 /* Checksum offload */ 5599 ctrl1 = csum_to_ctrl(sc, m0); 5600 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5601 txq->txcsum++; /* some hardware assistance provided */ 5602 5603 /* VLAN tag insertion */ 5604 if (needs_vlan_insertion(m0)) { 5605 ctrl1 |= F_TXPKT_VLAN_VLD | 5606 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5607 txq->vlan_insertion++; 5608 } else if (sc->vlan_id) 5609 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id); 5610 5611 /* CPL header */ 5612 cpl->ctrl0 = txq->cpl_ctrl0; 5613 cpl->pack = 0; 5614 cpl->len = htobe16(pktlen); 5615 cpl->ctrl1 = htobe64(ctrl1); 5616 5617 /* SGL */ 5618 dst = (void *)(cpl + 1); 5619 5620 /* 5621 * A packet using TSO will use up an entire descriptor for the 5622 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5623 * If this descriptor is the last descriptor in the ring, wrap 5624 * around to the front of the ring explicitly for the start of 5625 * the sgl. 5626 */ 5627 if (dst == (void *)&eq->desc[eq->sidx]) { 5628 dst = (void *)&eq->desc[0]; 5629 write_gl_to_txd(txq, m0, &dst, 0); 5630 } else 5631 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5632 txq->sgl_wrs++; 5633 txq->txpkt_wrs++; 5634 5635 txsd = &txq->sdesc[eq->pidx]; 5636 txsd->m = m0; 5637 txsd->desc_used = ndesc; 5638 5639 return (ndesc); 5640 } 5641 5642 /* 5643 * Write a raw WR to the hardware descriptors, update the software 5644 * descriptor, and advance the pidx. It is guaranteed that enough 5645 * descriptors are available. 5646 * 5647 * The return value is the # of hardware descriptors used. 5648 */ 5649 static u_int 5650 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5651 { 5652 struct sge_eq *eq = &txq->eq; 5653 struct tx_sdesc *txsd; 5654 struct mbuf *m; 5655 caddr_t dst; 5656 int len16, ndesc; 5657 5658 len16 = mbuf_len16(m0); 5659 ndesc = tx_len16_to_desc(len16); 5660 MPASS(ndesc <= available); 5661 5662 dst = wr; 5663 for (m = m0; m != NULL; m = m->m_next) 5664 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5665 5666 txq->raw_wrs++; 5667 5668 txsd = &txq->sdesc[eq->pidx]; 5669 txsd->m = m0; 5670 txsd->desc_used = ndesc; 5671 5672 return (ndesc); 5673 } 5674 5675 /* 5676 * Write a txpkt WR for this packet to the hardware descriptors, update the 5677 * software descriptor, and advance the pidx. It is guaranteed that enough 5678 * descriptors are available. 5679 * 5680 * The return value is the # of hardware descriptors used. 5681 */ 5682 static u_int 5683 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5684 u_int available) 5685 { 5686 struct sge_eq *eq; 5687 struct fw_eth_tx_pkt_wr *wr; 5688 struct tx_sdesc *txsd; 5689 struct cpl_tx_pkt_core *cpl; 5690 uint32_t ctrl; /* used in many unrelated places */ 5691 uint64_t ctrl1; 5692 int len16, ndesc, pktlen, nsegs; 5693 caddr_t dst; 5694 5695 TXQ_LOCK_ASSERT_OWNED(txq); 5696 M_ASSERTPKTHDR(m0); 5697 5698 len16 = mbuf_len16(m0); 5699 nsegs = mbuf_nsegs(m0); 5700 pktlen = m0->m_pkthdr.len; 5701 ctrl = sizeof(struct cpl_tx_pkt_core); 5702 if (needs_tso(m0)) { 5703 if (needs_vxlan_tso(m0)) 5704 ctrl += sizeof(struct cpl_tx_tnl_lso); 5705 else 5706 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5707 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5708 available >= 2) { 5709 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5710 ctrl += pktlen; 5711 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5712 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5713 nsegs = 0; 5714 } 5715 ndesc = tx_len16_to_desc(len16); 5716 MPASS(ndesc <= available); 5717 5718 /* Firmware work request header */ 5719 eq = &txq->eq; 5720 wr = (void *)&eq->desc[eq->pidx]; 5721 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5722 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5723 5724 ctrl = V_FW_WR_LEN16(len16); 5725 wr->equiq_to_len16 = htobe32(ctrl); 5726 wr->r3 = 0; 5727 5728 if (needs_tso(m0)) { 5729 if (needs_vxlan_tso(m0)) { 5730 cpl = write_tnl_lso_cpl(wr + 1, m0); 5731 txq->vxlan_tso_wrs++; 5732 } else { 5733 cpl = write_lso_cpl(wr + 1, m0); 5734 txq->tso_wrs++; 5735 } 5736 } else 5737 cpl = (void *)(wr + 1); 5738 5739 /* Checksum offload */ 5740 ctrl1 = csum_to_ctrl(sc, m0); 5741 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5742 /* some hardware assistance provided */ 5743 if (needs_vxlan_csum(m0)) 5744 txq->vxlan_txcsum++; 5745 else 5746 txq->txcsum++; 5747 } 5748 5749 /* VLAN tag insertion */ 5750 if (needs_vlan_insertion(m0)) { 5751 ctrl1 |= F_TXPKT_VLAN_VLD | 5752 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5753 txq->vlan_insertion++; 5754 } 5755 5756 /* CPL header */ 5757 cpl->ctrl0 = txq->cpl_ctrl0; 5758 cpl->pack = 0; 5759 cpl->len = htobe16(pktlen); 5760 cpl->ctrl1 = htobe64(ctrl1); 5761 5762 /* SGL */ 5763 dst = (void *)(cpl + 1); 5764 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5765 dst = (caddr_t)&eq->desc[0]; 5766 if (nsegs > 0) { 5767 5768 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5769 txq->sgl_wrs++; 5770 } else { 5771 struct mbuf *m; 5772 5773 for (m = m0; m != NULL; m = m->m_next) { 5774 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5775 #ifdef INVARIANTS 5776 pktlen -= m->m_len; 5777 #endif 5778 } 5779 #ifdef INVARIANTS 5780 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5781 #endif 5782 txq->imm_wrs++; 5783 } 5784 5785 txq->txpkt_wrs++; 5786 5787 txsd = &txq->sdesc[eq->pidx]; 5788 txsd->m = m0; 5789 txsd->desc_used = ndesc; 5790 5791 return (ndesc); 5792 } 5793 5794 static inline bool 5795 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5796 { 5797 int len; 5798 5799 MPASS(txp->npkt > 0); 5800 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5801 5802 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5803 len = VM_TX_L2HDR_LEN; 5804 else 5805 len = sizeof(struct ether_header); 5806 5807 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5808 } 5809 5810 static inline void 5811 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5812 { 5813 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5814 5815 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5816 } 5817 5818 static int 5819 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5820 int avail, bool *send) 5821 { 5822 struct txpkts *txp = &txq->txp; 5823 5824 /* Cannot have TSO and coalesce at the same time. */ 5825 if (cannot_use_txpkts(m)) { 5826 cannot_coalesce: 5827 *send = txp->npkt > 0; 5828 return (EINVAL); 5829 } 5830 5831 /* VF allows coalescing of type 1 (1 GL) only */ 5832 if (mbuf_nsegs(m) > 1) 5833 goto cannot_coalesce; 5834 5835 *send = false; 5836 if (txp->npkt > 0) { 5837 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5838 MPASS(txp->npkt < txp->max_npkt); 5839 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5840 5841 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5842 retry_after_send: 5843 *send = true; 5844 return (EAGAIN); 5845 } 5846 if (m->m_pkthdr.len + txp->plen > 65535) 5847 goto retry_after_send; 5848 if (cmp_l2hdr(txp, m)) 5849 goto retry_after_send; 5850 5851 txp->len16 += txpkts1_len16(); 5852 txp->plen += m->m_pkthdr.len; 5853 txp->mb[txp->npkt++] = m; 5854 if (txp->npkt == txp->max_npkt) 5855 *send = true; 5856 } else { 5857 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5858 txpkts1_len16(); 5859 if (tx_len16_to_desc(txp->len16) > avail) 5860 goto cannot_coalesce; 5861 txp->npkt = 1; 5862 txp->wr_type = 1; 5863 txp->plen = m->m_pkthdr.len; 5864 txp->mb[0] = m; 5865 save_l2hdr(txp, m); 5866 } 5867 return (0); 5868 } 5869 5870 static int 5871 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5872 int avail, bool *send) 5873 { 5874 struct txpkts *txp = &txq->txp; 5875 int nsegs; 5876 5877 MPASS(!(sc->flags & IS_VF)); 5878 5879 /* Cannot have TSO and coalesce at the same time. */ 5880 if (cannot_use_txpkts(m)) { 5881 cannot_coalesce: 5882 *send = txp->npkt > 0; 5883 return (EINVAL); 5884 } 5885 5886 *send = false; 5887 nsegs = mbuf_nsegs(m); 5888 if (txp->npkt == 0) { 5889 if (m->m_pkthdr.len > 65535) 5890 goto cannot_coalesce; 5891 if (nsegs > 1) { 5892 txp->wr_type = 0; 5893 txp->len16 = 5894 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5895 txpkts0_len16(nsegs); 5896 } else { 5897 txp->wr_type = 1; 5898 txp->len16 = 5899 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5900 txpkts1_len16(); 5901 } 5902 if (tx_len16_to_desc(txp->len16) > avail) 5903 goto cannot_coalesce; 5904 txp->npkt = 1; 5905 txp->plen = m->m_pkthdr.len; 5906 txp->mb[0] = m; 5907 } else { 5908 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5909 MPASS(txp->npkt < txp->max_npkt); 5910 5911 if (m->m_pkthdr.len + txp->plen > 65535) { 5912 retry_after_send: 5913 *send = true; 5914 return (EAGAIN); 5915 } 5916 5917 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5918 if (txp->wr_type == 0) { 5919 if (tx_len16_to_desc(txp->len16 + 5920 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5921 goto retry_after_send; 5922 txp->len16 += txpkts0_len16(nsegs); 5923 } else { 5924 if (nsegs != 1) 5925 goto retry_after_send; 5926 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5927 avail) 5928 goto retry_after_send; 5929 txp->len16 += txpkts1_len16(); 5930 } 5931 5932 txp->plen += m->m_pkthdr.len; 5933 txp->mb[txp->npkt++] = m; 5934 if (txp->npkt == txp->max_npkt) 5935 *send = true; 5936 } 5937 return (0); 5938 } 5939 5940 /* 5941 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5942 * the software descriptor, and advance the pidx. It is guaranteed that enough 5943 * descriptors are available. 5944 * 5945 * The return value is the # of hardware descriptors used. 5946 */ 5947 static u_int 5948 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5949 { 5950 const struct txpkts *txp = &txq->txp; 5951 struct sge_eq *eq = &txq->eq; 5952 struct fw_eth_tx_pkts_wr *wr; 5953 struct tx_sdesc *txsd; 5954 struct cpl_tx_pkt_core *cpl; 5955 uint64_t ctrl1; 5956 int ndesc, i, checkwrap; 5957 struct mbuf *m, *last; 5958 void *flitp; 5959 5960 TXQ_LOCK_ASSERT_OWNED(txq); 5961 MPASS(txp->npkt > 0); 5962 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5963 5964 wr = (void *)&eq->desc[eq->pidx]; 5965 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5966 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5967 wr->plen = htobe16(txp->plen); 5968 wr->npkt = txp->npkt; 5969 wr->r3 = 0; 5970 wr->type = txp->wr_type; 5971 flitp = wr + 1; 5972 5973 /* 5974 * At this point we are 16B into a hardware descriptor. If checkwrap is 5975 * set then we know the WR is going to wrap around somewhere. We'll 5976 * check for that at appropriate points. 5977 */ 5978 ndesc = tx_len16_to_desc(txp->len16); 5979 last = NULL; 5980 checkwrap = eq->sidx - ndesc < eq->pidx; 5981 for (i = 0; i < txp->npkt; i++) { 5982 m = txp->mb[i]; 5983 if (txp->wr_type == 0) { 5984 struct ulp_txpkt *ulpmc; 5985 struct ulptx_idata *ulpsc; 5986 5987 /* ULP master command */ 5988 ulpmc = flitp; 5989 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5990 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5991 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5992 5993 /* ULP subcommand */ 5994 ulpsc = (void *)(ulpmc + 1); 5995 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5996 F_ULP_TX_SC_MORE); 5997 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5998 5999 cpl = (void *)(ulpsc + 1); 6000 if (checkwrap && 6001 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 6002 cpl = (void *)&eq->desc[0]; 6003 } else { 6004 cpl = flitp; 6005 } 6006 6007 /* Checksum offload */ 6008 ctrl1 = csum_to_ctrl(sc, m); 6009 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 6010 /* some hardware assistance provided */ 6011 if (needs_vxlan_csum(m)) 6012 txq->vxlan_txcsum++; 6013 else 6014 txq->txcsum++; 6015 } 6016 6017 /* VLAN tag insertion */ 6018 if (needs_vlan_insertion(m)) { 6019 ctrl1 |= F_TXPKT_VLAN_VLD | 6020 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6021 txq->vlan_insertion++; 6022 } 6023 6024 /* CPL header */ 6025 cpl->ctrl0 = txq->cpl_ctrl0; 6026 cpl->pack = 0; 6027 cpl->len = htobe16(m->m_pkthdr.len); 6028 cpl->ctrl1 = htobe64(ctrl1); 6029 6030 flitp = cpl + 1; 6031 if (checkwrap && 6032 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6033 flitp = (void *)&eq->desc[0]; 6034 6035 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 6036 6037 if (last != NULL) 6038 last->m_nextpkt = m; 6039 last = m; 6040 } 6041 6042 txq->sgl_wrs++; 6043 if (txp->wr_type == 0) { 6044 txq->txpkts0_pkts += txp->npkt; 6045 txq->txpkts0_wrs++; 6046 } else { 6047 txq->txpkts1_pkts += txp->npkt; 6048 txq->txpkts1_wrs++; 6049 } 6050 6051 txsd = &txq->sdesc[eq->pidx]; 6052 txsd->m = txp->mb[0]; 6053 txsd->desc_used = ndesc; 6054 6055 return (ndesc); 6056 } 6057 6058 static u_int 6059 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 6060 { 6061 const struct txpkts *txp = &txq->txp; 6062 struct sge_eq *eq = &txq->eq; 6063 struct fw_eth_tx_pkts_vm_wr *wr; 6064 struct tx_sdesc *txsd; 6065 struct cpl_tx_pkt_core *cpl; 6066 uint64_t ctrl1; 6067 int ndesc, i; 6068 struct mbuf *m, *last; 6069 void *flitp; 6070 6071 TXQ_LOCK_ASSERT_OWNED(txq); 6072 MPASS(txp->npkt > 0); 6073 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 6074 MPASS(txp->mb[0] != NULL); 6075 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 6076 6077 wr = (void *)&eq->desc[eq->pidx]; 6078 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 6079 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 6080 wr->r3 = 0; 6081 wr->plen = htobe16(txp->plen); 6082 wr->npkt = txp->npkt; 6083 wr->r4 = 0; 6084 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 6085 flitp = wr + 1; 6086 6087 /* 6088 * At this point we are 32B into a hardware descriptor. Each mbuf in 6089 * the WR will take 32B so we check for the end of the descriptor ring 6090 * before writing odd mbufs (mb[1], 3, 5, ..) 6091 */ 6092 ndesc = tx_len16_to_desc(txp->len16); 6093 last = NULL; 6094 for (i = 0; i < txp->npkt; i++) { 6095 m = txp->mb[i]; 6096 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6097 flitp = &eq->desc[0]; 6098 cpl = flitp; 6099 6100 /* Checksum offload */ 6101 ctrl1 = csum_to_ctrl(sc, m); 6102 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 6103 txq->txcsum++; /* some hardware assistance provided */ 6104 6105 /* VLAN tag insertion */ 6106 if (needs_vlan_insertion(m)) { 6107 ctrl1 |= F_TXPKT_VLAN_VLD | 6108 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6109 txq->vlan_insertion++; 6110 } else if (sc->vlan_id) 6111 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id); 6112 6113 /* CPL header */ 6114 cpl->ctrl0 = txq->cpl_ctrl0; 6115 cpl->pack = 0; 6116 cpl->len = htobe16(m->m_pkthdr.len); 6117 cpl->ctrl1 = htobe64(ctrl1); 6118 6119 flitp = cpl + 1; 6120 MPASS(mbuf_nsegs(m) == 1); 6121 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 6122 6123 if (last != NULL) 6124 last->m_nextpkt = m; 6125 last = m; 6126 } 6127 6128 txq->sgl_wrs++; 6129 txq->txpkts1_pkts += txp->npkt; 6130 txq->txpkts1_wrs++; 6131 6132 txsd = &txq->sdesc[eq->pidx]; 6133 txsd->m = txp->mb[0]; 6134 txsd->desc_used = ndesc; 6135 6136 return (ndesc); 6137 } 6138 6139 /* 6140 * If the SGL ends on an address that is not 16 byte aligned, this function will 6141 * add a 0 filled flit at the end. 6142 */ 6143 static void 6144 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 6145 { 6146 struct sge_eq *eq = &txq->eq; 6147 struct sglist *gl = txq->gl; 6148 struct sglist_seg *seg; 6149 __be64 *flitp, *wrap; 6150 struct ulptx_sgl *usgl; 6151 int i, nflits, nsegs; 6152 6153 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 6154 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 6155 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6156 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6157 6158 get_pkt_gl(m, gl); 6159 nsegs = gl->sg_nseg; 6160 MPASS(nsegs > 0); 6161 6162 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 6163 flitp = (__be64 *)(*to); 6164 wrap = (__be64 *)(&eq->desc[eq->sidx]); 6165 seg = &gl->sg_segs[0]; 6166 usgl = (void *)flitp; 6167 6168 /* 6169 * We start at a 16 byte boundary somewhere inside the tx descriptor 6170 * ring, so we're at least 16 bytes away from the status page. There is 6171 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 6172 */ 6173 6174 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6175 V_ULPTX_NSGE(nsegs)); 6176 usgl->len0 = htobe32(seg->ss_len); 6177 usgl->addr0 = htobe64(seg->ss_paddr); 6178 seg++; 6179 6180 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6181 6182 /* Won't wrap around at all */ 6183 6184 for (i = 0; i < nsegs - 1; i++, seg++) { 6185 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6186 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6187 } 6188 if (i & 1) 6189 usgl->sge[i / 2].len[1] = htobe32(0); 6190 flitp += nflits; 6191 } else { 6192 6193 /* Will wrap somewhere in the rest of the SGL */ 6194 6195 /* 2 flits already written, write the rest flit by flit */ 6196 flitp = (void *)(usgl + 1); 6197 for (i = 0; i < nflits - 2; i++) { 6198 if (flitp == wrap) 6199 flitp = (void *)eq->desc; 6200 *flitp++ = get_flit(seg, nsegs - 1, i); 6201 } 6202 } 6203 6204 if (nflits & 1) { 6205 MPASS(((uintptr_t)flitp) & 0xf); 6206 *flitp++ = 0; 6207 } 6208 6209 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6210 if (__predict_false(flitp == wrap)) 6211 *to = (void *)eq->desc; 6212 else 6213 *to = (void *)flitp; 6214 } 6215 6216 static inline void 6217 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6218 { 6219 6220 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6221 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6222 6223 if (__predict_true((uintptr_t)(*to) + len <= 6224 (uintptr_t)&eq->desc[eq->sidx])) { 6225 bcopy(from, *to, len); 6226 (*to) += len; 6227 } else { 6228 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6229 6230 bcopy(from, *to, portion); 6231 from += portion; 6232 portion = len - portion; /* remaining */ 6233 bcopy(from, (void *)eq->desc, portion); 6234 (*to) = (caddr_t)eq->desc + portion; 6235 } 6236 } 6237 6238 static inline void 6239 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6240 { 6241 u_int db; 6242 6243 MPASS(n > 0); 6244 6245 db = eq->doorbells; 6246 if (n > 1) 6247 clrbit(&db, DOORBELL_WCWR); 6248 wmb(); 6249 6250 switch (ffs(db) - 1) { 6251 case DOORBELL_UDB: 6252 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6253 break; 6254 6255 case DOORBELL_WCWR: { 6256 volatile uint64_t *dst, *src; 6257 int i; 6258 6259 /* 6260 * Queues whose 128B doorbell segment fits in the page do not 6261 * use relative qid (udb_qid is always 0). Only queues with 6262 * doorbell segments can do WCWR. 6263 */ 6264 KASSERT(eq->udb_qid == 0 && n == 1, 6265 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6266 __func__, eq->doorbells, n, eq->dbidx, eq)); 6267 6268 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6269 UDBS_DB_OFFSET); 6270 i = eq->dbidx; 6271 src = (void *)&eq->desc[i]; 6272 while (src != (void *)&eq->desc[i + 1]) 6273 *dst++ = *src++; 6274 wmb(); 6275 break; 6276 } 6277 6278 case DOORBELL_UDBWC: 6279 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6280 wmb(); 6281 break; 6282 6283 case DOORBELL_KDB: 6284 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6285 V_QID(eq->cntxt_id) | V_PIDX(n)); 6286 break; 6287 } 6288 6289 IDXINCR(eq->dbidx, n, eq->sidx); 6290 } 6291 6292 static inline u_int 6293 reclaimable_tx_desc(struct sge_eq *eq) 6294 { 6295 uint16_t hw_cidx; 6296 6297 hw_cidx = read_hw_cidx(eq); 6298 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6299 } 6300 6301 static inline u_int 6302 total_available_tx_desc(struct sge_eq *eq) 6303 { 6304 uint16_t hw_cidx, pidx; 6305 6306 hw_cidx = read_hw_cidx(eq); 6307 pidx = eq->pidx; 6308 6309 if (pidx == hw_cidx) 6310 return (eq->sidx - 1); 6311 else 6312 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6313 } 6314 6315 static inline uint16_t 6316 read_hw_cidx(struct sge_eq *eq) 6317 { 6318 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6319 uint16_t cidx = spg->cidx; /* stable snapshot */ 6320 6321 return (be16toh(cidx)); 6322 } 6323 6324 /* 6325 * Reclaim 'n' descriptors approximately. 6326 */ 6327 static u_int 6328 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6329 { 6330 struct tx_sdesc *txsd; 6331 struct sge_eq *eq = &txq->eq; 6332 u_int can_reclaim, reclaimed; 6333 6334 TXQ_LOCK_ASSERT_OWNED(txq); 6335 MPASS(n > 0); 6336 6337 reclaimed = 0; 6338 can_reclaim = reclaimable_tx_desc(eq); 6339 while (can_reclaim && reclaimed < n) { 6340 int ndesc; 6341 struct mbuf *m, *nextpkt; 6342 6343 txsd = &txq->sdesc[eq->cidx]; 6344 ndesc = txsd->desc_used; 6345 6346 /* Firmware doesn't return "partial" credits. */ 6347 KASSERT(can_reclaim >= ndesc, 6348 ("%s: unexpected number of credits: %d, %d", 6349 __func__, can_reclaim, ndesc)); 6350 KASSERT(ndesc != 0, 6351 ("%s: descriptor with no credits: cidx %d", 6352 __func__, eq->cidx)); 6353 6354 for (m = txsd->m; m != NULL; m = nextpkt) { 6355 nextpkt = m->m_nextpkt; 6356 m->m_nextpkt = NULL; 6357 m_freem(m); 6358 } 6359 reclaimed += ndesc; 6360 can_reclaim -= ndesc; 6361 IDXINCR(eq->cidx, ndesc, eq->sidx); 6362 } 6363 6364 return (reclaimed); 6365 } 6366 6367 static void 6368 tx_reclaim(void *arg, int n) 6369 { 6370 struct sge_txq *txq = arg; 6371 struct sge_eq *eq = &txq->eq; 6372 6373 do { 6374 if (TXQ_TRYLOCK(txq) == 0) 6375 break; 6376 n = reclaim_tx_descs(txq, 32); 6377 if (eq->cidx == eq->pidx) 6378 eq->equeqidx = eq->pidx; 6379 TXQ_UNLOCK(txq); 6380 } while (n > 0); 6381 } 6382 6383 static __be64 6384 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6385 { 6386 int i = (idx / 3) * 2; 6387 6388 switch (idx % 3) { 6389 case 0: { 6390 uint64_t rc; 6391 6392 rc = (uint64_t)segs[i].ss_len << 32; 6393 if (i + 1 < nsegs) 6394 rc |= (uint64_t)(segs[i + 1].ss_len); 6395 6396 return (htobe64(rc)); 6397 } 6398 case 1: 6399 return (htobe64(segs[i].ss_paddr)); 6400 case 2: 6401 return (htobe64(segs[i + 1].ss_paddr)); 6402 } 6403 6404 return (0); 6405 } 6406 6407 static int 6408 find_refill_source(struct adapter *sc, int maxp, bool packing) 6409 { 6410 int i, zidx = -1; 6411 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6412 6413 if (packing) { 6414 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6415 if (rxb->hwidx2 == -1) 6416 continue; 6417 if (rxb->size1 < PAGE_SIZE && 6418 rxb->size1 < largest_rx_cluster) 6419 continue; 6420 if (rxb->size1 > largest_rx_cluster) 6421 break; 6422 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6423 if (rxb->size2 >= maxp) 6424 return (i); 6425 zidx = i; 6426 } 6427 } else { 6428 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6429 if (rxb->hwidx1 == -1) 6430 continue; 6431 if (rxb->size1 > largest_rx_cluster) 6432 break; 6433 if (rxb->size1 >= maxp) 6434 return (i); 6435 zidx = i; 6436 } 6437 } 6438 6439 return (zidx); 6440 } 6441 6442 static void 6443 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6444 { 6445 mtx_lock(&sc->sfl_lock); 6446 FL_LOCK(fl); 6447 if ((fl->flags & FL_DOOMED) == 0) { 6448 fl->flags |= FL_STARVING; 6449 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6450 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6451 } 6452 FL_UNLOCK(fl); 6453 mtx_unlock(&sc->sfl_lock); 6454 } 6455 6456 static void 6457 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6458 { 6459 struct sge_wrq *wrq = (void *)eq; 6460 6461 atomic_readandclear_int(&eq->equiq); 6462 taskqueue_enqueue(sc->tq[eq->port_id], &wrq->wrq_tx_task); 6463 } 6464 6465 static void 6466 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6467 { 6468 struct sge_txq *txq = (void *)eq; 6469 6470 MPASS(eq->type == EQ_ETH); 6471 6472 atomic_readandclear_int(&eq->equiq); 6473 if (mp_ring_is_idle(txq->r)) 6474 taskqueue_enqueue(sc->tq[eq->port_id], &txq->tx_reclaim_task); 6475 else 6476 mp_ring_check_drainage(txq->r, 64); 6477 } 6478 6479 static int 6480 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6481 struct mbuf *m) 6482 { 6483 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6484 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6485 struct adapter *sc = iq->adapter; 6486 struct sge *s = &sc->sge; 6487 struct sge_eq *eq; 6488 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6489 &handle_wrq_egr_update, &handle_eth_egr_update, 6490 &handle_wrq_egr_update}; 6491 6492 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6493 rss->opcode)); 6494 6495 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6496 (*h[eq->type])(sc, eq); 6497 6498 return (0); 6499 } 6500 6501 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6502 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6503 offsetof(struct cpl_fw6_msg, data)); 6504 6505 static int 6506 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6507 { 6508 struct adapter *sc = iq->adapter; 6509 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6510 6511 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6512 rss->opcode)); 6513 6514 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6515 const struct rss_header *rss2; 6516 6517 rss2 = (const struct rss_header *)&cpl->data[0]; 6518 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6519 } 6520 6521 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6522 } 6523 6524 /** 6525 * t4_handle_wrerr_rpl - process a FW work request error message 6526 * @adap: the adapter 6527 * @rpl: start of the FW message 6528 */ 6529 static int 6530 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6531 { 6532 u8 opcode = *(const u8 *)rpl; 6533 const struct fw_error_cmd *e = (const void *)rpl; 6534 unsigned int i; 6535 6536 if (opcode != FW_ERROR_CMD) { 6537 log(LOG_ERR, 6538 "%s: Received WRERR_RPL message with opcode %#x\n", 6539 device_get_nameunit(adap->dev), opcode); 6540 return (EINVAL); 6541 } 6542 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6543 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6544 "non-fatal"); 6545 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6546 case FW_ERROR_TYPE_EXCEPTION: 6547 log(LOG_ERR, "exception info:\n"); 6548 for (i = 0; i < nitems(e->u.exception.info); i++) 6549 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6550 be32toh(e->u.exception.info[i])); 6551 log(LOG_ERR, "\n"); 6552 break; 6553 case FW_ERROR_TYPE_HWMODULE: 6554 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6555 be32toh(e->u.hwmodule.regaddr), 6556 be32toh(e->u.hwmodule.regval)); 6557 break; 6558 case FW_ERROR_TYPE_WR: 6559 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6560 be16toh(e->u.wr.cidx), 6561 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6562 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6563 be32toh(e->u.wr.eqid)); 6564 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6565 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6566 e->u.wr.wrhdr[i]); 6567 log(LOG_ERR, "\n"); 6568 break; 6569 case FW_ERROR_TYPE_ACL: 6570 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6571 be16toh(e->u.acl.cidx), 6572 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6573 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6574 be32toh(e->u.acl.eqid), 6575 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6576 "MAC"); 6577 for (i = 0; i < nitems(e->u.acl.val); i++) 6578 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6579 log(LOG_ERR, "\n"); 6580 break; 6581 default: 6582 log(LOG_ERR, "type %#x\n", 6583 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6584 return (EINVAL); 6585 } 6586 return (0); 6587 } 6588 6589 static inline bool 6590 bufidx_used(struct adapter *sc, int idx) 6591 { 6592 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6593 int i; 6594 6595 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6596 if (rxb->size1 > largest_rx_cluster) 6597 continue; 6598 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6599 return (true); 6600 } 6601 6602 return (false); 6603 } 6604 6605 static int 6606 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6607 { 6608 struct adapter *sc = arg1; 6609 struct sge_params *sp = &sc->params.sge; 6610 int i, rc; 6611 struct sbuf sb; 6612 char c; 6613 6614 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6615 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6616 if (bufidx_used(sc, i)) 6617 c = '*'; 6618 else 6619 c = '\0'; 6620 6621 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6622 } 6623 sbuf_trim(&sb); 6624 sbuf_finish(&sb); 6625 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6626 sbuf_delete(&sb); 6627 return (rc); 6628 } 6629 6630 #ifdef RATELIMIT 6631 #if defined(INET) || defined(INET6) 6632 /* 6633 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6634 */ 6635 static inline u_int 6636 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6637 { 6638 u_int n; 6639 6640 MPASS(immhdrs > 0); 6641 6642 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6643 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6644 if (__predict_false(nsegs == 0)) 6645 goto done; 6646 6647 nsegs--; /* first segment is part of ulptx_sgl */ 6648 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6649 if (tso) 6650 n += sizeof(struct cpl_tx_pkt_lso_core); 6651 6652 done: 6653 return (howmany(n, 16)); 6654 } 6655 #endif 6656 6657 #define ETID_FLOWC_NPARAMS 6 6658 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6659 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6660 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6661 6662 #if defined(INET) || defined(INET6) 6663 static int 6664 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6665 struct vi_info *vi) 6666 { 6667 struct wrq_cookie cookie; 6668 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6669 struct fw_flowc_wr *flowc; 6670 6671 mtx_assert(&cst->lock, MA_OWNED); 6672 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6673 EO_FLOWC_PENDING); 6674 6675 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6676 if (__predict_false(flowc == NULL)) 6677 return (ENOMEM); 6678 6679 bzero(flowc, ETID_FLOWC_LEN); 6680 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6681 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6682 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6683 V_FW_WR_FLOWID(cst->etid)); 6684 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6685 flowc->mnemval[0].val = htobe32(pfvf); 6686 /* Firmware expects hw port and will translate to channel itself. */ 6687 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6688 flowc->mnemval[1].val = htobe32(pi->hw_port); 6689 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6690 flowc->mnemval[2].val = htobe32(pi->hw_port); 6691 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6692 flowc->mnemval[3].val = htobe32(cst->iqid); 6693 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6694 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6695 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6696 flowc->mnemval[5].val = htobe32(cst->schedcl); 6697 6698 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6699 6700 cst->flags &= ~EO_FLOWC_PENDING; 6701 cst->flags |= EO_FLOWC_RPL_PENDING; 6702 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6703 cst->tx_credits -= ETID_FLOWC_LEN16; 6704 6705 return (0); 6706 } 6707 #endif 6708 6709 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6710 6711 void 6712 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6713 { 6714 struct fw_flowc_wr *flowc; 6715 struct wrq_cookie cookie; 6716 6717 mtx_assert(&cst->lock, MA_OWNED); 6718 6719 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6720 if (__predict_false(flowc == NULL)) 6721 CXGBE_UNIMPLEMENTED(__func__); 6722 6723 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6724 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6725 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6726 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6727 V_FW_WR_FLOWID(cst->etid)); 6728 6729 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6730 6731 cst->flags |= EO_FLUSH_RPL_PENDING; 6732 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6733 cst->tx_credits -= ETID_FLUSH_LEN16; 6734 cst->ncompl++; 6735 } 6736 6737 static void 6738 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6739 struct mbuf *m0, int compl) 6740 { 6741 struct cpl_tx_pkt_core *cpl; 6742 uint64_t ctrl1; 6743 uint32_t ctrl; /* used in many unrelated places */ 6744 int len16, pktlen, nsegs, immhdrs; 6745 uintptr_t p; 6746 struct ulptx_sgl *usgl; 6747 struct sglist sg; 6748 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6749 6750 mtx_assert(&cst->lock, MA_OWNED); 6751 M_ASSERTPKTHDR(m0); 6752 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6753 m0->m_pkthdr.l4hlen > 0, 6754 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6755 6756 len16 = mbuf_eo_len16(m0); 6757 nsegs = mbuf_eo_nsegs(m0); 6758 pktlen = m0->m_pkthdr.len; 6759 ctrl = sizeof(struct cpl_tx_pkt_core); 6760 if (needs_tso(m0)) 6761 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6762 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6763 ctrl += immhdrs; 6764 6765 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6766 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6767 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6768 V_FW_WR_FLOWID(cst->etid)); 6769 wr->r3 = 0; 6770 if (needs_outer_udp_csum(m0)) { 6771 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6772 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6773 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6774 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6775 wr->u.udpseg.rtplen = 0; 6776 wr->u.udpseg.r4 = 0; 6777 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6778 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6779 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6780 cpl = (void *)(wr + 1); 6781 } else { 6782 MPASS(needs_outer_tcp_csum(m0)); 6783 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6784 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6785 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6786 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6787 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6788 wr->u.tcpseg.r4 = 0; 6789 wr->u.tcpseg.r5 = 0; 6790 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6791 6792 if (needs_tso(m0)) { 6793 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6794 6795 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6796 6797 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6798 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6799 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6800 ETHER_HDR_LEN) >> 2) | 6801 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6802 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6803 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6804 ctrl |= F_LSO_IPV6; 6805 lso->lso_ctrl = htobe32(ctrl); 6806 lso->ipid_ofst = htobe16(0); 6807 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6808 lso->seqno_offset = htobe32(0); 6809 lso->len = htobe32(pktlen); 6810 6811 cpl = (void *)(lso + 1); 6812 } else { 6813 wr->u.tcpseg.mss = htobe16(0xffff); 6814 cpl = (void *)(wr + 1); 6815 } 6816 } 6817 6818 /* Checksum offload must be requested for ethofld. */ 6819 MPASS(needs_outer_l4_csum(m0)); 6820 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6821 6822 /* VLAN tag insertion */ 6823 if (needs_vlan_insertion(m0)) { 6824 ctrl1 |= F_TXPKT_VLAN_VLD | 6825 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6826 } 6827 6828 /* CPL header */ 6829 cpl->ctrl0 = cst->ctrl0; 6830 cpl->pack = 0; 6831 cpl->len = htobe16(pktlen); 6832 cpl->ctrl1 = htobe64(ctrl1); 6833 6834 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6835 p = (uintptr_t)(cpl + 1); 6836 m_copydata(m0, 0, immhdrs, (void *)p); 6837 6838 /* SGL */ 6839 if (nsegs > 0) { 6840 int i, pad; 6841 6842 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6843 p += immhdrs; 6844 pad = 16 - (immhdrs & 0xf); 6845 bzero((void *)p, pad); 6846 6847 usgl = (void *)(p + pad); 6848 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6849 V_ULPTX_NSGE(nsegs)); 6850 6851 sglist_init(&sg, nitems(segs), segs); 6852 for (; m0 != NULL; m0 = m0->m_next) { 6853 if (__predict_false(m0->m_len == 0)) 6854 continue; 6855 if (immhdrs >= m0->m_len) { 6856 immhdrs -= m0->m_len; 6857 continue; 6858 } 6859 if (m0->m_flags & M_EXTPG) 6860 sglist_append_mbuf_epg(&sg, m0, 6861 mtod(m0, vm_offset_t), m0->m_len); 6862 else 6863 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6864 m0->m_len - immhdrs); 6865 immhdrs = 0; 6866 } 6867 MPASS(sg.sg_nseg == nsegs); 6868 6869 /* 6870 * Zero pad last 8B in case the WR doesn't end on a 16B 6871 * boundary. 6872 */ 6873 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6874 6875 usgl->len0 = htobe32(segs[0].ss_len); 6876 usgl->addr0 = htobe64(segs[0].ss_paddr); 6877 for (i = 0; i < nsegs - 1; i++) { 6878 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6879 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6880 } 6881 if (i & 1) 6882 usgl->sge[i / 2].len[1] = htobe32(0); 6883 } 6884 6885 } 6886 6887 static void 6888 ethofld_tx(struct cxgbe_rate_tag *cst) 6889 { 6890 struct mbuf *m; 6891 struct wrq_cookie cookie; 6892 int next_credits, compl; 6893 struct fw_eth_tx_eo_wr *wr; 6894 6895 mtx_assert(&cst->lock, MA_OWNED); 6896 6897 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6898 M_ASSERTPKTHDR(m); 6899 6900 /* How many len16 credits do we need to send this mbuf. */ 6901 next_credits = mbuf_eo_len16(m); 6902 MPASS(next_credits > 0); 6903 if (next_credits > cst->tx_credits) { 6904 /* 6905 * Tx will make progress eventually because there is at 6906 * least one outstanding fw4_ack that will return 6907 * credits and kick the tx. 6908 */ 6909 MPASS(cst->ncompl > 0); 6910 return; 6911 } 6912 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6913 if (__predict_false(wr == NULL)) { 6914 /* XXX: wishful thinking, not a real assertion. */ 6915 MPASS(cst->ncompl > 0); 6916 return; 6917 } 6918 cst->tx_credits -= next_credits; 6919 cst->tx_nocompl += next_credits; 6920 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6921 ETHER_BPF_MTAP(cst->com.ifp, m); 6922 write_ethofld_wr(cst, wr, m, compl); 6923 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6924 if (compl) { 6925 cst->ncompl++; 6926 cst->tx_nocompl = 0; 6927 } 6928 (void) mbufq_dequeue(&cst->pending_tx); 6929 6930 /* 6931 * Drop the mbuf's reference on the tag now rather 6932 * than waiting until m_freem(). This ensures that 6933 * cxgbe_rate_tag_free gets called when the inp drops 6934 * its reference on the tag and there are no more 6935 * mbufs in the pending_tx queue and can flush any 6936 * pending requests. Otherwise if the last mbuf 6937 * doesn't request a completion the etid will never be 6938 * released. 6939 */ 6940 m->m_pkthdr.snd_tag = NULL; 6941 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6942 m_snd_tag_rele(&cst->com); 6943 6944 mbufq_enqueue(&cst->pending_fwack, m); 6945 } 6946 } 6947 6948 #if defined(INET) || defined(INET6) 6949 static int 6950 ethofld_transmit(if_t ifp, struct mbuf *m0) 6951 { 6952 struct cxgbe_rate_tag *cst; 6953 int rc; 6954 6955 MPASS(m0->m_nextpkt == NULL); 6956 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6957 MPASS(m0->m_pkthdr.snd_tag != NULL); 6958 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6959 6960 mtx_lock(&cst->lock); 6961 MPASS(cst->flags & EO_SND_TAG_REF); 6962 6963 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6964 struct vi_info *vi = if_getsoftc(ifp); 6965 struct port_info *pi = vi->pi; 6966 struct adapter *sc = pi->adapter; 6967 const uint32_t rss_mask = vi->rss_size - 1; 6968 uint32_t rss_hash; 6969 6970 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6971 if (M_HASHTYPE_ISHASH(m0)) 6972 rss_hash = m0->m_pkthdr.flowid; 6973 else 6974 rss_hash = arc4random(); 6975 /* We assume RSS hashing */ 6976 cst->iqid = vi->rss[rss_hash & rss_mask]; 6977 cst->eo_txq += rss_hash % vi->nofldtxq; 6978 rc = send_etid_flowc_wr(cst, pi, vi); 6979 if (rc != 0) 6980 goto done; 6981 } 6982 6983 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6984 rc = ENOBUFS; 6985 goto done; 6986 } 6987 6988 mbufq_enqueue(&cst->pending_tx, m0); 6989 cst->plen += m0->m_pkthdr.len; 6990 6991 /* 6992 * Hold an extra reference on the tag while generating work 6993 * requests to ensure that we don't try to free the tag during 6994 * ethofld_tx() in case we are sending the final mbuf after 6995 * the inp was freed. 6996 */ 6997 m_snd_tag_ref(&cst->com); 6998 ethofld_tx(cst); 6999 mtx_unlock(&cst->lock); 7000 m_snd_tag_rele(&cst->com); 7001 return (0); 7002 7003 done: 7004 mtx_unlock(&cst->lock); 7005 return (rc); 7006 } 7007 #endif 7008 7009 static int 7010 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 7011 { 7012 struct adapter *sc = iq->adapter; 7013 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 7014 struct mbuf *m; 7015 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 7016 struct cxgbe_rate_tag *cst; 7017 uint8_t credits = cpl->credits; 7018 7019 cst = lookup_etid(sc, etid); 7020 mtx_lock(&cst->lock); 7021 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 7022 MPASS(credits >= ETID_FLOWC_LEN16); 7023 credits -= ETID_FLOWC_LEN16; 7024 cst->flags &= ~EO_FLOWC_RPL_PENDING; 7025 } 7026 7027 KASSERT(cst->ncompl > 0, 7028 ("%s: etid %u (%p) wasn't expecting completion.", 7029 __func__, etid, cst)); 7030 cst->ncompl--; 7031 7032 while (credits > 0) { 7033 m = mbufq_dequeue(&cst->pending_fwack); 7034 if (__predict_false(m == NULL)) { 7035 /* 7036 * The remaining credits are for the final flush that 7037 * was issued when the tag was freed by the kernel. 7038 */ 7039 MPASS((cst->flags & 7040 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 7041 EO_FLUSH_RPL_PENDING); 7042 MPASS(credits == ETID_FLUSH_LEN16); 7043 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 7044 MPASS(cst->ncompl == 0); 7045 7046 cst->flags &= ~EO_FLUSH_RPL_PENDING; 7047 cst->tx_credits += cpl->credits; 7048 cxgbe_rate_tag_free_locked(cst); 7049 return (0); /* cst is gone. */ 7050 } 7051 KASSERT(m != NULL, 7052 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 7053 credits)); 7054 KASSERT(credits >= mbuf_eo_len16(m), 7055 ("%s: too few credits (%u, %u, %u)", __func__, 7056 cpl->credits, credits, mbuf_eo_len16(m))); 7057 credits -= mbuf_eo_len16(m); 7058 cst->plen -= m->m_pkthdr.len; 7059 m_freem(m); 7060 } 7061 7062 cst->tx_credits += cpl->credits; 7063 MPASS(cst->tx_credits <= cst->tx_total); 7064 7065 if (cst->flags & EO_SND_TAG_REF) { 7066 /* 7067 * As with ethofld_transmit(), hold an extra reference 7068 * so that the tag is stable across ethold_tx(). 7069 */ 7070 m_snd_tag_ref(&cst->com); 7071 m = mbufq_first(&cst->pending_tx); 7072 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 7073 ethofld_tx(cst); 7074 mtx_unlock(&cst->lock); 7075 m_snd_tag_rele(&cst->com); 7076 } else { 7077 /* 7078 * There shouldn't be any pending packets if the tag 7079 * was freed by the kernel since any pending packet 7080 * should hold a reference to the tag. 7081 */ 7082 MPASS(mbufq_first(&cst->pending_tx) == NULL); 7083 mtx_unlock(&cst->lock); 7084 } 7085 7086 return (0); 7087 } 7088 #endif 7089