1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
62
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
71
72 #include <dev/ale/if_alereg.h>
73 #include <dev/ale/if_alevar.h>
74
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
77
78 /* For more information about Tx checksum offload issues see ale_encap(). */
79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
80
81 MODULE_DEPEND(ale, pci, 1, 1, 1);
82 MODULE_DEPEND(ale, ether, 1, 1, 1);
83 MODULE_DEPEND(ale, miibus, 1, 1, 1);
84
85 /* Tunables. */
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
90
91 /*
92 * Devices supported by this driver.
93 */
94 static const struct ale_dev {
95 uint16_t ale_vendorid;
96 uint16_t ale_deviceid;
97 const char *ale_name;
98 } ale_devs[] = {
99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
101 };
102
103 static int ale_attach(device_t);
104 static int ale_check_boundary(struct ale_softc *);
105 static int ale_detach(device_t);
106 static int ale_dma_alloc(struct ale_softc *);
107 static void ale_dma_free(struct ale_softc *);
108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
109 static int ale_encap(struct ale_softc *, struct mbuf **);
110 static void ale_get_macaddr(struct ale_softc *);
111 static void ale_init(void *);
112 static void ale_init_locked(struct ale_softc *);
113 static void ale_init_rx_pages(struct ale_softc *);
114 static void ale_init_tx_ring(struct ale_softc *);
115 static void ale_int_task(void *, int);
116 static int ale_intr(void *);
117 static int ale_ioctl(if_t, u_long, caddr_t);
118 static void ale_mac_config(struct ale_softc *);
119 static int ale_miibus_readreg(device_t, int, int);
120 static void ale_miibus_statchg(device_t);
121 static int ale_miibus_writereg(device_t, int, int, int);
122 static int ale_mediachange(if_t);
123 static void ale_mediastatus(if_t, struct ifmediareq *);
124 static void ale_phy_reset(struct ale_softc *);
125 static int ale_probe(device_t);
126 static void ale_reset(struct ale_softc *);
127 static int ale_resume(device_t);
128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
129 uint32_t, uint32_t *);
130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
131 static int ale_rxeof(struct ale_softc *sc, int);
132 static void ale_rxfilter(struct ale_softc *);
133 static void ale_rxvlan(struct ale_softc *);
134 static void ale_setlinkspeed(struct ale_softc *);
135 static void ale_setwol(struct ale_softc *);
136 static int ale_shutdown(device_t);
137 static void ale_start(if_t);
138 static void ale_start_locked(if_t);
139 static void ale_stats_clear(struct ale_softc *);
140 static void ale_stats_update(struct ale_softc *);
141 static void ale_stop(struct ale_softc *);
142 static void ale_stop_mac(struct ale_softc *);
143 static int ale_suspend(device_t);
144 static void ale_sysctl_node(struct ale_softc *);
145 static void ale_tick(void *);
146 static void ale_txeof(struct ale_softc *);
147 static void ale_watchdog(struct ale_softc *);
148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
151
152 static device_method_t ale_methods[] = {
153 /* Device interface. */
154 DEVMETHOD(device_probe, ale_probe),
155 DEVMETHOD(device_attach, ale_attach),
156 DEVMETHOD(device_detach, ale_detach),
157 DEVMETHOD(device_shutdown, ale_shutdown),
158 DEVMETHOD(device_suspend, ale_suspend),
159 DEVMETHOD(device_resume, ale_resume),
160
161 /* MII interface. */
162 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
163 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
164 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
165
166 DEVMETHOD_END
167 };
168
169 static driver_t ale_driver = {
170 "ale",
171 ale_methods,
172 sizeof(struct ale_softc)
173 };
174
175 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL);
176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs,
177 nitems(ale_devs));
178 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL);
179
180 static struct resource_spec ale_res_spec_mem[] = {
181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
182 { -1, 0, 0 }
183 };
184
185 static struct resource_spec ale_irq_spec_legacy[] = {
186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
187 { -1, 0, 0 }
188 };
189
190 static struct resource_spec ale_irq_spec_msi[] = {
191 { SYS_RES_IRQ, 1, RF_ACTIVE },
192 { -1, 0, 0 }
193 };
194
195 static struct resource_spec ale_irq_spec_msix[] = {
196 { SYS_RES_IRQ, 1, RF_ACTIVE },
197 { -1, 0, 0 }
198 };
199
200 static int
ale_miibus_readreg(device_t dev,int phy,int reg)201 ale_miibus_readreg(device_t dev, int phy, int reg)
202 {
203 struct ale_softc *sc;
204 uint32_t v;
205 int i;
206
207 sc = device_get_softc(dev);
208
209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
212 DELAY(5);
213 v = CSR_READ_4(sc, ALE_MDIO);
214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
215 break;
216 }
217
218 if (i == 0) {
219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
220 return (0);
221 }
222
223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
224 }
225
226 static int
ale_miibus_writereg(device_t dev,int phy,int reg,int val)227 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
228 {
229 struct ale_softc *sc;
230 uint32_t v;
231 int i;
232
233 sc = device_get_softc(dev);
234
235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
239 DELAY(5);
240 v = CSR_READ_4(sc, ALE_MDIO);
241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
242 break;
243 }
244
245 if (i == 0)
246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
247
248 return (0);
249 }
250
251 static void
ale_miibus_statchg(device_t dev)252 ale_miibus_statchg(device_t dev)
253 {
254 struct ale_softc *sc;
255 struct mii_data *mii;
256 if_t ifp;
257 uint32_t reg;
258
259 sc = device_get_softc(dev);
260 mii = device_get_softc(sc->ale_miibus);
261 ifp = sc->ale_ifp;
262 if (mii == NULL || ifp == NULL ||
263 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
264 return;
265
266 sc->ale_flags &= ~ALE_FLAG_LINK;
267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
268 (IFM_ACTIVE | IFM_AVALID)) {
269 switch (IFM_SUBTYPE(mii->mii_media_active)) {
270 case IFM_10_T:
271 case IFM_100_TX:
272 sc->ale_flags |= ALE_FLAG_LINK;
273 break;
274 case IFM_1000_T:
275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
276 sc->ale_flags |= ALE_FLAG_LINK;
277 break;
278 default:
279 break;
280 }
281 }
282
283 /* Stop Rx/Tx MACs. */
284 ale_stop_mac(sc);
285
286 /* Program MACs with resolved speed/duplex/flow-control. */
287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
288 ale_mac_config(sc);
289 /* Reenable Tx/Rx MACs. */
290 reg = CSR_READ_4(sc, ALE_MAC_CFG);
291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
293 }
294 }
295
296 static void
ale_mediastatus(if_t ifp,struct ifmediareq * ifmr)297 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr)
298 {
299 struct ale_softc *sc;
300 struct mii_data *mii;
301
302 sc = if_getsoftc(ifp);
303 ALE_LOCK(sc);
304 if ((if_getflags(ifp) & IFF_UP) == 0) {
305 ALE_UNLOCK(sc);
306 return;
307 }
308 mii = device_get_softc(sc->ale_miibus);
309
310 mii_pollstat(mii);
311 ifmr->ifm_status = mii->mii_media_status;
312 ifmr->ifm_active = mii->mii_media_active;
313 ALE_UNLOCK(sc);
314 }
315
316 static int
ale_mediachange(if_t ifp)317 ale_mediachange(if_t ifp)
318 {
319 struct ale_softc *sc;
320 struct mii_data *mii;
321 struct mii_softc *miisc;
322 int error;
323
324 sc = if_getsoftc(ifp);
325 ALE_LOCK(sc);
326 mii = device_get_softc(sc->ale_miibus);
327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
328 PHY_RESET(miisc);
329 error = mii_mediachg(mii);
330 ALE_UNLOCK(sc);
331
332 return (error);
333 }
334
335 static int
ale_probe(device_t dev)336 ale_probe(device_t dev)
337 {
338 const struct ale_dev *sp;
339 int i;
340 uint16_t vendor, devid;
341
342 vendor = pci_get_vendor(dev);
343 devid = pci_get_device(dev);
344 sp = ale_devs;
345 for (i = 0; i < nitems(ale_devs); i++) {
346 if (vendor == sp->ale_vendorid &&
347 devid == sp->ale_deviceid) {
348 device_set_desc(dev, sp->ale_name);
349 return (BUS_PROBE_DEFAULT);
350 }
351 sp++;
352 }
353
354 return (ENXIO);
355 }
356
357 static void
ale_get_macaddr(struct ale_softc * sc)358 ale_get_macaddr(struct ale_softc *sc)
359 {
360 uint32_t ea[2], reg;
361 int i, vpdc;
362
363 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
364 if ((reg & SPI_VPD_ENB) != 0) {
365 reg &= ~SPI_VPD_ENB;
366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
367 }
368
369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
370 /*
371 * PCI VPD capability found, let TWSI reload EEPROM.
372 * This will set ethernet address of controller.
373 */
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
375 TWSI_CTRL_SW_LD_START);
376 for (i = 100; i > 0; i--) {
377 DELAY(1000);
378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
379 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
380 break;
381 }
382 if (i == 0)
383 device_printf(sc->ale_dev,
384 "reloading EEPROM timeout!\n");
385 } else {
386 if (bootverbose)
387 device_printf(sc->ale_dev,
388 "PCI VPD capability not found!\n");
389 }
390
391 ea[0] = CSR_READ_4(sc, ALE_PAR0);
392 ea[1] = CSR_READ_4(sc, ALE_PAR1);
393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
399 }
400
401 static void
ale_phy_reset(struct ale_softc * sc)402 ale_phy_reset(struct ale_softc *sc)
403 {
404
405 /* Reset magic from Linux. */
406 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
408 GPHY_CTRL_PHY_PLL_ON);
409 DELAY(1000);
410 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
413 DELAY(1000);
414
415 #define ATPHY_DBG_ADDR 0x1D
416 #define ATPHY_DBG_DATA 0x1E
417
418 /* Enable hibernation mode. */
419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
420 ATPHY_DBG_ADDR, 0x0B);
421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
422 ATPHY_DBG_DATA, 0xBC00);
423 /* Set Class A/B for all modes. */
424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
425 ATPHY_DBG_ADDR, 0x00);
426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
427 ATPHY_DBG_DATA, 0x02EF);
428 /* Enable 10BT power saving. */
429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
430 ATPHY_DBG_ADDR, 0x12);
431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
432 ATPHY_DBG_DATA, 0x4C04);
433 /* Adjust 1000T power. */
434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
435 ATPHY_DBG_ADDR, 0x04);
436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
437 ATPHY_DBG_ADDR, 0x8BBB);
438 /* 10BT center tap voltage. */
439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
440 ATPHY_DBG_ADDR, 0x05);
441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
442 ATPHY_DBG_ADDR, 0x2C46);
443
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
446 DELAY(1000);
447 }
448
449 static int
ale_attach(device_t dev)450 ale_attach(device_t dev)
451 {
452 struct ale_softc *sc;
453 if_t ifp;
454 uint16_t burst;
455 int error, i, msic, msixc, pmc;
456 uint32_t rxf_len, txf_len;
457
458 error = 0;
459 sc = device_get_softc(dev);
460 sc->ale_dev = dev;
461
462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
463 MTX_DEF);
464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
465 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
466
467 /* Map the device. */
468 pci_enable_busmaster(dev);
469 sc->ale_res_spec = ale_res_spec_mem;
470 sc->ale_irq_spec = ale_irq_spec_legacy;
471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
472 if (error != 0) {
473 device_printf(dev, "cannot allocate memory resources.\n");
474 goto fail;
475 }
476
477 /* Set PHY address. */
478 sc->ale_phyaddr = ALE_PHY_ADDR;
479
480 /* Reset PHY. */
481 ale_phy_reset(sc);
482
483 /* Reset the ethernet controller. */
484 ale_reset(sc);
485
486 /* Get PCI and chip id/revision. */
487 sc->ale_rev = pci_get_revid(dev);
488 if (sc->ale_rev >= 0xF0) {
489 /* L2E Rev. B. AR8114 */
490 sc->ale_flags |= ALE_FLAG_FASTETHER;
491 } else {
492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
493 /* L1E AR8121 */
494 sc->ale_flags |= ALE_FLAG_JUMBO;
495 } else {
496 /* L2E Rev. A. AR8113 */
497 sc->ale_flags |= ALE_FLAG_FASTETHER;
498 }
499 }
500 /*
501 * All known controllers seems to require 4 bytes alignment
502 * of Tx buffers to make Tx checksum offload with custom
503 * checksum generation method work.
504 */
505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
506 /*
507 * All known controllers seems to have issues on Rx checksum
508 * offload for fragmented IP datagrams.
509 */
510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
511 /*
512 * Don't use Tx CMB. It is known to cause RRS update failure
513 * under certain circumstances. Typical phenomenon of the
514 * issue would be unexpected sequence number encountered in
515 * Rx handler.
516 */
517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
519 MASTER_CHIP_REV_SHIFT;
520 if (bootverbose) {
521 device_printf(dev, "PCI device revision : 0x%04x\n",
522 sc->ale_rev);
523 device_printf(dev, "Chip id/revision : 0x%04x\n",
524 sc->ale_chip_rev);
525 }
526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
528 /*
529 * Uninitialized hardware returns an invalid chip id/revision
530 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
531 */
532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
533 rxf_len == 0xFFFFFFF) {
534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
536 txf_len, rxf_len);
537 error = ENXIO;
538 goto fail;
539 }
540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
541
542 /* Allocate IRQ resources. */
543 msixc = pci_msix_count(dev);
544 msic = pci_msi_count(dev);
545 if (bootverbose) {
546 device_printf(dev, "MSIX count : %d\n", msixc);
547 device_printf(dev, "MSI count : %d\n", msic);
548 }
549
550 /* Prefer MSIX over MSI. */
551 if (msix_disable == 0 || msi_disable == 0) {
552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
553 pci_alloc_msix(dev, &msixc) == 0) {
554 if (msixc == ALE_MSIX_MESSAGES) {
555 device_printf(dev, "Using %d MSIX messages.\n",
556 msixc);
557 sc->ale_flags |= ALE_FLAG_MSIX;
558 sc->ale_irq_spec = ale_irq_spec_msix;
559 } else
560 pci_release_msi(dev);
561 }
562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
563 msic == ALE_MSI_MESSAGES &&
564 pci_alloc_msi(dev, &msic) == 0) {
565 if (msic == ALE_MSI_MESSAGES) {
566 device_printf(dev, "Using %d MSI messages.\n",
567 msic);
568 sc->ale_flags |= ALE_FLAG_MSI;
569 sc->ale_irq_spec = ale_irq_spec_msi;
570 } else
571 pci_release_msi(dev);
572 }
573 }
574
575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
576 if (error != 0) {
577 device_printf(dev, "cannot allocate IRQ resources.\n");
578 goto fail;
579 }
580
581 /* Get DMA parameters from PCIe device control register. */
582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
583 sc->ale_flags |= ALE_FLAG_PCIE;
584 burst = pci_read_config(dev, i + 0x08, 2);
585 /* Max read request size. */
586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
587 DMA_CFG_RD_BURST_SHIFT;
588 /* Max payload size. */
589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
590 DMA_CFG_WR_BURST_SHIFT;
591 if (bootverbose) {
592 device_printf(dev, "Read request size : %d bytes.\n",
593 128 << ((burst >> 12) & 0x07));
594 device_printf(dev, "TLP payload size : %d bytes.\n",
595 128 << ((burst >> 5) & 0x07));
596 }
597 } else {
598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
600 }
601
602 /* Create device sysctl node. */
603 ale_sysctl_node(sc);
604
605 if ((error = ale_dma_alloc(sc)) != 0)
606 goto fail;
607
608 /* Load station address. */
609 ale_get_macaddr(sc);
610
611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
612 if_setsoftc(ifp, sc);
613 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
614 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
615 if_setioctlfn(ifp, ale_ioctl);
616 if_setstartfn(ifp, ale_start);
617 if_setinitfn(ifp, ale_init);
618 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1);
619 if_setsendqready(ifp);
620 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4);
621 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO);
622 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
623 sc->ale_flags |= ALE_FLAG_PMCAP;
624 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
625 }
626 if_setcapenable(ifp, if_getcapabilities(ifp));
627
628 /* Set up MII bus. */
629 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
630 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
631 MIIF_DOPAUSE);
632 if (error != 0) {
633 device_printf(dev, "attaching PHYs failed\n");
634 goto fail;
635 }
636
637 ether_ifattach(ifp, sc->ale_eaddr);
638
639 /* VLAN capability setup. */
640 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
641 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
642 if_setcapenable(ifp, if_getcapabilities(ifp));
643 /*
644 * Even though controllers supported by ale(3) have Rx checksum
645 * offload bug the workaround for fragmented frames seemed to
646 * work so far. However it seems Rx checksum offload does not
647 * work under certain conditions. So disable Rx checksum offload
648 * until I find more clue about it but allow users to override it.
649 */
650 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
651
652 /* Tell the upper layer(s) we support long frames. */
653 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
654
655 /* Create local taskq. */
656 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
657 taskqueue_thread_enqueue, &sc->ale_tq);
658 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
659 device_get_nameunit(sc->ale_dev));
660
661 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
662 msic = ALE_MSIX_MESSAGES;
663 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
664 msic = ALE_MSI_MESSAGES;
665 else
666 msic = 1;
667 for (i = 0; i < msic; i++) {
668 error = bus_setup_intr(dev, sc->ale_irq[i],
669 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
670 &sc->ale_intrhand[i]);
671 if (error != 0)
672 break;
673 }
674 if (error != 0) {
675 device_printf(dev, "could not set up interrupt handler.\n");
676 taskqueue_free(sc->ale_tq);
677 sc->ale_tq = NULL;
678 ether_ifdetach(ifp);
679 goto fail;
680 }
681
682 fail:
683 if (error != 0)
684 ale_detach(dev);
685
686 return (error);
687 }
688
689 static int
ale_detach(device_t dev)690 ale_detach(device_t dev)
691 {
692 struct ale_softc *sc;
693 if_t ifp;
694 int i, msic;
695
696 sc = device_get_softc(dev);
697
698 ifp = sc->ale_ifp;
699 if (device_is_attached(dev)) {
700 ether_ifdetach(ifp);
701 ALE_LOCK(sc);
702 ale_stop(sc);
703 ALE_UNLOCK(sc);
704 callout_drain(&sc->ale_tick_ch);
705 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
706 }
707
708 if (sc->ale_tq != NULL) {
709 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
710 taskqueue_free(sc->ale_tq);
711 sc->ale_tq = NULL;
712 }
713
714 if (sc->ale_miibus != NULL) {
715 device_delete_child(dev, sc->ale_miibus);
716 sc->ale_miibus = NULL;
717 }
718 bus_generic_detach(dev);
719 ale_dma_free(sc);
720
721 if (ifp != NULL) {
722 if_free(ifp);
723 sc->ale_ifp = NULL;
724 }
725
726 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
727 msic = ALE_MSIX_MESSAGES;
728 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
729 msic = ALE_MSI_MESSAGES;
730 else
731 msic = 1;
732 for (i = 0; i < msic; i++) {
733 if (sc->ale_intrhand[i] != NULL) {
734 bus_teardown_intr(dev, sc->ale_irq[i],
735 sc->ale_intrhand[i]);
736 sc->ale_intrhand[i] = NULL;
737 }
738 }
739
740 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
741 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
742 pci_release_msi(dev);
743 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
744 mtx_destroy(&sc->ale_mtx);
745
746 return (0);
747 }
748
749 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
750 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
751
752 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
753 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
754
755 static void
ale_sysctl_node(struct ale_softc * sc)756 ale_sysctl_node(struct ale_softc *sc)
757 {
758 struct sysctl_ctx_list *ctx;
759 struct sysctl_oid_list *child, *parent;
760 struct sysctl_oid *tree;
761 struct ale_hw_stats *stats;
762 int error;
763
764 stats = &sc->ale_stats;
765 ctx = device_get_sysctl_ctx(sc->ale_dev);
766 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
767
768 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
769 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod,
770 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
771 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
772 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod,
773 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
774 /* Pull in device tunables. */
775 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
776 error = resource_int_value(device_get_name(sc->ale_dev),
777 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
778 if (error == 0) {
779 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
780 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
781 device_printf(sc->ale_dev, "int_rx_mod value out of "
782 "range; using default: %d\n",
783 ALE_IM_RX_TIMER_DEFAULT);
784 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
785 }
786 }
787 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
788 error = resource_int_value(device_get_name(sc->ale_dev),
789 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
790 if (error == 0) {
791 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
792 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
793 device_printf(sc->ale_dev, "int_tx_mod value out of "
794 "range; using default: %d\n",
795 ALE_IM_TX_TIMER_DEFAULT);
796 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
797 }
798 }
799 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
800 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
801 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I",
802 "max number of Rx events to process");
803 /* Pull in device tunables. */
804 sc->ale_process_limit = ALE_PROC_DEFAULT;
805 error = resource_int_value(device_get_name(sc->ale_dev),
806 device_get_unit(sc->ale_dev), "process_limit",
807 &sc->ale_process_limit);
808 if (error == 0) {
809 if (sc->ale_process_limit < ALE_PROC_MIN ||
810 sc->ale_process_limit > ALE_PROC_MAX) {
811 device_printf(sc->ale_dev,
812 "process_limit value out of range; "
813 "using default: %d\n", ALE_PROC_DEFAULT);
814 sc->ale_process_limit = ALE_PROC_DEFAULT;
815 }
816 }
817
818 /* Misc statistics. */
819 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
820 &stats->reset_brk_seq,
821 "Controller resets due to broken Rx sequnce number");
822
823 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
824 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics");
825 parent = SYSCTL_CHILDREN(tree);
826
827 /* Rx statistics. */
828 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
829 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
830 child = SYSCTL_CHILDREN(tree);
831 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
832 &stats->rx_frames, "Good frames");
833 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
834 &stats->rx_bcast_frames, "Good broadcast frames");
835 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
836 &stats->rx_mcast_frames, "Good multicast frames");
837 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
838 &stats->rx_pause_frames, "Pause control frames");
839 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
840 &stats->rx_control_frames, "Control frames");
841 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
842 &stats->rx_crcerrs, "CRC errors");
843 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
844 &stats->rx_lenerrs, "Frames with length mismatched");
845 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
846 &stats->rx_bytes, "Good octets");
847 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
848 &stats->rx_bcast_bytes, "Good broadcast octets");
849 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
850 &stats->rx_mcast_bytes, "Good multicast octets");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
852 &stats->rx_runts, "Too short frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
854 &stats->rx_fragments, "Fragmented frames");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
856 &stats->rx_pkts_64, "64 bytes frames");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
858 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
860 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
862 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
864 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
866 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
867 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
868 &stats->rx_pkts_1519_max, "1519 to max frames");
869 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
870 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
871 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
872 &stats->rx_fifo_oflows, "FIFO overflows");
873 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
874 &stats->rx_rrs_errs, "Return status write-back errors");
875 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
876 &stats->rx_alignerrs, "Alignment errors");
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
878 &stats->rx_pkts_filtered,
879 "Frames dropped due to address filtering");
880
881 /* Tx statistics. */
882 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
883 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
884 child = SYSCTL_CHILDREN(tree);
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
886 &stats->tx_frames, "Good frames");
887 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
888 &stats->tx_bcast_frames, "Good broadcast frames");
889 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
890 &stats->tx_mcast_frames, "Good multicast frames");
891 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
892 &stats->tx_pause_frames, "Pause control frames");
893 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
894 &stats->tx_control_frames, "Control frames");
895 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
896 &stats->tx_excess_defer, "Frames with excessive derferrals");
897 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
898 &stats->tx_excess_defer, "Frames with derferrals");
899 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
900 &stats->tx_bytes, "Good octets");
901 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
902 &stats->tx_bcast_bytes, "Good broadcast octets");
903 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
904 &stats->tx_mcast_bytes, "Good multicast octets");
905 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
906 &stats->tx_pkts_64, "64 bytes frames");
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
908 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
910 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
911 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
912 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
913 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
914 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
915 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
916 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
917 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
918 &stats->tx_pkts_1519_max, "1519 to max frames");
919 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
920 &stats->tx_single_colls, "Single collisions");
921 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
922 &stats->tx_multi_colls, "Multiple collisions");
923 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
924 &stats->tx_late_colls, "Late collisions");
925 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
926 &stats->tx_excess_colls, "Excessive collisions");
927 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
928 &stats->tx_underrun, "FIFO underruns");
929 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
930 &stats->tx_desc_underrun, "Descriptor write-back errors");
931 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
932 &stats->tx_lenerrs, "Frames with length mismatched");
933 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
934 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
935 }
936
937 #undef ALE_SYSCTL_STAT_ADD32
938 #undef ALE_SYSCTL_STAT_ADD64
939
940 struct ale_dmamap_arg {
941 bus_addr_t ale_busaddr;
942 };
943
944 static void
ale_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)945 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
946 {
947 struct ale_dmamap_arg *ctx;
948
949 if (error != 0)
950 return;
951
952 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
953
954 ctx = (struct ale_dmamap_arg *)arg;
955 ctx->ale_busaddr = segs[0].ds_addr;
956 }
957
958 /*
959 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
960 * which specifies high address region of DMA blocks. Therefore these
961 * blocks should have the same high address of given 4GB address
962 * space(i.e. crossing 4GB boundary is not allowed).
963 */
964 static int
ale_check_boundary(struct ale_softc * sc)965 ale_check_boundary(struct ale_softc *sc)
966 {
967 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
968 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
969
970 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
971 sc->ale_pagesize;
972 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
973 sc->ale_pagesize;
974 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
975 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
976 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
977 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
978
979 if ((ALE_ADDR_HI(tx_ring_end) !=
980 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
981 (ALE_ADDR_HI(rx_page_end[0]) !=
982 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
983 (ALE_ADDR_HI(rx_page_end[1]) !=
984 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
985 (ALE_ADDR_HI(tx_cmb_end) !=
986 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
987 (ALE_ADDR_HI(rx_cmb_end[0]) !=
988 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
989 (ALE_ADDR_HI(rx_cmb_end[1]) !=
990 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
991 return (EFBIG);
992
993 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
994 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
995 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
996 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
997 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
998 return (EFBIG);
999
1000 return (0);
1001 }
1002
1003 static int
ale_dma_alloc(struct ale_softc * sc)1004 ale_dma_alloc(struct ale_softc *sc)
1005 {
1006 struct ale_txdesc *txd;
1007 bus_addr_t lowaddr;
1008 struct ale_dmamap_arg ctx;
1009 int error, guard_size, i;
1010
1011 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1012 guard_size = ALE_JUMBO_FRAMELEN;
1013 else
1014 guard_size = ALE_MAX_FRAMELEN;
1015 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1016 ALE_RX_PAGE_ALIGN);
1017 lowaddr = BUS_SPACE_MAXADDR;
1018 again:
1019 /* Create parent DMA tag. */
1020 error = bus_dma_tag_create(
1021 bus_get_dma_tag(sc->ale_dev), /* parent */
1022 1, 0, /* alignment, boundary */
1023 lowaddr, /* lowaddr */
1024 BUS_SPACE_MAXADDR, /* highaddr */
1025 NULL, NULL, /* filter, filterarg */
1026 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1027 0, /* nsegments */
1028 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1029 0, /* flags */
1030 NULL, NULL, /* lockfunc, lockarg */
1031 &sc->ale_cdata.ale_parent_tag);
1032 if (error != 0) {
1033 device_printf(sc->ale_dev,
1034 "could not create parent DMA tag.\n");
1035 goto fail;
1036 }
1037
1038 /* Create DMA tag for Tx descriptor ring. */
1039 error = bus_dma_tag_create(
1040 sc->ale_cdata.ale_parent_tag, /* parent */
1041 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1042 BUS_SPACE_MAXADDR, /* lowaddr */
1043 BUS_SPACE_MAXADDR, /* highaddr */
1044 NULL, NULL, /* filter, filterarg */
1045 ALE_TX_RING_SZ, /* maxsize */
1046 1, /* nsegments */
1047 ALE_TX_RING_SZ, /* maxsegsize */
1048 0, /* flags */
1049 NULL, NULL, /* lockfunc, lockarg */
1050 &sc->ale_cdata.ale_tx_ring_tag);
1051 if (error != 0) {
1052 device_printf(sc->ale_dev,
1053 "could not create Tx ring DMA tag.\n");
1054 goto fail;
1055 }
1056
1057 /* Create DMA tag for Rx pages. */
1058 for (i = 0; i < ALE_RX_PAGES; i++) {
1059 error = bus_dma_tag_create(
1060 sc->ale_cdata.ale_parent_tag, /* parent */
1061 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1062 BUS_SPACE_MAXADDR, /* lowaddr */
1063 BUS_SPACE_MAXADDR, /* highaddr */
1064 NULL, NULL, /* filter, filterarg */
1065 sc->ale_pagesize, /* maxsize */
1066 1, /* nsegments */
1067 sc->ale_pagesize, /* maxsegsize */
1068 0, /* flags */
1069 NULL, NULL, /* lockfunc, lockarg */
1070 &sc->ale_cdata.ale_rx_page[i].page_tag);
1071 if (error != 0) {
1072 device_printf(sc->ale_dev,
1073 "could not create Rx page %d DMA tag.\n", i);
1074 goto fail;
1075 }
1076 }
1077
1078 /* Create DMA tag for Tx coalescing message block. */
1079 error = bus_dma_tag_create(
1080 sc->ale_cdata.ale_parent_tag, /* parent */
1081 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1082 BUS_SPACE_MAXADDR, /* lowaddr */
1083 BUS_SPACE_MAXADDR, /* highaddr */
1084 NULL, NULL, /* filter, filterarg */
1085 ALE_TX_CMB_SZ, /* maxsize */
1086 1, /* nsegments */
1087 ALE_TX_CMB_SZ, /* maxsegsize */
1088 0, /* flags */
1089 NULL, NULL, /* lockfunc, lockarg */
1090 &sc->ale_cdata.ale_tx_cmb_tag);
1091 if (error != 0) {
1092 device_printf(sc->ale_dev,
1093 "could not create Tx CMB DMA tag.\n");
1094 goto fail;
1095 }
1096
1097 /* Create DMA tag for Rx coalescing message block. */
1098 for (i = 0; i < ALE_RX_PAGES; i++) {
1099 error = bus_dma_tag_create(
1100 sc->ale_cdata.ale_parent_tag, /* parent */
1101 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1102 BUS_SPACE_MAXADDR, /* lowaddr */
1103 BUS_SPACE_MAXADDR, /* highaddr */
1104 NULL, NULL, /* filter, filterarg */
1105 ALE_RX_CMB_SZ, /* maxsize */
1106 1, /* nsegments */
1107 ALE_RX_CMB_SZ, /* maxsegsize */
1108 0, /* flags */
1109 NULL, NULL, /* lockfunc, lockarg */
1110 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1111 if (error != 0) {
1112 device_printf(sc->ale_dev,
1113 "could not create Rx page %d CMB DMA tag.\n", i);
1114 goto fail;
1115 }
1116 }
1117
1118 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1119 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1120 (void **)&sc->ale_cdata.ale_tx_ring,
1121 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1122 &sc->ale_cdata.ale_tx_ring_map);
1123 if (error != 0) {
1124 device_printf(sc->ale_dev,
1125 "could not allocate DMA'able memory for Tx ring.\n");
1126 goto fail;
1127 }
1128 ctx.ale_busaddr = 0;
1129 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1130 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1131 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1132 if (error != 0 || ctx.ale_busaddr == 0) {
1133 device_printf(sc->ale_dev,
1134 "could not load DMA'able memory for Tx ring.\n");
1135 goto fail;
1136 }
1137 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1138
1139 /* Rx pages. */
1140 for (i = 0; i < ALE_RX_PAGES; i++) {
1141 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1142 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1143 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1144 &sc->ale_cdata.ale_rx_page[i].page_map);
1145 if (error != 0) {
1146 device_printf(sc->ale_dev,
1147 "could not allocate DMA'able memory for "
1148 "Rx page %d.\n", i);
1149 goto fail;
1150 }
1151 ctx.ale_busaddr = 0;
1152 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1153 sc->ale_cdata.ale_rx_page[i].page_map,
1154 sc->ale_cdata.ale_rx_page[i].page_addr,
1155 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1156 if (error != 0 || ctx.ale_busaddr == 0) {
1157 device_printf(sc->ale_dev,
1158 "could not load DMA'able memory for "
1159 "Rx page %d.\n", i);
1160 goto fail;
1161 }
1162 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1163 }
1164
1165 /* Tx CMB. */
1166 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1167 (void **)&sc->ale_cdata.ale_tx_cmb,
1168 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1169 &sc->ale_cdata.ale_tx_cmb_map);
1170 if (error != 0) {
1171 device_printf(sc->ale_dev,
1172 "could not allocate DMA'able memory for Tx CMB.\n");
1173 goto fail;
1174 }
1175 ctx.ale_busaddr = 0;
1176 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1177 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1178 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1179 if (error != 0 || ctx.ale_busaddr == 0) {
1180 device_printf(sc->ale_dev,
1181 "could not load DMA'able memory for Tx CMB.\n");
1182 goto fail;
1183 }
1184 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1185
1186 /* Rx CMB. */
1187 for (i = 0; i < ALE_RX_PAGES; i++) {
1188 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1189 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1190 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1191 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1192 if (error != 0) {
1193 device_printf(sc->ale_dev, "could not allocate "
1194 "DMA'able memory for Rx page %d CMB.\n", i);
1195 goto fail;
1196 }
1197 ctx.ale_busaddr = 0;
1198 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1199 sc->ale_cdata.ale_rx_page[i].cmb_map,
1200 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1201 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1202 if (error != 0 || ctx.ale_busaddr == 0) {
1203 device_printf(sc->ale_dev, "could not load DMA'able "
1204 "memory for Rx page %d CMB.\n", i);
1205 goto fail;
1206 }
1207 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1208 }
1209
1210 /*
1211 * Tx descriptors/RXF0/CMB DMA blocks share the same
1212 * high address region of 64bit DMA address space.
1213 */
1214 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1215 (error = ale_check_boundary(sc)) != 0) {
1216 device_printf(sc->ale_dev, "4GB boundary crossed, "
1217 "switching to 32bit DMA addressing mode.\n");
1218 ale_dma_free(sc);
1219 /*
1220 * Limit max allowable DMA address space to 32bit
1221 * and try again.
1222 */
1223 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1224 goto again;
1225 }
1226
1227 /*
1228 * Create Tx buffer parent tag.
1229 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1230 * needs separate parent DMA tag as parent DMA address space
1231 * could be restricted to be within 32bit address space by
1232 * 4GB boundary crossing.
1233 */
1234 error = bus_dma_tag_create(
1235 bus_get_dma_tag(sc->ale_dev), /* parent */
1236 1, 0, /* alignment, boundary */
1237 BUS_SPACE_MAXADDR, /* lowaddr */
1238 BUS_SPACE_MAXADDR, /* highaddr */
1239 NULL, NULL, /* filter, filterarg */
1240 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1241 0, /* nsegments */
1242 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1243 0, /* flags */
1244 NULL, NULL, /* lockfunc, lockarg */
1245 &sc->ale_cdata.ale_buffer_tag);
1246 if (error != 0) {
1247 device_printf(sc->ale_dev,
1248 "could not create parent buffer DMA tag.\n");
1249 goto fail;
1250 }
1251
1252 /* Create DMA tag for Tx buffers. */
1253 error = bus_dma_tag_create(
1254 sc->ale_cdata.ale_buffer_tag, /* parent */
1255 1, 0, /* alignment, boundary */
1256 BUS_SPACE_MAXADDR, /* lowaddr */
1257 BUS_SPACE_MAXADDR, /* highaddr */
1258 NULL, NULL, /* filter, filterarg */
1259 ALE_TSO_MAXSIZE, /* maxsize */
1260 ALE_MAXTXSEGS, /* nsegments */
1261 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1262 0, /* flags */
1263 NULL, NULL, /* lockfunc, lockarg */
1264 &sc->ale_cdata.ale_tx_tag);
1265 if (error != 0) {
1266 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1267 goto fail;
1268 }
1269
1270 /* Create DMA maps for Tx buffers. */
1271 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1272 txd = &sc->ale_cdata.ale_txdesc[i];
1273 txd->tx_m = NULL;
1274 txd->tx_dmamap = NULL;
1275 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1276 &txd->tx_dmamap);
1277 if (error != 0) {
1278 device_printf(sc->ale_dev,
1279 "could not create Tx dmamap.\n");
1280 goto fail;
1281 }
1282 }
1283
1284 fail:
1285 return (error);
1286 }
1287
1288 static void
ale_dma_free(struct ale_softc * sc)1289 ale_dma_free(struct ale_softc *sc)
1290 {
1291 struct ale_txdesc *txd;
1292 int i;
1293
1294 /* Tx buffers. */
1295 if (sc->ale_cdata.ale_tx_tag != NULL) {
1296 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1297 txd = &sc->ale_cdata.ale_txdesc[i];
1298 if (txd->tx_dmamap != NULL) {
1299 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1300 txd->tx_dmamap);
1301 txd->tx_dmamap = NULL;
1302 }
1303 }
1304 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1305 sc->ale_cdata.ale_tx_tag = NULL;
1306 }
1307 /* Tx descriptor ring. */
1308 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1309 if (sc->ale_cdata.ale_tx_ring_paddr != 0)
1310 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1311 sc->ale_cdata.ale_tx_ring_map);
1312 if (sc->ale_cdata.ale_tx_ring != NULL)
1313 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1314 sc->ale_cdata.ale_tx_ring,
1315 sc->ale_cdata.ale_tx_ring_map);
1316 sc->ale_cdata.ale_tx_ring_paddr = 0;
1317 sc->ale_cdata.ale_tx_ring = NULL;
1318 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1319 sc->ale_cdata.ale_tx_ring_tag = NULL;
1320 }
1321 /* Rx page block. */
1322 for (i = 0; i < ALE_RX_PAGES; i++) {
1323 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1324 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0)
1325 bus_dmamap_unload(
1326 sc->ale_cdata.ale_rx_page[i].page_tag,
1327 sc->ale_cdata.ale_rx_page[i].page_map);
1328 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1329 bus_dmamem_free(
1330 sc->ale_cdata.ale_rx_page[i].page_tag,
1331 sc->ale_cdata.ale_rx_page[i].page_addr,
1332 sc->ale_cdata.ale_rx_page[i].page_map);
1333 sc->ale_cdata.ale_rx_page[i].page_paddr = 0;
1334 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1335 bus_dma_tag_destroy(
1336 sc->ale_cdata.ale_rx_page[i].page_tag);
1337 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1338 }
1339 }
1340 /* Rx CMB. */
1341 for (i = 0; i < ALE_RX_PAGES; i++) {
1342 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1343 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0)
1344 bus_dmamap_unload(
1345 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1346 sc->ale_cdata.ale_rx_page[i].cmb_map);
1347 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1348 bus_dmamem_free(
1349 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1350 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1351 sc->ale_cdata.ale_rx_page[i].cmb_map);
1352 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0;
1353 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1354 bus_dma_tag_destroy(
1355 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1356 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1357 }
1358 }
1359 /* Tx CMB. */
1360 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1361 if (sc->ale_cdata.ale_tx_cmb_paddr != 0)
1362 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1363 sc->ale_cdata.ale_tx_cmb_map);
1364 if (sc->ale_cdata.ale_tx_cmb != NULL)
1365 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1366 sc->ale_cdata.ale_tx_cmb,
1367 sc->ale_cdata.ale_tx_cmb_map);
1368 sc->ale_cdata.ale_tx_cmb_paddr = 0;
1369 sc->ale_cdata.ale_tx_cmb = NULL;
1370 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1371 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1372 }
1373 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1374 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1375 sc->ale_cdata.ale_buffer_tag = NULL;
1376 }
1377 if (sc->ale_cdata.ale_parent_tag != NULL) {
1378 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1379 sc->ale_cdata.ale_parent_tag = NULL;
1380 }
1381 }
1382
1383 static int
ale_shutdown(device_t dev)1384 ale_shutdown(device_t dev)
1385 {
1386
1387 return (ale_suspend(dev));
1388 }
1389
1390 /*
1391 * Note, this driver resets the link speed to 10/100Mbps by
1392 * restarting auto-negotiation in suspend/shutdown phase but we
1393 * don't know whether that auto-negotiation would succeed or not
1394 * as driver has no control after powering off/suspend operation.
1395 * If the renegotiation fail WOL may not work. Running at 1Gbps
1396 * will draw more power than 375mA at 3.3V which is specified in
1397 * PCI specification and that would result in complete
1398 * shutdowning power to ethernet controller.
1399 *
1400 * TODO
1401 * Save current negotiated media speed/duplex/flow-control to
1402 * softc and restore the same link again after resuming. PHY
1403 * handling such as power down/resetting to 100Mbps may be better
1404 * handled in suspend method in phy driver.
1405 */
1406 static void
ale_setlinkspeed(struct ale_softc * sc)1407 ale_setlinkspeed(struct ale_softc *sc)
1408 {
1409 struct mii_data *mii;
1410 int aneg, i;
1411
1412 mii = device_get_softc(sc->ale_miibus);
1413 mii_pollstat(mii);
1414 aneg = 0;
1415 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1416 (IFM_ACTIVE | IFM_AVALID)) {
1417 switch IFM_SUBTYPE(mii->mii_media_active) {
1418 case IFM_10_T:
1419 case IFM_100_TX:
1420 return;
1421 case IFM_1000_T:
1422 aneg++;
1423 break;
1424 default:
1425 break;
1426 }
1427 }
1428 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1430 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1432 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1433 DELAY(1000);
1434 if (aneg != 0) {
1435 /*
1436 * Poll link state until ale(4) get a 10/100Mbps link.
1437 */
1438 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1439 mii_pollstat(mii);
1440 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1441 == (IFM_ACTIVE | IFM_AVALID)) {
1442 switch (IFM_SUBTYPE(
1443 mii->mii_media_active)) {
1444 case IFM_10_T:
1445 case IFM_100_TX:
1446 ale_mac_config(sc);
1447 return;
1448 default:
1449 break;
1450 }
1451 }
1452 ALE_UNLOCK(sc);
1453 pause("alelnk", hz);
1454 ALE_LOCK(sc);
1455 }
1456 if (i == MII_ANEGTICKS_GIGE)
1457 device_printf(sc->ale_dev,
1458 "establishing a link failed, WOL may not work!");
1459 }
1460 /*
1461 * No link, force MAC to have 100Mbps, full-duplex link.
1462 * This is the last resort and may/may not work.
1463 */
1464 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1465 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1466 ale_mac_config(sc);
1467 }
1468
1469 static void
ale_setwol(struct ale_softc * sc)1470 ale_setwol(struct ale_softc *sc)
1471 {
1472 if_t ifp;
1473 uint32_t reg, pmcs;
1474 uint16_t pmstat;
1475 int pmc;
1476
1477 ALE_LOCK_ASSERT(sc);
1478
1479 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1480 /* Disable WOL. */
1481 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1482 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1483 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1484 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1485 /* Force PHY power down. */
1486 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1487 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1488 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1489 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1490 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1491 return;
1492 }
1493
1494 ifp = sc->ale_ifp;
1495 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1496 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1497 ale_setlinkspeed(sc);
1498 }
1499
1500 pmcs = 0;
1501 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
1502 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1503 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1504 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1505 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1506 MAC_CFG_BCAST);
1507 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
1508 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1509 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1510 reg |= MAC_CFG_RX_ENB;
1511 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1512
1513 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1514 /* WOL disabled, PHY power down. */
1515 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1516 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1517 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1518 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1519 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1520 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1521 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1522 GPHY_CTRL_PWDOWN_HW);
1523 }
1524 /* Request PME. */
1525 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1526 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1527 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1528 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1529 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1530 }
1531
1532 static int
ale_suspend(device_t dev)1533 ale_suspend(device_t dev)
1534 {
1535 struct ale_softc *sc;
1536
1537 sc = device_get_softc(dev);
1538
1539 ALE_LOCK(sc);
1540 ale_stop(sc);
1541 ale_setwol(sc);
1542 ALE_UNLOCK(sc);
1543
1544 return (0);
1545 }
1546
1547 static int
ale_resume(device_t dev)1548 ale_resume(device_t dev)
1549 {
1550 struct ale_softc *sc;
1551 if_t ifp;
1552 int pmc;
1553 uint16_t pmstat;
1554
1555 sc = device_get_softc(dev);
1556
1557 ALE_LOCK(sc);
1558 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1559 /* Disable PME and clear PME status. */
1560 pmstat = pci_read_config(sc->ale_dev,
1561 pmc + PCIR_POWER_STATUS, 2);
1562 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1563 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1564 pci_write_config(sc->ale_dev,
1565 pmc + PCIR_POWER_STATUS, pmstat, 2);
1566 }
1567 }
1568 /* Reset PHY. */
1569 ale_phy_reset(sc);
1570 ifp = sc->ale_ifp;
1571 if ((if_getflags(ifp) & IFF_UP) != 0) {
1572 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1573 ale_init_locked(sc);
1574 }
1575 ALE_UNLOCK(sc);
1576
1577 return (0);
1578 }
1579
1580 static int
ale_encap(struct ale_softc * sc,struct mbuf ** m_head)1581 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1582 {
1583 struct ale_txdesc *txd, *txd_last;
1584 struct tx_desc *desc;
1585 struct mbuf *m;
1586 struct ip *ip;
1587 struct tcphdr *tcp;
1588 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1589 bus_dmamap_t map;
1590 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1591 int error, i, nsegs, prod, si;
1592
1593 ALE_LOCK_ASSERT(sc);
1594
1595 M_ASSERTPKTHDR((*m_head));
1596
1597 m = *m_head;
1598 ip = NULL;
1599 tcp = NULL;
1600 cflags = vtag = 0;
1601 ip_off = poff = 0;
1602 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1603 /*
1604 * AR81xx requires offset of TCP/UDP payload in its Tx
1605 * descriptor to perform hardware Tx checksum offload.
1606 * Additionally, TSO requires IP/TCP header size and
1607 * modification of IP/TCP header in order to make TSO
1608 * engine work. This kind of operation takes many CPU
1609 * cycles on FreeBSD so fast host CPU is required to
1610 * get smooth TSO performance.
1611 */
1612 struct ether_header *eh;
1613
1614 if (M_WRITABLE(m) == 0) {
1615 /* Get a writable copy. */
1616 m = m_dup(*m_head, M_NOWAIT);
1617 /* Release original mbufs. */
1618 m_freem(*m_head);
1619 if (m == NULL) {
1620 *m_head = NULL;
1621 return (ENOBUFS);
1622 }
1623 *m_head = m;
1624 }
1625
1626 /*
1627 * Buggy-controller requires 4 byte aligned Tx buffer
1628 * to make custom checksum offload work.
1629 */
1630 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1631 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1632 (mtod(m, intptr_t) & 3) != 0) {
1633 m = m_defrag(*m_head, M_NOWAIT);
1634 if (m == NULL) {
1635 m_freem(*m_head);
1636 *m_head = NULL;
1637 return (ENOBUFS);
1638 }
1639 *m_head = m;
1640 }
1641
1642 ip_off = sizeof(struct ether_header);
1643 m = m_pullup(m, ip_off);
1644 if (m == NULL) {
1645 *m_head = NULL;
1646 return (ENOBUFS);
1647 }
1648 eh = mtod(m, struct ether_header *);
1649 /*
1650 * Check if hardware VLAN insertion is off.
1651 * Additional check for LLC/SNAP frame?
1652 */
1653 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1654 ip_off = sizeof(struct ether_vlan_header);
1655 m = m_pullup(m, ip_off);
1656 if (m == NULL) {
1657 *m_head = NULL;
1658 return (ENOBUFS);
1659 }
1660 }
1661 m = m_pullup(m, ip_off + sizeof(struct ip));
1662 if (m == NULL) {
1663 *m_head = NULL;
1664 return (ENOBUFS);
1665 }
1666 ip = (struct ip *)(mtod(m, char *) + ip_off);
1667 poff = ip_off + (ip->ip_hl << 2);
1668 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1669 /*
1670 * XXX
1671 * AR81xx requires the first descriptor should
1672 * not include any TCP playload for TSO case.
1673 * (i.e. ethernet header + IP + TCP header only)
1674 * m_pullup(9) above will ensure this too.
1675 * However it's not correct if the first mbuf
1676 * of the chain does not use cluster.
1677 */
1678 m = m_pullup(m, poff + sizeof(struct tcphdr));
1679 if (m == NULL) {
1680 *m_head = NULL;
1681 return (ENOBUFS);
1682 }
1683 ip = (struct ip *)(mtod(m, char *) + ip_off);
1684 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1685 m = m_pullup(m, poff + (tcp->th_off << 2));
1686 if (m == NULL) {
1687 *m_head = NULL;
1688 return (ENOBUFS);
1689 }
1690 /*
1691 * AR81xx requires IP/TCP header size and offset as
1692 * well as TCP pseudo checksum which complicates
1693 * TSO configuration. I guess this comes from the
1694 * adherence to Microsoft NDIS Large Send
1695 * specification which requires insertion of
1696 * pseudo checksum by upper stack. The pseudo
1697 * checksum that NDIS refers to doesn't include
1698 * TCP payload length so ale(4) should recompute
1699 * the pseudo checksum here. Hopefully this wouldn't
1700 * be much burden on modern CPUs.
1701 * Reset IP checksum and recompute TCP pseudo
1702 * checksum as NDIS specification said.
1703 */
1704 ip->ip_sum = 0;
1705 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1706 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1707 }
1708 *m_head = m;
1709 }
1710
1711 si = prod = sc->ale_cdata.ale_tx_prod;
1712 txd = &sc->ale_cdata.ale_txdesc[prod];
1713 txd_last = txd;
1714 map = txd->tx_dmamap;
1715
1716 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1717 *m_head, txsegs, &nsegs, 0);
1718 if (error == EFBIG) {
1719 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS);
1720 if (m == NULL) {
1721 m_freem(*m_head);
1722 *m_head = NULL;
1723 return (ENOMEM);
1724 }
1725 *m_head = m;
1726 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1727 *m_head, txsegs, &nsegs, 0);
1728 if (error != 0) {
1729 m_freem(*m_head);
1730 *m_head = NULL;
1731 return (error);
1732 }
1733 } else if (error != 0)
1734 return (error);
1735 if (nsegs == 0) {
1736 m_freem(*m_head);
1737 *m_head = NULL;
1738 return (EIO);
1739 }
1740
1741 /* Check descriptor overrun. */
1742 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1743 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1744 return (ENOBUFS);
1745 }
1746 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1747
1748 m = *m_head;
1749 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1750 /* Request TSO and set MSS. */
1751 cflags |= ALE_TD_TSO;
1752 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1753 /* Set IP/TCP header size. */
1754 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1755 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1756 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1757 /*
1758 * AR81xx supports Tx custom checksum offload feature
1759 * that offloads single 16bit checksum computation.
1760 * So you can choose one among IP, TCP and UDP.
1761 * Normally driver sets checksum start/insertion
1762 * position from the information of TCP/UDP frame as
1763 * TCP/UDP checksum takes more time than that of IP.
1764 * However it seems that custom checksum offload
1765 * requires 4 bytes aligned Tx buffers due to hardware
1766 * bug.
1767 * AR81xx also supports explicit Tx checksum computation
1768 * if it is told that the size of IP header and TCP
1769 * header(for UDP, the header size does not matter
1770 * because it's fixed length). However with this scheme
1771 * TSO does not work so you have to choose one either
1772 * TSO or explicit Tx checksum offload. I chosen TSO
1773 * plus custom checksum offload with work-around which
1774 * will cover most common usage for this consumer
1775 * ethernet controller. The work-around takes a lot of
1776 * CPU cycles if Tx buffer is not aligned on 4 bytes
1777 * boundary, though.
1778 */
1779 cflags |= ALE_TD_CXSUM;
1780 /* Set checksum start offset. */
1781 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1782 /* Set checksum insertion position of TCP/UDP. */
1783 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1784 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1785 }
1786
1787 /* Configure VLAN hardware tag insertion. */
1788 if ((m->m_flags & M_VLANTAG) != 0) {
1789 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1790 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1791 cflags |= ALE_TD_INSERT_VLAN_TAG;
1792 }
1793
1794 i = 0;
1795 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1796 /*
1797 * Make sure the first fragment contains
1798 * only ethernet and IP/TCP header with options.
1799 */
1800 hdrlen = poff + (tcp->th_off << 2);
1801 desc = &sc->ale_cdata.ale_tx_ring[prod];
1802 desc->addr = htole64(txsegs[i].ds_addr);
1803 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1804 desc->flags = htole32(cflags);
1805 sc->ale_cdata.ale_tx_cnt++;
1806 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1807 if (m->m_len - hdrlen > 0) {
1808 /* Handle remaining payload of the first fragment. */
1809 desc = &sc->ale_cdata.ale_tx_ring[prod];
1810 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1811 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1812 vtag);
1813 desc->flags = htole32(cflags);
1814 sc->ale_cdata.ale_tx_cnt++;
1815 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1816 }
1817 i = 1;
1818 }
1819 for (; i < nsegs; i++) {
1820 desc = &sc->ale_cdata.ale_tx_ring[prod];
1821 desc->addr = htole64(txsegs[i].ds_addr);
1822 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1823 desc->flags = htole32(cflags);
1824 sc->ale_cdata.ale_tx_cnt++;
1825 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1826 }
1827 /* Update producer index. */
1828 sc->ale_cdata.ale_tx_prod = prod;
1829 /* Set TSO header on the first descriptor. */
1830 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1831 desc = &sc->ale_cdata.ale_tx_ring[si];
1832 desc->flags |= htole32(ALE_TD_TSO_HDR);
1833 }
1834
1835 /* Finally set EOP on the last descriptor. */
1836 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1837 desc = &sc->ale_cdata.ale_tx_ring[prod];
1838 desc->flags |= htole32(ALE_TD_EOP);
1839
1840 /* Swap dmamap of the first and the last. */
1841 txd = &sc->ale_cdata.ale_txdesc[prod];
1842 map = txd_last->tx_dmamap;
1843 txd_last->tx_dmamap = txd->tx_dmamap;
1844 txd->tx_dmamap = map;
1845 txd->tx_m = m;
1846
1847 /* Sync descriptors. */
1848 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1849 sc->ale_cdata.ale_tx_ring_map,
1850 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1851
1852 return (0);
1853 }
1854
1855 static void
ale_start(if_t ifp)1856 ale_start(if_t ifp)
1857 {
1858 struct ale_softc *sc;
1859
1860 sc = if_getsoftc(ifp);
1861 ALE_LOCK(sc);
1862 ale_start_locked(ifp);
1863 ALE_UNLOCK(sc);
1864 }
1865
1866 static void
ale_start_locked(if_t ifp)1867 ale_start_locked(if_t ifp)
1868 {
1869 struct ale_softc *sc;
1870 struct mbuf *m_head;
1871 int enq;
1872
1873 sc = if_getsoftc(ifp);
1874
1875 ALE_LOCK_ASSERT(sc);
1876
1877 /* Reclaim transmitted frames. */
1878 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1879 ale_txeof(sc);
1880
1881 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1882 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1883 return;
1884
1885 for (enq = 0; !if_sendq_empty(ifp); ) {
1886 m_head = if_dequeue(ifp);
1887 if (m_head == NULL)
1888 break;
1889 /*
1890 * Pack the data into the transmit ring. If we
1891 * don't have room, set the OACTIVE flag and wait
1892 * for the NIC to drain the ring.
1893 */
1894 if (ale_encap(sc, &m_head)) {
1895 if (m_head == NULL)
1896 break;
1897 if_sendq_prepend(ifp, m_head);
1898 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1899 break;
1900 }
1901
1902 enq++;
1903 /*
1904 * If there's a BPF listener, bounce a copy of this frame
1905 * to him.
1906 */
1907 ETHER_BPF_MTAP(ifp, m_head);
1908 }
1909
1910 if (enq > 0) {
1911 /* Kick. */
1912 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1913 sc->ale_cdata.ale_tx_prod);
1914 /* Set a timeout in case the chip goes out to lunch. */
1915 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1916 }
1917 }
1918
1919 static void
ale_watchdog(struct ale_softc * sc)1920 ale_watchdog(struct ale_softc *sc)
1921 {
1922 if_t ifp;
1923
1924 ALE_LOCK_ASSERT(sc);
1925
1926 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1927 return;
1928
1929 ifp = sc->ale_ifp;
1930 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1931 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1932 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1933 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1934 ale_init_locked(sc);
1935 return;
1936 }
1937 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1938 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1939 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1940 ale_init_locked(sc);
1941 if (!if_sendq_empty(ifp))
1942 ale_start_locked(ifp);
1943 }
1944
1945 static int
ale_ioctl(if_t ifp,u_long cmd,caddr_t data)1946 ale_ioctl(if_t ifp, u_long cmd, caddr_t data)
1947 {
1948 struct ale_softc *sc;
1949 struct ifreq *ifr;
1950 struct mii_data *mii;
1951 int error, mask;
1952
1953 sc = if_getsoftc(ifp);
1954 ifr = (struct ifreq *)data;
1955 error = 0;
1956 switch (cmd) {
1957 case SIOCSIFMTU:
1958 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1959 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1960 ifr->ifr_mtu > ETHERMTU))
1961 error = EINVAL;
1962 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1963 ALE_LOCK(sc);
1964 if_setmtu(ifp, ifr->ifr_mtu);
1965 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1966 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1967 ale_init_locked(sc);
1968 }
1969 ALE_UNLOCK(sc);
1970 }
1971 break;
1972 case SIOCSIFFLAGS:
1973 ALE_LOCK(sc);
1974 if ((if_getflags(ifp) & IFF_UP) != 0) {
1975 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1976 if (((if_getflags(ifp) ^ sc->ale_if_flags)
1977 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1978 ale_rxfilter(sc);
1979 } else {
1980 ale_init_locked(sc);
1981 }
1982 } else {
1983 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1984 ale_stop(sc);
1985 }
1986 sc->ale_if_flags = if_getflags(ifp);
1987 ALE_UNLOCK(sc);
1988 break;
1989 case SIOCADDMULTI:
1990 case SIOCDELMULTI:
1991 ALE_LOCK(sc);
1992 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1993 ale_rxfilter(sc);
1994 ALE_UNLOCK(sc);
1995 break;
1996 case SIOCSIFMEDIA:
1997 case SIOCGIFMEDIA:
1998 mii = device_get_softc(sc->ale_miibus);
1999 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2000 break;
2001 case SIOCSIFCAP:
2002 ALE_LOCK(sc);
2003 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2004 if ((mask & IFCAP_TXCSUM) != 0 &&
2005 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2006 if_togglecapenable(ifp, IFCAP_TXCSUM);
2007 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2008 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0);
2009 else
2010 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES);
2011 }
2012 if ((mask & IFCAP_RXCSUM) != 0 &&
2013 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
2014 if_togglecapenable(ifp, IFCAP_RXCSUM);
2015 if ((mask & IFCAP_TSO4) != 0 &&
2016 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2017 if_togglecapenable(ifp, IFCAP_TSO4);
2018 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2019 if_sethwassistbits(ifp, CSUM_TSO, 0);
2020 else
2021 if_sethwassistbits(ifp, 0, CSUM_TSO);
2022 }
2023
2024 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2025 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
2026 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
2027 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2028 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2029 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2030 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2031 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2032 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2033 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2034 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2035 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2036 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2037 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2038 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2039 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2040 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
2041 ale_rxvlan(sc);
2042 }
2043 ALE_UNLOCK(sc);
2044 VLAN_CAPABILITIES(ifp);
2045 break;
2046 default:
2047 error = ether_ioctl(ifp, cmd, data);
2048 break;
2049 }
2050
2051 return (error);
2052 }
2053
2054 static void
ale_mac_config(struct ale_softc * sc)2055 ale_mac_config(struct ale_softc *sc)
2056 {
2057 struct mii_data *mii;
2058 uint32_t reg;
2059
2060 ALE_LOCK_ASSERT(sc);
2061
2062 mii = device_get_softc(sc->ale_miibus);
2063 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2064 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2065 MAC_CFG_SPEED_MASK);
2066 /* Reprogram MAC with resolved speed/duplex. */
2067 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2068 case IFM_10_T:
2069 case IFM_100_TX:
2070 reg |= MAC_CFG_SPEED_10_100;
2071 break;
2072 case IFM_1000_T:
2073 reg |= MAC_CFG_SPEED_1000;
2074 break;
2075 }
2076 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2077 reg |= MAC_CFG_FULL_DUPLEX;
2078 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2079 reg |= MAC_CFG_TX_FC;
2080 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2081 reg |= MAC_CFG_RX_FC;
2082 }
2083 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2084 }
2085
2086 static void
ale_stats_clear(struct ale_softc * sc)2087 ale_stats_clear(struct ale_softc *sc)
2088 {
2089 struct smb sb;
2090 uint32_t *reg;
2091 int i;
2092
2093 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2094 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2095 i += sizeof(uint32_t);
2096 }
2097 /* Read Tx statistics. */
2098 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2099 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2100 i += sizeof(uint32_t);
2101 }
2102 }
2103
2104 static void
ale_stats_update(struct ale_softc * sc)2105 ale_stats_update(struct ale_softc *sc)
2106 {
2107 struct ale_hw_stats *stat;
2108 struct smb sb, *smb;
2109 if_t ifp;
2110 uint32_t *reg;
2111 int i;
2112
2113 ALE_LOCK_ASSERT(sc);
2114
2115 ifp = sc->ale_ifp;
2116 stat = &sc->ale_stats;
2117 smb = &sb;
2118
2119 /* Read Rx statistics. */
2120 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2121 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2122 i += sizeof(uint32_t);
2123 }
2124 /* Read Tx statistics. */
2125 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2126 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2127 i += sizeof(uint32_t);
2128 }
2129
2130 /* Rx stats. */
2131 stat->rx_frames += smb->rx_frames;
2132 stat->rx_bcast_frames += smb->rx_bcast_frames;
2133 stat->rx_mcast_frames += smb->rx_mcast_frames;
2134 stat->rx_pause_frames += smb->rx_pause_frames;
2135 stat->rx_control_frames += smb->rx_control_frames;
2136 stat->rx_crcerrs += smb->rx_crcerrs;
2137 stat->rx_lenerrs += smb->rx_lenerrs;
2138 stat->rx_bytes += smb->rx_bytes;
2139 stat->rx_runts += smb->rx_runts;
2140 stat->rx_fragments += smb->rx_fragments;
2141 stat->rx_pkts_64 += smb->rx_pkts_64;
2142 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2143 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2144 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2145 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2146 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2147 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2148 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2149 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2150 stat->rx_rrs_errs += smb->rx_rrs_errs;
2151 stat->rx_alignerrs += smb->rx_alignerrs;
2152 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2153 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2154 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2155
2156 /* Tx stats. */
2157 stat->tx_frames += smb->tx_frames;
2158 stat->tx_bcast_frames += smb->tx_bcast_frames;
2159 stat->tx_mcast_frames += smb->tx_mcast_frames;
2160 stat->tx_pause_frames += smb->tx_pause_frames;
2161 stat->tx_excess_defer += smb->tx_excess_defer;
2162 stat->tx_control_frames += smb->tx_control_frames;
2163 stat->tx_deferred += smb->tx_deferred;
2164 stat->tx_bytes += smb->tx_bytes;
2165 stat->tx_pkts_64 += smb->tx_pkts_64;
2166 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2167 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2168 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2169 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2170 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2171 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2172 stat->tx_single_colls += smb->tx_single_colls;
2173 stat->tx_multi_colls += smb->tx_multi_colls;
2174 stat->tx_late_colls += smb->tx_late_colls;
2175 stat->tx_excess_colls += smb->tx_excess_colls;
2176 stat->tx_underrun += smb->tx_underrun;
2177 stat->tx_desc_underrun += smb->tx_desc_underrun;
2178 stat->tx_lenerrs += smb->tx_lenerrs;
2179 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2180 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2181 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2182
2183 /* Update counters in ifnet. */
2184 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2185
2186 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2187 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2188 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2189
2190 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
2191 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
2192
2193 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2194
2195 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2196 smb->rx_crcerrs + smb->rx_lenerrs +
2197 smb->rx_runts + smb->rx_pkts_truncated +
2198 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2199 smb->rx_alignerrs);
2200 }
2201
2202 static int
ale_intr(void * arg)2203 ale_intr(void *arg)
2204 {
2205 struct ale_softc *sc;
2206 uint32_t status;
2207
2208 sc = (struct ale_softc *)arg;
2209
2210 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2211 if ((status & ALE_INTRS) == 0)
2212 return (FILTER_STRAY);
2213 /* Disable interrupts. */
2214 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2215 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2216
2217 return (FILTER_HANDLED);
2218 }
2219
2220 static void
ale_int_task(void * arg,int pending)2221 ale_int_task(void *arg, int pending)
2222 {
2223 struct ale_softc *sc;
2224 if_t ifp;
2225 uint32_t status;
2226 int more;
2227
2228 sc = (struct ale_softc *)arg;
2229
2230 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2231 ALE_LOCK(sc);
2232 if (sc->ale_morework != 0)
2233 status |= INTR_RX_PKT;
2234 if ((status & ALE_INTRS) == 0)
2235 goto done;
2236
2237 /* Acknowledge interrupts but still disable interrupts. */
2238 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2239
2240 ifp = sc->ale_ifp;
2241 more = 0;
2242 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2243 more = ale_rxeof(sc, sc->ale_process_limit);
2244 if (more == EAGAIN)
2245 sc->ale_morework = 1;
2246 else if (more == EIO) {
2247 sc->ale_stats.reset_brk_seq++;
2248 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2249 ale_init_locked(sc);
2250 ALE_UNLOCK(sc);
2251 return;
2252 }
2253
2254 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2255 if ((status & INTR_DMA_RD_TO_RST) != 0)
2256 device_printf(sc->ale_dev,
2257 "DMA read error! -- resetting\n");
2258 if ((status & INTR_DMA_WR_TO_RST) != 0)
2259 device_printf(sc->ale_dev,
2260 "DMA write error! -- resetting\n");
2261 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2262 ale_init_locked(sc);
2263 ALE_UNLOCK(sc);
2264 return;
2265 }
2266 if (!if_sendq_empty(ifp))
2267 ale_start_locked(ifp);
2268 }
2269
2270 if (more == EAGAIN ||
2271 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2272 ALE_UNLOCK(sc);
2273 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2274 return;
2275 }
2276
2277 done:
2278 ALE_UNLOCK(sc);
2279
2280 /* Re-enable interrupts. */
2281 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2282 }
2283
2284 static void
ale_txeof(struct ale_softc * sc)2285 ale_txeof(struct ale_softc *sc)
2286 {
2287 if_t ifp;
2288 struct ale_txdesc *txd;
2289 uint32_t cons, prod;
2290 int prog;
2291
2292 ALE_LOCK_ASSERT(sc);
2293
2294 ifp = sc->ale_ifp;
2295
2296 if (sc->ale_cdata.ale_tx_cnt == 0)
2297 return;
2298
2299 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2300 sc->ale_cdata.ale_tx_ring_map,
2301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2302 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2303 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2304 sc->ale_cdata.ale_tx_cmb_map,
2305 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2306 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2307 } else
2308 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2309 cons = sc->ale_cdata.ale_tx_cons;
2310 /*
2311 * Go through our Tx list and free mbufs for those
2312 * frames which have been transmitted.
2313 */
2314 for (prog = 0; cons != prod; prog++,
2315 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2316 if (sc->ale_cdata.ale_tx_cnt <= 0)
2317 break;
2318 prog++;
2319 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2320 sc->ale_cdata.ale_tx_cnt--;
2321 txd = &sc->ale_cdata.ale_txdesc[cons];
2322 if (txd->tx_m != NULL) {
2323 /* Reclaim transmitted mbufs. */
2324 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2325 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2326 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2327 txd->tx_dmamap);
2328 m_freem(txd->tx_m);
2329 txd->tx_m = NULL;
2330 }
2331 }
2332
2333 if (prog > 0) {
2334 sc->ale_cdata.ale_tx_cons = cons;
2335 /*
2336 * Unarm watchdog timer only when there is no pending
2337 * Tx descriptors in queue.
2338 */
2339 if (sc->ale_cdata.ale_tx_cnt == 0)
2340 sc->ale_watchdog_timer = 0;
2341 }
2342 }
2343
2344 static void
ale_rx_update_page(struct ale_softc * sc,struct ale_rx_page ** page,uint32_t length,uint32_t * prod)2345 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2346 uint32_t length, uint32_t *prod)
2347 {
2348 struct ale_rx_page *rx_page;
2349
2350 rx_page = *page;
2351 /* Update consumer position. */
2352 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2353 ALE_RX_PAGE_ALIGN);
2354 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2355 /*
2356 * End of Rx page reached, let hardware reuse
2357 * this page.
2358 */
2359 rx_page->cons = 0;
2360 *rx_page->cmb_addr = 0;
2361 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2362 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2363 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2364 RXF_VALID);
2365 /* Switch to alternate Rx page. */
2366 sc->ale_cdata.ale_rx_curp ^= 1;
2367 rx_page = *page =
2368 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2369 /* Page flipped, sync CMB and Rx page. */
2370 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2371 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2372 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2373 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2374 /* Sync completed, cache updated producer index. */
2375 *prod = *rx_page->cmb_addr;
2376 }
2377 }
2378
2379 /*
2380 * It seems that AR81xx controller can compute partial checksum.
2381 * The partial checksum value can be used to accelerate checksum
2382 * computation for fragmented TCP/UDP packets. Upper network stack
2383 * already takes advantage of the partial checksum value in IP
2384 * reassembly stage. But I'm not sure the correctness of the
2385 * partial hardware checksum assistance due to lack of data sheet.
2386 * In addition, the Rx feature of controller that requires copying
2387 * for every frames effectively nullifies one of most nice offload
2388 * capability of controller.
2389 */
2390 static void
ale_rxcsum(struct ale_softc * sc,struct mbuf * m,uint32_t status)2391 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2392 {
2393 if_t ifp;
2394 struct ip *ip;
2395 char *p;
2396
2397 ifp = sc->ale_ifp;
2398 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2399 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2400 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2401
2402 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2403 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2404 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2405 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2406 m->m_pkthdr.csum_flags |=
2407 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2408 m->m_pkthdr.csum_data = 0xffff;
2409 }
2410 } else {
2411 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2412 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2413 p = mtod(m, char *);
2414 p += ETHER_HDR_LEN;
2415 if ((status & ALE_RD_802_3) != 0)
2416 p += LLC_SNAPFRAMELEN;
2417 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 &&
2418 (status & ALE_RD_VLAN) != 0)
2419 p += ETHER_VLAN_ENCAP_LEN;
2420 ip = (struct ip *)p;
2421 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2422 return;
2423 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2424 CSUM_PSEUDO_HDR;
2425 m->m_pkthdr.csum_data = 0xffff;
2426 }
2427 }
2428 /*
2429 * Don't mark bad checksum for TCP/UDP frames
2430 * as fragmented frames may always have set
2431 * bad checksummed bit of frame status.
2432 */
2433 }
2434
2435 /* Process received frames. */
2436 static int
ale_rxeof(struct ale_softc * sc,int count)2437 ale_rxeof(struct ale_softc *sc, int count)
2438 {
2439 struct ale_rx_page *rx_page;
2440 struct rx_rs *rs;
2441 if_t ifp;
2442 struct mbuf *m;
2443 uint32_t length, prod, seqno, status, vtags;
2444 int prog;
2445
2446 ifp = sc->ale_ifp;
2447 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2448 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2449 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2450 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2451 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2452 /*
2453 * Don't directly access producer index as hardware may
2454 * update it while Rx handler is in progress. It would
2455 * be even better if there is a way to let hardware
2456 * know how far driver processed its received frames.
2457 * Alternatively, hardware could provide a way to disable
2458 * CMB updates until driver acknowledges the end of CMB
2459 * access.
2460 */
2461 prod = *rx_page->cmb_addr;
2462 for (prog = 0; prog < count; prog++) {
2463 if (rx_page->cons >= prod)
2464 break;
2465 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2466 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2467 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2468 /*
2469 * Normally I believe this should not happen unless
2470 * severe driver bug or corrupted memory. However
2471 * it seems to happen under certain conditions which
2472 * is triggered by abrupt Rx events such as initiation
2473 * of bulk transfer of remote host. It's not easy to
2474 * reproduce this and I doubt it could be related
2475 * with FIFO overflow of hardware or activity of Tx
2476 * CMB updates. I also remember similar behaviour
2477 * seen on RealTek 8139 which uses resembling Rx
2478 * scheme.
2479 */
2480 if (bootverbose)
2481 device_printf(sc->ale_dev,
2482 "garbled seq: %u, expected: %u -- "
2483 "resetting!\n", seqno,
2484 sc->ale_cdata.ale_rx_seqno);
2485 return (EIO);
2486 }
2487 /* Frame received. */
2488 sc->ale_cdata.ale_rx_seqno++;
2489 length = ALE_RX_BYTES(le32toh(rs->length));
2490 status = le32toh(rs->flags);
2491 if ((status & ALE_RD_ERROR) != 0) {
2492 /*
2493 * We want to pass the following frames to upper
2494 * layer regardless of error status of Rx return
2495 * status.
2496 *
2497 * o IP/TCP/UDP checksum is bad.
2498 * o frame length and protocol specific length
2499 * does not match.
2500 */
2501 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2502 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2503 ALE_RD_TRUNC)) != 0) {
2504 ale_rx_update_page(sc, &rx_page, length, &prod);
2505 continue;
2506 }
2507 }
2508 /*
2509 * m_devget(9) is major bottle-neck of ale(4)(It comes
2510 * from hardware limitation). For jumbo frames we could
2511 * get a slightly better performance if driver use
2512 * m_getjcl(9) with proper buffer size argument. However
2513 * that would make code more complicated and I don't
2514 * think users would expect good Rx performance numbers
2515 * on these low-end consumer ethernet controller.
2516 */
2517 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2518 ETHER_ALIGN, ifp, NULL);
2519 if (m == NULL) {
2520 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2521 ale_rx_update_page(sc, &rx_page, length, &prod);
2522 continue;
2523 }
2524 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2525 (status & ALE_RD_IPV4) != 0)
2526 ale_rxcsum(sc, m, status);
2527 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2528 (status & ALE_RD_VLAN) != 0) {
2529 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2530 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2531 m->m_flags |= M_VLANTAG;
2532 }
2533
2534 /* Pass it to upper layer. */
2535 ALE_UNLOCK(sc);
2536 if_input(ifp, m);
2537 ALE_LOCK(sc);
2538
2539 ale_rx_update_page(sc, &rx_page, length, &prod);
2540 }
2541
2542 return (count > 0 ? 0 : EAGAIN);
2543 }
2544
2545 static void
ale_tick(void * arg)2546 ale_tick(void *arg)
2547 {
2548 struct ale_softc *sc;
2549 struct mii_data *mii;
2550
2551 sc = (struct ale_softc *)arg;
2552
2553 ALE_LOCK_ASSERT(sc);
2554
2555 mii = device_get_softc(sc->ale_miibus);
2556 mii_tick(mii);
2557 ale_stats_update(sc);
2558 /*
2559 * Reclaim Tx buffers that have been transferred. It's not
2560 * needed here but it would release allocated mbuf chains
2561 * faster and limit the maximum delay to a hz.
2562 */
2563 ale_txeof(sc);
2564 ale_watchdog(sc);
2565 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2566 }
2567
2568 static void
ale_reset(struct ale_softc * sc)2569 ale_reset(struct ale_softc *sc)
2570 {
2571 uint32_t reg;
2572 int i;
2573
2574 /* Initialize PCIe module. From Linux. */
2575 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2576
2577 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2578 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2579 DELAY(10);
2580 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2581 break;
2582 }
2583 if (i == 0)
2584 device_printf(sc->ale_dev, "master reset timeout!\n");
2585
2586 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2587 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2588 break;
2589 DELAY(10);
2590 }
2591
2592 if (i == 0)
2593 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2594 }
2595
2596 static void
ale_init(void * xsc)2597 ale_init(void *xsc)
2598 {
2599 struct ale_softc *sc;
2600
2601 sc = (struct ale_softc *)xsc;
2602 ALE_LOCK(sc);
2603 ale_init_locked(sc);
2604 ALE_UNLOCK(sc);
2605 }
2606
2607 static void
ale_init_locked(struct ale_softc * sc)2608 ale_init_locked(struct ale_softc *sc)
2609 {
2610 if_t ifp;
2611 struct mii_data *mii;
2612 uint8_t eaddr[ETHER_ADDR_LEN];
2613 bus_addr_t paddr;
2614 uint32_t reg, rxf_hi, rxf_lo;
2615
2616 ALE_LOCK_ASSERT(sc);
2617
2618 ifp = sc->ale_ifp;
2619 mii = device_get_softc(sc->ale_miibus);
2620
2621 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2622 return;
2623 /*
2624 * Cancel any pending I/O.
2625 */
2626 ale_stop(sc);
2627 /*
2628 * Reset the chip to a known state.
2629 */
2630 ale_reset(sc);
2631 /* Initialize Tx descriptors, DMA memory blocks. */
2632 ale_init_rx_pages(sc);
2633 ale_init_tx_ring(sc);
2634
2635 /* Reprogram the station address. */
2636 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2637 CSR_WRITE_4(sc, ALE_PAR0,
2638 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2639 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2640 /*
2641 * Clear WOL status and disable all WOL feature as WOL
2642 * would interfere Rx operation under normal environments.
2643 */
2644 CSR_READ_4(sc, ALE_WOL_CFG);
2645 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2646 /*
2647 * Set Tx descriptor/RXF0/CMB base addresses. They share
2648 * the same high address part of DMAable region.
2649 */
2650 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2651 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2652 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2653 CSR_WRITE_4(sc, ALE_TPD_CNT,
2654 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2655 /* Set Rx page base address, note we use single queue. */
2656 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2657 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2658 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2659 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2660 /* Set Tx/Rx CMB addresses. */
2661 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2662 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2663 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2664 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2665 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2666 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2667 /* Mark RXF0 is valid. */
2668 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2669 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2670 /*
2671 * No need to initialize RFX1/RXF2/RXF3. We don't use
2672 * multi-queue yet.
2673 */
2674
2675 /* Set Rx page size, excluding guard frame size. */
2676 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2677 /* Tell hardware that we're ready to load DMA blocks. */
2678 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2679
2680 /* Set Rx/Tx interrupt trigger threshold. */
2681 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2682 (4 << INT_TRIG_TX_THRESH_SHIFT));
2683 /*
2684 * XXX
2685 * Set interrupt trigger timer, its purpose and relation
2686 * with interrupt moderation mechanism is not clear yet.
2687 */
2688 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2689 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2690 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2691
2692 /* Configure interrupt moderation timer. */
2693 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2694 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2695 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2696 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2697 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2698 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2699 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2700 reg |= MASTER_IM_RX_TIMER_ENB;
2701 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2702 reg |= MASTER_IM_TX_TIMER_ENB;
2703 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2704 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2705
2706 /* Set Maximum frame size of controller. */
2707 if (if_getmtu(ifp) < ETHERMTU)
2708 sc->ale_max_frame_size = ETHERMTU;
2709 else
2710 sc->ale_max_frame_size = if_getmtu(ifp);
2711 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2712 ETHER_CRC_LEN;
2713 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2714 /* Configure IPG/IFG parameters. */
2715 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2716 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2717 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2718 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2719 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2720 /* Set parameters for half-duplex media. */
2721 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2722 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2723 HDPX_CFG_LCOL_MASK) |
2724 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2725 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2726 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2727 HDPX_CFG_ABEBT_MASK) |
2728 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2729 HDPX_CFG_JAMIPG_MASK));
2730
2731 /* Configure Tx jumbo frame parameters. */
2732 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2733 if (if_getmtu(ifp) < ETHERMTU)
2734 reg = sc->ale_max_frame_size;
2735 else if (if_getmtu(ifp) < 6 * 1024)
2736 reg = (sc->ale_max_frame_size * 2) / 3;
2737 else
2738 reg = sc->ale_max_frame_size / 2;
2739 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2740 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2741 TX_JUMBO_THRESH_UNIT_SHIFT);
2742 }
2743 /* Configure TxQ. */
2744 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2745 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2746 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2747 TXQ_CFG_TPD_BURST_MASK;
2748 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2749
2750 /* Configure Rx jumbo frame & flow control parameters. */
2751 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2752 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2753 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2754 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2755 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2756 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2757 RX_JUMBO_LKAH_MASK));
2758 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2759 rxf_hi = (reg * 7) / 10;
2760 rxf_lo = (reg * 3)/ 10;
2761 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2762 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2763 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2764 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2765 RX_FIFO_PAUSE_THRESH_HI_MASK));
2766 }
2767
2768 /* Disable RSS. */
2769 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2770 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2771
2772 /* Configure RxQ. */
2773 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2774 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2775
2776 /* Configure DMA parameters. */
2777 reg = 0;
2778 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2779 reg |= DMA_CFG_TXCMB_ENB;
2780 CSR_WRITE_4(sc, ALE_DMA_CFG,
2781 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2782 sc->ale_dma_rd_burst | reg |
2783 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2784 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2785 DMA_CFG_RD_DELAY_CNT_MASK) |
2786 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2787 DMA_CFG_WR_DELAY_CNT_MASK));
2788
2789 /*
2790 * Hardware can be configured to issue SMB interrupt based
2791 * on programmed interval. Since there is a callout that is
2792 * invoked for every hz in driver we use that instead of
2793 * relying on periodic SMB interrupt.
2794 */
2795 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2796 /* Clear MAC statistics. */
2797 ale_stats_clear(sc);
2798
2799 /*
2800 * Configure Tx/Rx MACs.
2801 * - Auto-padding for short frames.
2802 * - Enable CRC generation.
2803 * Actual reconfiguration of MAC for resolved speed/duplex
2804 * is followed after detection of link establishment.
2805 * AR81xx always does checksum computation regardless of
2806 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2807 * cause Rx handling issue for fragmented IP datagrams due
2808 * to silicon bug.
2809 */
2810 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2811 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2812 MAC_CFG_PREAMBLE_MASK);
2813 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2814 reg |= MAC_CFG_SPEED_10_100;
2815 else
2816 reg |= MAC_CFG_SPEED_1000;
2817 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2818
2819 /* Set up the receive filter. */
2820 ale_rxfilter(sc);
2821 ale_rxvlan(sc);
2822
2823 /* Acknowledge all pending interrupts and clear it. */
2824 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2825 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2826 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2827
2828 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2829 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2830
2831 sc->ale_flags &= ~ALE_FLAG_LINK;
2832 /* Switch to the current media. */
2833 mii_mediachg(mii);
2834
2835 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2836 }
2837
2838 static void
ale_stop(struct ale_softc * sc)2839 ale_stop(struct ale_softc *sc)
2840 {
2841 if_t ifp;
2842 struct ale_txdesc *txd;
2843 uint32_t reg;
2844 int i;
2845
2846 ALE_LOCK_ASSERT(sc);
2847 /*
2848 * Mark the interface down and cancel the watchdog timer.
2849 */
2850 ifp = sc->ale_ifp;
2851 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2852 sc->ale_flags &= ~ALE_FLAG_LINK;
2853 callout_stop(&sc->ale_tick_ch);
2854 sc->ale_watchdog_timer = 0;
2855 ale_stats_update(sc);
2856 /* Disable interrupts. */
2857 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2858 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2859 /* Disable queue processing and DMA. */
2860 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2861 reg &= ~TXQ_CFG_ENB;
2862 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2863 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2864 reg &= ~RXQ_CFG_ENB;
2865 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2866 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2867 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2868 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2869 DELAY(1000);
2870 /* Stop Rx/Tx MACs. */
2871 ale_stop_mac(sc);
2872 /* Disable interrupts which might be touched in taskq handler. */
2873 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2874
2875 /*
2876 * Free TX mbufs still in the queues.
2877 */
2878 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2879 txd = &sc->ale_cdata.ale_txdesc[i];
2880 if (txd->tx_m != NULL) {
2881 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2882 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2883 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2884 txd->tx_dmamap);
2885 m_freem(txd->tx_m);
2886 txd->tx_m = NULL;
2887 }
2888 }
2889 }
2890
2891 static void
ale_stop_mac(struct ale_softc * sc)2892 ale_stop_mac(struct ale_softc *sc)
2893 {
2894 uint32_t reg;
2895 int i;
2896
2897 ALE_LOCK_ASSERT(sc);
2898
2899 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2900 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2901 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2902 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2903 }
2904
2905 for (i = ALE_TIMEOUT; i > 0; i--) {
2906 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2907 if (reg == 0)
2908 break;
2909 DELAY(10);
2910 }
2911 if (i == 0)
2912 device_printf(sc->ale_dev,
2913 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2914 }
2915
2916 static void
ale_init_tx_ring(struct ale_softc * sc)2917 ale_init_tx_ring(struct ale_softc *sc)
2918 {
2919 struct ale_txdesc *txd;
2920 int i;
2921
2922 ALE_LOCK_ASSERT(sc);
2923
2924 sc->ale_cdata.ale_tx_prod = 0;
2925 sc->ale_cdata.ale_tx_cons = 0;
2926 sc->ale_cdata.ale_tx_cnt = 0;
2927
2928 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2929 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2930 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2931 txd = &sc->ale_cdata.ale_txdesc[i];
2932 txd->tx_m = NULL;
2933 }
2934 *sc->ale_cdata.ale_tx_cmb = 0;
2935 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2936 sc->ale_cdata.ale_tx_cmb_map,
2937 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2938 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2939 sc->ale_cdata.ale_tx_ring_map,
2940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2941 }
2942
2943 static void
ale_init_rx_pages(struct ale_softc * sc)2944 ale_init_rx_pages(struct ale_softc *sc)
2945 {
2946 struct ale_rx_page *rx_page;
2947 int i;
2948
2949 ALE_LOCK_ASSERT(sc);
2950
2951 sc->ale_morework = 0;
2952 sc->ale_cdata.ale_rx_seqno = 0;
2953 sc->ale_cdata.ale_rx_curp = 0;
2954
2955 for (i = 0; i < ALE_RX_PAGES; i++) {
2956 rx_page = &sc->ale_cdata.ale_rx_page[i];
2957 bzero(rx_page->page_addr, sc->ale_pagesize);
2958 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2959 rx_page->cons = 0;
2960 *rx_page->cmb_addr = 0;
2961 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2963 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2964 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2965 }
2966 }
2967
2968 static void
ale_rxvlan(struct ale_softc * sc)2969 ale_rxvlan(struct ale_softc *sc)
2970 {
2971 if_t ifp;
2972 uint32_t reg;
2973
2974 ALE_LOCK_ASSERT(sc);
2975
2976 ifp = sc->ale_ifp;
2977 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2978 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2979 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2980 reg |= MAC_CFG_VLAN_TAG_STRIP;
2981 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2982 }
2983
2984 static u_int
ale_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2985 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2986 {
2987 uint32_t crc, *mchash = arg;
2988
2989 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
2990 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2991
2992 return (1);
2993 }
2994
2995 static void
ale_rxfilter(struct ale_softc * sc)2996 ale_rxfilter(struct ale_softc *sc)
2997 {
2998 if_t ifp;
2999 uint32_t mchash[2];
3000 uint32_t rxcfg;
3001
3002 ALE_LOCK_ASSERT(sc);
3003
3004 ifp = sc->ale_ifp;
3005
3006 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3007 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3008 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
3009 rxcfg |= MAC_CFG_BCAST;
3010 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3011 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
3012 rxcfg |= MAC_CFG_PROMISC;
3013 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
3014 rxcfg |= MAC_CFG_ALLMULTI;
3015 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3016 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3017 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3018 return;
3019 }
3020
3021 /* Program new filter. */
3022 bzero(mchash, sizeof(mchash));
3023 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash);
3024
3025 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3026 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3027 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3028 }
3029
3030 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3031 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3032 {
3033 int error, value;
3034
3035 if (arg1 == NULL)
3036 return (EINVAL);
3037 value = *(int *)arg1;
3038 error = sysctl_handle_int(oidp, &value, 0, req);
3039 if (error || req->newptr == NULL)
3040 return (error);
3041 if (value < low || value > high)
3042 return (EINVAL);
3043 *(int *)arg1 = value;
3044
3045 return (0);
3046 }
3047
3048 static int
sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)3049 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3050 {
3051 return (sysctl_int_range(oidp, arg1, arg2, req,
3052 ALE_PROC_MIN, ALE_PROC_MAX));
3053 }
3054
3055 static int
sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)3056 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3057 {
3058
3059 return (sysctl_int_range(oidp, arg1, arg2, req,
3060 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
3061 }
3062