1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 323 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 325 MLX5_CMD_OP_MAX 326 }; 327 328 /* Valid range for general commands that don't work over an object */ 329 enum { 330 MLX5_CMD_OP_GENERAL_START = 0xb00, 331 MLX5_CMD_OP_GENERAL_END = 0xd00, 332 }; 333 334 enum { 335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 337 }; 338 339 enum { 340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 341 }; 342 343 struct mlx5_ifc_flow_table_fields_supported_bits { 344 u8 outer_dmac[0x1]; 345 u8 outer_smac[0x1]; 346 u8 outer_ether_type[0x1]; 347 u8 outer_ip_version[0x1]; 348 u8 outer_first_prio[0x1]; 349 u8 outer_first_cfi[0x1]; 350 u8 outer_first_vid[0x1]; 351 u8 outer_ipv4_ttl[0x1]; 352 u8 outer_second_prio[0x1]; 353 u8 outer_second_cfi[0x1]; 354 u8 outer_second_vid[0x1]; 355 u8 reserved_at_b[0x1]; 356 u8 outer_sip[0x1]; 357 u8 outer_dip[0x1]; 358 u8 outer_frag[0x1]; 359 u8 outer_ip_protocol[0x1]; 360 u8 outer_ip_ecn[0x1]; 361 u8 outer_ip_dscp[0x1]; 362 u8 outer_udp_sport[0x1]; 363 u8 outer_udp_dport[0x1]; 364 u8 outer_tcp_sport[0x1]; 365 u8 outer_tcp_dport[0x1]; 366 u8 outer_tcp_flags[0x1]; 367 u8 outer_gre_protocol[0x1]; 368 u8 outer_gre_key[0x1]; 369 u8 outer_vxlan_vni[0x1]; 370 u8 outer_geneve_vni[0x1]; 371 u8 outer_geneve_oam[0x1]; 372 u8 outer_geneve_protocol_type[0x1]; 373 u8 outer_geneve_opt_len[0x1]; 374 u8 source_vhca_port[0x1]; 375 u8 source_eswitch_port[0x1]; 376 377 u8 inner_dmac[0x1]; 378 u8 inner_smac[0x1]; 379 u8 inner_ether_type[0x1]; 380 u8 inner_ip_version[0x1]; 381 u8 inner_first_prio[0x1]; 382 u8 inner_first_cfi[0x1]; 383 u8 inner_first_vid[0x1]; 384 u8 reserved_at_27[0x1]; 385 u8 inner_second_prio[0x1]; 386 u8 inner_second_cfi[0x1]; 387 u8 inner_second_vid[0x1]; 388 u8 reserved_at_2b[0x1]; 389 u8 inner_sip[0x1]; 390 u8 inner_dip[0x1]; 391 u8 inner_frag[0x1]; 392 u8 inner_ip_protocol[0x1]; 393 u8 inner_ip_ecn[0x1]; 394 u8 inner_ip_dscp[0x1]; 395 u8 inner_udp_sport[0x1]; 396 u8 inner_udp_dport[0x1]; 397 u8 inner_tcp_sport[0x1]; 398 u8 inner_tcp_dport[0x1]; 399 u8 inner_tcp_flags[0x1]; 400 u8 reserved_at_37[0x9]; 401 402 u8 geneve_tlv_option_0_data[0x1]; 403 u8 geneve_tlv_option_0_exist[0x1]; 404 u8 reserved_at_42[0x3]; 405 u8 outer_first_mpls_over_udp[0x4]; 406 u8 outer_first_mpls_over_gre[0x4]; 407 u8 inner_first_mpls[0x4]; 408 u8 outer_first_mpls[0x4]; 409 u8 reserved_at_55[0x2]; 410 u8 outer_esp_spi[0x1]; 411 u8 reserved_at_58[0x2]; 412 u8 bth_dst_qp[0x1]; 413 u8 reserved_at_5b[0x5]; 414 415 u8 reserved_at_60[0x18]; 416 u8 metadata_reg_c_7[0x1]; 417 u8 metadata_reg_c_6[0x1]; 418 u8 metadata_reg_c_5[0x1]; 419 u8 metadata_reg_c_4[0x1]; 420 u8 metadata_reg_c_3[0x1]; 421 u8 metadata_reg_c_2[0x1]; 422 u8 metadata_reg_c_1[0x1]; 423 u8 metadata_reg_c_0[0x1]; 424 }; 425 426 /* Table 2170 - Flow Table Fields Supported 2 Format */ 427 struct mlx5_ifc_flow_table_fields_supported_2_bits { 428 u8 inner_l4_type_ext[0x1]; 429 u8 outer_l4_type_ext[0x1]; 430 u8 inner_l4_type[0x1]; 431 u8 outer_l4_type[0x1]; 432 u8 reserved_at_4[0xa]; 433 u8 bth_opcode[0x1]; 434 u8 reserved_at_f[0x1]; 435 u8 tunnel_header_0_1[0x1]; 436 u8 reserved_at_11[0xf]; 437 438 u8 reserved_at_20[0xf]; 439 u8 ipsec_next_header[0x1]; 440 u8 reserved_at_30[0x10]; 441 442 u8 reserved_at_40[0x40]; 443 }; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits { 446 u8 ft_support[0x1]; 447 u8 reserved_at_1[0x1]; 448 u8 flow_counter[0x1]; 449 u8 flow_modify_en[0x1]; 450 u8 modify_root[0x1]; 451 u8 identified_miss_table_mode[0x1]; 452 u8 flow_table_modify[0x1]; 453 u8 reformat[0x1]; 454 u8 decap[0x1]; 455 u8 reset_root_to_default[0x1]; 456 u8 pop_vlan[0x1]; 457 u8 push_vlan[0x1]; 458 u8 reserved_at_c[0x1]; 459 u8 pop_vlan_2[0x1]; 460 u8 push_vlan_2[0x1]; 461 u8 reformat_and_vlan_action[0x1]; 462 u8 reserved_at_10[0x1]; 463 u8 sw_owner[0x1]; 464 u8 reformat_l3_tunnel_to_l2[0x1]; 465 u8 reformat_l2_to_l3_tunnel[0x1]; 466 u8 reformat_and_modify_action[0x1]; 467 u8 ignore_flow_level[0x1]; 468 u8 reserved_at_16[0x1]; 469 u8 table_miss_action_domain[0x1]; 470 u8 termination_table[0x1]; 471 u8 reformat_and_fwd_to_table[0x1]; 472 u8 reserved_at_1a[0x2]; 473 u8 ipsec_encrypt[0x1]; 474 u8 ipsec_decrypt[0x1]; 475 u8 sw_owner_v2[0x1]; 476 u8 reserved_at_1f[0x1]; 477 478 u8 termination_table_raw_traffic[0x1]; 479 u8 reserved_at_21[0x1]; 480 u8 log_max_ft_size[0x6]; 481 u8 log_max_modify_header_context[0x8]; 482 u8 max_modify_header_actions[0x8]; 483 u8 max_ft_level[0x8]; 484 485 u8 reformat_add_esp_trasport[0x1]; 486 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 487 u8 reformat_add_esp_transport_over_udp[0x1]; 488 u8 reformat_del_esp_trasport[0x1]; 489 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 490 u8 reformat_del_esp_transport_over_udp[0x1]; 491 u8 execute_aso[0x1]; 492 u8 reserved_at_47[0x19]; 493 494 u8 reformat_l2_to_l3_psp_tunnel[0x1]; 495 u8 reformat_l3_psp_tunnel_to_l2[0x1]; 496 u8 reformat_insert[0x1]; 497 u8 reformat_remove[0x1]; 498 u8 macsec_encrypt[0x1]; 499 u8 macsec_decrypt[0x1]; 500 u8 psp_encrypt[0x1]; 501 u8 psp_decrypt[0x1]; 502 u8 reformat_add_macsec[0x1]; 503 u8 reformat_remove_macsec[0x1]; 504 u8 reparse[0x1]; 505 u8 reserved_at_6b[0x1]; 506 u8 cross_vhca_object[0x1]; 507 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 508 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 509 u8 ignore_flow_level_rtc_valid[0x1]; 510 u8 reserved_at_70[0x8]; 511 u8 log_max_ft_num[0x8]; 512 513 u8 reserved_at_80[0x10]; 514 u8 log_max_flow_counter[0x8]; 515 u8 log_max_destination[0x8]; 516 517 u8 reserved_at_a0[0x18]; 518 u8 log_max_flow[0x8]; 519 520 u8 reserved_at_c0[0x40]; 521 522 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 523 524 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 525 }; 526 527 struct mlx5_ifc_odp_per_transport_service_cap_bits { 528 u8 send[0x1]; 529 u8 receive[0x1]; 530 u8 write[0x1]; 531 u8 read[0x1]; 532 u8 atomic[0x1]; 533 u8 srq_receive[0x1]; 534 u8 reserved_at_6[0x1a]; 535 }; 536 537 struct mlx5_ifc_ipv4_layout_bits { 538 u8 reserved_at_0[0x60]; 539 540 u8 ipv4[0x20]; 541 }; 542 543 struct mlx5_ifc_ipv6_layout_bits { 544 u8 ipv6[16][0x8]; 545 }; 546 547 struct mlx5_ifc_ipv6_simple_layout_bits { 548 u8 ipv6_127_96[0x20]; 549 u8 ipv6_95_64[0x20]; 550 u8 ipv6_63_32[0x20]; 551 u8 ipv6_31_0[0x20]; 552 }; 553 554 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 555 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 556 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 557 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 558 u8 reserved_at_0[0x80]; 559 }; 560 561 enum { 562 MLX5_PACKET_L4_TYPE_NONE, 563 MLX5_PACKET_L4_TYPE_TCP, 564 MLX5_PACKET_L4_TYPE_UDP, 565 }; 566 567 enum { 568 MLX5_PACKET_L4_TYPE_EXT_NONE, 569 MLX5_PACKET_L4_TYPE_EXT_TCP, 570 MLX5_PACKET_L4_TYPE_EXT_UDP, 571 MLX5_PACKET_L4_TYPE_EXT_ICMP, 572 }; 573 574 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 575 u8 smac_47_16[0x20]; 576 577 u8 smac_15_0[0x10]; 578 u8 ethertype[0x10]; 579 580 u8 dmac_47_16[0x20]; 581 582 u8 dmac_15_0[0x10]; 583 u8 first_prio[0x3]; 584 u8 first_cfi[0x1]; 585 u8 first_vid[0xc]; 586 587 u8 ip_protocol[0x8]; 588 u8 ip_dscp[0x6]; 589 u8 ip_ecn[0x2]; 590 u8 cvlan_tag[0x1]; 591 u8 svlan_tag[0x1]; 592 u8 frag[0x1]; 593 u8 ip_version[0x4]; 594 u8 tcp_flags[0x9]; 595 596 u8 tcp_sport[0x10]; 597 u8 tcp_dport[0x10]; 598 599 u8 l4_type[0x2]; 600 u8 l4_type_ext[0x4]; 601 u8 reserved_at_c6[0xa]; 602 u8 ipv4_ihl[0x4]; 603 u8 reserved_at_d4[0x4]; 604 u8 ttl_hoplimit[0x8]; 605 606 u8 udp_sport[0x10]; 607 u8 udp_dport[0x10]; 608 609 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 610 611 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 612 }; 613 614 struct mlx5_ifc_nvgre_key_bits { 615 u8 hi[0x18]; 616 u8 lo[0x8]; 617 }; 618 619 union mlx5_ifc_gre_key_bits { 620 struct mlx5_ifc_nvgre_key_bits nvgre; 621 u8 key[0x20]; 622 }; 623 624 struct mlx5_ifc_fte_match_set_misc_bits { 625 u8 gre_c_present[0x1]; 626 u8 reserved_at_1[0x1]; 627 u8 gre_k_present[0x1]; 628 u8 gre_s_present[0x1]; 629 u8 source_vhca_port[0x4]; 630 u8 source_sqn[0x18]; 631 632 u8 source_eswitch_owner_vhca_id[0x10]; 633 u8 source_port[0x10]; 634 635 u8 outer_second_prio[0x3]; 636 u8 outer_second_cfi[0x1]; 637 u8 outer_second_vid[0xc]; 638 u8 inner_second_prio[0x3]; 639 u8 inner_second_cfi[0x1]; 640 u8 inner_second_vid[0xc]; 641 642 u8 outer_second_cvlan_tag[0x1]; 643 u8 inner_second_cvlan_tag[0x1]; 644 u8 outer_second_svlan_tag[0x1]; 645 u8 inner_second_svlan_tag[0x1]; 646 u8 reserved_at_64[0xc]; 647 u8 gre_protocol[0x10]; 648 649 union mlx5_ifc_gre_key_bits gre_key; 650 651 u8 vxlan_vni[0x18]; 652 u8 bth_opcode[0x8]; 653 654 u8 geneve_vni[0x18]; 655 u8 reserved_at_d8[0x6]; 656 u8 geneve_tlv_option_0_exist[0x1]; 657 u8 geneve_oam[0x1]; 658 659 u8 reserved_at_e0[0xc]; 660 u8 outer_ipv6_flow_label[0x14]; 661 662 u8 reserved_at_100[0xc]; 663 u8 inner_ipv6_flow_label[0x14]; 664 665 u8 reserved_at_120[0xa]; 666 u8 geneve_opt_len[0x6]; 667 u8 geneve_protocol_type[0x10]; 668 669 u8 reserved_at_140[0x8]; 670 u8 bth_dst_qp[0x18]; 671 u8 inner_esp_spi[0x20]; 672 u8 outer_esp_spi[0x20]; 673 u8 reserved_at_1a0[0x60]; 674 }; 675 676 struct mlx5_ifc_fte_match_mpls_bits { 677 u8 mpls_label[0x14]; 678 u8 mpls_exp[0x3]; 679 u8 mpls_s_bos[0x1]; 680 u8 mpls_ttl[0x8]; 681 }; 682 683 struct mlx5_ifc_fte_match_set_misc2_bits { 684 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 685 686 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 687 688 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 689 690 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 691 692 u8 metadata_reg_c_7[0x20]; 693 694 u8 metadata_reg_c_6[0x20]; 695 696 u8 metadata_reg_c_5[0x20]; 697 698 u8 metadata_reg_c_4[0x20]; 699 700 u8 metadata_reg_c_3[0x20]; 701 702 u8 metadata_reg_c_2[0x20]; 703 704 u8 metadata_reg_c_1[0x20]; 705 706 u8 metadata_reg_c_0[0x20]; 707 708 u8 metadata_reg_a[0x20]; 709 710 u8 psp_syndrome[0x8]; 711 u8 macsec_syndrome[0x8]; 712 u8 ipsec_syndrome[0x8]; 713 u8 ipsec_next_header[0x8]; 714 715 u8 reserved_at_1c0[0x40]; 716 }; 717 718 struct mlx5_ifc_fte_match_set_misc3_bits { 719 u8 inner_tcp_seq_num[0x20]; 720 721 u8 outer_tcp_seq_num[0x20]; 722 723 u8 inner_tcp_ack_num[0x20]; 724 725 u8 outer_tcp_ack_num[0x20]; 726 727 u8 reserved_at_80[0x8]; 728 u8 outer_vxlan_gpe_vni[0x18]; 729 730 u8 outer_vxlan_gpe_next_protocol[0x8]; 731 u8 outer_vxlan_gpe_flags[0x8]; 732 u8 reserved_at_b0[0x10]; 733 734 u8 icmp_header_data[0x20]; 735 736 u8 icmpv6_header_data[0x20]; 737 738 u8 icmp_type[0x8]; 739 u8 icmp_code[0x8]; 740 u8 icmpv6_type[0x8]; 741 u8 icmpv6_code[0x8]; 742 743 u8 geneve_tlv_option_0_data[0x20]; 744 745 u8 gtpu_teid[0x20]; 746 747 u8 gtpu_msg_type[0x8]; 748 u8 gtpu_msg_flags[0x8]; 749 u8 reserved_at_170[0x10]; 750 751 u8 gtpu_dw_2[0x20]; 752 753 u8 gtpu_first_ext_dw_0[0x20]; 754 755 u8 gtpu_dw_0[0x20]; 756 757 u8 reserved_at_1e0[0x20]; 758 }; 759 760 struct mlx5_ifc_fte_match_set_misc4_bits { 761 u8 prog_sample_field_value_0[0x20]; 762 763 u8 prog_sample_field_id_0[0x20]; 764 765 u8 prog_sample_field_value_1[0x20]; 766 767 u8 prog_sample_field_id_1[0x20]; 768 769 u8 prog_sample_field_value_2[0x20]; 770 771 u8 prog_sample_field_id_2[0x20]; 772 773 u8 prog_sample_field_value_3[0x20]; 774 775 u8 prog_sample_field_id_3[0x20]; 776 777 u8 reserved_at_100[0x100]; 778 }; 779 780 struct mlx5_ifc_fte_match_set_misc5_bits { 781 u8 macsec_tag_0[0x20]; 782 783 u8 macsec_tag_1[0x20]; 784 785 u8 macsec_tag_2[0x20]; 786 787 u8 macsec_tag_3[0x20]; 788 789 u8 tunnel_header_0[0x20]; 790 791 u8 tunnel_header_1[0x20]; 792 793 u8 tunnel_header_2[0x20]; 794 795 u8 tunnel_header_3[0x20]; 796 797 u8 reserved_at_100[0x100]; 798 }; 799 800 struct mlx5_ifc_cmd_pas_bits { 801 u8 pa_h[0x20]; 802 803 u8 pa_l[0x14]; 804 u8 reserved_at_34[0xc]; 805 }; 806 807 struct mlx5_ifc_uint64_bits { 808 u8 hi[0x20]; 809 810 u8 lo[0x20]; 811 }; 812 813 enum { 814 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 815 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 816 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 817 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 818 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 819 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 820 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 821 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 822 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 823 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 824 }; 825 826 struct mlx5_ifc_ads_bits { 827 u8 fl[0x1]; 828 u8 free_ar[0x1]; 829 u8 reserved_at_2[0xe]; 830 u8 pkey_index[0x10]; 831 832 u8 plane_index[0x8]; 833 u8 grh[0x1]; 834 u8 mlid[0x7]; 835 u8 rlid[0x10]; 836 837 u8 ack_timeout[0x5]; 838 u8 reserved_at_45[0x3]; 839 u8 src_addr_index[0x8]; 840 u8 reserved_at_50[0x4]; 841 u8 stat_rate[0x4]; 842 u8 hop_limit[0x8]; 843 844 u8 reserved_at_60[0x4]; 845 u8 tclass[0x8]; 846 u8 flow_label[0x14]; 847 848 u8 rgid_rip[16][0x8]; 849 850 u8 reserved_at_100[0x4]; 851 u8 f_dscp[0x1]; 852 u8 f_ecn[0x1]; 853 u8 reserved_at_106[0x1]; 854 u8 f_eth_prio[0x1]; 855 u8 ecn[0x2]; 856 u8 dscp[0x6]; 857 u8 udp_sport[0x10]; 858 859 u8 dei_cfi[0x1]; 860 u8 eth_prio[0x3]; 861 u8 sl[0x4]; 862 u8 vhca_port_num[0x8]; 863 u8 rmac_47_32[0x10]; 864 865 u8 rmac_31_0[0x20]; 866 }; 867 868 struct mlx5_ifc_flow_table_nic_cap_bits { 869 u8 nic_rx_multi_path_tirs[0x1]; 870 u8 nic_rx_multi_path_tirs_fts[0x1]; 871 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 872 u8 reserved_at_3[0x4]; 873 u8 sw_owner_reformat_supported[0x1]; 874 u8 reserved_at_8[0x18]; 875 876 u8 encap_general_header[0x1]; 877 u8 reserved_at_21[0xa]; 878 u8 log_max_packet_reformat_context[0x5]; 879 u8 reserved_at_30[0x6]; 880 u8 max_encap_header_size[0xa]; 881 u8 reserved_at_40[0x1c0]; 882 883 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 884 885 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 886 887 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 888 889 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 892 893 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 894 895 u8 reserved_at_e00[0x600]; 896 897 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 898 899 u8 reserved_at_1480[0x80]; 900 901 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 902 903 u8 reserved_at_1580[0x280]; 904 905 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 906 907 u8 reserved_at_1880[0x780]; 908 909 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 910 911 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 912 913 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 914 915 u8 reserved_at_20c0[0x5f40]; 916 }; 917 918 struct mlx5_ifc_port_selection_cap_bits { 919 u8 reserved_at_0[0x10]; 920 u8 port_select_flow_table[0x1]; 921 u8 reserved_at_11[0x1]; 922 u8 port_select_flow_table_bypass[0x1]; 923 u8 reserved_at_13[0xd]; 924 925 u8 reserved_at_20[0x1e0]; 926 927 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 928 929 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 930 931 u8 reserved_at_480[0x7b80]; 932 }; 933 934 enum { 935 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 936 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 937 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 938 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 939 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 940 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 941 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 942 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 943 }; 944 945 struct mlx5_ifc_flow_table_eswitch_cap_bits { 946 u8 fdb_to_vport_reg_c_id[0x8]; 947 u8 reserved_at_8[0x5]; 948 u8 fdb_uplink_hairpin[0x1]; 949 u8 fdb_multi_path_any_table_limit_regc[0x1]; 950 u8 reserved_at_f[0x1]; 951 u8 fdb_dynamic_tunnel[0x1]; 952 u8 reserved_at_11[0x1]; 953 u8 fdb_multi_path_any_table[0x1]; 954 u8 reserved_at_13[0x2]; 955 u8 fdb_modify_header_fwd_to_table[0x1]; 956 u8 fdb_ipv4_ttl_modify[0x1]; 957 u8 flow_source[0x1]; 958 u8 reserved_at_18[0x2]; 959 u8 multi_fdb_encap[0x1]; 960 u8 egress_acl_forward_to_vport[0x1]; 961 u8 fdb_multi_path_to_table[0x1]; 962 u8 reserved_at_1d[0x3]; 963 964 u8 reserved_at_20[0x1e0]; 965 966 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 967 968 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 969 970 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 971 972 u8 reserved_at_800[0xC00]; 973 974 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 975 976 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 977 978 u8 reserved_at_1500[0x300]; 979 980 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 981 982 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 983 984 u8 sw_steering_uplink_icm_address_rx[0x40]; 985 986 u8 sw_steering_uplink_icm_address_tx[0x40]; 987 988 u8 reserved_at_1900[0x6700]; 989 }; 990 991 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 992 u8 reserved_at_0[0x3]; 993 u8 log_max_num_ste[0x5]; 994 u8 reserved_at_8[0x3]; 995 u8 log_max_num_stc[0x5]; 996 u8 reserved_at_10[0x3]; 997 u8 log_max_num_rtc[0x5]; 998 u8 reserved_at_18[0x3]; 999 u8 log_max_num_header_modify_pattern[0x5]; 1000 1001 u8 rtc_hash_split_table[0x1]; 1002 u8 rtc_linear_lookup_table[0x1]; 1003 u8 reserved_at_22[0x1]; 1004 u8 stc_alloc_log_granularity[0x5]; 1005 u8 reserved_at_28[0x3]; 1006 u8 stc_alloc_log_max[0x5]; 1007 u8 reserved_at_30[0x3]; 1008 u8 ste_alloc_log_granularity[0x5]; 1009 u8 reserved_at_38[0x3]; 1010 u8 ste_alloc_log_max[0x5]; 1011 1012 u8 reserved_at_40[0xb]; 1013 u8 rtc_reparse_mode[0x5]; 1014 u8 reserved_at_50[0x3]; 1015 u8 rtc_index_mode[0x5]; 1016 u8 reserved_at_58[0x3]; 1017 u8 rtc_log_depth_max[0x5]; 1018 1019 u8 reserved_at_60[0x10]; 1020 u8 ste_format[0x10]; 1021 1022 u8 stc_action_type[0x80]; 1023 1024 u8 header_insert_type[0x10]; 1025 u8 header_remove_type[0x10]; 1026 1027 u8 trivial_match_definer[0x20]; 1028 1029 u8 reserved_at_140[0x1b]; 1030 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1031 1032 u8 reserved_at_160[0x18]; 1033 u8 access_index_mode[0x8]; 1034 1035 u8 reserved_at_180[0x10]; 1036 u8 ste_format_gen_wqe[0x10]; 1037 1038 u8 linear_match_definer_reg_c3[0x20]; 1039 1040 u8 fdb_jump_to_tir_stc[0x1]; 1041 u8 reserved_at_1c1[0x1f]; 1042 }; 1043 1044 struct mlx5_ifc_esw_cap_bits { 1045 u8 reserved_at_0[0x1d]; 1046 u8 merged_eswitch[0x1]; 1047 u8 reserved_at_1e[0x2]; 1048 1049 u8 reserved_at_20[0x40]; 1050 1051 u8 esw_manager_vport_number_valid[0x1]; 1052 u8 reserved_at_61[0xf]; 1053 u8 esw_manager_vport_number[0x10]; 1054 1055 u8 reserved_at_80[0x780]; 1056 }; 1057 1058 enum { 1059 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1060 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1061 }; 1062 1063 struct mlx5_ifc_e_switch_cap_bits { 1064 u8 vport_svlan_strip[0x1]; 1065 u8 vport_cvlan_strip[0x1]; 1066 u8 vport_svlan_insert[0x1]; 1067 u8 vport_cvlan_insert_if_not_exist[0x1]; 1068 u8 vport_cvlan_insert_overwrite[0x1]; 1069 u8 reserved_at_5[0x1]; 1070 u8 vport_cvlan_insert_always[0x1]; 1071 u8 esw_shared_ingress_acl[0x1]; 1072 u8 esw_uplink_ingress_acl[0x1]; 1073 u8 root_ft_on_other_esw[0x1]; 1074 u8 reserved_at_a[0xf]; 1075 u8 esw_functions_changed[0x1]; 1076 u8 reserved_at_1a[0x1]; 1077 u8 ecpf_vport_exists[0x1]; 1078 u8 counter_eswitch_affinity[0x1]; 1079 u8 merged_eswitch[0x1]; 1080 u8 nic_vport_node_guid_modify[0x1]; 1081 u8 nic_vport_port_guid_modify[0x1]; 1082 1083 u8 vxlan_encap_decap[0x1]; 1084 u8 nvgre_encap_decap[0x1]; 1085 u8 reserved_at_22[0x1]; 1086 u8 log_max_fdb_encap_uplink[0x5]; 1087 u8 reserved_at_21[0x3]; 1088 u8 log_max_packet_reformat_context[0x5]; 1089 u8 reserved_2b[0x6]; 1090 u8 max_encap_header_size[0xa]; 1091 1092 u8 reserved_at_40[0xb]; 1093 u8 log_max_esw_sf[0x5]; 1094 u8 esw_sf_base_id[0x10]; 1095 1096 u8 reserved_at_60[0x7a0]; 1097 1098 }; 1099 1100 struct mlx5_ifc_qos_cap_bits { 1101 u8 packet_pacing[0x1]; 1102 u8 esw_scheduling[0x1]; 1103 u8 esw_bw_share[0x1]; 1104 u8 esw_rate_limit[0x1]; 1105 u8 reserved_at_4[0x1]; 1106 u8 packet_pacing_burst_bound[0x1]; 1107 u8 packet_pacing_typical_size[0x1]; 1108 u8 reserved_at_7[0x1]; 1109 u8 nic_sq_scheduling[0x1]; 1110 u8 nic_bw_share[0x1]; 1111 u8 nic_rate_limit[0x1]; 1112 u8 packet_pacing_uid[0x1]; 1113 u8 log_esw_max_sched_depth[0x4]; 1114 u8 reserved_at_10[0x10]; 1115 1116 u8 reserved_at_20[0x9]; 1117 u8 esw_cross_esw_sched[0x1]; 1118 u8 reserved_at_2a[0x1]; 1119 u8 log_max_qos_nic_queue_group[0x5]; 1120 u8 reserved_at_30[0x10]; 1121 1122 u8 packet_pacing_max_rate[0x20]; 1123 1124 u8 packet_pacing_min_rate[0x20]; 1125 1126 u8 reserved_at_80[0xb]; 1127 u8 log_esw_max_rate_limit[0x5]; 1128 u8 packet_pacing_rate_table_size[0x10]; 1129 1130 u8 esw_element_type[0x10]; 1131 u8 esw_tsar_type[0x10]; 1132 1133 u8 reserved_at_c0[0x10]; 1134 u8 max_qos_para_vport[0x10]; 1135 1136 u8 max_tsar_bw_share[0x20]; 1137 1138 u8 nic_element_type[0x10]; 1139 u8 nic_tsar_type[0x10]; 1140 1141 u8 reserved_at_120[0x3]; 1142 u8 log_meter_aso_granularity[0x5]; 1143 u8 reserved_at_128[0x3]; 1144 u8 log_meter_aso_max_alloc[0x5]; 1145 u8 reserved_at_130[0x3]; 1146 u8 log_max_num_meter_aso[0x5]; 1147 u8 reserved_at_138[0x8]; 1148 1149 u8 reserved_at_140[0x6c0]; 1150 }; 1151 1152 struct mlx5_ifc_debug_cap_bits { 1153 u8 core_dump_general[0x1]; 1154 u8 core_dump_qp[0x1]; 1155 u8 reserved_at_2[0x7]; 1156 u8 resource_dump[0x1]; 1157 u8 reserved_at_a[0x16]; 1158 1159 u8 reserved_at_20[0x2]; 1160 u8 stall_detect[0x1]; 1161 u8 reserved_at_23[0x1d]; 1162 1163 u8 reserved_at_40[0x7c0]; 1164 }; 1165 1166 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1167 u8 csum_cap[0x1]; 1168 u8 vlan_cap[0x1]; 1169 u8 lro_cap[0x1]; 1170 u8 lro_psh_flag[0x1]; 1171 u8 lro_time_stamp[0x1]; 1172 u8 reserved_at_5[0x2]; 1173 u8 wqe_vlan_insert[0x1]; 1174 u8 self_lb_en_modifiable[0x1]; 1175 u8 reserved_at_9[0x2]; 1176 u8 max_lso_cap[0x5]; 1177 u8 multi_pkt_send_wqe[0x2]; 1178 u8 wqe_inline_mode[0x2]; 1179 u8 rss_ind_tbl_cap[0x4]; 1180 u8 reg_umr_sq[0x1]; 1181 u8 scatter_fcs[0x1]; 1182 u8 enhanced_multi_pkt_send_wqe[0x1]; 1183 u8 tunnel_lso_const_out_ip_id[0x1]; 1184 u8 tunnel_lro_gre[0x1]; 1185 u8 tunnel_lro_vxlan[0x1]; 1186 u8 tunnel_stateless_gre[0x1]; 1187 u8 tunnel_stateless_vxlan[0x1]; 1188 1189 u8 swp[0x1]; 1190 u8 swp_csum[0x1]; 1191 u8 swp_lso[0x1]; 1192 u8 cqe_checksum_full[0x1]; 1193 u8 tunnel_stateless_geneve_tx[0x1]; 1194 u8 tunnel_stateless_mpls_over_udp[0x1]; 1195 u8 tunnel_stateless_mpls_over_gre[0x1]; 1196 u8 tunnel_stateless_vxlan_gpe[0x1]; 1197 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1198 u8 tunnel_stateless_ip_over_ip[0x1]; 1199 u8 insert_trailer[0x1]; 1200 u8 reserved_at_2b[0x1]; 1201 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1202 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1203 u8 reserved_at_2e[0x2]; 1204 u8 max_vxlan_udp_ports[0x8]; 1205 u8 swp_csum_l4_partial[0x1]; 1206 u8 reserved_at_39[0x5]; 1207 u8 max_geneve_opt_len[0x1]; 1208 u8 tunnel_stateless_geneve_rx[0x1]; 1209 1210 u8 reserved_at_40[0x10]; 1211 u8 lro_min_mss_size[0x10]; 1212 1213 u8 reserved_at_60[0x120]; 1214 1215 u8 lro_timer_supported_periods[4][0x20]; 1216 1217 u8 reserved_at_200[0x600]; 1218 }; 1219 1220 enum { 1221 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1222 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1223 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1224 }; 1225 1226 struct mlx5_ifc_roce_cap_bits { 1227 u8 roce_apm[0x1]; 1228 u8 reserved_at_1[0x3]; 1229 u8 sw_r_roce_src_udp_port[0x1]; 1230 u8 fl_rc_qp_when_roce_disabled[0x1]; 1231 u8 fl_rc_qp_when_roce_enabled[0x1]; 1232 u8 roce_cc_general[0x1]; 1233 u8 qp_ooo_transmit_default[0x1]; 1234 u8 reserved_at_9[0x15]; 1235 u8 qp_ts_format[0x2]; 1236 1237 u8 reserved_at_20[0x60]; 1238 1239 u8 reserved_at_80[0xc]; 1240 u8 l3_type[0x4]; 1241 u8 reserved_at_90[0x8]; 1242 u8 roce_version[0x8]; 1243 1244 u8 reserved_at_a0[0x10]; 1245 u8 r_roce_dest_udp_port[0x10]; 1246 1247 u8 r_roce_max_src_udp_port[0x10]; 1248 u8 r_roce_min_src_udp_port[0x10]; 1249 1250 u8 reserved_at_e0[0x10]; 1251 u8 roce_address_table_size[0x10]; 1252 1253 u8 reserved_at_100[0x700]; 1254 }; 1255 1256 struct mlx5_ifc_sync_steering_in_bits { 1257 u8 opcode[0x10]; 1258 u8 uid[0x10]; 1259 1260 u8 reserved_at_20[0x10]; 1261 u8 op_mod[0x10]; 1262 1263 u8 reserved_at_40[0xc0]; 1264 }; 1265 1266 struct mlx5_ifc_sync_steering_out_bits { 1267 u8 status[0x8]; 1268 u8 reserved_at_8[0x18]; 1269 1270 u8 syndrome[0x20]; 1271 1272 u8 reserved_at_40[0x40]; 1273 }; 1274 1275 struct mlx5_ifc_sync_crypto_in_bits { 1276 u8 opcode[0x10]; 1277 u8 uid[0x10]; 1278 1279 u8 reserved_at_20[0x10]; 1280 u8 op_mod[0x10]; 1281 1282 u8 reserved_at_40[0x20]; 1283 1284 u8 reserved_at_60[0x10]; 1285 u8 crypto_type[0x10]; 1286 1287 u8 reserved_at_80[0x80]; 1288 }; 1289 1290 struct mlx5_ifc_sync_crypto_out_bits { 1291 u8 status[0x8]; 1292 u8 reserved_at_8[0x18]; 1293 1294 u8 syndrome[0x20]; 1295 1296 u8 reserved_at_40[0x40]; 1297 }; 1298 1299 struct mlx5_ifc_device_mem_cap_bits { 1300 u8 memic[0x1]; 1301 u8 reserved_at_1[0x1f]; 1302 1303 u8 reserved_at_20[0xb]; 1304 u8 log_min_memic_alloc_size[0x5]; 1305 u8 reserved_at_30[0x8]; 1306 u8 log_max_memic_addr_alignment[0x8]; 1307 1308 u8 memic_bar_start_addr[0x40]; 1309 1310 u8 memic_bar_size[0x20]; 1311 1312 u8 max_memic_size[0x20]; 1313 1314 u8 steering_sw_icm_start_address[0x40]; 1315 1316 u8 reserved_at_100[0x8]; 1317 u8 log_header_modify_sw_icm_size[0x8]; 1318 u8 reserved_at_110[0x2]; 1319 u8 log_sw_icm_alloc_granularity[0x6]; 1320 u8 log_steering_sw_icm_size[0x8]; 1321 1322 u8 log_indirect_encap_sw_icm_size[0x8]; 1323 u8 reserved_at_128[0x10]; 1324 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1325 1326 u8 header_modify_sw_icm_start_address[0x40]; 1327 1328 u8 reserved_at_180[0x40]; 1329 1330 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1331 1332 u8 memic_operations[0x20]; 1333 1334 u8 reserved_at_220[0x20]; 1335 1336 u8 indirect_encap_sw_icm_start_address[0x40]; 1337 1338 u8 reserved_at_280[0x580]; 1339 }; 1340 1341 struct mlx5_ifc_device_event_cap_bits { 1342 u8 user_affiliated_events[4][0x40]; 1343 1344 u8 user_unaffiliated_events[4][0x40]; 1345 }; 1346 1347 struct mlx5_ifc_virtio_emulation_cap_bits { 1348 u8 desc_tunnel_offload_type[0x1]; 1349 u8 eth_frame_offload_type[0x1]; 1350 u8 virtio_version_1_0[0x1]; 1351 u8 device_features_bits_mask[0xd]; 1352 u8 event_mode[0x8]; 1353 u8 virtio_queue_type[0x8]; 1354 1355 u8 max_tunnel_desc[0x10]; 1356 u8 reserved_at_30[0x3]; 1357 u8 log_doorbell_stride[0x5]; 1358 u8 reserved_at_38[0x3]; 1359 u8 log_doorbell_bar_size[0x5]; 1360 1361 u8 doorbell_bar_offset[0x40]; 1362 1363 u8 max_emulated_devices[0x8]; 1364 u8 max_num_virtio_queues[0x18]; 1365 1366 u8 reserved_at_a0[0x20]; 1367 1368 u8 reserved_at_c0[0x13]; 1369 u8 desc_group_mkey_supported[0x1]; 1370 u8 freeze_to_rdy_supported[0x1]; 1371 u8 reserved_at_d5[0xb]; 1372 1373 u8 reserved_at_e0[0x20]; 1374 1375 u8 umem_1_buffer_param_a[0x20]; 1376 1377 u8 umem_1_buffer_param_b[0x20]; 1378 1379 u8 umem_2_buffer_param_a[0x20]; 1380 1381 u8 umem_2_buffer_param_b[0x20]; 1382 1383 u8 umem_3_buffer_param_a[0x20]; 1384 1385 u8 umem_3_buffer_param_b[0x20]; 1386 1387 u8 reserved_at_1c0[0x640]; 1388 }; 1389 1390 enum { 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1394 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1395 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1396 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1397 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1398 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1399 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1400 }; 1401 1402 enum { 1403 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1404 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1405 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1406 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1407 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1408 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1409 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1410 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1411 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1412 }; 1413 1414 struct mlx5_ifc_atomic_caps_bits { 1415 u8 reserved_at_0[0x40]; 1416 1417 u8 atomic_req_8B_endianness_mode[0x2]; 1418 u8 reserved_at_42[0x4]; 1419 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1420 1421 u8 reserved_at_47[0x19]; 1422 1423 u8 reserved_at_60[0x20]; 1424 1425 u8 reserved_at_80[0x10]; 1426 u8 atomic_operations[0x10]; 1427 1428 u8 reserved_at_a0[0x10]; 1429 u8 atomic_size_qp[0x10]; 1430 1431 u8 reserved_at_c0[0x10]; 1432 u8 atomic_size_dc[0x10]; 1433 1434 u8 reserved_at_e0[0x720]; 1435 }; 1436 1437 struct mlx5_ifc_odp_scheme_cap_bits { 1438 u8 reserved_at_0[0x40]; 1439 1440 u8 sig[0x1]; 1441 u8 reserved_at_41[0x4]; 1442 u8 page_prefetch[0x1]; 1443 u8 reserved_at_46[0x1a]; 1444 1445 u8 reserved_at_60[0x20]; 1446 1447 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1448 1449 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1450 1451 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1452 1453 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1454 1455 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1456 1457 u8 reserved_at_120[0xe0]; 1458 }; 1459 1460 struct mlx5_ifc_odp_cap_bits { 1461 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1462 1463 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1464 1465 u8 reserved_at_400[0x200]; 1466 1467 u8 mem_page_fault[0x1]; 1468 u8 reserved_at_601[0x1f]; 1469 1470 u8 reserved_at_620[0x1e0]; 1471 }; 1472 1473 struct mlx5_ifc_tls_cap_bits { 1474 u8 tls_1_2_aes_gcm_128[0x1]; 1475 u8 tls_1_3_aes_gcm_128[0x1]; 1476 u8 tls_1_2_aes_gcm_256[0x1]; 1477 u8 tls_1_3_aes_gcm_256[0x1]; 1478 u8 reserved_at_4[0x1c]; 1479 1480 u8 reserved_at_20[0x7e0]; 1481 }; 1482 1483 struct mlx5_ifc_ipsec_cap_bits { 1484 u8 ipsec_full_offload[0x1]; 1485 u8 ipsec_crypto_offload[0x1]; 1486 u8 ipsec_esn[0x1]; 1487 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1488 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1489 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1490 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1491 u8 reserved_at_7[0x4]; 1492 u8 log_max_ipsec_offload[0x5]; 1493 u8 reserved_at_10[0x10]; 1494 1495 u8 min_log_ipsec_full_replay_window[0x8]; 1496 u8 max_log_ipsec_full_replay_window[0x8]; 1497 u8 reserved_at_30[0x7d0]; 1498 }; 1499 1500 struct mlx5_ifc_macsec_cap_bits { 1501 u8 macsec_epn[0x1]; 1502 u8 reserved_at_1[0x2]; 1503 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1504 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1505 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1506 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1507 u8 reserved_at_7[0x4]; 1508 u8 log_max_macsec_offload[0x5]; 1509 u8 reserved_at_10[0x10]; 1510 1511 u8 min_log_macsec_full_replay_window[0x8]; 1512 u8 max_log_macsec_full_replay_window[0x8]; 1513 u8 reserved_at_30[0x10]; 1514 1515 u8 reserved_at_40[0x7c0]; 1516 }; 1517 1518 struct mlx5_ifc_psp_cap_bits { 1519 u8 reserved_at_0[0x1]; 1520 u8 psp_crypto_offload[0x1]; 1521 u8 reserved_at_2[0x1]; 1522 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1523 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1524 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1525 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1526 u8 reserved_at_7[0x4]; 1527 u8 log_max_num_of_psp_spi[0x5]; 1528 u8 reserved_at_10[0x10]; 1529 1530 u8 reserved_at_20[0x7e0]; 1531 }; 1532 1533 enum { 1534 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1535 MLX5_WQ_TYPE_CYCLIC = 0x1, 1536 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1537 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1538 }; 1539 1540 enum { 1541 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1542 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1543 }; 1544 1545 enum { 1546 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1547 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1548 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1549 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1550 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1551 }; 1552 1553 enum { 1554 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1555 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1556 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1557 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1558 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1559 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1560 }; 1561 1562 enum { 1563 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1564 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1565 }; 1566 1567 enum { 1568 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1569 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1570 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1571 }; 1572 1573 enum { 1574 MLX5_CAP_PORT_TYPE_IB = 0x0, 1575 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1576 }; 1577 1578 enum { 1579 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1580 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1581 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1582 }; 1583 1584 enum { 1585 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1586 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1587 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1588 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1589 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1590 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1591 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1592 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1593 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1594 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1595 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1596 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1597 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1598 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1599 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1600 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1601 }; 1602 1603 enum { 1604 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1605 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1606 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1607 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1608 }; 1609 1610 #define MLX5_FC_BULK_SIZE_FACTOR 128 1611 1612 enum mlx5_fc_bulk_alloc_bitmask { 1613 MLX5_FC_BULK_128 = (1 << 0), 1614 MLX5_FC_BULK_256 = (1 << 1), 1615 MLX5_FC_BULK_512 = (1 << 2), 1616 MLX5_FC_BULK_1024 = (1 << 3), 1617 MLX5_FC_BULK_2048 = (1 << 4), 1618 MLX5_FC_BULK_4096 = (1 << 5), 1619 MLX5_FC_BULK_8192 = (1 << 6), 1620 MLX5_FC_BULK_16384 = (1 << 7), 1621 }; 1622 1623 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1624 1625 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1626 1627 enum { 1628 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1629 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1630 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1631 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1632 }; 1633 1634 struct mlx5_ifc_cmd_hca_cap_bits { 1635 u8 reserved_at_0[0x6]; 1636 u8 page_request_disable[0x1]; 1637 u8 abs_native_port_num[0x1]; 1638 u8 reserved_at_8[0x8]; 1639 u8 shared_object_to_user_object_allowed[0x1]; 1640 u8 reserved_at_13[0xe]; 1641 u8 vhca_resource_manager[0x1]; 1642 1643 u8 hca_cap_2[0x1]; 1644 u8 create_lag_when_not_master_up[0x1]; 1645 u8 dtor[0x1]; 1646 u8 event_on_vhca_state_teardown_request[0x1]; 1647 u8 event_on_vhca_state_in_use[0x1]; 1648 u8 event_on_vhca_state_active[0x1]; 1649 u8 event_on_vhca_state_allocated[0x1]; 1650 u8 event_on_vhca_state_invalid[0x1]; 1651 u8 reserved_at_28[0x8]; 1652 u8 vhca_id[0x10]; 1653 1654 u8 reserved_at_40[0x40]; 1655 1656 u8 log_max_srq_sz[0x8]; 1657 u8 log_max_qp_sz[0x8]; 1658 u8 event_cap[0x1]; 1659 u8 reserved_at_91[0x2]; 1660 u8 isolate_vl_tc_new[0x1]; 1661 u8 reserved_at_94[0x4]; 1662 u8 prio_tag_required[0x1]; 1663 u8 reserved_at_99[0x2]; 1664 u8 log_max_qp[0x5]; 1665 1666 u8 reserved_at_a0[0x3]; 1667 u8 ece_support[0x1]; 1668 u8 reserved_at_a4[0x5]; 1669 u8 reg_c_preserve[0x1]; 1670 u8 reserved_at_aa[0x1]; 1671 u8 log_max_srq[0x5]; 1672 u8 reserved_at_b0[0x1]; 1673 u8 uplink_follow[0x1]; 1674 u8 ts_cqe_to_dest_cqn[0x1]; 1675 u8 reserved_at_b3[0x6]; 1676 u8 go_back_n[0x1]; 1677 u8 reserved_at_ba[0x6]; 1678 1679 u8 max_sgl_for_optimized_performance[0x8]; 1680 u8 log_max_cq_sz[0x8]; 1681 u8 relaxed_ordering_write_umr[0x1]; 1682 u8 relaxed_ordering_read_umr[0x1]; 1683 u8 reserved_at_d2[0x7]; 1684 u8 virtio_net_device_emualtion_manager[0x1]; 1685 u8 virtio_blk_device_emualtion_manager[0x1]; 1686 u8 log_max_cq[0x5]; 1687 1688 u8 log_max_eq_sz[0x8]; 1689 u8 relaxed_ordering_write[0x1]; 1690 u8 relaxed_ordering_read_pci_enabled[0x1]; 1691 u8 log_max_mkey[0x6]; 1692 u8 reserved_at_f0[0x6]; 1693 u8 terminate_scatter_list_mkey[0x1]; 1694 u8 repeated_mkey[0x1]; 1695 u8 dump_fill_mkey[0x1]; 1696 u8 reserved_at_f9[0x2]; 1697 u8 fast_teardown[0x1]; 1698 u8 log_max_eq[0x4]; 1699 1700 u8 max_indirection[0x8]; 1701 u8 fixed_buffer_size[0x1]; 1702 u8 log_max_mrw_sz[0x7]; 1703 u8 force_teardown[0x1]; 1704 u8 reserved_at_111[0x1]; 1705 u8 log_max_bsf_list_size[0x6]; 1706 u8 umr_extended_translation_offset[0x1]; 1707 u8 null_mkey[0x1]; 1708 u8 log_max_klm_list_size[0x6]; 1709 1710 u8 reserved_at_120[0x2]; 1711 u8 qpc_extension[0x1]; 1712 u8 reserved_at_123[0x7]; 1713 u8 log_max_ra_req_dc[0x6]; 1714 u8 reserved_at_130[0x2]; 1715 u8 eth_wqe_too_small[0x1]; 1716 u8 reserved_at_133[0x6]; 1717 u8 vnic_env_cq_overrun[0x1]; 1718 u8 log_max_ra_res_dc[0x6]; 1719 1720 u8 reserved_at_140[0x5]; 1721 u8 release_all_pages[0x1]; 1722 u8 must_not_use[0x1]; 1723 u8 reserved_at_147[0x2]; 1724 u8 roce_accl[0x1]; 1725 u8 log_max_ra_req_qp[0x6]; 1726 u8 reserved_at_150[0xa]; 1727 u8 log_max_ra_res_qp[0x6]; 1728 1729 u8 end_pad[0x1]; 1730 u8 cc_query_allowed[0x1]; 1731 u8 cc_modify_allowed[0x1]; 1732 u8 start_pad[0x1]; 1733 u8 cache_line_128byte[0x1]; 1734 u8 reserved_at_165[0x4]; 1735 u8 rts2rts_qp_counters_set_id[0x1]; 1736 u8 reserved_at_16a[0x2]; 1737 u8 vnic_env_int_rq_oob[0x1]; 1738 u8 sbcam_reg[0x1]; 1739 u8 reserved_at_16e[0x1]; 1740 u8 qcam_reg[0x1]; 1741 u8 gid_table_size[0x10]; 1742 1743 u8 out_of_seq_cnt[0x1]; 1744 u8 vport_counters[0x1]; 1745 u8 retransmission_q_counters[0x1]; 1746 u8 debug[0x1]; 1747 u8 modify_rq_counter_set_id[0x1]; 1748 u8 rq_delay_drop[0x1]; 1749 u8 max_qp_cnt[0xa]; 1750 u8 pkey_table_size[0x10]; 1751 1752 u8 vport_group_manager[0x1]; 1753 u8 vhca_group_manager[0x1]; 1754 u8 ib_virt[0x1]; 1755 u8 eth_virt[0x1]; 1756 u8 vnic_env_queue_counters[0x1]; 1757 u8 ets[0x1]; 1758 u8 nic_flow_table[0x1]; 1759 u8 eswitch_manager[0x1]; 1760 u8 device_memory[0x1]; 1761 u8 mcam_reg[0x1]; 1762 u8 pcam_reg[0x1]; 1763 u8 local_ca_ack_delay[0x5]; 1764 u8 port_module_event[0x1]; 1765 u8 enhanced_error_q_counters[0x1]; 1766 u8 ports_check[0x1]; 1767 u8 reserved_at_1b3[0x1]; 1768 u8 disable_link_up[0x1]; 1769 u8 beacon_led[0x1]; 1770 u8 port_type[0x2]; 1771 u8 num_ports[0x8]; 1772 1773 u8 reserved_at_1c0[0x1]; 1774 u8 pps[0x1]; 1775 u8 pps_modify[0x1]; 1776 u8 log_max_msg[0x5]; 1777 u8 reserved_at_1c8[0x4]; 1778 u8 max_tc[0x4]; 1779 u8 temp_warn_event[0x1]; 1780 u8 dcbx[0x1]; 1781 u8 general_notification_event[0x1]; 1782 u8 reserved_at_1d3[0x2]; 1783 u8 fpga[0x1]; 1784 u8 rol_s[0x1]; 1785 u8 rol_g[0x1]; 1786 u8 reserved_at_1d8[0x1]; 1787 u8 wol_s[0x1]; 1788 u8 wol_g[0x1]; 1789 u8 wol_a[0x1]; 1790 u8 wol_b[0x1]; 1791 u8 wol_m[0x1]; 1792 u8 wol_u[0x1]; 1793 u8 wol_p[0x1]; 1794 1795 u8 stat_rate_support[0x10]; 1796 u8 reserved_at_1f0[0x1]; 1797 u8 pci_sync_for_fw_update_event[0x1]; 1798 u8 reserved_at_1f2[0x6]; 1799 u8 init2_lag_tx_port_affinity[0x1]; 1800 u8 reserved_at_1fa[0x2]; 1801 u8 wqe_based_flow_table_update_cap[0x1]; 1802 u8 cqe_version[0x4]; 1803 1804 u8 compact_address_vector[0x1]; 1805 u8 striding_rq[0x1]; 1806 u8 reserved_at_202[0x1]; 1807 u8 ipoib_enhanced_offloads[0x1]; 1808 u8 ipoib_basic_offloads[0x1]; 1809 u8 reserved_at_205[0x1]; 1810 u8 repeated_block_disabled[0x1]; 1811 u8 umr_modify_entity_size_disabled[0x1]; 1812 u8 umr_modify_atomic_disabled[0x1]; 1813 u8 umr_indirect_mkey_disabled[0x1]; 1814 u8 umr_fence[0x2]; 1815 u8 dc_req_scat_data_cqe[0x1]; 1816 u8 reserved_at_20d[0x2]; 1817 u8 drain_sigerr[0x1]; 1818 u8 cmdif_checksum[0x2]; 1819 u8 sigerr_cqe[0x1]; 1820 u8 reserved_at_213[0x1]; 1821 u8 wq_signature[0x1]; 1822 u8 sctr_data_cqe[0x1]; 1823 u8 reserved_at_216[0x1]; 1824 u8 sho[0x1]; 1825 u8 tph[0x1]; 1826 u8 rf[0x1]; 1827 u8 dct[0x1]; 1828 u8 qos[0x1]; 1829 u8 eth_net_offloads[0x1]; 1830 u8 roce[0x1]; 1831 u8 atomic[0x1]; 1832 u8 reserved_at_21f[0x1]; 1833 1834 u8 cq_oi[0x1]; 1835 u8 cq_resize[0x1]; 1836 u8 cq_moderation[0x1]; 1837 u8 cq_period_mode_modify[0x1]; 1838 u8 reserved_at_224[0x2]; 1839 u8 cq_eq_remap[0x1]; 1840 u8 pg[0x1]; 1841 u8 block_lb_mc[0x1]; 1842 u8 reserved_at_229[0x1]; 1843 u8 scqe_break_moderation[0x1]; 1844 u8 cq_period_start_from_cqe[0x1]; 1845 u8 cd[0x1]; 1846 u8 reserved_at_22d[0x1]; 1847 u8 apm[0x1]; 1848 u8 vector_calc[0x1]; 1849 u8 umr_ptr_rlky[0x1]; 1850 u8 imaicl[0x1]; 1851 u8 qp_packet_based[0x1]; 1852 u8 reserved_at_233[0x3]; 1853 u8 qkv[0x1]; 1854 u8 pkv[0x1]; 1855 u8 set_deth_sqpn[0x1]; 1856 u8 reserved_at_239[0x3]; 1857 u8 xrc[0x1]; 1858 u8 ud[0x1]; 1859 u8 uc[0x1]; 1860 u8 rc[0x1]; 1861 1862 u8 uar_4k[0x1]; 1863 u8 reserved_at_241[0x7]; 1864 u8 fl_rc_qp_when_roce_disabled[0x1]; 1865 u8 regexp_params[0x1]; 1866 u8 uar_sz[0x6]; 1867 u8 port_selection_cap[0x1]; 1868 u8 nic_cap_reg[0x1]; 1869 u8 umem_uid_0[0x1]; 1870 u8 reserved_at_253[0x5]; 1871 u8 log_pg_sz[0x8]; 1872 1873 u8 bf[0x1]; 1874 u8 driver_version[0x1]; 1875 u8 pad_tx_eth_packet[0x1]; 1876 u8 reserved_at_263[0x3]; 1877 u8 mkey_by_name[0x1]; 1878 u8 reserved_at_267[0x4]; 1879 1880 u8 log_bf_reg_size[0x5]; 1881 1882 u8 disciplined_fr_counter[0x1]; 1883 u8 reserved_at_271[0x2]; 1884 u8 qp_error_syndrome[0x1]; 1885 u8 reserved_at_274[0x2]; 1886 u8 lag_dct[0x2]; 1887 u8 lag_tx_port_affinity[0x1]; 1888 u8 lag_native_fdb_selection[0x1]; 1889 u8 reserved_at_27a[0x1]; 1890 u8 lag_master[0x1]; 1891 u8 num_lag_ports[0x4]; 1892 1893 u8 reserved_at_280[0x10]; 1894 u8 max_wqe_sz_sq[0x10]; 1895 1896 u8 reserved_at_2a0[0x7]; 1897 u8 mkey_pcie_tph[0x1]; 1898 u8 reserved_at_2a8[0x1]; 1899 u8 tis_tir_td_order[0x1]; 1900 1901 u8 psp[0x1]; 1902 u8 shampo[0x1]; 1903 u8 reserved_at_2ac[0x4]; 1904 u8 max_wqe_sz_rq[0x10]; 1905 1906 u8 max_flow_counter_31_16[0x10]; 1907 u8 max_wqe_sz_sq_dc[0x10]; 1908 1909 u8 reserved_at_2e0[0x7]; 1910 u8 max_qp_mcg[0x19]; 1911 1912 u8 reserved_at_300[0x10]; 1913 u8 flow_counter_bulk_alloc[0x8]; 1914 u8 log_max_mcg[0x8]; 1915 1916 u8 reserved_at_320[0x3]; 1917 u8 log_max_transport_domain[0x5]; 1918 u8 reserved_at_328[0x2]; 1919 u8 relaxed_ordering_read[0x1]; 1920 u8 log_max_pd[0x5]; 1921 u8 dp_ordering_ooo_all_ud[0x1]; 1922 u8 dp_ordering_ooo_all_uc[0x1]; 1923 u8 dp_ordering_ooo_all_xrc[0x1]; 1924 u8 dp_ordering_ooo_all_dc[0x1]; 1925 u8 dp_ordering_ooo_all_rc[0x1]; 1926 u8 pcie_reset_using_hotreset_method[0x1]; 1927 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1928 u8 vnic_env_cnt_steering_fail[0x1]; 1929 u8 vport_counter_local_loopback[0x1]; 1930 u8 q_counter_aggregation[0x1]; 1931 u8 q_counter_other_vport[0x1]; 1932 u8 log_max_xrcd[0x5]; 1933 1934 u8 nic_receive_steering_discard[0x1]; 1935 u8 receive_discard_vport_down[0x1]; 1936 u8 transmit_discard_vport_down[0x1]; 1937 u8 eq_overrun_count[0x1]; 1938 u8 reserved_at_344[0x1]; 1939 u8 invalid_command_count[0x1]; 1940 u8 quota_exceeded_count[0x1]; 1941 u8 reserved_at_347[0x1]; 1942 u8 log_max_flow_counter_bulk[0x8]; 1943 u8 max_flow_counter_15_0[0x10]; 1944 1945 1946 u8 reserved_at_360[0x3]; 1947 u8 log_max_rq[0x5]; 1948 u8 reserved_at_368[0x3]; 1949 u8 log_max_sq[0x5]; 1950 u8 reserved_at_370[0x3]; 1951 u8 log_max_tir[0x5]; 1952 u8 reserved_at_378[0x3]; 1953 u8 log_max_tis[0x5]; 1954 1955 u8 basic_cyclic_rcv_wqe[0x1]; 1956 u8 reserved_at_381[0x2]; 1957 u8 log_max_rmp[0x5]; 1958 u8 reserved_at_388[0x3]; 1959 u8 log_max_rqt[0x5]; 1960 u8 reserved_at_390[0x3]; 1961 u8 log_max_rqt_size[0x5]; 1962 u8 reserved_at_398[0x1]; 1963 u8 vnic_env_cnt_bar_uar_access[0x1]; 1964 u8 vnic_env_cnt_odp_page_fault[0x1]; 1965 u8 log_max_tis_per_sq[0x5]; 1966 1967 u8 ext_stride_num_range[0x1]; 1968 u8 roce_rw_supported[0x1]; 1969 u8 log_max_current_uc_list_wr_supported[0x1]; 1970 u8 log_max_stride_sz_rq[0x5]; 1971 u8 reserved_at_3a8[0x3]; 1972 u8 log_min_stride_sz_rq[0x5]; 1973 u8 reserved_at_3b0[0x3]; 1974 u8 log_max_stride_sz_sq[0x5]; 1975 u8 reserved_at_3b8[0x3]; 1976 u8 log_min_stride_sz_sq[0x5]; 1977 1978 u8 hairpin[0x1]; 1979 u8 reserved_at_3c1[0x2]; 1980 u8 log_max_hairpin_queues[0x5]; 1981 u8 reserved_at_3c8[0x3]; 1982 u8 log_max_hairpin_wq_data_sz[0x5]; 1983 u8 reserved_at_3d0[0x3]; 1984 u8 log_max_hairpin_num_packets[0x5]; 1985 u8 reserved_at_3d8[0x3]; 1986 u8 log_max_wq_sz[0x5]; 1987 1988 u8 nic_vport_change_event[0x1]; 1989 u8 disable_local_lb_uc[0x1]; 1990 u8 disable_local_lb_mc[0x1]; 1991 u8 log_min_hairpin_wq_data_sz[0x5]; 1992 u8 reserved_at_3e8[0x1]; 1993 u8 silent_mode[0x1]; 1994 u8 vhca_state[0x1]; 1995 u8 log_max_vlan_list[0x5]; 1996 u8 reserved_at_3f0[0x3]; 1997 u8 log_max_current_mc_list[0x5]; 1998 u8 reserved_at_3f8[0x3]; 1999 u8 log_max_current_uc_list[0x5]; 2000 2001 u8 general_obj_types[0x40]; 2002 2003 u8 sq_ts_format[0x2]; 2004 u8 rq_ts_format[0x2]; 2005 u8 steering_format_version[0x4]; 2006 u8 create_qp_start_hint[0x18]; 2007 2008 u8 reserved_at_460[0x1]; 2009 u8 ats[0x1]; 2010 u8 cross_vhca_rqt[0x1]; 2011 u8 log_max_uctx[0x5]; 2012 u8 reserved_at_468[0x1]; 2013 u8 crypto[0x1]; 2014 u8 ipsec_offload[0x1]; 2015 u8 log_max_umem[0x5]; 2016 u8 max_num_eqs[0x10]; 2017 2018 u8 reserved_at_480[0x1]; 2019 u8 tls_tx[0x1]; 2020 u8 tls_rx[0x1]; 2021 u8 log_max_l2_table[0x5]; 2022 u8 reserved_at_488[0x8]; 2023 u8 log_uar_page_sz[0x10]; 2024 2025 u8 reserved_at_4a0[0x20]; 2026 u8 device_frequency_mhz[0x20]; 2027 u8 device_frequency_khz[0x20]; 2028 2029 u8 reserved_at_500[0x20]; 2030 u8 num_of_uars_per_page[0x20]; 2031 2032 u8 flex_parser_protocols[0x20]; 2033 2034 u8 max_geneve_tlv_options[0x8]; 2035 u8 reserved_at_568[0x3]; 2036 u8 max_geneve_tlv_option_data_len[0x5]; 2037 u8 reserved_at_570[0x1]; 2038 u8 adv_rdma[0x1]; 2039 u8 reserved_at_572[0x7]; 2040 u8 adv_virtualization[0x1]; 2041 u8 reserved_at_57a[0x6]; 2042 2043 u8 reserved_at_580[0xb]; 2044 u8 log_max_dci_stream_channels[0x5]; 2045 u8 reserved_at_590[0x3]; 2046 u8 log_max_dci_errored_streams[0x5]; 2047 u8 reserved_at_598[0x8]; 2048 2049 u8 reserved_at_5a0[0x10]; 2050 u8 enhanced_cqe_compression[0x1]; 2051 u8 reserved_at_5b1[0x1]; 2052 u8 crossing_vhca_mkey[0x1]; 2053 u8 log_max_dek[0x5]; 2054 u8 reserved_at_5b8[0x4]; 2055 u8 mini_cqe_resp_stride_index[0x1]; 2056 u8 cqe_128_always[0x1]; 2057 u8 cqe_compression_128[0x1]; 2058 u8 cqe_compression[0x1]; 2059 2060 u8 cqe_compression_timeout[0x10]; 2061 u8 cqe_compression_max_num[0x10]; 2062 2063 u8 reserved_at_5e0[0x8]; 2064 u8 flex_parser_id_gtpu_dw_0[0x4]; 2065 u8 reserved_at_5ec[0x4]; 2066 u8 tag_matching[0x1]; 2067 u8 rndv_offload_rc[0x1]; 2068 u8 rndv_offload_dc[0x1]; 2069 u8 log_tag_matching_list_sz[0x5]; 2070 u8 reserved_at_5f8[0x3]; 2071 u8 log_max_xrq[0x5]; 2072 2073 u8 affiliate_nic_vport_criteria[0x8]; 2074 u8 native_port_num[0x8]; 2075 u8 num_vhca_ports[0x8]; 2076 u8 flex_parser_id_gtpu_teid[0x4]; 2077 u8 reserved_at_61c[0x2]; 2078 u8 sw_owner_id[0x1]; 2079 u8 reserved_at_61f[0x1]; 2080 2081 u8 max_num_of_monitor_counters[0x10]; 2082 u8 num_ppcnt_monitor_counters[0x10]; 2083 2084 u8 max_num_sf[0x10]; 2085 u8 num_q_monitor_counters[0x10]; 2086 2087 u8 reserved_at_660[0x20]; 2088 2089 u8 sf[0x1]; 2090 u8 sf_set_partition[0x1]; 2091 u8 reserved_at_682[0x1]; 2092 u8 log_max_sf[0x5]; 2093 u8 apu[0x1]; 2094 u8 reserved_at_689[0x4]; 2095 u8 migration[0x1]; 2096 u8 reserved_at_68e[0x2]; 2097 u8 log_min_sf_size[0x8]; 2098 u8 max_num_sf_partitions[0x8]; 2099 2100 u8 uctx_cap[0x20]; 2101 2102 u8 reserved_at_6c0[0x4]; 2103 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2104 u8 flex_parser_id_icmp_dw1[0x4]; 2105 u8 flex_parser_id_icmp_dw0[0x4]; 2106 u8 flex_parser_id_icmpv6_dw1[0x4]; 2107 u8 flex_parser_id_icmpv6_dw0[0x4]; 2108 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2109 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2110 2111 u8 max_num_match_definer[0x10]; 2112 u8 sf_base_id[0x10]; 2113 2114 u8 flex_parser_id_gtpu_dw_2[0x4]; 2115 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2116 u8 num_total_dynamic_vf_msix[0x18]; 2117 u8 reserved_at_720[0x14]; 2118 u8 dynamic_msix_table_size[0xc]; 2119 u8 reserved_at_740[0xc]; 2120 u8 min_dynamic_vf_msix_table_size[0x4]; 2121 u8 reserved_at_750[0x2]; 2122 u8 data_direct[0x1]; 2123 u8 reserved_at_753[0x1]; 2124 u8 max_dynamic_vf_msix_table_size[0xc]; 2125 2126 u8 reserved_at_760[0x3]; 2127 u8 log_max_num_header_modify_argument[0x5]; 2128 u8 log_header_modify_argument_granularity_offset[0x4]; 2129 u8 log_header_modify_argument_granularity[0x4]; 2130 u8 reserved_at_770[0x3]; 2131 u8 log_header_modify_argument_max_alloc[0x5]; 2132 u8 reserved_at_778[0x8]; 2133 2134 u8 vhca_tunnel_commands[0x40]; 2135 u8 match_definer_format_supported[0x40]; 2136 }; 2137 2138 enum { 2139 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2140 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2141 }; 2142 2143 enum { 2144 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2145 }; 2146 2147 struct mlx5_ifc_cmd_hca_cap_2_bits { 2148 u8 reserved_at_0[0x80]; 2149 2150 u8 migratable[0x1]; 2151 u8 reserved_at_81[0x7]; 2152 u8 dp_ordering_force[0x1]; 2153 u8 reserved_at_89[0x9]; 2154 u8 query_vuid[0x1]; 2155 u8 reserved_at_93[0x5]; 2156 u8 umr_log_entity_size_5[0x1]; 2157 u8 reserved_at_99[0x7]; 2158 2159 u8 max_reformat_insert_size[0x8]; 2160 u8 max_reformat_insert_offset[0x8]; 2161 u8 max_reformat_remove_size[0x8]; 2162 u8 max_reformat_remove_offset[0x8]; 2163 2164 u8 reserved_at_c0[0x8]; 2165 u8 migration_multi_load[0x1]; 2166 u8 migration_tracking_state[0x1]; 2167 u8 multiplane_qp_ud[0x1]; 2168 u8 reserved_at_cb[0x5]; 2169 u8 migration_in_chunks[0x1]; 2170 u8 reserved_at_d1[0x1]; 2171 u8 sf_eq_usage[0x1]; 2172 u8 reserved_at_d3[0x5]; 2173 u8 multiplane[0x1]; 2174 u8 reserved_at_d9[0x7]; 2175 2176 u8 cross_vhca_object_to_object_supported[0x20]; 2177 2178 u8 allowed_object_for_other_vhca_access[0x40]; 2179 2180 u8 reserved_at_140[0x60]; 2181 2182 u8 flow_table_type_2_type[0x8]; 2183 u8 reserved_at_1a8[0x2]; 2184 u8 format_select_dw_8_6_ext[0x1]; 2185 u8 log_min_mkey_entity_size[0x5]; 2186 u8 reserved_at_1b0[0x10]; 2187 2188 u8 general_obj_types_127_64[0x40]; 2189 u8 reserved_at_200[0x20]; 2190 2191 u8 reserved_at_220[0x1]; 2192 u8 sw_vhca_id_valid[0x1]; 2193 u8 sw_vhca_id[0xe]; 2194 u8 reserved_at_230[0x10]; 2195 2196 u8 reserved_at_240[0xb]; 2197 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2198 u8 reserved_at_250[0x10]; 2199 2200 u8 reserved_at_260[0x20]; 2201 2202 u8 format_select_dw_gtpu_dw_0[0x8]; 2203 u8 format_select_dw_gtpu_dw_1[0x8]; 2204 u8 format_select_dw_gtpu_dw_2[0x8]; 2205 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2206 2207 u8 generate_wqe_type[0x20]; 2208 2209 u8 reserved_at_2c0[0xc0]; 2210 2211 u8 reserved_at_380[0xb]; 2212 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2213 u8 ec_vf_vport_base[0x10]; 2214 2215 u8 reserved_at_3a0[0x2]; 2216 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2217 u8 reserved_at_3a8[0x2]; 2218 u8 max_mkey_log_entity_size_mtt[0x6]; 2219 u8 max_rqt_vhca_id[0x10]; 2220 2221 u8 reserved_at_3c0[0x20]; 2222 2223 u8 reserved_at_3e0[0x10]; 2224 u8 pcc_ifa2[0x1]; 2225 u8 reserved_at_3f1[0xf]; 2226 2227 u8 reserved_at_400[0x1]; 2228 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2229 u8 reserved_at_402[0xe]; 2230 u8 return_reg_id[0x10]; 2231 2232 u8 reserved_at_420[0x1c]; 2233 u8 flow_table_hash_type[0x4]; 2234 2235 u8 reserved_at_440[0x8]; 2236 u8 max_num_eqs_24b[0x18]; 2237 2238 u8 reserved_at_460[0x144]; 2239 u8 load_balance_id[0x4]; 2240 u8 reserved_at_5a8[0x18]; 2241 2242 u8 query_adjacent_functions_id[0x1]; 2243 u8 ingress_egress_esw_vport_connect[0x1]; 2244 u8 function_id_type_vhca_id[0x1]; 2245 u8 reserved_at_5c3[0x1]; 2246 u8 lag_per_mp_group[0x1]; 2247 u8 reserved_at_5c5[0xb]; 2248 u8 delegate_vhca_management_profiles[0x10]; 2249 2250 u8 delegated_vhca_max[0x10]; 2251 u8 delegate_vhca_max[0x10]; 2252 2253 u8 reserved_at_600[0x200]; 2254 }; 2255 2256 enum mlx5_ifc_flow_destination_type { 2257 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2258 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2259 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2260 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2261 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2262 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2263 }; 2264 2265 enum mlx5_flow_table_miss_action { 2266 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2267 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2268 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2269 }; 2270 2271 struct mlx5_ifc_dest_format_struct_bits { 2272 u8 destination_type[0x8]; 2273 u8 destination_id[0x18]; 2274 2275 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2276 u8 packet_reformat[0x1]; 2277 u8 reserved_at_22[0x6]; 2278 u8 destination_table_type[0x8]; 2279 u8 destination_eswitch_owner_vhca_id[0x10]; 2280 }; 2281 2282 struct mlx5_ifc_flow_counter_list_bits { 2283 u8 flow_counter_id[0x20]; 2284 2285 u8 reserved_at_20[0x20]; 2286 }; 2287 2288 struct mlx5_ifc_extended_dest_format_bits { 2289 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2290 2291 u8 packet_reformat_id[0x20]; 2292 2293 u8 reserved_at_60[0x20]; 2294 }; 2295 2296 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2297 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2298 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2299 }; 2300 2301 struct mlx5_ifc_fte_match_param_bits { 2302 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2303 2304 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2305 2306 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2307 2308 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2309 2310 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2311 2312 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2313 2314 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2315 2316 u8 reserved_at_e00[0x200]; 2317 }; 2318 2319 enum { 2320 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2321 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2322 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2323 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2324 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2325 }; 2326 2327 struct mlx5_ifc_rx_hash_field_select_bits { 2328 u8 l3_prot_type[0x1]; 2329 u8 l4_prot_type[0x1]; 2330 u8 selected_fields[0x1e]; 2331 }; 2332 2333 enum { 2334 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2335 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2336 }; 2337 2338 enum { 2339 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2340 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2341 }; 2342 2343 struct mlx5_ifc_wq_bits { 2344 u8 wq_type[0x4]; 2345 u8 wq_signature[0x1]; 2346 u8 end_padding_mode[0x2]; 2347 u8 cd_slave[0x1]; 2348 u8 reserved_at_8[0x18]; 2349 2350 u8 hds_skip_first_sge[0x1]; 2351 u8 log2_hds_buf_size[0x3]; 2352 u8 reserved_at_24[0x7]; 2353 u8 page_offset[0x5]; 2354 u8 lwm[0x10]; 2355 2356 u8 reserved_at_40[0x8]; 2357 u8 pd[0x18]; 2358 2359 u8 reserved_at_60[0x8]; 2360 u8 uar_page[0x18]; 2361 2362 u8 dbr_addr[0x40]; 2363 2364 u8 hw_counter[0x20]; 2365 2366 u8 sw_counter[0x20]; 2367 2368 u8 reserved_at_100[0xc]; 2369 u8 log_wq_stride[0x4]; 2370 u8 reserved_at_110[0x3]; 2371 u8 log_wq_pg_sz[0x5]; 2372 u8 reserved_at_118[0x3]; 2373 u8 log_wq_sz[0x5]; 2374 2375 u8 dbr_umem_valid[0x1]; 2376 u8 wq_umem_valid[0x1]; 2377 u8 reserved_at_122[0x1]; 2378 u8 log_hairpin_num_packets[0x5]; 2379 u8 reserved_at_128[0x3]; 2380 u8 log_hairpin_data_sz[0x5]; 2381 2382 u8 reserved_at_130[0x4]; 2383 u8 log_wqe_num_of_strides[0x4]; 2384 u8 two_byte_shift_en[0x1]; 2385 u8 reserved_at_139[0x4]; 2386 u8 log_wqe_stride_size[0x3]; 2387 2388 u8 dbr_umem_id[0x20]; 2389 u8 wq_umem_id[0x20]; 2390 2391 u8 wq_umem_offset[0x40]; 2392 2393 u8 headers_mkey[0x20]; 2394 2395 u8 shampo_enable[0x1]; 2396 u8 reserved_at_1e1[0x1]; 2397 u8 shampo_mode[0x2]; 2398 u8 reserved_at_1e4[0x1]; 2399 u8 log_reservation_size[0x3]; 2400 u8 reserved_at_1e8[0x5]; 2401 u8 log_max_num_of_packets_per_reservation[0x3]; 2402 u8 reserved_at_1f0[0x6]; 2403 u8 log_headers_entry_size[0x2]; 2404 u8 reserved_at_1f8[0x4]; 2405 u8 log_headers_buffer_entry_num[0x4]; 2406 2407 u8 reserved_at_200[0x400]; 2408 2409 struct mlx5_ifc_cmd_pas_bits pas[]; 2410 }; 2411 2412 struct mlx5_ifc_rq_num_bits { 2413 u8 reserved_at_0[0x8]; 2414 u8 rq_num[0x18]; 2415 }; 2416 2417 struct mlx5_ifc_rq_vhca_bits { 2418 u8 reserved_at_0[0x8]; 2419 u8 rq_num[0x18]; 2420 u8 reserved_at_20[0x10]; 2421 u8 rq_vhca_id[0x10]; 2422 }; 2423 2424 struct mlx5_ifc_mac_address_layout_bits { 2425 u8 reserved_at_0[0x10]; 2426 u8 mac_addr_47_32[0x10]; 2427 2428 u8 mac_addr_31_0[0x20]; 2429 }; 2430 2431 struct mlx5_ifc_vlan_layout_bits { 2432 u8 reserved_at_0[0x14]; 2433 u8 vlan[0x0c]; 2434 2435 u8 reserved_at_20[0x20]; 2436 }; 2437 2438 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2439 u8 reserved_at_0[0xa0]; 2440 2441 u8 min_time_between_cnps[0x20]; 2442 2443 u8 reserved_at_c0[0x12]; 2444 u8 cnp_dscp[0x6]; 2445 u8 reserved_at_d8[0x4]; 2446 u8 cnp_prio_mode[0x1]; 2447 u8 cnp_802p_prio[0x3]; 2448 2449 u8 reserved_at_e0[0x720]; 2450 }; 2451 2452 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2453 u8 reserved_at_0[0x60]; 2454 2455 u8 reserved_at_60[0x4]; 2456 u8 clamp_tgt_rate[0x1]; 2457 u8 reserved_at_65[0x3]; 2458 u8 clamp_tgt_rate_after_time_inc[0x1]; 2459 u8 reserved_at_69[0x17]; 2460 2461 u8 reserved_at_80[0x20]; 2462 2463 u8 rpg_time_reset[0x20]; 2464 2465 u8 rpg_byte_reset[0x20]; 2466 2467 u8 rpg_threshold[0x20]; 2468 2469 u8 rpg_max_rate[0x20]; 2470 2471 u8 rpg_ai_rate[0x20]; 2472 2473 u8 rpg_hai_rate[0x20]; 2474 2475 u8 rpg_gd[0x20]; 2476 2477 u8 rpg_min_dec_fac[0x20]; 2478 2479 u8 rpg_min_rate[0x20]; 2480 2481 u8 reserved_at_1c0[0xe0]; 2482 2483 u8 rate_to_set_on_first_cnp[0x20]; 2484 2485 u8 dce_tcp_g[0x20]; 2486 2487 u8 dce_tcp_rtt[0x20]; 2488 2489 u8 rate_reduce_monitor_period[0x20]; 2490 2491 u8 reserved_at_320[0x20]; 2492 2493 u8 initial_alpha_value[0x20]; 2494 2495 u8 reserved_at_360[0x4a0]; 2496 }; 2497 2498 struct mlx5_ifc_cong_control_r_roce_general_bits { 2499 u8 reserved_at_0[0x80]; 2500 2501 u8 reserved_at_80[0x10]; 2502 u8 rtt_resp_dscp_valid[0x1]; 2503 u8 reserved_at_91[0x9]; 2504 u8 rtt_resp_dscp[0x6]; 2505 2506 u8 reserved_at_a0[0x760]; 2507 }; 2508 2509 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2510 u8 reserved_at_0[0x80]; 2511 2512 u8 rppp_max_rps[0x20]; 2513 2514 u8 rpg_time_reset[0x20]; 2515 2516 u8 rpg_byte_reset[0x20]; 2517 2518 u8 rpg_threshold[0x20]; 2519 2520 u8 rpg_max_rate[0x20]; 2521 2522 u8 rpg_ai_rate[0x20]; 2523 2524 u8 rpg_hai_rate[0x20]; 2525 2526 u8 rpg_gd[0x20]; 2527 2528 u8 rpg_min_dec_fac[0x20]; 2529 2530 u8 rpg_min_rate[0x20]; 2531 2532 u8 reserved_at_1c0[0x640]; 2533 }; 2534 2535 enum { 2536 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2537 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2538 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2539 }; 2540 2541 struct mlx5_ifc_resize_field_select_bits { 2542 u8 resize_field_select[0x20]; 2543 }; 2544 2545 struct mlx5_ifc_resource_dump_bits { 2546 u8 more_dump[0x1]; 2547 u8 inline_dump[0x1]; 2548 u8 reserved_at_2[0xa]; 2549 u8 seq_num[0x4]; 2550 u8 segment_type[0x10]; 2551 2552 u8 reserved_at_20[0x10]; 2553 u8 vhca_id[0x10]; 2554 2555 u8 index1[0x20]; 2556 2557 u8 index2[0x20]; 2558 2559 u8 num_of_obj1[0x10]; 2560 u8 num_of_obj2[0x10]; 2561 2562 u8 reserved_at_a0[0x20]; 2563 2564 u8 device_opaque[0x40]; 2565 2566 u8 mkey[0x20]; 2567 2568 u8 size[0x20]; 2569 2570 u8 address[0x40]; 2571 2572 u8 inline_data[52][0x20]; 2573 }; 2574 2575 struct mlx5_ifc_resource_dump_menu_record_bits { 2576 u8 reserved_at_0[0x4]; 2577 u8 num_of_obj2_supports_active[0x1]; 2578 u8 num_of_obj2_supports_all[0x1]; 2579 u8 must_have_num_of_obj2[0x1]; 2580 u8 support_num_of_obj2[0x1]; 2581 u8 num_of_obj1_supports_active[0x1]; 2582 u8 num_of_obj1_supports_all[0x1]; 2583 u8 must_have_num_of_obj1[0x1]; 2584 u8 support_num_of_obj1[0x1]; 2585 u8 must_have_index2[0x1]; 2586 u8 support_index2[0x1]; 2587 u8 must_have_index1[0x1]; 2588 u8 support_index1[0x1]; 2589 u8 segment_type[0x10]; 2590 2591 u8 segment_name[4][0x20]; 2592 2593 u8 index1_name[4][0x20]; 2594 2595 u8 index2_name[4][0x20]; 2596 }; 2597 2598 struct mlx5_ifc_resource_dump_segment_header_bits { 2599 u8 length_dw[0x10]; 2600 u8 segment_type[0x10]; 2601 }; 2602 2603 struct mlx5_ifc_resource_dump_command_segment_bits { 2604 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2605 2606 u8 segment_called[0x10]; 2607 u8 vhca_id[0x10]; 2608 2609 u8 index1[0x20]; 2610 2611 u8 index2[0x20]; 2612 2613 u8 num_of_obj1[0x10]; 2614 u8 num_of_obj2[0x10]; 2615 }; 2616 2617 struct mlx5_ifc_resource_dump_error_segment_bits { 2618 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2619 2620 u8 reserved_at_20[0x10]; 2621 u8 syndrome_id[0x10]; 2622 2623 u8 reserved_at_40[0x40]; 2624 2625 u8 error[8][0x20]; 2626 }; 2627 2628 struct mlx5_ifc_resource_dump_info_segment_bits { 2629 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2630 2631 u8 reserved_at_20[0x18]; 2632 u8 dump_version[0x8]; 2633 2634 u8 hw_version[0x20]; 2635 2636 u8 fw_version[0x20]; 2637 }; 2638 2639 struct mlx5_ifc_resource_dump_menu_segment_bits { 2640 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2641 2642 u8 reserved_at_20[0x10]; 2643 u8 num_of_records[0x10]; 2644 2645 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2646 }; 2647 2648 struct mlx5_ifc_resource_dump_resource_segment_bits { 2649 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2650 2651 u8 reserved_at_20[0x20]; 2652 2653 u8 index1[0x20]; 2654 2655 u8 index2[0x20]; 2656 2657 u8 payload[][0x20]; 2658 }; 2659 2660 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2661 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2662 }; 2663 2664 struct mlx5_ifc_menu_resource_dump_response_bits { 2665 struct mlx5_ifc_resource_dump_info_segment_bits info; 2666 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2667 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2668 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2669 }; 2670 2671 enum { 2672 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2673 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2674 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2675 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2676 }; 2677 2678 struct mlx5_ifc_modify_field_select_bits { 2679 u8 modify_field_select[0x20]; 2680 }; 2681 2682 struct mlx5_ifc_field_select_r_roce_np_bits { 2683 u8 field_select_r_roce_np[0x20]; 2684 }; 2685 2686 struct mlx5_ifc_field_select_r_roce_rp_bits { 2687 u8 field_select_r_roce_rp[0x20]; 2688 }; 2689 2690 enum { 2691 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2692 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2693 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2694 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2695 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2696 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2697 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2698 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2699 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2700 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2701 }; 2702 2703 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2704 u8 field_select_8021qaurp[0x20]; 2705 }; 2706 2707 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2708 u8 total_successful_recovery_events[0x20]; 2709 2710 u8 reserved_at_20[0x7a0]; 2711 }; 2712 2713 struct mlx5_ifc_phys_layer_cntrs_bits { 2714 u8 time_since_last_clear_high[0x20]; 2715 2716 u8 time_since_last_clear_low[0x20]; 2717 2718 u8 symbol_errors_high[0x20]; 2719 2720 u8 symbol_errors_low[0x20]; 2721 2722 u8 sync_headers_errors_high[0x20]; 2723 2724 u8 sync_headers_errors_low[0x20]; 2725 2726 u8 edpl_bip_errors_lane0_high[0x20]; 2727 2728 u8 edpl_bip_errors_lane0_low[0x20]; 2729 2730 u8 edpl_bip_errors_lane1_high[0x20]; 2731 2732 u8 edpl_bip_errors_lane1_low[0x20]; 2733 2734 u8 edpl_bip_errors_lane2_high[0x20]; 2735 2736 u8 edpl_bip_errors_lane2_low[0x20]; 2737 2738 u8 edpl_bip_errors_lane3_high[0x20]; 2739 2740 u8 edpl_bip_errors_lane3_low[0x20]; 2741 2742 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2743 2744 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2745 2746 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2747 2748 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2749 2750 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2751 2752 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2753 2754 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2755 2756 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2757 2758 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2759 2760 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2761 2762 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2763 2764 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2765 2766 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2767 2768 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2769 2770 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2771 2772 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2773 2774 u8 rs_fec_corrected_blocks_high[0x20]; 2775 2776 u8 rs_fec_corrected_blocks_low[0x20]; 2777 2778 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2779 2780 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2781 2782 u8 rs_fec_no_errors_blocks_high[0x20]; 2783 2784 u8 rs_fec_no_errors_blocks_low[0x20]; 2785 2786 u8 rs_fec_single_error_blocks_high[0x20]; 2787 2788 u8 rs_fec_single_error_blocks_low[0x20]; 2789 2790 u8 rs_fec_corrected_symbols_total_high[0x20]; 2791 2792 u8 rs_fec_corrected_symbols_total_low[0x20]; 2793 2794 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2795 2796 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2797 2798 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2799 2800 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2801 2802 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2803 2804 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2805 2806 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2807 2808 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2809 2810 u8 link_down_events[0x20]; 2811 2812 u8 successful_recovery_events[0x20]; 2813 2814 u8 reserved_at_640[0x180]; 2815 }; 2816 2817 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2818 u8 time_since_last_clear_high[0x20]; 2819 2820 u8 time_since_last_clear_low[0x20]; 2821 2822 u8 phy_received_bits_high[0x20]; 2823 2824 u8 phy_received_bits_low[0x20]; 2825 2826 u8 phy_symbol_errors_high[0x20]; 2827 2828 u8 phy_symbol_errors_low[0x20]; 2829 2830 u8 phy_corrected_bits_high[0x20]; 2831 2832 u8 phy_corrected_bits_low[0x20]; 2833 2834 u8 phy_corrected_bits_lane0_high[0x20]; 2835 2836 u8 phy_corrected_bits_lane0_low[0x20]; 2837 2838 u8 phy_corrected_bits_lane1_high[0x20]; 2839 2840 u8 phy_corrected_bits_lane1_low[0x20]; 2841 2842 u8 phy_corrected_bits_lane2_high[0x20]; 2843 2844 u8 phy_corrected_bits_lane2_low[0x20]; 2845 2846 u8 phy_corrected_bits_lane3_high[0x20]; 2847 2848 u8 phy_corrected_bits_lane3_low[0x20]; 2849 2850 u8 reserved_at_200[0x5c0]; 2851 }; 2852 2853 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2854 u8 symbol_error_counter[0x10]; 2855 2856 u8 link_error_recovery_counter[0x8]; 2857 2858 u8 link_downed_counter[0x8]; 2859 2860 u8 port_rcv_errors[0x10]; 2861 2862 u8 port_rcv_remote_physical_errors[0x10]; 2863 2864 u8 port_rcv_switch_relay_errors[0x10]; 2865 2866 u8 port_xmit_discards[0x10]; 2867 2868 u8 port_xmit_constraint_errors[0x8]; 2869 2870 u8 port_rcv_constraint_errors[0x8]; 2871 2872 u8 reserved_at_70[0x8]; 2873 2874 u8 link_overrun_errors[0x8]; 2875 2876 u8 reserved_at_80[0x10]; 2877 2878 u8 vl_15_dropped[0x10]; 2879 2880 u8 reserved_at_a0[0x80]; 2881 2882 u8 port_xmit_wait[0x20]; 2883 }; 2884 2885 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2886 u8 reserved_at_0[0x300]; 2887 2888 u8 port_xmit_data_high[0x20]; 2889 2890 u8 port_xmit_data_low[0x20]; 2891 2892 u8 port_rcv_data_high[0x20]; 2893 2894 u8 port_rcv_data_low[0x20]; 2895 2896 u8 port_xmit_pkts_high[0x20]; 2897 2898 u8 port_xmit_pkts_low[0x20]; 2899 2900 u8 port_rcv_pkts_high[0x20]; 2901 2902 u8 port_rcv_pkts_low[0x20]; 2903 2904 u8 reserved_at_400[0x80]; 2905 2906 u8 port_unicast_xmit_pkts_high[0x20]; 2907 2908 u8 port_unicast_xmit_pkts_low[0x20]; 2909 2910 u8 port_multicast_xmit_pkts_high[0x20]; 2911 2912 u8 port_multicast_xmit_pkts_low[0x20]; 2913 2914 u8 port_unicast_rcv_pkts_high[0x20]; 2915 2916 u8 port_unicast_rcv_pkts_low[0x20]; 2917 2918 u8 port_multicast_rcv_pkts_high[0x20]; 2919 2920 u8 port_multicast_rcv_pkts_low[0x20]; 2921 2922 u8 reserved_at_580[0x240]; 2923 }; 2924 2925 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2926 u8 transmit_queue_high[0x20]; 2927 2928 u8 transmit_queue_low[0x20]; 2929 2930 u8 no_buffer_discard_uc_high[0x20]; 2931 2932 u8 no_buffer_discard_uc_low[0x20]; 2933 2934 u8 reserved_at_80[0x740]; 2935 }; 2936 2937 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2938 u8 wred_discard_high[0x20]; 2939 2940 u8 wred_discard_low[0x20]; 2941 2942 u8 ecn_marked_tc_high[0x20]; 2943 2944 u8 ecn_marked_tc_low[0x20]; 2945 2946 u8 reserved_at_80[0x740]; 2947 }; 2948 2949 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2950 u8 rx_octets_high[0x20]; 2951 2952 u8 rx_octets_low[0x20]; 2953 2954 u8 reserved_at_40[0xc0]; 2955 2956 u8 rx_frames_high[0x20]; 2957 2958 u8 rx_frames_low[0x20]; 2959 2960 u8 tx_octets_high[0x20]; 2961 2962 u8 tx_octets_low[0x20]; 2963 2964 u8 reserved_at_180[0xc0]; 2965 2966 u8 tx_frames_high[0x20]; 2967 2968 u8 tx_frames_low[0x20]; 2969 2970 u8 rx_pause_high[0x20]; 2971 2972 u8 rx_pause_low[0x20]; 2973 2974 u8 rx_pause_duration_high[0x20]; 2975 2976 u8 rx_pause_duration_low[0x20]; 2977 2978 u8 tx_pause_high[0x20]; 2979 2980 u8 tx_pause_low[0x20]; 2981 2982 u8 tx_pause_duration_high[0x20]; 2983 2984 u8 tx_pause_duration_low[0x20]; 2985 2986 u8 rx_pause_transition_high[0x20]; 2987 2988 u8 rx_pause_transition_low[0x20]; 2989 2990 u8 rx_discards_high[0x20]; 2991 2992 u8 rx_discards_low[0x20]; 2993 2994 u8 device_stall_minor_watermark_cnt_high[0x20]; 2995 2996 u8 device_stall_minor_watermark_cnt_low[0x20]; 2997 2998 u8 device_stall_critical_watermark_cnt_high[0x20]; 2999 3000 u8 device_stall_critical_watermark_cnt_low[0x20]; 3001 3002 u8 reserved_at_480[0x340]; 3003 }; 3004 3005 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 3006 u8 port_transmit_wait_high[0x20]; 3007 3008 u8 port_transmit_wait_low[0x20]; 3009 3010 u8 reserved_at_40[0x100]; 3011 3012 u8 rx_buffer_almost_full_high[0x20]; 3013 3014 u8 rx_buffer_almost_full_low[0x20]; 3015 3016 u8 rx_buffer_full_high[0x20]; 3017 3018 u8 rx_buffer_full_low[0x20]; 3019 3020 u8 rx_icrc_encapsulated_high[0x20]; 3021 3022 u8 rx_icrc_encapsulated_low[0x20]; 3023 3024 u8 reserved_at_200[0x5c0]; 3025 }; 3026 3027 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3028 u8 dot3stats_alignment_errors_high[0x20]; 3029 3030 u8 dot3stats_alignment_errors_low[0x20]; 3031 3032 u8 dot3stats_fcs_errors_high[0x20]; 3033 3034 u8 dot3stats_fcs_errors_low[0x20]; 3035 3036 u8 dot3stats_single_collision_frames_high[0x20]; 3037 3038 u8 dot3stats_single_collision_frames_low[0x20]; 3039 3040 u8 dot3stats_multiple_collision_frames_high[0x20]; 3041 3042 u8 dot3stats_multiple_collision_frames_low[0x20]; 3043 3044 u8 dot3stats_sqe_test_errors_high[0x20]; 3045 3046 u8 dot3stats_sqe_test_errors_low[0x20]; 3047 3048 u8 dot3stats_deferred_transmissions_high[0x20]; 3049 3050 u8 dot3stats_deferred_transmissions_low[0x20]; 3051 3052 u8 dot3stats_late_collisions_high[0x20]; 3053 3054 u8 dot3stats_late_collisions_low[0x20]; 3055 3056 u8 dot3stats_excessive_collisions_high[0x20]; 3057 3058 u8 dot3stats_excessive_collisions_low[0x20]; 3059 3060 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3061 3062 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3063 3064 u8 dot3stats_carrier_sense_errors_high[0x20]; 3065 3066 u8 dot3stats_carrier_sense_errors_low[0x20]; 3067 3068 u8 dot3stats_frame_too_longs_high[0x20]; 3069 3070 u8 dot3stats_frame_too_longs_low[0x20]; 3071 3072 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3073 3074 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3075 3076 u8 dot3stats_symbol_errors_high[0x20]; 3077 3078 u8 dot3stats_symbol_errors_low[0x20]; 3079 3080 u8 dot3control_in_unknown_opcodes_high[0x20]; 3081 3082 u8 dot3control_in_unknown_opcodes_low[0x20]; 3083 3084 u8 dot3in_pause_frames_high[0x20]; 3085 3086 u8 dot3in_pause_frames_low[0x20]; 3087 3088 u8 dot3out_pause_frames_high[0x20]; 3089 3090 u8 dot3out_pause_frames_low[0x20]; 3091 3092 u8 reserved_at_400[0x3c0]; 3093 }; 3094 3095 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3096 u8 ether_stats_drop_events_high[0x20]; 3097 3098 u8 ether_stats_drop_events_low[0x20]; 3099 3100 u8 ether_stats_octets_high[0x20]; 3101 3102 u8 ether_stats_octets_low[0x20]; 3103 3104 u8 ether_stats_pkts_high[0x20]; 3105 3106 u8 ether_stats_pkts_low[0x20]; 3107 3108 u8 ether_stats_broadcast_pkts_high[0x20]; 3109 3110 u8 ether_stats_broadcast_pkts_low[0x20]; 3111 3112 u8 ether_stats_multicast_pkts_high[0x20]; 3113 3114 u8 ether_stats_multicast_pkts_low[0x20]; 3115 3116 u8 ether_stats_crc_align_errors_high[0x20]; 3117 3118 u8 ether_stats_crc_align_errors_low[0x20]; 3119 3120 u8 ether_stats_undersize_pkts_high[0x20]; 3121 3122 u8 ether_stats_undersize_pkts_low[0x20]; 3123 3124 u8 ether_stats_oversize_pkts_high[0x20]; 3125 3126 u8 ether_stats_oversize_pkts_low[0x20]; 3127 3128 u8 ether_stats_fragments_high[0x20]; 3129 3130 u8 ether_stats_fragments_low[0x20]; 3131 3132 u8 ether_stats_jabbers_high[0x20]; 3133 3134 u8 ether_stats_jabbers_low[0x20]; 3135 3136 u8 ether_stats_collisions_high[0x20]; 3137 3138 u8 ether_stats_collisions_low[0x20]; 3139 3140 u8 ether_stats_pkts64octets_high[0x20]; 3141 3142 u8 ether_stats_pkts64octets_low[0x20]; 3143 3144 u8 ether_stats_pkts65to127octets_high[0x20]; 3145 3146 u8 ether_stats_pkts65to127octets_low[0x20]; 3147 3148 u8 ether_stats_pkts128to255octets_high[0x20]; 3149 3150 u8 ether_stats_pkts128to255octets_low[0x20]; 3151 3152 u8 ether_stats_pkts256to511octets_high[0x20]; 3153 3154 u8 ether_stats_pkts256to511octets_low[0x20]; 3155 3156 u8 ether_stats_pkts512to1023octets_high[0x20]; 3157 3158 u8 ether_stats_pkts512to1023octets_low[0x20]; 3159 3160 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3161 3162 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3163 3164 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3165 3166 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3167 3168 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3169 3170 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3171 3172 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3173 3174 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3175 3176 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3177 3178 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3179 3180 u8 reserved_at_540[0x280]; 3181 }; 3182 3183 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3184 u8 if_in_octets_high[0x20]; 3185 3186 u8 if_in_octets_low[0x20]; 3187 3188 u8 if_in_ucast_pkts_high[0x20]; 3189 3190 u8 if_in_ucast_pkts_low[0x20]; 3191 3192 u8 if_in_discards_high[0x20]; 3193 3194 u8 if_in_discards_low[0x20]; 3195 3196 u8 if_in_errors_high[0x20]; 3197 3198 u8 if_in_errors_low[0x20]; 3199 3200 u8 if_in_unknown_protos_high[0x20]; 3201 3202 u8 if_in_unknown_protos_low[0x20]; 3203 3204 u8 if_out_octets_high[0x20]; 3205 3206 u8 if_out_octets_low[0x20]; 3207 3208 u8 if_out_ucast_pkts_high[0x20]; 3209 3210 u8 if_out_ucast_pkts_low[0x20]; 3211 3212 u8 if_out_discards_high[0x20]; 3213 3214 u8 if_out_discards_low[0x20]; 3215 3216 u8 if_out_errors_high[0x20]; 3217 3218 u8 if_out_errors_low[0x20]; 3219 3220 u8 if_in_multicast_pkts_high[0x20]; 3221 3222 u8 if_in_multicast_pkts_low[0x20]; 3223 3224 u8 if_in_broadcast_pkts_high[0x20]; 3225 3226 u8 if_in_broadcast_pkts_low[0x20]; 3227 3228 u8 if_out_multicast_pkts_high[0x20]; 3229 3230 u8 if_out_multicast_pkts_low[0x20]; 3231 3232 u8 if_out_broadcast_pkts_high[0x20]; 3233 3234 u8 if_out_broadcast_pkts_low[0x20]; 3235 3236 u8 reserved_at_340[0x480]; 3237 }; 3238 3239 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3240 u8 a_frames_transmitted_ok_high[0x20]; 3241 3242 u8 a_frames_transmitted_ok_low[0x20]; 3243 3244 u8 a_frames_received_ok_high[0x20]; 3245 3246 u8 a_frames_received_ok_low[0x20]; 3247 3248 u8 a_frame_check_sequence_errors_high[0x20]; 3249 3250 u8 a_frame_check_sequence_errors_low[0x20]; 3251 3252 u8 a_alignment_errors_high[0x20]; 3253 3254 u8 a_alignment_errors_low[0x20]; 3255 3256 u8 a_octets_transmitted_ok_high[0x20]; 3257 3258 u8 a_octets_transmitted_ok_low[0x20]; 3259 3260 u8 a_octets_received_ok_high[0x20]; 3261 3262 u8 a_octets_received_ok_low[0x20]; 3263 3264 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3265 3266 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3267 3268 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3269 3270 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3271 3272 u8 a_multicast_frames_received_ok_high[0x20]; 3273 3274 u8 a_multicast_frames_received_ok_low[0x20]; 3275 3276 u8 a_broadcast_frames_received_ok_high[0x20]; 3277 3278 u8 a_broadcast_frames_received_ok_low[0x20]; 3279 3280 u8 a_in_range_length_errors_high[0x20]; 3281 3282 u8 a_in_range_length_errors_low[0x20]; 3283 3284 u8 a_out_of_range_length_field_high[0x20]; 3285 3286 u8 a_out_of_range_length_field_low[0x20]; 3287 3288 u8 a_frame_too_long_errors_high[0x20]; 3289 3290 u8 a_frame_too_long_errors_low[0x20]; 3291 3292 u8 a_symbol_error_during_carrier_high[0x20]; 3293 3294 u8 a_symbol_error_during_carrier_low[0x20]; 3295 3296 u8 a_mac_control_frames_transmitted_high[0x20]; 3297 3298 u8 a_mac_control_frames_transmitted_low[0x20]; 3299 3300 u8 a_mac_control_frames_received_high[0x20]; 3301 3302 u8 a_mac_control_frames_received_low[0x20]; 3303 3304 u8 a_unsupported_opcodes_received_high[0x20]; 3305 3306 u8 a_unsupported_opcodes_received_low[0x20]; 3307 3308 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3309 3310 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3311 3312 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3313 3314 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3315 3316 u8 reserved_at_4c0[0x300]; 3317 }; 3318 3319 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3320 u8 life_time_counter_high[0x20]; 3321 3322 u8 life_time_counter_low[0x20]; 3323 3324 u8 rx_errors[0x20]; 3325 3326 u8 tx_errors[0x20]; 3327 3328 u8 l0_to_recovery_eieos[0x20]; 3329 3330 u8 l0_to_recovery_ts[0x20]; 3331 3332 u8 l0_to_recovery_framing[0x20]; 3333 3334 u8 l0_to_recovery_retrain[0x20]; 3335 3336 u8 crc_error_dllp[0x20]; 3337 3338 u8 crc_error_tlp[0x20]; 3339 3340 u8 tx_overflow_buffer_pkt_high[0x20]; 3341 3342 u8 tx_overflow_buffer_pkt_low[0x20]; 3343 3344 u8 outbound_stalled_reads[0x20]; 3345 3346 u8 outbound_stalled_writes[0x20]; 3347 3348 u8 outbound_stalled_reads_events[0x20]; 3349 3350 u8 outbound_stalled_writes_events[0x20]; 3351 3352 u8 reserved_at_200[0x5c0]; 3353 }; 3354 3355 struct mlx5_ifc_cmd_inter_comp_event_bits { 3356 u8 command_completion_vector[0x20]; 3357 3358 u8 reserved_at_20[0xc0]; 3359 }; 3360 3361 struct mlx5_ifc_stall_vl_event_bits { 3362 u8 reserved_at_0[0x18]; 3363 u8 port_num[0x1]; 3364 u8 reserved_at_19[0x3]; 3365 u8 vl[0x4]; 3366 3367 u8 reserved_at_20[0xa0]; 3368 }; 3369 3370 struct mlx5_ifc_db_bf_congestion_event_bits { 3371 u8 event_subtype[0x8]; 3372 u8 reserved_at_8[0x8]; 3373 u8 congestion_level[0x8]; 3374 u8 reserved_at_18[0x8]; 3375 3376 u8 reserved_at_20[0xa0]; 3377 }; 3378 3379 struct mlx5_ifc_gpio_event_bits { 3380 u8 reserved_at_0[0x60]; 3381 3382 u8 gpio_event_hi[0x20]; 3383 3384 u8 gpio_event_lo[0x20]; 3385 3386 u8 reserved_at_a0[0x40]; 3387 }; 3388 3389 struct mlx5_ifc_port_state_change_event_bits { 3390 u8 reserved_at_0[0x40]; 3391 3392 u8 port_num[0x4]; 3393 u8 reserved_at_44[0x1c]; 3394 3395 u8 reserved_at_60[0x80]; 3396 }; 3397 3398 struct mlx5_ifc_dropped_packet_logged_bits { 3399 u8 reserved_at_0[0xe0]; 3400 }; 3401 3402 struct mlx5_ifc_nic_cap_reg_bits { 3403 u8 reserved_at_0[0x1a]; 3404 u8 vhca_icm_ctrl[0x1]; 3405 u8 reserved_at_1b[0x5]; 3406 3407 u8 reserved_at_20[0x60]; 3408 }; 3409 3410 struct mlx5_ifc_default_timeout_bits { 3411 u8 to_multiplier[0x3]; 3412 u8 reserved_at_3[0x9]; 3413 u8 to_value[0x14]; 3414 }; 3415 3416 struct mlx5_ifc_dtor_reg_bits { 3417 u8 reserved_at_0[0x20]; 3418 3419 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3420 3421 u8 reserved_at_40[0x60]; 3422 3423 struct mlx5_ifc_default_timeout_bits health_poll_to; 3424 3425 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3426 3427 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3428 3429 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3430 3431 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3432 3433 struct mlx5_ifc_default_timeout_bits tear_down_to; 3434 3435 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3436 3437 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3438 3439 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3440 3441 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3442 3443 u8 reserved_at_1c0[0x20]; 3444 }; 3445 3446 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3447 u8 vhca_id_valid[0x1]; 3448 u8 reserved_at_1[0xf]; 3449 u8 vhca_id[0x10]; 3450 3451 u8 reserved_at_20[0xa0]; 3452 3453 u8 cur_alloc_icm[0x20]; 3454 3455 u8 reserved_at_e0[0x120]; 3456 }; 3457 3458 enum { 3459 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3460 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3461 }; 3462 3463 struct mlx5_ifc_cq_error_bits { 3464 u8 reserved_at_0[0x8]; 3465 u8 cqn[0x18]; 3466 3467 u8 reserved_at_20[0x20]; 3468 3469 u8 reserved_at_40[0x18]; 3470 u8 syndrome[0x8]; 3471 3472 u8 reserved_at_60[0x80]; 3473 }; 3474 3475 struct mlx5_ifc_rdma_page_fault_event_bits { 3476 u8 bytes_committed[0x20]; 3477 3478 u8 r_key[0x20]; 3479 3480 u8 reserved_at_40[0x10]; 3481 u8 packet_len[0x10]; 3482 3483 u8 rdma_op_len[0x20]; 3484 3485 u8 rdma_va[0x40]; 3486 3487 u8 reserved_at_c0[0x5]; 3488 u8 rdma[0x1]; 3489 u8 write[0x1]; 3490 u8 requestor[0x1]; 3491 u8 qp_number[0x18]; 3492 }; 3493 3494 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3495 u8 bytes_committed[0x20]; 3496 3497 u8 reserved_at_20[0x10]; 3498 u8 wqe_index[0x10]; 3499 3500 u8 reserved_at_40[0x10]; 3501 u8 len[0x10]; 3502 3503 u8 reserved_at_60[0x60]; 3504 3505 u8 reserved_at_c0[0x5]; 3506 u8 rdma[0x1]; 3507 u8 write_read[0x1]; 3508 u8 requestor[0x1]; 3509 u8 qpn[0x18]; 3510 }; 3511 3512 struct mlx5_ifc_qp_events_bits { 3513 u8 reserved_at_0[0xa0]; 3514 3515 u8 type[0x8]; 3516 u8 reserved_at_a8[0x18]; 3517 3518 u8 reserved_at_c0[0x8]; 3519 u8 qpn_rqn_sqn[0x18]; 3520 }; 3521 3522 struct mlx5_ifc_dct_events_bits { 3523 u8 reserved_at_0[0xc0]; 3524 3525 u8 reserved_at_c0[0x8]; 3526 u8 dct_number[0x18]; 3527 }; 3528 3529 struct mlx5_ifc_comp_event_bits { 3530 u8 reserved_at_0[0xc0]; 3531 3532 u8 reserved_at_c0[0x8]; 3533 u8 cq_number[0x18]; 3534 }; 3535 3536 enum { 3537 MLX5_QPC_STATE_RST = 0x0, 3538 MLX5_QPC_STATE_INIT = 0x1, 3539 MLX5_QPC_STATE_RTR = 0x2, 3540 MLX5_QPC_STATE_RTS = 0x3, 3541 MLX5_QPC_STATE_SQER = 0x4, 3542 MLX5_QPC_STATE_ERR = 0x6, 3543 MLX5_QPC_STATE_SQD = 0x7, 3544 MLX5_QPC_STATE_SUSPENDED = 0x9, 3545 }; 3546 3547 enum { 3548 MLX5_QPC_ST_RC = 0x0, 3549 MLX5_QPC_ST_UC = 0x1, 3550 MLX5_QPC_ST_UD = 0x2, 3551 MLX5_QPC_ST_XRC = 0x3, 3552 MLX5_QPC_ST_DCI = 0x5, 3553 MLX5_QPC_ST_QP0 = 0x7, 3554 MLX5_QPC_ST_QP1 = 0x8, 3555 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3556 MLX5_QPC_ST_REG_UMR = 0xc, 3557 }; 3558 3559 enum { 3560 MLX5_QPC_PM_STATE_ARMED = 0x0, 3561 MLX5_QPC_PM_STATE_REARM = 0x1, 3562 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3563 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3564 }; 3565 3566 enum { 3567 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3568 }; 3569 3570 enum { 3571 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3572 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3573 }; 3574 3575 enum { 3576 MLX5_QPC_MTU_256_BYTES = 0x1, 3577 MLX5_QPC_MTU_512_BYTES = 0x2, 3578 MLX5_QPC_MTU_1K_BYTES = 0x3, 3579 MLX5_QPC_MTU_2K_BYTES = 0x4, 3580 MLX5_QPC_MTU_4K_BYTES = 0x5, 3581 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3582 }; 3583 3584 enum { 3585 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3586 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3587 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3588 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3589 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3590 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3591 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3592 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3593 }; 3594 3595 enum { 3596 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3597 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3598 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3599 }; 3600 3601 enum { 3602 MLX5_QPC_CS_RES_DISABLE = 0x0, 3603 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3604 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3605 }; 3606 3607 enum { 3608 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3609 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3610 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3611 }; 3612 3613 struct mlx5_ifc_qpc_bits { 3614 u8 state[0x4]; 3615 u8 lag_tx_port_affinity[0x4]; 3616 u8 st[0x8]; 3617 u8 reserved_at_10[0x2]; 3618 u8 isolate_vl_tc[0x1]; 3619 u8 pm_state[0x2]; 3620 u8 reserved_at_15[0x1]; 3621 u8 req_e2e_credit_mode[0x2]; 3622 u8 offload_type[0x4]; 3623 u8 end_padding_mode[0x2]; 3624 u8 reserved_at_1e[0x2]; 3625 3626 u8 wq_signature[0x1]; 3627 u8 block_lb_mc[0x1]; 3628 u8 atomic_like_write_en[0x1]; 3629 u8 latency_sensitive[0x1]; 3630 u8 reserved_at_24[0x1]; 3631 u8 drain_sigerr[0x1]; 3632 u8 reserved_at_26[0x1]; 3633 u8 dp_ordering_force[0x1]; 3634 u8 pd[0x18]; 3635 3636 u8 mtu[0x3]; 3637 u8 log_msg_max[0x5]; 3638 u8 reserved_at_48[0x1]; 3639 u8 log_rq_size[0x4]; 3640 u8 log_rq_stride[0x3]; 3641 u8 no_sq[0x1]; 3642 u8 log_sq_size[0x4]; 3643 u8 reserved_at_55[0x1]; 3644 u8 retry_mode[0x2]; 3645 u8 ts_format[0x2]; 3646 u8 reserved_at_5a[0x1]; 3647 u8 rlky[0x1]; 3648 u8 ulp_stateless_offload_mode[0x4]; 3649 3650 u8 counter_set_id[0x8]; 3651 u8 uar_page[0x18]; 3652 3653 u8 reserved_at_80[0x8]; 3654 u8 user_index[0x18]; 3655 3656 u8 reserved_at_a0[0x3]; 3657 u8 log_page_size[0x5]; 3658 u8 remote_qpn[0x18]; 3659 3660 struct mlx5_ifc_ads_bits primary_address_path; 3661 3662 struct mlx5_ifc_ads_bits secondary_address_path; 3663 3664 u8 log_ack_req_freq[0x4]; 3665 u8 reserved_at_384[0x4]; 3666 u8 log_sra_max[0x3]; 3667 u8 reserved_at_38b[0x2]; 3668 u8 retry_count[0x3]; 3669 u8 rnr_retry[0x3]; 3670 u8 reserved_at_393[0x1]; 3671 u8 fre[0x1]; 3672 u8 cur_rnr_retry[0x3]; 3673 u8 cur_retry_count[0x3]; 3674 u8 reserved_at_39b[0x5]; 3675 3676 u8 reserved_at_3a0[0x20]; 3677 3678 u8 reserved_at_3c0[0x8]; 3679 u8 next_send_psn[0x18]; 3680 3681 u8 reserved_at_3e0[0x3]; 3682 u8 log_num_dci_stream_channels[0x5]; 3683 u8 cqn_snd[0x18]; 3684 3685 u8 reserved_at_400[0x3]; 3686 u8 log_num_dci_errored_streams[0x5]; 3687 u8 deth_sqpn[0x18]; 3688 3689 u8 reserved_at_420[0x20]; 3690 3691 u8 reserved_at_440[0x8]; 3692 u8 last_acked_psn[0x18]; 3693 3694 u8 reserved_at_460[0x8]; 3695 u8 ssn[0x18]; 3696 3697 u8 reserved_at_480[0x8]; 3698 u8 log_rra_max[0x3]; 3699 u8 reserved_at_48b[0x1]; 3700 u8 atomic_mode[0x4]; 3701 u8 rre[0x1]; 3702 u8 rwe[0x1]; 3703 u8 rae[0x1]; 3704 u8 reserved_at_493[0x1]; 3705 u8 page_offset[0x6]; 3706 u8 reserved_at_49a[0x2]; 3707 u8 dp_ordering_1[0x1]; 3708 u8 cd_slave_receive[0x1]; 3709 u8 cd_slave_send[0x1]; 3710 u8 cd_master[0x1]; 3711 3712 u8 reserved_at_4a0[0x3]; 3713 u8 min_rnr_nak[0x5]; 3714 u8 next_rcv_psn[0x18]; 3715 3716 u8 reserved_at_4c0[0x8]; 3717 u8 xrcd[0x18]; 3718 3719 u8 reserved_at_4e0[0x8]; 3720 u8 cqn_rcv[0x18]; 3721 3722 u8 dbr_addr[0x40]; 3723 3724 u8 q_key[0x20]; 3725 3726 u8 reserved_at_560[0x5]; 3727 u8 rq_type[0x3]; 3728 u8 srqn_rmpn_xrqn[0x18]; 3729 3730 u8 reserved_at_580[0x8]; 3731 u8 rmsn[0x18]; 3732 3733 u8 hw_sq_wqebb_counter[0x10]; 3734 u8 sw_sq_wqebb_counter[0x10]; 3735 3736 u8 hw_rq_counter[0x20]; 3737 3738 u8 sw_rq_counter[0x20]; 3739 3740 u8 reserved_at_600[0x20]; 3741 3742 u8 reserved_at_620[0xf]; 3743 u8 cgs[0x1]; 3744 u8 cs_req[0x8]; 3745 u8 cs_res[0x8]; 3746 3747 u8 dc_access_key[0x40]; 3748 3749 u8 reserved_at_680[0x3]; 3750 u8 dbr_umem_valid[0x1]; 3751 3752 u8 reserved_at_684[0xbc]; 3753 }; 3754 3755 struct mlx5_ifc_roce_addr_layout_bits { 3756 u8 source_l3_address[16][0x8]; 3757 3758 u8 reserved_at_80[0x3]; 3759 u8 vlan_valid[0x1]; 3760 u8 vlan_id[0xc]; 3761 u8 source_mac_47_32[0x10]; 3762 3763 u8 source_mac_31_0[0x20]; 3764 3765 u8 reserved_at_c0[0x14]; 3766 u8 roce_l3_type[0x4]; 3767 u8 roce_version[0x8]; 3768 3769 u8 reserved_at_e0[0x20]; 3770 }; 3771 3772 struct mlx5_ifc_crypto_cap_bits { 3773 u8 reserved_at_0[0x3]; 3774 u8 synchronize_dek[0x1]; 3775 u8 int_kek_manual[0x1]; 3776 u8 int_kek_auto[0x1]; 3777 u8 reserved_at_6[0x1a]; 3778 3779 u8 reserved_at_20[0x3]; 3780 u8 log_dek_max_alloc[0x5]; 3781 u8 reserved_at_28[0x3]; 3782 u8 log_max_num_deks[0x5]; 3783 u8 reserved_at_30[0x10]; 3784 3785 u8 reserved_at_40[0x20]; 3786 3787 u8 reserved_at_60[0x3]; 3788 u8 log_dek_granularity[0x5]; 3789 u8 reserved_at_68[0x3]; 3790 u8 log_max_num_int_kek[0x5]; 3791 u8 sw_wrapped_dek[0x10]; 3792 3793 u8 reserved_at_80[0x780]; 3794 }; 3795 3796 struct mlx5_ifc_shampo_cap_bits { 3797 u8 reserved_at_0[0x3]; 3798 u8 shampo_log_max_reservation_size[0x5]; 3799 u8 reserved_at_8[0x3]; 3800 u8 shampo_log_min_reservation_size[0x5]; 3801 u8 shampo_min_mss_size[0x10]; 3802 3803 u8 shampo_header_split[0x1]; 3804 u8 shampo_header_split_data_merge[0x1]; 3805 u8 reserved_at_22[0x1]; 3806 u8 shampo_log_max_headers_entry_size[0x5]; 3807 u8 reserved_at_28[0x18]; 3808 3809 u8 reserved_at_40[0x7c0]; 3810 }; 3811 3812 union mlx5_ifc_hca_cap_union_bits { 3813 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3814 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3815 struct mlx5_ifc_odp_cap_bits odp_cap; 3816 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3817 struct mlx5_ifc_roce_cap_bits roce_cap; 3818 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3819 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3820 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3821 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3822 struct mlx5_ifc_esw_cap_bits esw_cap; 3823 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3824 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3825 struct mlx5_ifc_qos_cap_bits qos_cap; 3826 struct mlx5_ifc_debug_cap_bits debug_cap; 3827 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3828 struct mlx5_ifc_tls_cap_bits tls_cap; 3829 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3830 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3831 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3832 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3833 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3834 struct mlx5_ifc_psp_cap_bits psp_cap; 3835 u8 reserved_at_0[0x8000]; 3836 }; 3837 3838 enum { 3839 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3840 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3841 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3842 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3843 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3844 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3845 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3846 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3847 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3848 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3849 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3850 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3851 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3852 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3853 }; 3854 3855 enum { 3856 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3857 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3858 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3859 }; 3860 3861 enum { 3862 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3863 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3864 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3865 }; 3866 3867 struct mlx5_ifc_vlan_bits { 3868 u8 ethtype[0x10]; 3869 u8 prio[0x3]; 3870 u8 cfi[0x1]; 3871 u8 vid[0xc]; 3872 }; 3873 3874 enum { 3875 MLX5_FLOW_METER_COLOR_RED = 0x0, 3876 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3877 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3878 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3879 }; 3880 3881 enum { 3882 MLX5_EXE_ASO_FLOW_METER = 0x2, 3883 }; 3884 3885 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3886 u8 return_reg_id[0x4]; 3887 u8 aso_type[0x4]; 3888 u8 reserved_at_8[0x14]; 3889 u8 action[0x1]; 3890 u8 init_color[0x2]; 3891 u8 meter_id[0x1]; 3892 }; 3893 3894 union mlx5_ifc_exe_aso_ctrl { 3895 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3896 }; 3897 3898 struct mlx5_ifc_execute_aso_bits { 3899 u8 valid[0x1]; 3900 u8 reserved_at_1[0x7]; 3901 u8 aso_object_id[0x18]; 3902 3903 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3904 }; 3905 3906 struct mlx5_ifc_flow_context_bits { 3907 struct mlx5_ifc_vlan_bits push_vlan; 3908 3909 u8 group_id[0x20]; 3910 3911 u8 reserved_at_40[0x8]; 3912 u8 flow_tag[0x18]; 3913 3914 u8 reserved_at_60[0x10]; 3915 u8 action[0x10]; 3916 3917 u8 extended_destination[0x1]; 3918 u8 uplink_hairpin_en[0x1]; 3919 u8 flow_source[0x2]; 3920 u8 encrypt_decrypt_type[0x4]; 3921 u8 destination_list_size[0x18]; 3922 3923 u8 reserved_at_a0[0x8]; 3924 u8 flow_counter_list_size[0x18]; 3925 3926 u8 packet_reformat_id[0x20]; 3927 3928 u8 modify_header_id[0x20]; 3929 3930 struct mlx5_ifc_vlan_bits push_vlan_2; 3931 3932 u8 encrypt_decrypt_obj_id[0x20]; 3933 u8 reserved_at_140[0xc0]; 3934 3935 struct mlx5_ifc_fte_match_param_bits match_value; 3936 3937 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3938 3939 u8 reserved_at_1300[0x500]; 3940 3941 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3942 }; 3943 3944 enum { 3945 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3946 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3947 }; 3948 3949 struct mlx5_ifc_xrc_srqc_bits { 3950 u8 state[0x4]; 3951 u8 log_xrc_srq_size[0x4]; 3952 u8 reserved_at_8[0x18]; 3953 3954 u8 wq_signature[0x1]; 3955 u8 cont_srq[0x1]; 3956 u8 reserved_at_22[0x1]; 3957 u8 rlky[0x1]; 3958 u8 basic_cyclic_rcv_wqe[0x1]; 3959 u8 log_rq_stride[0x3]; 3960 u8 xrcd[0x18]; 3961 3962 u8 page_offset[0x6]; 3963 u8 reserved_at_46[0x1]; 3964 u8 dbr_umem_valid[0x1]; 3965 u8 cqn[0x18]; 3966 3967 u8 reserved_at_60[0x20]; 3968 3969 u8 user_index_equal_xrc_srqn[0x1]; 3970 u8 reserved_at_81[0x1]; 3971 u8 log_page_size[0x6]; 3972 u8 user_index[0x18]; 3973 3974 u8 reserved_at_a0[0x20]; 3975 3976 u8 reserved_at_c0[0x8]; 3977 u8 pd[0x18]; 3978 3979 u8 lwm[0x10]; 3980 u8 wqe_cnt[0x10]; 3981 3982 u8 reserved_at_100[0x40]; 3983 3984 u8 db_record_addr_h[0x20]; 3985 3986 u8 db_record_addr_l[0x1e]; 3987 u8 reserved_at_17e[0x2]; 3988 3989 u8 reserved_at_180[0x80]; 3990 }; 3991 3992 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3993 u8 counter_error_queues[0x20]; 3994 3995 u8 total_error_queues[0x20]; 3996 3997 u8 send_queue_priority_update_flow[0x20]; 3998 3999 u8 reserved_at_60[0x20]; 4000 4001 u8 nic_receive_steering_discard[0x40]; 4002 4003 u8 receive_discard_vport_down[0x40]; 4004 4005 u8 transmit_discard_vport_down[0x40]; 4006 4007 u8 async_eq_overrun[0x20]; 4008 4009 u8 comp_eq_overrun[0x20]; 4010 4011 u8 reserved_at_180[0x20]; 4012 4013 u8 invalid_command[0x20]; 4014 4015 u8 quota_exceeded_command[0x20]; 4016 4017 u8 internal_rq_out_of_buffer[0x20]; 4018 4019 u8 cq_overrun[0x20]; 4020 4021 u8 eth_wqe_too_small[0x20]; 4022 4023 u8 reserved_at_220[0xc0]; 4024 4025 u8 generated_pkt_steering_fail[0x40]; 4026 4027 u8 handled_pkt_steering_fail[0x40]; 4028 4029 u8 bar_uar_access[0x20]; 4030 4031 u8 odp_local_triggered_page_fault[0x20]; 4032 4033 u8 odp_remote_triggered_page_fault[0x20]; 4034 4035 u8 reserved_at_3c0[0xc20]; 4036 }; 4037 4038 struct mlx5_ifc_traffic_counter_bits { 4039 u8 packets[0x40]; 4040 4041 u8 octets[0x40]; 4042 }; 4043 4044 struct mlx5_ifc_tisc_bits { 4045 u8 strict_lag_tx_port_affinity[0x1]; 4046 u8 tls_en[0x1]; 4047 u8 reserved_at_2[0x2]; 4048 u8 lag_tx_port_affinity[0x04]; 4049 4050 u8 reserved_at_8[0x4]; 4051 u8 prio[0x4]; 4052 u8 reserved_at_10[0x10]; 4053 4054 u8 reserved_at_20[0x100]; 4055 4056 u8 reserved_at_120[0x8]; 4057 u8 transport_domain[0x18]; 4058 4059 u8 reserved_at_140[0x8]; 4060 u8 underlay_qpn[0x18]; 4061 4062 u8 reserved_at_160[0x8]; 4063 u8 pd[0x18]; 4064 4065 u8 reserved_at_180[0x380]; 4066 }; 4067 4068 enum { 4069 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4070 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4071 }; 4072 4073 enum { 4074 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4075 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4076 }; 4077 4078 enum { 4079 MLX5_RX_HASH_FN_NONE = 0x0, 4080 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4081 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4082 }; 4083 4084 enum { 4085 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4086 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4087 }; 4088 4089 struct mlx5_ifc_tirc_bits { 4090 u8 reserved_at_0[0x20]; 4091 4092 u8 disp_type[0x4]; 4093 u8 tls_en[0x1]; 4094 u8 reserved_at_25[0x1b]; 4095 4096 u8 reserved_at_40[0x40]; 4097 4098 u8 reserved_at_80[0x4]; 4099 u8 lro_timeout_period_usecs[0x10]; 4100 u8 packet_merge_mask[0x4]; 4101 u8 lro_max_ip_payload_size[0x8]; 4102 4103 u8 reserved_at_a0[0x40]; 4104 4105 u8 reserved_at_e0[0x8]; 4106 u8 inline_rqn[0x18]; 4107 4108 u8 rx_hash_symmetric[0x1]; 4109 u8 reserved_at_101[0x1]; 4110 u8 tunneled_offload_en[0x1]; 4111 u8 reserved_at_103[0x5]; 4112 u8 indirect_table[0x18]; 4113 4114 u8 rx_hash_fn[0x4]; 4115 u8 reserved_at_124[0x2]; 4116 u8 self_lb_block[0x2]; 4117 u8 transport_domain[0x18]; 4118 4119 u8 rx_hash_toeplitz_key[10][0x20]; 4120 4121 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4122 4123 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4124 4125 u8 reserved_at_2c0[0x4c0]; 4126 }; 4127 4128 enum { 4129 MLX5_SRQC_STATE_GOOD = 0x0, 4130 MLX5_SRQC_STATE_ERROR = 0x1, 4131 }; 4132 4133 struct mlx5_ifc_srqc_bits { 4134 u8 state[0x4]; 4135 u8 log_srq_size[0x4]; 4136 u8 reserved_at_8[0x18]; 4137 4138 u8 wq_signature[0x1]; 4139 u8 cont_srq[0x1]; 4140 u8 reserved_at_22[0x1]; 4141 u8 rlky[0x1]; 4142 u8 reserved_at_24[0x1]; 4143 u8 log_rq_stride[0x3]; 4144 u8 xrcd[0x18]; 4145 4146 u8 page_offset[0x6]; 4147 u8 reserved_at_46[0x2]; 4148 u8 cqn[0x18]; 4149 4150 u8 reserved_at_60[0x20]; 4151 4152 u8 reserved_at_80[0x2]; 4153 u8 log_page_size[0x6]; 4154 u8 reserved_at_88[0x18]; 4155 4156 u8 reserved_at_a0[0x20]; 4157 4158 u8 reserved_at_c0[0x8]; 4159 u8 pd[0x18]; 4160 4161 u8 lwm[0x10]; 4162 u8 wqe_cnt[0x10]; 4163 4164 u8 reserved_at_100[0x40]; 4165 4166 u8 dbr_addr[0x40]; 4167 4168 u8 reserved_at_180[0x80]; 4169 }; 4170 4171 enum { 4172 MLX5_SQC_STATE_RST = 0x0, 4173 MLX5_SQC_STATE_RDY = 0x1, 4174 MLX5_SQC_STATE_ERR = 0x3, 4175 }; 4176 4177 struct mlx5_ifc_sqc_bits { 4178 u8 rlky[0x1]; 4179 u8 cd_master[0x1]; 4180 u8 fre[0x1]; 4181 u8 flush_in_error_en[0x1]; 4182 u8 allow_multi_pkt_send_wqe[0x1]; 4183 u8 min_wqe_inline_mode[0x3]; 4184 u8 state[0x4]; 4185 u8 reg_umr[0x1]; 4186 u8 allow_swp[0x1]; 4187 u8 hairpin[0x1]; 4188 u8 non_wire[0x1]; 4189 u8 reserved_at_10[0xa]; 4190 u8 ts_format[0x2]; 4191 u8 reserved_at_1c[0x4]; 4192 4193 u8 reserved_at_20[0x8]; 4194 u8 user_index[0x18]; 4195 4196 u8 reserved_at_40[0x8]; 4197 u8 cqn[0x18]; 4198 4199 u8 reserved_at_60[0x8]; 4200 u8 hairpin_peer_rq[0x18]; 4201 4202 u8 reserved_at_80[0x10]; 4203 u8 hairpin_peer_vhca[0x10]; 4204 4205 u8 reserved_at_a0[0x20]; 4206 4207 u8 reserved_at_c0[0x8]; 4208 u8 ts_cqe_to_dest_cqn[0x18]; 4209 4210 u8 reserved_at_e0[0x10]; 4211 u8 packet_pacing_rate_limit_index[0x10]; 4212 u8 tis_lst_sz[0x10]; 4213 u8 qos_queue_group_id[0x10]; 4214 4215 u8 reserved_at_120[0x40]; 4216 4217 u8 reserved_at_160[0x8]; 4218 u8 tis_num_0[0x18]; 4219 4220 struct mlx5_ifc_wq_bits wq; 4221 }; 4222 4223 enum { 4224 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4225 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4226 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4227 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4228 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4229 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4230 }; 4231 4232 enum { 4233 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4234 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4235 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4236 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4237 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4238 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4239 }; 4240 4241 enum { 4242 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4243 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4244 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4245 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4246 }; 4247 4248 enum { 4249 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4250 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4251 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4252 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4253 }; 4254 4255 struct mlx5_ifc_tsar_element_bits { 4256 u8 traffic_class[0x4]; 4257 u8 reserved_at_4[0x4]; 4258 u8 tsar_type[0x8]; 4259 u8 reserved_at_10[0x10]; 4260 }; 4261 4262 struct mlx5_ifc_vport_element_bits { 4263 u8 reserved_at_0[0x4]; 4264 u8 eswitch_owner_vhca_id_valid[0x1]; 4265 u8 eswitch_owner_vhca_id[0xb]; 4266 u8 vport_number[0x10]; 4267 }; 4268 4269 struct mlx5_ifc_vport_tc_element_bits { 4270 u8 traffic_class[0x4]; 4271 u8 eswitch_owner_vhca_id_valid[0x1]; 4272 u8 eswitch_owner_vhca_id[0xb]; 4273 u8 vport_number[0x10]; 4274 }; 4275 4276 union mlx5_ifc_element_attributes_bits { 4277 struct mlx5_ifc_tsar_element_bits tsar; 4278 struct mlx5_ifc_vport_element_bits vport; 4279 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4280 u8 reserved_at_0[0x20]; 4281 }; 4282 4283 struct mlx5_ifc_scheduling_context_bits { 4284 u8 element_type[0x8]; 4285 u8 reserved_at_8[0x18]; 4286 4287 union mlx5_ifc_element_attributes_bits element_attributes; 4288 4289 u8 parent_element_id[0x20]; 4290 4291 u8 reserved_at_60[0x40]; 4292 4293 u8 bw_share[0x20]; 4294 4295 u8 max_average_bw[0x20]; 4296 4297 u8 max_bw_obj_id[0x20]; 4298 4299 u8 reserved_at_100[0x100]; 4300 }; 4301 4302 struct mlx5_ifc_rqtc_bits { 4303 u8 reserved_at_0[0xa0]; 4304 4305 u8 reserved_at_a0[0x5]; 4306 u8 list_q_type[0x3]; 4307 u8 reserved_at_a8[0x8]; 4308 u8 rqt_max_size[0x10]; 4309 4310 u8 rq_vhca_id_format[0x1]; 4311 u8 reserved_at_c1[0xf]; 4312 u8 rqt_actual_size[0x10]; 4313 4314 u8 reserved_at_e0[0x6a0]; 4315 4316 union { 4317 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4318 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4319 }; 4320 }; 4321 4322 enum { 4323 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4324 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4325 }; 4326 4327 enum { 4328 MLX5_RQC_STATE_RST = 0x0, 4329 MLX5_RQC_STATE_RDY = 0x1, 4330 MLX5_RQC_STATE_ERR = 0x3, 4331 }; 4332 4333 enum { 4334 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4335 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4336 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4337 }; 4338 4339 enum { 4340 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4341 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4342 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4343 }; 4344 4345 struct mlx5_ifc_rqc_bits { 4346 u8 rlky[0x1]; 4347 u8 delay_drop_en[0x1]; 4348 u8 scatter_fcs[0x1]; 4349 u8 vsd[0x1]; 4350 u8 mem_rq_type[0x4]; 4351 u8 state[0x4]; 4352 u8 reserved_at_c[0x1]; 4353 u8 flush_in_error_en[0x1]; 4354 u8 hairpin[0x1]; 4355 u8 reserved_at_f[0xb]; 4356 u8 ts_format[0x2]; 4357 u8 reserved_at_1c[0x4]; 4358 4359 u8 reserved_at_20[0x8]; 4360 u8 user_index[0x18]; 4361 4362 u8 reserved_at_40[0x8]; 4363 u8 cqn[0x18]; 4364 4365 u8 counter_set_id[0x8]; 4366 u8 reserved_at_68[0x18]; 4367 4368 u8 reserved_at_80[0x8]; 4369 u8 rmpn[0x18]; 4370 4371 u8 reserved_at_a0[0x8]; 4372 u8 hairpin_peer_sq[0x18]; 4373 4374 u8 reserved_at_c0[0x10]; 4375 u8 hairpin_peer_vhca[0x10]; 4376 4377 u8 reserved_at_e0[0x46]; 4378 u8 shampo_no_match_alignment_granularity[0x2]; 4379 u8 reserved_at_128[0x6]; 4380 u8 shampo_match_criteria_type[0x2]; 4381 u8 reservation_timeout[0x10]; 4382 4383 u8 reserved_at_140[0x40]; 4384 4385 struct mlx5_ifc_wq_bits wq; 4386 }; 4387 4388 enum { 4389 MLX5_RMPC_STATE_RDY = 0x1, 4390 MLX5_RMPC_STATE_ERR = 0x3, 4391 }; 4392 4393 struct mlx5_ifc_rmpc_bits { 4394 u8 reserved_at_0[0x8]; 4395 u8 state[0x4]; 4396 u8 reserved_at_c[0x14]; 4397 4398 u8 basic_cyclic_rcv_wqe[0x1]; 4399 u8 reserved_at_21[0x1f]; 4400 4401 u8 reserved_at_40[0x140]; 4402 4403 struct mlx5_ifc_wq_bits wq; 4404 }; 4405 4406 enum { 4407 VHCA_ID_TYPE_HW = 0, 4408 VHCA_ID_TYPE_SW = 1, 4409 }; 4410 4411 struct mlx5_ifc_nic_vport_context_bits { 4412 u8 reserved_at_0[0x5]; 4413 u8 min_wqe_inline_mode[0x3]; 4414 u8 reserved_at_8[0x15]; 4415 u8 disable_mc_local_lb[0x1]; 4416 u8 disable_uc_local_lb[0x1]; 4417 u8 roce_en[0x1]; 4418 4419 u8 arm_change_event[0x1]; 4420 u8 reserved_at_21[0x1a]; 4421 u8 event_on_mtu[0x1]; 4422 u8 event_on_promisc_change[0x1]; 4423 u8 event_on_vlan_change[0x1]; 4424 u8 event_on_mc_address_change[0x1]; 4425 u8 event_on_uc_address_change[0x1]; 4426 4427 u8 vhca_id_type[0x1]; 4428 u8 reserved_at_41[0xb]; 4429 u8 affiliation_criteria[0x4]; 4430 u8 affiliated_vhca_id[0x10]; 4431 4432 u8 reserved_at_60[0xa0]; 4433 4434 u8 reserved_at_100[0x1]; 4435 u8 sd_group[0x3]; 4436 u8 reserved_at_104[0x1c]; 4437 4438 u8 reserved_at_120[0x10]; 4439 u8 mtu[0x10]; 4440 4441 u8 system_image_guid[0x40]; 4442 u8 port_guid[0x40]; 4443 u8 node_guid[0x40]; 4444 4445 u8 reserved_at_200[0x140]; 4446 u8 qkey_violation_counter[0x10]; 4447 u8 reserved_at_350[0x430]; 4448 4449 u8 promisc_uc[0x1]; 4450 u8 promisc_mc[0x1]; 4451 u8 promisc_all[0x1]; 4452 u8 reserved_at_783[0x2]; 4453 u8 allowed_list_type[0x3]; 4454 u8 reserved_at_788[0xc]; 4455 u8 allowed_list_size[0xc]; 4456 4457 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4458 4459 u8 reserved_at_7e0[0x20]; 4460 4461 u8 current_uc_mac_address[][0x40]; 4462 }; 4463 4464 enum { 4465 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4466 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4467 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4468 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4469 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4470 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4471 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4472 }; 4473 4474 enum { 4475 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4476 }; 4477 4478 struct mlx5_ifc_mkc_bits { 4479 u8 reserved_at_0[0x1]; 4480 u8 free[0x1]; 4481 u8 reserved_at_2[0x1]; 4482 u8 access_mode_4_2[0x3]; 4483 u8 reserved_at_6[0x7]; 4484 u8 relaxed_ordering_write[0x1]; 4485 u8 reserved_at_e[0x1]; 4486 u8 small_fence_on_rdma_read_response[0x1]; 4487 u8 umr_en[0x1]; 4488 u8 a[0x1]; 4489 u8 rw[0x1]; 4490 u8 rr[0x1]; 4491 u8 lw[0x1]; 4492 u8 lr[0x1]; 4493 u8 access_mode_1_0[0x2]; 4494 u8 reserved_at_18[0x2]; 4495 u8 ma_translation_mode[0x2]; 4496 u8 reserved_at_1c[0x4]; 4497 4498 u8 qpn[0x18]; 4499 u8 mkey_7_0[0x8]; 4500 4501 u8 reserved_at_40[0x20]; 4502 4503 u8 length64[0x1]; 4504 u8 bsf_en[0x1]; 4505 u8 sync_umr[0x1]; 4506 u8 reserved_at_63[0x2]; 4507 u8 expected_sigerr_count[0x1]; 4508 u8 reserved_at_66[0x1]; 4509 u8 en_rinval[0x1]; 4510 u8 pd[0x18]; 4511 4512 u8 start_addr[0x40]; 4513 4514 u8 len[0x40]; 4515 4516 u8 bsf_octword_size[0x20]; 4517 4518 u8 reserved_at_120[0x60]; 4519 4520 u8 crossing_target_vhca_id[0x10]; 4521 u8 reserved_at_190[0x10]; 4522 4523 u8 translations_octword_size[0x20]; 4524 4525 u8 reserved_at_1c0[0x19]; 4526 u8 relaxed_ordering_read[0x1]; 4527 u8 log_page_size[0x6]; 4528 4529 u8 reserved_at_1e0[0x5]; 4530 u8 pcie_tph_en[0x1]; 4531 u8 pcie_tph_ph[0x2]; 4532 u8 pcie_tph_steering_tag_index[0x8]; 4533 u8 reserved_at_1f0[0x10]; 4534 }; 4535 4536 struct mlx5_ifc_pkey_bits { 4537 u8 reserved_at_0[0x10]; 4538 u8 pkey[0x10]; 4539 }; 4540 4541 struct mlx5_ifc_array128_auto_bits { 4542 u8 array128_auto[16][0x8]; 4543 }; 4544 4545 struct mlx5_ifc_hca_vport_context_bits { 4546 u8 field_select[0x20]; 4547 4548 u8 reserved_at_20[0xe0]; 4549 4550 u8 sm_virt_aware[0x1]; 4551 u8 has_smi[0x1]; 4552 u8 has_raw[0x1]; 4553 u8 grh_required[0x1]; 4554 u8 reserved_at_104[0x4]; 4555 u8 num_port_plane[0x8]; 4556 u8 port_physical_state[0x4]; 4557 u8 vport_state_policy[0x4]; 4558 u8 port_state[0x4]; 4559 u8 vport_state[0x4]; 4560 4561 u8 reserved_at_120[0x20]; 4562 4563 u8 system_image_guid[0x40]; 4564 4565 u8 port_guid[0x40]; 4566 4567 u8 node_guid[0x40]; 4568 4569 u8 cap_mask1[0x20]; 4570 4571 u8 cap_mask1_field_select[0x20]; 4572 4573 u8 cap_mask2[0x20]; 4574 4575 u8 cap_mask2_field_select[0x20]; 4576 4577 u8 reserved_at_280[0x80]; 4578 4579 u8 lid[0x10]; 4580 u8 reserved_at_310[0x4]; 4581 u8 init_type_reply[0x4]; 4582 u8 lmc[0x3]; 4583 u8 subnet_timeout[0x5]; 4584 4585 u8 sm_lid[0x10]; 4586 u8 sm_sl[0x4]; 4587 u8 reserved_at_334[0xc]; 4588 4589 u8 qkey_violation_counter[0x10]; 4590 u8 pkey_violation_counter[0x10]; 4591 4592 u8 reserved_at_360[0xca0]; 4593 }; 4594 4595 struct mlx5_ifc_esw_vport_context_bits { 4596 u8 fdb_to_vport_reg_c[0x1]; 4597 u8 reserved_at_1[0x2]; 4598 u8 vport_svlan_strip[0x1]; 4599 u8 vport_cvlan_strip[0x1]; 4600 u8 vport_svlan_insert[0x1]; 4601 u8 vport_cvlan_insert[0x2]; 4602 u8 fdb_to_vport_reg_c_id[0x8]; 4603 u8 reserved_at_10[0x10]; 4604 4605 u8 reserved_at_20[0x20]; 4606 4607 u8 svlan_cfi[0x1]; 4608 u8 svlan_pcp[0x3]; 4609 u8 svlan_id[0xc]; 4610 u8 cvlan_cfi[0x1]; 4611 u8 cvlan_pcp[0x3]; 4612 u8 cvlan_id[0xc]; 4613 4614 u8 reserved_at_60[0x720]; 4615 4616 u8 sw_steering_vport_icm_address_rx[0x40]; 4617 4618 u8 sw_steering_vport_icm_address_tx[0x40]; 4619 }; 4620 4621 enum { 4622 MLX5_EQC_STATUS_OK = 0x0, 4623 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4624 }; 4625 4626 enum { 4627 MLX5_EQC_ST_ARMED = 0x9, 4628 MLX5_EQC_ST_FIRED = 0xa, 4629 }; 4630 4631 struct mlx5_ifc_eqc_bits { 4632 u8 status[0x4]; 4633 u8 reserved_at_4[0x9]; 4634 u8 ec[0x1]; 4635 u8 oi[0x1]; 4636 u8 reserved_at_f[0x5]; 4637 u8 st[0x4]; 4638 u8 reserved_at_18[0x8]; 4639 4640 u8 reserved_at_20[0x20]; 4641 4642 u8 reserved_at_40[0x14]; 4643 u8 page_offset[0x6]; 4644 u8 reserved_at_5a[0x6]; 4645 4646 u8 reserved_at_60[0x3]; 4647 u8 log_eq_size[0x5]; 4648 u8 uar_page[0x18]; 4649 4650 u8 reserved_at_80[0x20]; 4651 4652 u8 reserved_at_a0[0x14]; 4653 u8 intr[0xc]; 4654 4655 u8 reserved_at_c0[0x3]; 4656 u8 log_page_size[0x5]; 4657 u8 reserved_at_c8[0x18]; 4658 4659 u8 reserved_at_e0[0x60]; 4660 4661 u8 reserved_at_140[0x8]; 4662 u8 consumer_counter[0x18]; 4663 4664 u8 reserved_at_160[0x8]; 4665 u8 producer_counter[0x18]; 4666 4667 u8 reserved_at_180[0x80]; 4668 }; 4669 4670 enum { 4671 MLX5_DCTC_STATE_ACTIVE = 0x0, 4672 MLX5_DCTC_STATE_DRAINING = 0x1, 4673 MLX5_DCTC_STATE_DRAINED = 0x2, 4674 }; 4675 4676 enum { 4677 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4678 MLX5_DCTC_CS_RES_NA = 0x1, 4679 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4680 }; 4681 4682 enum { 4683 MLX5_DCTC_MTU_256_BYTES = 0x1, 4684 MLX5_DCTC_MTU_512_BYTES = 0x2, 4685 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4686 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4687 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4688 }; 4689 4690 struct mlx5_ifc_dctc_bits { 4691 u8 reserved_at_0[0x4]; 4692 u8 state[0x4]; 4693 u8 reserved_at_8[0x18]; 4694 4695 u8 reserved_at_20[0x7]; 4696 u8 dp_ordering_force[0x1]; 4697 u8 user_index[0x18]; 4698 4699 u8 reserved_at_40[0x8]; 4700 u8 cqn[0x18]; 4701 4702 u8 counter_set_id[0x8]; 4703 u8 atomic_mode[0x4]; 4704 u8 rre[0x1]; 4705 u8 rwe[0x1]; 4706 u8 rae[0x1]; 4707 u8 atomic_like_write_en[0x1]; 4708 u8 latency_sensitive[0x1]; 4709 u8 rlky[0x1]; 4710 u8 free_ar[0x1]; 4711 u8 reserved_at_73[0x1]; 4712 u8 dp_ordering_1[0x1]; 4713 u8 reserved_at_75[0xb]; 4714 4715 u8 reserved_at_80[0x8]; 4716 u8 cs_res[0x8]; 4717 u8 reserved_at_90[0x3]; 4718 u8 min_rnr_nak[0x5]; 4719 u8 reserved_at_98[0x8]; 4720 4721 u8 reserved_at_a0[0x8]; 4722 u8 srqn_xrqn[0x18]; 4723 4724 u8 reserved_at_c0[0x8]; 4725 u8 pd[0x18]; 4726 4727 u8 tclass[0x8]; 4728 u8 reserved_at_e8[0x4]; 4729 u8 flow_label[0x14]; 4730 4731 u8 dc_access_key[0x40]; 4732 4733 u8 reserved_at_140[0x5]; 4734 u8 mtu[0x3]; 4735 u8 port[0x8]; 4736 u8 pkey_index[0x10]; 4737 4738 u8 reserved_at_160[0x8]; 4739 u8 my_addr_index[0x8]; 4740 u8 reserved_at_170[0x8]; 4741 u8 hop_limit[0x8]; 4742 4743 u8 dc_access_key_violation_count[0x20]; 4744 4745 u8 reserved_at_1a0[0x14]; 4746 u8 dei_cfi[0x1]; 4747 u8 eth_prio[0x3]; 4748 u8 ecn[0x2]; 4749 u8 dscp[0x6]; 4750 4751 u8 reserved_at_1c0[0x20]; 4752 u8 ece[0x20]; 4753 }; 4754 4755 enum { 4756 MLX5_CQC_STATUS_OK = 0x0, 4757 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4758 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4759 }; 4760 4761 enum { 4762 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4763 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4764 }; 4765 4766 enum { 4767 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4768 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4769 MLX5_CQC_ST_FIRED = 0xa, 4770 }; 4771 4772 enum mlx5_cq_period_mode { 4773 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4774 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4775 MLX5_CQ_PERIOD_NUM_MODES, 4776 }; 4777 4778 struct mlx5_ifc_cqc_bits { 4779 u8 status[0x4]; 4780 u8 reserved_at_4[0x2]; 4781 u8 dbr_umem_valid[0x1]; 4782 u8 apu_cq[0x1]; 4783 u8 cqe_sz[0x3]; 4784 u8 cc[0x1]; 4785 u8 reserved_at_c[0x1]; 4786 u8 scqe_break_moderation_en[0x1]; 4787 u8 oi[0x1]; 4788 u8 cq_period_mode[0x2]; 4789 u8 cqe_comp_en[0x1]; 4790 u8 mini_cqe_res_format[0x2]; 4791 u8 st[0x4]; 4792 u8 reserved_at_18[0x6]; 4793 u8 cqe_compression_layout[0x2]; 4794 4795 u8 reserved_at_20[0x20]; 4796 4797 u8 reserved_at_40[0x14]; 4798 u8 page_offset[0x6]; 4799 u8 reserved_at_5a[0x6]; 4800 4801 u8 reserved_at_60[0x3]; 4802 u8 log_cq_size[0x5]; 4803 u8 uar_page[0x18]; 4804 4805 u8 reserved_at_80[0x4]; 4806 u8 cq_period[0xc]; 4807 u8 cq_max_count[0x10]; 4808 4809 u8 c_eqn_or_apu_element[0x20]; 4810 4811 u8 reserved_at_c0[0x3]; 4812 u8 log_page_size[0x5]; 4813 u8 reserved_at_c8[0x18]; 4814 4815 u8 reserved_at_e0[0x20]; 4816 4817 u8 reserved_at_100[0x8]; 4818 u8 last_notified_index[0x18]; 4819 4820 u8 reserved_at_120[0x8]; 4821 u8 last_solicit_index[0x18]; 4822 4823 u8 reserved_at_140[0x8]; 4824 u8 consumer_counter[0x18]; 4825 4826 u8 reserved_at_160[0x8]; 4827 u8 producer_counter[0x18]; 4828 4829 u8 reserved_at_180[0x40]; 4830 4831 u8 dbr_addr[0x40]; 4832 }; 4833 4834 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4835 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4836 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4837 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4838 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4839 u8 reserved_at_0[0x800]; 4840 }; 4841 4842 struct mlx5_ifc_query_adapter_param_block_bits { 4843 u8 reserved_at_0[0xc0]; 4844 4845 u8 reserved_at_c0[0x8]; 4846 u8 ieee_vendor_id[0x18]; 4847 4848 u8 reserved_at_e0[0x10]; 4849 u8 vsd_vendor_id[0x10]; 4850 4851 u8 vsd[208][0x8]; 4852 4853 u8 vsd_contd_psid[16][0x8]; 4854 }; 4855 4856 enum { 4857 MLX5_XRQC_STATE_GOOD = 0x0, 4858 MLX5_XRQC_STATE_ERROR = 0x1, 4859 }; 4860 4861 enum { 4862 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4863 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4864 }; 4865 4866 enum { 4867 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4868 }; 4869 4870 struct mlx5_ifc_tag_matching_topology_context_bits { 4871 u8 log_matching_list_sz[0x4]; 4872 u8 reserved_at_4[0xc]; 4873 u8 append_next_index[0x10]; 4874 4875 u8 sw_phase_cnt[0x10]; 4876 u8 hw_phase_cnt[0x10]; 4877 4878 u8 reserved_at_40[0x40]; 4879 }; 4880 4881 struct mlx5_ifc_xrqc_bits { 4882 u8 state[0x4]; 4883 u8 rlkey[0x1]; 4884 u8 reserved_at_5[0xf]; 4885 u8 topology[0x4]; 4886 u8 reserved_at_18[0x4]; 4887 u8 offload[0x4]; 4888 4889 u8 reserved_at_20[0x8]; 4890 u8 user_index[0x18]; 4891 4892 u8 reserved_at_40[0x8]; 4893 u8 cqn[0x18]; 4894 4895 u8 reserved_at_60[0xa0]; 4896 4897 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4898 4899 u8 reserved_at_180[0x280]; 4900 4901 struct mlx5_ifc_wq_bits wq; 4902 }; 4903 4904 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4905 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4906 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4907 u8 reserved_at_0[0x20]; 4908 }; 4909 4910 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4911 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4912 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4913 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4914 u8 reserved_at_0[0x20]; 4915 }; 4916 4917 struct mlx5_ifc_rs_histogram_cntrs_bits { 4918 u8 hist[16][0x40]; 4919 u8 reserved_at_400[0x2c0]; 4920 }; 4921 4922 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4923 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4924 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4925 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4926 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4927 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4928 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4929 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4930 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4931 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4932 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4933 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4934 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4935 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4936 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; 4937 u8 reserved_at_0[0x7c0]; 4938 }; 4939 4940 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4941 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4942 u8 reserved_at_0[0x7c0]; 4943 }; 4944 4945 union mlx5_ifc_event_auto_bits { 4946 struct mlx5_ifc_comp_event_bits comp_event; 4947 struct mlx5_ifc_dct_events_bits dct_events; 4948 struct mlx5_ifc_qp_events_bits qp_events; 4949 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4950 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4951 struct mlx5_ifc_cq_error_bits cq_error; 4952 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4953 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4954 struct mlx5_ifc_gpio_event_bits gpio_event; 4955 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4956 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4957 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4958 u8 reserved_at_0[0xe0]; 4959 }; 4960 4961 struct mlx5_ifc_health_buffer_bits { 4962 u8 reserved_at_0[0x100]; 4963 4964 u8 assert_existptr[0x20]; 4965 4966 u8 assert_callra[0x20]; 4967 4968 u8 reserved_at_140[0x20]; 4969 4970 u8 time[0x20]; 4971 4972 u8 fw_version[0x20]; 4973 4974 u8 hw_id[0x20]; 4975 4976 u8 rfr[0x1]; 4977 u8 reserved_at_1c1[0x3]; 4978 u8 valid[0x1]; 4979 u8 severity[0x3]; 4980 u8 reserved_at_1c8[0x18]; 4981 4982 u8 irisc_index[0x8]; 4983 u8 synd[0x8]; 4984 u8 ext_synd[0x10]; 4985 }; 4986 4987 struct mlx5_ifc_register_loopback_control_bits { 4988 u8 no_lb[0x1]; 4989 u8 reserved_at_1[0x7]; 4990 u8 port[0x8]; 4991 u8 reserved_at_10[0x10]; 4992 4993 u8 reserved_at_20[0x60]; 4994 }; 4995 4996 enum { 4997 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4998 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4999 }; 5000 5001 struct mlx5_ifc_teardown_hca_out_bits { 5002 u8 status[0x8]; 5003 u8 reserved_at_8[0x18]; 5004 5005 u8 syndrome[0x20]; 5006 5007 u8 reserved_at_40[0x3f]; 5008 5009 u8 state[0x1]; 5010 }; 5011 5012 enum { 5013 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 5014 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 5015 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 5016 }; 5017 5018 struct mlx5_ifc_teardown_hca_in_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_at_10[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 reserved_at_40[0x10]; 5026 u8 profile[0x10]; 5027 5028 u8 reserved_at_60[0x20]; 5029 }; 5030 5031 struct mlx5_ifc_sqerr2rts_qp_out_bits { 5032 u8 status[0x8]; 5033 u8 reserved_at_8[0x18]; 5034 5035 u8 syndrome[0x20]; 5036 5037 u8 reserved_at_40[0x40]; 5038 }; 5039 5040 struct mlx5_ifc_sqerr2rts_qp_in_bits { 5041 u8 opcode[0x10]; 5042 u8 uid[0x10]; 5043 5044 u8 reserved_at_20[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 reserved_at_40[0x8]; 5048 u8 qpn[0x18]; 5049 5050 u8 reserved_at_60[0x20]; 5051 5052 u8 opt_param_mask[0x20]; 5053 5054 u8 reserved_at_a0[0x20]; 5055 5056 struct mlx5_ifc_qpc_bits qpc; 5057 5058 u8 reserved_at_800[0x80]; 5059 }; 5060 5061 struct mlx5_ifc_sqd2rts_qp_out_bits { 5062 u8 status[0x8]; 5063 u8 reserved_at_8[0x18]; 5064 5065 u8 syndrome[0x20]; 5066 5067 u8 reserved_at_40[0x40]; 5068 }; 5069 5070 struct mlx5_ifc_sqd2rts_qp_in_bits { 5071 u8 opcode[0x10]; 5072 u8 uid[0x10]; 5073 5074 u8 reserved_at_20[0x10]; 5075 u8 op_mod[0x10]; 5076 5077 u8 reserved_at_40[0x8]; 5078 u8 qpn[0x18]; 5079 5080 u8 reserved_at_60[0x20]; 5081 5082 u8 opt_param_mask[0x20]; 5083 5084 u8 reserved_at_a0[0x20]; 5085 5086 struct mlx5_ifc_qpc_bits qpc; 5087 5088 u8 reserved_at_800[0x80]; 5089 }; 5090 5091 struct mlx5_ifc_set_roce_address_out_bits { 5092 u8 status[0x8]; 5093 u8 reserved_at_8[0x18]; 5094 5095 u8 syndrome[0x20]; 5096 5097 u8 reserved_at_40[0x40]; 5098 }; 5099 5100 struct mlx5_ifc_set_roce_address_in_bits { 5101 u8 opcode[0x10]; 5102 u8 reserved_at_10[0x10]; 5103 5104 u8 reserved_at_20[0x10]; 5105 u8 op_mod[0x10]; 5106 5107 u8 roce_address_index[0x10]; 5108 u8 reserved_at_50[0xc]; 5109 u8 vhca_port_num[0x4]; 5110 5111 u8 reserved_at_60[0x20]; 5112 5113 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5114 }; 5115 5116 struct mlx5_ifc_set_mad_demux_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_at_8[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_at_40[0x40]; 5123 }; 5124 5125 enum { 5126 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5127 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5128 }; 5129 5130 struct mlx5_ifc_set_mad_demux_in_bits { 5131 u8 opcode[0x10]; 5132 u8 reserved_at_10[0x10]; 5133 5134 u8 reserved_at_20[0x10]; 5135 u8 op_mod[0x10]; 5136 5137 u8 reserved_at_40[0x20]; 5138 5139 u8 reserved_at_60[0x6]; 5140 u8 demux_mode[0x2]; 5141 u8 reserved_at_68[0x18]; 5142 }; 5143 5144 struct mlx5_ifc_set_l2_table_entry_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 }; 5152 5153 struct mlx5_ifc_set_l2_table_entry_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 reserved_at_40[0x60]; 5161 5162 u8 reserved_at_a0[0x8]; 5163 u8 table_index[0x18]; 5164 5165 u8 reserved_at_c0[0x20]; 5166 5167 u8 reserved_at_e0[0x10]; 5168 u8 silent_mode_valid[0x1]; 5169 u8 silent_mode[0x1]; 5170 u8 reserved_at_f2[0x1]; 5171 u8 vlan_valid[0x1]; 5172 u8 vlan[0xc]; 5173 5174 struct mlx5_ifc_mac_address_layout_bits mac_address; 5175 5176 u8 reserved_at_140[0xc0]; 5177 }; 5178 5179 struct mlx5_ifc_set_issi_out_bits { 5180 u8 status[0x8]; 5181 u8 reserved_at_8[0x18]; 5182 5183 u8 syndrome[0x20]; 5184 5185 u8 reserved_at_40[0x40]; 5186 }; 5187 5188 struct mlx5_ifc_set_issi_in_bits { 5189 u8 opcode[0x10]; 5190 u8 reserved_at_10[0x10]; 5191 5192 u8 reserved_at_20[0x10]; 5193 u8 op_mod[0x10]; 5194 5195 u8 reserved_at_40[0x10]; 5196 u8 current_issi[0x10]; 5197 5198 u8 reserved_at_60[0x20]; 5199 }; 5200 5201 struct mlx5_ifc_set_hca_cap_out_bits { 5202 u8 status[0x8]; 5203 u8 reserved_at_8[0x18]; 5204 5205 u8 syndrome[0x20]; 5206 5207 u8 reserved_at_40[0x40]; 5208 }; 5209 5210 struct mlx5_ifc_set_hca_cap_in_bits { 5211 u8 opcode[0x10]; 5212 u8 reserved_at_10[0x10]; 5213 5214 u8 reserved_at_20[0x10]; 5215 u8 op_mod[0x10]; 5216 5217 u8 other_function[0x1]; 5218 u8 ec_vf_function[0x1]; 5219 u8 reserved_at_42[0x1]; 5220 u8 function_id_type[0x1]; 5221 u8 reserved_at_44[0xc]; 5222 u8 function_id[0x10]; 5223 5224 u8 reserved_at_60[0x20]; 5225 5226 union mlx5_ifc_hca_cap_union_bits capability; 5227 }; 5228 5229 enum { 5230 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5231 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5232 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5233 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5234 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5235 }; 5236 5237 struct mlx5_ifc_set_fte_out_bits { 5238 u8 status[0x8]; 5239 u8 reserved_at_8[0x18]; 5240 5241 u8 syndrome[0x20]; 5242 5243 u8 reserved_at_40[0x40]; 5244 }; 5245 5246 struct mlx5_ifc_set_fte_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_at_10[0x10]; 5249 5250 u8 reserved_at_20[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 other_vport[0x1]; 5254 u8 reserved_at_41[0xf]; 5255 u8 vport_number[0x10]; 5256 5257 u8 reserved_at_60[0x20]; 5258 5259 u8 table_type[0x8]; 5260 u8 reserved_at_88[0x18]; 5261 5262 u8 reserved_at_a0[0x8]; 5263 u8 table_id[0x18]; 5264 5265 u8 ignore_flow_level[0x1]; 5266 u8 reserved_at_c1[0x17]; 5267 u8 modify_enable_mask[0x8]; 5268 5269 u8 reserved_at_e0[0x20]; 5270 5271 u8 flow_index[0x20]; 5272 5273 u8 reserved_at_120[0xe0]; 5274 5275 struct mlx5_ifc_flow_context_bits flow_context; 5276 }; 5277 5278 struct mlx5_ifc_dest_format_bits { 5279 u8 destination_type[0x8]; 5280 u8 destination_id[0x18]; 5281 5282 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5283 u8 packet_reformat[0x1]; 5284 u8 reserved_at_22[0xe]; 5285 u8 destination_eswitch_owner_vhca_id[0x10]; 5286 }; 5287 5288 struct mlx5_ifc_rts2rts_qp_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_at_40[0x20]; 5295 u8 ece[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_rts2rts_qp_in_bits { 5299 u8 opcode[0x10]; 5300 u8 uid[0x10]; 5301 5302 u8 reserved_at_20[0x10]; 5303 u8 op_mod[0x10]; 5304 5305 u8 reserved_at_40[0x8]; 5306 u8 qpn[0x18]; 5307 5308 u8 reserved_at_60[0x20]; 5309 5310 u8 opt_param_mask[0x20]; 5311 5312 u8 ece[0x20]; 5313 5314 struct mlx5_ifc_qpc_bits qpc; 5315 5316 u8 reserved_at_800[0x80]; 5317 }; 5318 5319 struct mlx5_ifc_rtr2rts_qp_out_bits { 5320 u8 status[0x8]; 5321 u8 reserved_at_8[0x18]; 5322 5323 u8 syndrome[0x20]; 5324 5325 u8 reserved_at_40[0x20]; 5326 u8 ece[0x20]; 5327 }; 5328 5329 struct mlx5_ifc_rtr2rts_qp_in_bits { 5330 u8 opcode[0x10]; 5331 u8 uid[0x10]; 5332 5333 u8 reserved_at_20[0x10]; 5334 u8 op_mod[0x10]; 5335 5336 u8 reserved_at_40[0x8]; 5337 u8 qpn[0x18]; 5338 5339 u8 reserved_at_60[0x20]; 5340 5341 u8 opt_param_mask[0x20]; 5342 5343 u8 ece[0x20]; 5344 5345 struct mlx5_ifc_qpc_bits qpc; 5346 5347 u8 reserved_at_800[0x80]; 5348 }; 5349 5350 struct mlx5_ifc_rst2init_qp_out_bits { 5351 u8 status[0x8]; 5352 u8 reserved_at_8[0x18]; 5353 5354 u8 syndrome[0x20]; 5355 5356 u8 reserved_at_40[0x20]; 5357 u8 ece[0x20]; 5358 }; 5359 5360 struct mlx5_ifc_rst2init_qp_in_bits { 5361 u8 opcode[0x10]; 5362 u8 uid[0x10]; 5363 5364 u8 reserved_at_20[0x10]; 5365 u8 op_mod[0x10]; 5366 5367 u8 reserved_at_40[0x8]; 5368 u8 qpn[0x18]; 5369 5370 u8 reserved_at_60[0x20]; 5371 5372 u8 opt_param_mask[0x20]; 5373 5374 u8 ece[0x20]; 5375 5376 struct mlx5_ifc_qpc_bits qpc; 5377 5378 u8 reserved_at_800[0x80]; 5379 }; 5380 5381 struct mlx5_ifc_query_xrq_out_bits { 5382 u8 status[0x8]; 5383 u8 reserved_at_8[0x18]; 5384 5385 u8 syndrome[0x20]; 5386 5387 u8 reserved_at_40[0x40]; 5388 5389 struct mlx5_ifc_xrqc_bits xrq_context; 5390 }; 5391 5392 struct mlx5_ifc_query_xrq_in_bits { 5393 u8 opcode[0x10]; 5394 u8 reserved_at_10[0x10]; 5395 5396 u8 reserved_at_20[0x10]; 5397 u8 op_mod[0x10]; 5398 5399 u8 reserved_at_40[0x8]; 5400 u8 xrqn[0x18]; 5401 5402 u8 reserved_at_60[0x20]; 5403 }; 5404 5405 struct mlx5_ifc_query_xrc_srq_out_bits { 5406 u8 status[0x8]; 5407 u8 reserved_at_8[0x18]; 5408 5409 u8 syndrome[0x20]; 5410 5411 u8 reserved_at_40[0x40]; 5412 5413 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5414 5415 u8 reserved_at_280[0x600]; 5416 5417 u8 pas[][0x40]; 5418 }; 5419 5420 struct mlx5_ifc_query_xrc_srq_in_bits { 5421 u8 opcode[0x10]; 5422 u8 reserved_at_10[0x10]; 5423 5424 u8 reserved_at_20[0x10]; 5425 u8 op_mod[0x10]; 5426 5427 u8 reserved_at_40[0x8]; 5428 u8 xrc_srqn[0x18]; 5429 5430 u8 reserved_at_60[0x20]; 5431 }; 5432 5433 enum { 5434 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5435 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5436 }; 5437 5438 struct mlx5_ifc_query_vport_state_out_bits { 5439 u8 status[0x8]; 5440 u8 reserved_at_8[0x18]; 5441 5442 u8 syndrome[0x20]; 5443 5444 u8 reserved_at_40[0x20]; 5445 5446 u8 reserved_at_60[0x18]; 5447 u8 admin_state[0x4]; 5448 u8 state[0x4]; 5449 }; 5450 5451 struct mlx5_ifc_array1024_auto_bits { 5452 u8 array1024_auto[32][0x20]; 5453 }; 5454 5455 struct mlx5_ifc_query_vuid_in_bits { 5456 u8 opcode[0x10]; 5457 u8 uid[0x10]; 5458 5459 u8 reserved_at_20[0x40]; 5460 5461 u8 query_vfs_vuid[0x1]; 5462 u8 data_direct[0x1]; 5463 u8 reserved_at_62[0xe]; 5464 u8 vhca_id[0x10]; 5465 }; 5466 5467 struct mlx5_ifc_query_vuid_out_bits { 5468 u8 status[0x8]; 5469 u8 reserved_at_8[0x18]; 5470 5471 u8 syndrome[0x20]; 5472 5473 u8 reserved_at_40[0x1a0]; 5474 5475 u8 reserved_at_1e0[0x10]; 5476 u8 num_of_entries[0x10]; 5477 5478 struct mlx5_ifc_array1024_auto_bits vuid[]; 5479 }; 5480 5481 enum { 5482 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5483 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5484 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5485 }; 5486 5487 struct mlx5_ifc_arm_monitor_counter_in_bits { 5488 u8 opcode[0x10]; 5489 u8 uid[0x10]; 5490 5491 u8 reserved_at_20[0x10]; 5492 u8 op_mod[0x10]; 5493 5494 u8 reserved_at_40[0x20]; 5495 5496 u8 reserved_at_60[0x20]; 5497 }; 5498 5499 struct mlx5_ifc_arm_monitor_counter_out_bits { 5500 u8 status[0x8]; 5501 u8 reserved_at_8[0x18]; 5502 5503 u8 syndrome[0x20]; 5504 5505 u8 reserved_at_40[0x40]; 5506 }; 5507 5508 enum { 5509 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5510 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5511 }; 5512 5513 enum mlx5_monitor_counter_ppcnt { 5514 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5515 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5516 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5517 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5518 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5519 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5520 }; 5521 5522 enum { 5523 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5524 }; 5525 5526 struct mlx5_ifc_monitor_counter_output_bits { 5527 u8 reserved_at_0[0x4]; 5528 u8 type[0x4]; 5529 u8 reserved_at_8[0x8]; 5530 u8 counter[0x10]; 5531 5532 u8 counter_group_id[0x20]; 5533 }; 5534 5535 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5536 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5537 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5538 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5539 5540 struct mlx5_ifc_set_monitor_counter_in_bits { 5541 u8 opcode[0x10]; 5542 u8 uid[0x10]; 5543 5544 u8 reserved_at_20[0x10]; 5545 u8 op_mod[0x10]; 5546 5547 u8 reserved_at_40[0x10]; 5548 u8 num_of_counters[0x10]; 5549 5550 u8 reserved_at_60[0x20]; 5551 5552 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5553 }; 5554 5555 struct mlx5_ifc_set_monitor_counter_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x40]; 5562 }; 5563 5564 struct mlx5_ifc_query_vport_state_in_bits { 5565 u8 opcode[0x10]; 5566 u8 reserved_at_10[0x10]; 5567 5568 u8 reserved_at_20[0x10]; 5569 u8 op_mod[0x10]; 5570 5571 u8 other_vport[0x1]; 5572 u8 reserved_at_41[0xf]; 5573 u8 vport_number[0x10]; 5574 5575 u8 reserved_at_60[0x20]; 5576 }; 5577 5578 struct mlx5_ifc_query_vnic_env_out_bits { 5579 u8 status[0x8]; 5580 u8 reserved_at_8[0x18]; 5581 5582 u8 syndrome[0x20]; 5583 5584 u8 reserved_at_40[0x40]; 5585 5586 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5587 }; 5588 5589 enum { 5590 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5591 }; 5592 5593 struct mlx5_ifc_query_vnic_env_in_bits { 5594 u8 opcode[0x10]; 5595 u8 reserved_at_10[0x10]; 5596 5597 u8 reserved_at_20[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 other_vport[0x1]; 5601 u8 reserved_at_41[0xf]; 5602 u8 vport_number[0x10]; 5603 5604 u8 reserved_at_60[0x20]; 5605 }; 5606 5607 struct mlx5_ifc_query_vport_counter_out_bits { 5608 u8 status[0x8]; 5609 u8 reserved_at_8[0x18]; 5610 5611 u8 syndrome[0x20]; 5612 5613 u8 reserved_at_40[0x40]; 5614 5615 struct mlx5_ifc_traffic_counter_bits received_errors; 5616 5617 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5618 5619 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5620 5621 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5622 5623 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5624 5625 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5626 5627 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5628 5629 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5630 5631 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5632 5633 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5634 5635 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5636 5637 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5638 5639 struct mlx5_ifc_traffic_counter_bits local_loopback; 5640 5641 u8 reserved_at_700[0x980]; 5642 }; 5643 5644 enum { 5645 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5646 }; 5647 5648 struct mlx5_ifc_query_vport_counter_in_bits { 5649 u8 opcode[0x10]; 5650 u8 reserved_at_10[0x10]; 5651 5652 u8 reserved_at_20[0x10]; 5653 u8 op_mod[0x10]; 5654 5655 u8 other_vport[0x1]; 5656 u8 reserved_at_41[0xb]; 5657 u8 port_num[0x4]; 5658 u8 vport_number[0x10]; 5659 5660 u8 reserved_at_60[0x60]; 5661 5662 u8 clear[0x1]; 5663 u8 reserved_at_c1[0x1f]; 5664 5665 u8 reserved_at_e0[0x20]; 5666 }; 5667 5668 struct mlx5_ifc_query_tis_out_bits { 5669 u8 status[0x8]; 5670 u8 reserved_at_8[0x18]; 5671 5672 u8 syndrome[0x20]; 5673 5674 u8 reserved_at_40[0x40]; 5675 5676 struct mlx5_ifc_tisc_bits tis_context; 5677 }; 5678 5679 struct mlx5_ifc_query_tis_in_bits { 5680 u8 opcode[0x10]; 5681 u8 reserved_at_10[0x10]; 5682 5683 u8 reserved_at_20[0x10]; 5684 u8 op_mod[0x10]; 5685 5686 u8 reserved_at_40[0x8]; 5687 u8 tisn[0x18]; 5688 5689 u8 reserved_at_60[0x20]; 5690 }; 5691 5692 struct mlx5_ifc_query_tir_out_bits { 5693 u8 status[0x8]; 5694 u8 reserved_at_8[0x18]; 5695 5696 u8 syndrome[0x20]; 5697 5698 u8 reserved_at_40[0xc0]; 5699 5700 struct mlx5_ifc_tirc_bits tir_context; 5701 }; 5702 5703 struct mlx5_ifc_query_tir_in_bits { 5704 u8 opcode[0x10]; 5705 u8 reserved_at_10[0x10]; 5706 5707 u8 reserved_at_20[0x10]; 5708 u8 op_mod[0x10]; 5709 5710 u8 reserved_at_40[0x8]; 5711 u8 tirn[0x18]; 5712 5713 u8 reserved_at_60[0x20]; 5714 }; 5715 5716 struct mlx5_ifc_query_srq_out_bits { 5717 u8 status[0x8]; 5718 u8 reserved_at_8[0x18]; 5719 5720 u8 syndrome[0x20]; 5721 5722 u8 reserved_at_40[0x40]; 5723 5724 struct mlx5_ifc_srqc_bits srq_context_entry; 5725 5726 u8 reserved_at_280[0x600]; 5727 5728 u8 pas[][0x40]; 5729 }; 5730 5731 struct mlx5_ifc_query_srq_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_at_40[0x8]; 5739 u8 srqn[0x18]; 5740 5741 u8 reserved_at_60[0x20]; 5742 }; 5743 5744 struct mlx5_ifc_query_sq_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0xc0]; 5751 5752 struct mlx5_ifc_sqc_bits sq_context; 5753 }; 5754 5755 struct mlx5_ifc_query_sq_in_bits { 5756 u8 opcode[0x10]; 5757 u8 reserved_at_10[0x10]; 5758 5759 u8 reserved_at_20[0x10]; 5760 u8 op_mod[0x10]; 5761 5762 u8 reserved_at_40[0x8]; 5763 u8 sqn[0x18]; 5764 5765 u8 reserved_at_60[0x20]; 5766 }; 5767 5768 struct mlx5_ifc_query_special_contexts_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 dump_fill_mkey[0x20]; 5775 5776 u8 resd_lkey[0x20]; 5777 5778 u8 null_mkey[0x20]; 5779 5780 u8 terminate_scatter_list_mkey[0x20]; 5781 5782 u8 repeated_mkey[0x20]; 5783 5784 u8 reserved_at_a0[0x20]; 5785 }; 5786 5787 struct mlx5_ifc_query_special_contexts_in_bits { 5788 u8 opcode[0x10]; 5789 u8 reserved_at_10[0x10]; 5790 5791 u8 reserved_at_20[0x10]; 5792 u8 op_mod[0x10]; 5793 5794 u8 reserved_at_40[0x40]; 5795 }; 5796 5797 struct mlx5_ifc_query_scheduling_element_out_bits { 5798 u8 opcode[0x10]; 5799 u8 reserved_at_10[0x10]; 5800 5801 u8 reserved_at_20[0x10]; 5802 u8 op_mod[0x10]; 5803 5804 u8 reserved_at_40[0xc0]; 5805 5806 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5807 5808 u8 reserved_at_300[0x100]; 5809 }; 5810 5811 enum { 5812 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5813 SCHEDULING_HIERARCHY_NIC = 0x3, 5814 }; 5815 5816 struct mlx5_ifc_query_scheduling_element_in_bits { 5817 u8 opcode[0x10]; 5818 u8 reserved_at_10[0x10]; 5819 5820 u8 reserved_at_20[0x10]; 5821 u8 op_mod[0x10]; 5822 5823 u8 scheduling_hierarchy[0x8]; 5824 u8 reserved_at_48[0x18]; 5825 5826 u8 scheduling_element_id[0x20]; 5827 5828 u8 reserved_at_80[0x180]; 5829 }; 5830 5831 struct mlx5_ifc_query_rqt_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_at_8[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_at_40[0xc0]; 5838 5839 struct mlx5_ifc_rqtc_bits rqt_context; 5840 }; 5841 5842 struct mlx5_ifc_query_rqt_in_bits { 5843 u8 opcode[0x10]; 5844 u8 reserved_at_10[0x10]; 5845 5846 u8 reserved_at_20[0x10]; 5847 u8 op_mod[0x10]; 5848 5849 u8 reserved_at_40[0x8]; 5850 u8 rqtn[0x18]; 5851 5852 u8 reserved_at_60[0x20]; 5853 }; 5854 5855 struct mlx5_ifc_query_rq_out_bits { 5856 u8 status[0x8]; 5857 u8 reserved_at_8[0x18]; 5858 5859 u8 syndrome[0x20]; 5860 5861 u8 reserved_at_40[0xc0]; 5862 5863 struct mlx5_ifc_rqc_bits rq_context; 5864 }; 5865 5866 struct mlx5_ifc_query_rq_in_bits { 5867 u8 opcode[0x10]; 5868 u8 reserved_at_10[0x10]; 5869 5870 u8 reserved_at_20[0x10]; 5871 u8 op_mod[0x10]; 5872 5873 u8 reserved_at_40[0x8]; 5874 u8 rqn[0x18]; 5875 5876 u8 reserved_at_60[0x20]; 5877 }; 5878 5879 struct mlx5_ifc_query_roce_address_out_bits { 5880 u8 status[0x8]; 5881 u8 reserved_at_8[0x18]; 5882 5883 u8 syndrome[0x20]; 5884 5885 u8 reserved_at_40[0x40]; 5886 5887 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5888 }; 5889 5890 struct mlx5_ifc_query_roce_address_in_bits { 5891 u8 opcode[0x10]; 5892 u8 reserved_at_10[0x10]; 5893 5894 u8 reserved_at_20[0x10]; 5895 u8 op_mod[0x10]; 5896 5897 u8 roce_address_index[0x10]; 5898 u8 reserved_at_50[0xc]; 5899 u8 vhca_port_num[0x4]; 5900 5901 u8 reserved_at_60[0x20]; 5902 }; 5903 5904 struct mlx5_ifc_query_rmp_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_at_8[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_at_40[0xc0]; 5911 5912 struct mlx5_ifc_rmpc_bits rmp_context; 5913 }; 5914 5915 struct mlx5_ifc_query_rmp_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_at_40[0x8]; 5923 u8 rmpn[0x18]; 5924 5925 u8 reserved_at_60[0x20]; 5926 }; 5927 5928 struct mlx5_ifc_cqe_error_syndrome_bits { 5929 u8 hw_error_syndrome[0x8]; 5930 u8 hw_syndrome_type[0x4]; 5931 u8 reserved_at_c[0x4]; 5932 u8 vendor_error_syndrome[0x8]; 5933 u8 syndrome[0x8]; 5934 }; 5935 5936 struct mlx5_ifc_qp_context_extension_bits { 5937 u8 reserved_at_0[0x60]; 5938 5939 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5940 5941 u8 reserved_at_80[0x580]; 5942 }; 5943 5944 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5945 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5946 5947 u8 pas[0][0x40]; 5948 }; 5949 5950 struct mlx5_ifc_qp_pas_list_in_bits { 5951 struct mlx5_ifc_cmd_pas_bits pas[0]; 5952 }; 5953 5954 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5955 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5956 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5957 }; 5958 5959 struct mlx5_ifc_query_qp_out_bits { 5960 u8 status[0x8]; 5961 u8 reserved_at_8[0x18]; 5962 5963 u8 syndrome[0x20]; 5964 5965 u8 reserved_at_40[0x40]; 5966 5967 u8 opt_param_mask[0x20]; 5968 5969 u8 ece[0x20]; 5970 5971 struct mlx5_ifc_qpc_bits qpc; 5972 5973 u8 reserved_at_800[0x80]; 5974 5975 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5976 }; 5977 5978 struct mlx5_ifc_query_qp_in_bits { 5979 u8 opcode[0x10]; 5980 u8 reserved_at_10[0x10]; 5981 5982 u8 reserved_at_20[0x10]; 5983 u8 op_mod[0x10]; 5984 5985 u8 qpc_ext[0x1]; 5986 u8 reserved_at_41[0x7]; 5987 u8 qpn[0x18]; 5988 5989 u8 reserved_at_60[0x20]; 5990 }; 5991 5992 struct mlx5_ifc_query_q_counter_out_bits { 5993 u8 status[0x8]; 5994 u8 reserved_at_8[0x18]; 5995 5996 u8 syndrome[0x20]; 5997 5998 u8 reserved_at_40[0x40]; 5999 6000 u8 rx_write_requests[0x20]; 6001 6002 u8 reserved_at_a0[0x20]; 6003 6004 u8 rx_read_requests[0x20]; 6005 6006 u8 reserved_at_e0[0x20]; 6007 6008 u8 rx_atomic_requests[0x20]; 6009 6010 u8 reserved_at_120[0x20]; 6011 6012 u8 rx_dct_connect[0x20]; 6013 6014 u8 reserved_at_160[0x20]; 6015 6016 u8 out_of_buffer[0x20]; 6017 6018 u8 reserved_at_1a0[0x20]; 6019 6020 u8 out_of_sequence[0x20]; 6021 6022 u8 reserved_at_1e0[0x20]; 6023 6024 u8 duplicate_request[0x20]; 6025 6026 u8 reserved_at_220[0x20]; 6027 6028 u8 rnr_nak_retry_err[0x20]; 6029 6030 u8 reserved_at_260[0x20]; 6031 6032 u8 packet_seq_err[0x20]; 6033 6034 u8 reserved_at_2a0[0x20]; 6035 6036 u8 implied_nak_seq_err[0x20]; 6037 6038 u8 reserved_at_2e0[0x20]; 6039 6040 u8 local_ack_timeout_err[0x20]; 6041 6042 u8 reserved_at_320[0x60]; 6043 6044 u8 req_rnr_retries_exceeded[0x20]; 6045 6046 u8 reserved_at_3a0[0x20]; 6047 6048 u8 resp_local_length_error[0x20]; 6049 6050 u8 req_local_length_error[0x20]; 6051 6052 u8 resp_local_qp_error[0x20]; 6053 6054 u8 local_operation_error[0x20]; 6055 6056 u8 resp_local_protection[0x20]; 6057 6058 u8 req_local_protection[0x20]; 6059 6060 u8 resp_cqe_error[0x20]; 6061 6062 u8 req_cqe_error[0x20]; 6063 6064 u8 req_mw_binding[0x20]; 6065 6066 u8 req_bad_response[0x20]; 6067 6068 u8 req_remote_invalid_request[0x20]; 6069 6070 u8 resp_remote_invalid_request[0x20]; 6071 6072 u8 req_remote_access_errors[0x20]; 6073 6074 u8 resp_remote_access_errors[0x20]; 6075 6076 u8 req_remote_operation_errors[0x20]; 6077 6078 u8 req_transport_retries_exceeded[0x20]; 6079 6080 u8 cq_overflow[0x20]; 6081 6082 u8 resp_cqe_flush_error[0x20]; 6083 6084 u8 req_cqe_flush_error[0x20]; 6085 6086 u8 reserved_at_620[0x20]; 6087 6088 u8 roce_adp_retrans[0x20]; 6089 6090 u8 roce_adp_retrans_to[0x20]; 6091 6092 u8 roce_slow_restart[0x20]; 6093 6094 u8 roce_slow_restart_cnps[0x20]; 6095 6096 u8 roce_slow_restart_trans[0x20]; 6097 6098 u8 reserved_at_6e0[0x120]; 6099 }; 6100 6101 struct mlx5_ifc_query_q_counter_in_bits { 6102 u8 opcode[0x10]; 6103 u8 reserved_at_10[0x10]; 6104 6105 u8 reserved_at_20[0x10]; 6106 u8 op_mod[0x10]; 6107 6108 u8 other_vport[0x1]; 6109 u8 reserved_at_41[0xf]; 6110 u8 vport_number[0x10]; 6111 6112 u8 reserved_at_60[0x60]; 6113 6114 u8 clear[0x1]; 6115 u8 aggregate[0x1]; 6116 u8 reserved_at_c2[0x1e]; 6117 6118 u8 reserved_at_e0[0x18]; 6119 u8 counter_set_id[0x8]; 6120 }; 6121 6122 struct mlx5_ifc_query_pages_out_bits { 6123 u8 status[0x8]; 6124 u8 reserved_at_8[0x18]; 6125 6126 u8 syndrome[0x20]; 6127 6128 u8 embedded_cpu_function[0x1]; 6129 u8 reserved_at_41[0xf]; 6130 u8 function_id[0x10]; 6131 6132 u8 num_pages[0x20]; 6133 }; 6134 6135 enum { 6136 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6137 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6138 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6139 }; 6140 6141 struct mlx5_ifc_query_pages_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_at_10[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 embedded_cpu_function[0x1]; 6149 u8 reserved_at_41[0xf]; 6150 u8 function_id[0x10]; 6151 6152 u8 reserved_at_60[0x20]; 6153 }; 6154 6155 struct mlx5_ifc_query_nic_vport_context_out_bits { 6156 u8 status[0x8]; 6157 u8 reserved_at_8[0x18]; 6158 6159 u8 syndrome[0x20]; 6160 6161 u8 reserved_at_40[0x40]; 6162 6163 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6164 }; 6165 6166 struct mlx5_ifc_query_nic_vport_context_in_bits { 6167 u8 opcode[0x10]; 6168 u8 reserved_at_10[0x10]; 6169 6170 u8 reserved_at_20[0x10]; 6171 u8 op_mod[0x10]; 6172 6173 u8 other_vport[0x1]; 6174 u8 reserved_at_41[0xf]; 6175 u8 vport_number[0x10]; 6176 6177 u8 reserved_at_60[0x5]; 6178 u8 allowed_list_type[0x3]; 6179 u8 reserved_at_68[0x18]; 6180 }; 6181 6182 struct mlx5_ifc_query_mkey_out_bits { 6183 u8 status[0x8]; 6184 u8 reserved_at_8[0x18]; 6185 6186 u8 syndrome[0x20]; 6187 6188 u8 reserved_at_40[0x40]; 6189 6190 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6191 6192 u8 reserved_at_280[0x600]; 6193 6194 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6195 6196 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6197 }; 6198 6199 struct mlx5_ifc_query_mkey_in_bits { 6200 u8 opcode[0x10]; 6201 u8 reserved_at_10[0x10]; 6202 6203 u8 reserved_at_20[0x10]; 6204 u8 op_mod[0x10]; 6205 6206 u8 reserved_at_40[0x8]; 6207 u8 mkey_index[0x18]; 6208 6209 u8 pg_access[0x1]; 6210 u8 reserved_at_61[0x1f]; 6211 }; 6212 6213 struct mlx5_ifc_query_mad_demux_out_bits { 6214 u8 status[0x8]; 6215 u8 reserved_at_8[0x18]; 6216 6217 u8 syndrome[0x20]; 6218 6219 u8 reserved_at_40[0x40]; 6220 6221 u8 mad_dumux_parameters_block[0x20]; 6222 }; 6223 6224 struct mlx5_ifc_query_mad_demux_in_bits { 6225 u8 opcode[0x10]; 6226 u8 reserved_at_10[0x10]; 6227 6228 u8 reserved_at_20[0x10]; 6229 u8 op_mod[0x10]; 6230 6231 u8 reserved_at_40[0x40]; 6232 }; 6233 6234 struct mlx5_ifc_query_l2_table_entry_out_bits { 6235 u8 status[0x8]; 6236 u8 reserved_at_8[0x18]; 6237 6238 u8 syndrome[0x20]; 6239 6240 u8 reserved_at_40[0xa0]; 6241 6242 u8 reserved_at_e0[0x13]; 6243 u8 vlan_valid[0x1]; 6244 u8 vlan[0xc]; 6245 6246 struct mlx5_ifc_mac_address_layout_bits mac_address; 6247 6248 u8 reserved_at_140[0xc0]; 6249 }; 6250 6251 struct mlx5_ifc_query_l2_table_entry_in_bits { 6252 u8 opcode[0x10]; 6253 u8 reserved_at_10[0x10]; 6254 6255 u8 reserved_at_20[0x10]; 6256 u8 op_mod[0x10]; 6257 6258 u8 reserved_at_40[0x60]; 6259 6260 u8 reserved_at_a0[0x8]; 6261 u8 table_index[0x18]; 6262 6263 u8 reserved_at_c0[0x140]; 6264 }; 6265 6266 struct mlx5_ifc_query_issi_out_bits { 6267 u8 status[0x8]; 6268 u8 reserved_at_8[0x18]; 6269 6270 u8 syndrome[0x20]; 6271 6272 u8 reserved_at_40[0x10]; 6273 u8 current_issi[0x10]; 6274 6275 u8 reserved_at_60[0xa0]; 6276 6277 u8 reserved_at_100[76][0x8]; 6278 u8 supported_issi_dw0[0x20]; 6279 }; 6280 6281 struct mlx5_ifc_query_issi_in_bits { 6282 u8 opcode[0x10]; 6283 u8 reserved_at_10[0x10]; 6284 6285 u8 reserved_at_20[0x10]; 6286 u8 op_mod[0x10]; 6287 6288 u8 reserved_at_40[0x40]; 6289 }; 6290 6291 struct mlx5_ifc_set_driver_version_out_bits { 6292 u8 status[0x8]; 6293 u8 reserved_0[0x18]; 6294 6295 u8 syndrome[0x20]; 6296 u8 reserved_1[0x40]; 6297 }; 6298 6299 struct mlx5_ifc_set_driver_version_in_bits { 6300 u8 opcode[0x10]; 6301 u8 reserved_0[0x10]; 6302 6303 u8 reserved_1[0x10]; 6304 u8 op_mod[0x10]; 6305 6306 u8 reserved_2[0x40]; 6307 u8 driver_version[64][0x8]; 6308 }; 6309 6310 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6311 u8 status[0x8]; 6312 u8 reserved_at_8[0x18]; 6313 6314 u8 syndrome[0x20]; 6315 6316 u8 reserved_at_40[0x40]; 6317 6318 struct mlx5_ifc_pkey_bits pkey[]; 6319 }; 6320 6321 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6322 u8 opcode[0x10]; 6323 u8 reserved_at_10[0x10]; 6324 6325 u8 reserved_at_20[0x10]; 6326 u8 op_mod[0x10]; 6327 6328 u8 other_vport[0x1]; 6329 u8 reserved_at_41[0xb]; 6330 u8 port_num[0x4]; 6331 u8 vport_number[0x10]; 6332 6333 u8 reserved_at_60[0x10]; 6334 u8 pkey_index[0x10]; 6335 }; 6336 6337 enum { 6338 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6339 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6340 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6341 }; 6342 6343 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6344 u8 status[0x8]; 6345 u8 reserved_at_8[0x18]; 6346 6347 u8 syndrome[0x20]; 6348 6349 u8 reserved_at_40[0x20]; 6350 6351 u8 gids_num[0x10]; 6352 u8 reserved_at_70[0x10]; 6353 6354 struct mlx5_ifc_array128_auto_bits gid[]; 6355 }; 6356 6357 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6358 u8 opcode[0x10]; 6359 u8 reserved_at_10[0x10]; 6360 6361 u8 reserved_at_20[0x10]; 6362 u8 op_mod[0x10]; 6363 6364 u8 other_vport[0x1]; 6365 u8 reserved_at_41[0xb]; 6366 u8 port_num[0x4]; 6367 u8 vport_number[0x10]; 6368 6369 u8 reserved_at_60[0x10]; 6370 u8 gid_index[0x10]; 6371 }; 6372 6373 struct mlx5_ifc_query_hca_vport_context_out_bits { 6374 u8 status[0x8]; 6375 u8 reserved_at_8[0x18]; 6376 6377 u8 syndrome[0x20]; 6378 6379 u8 reserved_at_40[0x40]; 6380 6381 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6382 }; 6383 6384 struct mlx5_ifc_query_hca_vport_context_in_bits { 6385 u8 opcode[0x10]; 6386 u8 reserved_at_10[0x10]; 6387 6388 u8 reserved_at_20[0x10]; 6389 u8 op_mod[0x10]; 6390 6391 u8 other_vport[0x1]; 6392 u8 reserved_at_41[0xb]; 6393 u8 port_num[0x4]; 6394 u8 vport_number[0x10]; 6395 6396 u8 reserved_at_60[0x20]; 6397 }; 6398 6399 struct mlx5_ifc_query_hca_cap_out_bits { 6400 u8 status[0x8]; 6401 u8 reserved_at_8[0x18]; 6402 6403 u8 syndrome[0x20]; 6404 6405 u8 reserved_at_40[0x40]; 6406 6407 union mlx5_ifc_hca_cap_union_bits capability; 6408 }; 6409 6410 struct mlx5_ifc_query_hca_cap_in_bits { 6411 u8 opcode[0x10]; 6412 u8 reserved_at_10[0x10]; 6413 6414 u8 reserved_at_20[0x10]; 6415 u8 op_mod[0x10]; 6416 6417 u8 other_function[0x1]; 6418 u8 ec_vf_function[0x1]; 6419 u8 reserved_at_42[0x1]; 6420 u8 function_id_type[0x1]; 6421 u8 reserved_at_44[0xc]; 6422 u8 function_id[0x10]; 6423 6424 u8 reserved_at_60[0x20]; 6425 }; 6426 6427 struct mlx5_ifc_other_hca_cap_bits { 6428 u8 roce[0x1]; 6429 u8 reserved_at_1[0x27f]; 6430 }; 6431 6432 struct mlx5_ifc_query_other_hca_cap_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_at_8[0x18]; 6435 6436 u8 syndrome[0x20]; 6437 6438 u8 reserved_at_40[0x40]; 6439 6440 struct mlx5_ifc_other_hca_cap_bits other_capability; 6441 }; 6442 6443 struct mlx5_ifc_query_other_hca_cap_in_bits { 6444 u8 opcode[0x10]; 6445 u8 reserved_at_10[0x10]; 6446 6447 u8 reserved_at_20[0x10]; 6448 u8 op_mod[0x10]; 6449 6450 u8 reserved_at_40[0x10]; 6451 u8 function_id[0x10]; 6452 6453 u8 reserved_at_60[0x20]; 6454 }; 6455 6456 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6457 u8 status[0x8]; 6458 u8 reserved_at_8[0x18]; 6459 6460 u8 syndrome[0x20]; 6461 6462 u8 reserved_at_40[0x40]; 6463 }; 6464 6465 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6466 u8 opcode[0x10]; 6467 u8 reserved_at_10[0x10]; 6468 6469 u8 reserved_at_20[0x10]; 6470 u8 op_mod[0x10]; 6471 6472 u8 reserved_at_40[0x10]; 6473 u8 function_id[0x10]; 6474 u8 field_select[0x20]; 6475 6476 struct mlx5_ifc_other_hca_cap_bits other_capability; 6477 }; 6478 6479 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6480 u8 sw_owner_icm_root_1[0x40]; 6481 6482 u8 sw_owner_icm_root_0[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_rtc_params_bits { 6486 u8 rtc_id_0[0x20]; 6487 6488 u8 rtc_id_1[0x20]; 6489 6490 u8 reserved_at_40[0x40]; 6491 }; 6492 6493 struct mlx5_ifc_flow_table_context_bits { 6494 u8 reformat_en[0x1]; 6495 u8 decap_en[0x1]; 6496 u8 sw_owner[0x1]; 6497 u8 termination_table[0x1]; 6498 u8 table_miss_action[0x4]; 6499 u8 level[0x8]; 6500 u8 rtc_valid[0x1]; 6501 u8 reserved_at_11[0x7]; 6502 u8 log_size[0x8]; 6503 6504 u8 reserved_at_20[0x8]; 6505 u8 table_miss_id[0x18]; 6506 6507 u8 reserved_at_40[0x8]; 6508 u8 lag_master_next_table_id[0x18]; 6509 6510 u8 reserved_at_60[0x60]; 6511 6512 union { 6513 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6514 struct mlx5_ifc_rtc_params_bits hws; 6515 }; 6516 }; 6517 6518 struct mlx5_ifc_query_flow_table_out_bits { 6519 u8 status[0x8]; 6520 u8 reserved_at_8[0x18]; 6521 6522 u8 syndrome[0x20]; 6523 6524 u8 reserved_at_40[0x80]; 6525 6526 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6527 }; 6528 6529 struct mlx5_ifc_query_flow_table_in_bits { 6530 u8 opcode[0x10]; 6531 u8 reserved_at_10[0x10]; 6532 6533 u8 reserved_at_20[0x10]; 6534 u8 op_mod[0x10]; 6535 6536 u8 reserved_at_40[0x40]; 6537 6538 u8 table_type[0x8]; 6539 u8 reserved_at_88[0x18]; 6540 6541 u8 reserved_at_a0[0x8]; 6542 u8 table_id[0x18]; 6543 6544 u8 reserved_at_c0[0x140]; 6545 }; 6546 6547 struct mlx5_ifc_query_fte_out_bits { 6548 u8 status[0x8]; 6549 u8 reserved_at_8[0x18]; 6550 6551 u8 syndrome[0x20]; 6552 6553 u8 reserved_at_40[0x1c0]; 6554 6555 struct mlx5_ifc_flow_context_bits flow_context; 6556 }; 6557 6558 struct mlx5_ifc_query_fte_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_at_10[0x10]; 6561 6562 u8 reserved_at_20[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 reserved_at_40[0x40]; 6566 6567 u8 table_type[0x8]; 6568 u8 reserved_at_88[0x18]; 6569 6570 u8 reserved_at_a0[0x8]; 6571 u8 table_id[0x18]; 6572 6573 u8 reserved_at_c0[0x40]; 6574 6575 u8 flow_index[0x20]; 6576 6577 u8 reserved_at_120[0xe0]; 6578 }; 6579 6580 struct mlx5_ifc_match_definer_format_0_bits { 6581 u8 reserved_at_0[0x100]; 6582 6583 u8 metadata_reg_c_0[0x20]; 6584 6585 u8 metadata_reg_c_1[0x20]; 6586 6587 u8 outer_dmac_47_16[0x20]; 6588 6589 u8 outer_dmac_15_0[0x10]; 6590 u8 outer_ethertype[0x10]; 6591 6592 u8 reserved_at_180[0x1]; 6593 u8 sx_sniffer[0x1]; 6594 u8 functional_lb[0x1]; 6595 u8 outer_ip_frag[0x1]; 6596 u8 outer_qp_type[0x2]; 6597 u8 outer_encap_type[0x2]; 6598 u8 port_number[0x2]; 6599 u8 outer_l3_type[0x2]; 6600 u8 outer_l4_type[0x2]; 6601 u8 outer_first_vlan_type[0x2]; 6602 u8 outer_first_vlan_prio[0x3]; 6603 u8 outer_first_vlan_cfi[0x1]; 6604 u8 outer_first_vlan_vid[0xc]; 6605 6606 u8 outer_l4_type_ext[0x4]; 6607 u8 reserved_at_1a4[0x2]; 6608 u8 outer_ipsec_layer[0x2]; 6609 u8 outer_l2_type[0x2]; 6610 u8 force_lb[0x1]; 6611 u8 outer_l2_ok[0x1]; 6612 u8 outer_l3_ok[0x1]; 6613 u8 outer_l4_ok[0x1]; 6614 u8 outer_second_vlan_type[0x2]; 6615 u8 outer_second_vlan_prio[0x3]; 6616 u8 outer_second_vlan_cfi[0x1]; 6617 u8 outer_second_vlan_vid[0xc]; 6618 6619 u8 outer_smac_47_16[0x20]; 6620 6621 u8 outer_smac_15_0[0x10]; 6622 u8 inner_ipv4_checksum_ok[0x1]; 6623 u8 inner_l4_checksum_ok[0x1]; 6624 u8 outer_ipv4_checksum_ok[0x1]; 6625 u8 outer_l4_checksum_ok[0x1]; 6626 u8 inner_l3_ok[0x1]; 6627 u8 inner_l4_ok[0x1]; 6628 u8 outer_l3_ok_duplicate[0x1]; 6629 u8 outer_l4_ok_duplicate[0x1]; 6630 u8 outer_tcp_cwr[0x1]; 6631 u8 outer_tcp_ece[0x1]; 6632 u8 outer_tcp_urg[0x1]; 6633 u8 outer_tcp_ack[0x1]; 6634 u8 outer_tcp_psh[0x1]; 6635 u8 outer_tcp_rst[0x1]; 6636 u8 outer_tcp_syn[0x1]; 6637 u8 outer_tcp_fin[0x1]; 6638 }; 6639 6640 struct mlx5_ifc_match_definer_format_22_bits { 6641 u8 reserved_at_0[0x100]; 6642 6643 u8 outer_ip_src_addr[0x20]; 6644 6645 u8 outer_ip_dest_addr[0x20]; 6646 6647 u8 outer_l4_sport[0x10]; 6648 u8 outer_l4_dport[0x10]; 6649 6650 u8 reserved_at_160[0x1]; 6651 u8 sx_sniffer[0x1]; 6652 u8 functional_lb[0x1]; 6653 u8 outer_ip_frag[0x1]; 6654 u8 outer_qp_type[0x2]; 6655 u8 outer_encap_type[0x2]; 6656 u8 port_number[0x2]; 6657 u8 outer_l3_type[0x2]; 6658 u8 outer_l4_type[0x2]; 6659 u8 outer_first_vlan_type[0x2]; 6660 u8 outer_first_vlan_prio[0x3]; 6661 u8 outer_first_vlan_cfi[0x1]; 6662 u8 outer_first_vlan_vid[0xc]; 6663 6664 u8 metadata_reg_c_0[0x20]; 6665 6666 u8 outer_dmac_47_16[0x20]; 6667 6668 u8 outer_smac_47_16[0x20]; 6669 6670 u8 outer_smac_15_0[0x10]; 6671 u8 outer_dmac_15_0[0x10]; 6672 }; 6673 6674 struct mlx5_ifc_match_definer_format_23_bits { 6675 u8 reserved_at_0[0x100]; 6676 6677 u8 inner_ip_src_addr[0x20]; 6678 6679 u8 inner_ip_dest_addr[0x20]; 6680 6681 u8 inner_l4_sport[0x10]; 6682 u8 inner_l4_dport[0x10]; 6683 6684 u8 reserved_at_160[0x1]; 6685 u8 sx_sniffer[0x1]; 6686 u8 functional_lb[0x1]; 6687 u8 inner_ip_frag[0x1]; 6688 u8 inner_qp_type[0x2]; 6689 u8 inner_encap_type[0x2]; 6690 u8 port_number[0x2]; 6691 u8 inner_l3_type[0x2]; 6692 u8 inner_l4_type[0x2]; 6693 u8 inner_first_vlan_type[0x2]; 6694 u8 inner_first_vlan_prio[0x3]; 6695 u8 inner_first_vlan_cfi[0x1]; 6696 u8 inner_first_vlan_vid[0xc]; 6697 6698 u8 tunnel_header_0[0x20]; 6699 6700 u8 inner_dmac_47_16[0x20]; 6701 6702 u8 inner_smac_47_16[0x20]; 6703 6704 u8 inner_smac_15_0[0x10]; 6705 u8 inner_dmac_15_0[0x10]; 6706 }; 6707 6708 struct mlx5_ifc_match_definer_format_29_bits { 6709 u8 reserved_at_0[0xc0]; 6710 6711 u8 outer_ip_dest_addr[0x80]; 6712 6713 u8 outer_ip_src_addr[0x80]; 6714 6715 u8 outer_l4_sport[0x10]; 6716 u8 outer_l4_dport[0x10]; 6717 6718 u8 reserved_at_1e0[0x20]; 6719 }; 6720 6721 struct mlx5_ifc_match_definer_format_30_bits { 6722 u8 reserved_at_0[0xa0]; 6723 6724 u8 outer_ip_dest_addr[0x80]; 6725 6726 u8 outer_ip_src_addr[0x80]; 6727 6728 u8 outer_dmac_47_16[0x20]; 6729 6730 u8 outer_smac_47_16[0x20]; 6731 6732 u8 outer_smac_15_0[0x10]; 6733 u8 outer_dmac_15_0[0x10]; 6734 }; 6735 6736 struct mlx5_ifc_match_definer_format_31_bits { 6737 u8 reserved_at_0[0xc0]; 6738 6739 u8 inner_ip_dest_addr[0x80]; 6740 6741 u8 inner_ip_src_addr[0x80]; 6742 6743 u8 inner_l4_sport[0x10]; 6744 u8 inner_l4_dport[0x10]; 6745 6746 u8 reserved_at_1e0[0x20]; 6747 }; 6748 6749 struct mlx5_ifc_match_definer_format_32_bits { 6750 u8 reserved_at_0[0xa0]; 6751 6752 u8 inner_ip_dest_addr[0x80]; 6753 6754 u8 inner_ip_src_addr[0x80]; 6755 6756 u8 inner_dmac_47_16[0x20]; 6757 6758 u8 inner_smac_47_16[0x20]; 6759 6760 u8 inner_smac_15_0[0x10]; 6761 u8 inner_dmac_15_0[0x10]; 6762 }; 6763 6764 enum { 6765 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6766 }; 6767 6768 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6769 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6770 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6771 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6772 6773 struct mlx5_ifc_match_definer_match_mask_bits { 6774 u8 reserved_at_1c0[5][0x20]; 6775 u8 match_dw_8[0x20]; 6776 u8 match_dw_7[0x20]; 6777 u8 match_dw_6[0x20]; 6778 u8 match_dw_5[0x20]; 6779 u8 match_dw_4[0x20]; 6780 u8 match_dw_3[0x20]; 6781 u8 match_dw_2[0x20]; 6782 u8 match_dw_1[0x20]; 6783 u8 match_dw_0[0x20]; 6784 6785 u8 match_byte_7[0x8]; 6786 u8 match_byte_6[0x8]; 6787 u8 match_byte_5[0x8]; 6788 u8 match_byte_4[0x8]; 6789 6790 u8 match_byte_3[0x8]; 6791 u8 match_byte_2[0x8]; 6792 u8 match_byte_1[0x8]; 6793 u8 match_byte_0[0x8]; 6794 }; 6795 6796 struct mlx5_ifc_match_definer_bits { 6797 u8 modify_field_select[0x40]; 6798 6799 u8 reserved_at_40[0x40]; 6800 6801 u8 reserved_at_80[0x10]; 6802 u8 format_id[0x10]; 6803 6804 u8 reserved_at_a0[0x60]; 6805 6806 u8 format_select_dw3[0x8]; 6807 u8 format_select_dw2[0x8]; 6808 u8 format_select_dw1[0x8]; 6809 u8 format_select_dw0[0x8]; 6810 6811 u8 format_select_dw7[0x8]; 6812 u8 format_select_dw6[0x8]; 6813 u8 format_select_dw5[0x8]; 6814 u8 format_select_dw4[0x8]; 6815 6816 u8 reserved_at_100[0x18]; 6817 u8 format_select_dw8[0x8]; 6818 6819 u8 reserved_at_120[0x20]; 6820 6821 u8 format_select_byte3[0x8]; 6822 u8 format_select_byte2[0x8]; 6823 u8 format_select_byte1[0x8]; 6824 u8 format_select_byte0[0x8]; 6825 6826 u8 format_select_byte7[0x8]; 6827 u8 format_select_byte6[0x8]; 6828 u8 format_select_byte5[0x8]; 6829 u8 format_select_byte4[0x8]; 6830 6831 u8 reserved_at_180[0x40]; 6832 6833 union { 6834 struct { 6835 u8 match_mask[16][0x20]; 6836 }; 6837 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6838 }; 6839 }; 6840 6841 struct mlx5_ifc_general_obj_create_param_bits { 6842 u8 alias_object[0x1]; 6843 u8 reserved_at_1[0x2]; 6844 u8 log_obj_range[0x5]; 6845 u8 reserved_at_8[0x18]; 6846 }; 6847 6848 struct mlx5_ifc_general_obj_query_param_bits { 6849 u8 alias_object[0x1]; 6850 u8 obj_offset[0x1f]; 6851 }; 6852 6853 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6854 u8 opcode[0x10]; 6855 u8 uid[0x10]; 6856 6857 u8 vhca_tunnel_id[0x10]; 6858 u8 obj_type[0x10]; 6859 6860 u8 obj_id[0x20]; 6861 6862 union { 6863 struct mlx5_ifc_general_obj_create_param_bits create; 6864 struct mlx5_ifc_general_obj_query_param_bits query; 6865 } op_param; 6866 }; 6867 6868 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6869 u8 status[0x8]; 6870 u8 reserved_at_8[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 obj_id[0x20]; 6875 6876 u8 reserved_at_60[0x20]; 6877 }; 6878 6879 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6880 u8 opcode[0x10]; 6881 u8 uid[0x10]; 6882 u8 reserved_at_20[0x10]; 6883 u8 op_mod[0x10]; 6884 u8 reserved_at_40[0x50]; 6885 u8 object_type_to_be_accessed[0x10]; 6886 u8 object_id_to_be_accessed[0x20]; 6887 u8 reserved_at_c0[0x40]; 6888 union { 6889 u8 access_key_raw[0x100]; 6890 u8 access_key[8][0x20]; 6891 }; 6892 }; 6893 6894 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6895 u8 status[0x8]; 6896 u8 reserved_at_8[0x18]; 6897 u8 syndrome[0x20]; 6898 u8 reserved_at_40[0x40]; 6899 }; 6900 6901 struct mlx5_ifc_modify_header_arg_bits { 6902 u8 reserved_at_0[0x80]; 6903 6904 u8 reserved_at_80[0x8]; 6905 u8 access_pd[0x18]; 6906 }; 6907 6908 struct mlx5_ifc_create_modify_header_arg_in_bits { 6909 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6910 struct mlx5_ifc_modify_header_arg_bits arg; 6911 }; 6912 6913 struct mlx5_ifc_create_match_definer_in_bits { 6914 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6915 6916 struct mlx5_ifc_match_definer_bits obj_context; 6917 }; 6918 6919 struct mlx5_ifc_create_match_definer_out_bits { 6920 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6921 }; 6922 6923 struct mlx5_ifc_alias_context_bits { 6924 u8 vhca_id_to_be_accessed[0x10]; 6925 u8 reserved_at_10[0xd]; 6926 u8 status[0x3]; 6927 u8 object_id_to_be_accessed[0x20]; 6928 u8 reserved_at_40[0x40]; 6929 union { 6930 u8 access_key_raw[0x100]; 6931 u8 access_key[8][0x20]; 6932 }; 6933 u8 metadata[0x80]; 6934 }; 6935 6936 struct mlx5_ifc_create_alias_obj_in_bits { 6937 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6938 struct mlx5_ifc_alias_context_bits alias_ctx; 6939 }; 6940 6941 enum { 6942 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6943 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6944 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6945 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6946 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6947 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6948 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6949 }; 6950 6951 struct mlx5_ifc_query_flow_group_out_bits { 6952 u8 status[0x8]; 6953 u8 reserved_at_8[0x18]; 6954 6955 u8 syndrome[0x20]; 6956 6957 u8 reserved_at_40[0xa0]; 6958 6959 u8 start_flow_index[0x20]; 6960 6961 u8 reserved_at_100[0x20]; 6962 6963 u8 end_flow_index[0x20]; 6964 6965 u8 reserved_at_140[0xa0]; 6966 6967 u8 reserved_at_1e0[0x18]; 6968 u8 match_criteria_enable[0x8]; 6969 6970 struct mlx5_ifc_fte_match_param_bits match_criteria; 6971 6972 u8 reserved_at_1200[0xe00]; 6973 }; 6974 6975 struct mlx5_ifc_query_flow_group_in_bits { 6976 u8 opcode[0x10]; 6977 u8 reserved_at_10[0x10]; 6978 6979 u8 reserved_at_20[0x10]; 6980 u8 op_mod[0x10]; 6981 6982 u8 reserved_at_40[0x40]; 6983 6984 u8 table_type[0x8]; 6985 u8 reserved_at_88[0x18]; 6986 6987 u8 reserved_at_a0[0x8]; 6988 u8 table_id[0x18]; 6989 6990 u8 group_id[0x20]; 6991 6992 u8 reserved_at_e0[0x120]; 6993 }; 6994 6995 struct mlx5_ifc_query_flow_counter_out_bits { 6996 u8 status[0x8]; 6997 u8 reserved_at_8[0x18]; 6998 6999 u8 syndrome[0x20]; 7000 7001 u8 reserved_at_40[0x40]; 7002 7003 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 7004 }; 7005 7006 struct mlx5_ifc_query_flow_counter_in_bits { 7007 u8 opcode[0x10]; 7008 u8 reserved_at_10[0x10]; 7009 7010 u8 reserved_at_20[0x10]; 7011 u8 op_mod[0x10]; 7012 7013 u8 reserved_at_40[0x80]; 7014 7015 u8 clear[0x1]; 7016 u8 reserved_at_c1[0xf]; 7017 u8 num_of_counters[0x10]; 7018 7019 u8 flow_counter_id[0x20]; 7020 }; 7021 7022 struct mlx5_ifc_query_esw_vport_context_out_bits { 7023 u8 status[0x8]; 7024 u8 reserved_at_8[0x18]; 7025 7026 u8 syndrome[0x20]; 7027 7028 u8 reserved_at_40[0x40]; 7029 7030 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7031 }; 7032 7033 struct mlx5_ifc_query_esw_vport_context_in_bits { 7034 u8 opcode[0x10]; 7035 u8 reserved_at_10[0x10]; 7036 7037 u8 reserved_at_20[0x10]; 7038 u8 op_mod[0x10]; 7039 7040 u8 other_vport[0x1]; 7041 u8 reserved_at_41[0xf]; 7042 u8 vport_number[0x10]; 7043 7044 u8 reserved_at_60[0x20]; 7045 }; 7046 7047 struct mlx5_ifc_destroy_esw_vport_out_bits { 7048 u8 status[0x8]; 7049 u8 reserved_at_8[0x18]; 7050 7051 u8 syndrome[0x20]; 7052 7053 u8 reserved_at_40[0x20]; 7054 }; 7055 7056 struct mlx5_ifc_destroy_esw_vport_in_bits { 7057 u8 opcode[0x10]; 7058 u8 uid[0x10]; 7059 7060 u8 reserved_at_20[0x10]; 7061 u8 op_mod[0x10]; 7062 7063 u8 reserved_at_40[0x10]; 7064 u8 vport_num[0x10]; 7065 7066 u8 reserved_at_60[0x20]; 7067 }; 7068 7069 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7070 u8 status[0x8]; 7071 u8 reserved_at_8[0x18]; 7072 7073 u8 syndrome[0x20]; 7074 7075 u8 reserved_at_40[0x40]; 7076 }; 7077 7078 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7079 u8 reserved_at_0[0x1b]; 7080 u8 fdb_to_vport_reg_c_id[0x1]; 7081 u8 vport_cvlan_insert[0x1]; 7082 u8 vport_svlan_insert[0x1]; 7083 u8 vport_cvlan_strip[0x1]; 7084 u8 vport_svlan_strip[0x1]; 7085 }; 7086 7087 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7088 u8 opcode[0x10]; 7089 u8 reserved_at_10[0x10]; 7090 7091 u8 reserved_at_20[0x10]; 7092 u8 op_mod[0x10]; 7093 7094 u8 other_vport[0x1]; 7095 u8 reserved_at_41[0xf]; 7096 u8 vport_number[0x10]; 7097 7098 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7099 7100 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7101 }; 7102 7103 struct mlx5_ifc_query_eq_out_bits { 7104 u8 status[0x8]; 7105 u8 reserved_at_8[0x18]; 7106 7107 u8 syndrome[0x20]; 7108 7109 u8 reserved_at_40[0x40]; 7110 7111 struct mlx5_ifc_eqc_bits eq_context_entry; 7112 7113 u8 reserved_at_280[0x40]; 7114 7115 u8 event_bitmask[0x40]; 7116 7117 u8 reserved_at_300[0x580]; 7118 7119 u8 pas[][0x40]; 7120 }; 7121 7122 struct mlx5_ifc_query_eq_in_bits { 7123 u8 opcode[0x10]; 7124 u8 reserved_at_10[0x10]; 7125 7126 u8 reserved_at_20[0x10]; 7127 u8 op_mod[0x10]; 7128 7129 u8 reserved_at_40[0x18]; 7130 u8 eq_number[0x8]; 7131 7132 u8 reserved_at_60[0x20]; 7133 }; 7134 7135 struct mlx5_ifc_packet_reformat_context_in_bits { 7136 u8 reformat_type[0x8]; 7137 u8 reserved_at_8[0x4]; 7138 u8 reformat_param_0[0x4]; 7139 u8 reserved_at_10[0x6]; 7140 u8 reformat_data_size[0xa]; 7141 7142 u8 reformat_param_1[0x8]; 7143 u8 reserved_at_28[0x8]; 7144 u8 reformat_data[2][0x8]; 7145 7146 u8 more_reformat_data[][0x8]; 7147 }; 7148 7149 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7150 u8 status[0x8]; 7151 u8 reserved_at_8[0x18]; 7152 7153 u8 syndrome[0x20]; 7154 7155 u8 reserved_at_40[0xa0]; 7156 7157 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7158 }; 7159 7160 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 packet_reformat_id[0x20]; 7168 7169 u8 reserved_at_60[0xa0]; 7170 }; 7171 7172 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7173 u8 status[0x8]; 7174 u8 reserved_at_8[0x18]; 7175 7176 u8 syndrome[0x20]; 7177 7178 u8 packet_reformat_id[0x20]; 7179 7180 u8 reserved_at_60[0x20]; 7181 }; 7182 7183 enum { 7184 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7185 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7186 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7187 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7188 }; 7189 7190 enum mlx5_reformat_ctx_type { 7191 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7192 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7193 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7194 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7195 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7196 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7197 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7198 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7199 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7200 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7201 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7202 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7203 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7204 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7205 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7206 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7207 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7208 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7209 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7210 }; 7211 7212 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7213 u8 opcode[0x10]; 7214 u8 reserved_at_10[0x10]; 7215 7216 u8 reserved_at_20[0x10]; 7217 u8 op_mod[0x10]; 7218 7219 u8 reserved_at_40[0xa0]; 7220 7221 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7222 }; 7223 7224 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7225 u8 status[0x8]; 7226 u8 reserved_at_8[0x18]; 7227 7228 u8 syndrome[0x20]; 7229 7230 u8 reserved_at_40[0x40]; 7231 }; 7232 7233 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7234 u8 opcode[0x10]; 7235 u8 reserved_at_10[0x10]; 7236 7237 u8 reserved_20[0x10]; 7238 u8 op_mod[0x10]; 7239 7240 u8 packet_reformat_id[0x20]; 7241 7242 u8 reserved_60[0x20]; 7243 }; 7244 7245 struct mlx5_ifc_set_action_in_bits { 7246 u8 action_type[0x4]; 7247 u8 field[0xc]; 7248 u8 reserved_at_10[0x3]; 7249 u8 offset[0x5]; 7250 u8 reserved_at_18[0x3]; 7251 u8 length[0x5]; 7252 7253 u8 data[0x20]; 7254 }; 7255 7256 struct mlx5_ifc_add_action_in_bits { 7257 u8 action_type[0x4]; 7258 u8 field[0xc]; 7259 u8 reserved_at_10[0x10]; 7260 7261 u8 data[0x20]; 7262 }; 7263 7264 struct mlx5_ifc_copy_action_in_bits { 7265 u8 action_type[0x4]; 7266 u8 src_field[0xc]; 7267 u8 reserved_at_10[0x3]; 7268 u8 src_offset[0x5]; 7269 u8 reserved_at_18[0x3]; 7270 u8 length[0x5]; 7271 7272 u8 reserved_at_20[0x4]; 7273 u8 dst_field[0xc]; 7274 u8 reserved_at_30[0x3]; 7275 u8 dst_offset[0x5]; 7276 u8 reserved_at_38[0x8]; 7277 }; 7278 7279 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7280 struct mlx5_ifc_set_action_in_bits set_action_in; 7281 struct mlx5_ifc_add_action_in_bits add_action_in; 7282 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7283 u8 reserved_at_0[0x40]; 7284 }; 7285 7286 enum { 7287 MLX5_ACTION_TYPE_SET = 0x1, 7288 MLX5_ACTION_TYPE_ADD = 0x2, 7289 MLX5_ACTION_TYPE_COPY = 0x3, 7290 }; 7291 7292 enum { 7293 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7294 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7295 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7296 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7297 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7298 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7299 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7300 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7301 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7302 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7303 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7304 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7305 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7306 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7307 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7308 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7309 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7310 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7311 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7312 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7313 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7314 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7315 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7316 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7317 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7318 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7319 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7320 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7321 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7322 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7323 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7324 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7325 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7326 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7327 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7328 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7329 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7330 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7331 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7332 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7333 }; 7334 7335 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_at_8[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 modify_header_id[0x20]; 7342 7343 u8 reserved_at_60[0x20]; 7344 }; 7345 7346 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7347 u8 opcode[0x10]; 7348 u8 reserved_at_10[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 reserved_at_40[0x20]; 7354 7355 u8 table_type[0x8]; 7356 u8 reserved_at_68[0x10]; 7357 u8 num_of_actions[0x8]; 7358 7359 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7360 }; 7361 7362 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7363 u8 status[0x8]; 7364 u8 reserved_at_8[0x18]; 7365 7366 u8 syndrome[0x20]; 7367 7368 u8 reserved_at_40[0x40]; 7369 }; 7370 7371 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7372 u8 opcode[0x10]; 7373 u8 reserved_at_10[0x10]; 7374 7375 u8 reserved_at_20[0x10]; 7376 u8 op_mod[0x10]; 7377 7378 u8 modify_header_id[0x20]; 7379 7380 u8 reserved_at_60[0x20]; 7381 }; 7382 7383 struct mlx5_ifc_query_modify_header_context_in_bits { 7384 u8 opcode[0x10]; 7385 u8 uid[0x10]; 7386 7387 u8 reserved_at_20[0x10]; 7388 u8 op_mod[0x10]; 7389 7390 u8 modify_header_id[0x20]; 7391 7392 u8 reserved_at_60[0xa0]; 7393 }; 7394 7395 struct mlx5_ifc_query_dct_out_bits { 7396 u8 status[0x8]; 7397 u8 reserved_at_8[0x18]; 7398 7399 u8 syndrome[0x20]; 7400 7401 u8 reserved_at_40[0x40]; 7402 7403 struct mlx5_ifc_dctc_bits dct_context_entry; 7404 7405 u8 reserved_at_280[0x180]; 7406 }; 7407 7408 struct mlx5_ifc_query_dct_in_bits { 7409 u8 opcode[0x10]; 7410 u8 reserved_at_10[0x10]; 7411 7412 u8 reserved_at_20[0x10]; 7413 u8 op_mod[0x10]; 7414 7415 u8 reserved_at_40[0x8]; 7416 u8 dctn[0x18]; 7417 7418 u8 reserved_at_60[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_query_cq_out_bits { 7422 u8 status[0x8]; 7423 u8 reserved_at_8[0x18]; 7424 7425 u8 syndrome[0x20]; 7426 7427 u8 reserved_at_40[0x40]; 7428 7429 struct mlx5_ifc_cqc_bits cq_context; 7430 7431 u8 reserved_at_280[0x600]; 7432 7433 u8 pas[][0x40]; 7434 }; 7435 7436 struct mlx5_ifc_query_cq_in_bits { 7437 u8 opcode[0x10]; 7438 u8 reserved_at_10[0x10]; 7439 7440 u8 reserved_at_20[0x10]; 7441 u8 op_mod[0x10]; 7442 7443 u8 reserved_at_40[0x8]; 7444 u8 cqn[0x18]; 7445 7446 u8 reserved_at_60[0x20]; 7447 }; 7448 7449 struct mlx5_ifc_query_cong_status_out_bits { 7450 u8 status[0x8]; 7451 u8 reserved_at_8[0x18]; 7452 7453 u8 syndrome[0x20]; 7454 7455 u8 reserved_at_40[0x20]; 7456 7457 u8 enable[0x1]; 7458 u8 tag_enable[0x1]; 7459 u8 reserved_at_62[0x1e]; 7460 }; 7461 7462 struct mlx5_ifc_query_cong_status_in_bits { 7463 u8 opcode[0x10]; 7464 u8 reserved_at_10[0x10]; 7465 7466 u8 reserved_at_20[0x10]; 7467 u8 op_mod[0x10]; 7468 7469 u8 reserved_at_40[0x18]; 7470 u8 priority[0x4]; 7471 u8 cong_protocol[0x4]; 7472 7473 u8 reserved_at_60[0x20]; 7474 }; 7475 7476 struct mlx5_ifc_query_cong_statistics_out_bits { 7477 u8 status[0x8]; 7478 u8 reserved_at_8[0x18]; 7479 7480 u8 syndrome[0x20]; 7481 7482 u8 reserved_at_40[0x40]; 7483 7484 u8 rp_cur_flows[0x20]; 7485 7486 u8 sum_flows[0x20]; 7487 7488 u8 rp_cnp_ignored_high[0x20]; 7489 7490 u8 rp_cnp_ignored_low[0x20]; 7491 7492 u8 rp_cnp_handled_high[0x20]; 7493 7494 u8 rp_cnp_handled_low[0x20]; 7495 7496 u8 reserved_at_140[0x100]; 7497 7498 u8 time_stamp_high[0x20]; 7499 7500 u8 time_stamp_low[0x20]; 7501 7502 u8 accumulators_period[0x20]; 7503 7504 u8 np_ecn_marked_roce_packets_high[0x20]; 7505 7506 u8 np_ecn_marked_roce_packets_low[0x20]; 7507 7508 u8 np_cnp_sent_high[0x20]; 7509 7510 u8 np_cnp_sent_low[0x20]; 7511 7512 u8 reserved_at_320[0x560]; 7513 }; 7514 7515 struct mlx5_ifc_query_cong_statistics_in_bits { 7516 u8 opcode[0x10]; 7517 u8 reserved_at_10[0x10]; 7518 7519 u8 reserved_at_20[0x10]; 7520 u8 op_mod[0x10]; 7521 7522 u8 clear[0x1]; 7523 u8 reserved_at_41[0x1f]; 7524 7525 u8 reserved_at_60[0x20]; 7526 }; 7527 7528 struct mlx5_ifc_query_cong_params_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x40]; 7535 7536 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7537 }; 7538 7539 struct mlx5_ifc_query_cong_params_in_bits { 7540 u8 opcode[0x10]; 7541 u8 reserved_at_10[0x10]; 7542 7543 u8 reserved_at_20[0x10]; 7544 u8 op_mod[0x10]; 7545 7546 u8 reserved_at_40[0x1c]; 7547 u8 cong_protocol[0x4]; 7548 7549 u8 reserved_at_60[0x20]; 7550 }; 7551 7552 struct mlx5_ifc_query_adapter_out_bits { 7553 u8 status[0x8]; 7554 u8 reserved_at_8[0x18]; 7555 7556 u8 syndrome[0x20]; 7557 7558 u8 reserved_at_40[0x40]; 7559 7560 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7561 }; 7562 7563 struct mlx5_ifc_query_adapter_in_bits { 7564 u8 opcode[0x10]; 7565 u8 reserved_at_10[0x10]; 7566 7567 u8 reserved_at_20[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_at_40[0x40]; 7571 }; 7572 7573 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7574 u8 host_number[0x8]; 7575 u8 host_pci_device_function[0x8]; 7576 u8 host_pci_bus[0x8]; 7577 u8 reserved_at_18[0x3]; 7578 u8 pci_bus_assigned[0x1]; 7579 u8 function_type[0x4]; 7580 7581 u8 parent_pci_device_function[0x8]; 7582 u8 parent_pci_bus[0x8]; 7583 u8 vhca_id[0x10]; 7584 7585 u8 reserved_at_40[0x10]; 7586 u8 function_id[0x10]; 7587 7588 u8 reserved_at_60[0x20]; 7589 }; 7590 7591 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7592 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7593 7594 u8 reserved_at_80[0x18]; 7595 u8 manage_profile[0x8]; 7596 7597 u8 reserved_at_a0[0x60]; 7598 }; 7599 7600 struct mlx5_ifc_query_delegated_vhca_out_bits { 7601 u8 status[0x8]; 7602 u8 reserved_at_8[0x18]; 7603 7604 u8 syndrome[0x20]; 7605 7606 u8 reserved_at_40[0x20]; 7607 7608 u8 reserved_at_60[0x10]; 7609 u8 functions_count[0x10]; 7610 7611 u8 reserved_at_80[0x80]; 7612 7613 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7614 delegated_function_vhca_rid_info[]; 7615 }; 7616 7617 struct mlx5_ifc_query_delegated_vhca_in_bits { 7618 u8 opcode[0x10]; 7619 u8 uid[0x10]; 7620 7621 u8 reserved_at_20[0x10]; 7622 u8 op_mod[0x10]; 7623 7624 u8 reserved_at_40[0x40]; 7625 }; 7626 7627 struct mlx5_ifc_create_esw_vport_out_bits { 7628 u8 status[0x8]; 7629 u8 reserved_at_8[0x18]; 7630 7631 u8 syndrome[0x20]; 7632 7633 u8 reserved_at_40[0x20]; 7634 7635 u8 reserved_at_60[0x10]; 7636 u8 vport_num[0x10]; 7637 }; 7638 7639 struct mlx5_ifc_create_esw_vport_in_bits { 7640 u8 opcode[0x10]; 7641 u8 reserved_at_10[0x10]; 7642 7643 u8 reserved_at_20[0x10]; 7644 u8 op_mod[0x10]; 7645 7646 u8 reserved_at_40[0x10]; 7647 u8 managed_vhca_id[0x10]; 7648 7649 u8 reserved_at_60[0x20]; 7650 }; 7651 7652 struct mlx5_ifc_qp_2rst_out_bits { 7653 u8 status[0x8]; 7654 u8 reserved_at_8[0x18]; 7655 7656 u8 syndrome[0x20]; 7657 7658 u8 reserved_at_40[0x40]; 7659 }; 7660 7661 struct mlx5_ifc_qp_2rst_in_bits { 7662 u8 opcode[0x10]; 7663 u8 uid[0x10]; 7664 7665 u8 reserved_at_20[0x10]; 7666 u8 op_mod[0x10]; 7667 7668 u8 reserved_at_40[0x8]; 7669 u8 qpn[0x18]; 7670 7671 u8 reserved_at_60[0x20]; 7672 }; 7673 7674 struct mlx5_ifc_qp_2err_out_bits { 7675 u8 status[0x8]; 7676 u8 reserved_at_8[0x18]; 7677 7678 u8 syndrome[0x20]; 7679 7680 u8 reserved_at_40[0x40]; 7681 }; 7682 7683 struct mlx5_ifc_qp_2err_in_bits { 7684 u8 opcode[0x10]; 7685 u8 uid[0x10]; 7686 7687 u8 reserved_at_20[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 reserved_at_40[0x8]; 7691 u8 qpn[0x18]; 7692 7693 u8 reserved_at_60[0x20]; 7694 }; 7695 7696 struct mlx5_ifc_trans_page_fault_info_bits { 7697 u8 error[0x1]; 7698 u8 reserved_at_1[0x4]; 7699 u8 page_fault_type[0x3]; 7700 u8 wq_number[0x18]; 7701 7702 u8 reserved_at_20[0x8]; 7703 u8 fault_token[0x18]; 7704 }; 7705 7706 struct mlx5_ifc_mem_page_fault_info_bits { 7707 u8 error[0x1]; 7708 u8 reserved_at_1[0xf]; 7709 u8 fault_token_47_32[0x10]; 7710 7711 u8 fault_token_31_0[0x20]; 7712 }; 7713 7714 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7715 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7716 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7717 u8 reserved_at_0[0x40]; 7718 }; 7719 7720 struct mlx5_ifc_page_fault_resume_out_bits { 7721 u8 status[0x8]; 7722 u8 reserved_at_8[0x18]; 7723 7724 u8 syndrome[0x20]; 7725 7726 u8 reserved_at_40[0x40]; 7727 }; 7728 7729 struct mlx5_ifc_page_fault_resume_in_bits { 7730 u8 opcode[0x10]; 7731 u8 reserved_at_10[0x10]; 7732 7733 u8 reserved_at_20[0x10]; 7734 u8 op_mod[0x10]; 7735 7736 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7737 page_fault_info; 7738 }; 7739 7740 struct mlx5_ifc_nop_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x40]; 7747 }; 7748 7749 struct mlx5_ifc_nop_in_bits { 7750 u8 opcode[0x10]; 7751 u8 reserved_at_10[0x10]; 7752 7753 u8 reserved_at_20[0x10]; 7754 u8 op_mod[0x10]; 7755 7756 u8 reserved_at_40[0x40]; 7757 }; 7758 7759 struct mlx5_ifc_modify_vport_state_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_at_8[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_at_40[0x40]; 7766 }; 7767 7768 struct mlx5_ifc_modify_vport_state_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_at_10[0x10]; 7771 7772 u8 reserved_at_20[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 other_vport[0x1]; 7776 u8 reserved_at_41[0xf]; 7777 u8 vport_number[0x10]; 7778 7779 u8 reserved_at_60[0x10]; 7780 u8 ingress_connect[0x1]; 7781 u8 egress_connect[0x1]; 7782 u8 ingress_connect_valid[0x1]; 7783 u8 egress_connect_valid[0x1]; 7784 u8 reserved_at_74[0x4]; 7785 u8 admin_state[0x4]; 7786 u8 reserved_at_7c[0x4]; 7787 }; 7788 7789 struct mlx5_ifc_modify_tis_out_bits { 7790 u8 status[0x8]; 7791 u8 reserved_at_8[0x18]; 7792 7793 u8 syndrome[0x20]; 7794 7795 u8 reserved_at_40[0x40]; 7796 }; 7797 7798 struct mlx5_ifc_modify_tis_bitmask_bits { 7799 u8 reserved_at_0[0x20]; 7800 7801 u8 reserved_at_20[0x1d]; 7802 u8 lag_tx_port_affinity[0x1]; 7803 u8 strict_lag_tx_port_affinity[0x1]; 7804 u8 prio[0x1]; 7805 }; 7806 7807 struct mlx5_ifc_modify_tis_in_bits { 7808 u8 opcode[0x10]; 7809 u8 uid[0x10]; 7810 7811 u8 reserved_at_20[0x10]; 7812 u8 op_mod[0x10]; 7813 7814 u8 reserved_at_40[0x8]; 7815 u8 tisn[0x18]; 7816 7817 u8 reserved_at_60[0x20]; 7818 7819 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7820 7821 u8 reserved_at_c0[0x40]; 7822 7823 struct mlx5_ifc_tisc_bits ctx; 7824 }; 7825 7826 struct mlx5_ifc_modify_tir_bitmask_bits { 7827 u8 reserved_at_0[0x20]; 7828 7829 u8 reserved_at_20[0x1b]; 7830 u8 self_lb_en[0x1]; 7831 u8 reserved_at_3c[0x1]; 7832 u8 hash[0x1]; 7833 u8 reserved_at_3e[0x1]; 7834 u8 packet_merge[0x1]; 7835 }; 7836 7837 struct mlx5_ifc_modify_tir_out_bits { 7838 u8 status[0x8]; 7839 u8 reserved_at_8[0x18]; 7840 7841 u8 syndrome[0x20]; 7842 7843 u8 reserved_at_40[0x40]; 7844 }; 7845 7846 struct mlx5_ifc_modify_tir_in_bits { 7847 u8 opcode[0x10]; 7848 u8 uid[0x10]; 7849 7850 u8 reserved_at_20[0x10]; 7851 u8 op_mod[0x10]; 7852 7853 u8 reserved_at_40[0x8]; 7854 u8 tirn[0x18]; 7855 7856 u8 reserved_at_60[0x20]; 7857 7858 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7859 7860 u8 reserved_at_c0[0x40]; 7861 7862 struct mlx5_ifc_tirc_bits ctx; 7863 }; 7864 7865 struct mlx5_ifc_modify_sq_out_bits { 7866 u8 status[0x8]; 7867 u8 reserved_at_8[0x18]; 7868 7869 u8 syndrome[0x20]; 7870 7871 u8 reserved_at_40[0x40]; 7872 }; 7873 7874 struct mlx5_ifc_modify_sq_in_bits { 7875 u8 opcode[0x10]; 7876 u8 uid[0x10]; 7877 7878 u8 reserved_at_20[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 sq_state[0x4]; 7882 u8 reserved_at_44[0x4]; 7883 u8 sqn[0x18]; 7884 7885 u8 reserved_at_60[0x20]; 7886 7887 u8 modify_bitmask[0x40]; 7888 7889 u8 reserved_at_c0[0x40]; 7890 7891 struct mlx5_ifc_sqc_bits ctx; 7892 }; 7893 7894 struct mlx5_ifc_modify_scheduling_element_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x1c0]; 7901 }; 7902 7903 enum { 7904 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7905 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7906 }; 7907 7908 struct mlx5_ifc_modify_scheduling_element_in_bits { 7909 u8 opcode[0x10]; 7910 u8 reserved_at_10[0x10]; 7911 7912 u8 reserved_at_20[0x10]; 7913 u8 op_mod[0x10]; 7914 7915 u8 scheduling_hierarchy[0x8]; 7916 u8 reserved_at_48[0x18]; 7917 7918 u8 scheduling_element_id[0x20]; 7919 7920 u8 reserved_at_80[0x20]; 7921 7922 u8 modify_bitmask[0x20]; 7923 7924 u8 reserved_at_c0[0x40]; 7925 7926 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7927 7928 u8 reserved_at_300[0x100]; 7929 }; 7930 7931 struct mlx5_ifc_modify_rqt_out_bits { 7932 u8 status[0x8]; 7933 u8 reserved_at_8[0x18]; 7934 7935 u8 syndrome[0x20]; 7936 7937 u8 reserved_at_40[0x40]; 7938 }; 7939 7940 struct mlx5_ifc_rqt_bitmask_bits { 7941 u8 reserved_at_0[0x20]; 7942 7943 u8 reserved_at_20[0x1f]; 7944 u8 rqn_list[0x1]; 7945 }; 7946 7947 struct mlx5_ifc_modify_rqt_in_bits { 7948 u8 opcode[0x10]; 7949 u8 uid[0x10]; 7950 7951 u8 reserved_at_20[0x10]; 7952 u8 op_mod[0x10]; 7953 7954 u8 reserved_at_40[0x8]; 7955 u8 rqtn[0x18]; 7956 7957 u8 reserved_at_60[0x20]; 7958 7959 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7960 7961 u8 reserved_at_c0[0x40]; 7962 7963 struct mlx5_ifc_rqtc_bits ctx; 7964 }; 7965 7966 struct mlx5_ifc_modify_rq_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_at_8[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_at_40[0x40]; 7973 }; 7974 7975 enum { 7976 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7977 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7978 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7979 }; 7980 7981 struct mlx5_ifc_modify_rq_in_bits { 7982 u8 opcode[0x10]; 7983 u8 uid[0x10]; 7984 7985 u8 reserved_at_20[0x10]; 7986 u8 op_mod[0x10]; 7987 7988 u8 rq_state[0x4]; 7989 u8 reserved_at_44[0x4]; 7990 u8 rqn[0x18]; 7991 7992 u8 reserved_at_60[0x20]; 7993 7994 u8 modify_bitmask[0x40]; 7995 7996 u8 reserved_at_c0[0x40]; 7997 7998 struct mlx5_ifc_rqc_bits ctx; 7999 }; 8000 8001 struct mlx5_ifc_modify_rmp_out_bits { 8002 u8 status[0x8]; 8003 u8 reserved_at_8[0x18]; 8004 8005 u8 syndrome[0x20]; 8006 8007 u8 reserved_at_40[0x40]; 8008 }; 8009 8010 struct mlx5_ifc_rmp_bitmask_bits { 8011 u8 reserved_at_0[0x20]; 8012 8013 u8 reserved_at_20[0x1f]; 8014 u8 lwm[0x1]; 8015 }; 8016 8017 struct mlx5_ifc_modify_rmp_in_bits { 8018 u8 opcode[0x10]; 8019 u8 uid[0x10]; 8020 8021 u8 reserved_at_20[0x10]; 8022 u8 op_mod[0x10]; 8023 8024 u8 rmp_state[0x4]; 8025 u8 reserved_at_44[0x4]; 8026 u8 rmpn[0x18]; 8027 8028 u8 reserved_at_60[0x20]; 8029 8030 struct mlx5_ifc_rmp_bitmask_bits bitmask; 8031 8032 u8 reserved_at_c0[0x40]; 8033 8034 struct mlx5_ifc_rmpc_bits ctx; 8035 }; 8036 8037 struct mlx5_ifc_modify_nic_vport_context_out_bits { 8038 u8 status[0x8]; 8039 u8 reserved_at_8[0x18]; 8040 8041 u8 syndrome[0x20]; 8042 8043 u8 reserved_at_40[0x40]; 8044 }; 8045 8046 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8047 u8 reserved_at_0[0x12]; 8048 u8 affiliation[0x1]; 8049 u8 reserved_at_13[0x1]; 8050 u8 disable_uc_local_lb[0x1]; 8051 u8 disable_mc_local_lb[0x1]; 8052 u8 node_guid[0x1]; 8053 u8 port_guid[0x1]; 8054 u8 min_inline[0x1]; 8055 u8 mtu[0x1]; 8056 u8 change_event[0x1]; 8057 u8 promisc[0x1]; 8058 u8 permanent_address[0x1]; 8059 u8 addresses_list[0x1]; 8060 u8 roce_en[0x1]; 8061 u8 reserved_at_1f[0x1]; 8062 }; 8063 8064 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8065 u8 opcode[0x10]; 8066 u8 reserved_at_10[0x10]; 8067 8068 u8 reserved_at_20[0x10]; 8069 u8 op_mod[0x10]; 8070 8071 u8 other_vport[0x1]; 8072 u8 reserved_at_41[0xf]; 8073 u8 vport_number[0x10]; 8074 8075 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8076 8077 u8 reserved_at_80[0x780]; 8078 8079 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8080 }; 8081 8082 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8083 u8 status[0x8]; 8084 u8 reserved_at_8[0x18]; 8085 8086 u8 syndrome[0x20]; 8087 8088 u8 reserved_at_40[0x40]; 8089 }; 8090 8091 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8092 u8 opcode[0x10]; 8093 u8 reserved_at_10[0x10]; 8094 8095 u8 reserved_at_20[0x10]; 8096 u8 op_mod[0x10]; 8097 8098 u8 other_vport[0x1]; 8099 u8 reserved_at_41[0xb]; 8100 u8 port_num[0x4]; 8101 u8 vport_number[0x10]; 8102 8103 u8 reserved_at_60[0x20]; 8104 8105 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8106 }; 8107 8108 struct mlx5_ifc_modify_cq_out_bits { 8109 u8 status[0x8]; 8110 u8 reserved_at_8[0x18]; 8111 8112 u8 syndrome[0x20]; 8113 8114 u8 reserved_at_40[0x40]; 8115 }; 8116 8117 enum { 8118 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8119 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8120 }; 8121 8122 struct mlx5_ifc_modify_cq_in_bits { 8123 u8 opcode[0x10]; 8124 u8 uid[0x10]; 8125 8126 u8 reserved_at_20[0x10]; 8127 u8 op_mod[0x10]; 8128 8129 u8 reserved_at_40[0x8]; 8130 u8 cqn[0x18]; 8131 8132 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8133 8134 struct mlx5_ifc_cqc_bits cq_context; 8135 8136 u8 reserved_at_280[0x60]; 8137 8138 u8 cq_umem_valid[0x1]; 8139 u8 reserved_at_2e1[0x1f]; 8140 8141 u8 reserved_at_300[0x580]; 8142 8143 u8 pas[][0x40]; 8144 }; 8145 8146 struct mlx5_ifc_modify_cong_status_out_bits { 8147 u8 status[0x8]; 8148 u8 reserved_at_8[0x18]; 8149 8150 u8 syndrome[0x20]; 8151 8152 u8 reserved_at_40[0x40]; 8153 }; 8154 8155 struct mlx5_ifc_modify_cong_status_in_bits { 8156 u8 opcode[0x10]; 8157 u8 reserved_at_10[0x10]; 8158 8159 u8 reserved_at_20[0x10]; 8160 u8 op_mod[0x10]; 8161 8162 u8 reserved_at_40[0x18]; 8163 u8 priority[0x4]; 8164 u8 cong_protocol[0x4]; 8165 8166 u8 enable[0x1]; 8167 u8 tag_enable[0x1]; 8168 u8 reserved_at_62[0x1e]; 8169 }; 8170 8171 struct mlx5_ifc_modify_cong_params_out_bits { 8172 u8 status[0x8]; 8173 u8 reserved_at_8[0x18]; 8174 8175 u8 syndrome[0x20]; 8176 8177 u8 reserved_at_40[0x40]; 8178 }; 8179 8180 struct mlx5_ifc_modify_cong_params_in_bits { 8181 u8 opcode[0x10]; 8182 u8 reserved_at_10[0x10]; 8183 8184 u8 reserved_at_20[0x10]; 8185 u8 op_mod[0x10]; 8186 8187 u8 reserved_at_40[0x1c]; 8188 u8 cong_protocol[0x4]; 8189 8190 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8191 8192 u8 reserved_at_80[0x80]; 8193 8194 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8195 }; 8196 8197 struct mlx5_ifc_manage_pages_out_bits { 8198 u8 status[0x8]; 8199 u8 reserved_at_8[0x18]; 8200 8201 u8 syndrome[0x20]; 8202 8203 u8 output_num_entries[0x20]; 8204 8205 u8 reserved_at_60[0x20]; 8206 8207 u8 pas[][0x40]; 8208 }; 8209 8210 enum { 8211 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8212 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8213 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8214 }; 8215 8216 struct mlx5_ifc_manage_pages_in_bits { 8217 u8 opcode[0x10]; 8218 u8 reserved_at_10[0x10]; 8219 8220 u8 reserved_at_20[0x10]; 8221 u8 op_mod[0x10]; 8222 8223 u8 embedded_cpu_function[0x1]; 8224 u8 reserved_at_41[0xf]; 8225 u8 function_id[0x10]; 8226 8227 u8 input_num_entries[0x20]; 8228 8229 u8 pas[][0x40]; 8230 }; 8231 8232 struct mlx5_ifc_mad_ifc_out_bits { 8233 u8 status[0x8]; 8234 u8 reserved_at_8[0x18]; 8235 8236 u8 syndrome[0x20]; 8237 8238 u8 reserved_at_40[0x40]; 8239 8240 u8 response_mad_packet[256][0x8]; 8241 }; 8242 8243 struct mlx5_ifc_mad_ifc_in_bits { 8244 u8 opcode[0x10]; 8245 u8 reserved_at_10[0x10]; 8246 8247 u8 reserved_at_20[0x10]; 8248 u8 op_mod[0x10]; 8249 8250 u8 remote_lid[0x10]; 8251 u8 plane_index[0x8]; 8252 u8 port[0x8]; 8253 8254 u8 reserved_at_60[0x20]; 8255 8256 u8 mad[256][0x8]; 8257 }; 8258 8259 struct mlx5_ifc_init_hca_out_bits { 8260 u8 status[0x8]; 8261 u8 reserved_at_8[0x18]; 8262 8263 u8 syndrome[0x20]; 8264 8265 u8 reserved_at_40[0x40]; 8266 }; 8267 8268 struct mlx5_ifc_init_hca_in_bits { 8269 u8 opcode[0x10]; 8270 u8 reserved_at_10[0x10]; 8271 8272 u8 reserved_at_20[0x10]; 8273 u8 op_mod[0x10]; 8274 8275 u8 reserved_at_40[0x20]; 8276 8277 u8 reserved_at_60[0x2]; 8278 u8 sw_vhca_id[0xe]; 8279 u8 reserved_at_70[0x10]; 8280 8281 u8 sw_owner_id[4][0x20]; 8282 }; 8283 8284 struct mlx5_ifc_init2rtr_qp_out_bits { 8285 u8 status[0x8]; 8286 u8 reserved_at_8[0x18]; 8287 8288 u8 syndrome[0x20]; 8289 8290 u8 reserved_at_40[0x20]; 8291 u8 ece[0x20]; 8292 }; 8293 8294 struct mlx5_ifc_init2rtr_qp_in_bits { 8295 u8 opcode[0x10]; 8296 u8 uid[0x10]; 8297 8298 u8 reserved_at_20[0x10]; 8299 u8 op_mod[0x10]; 8300 8301 u8 reserved_at_40[0x8]; 8302 u8 qpn[0x18]; 8303 8304 u8 reserved_at_60[0x20]; 8305 8306 u8 opt_param_mask[0x20]; 8307 8308 u8 ece[0x20]; 8309 8310 struct mlx5_ifc_qpc_bits qpc; 8311 8312 u8 reserved_at_800[0x80]; 8313 }; 8314 8315 struct mlx5_ifc_init2init_qp_out_bits { 8316 u8 status[0x8]; 8317 u8 reserved_at_8[0x18]; 8318 8319 u8 syndrome[0x20]; 8320 8321 u8 reserved_at_40[0x20]; 8322 u8 ece[0x20]; 8323 }; 8324 8325 struct mlx5_ifc_init2init_qp_in_bits { 8326 u8 opcode[0x10]; 8327 u8 uid[0x10]; 8328 8329 u8 reserved_at_20[0x10]; 8330 u8 op_mod[0x10]; 8331 8332 u8 reserved_at_40[0x8]; 8333 u8 qpn[0x18]; 8334 8335 u8 reserved_at_60[0x20]; 8336 8337 u8 opt_param_mask[0x20]; 8338 8339 u8 ece[0x20]; 8340 8341 struct mlx5_ifc_qpc_bits qpc; 8342 8343 u8 reserved_at_800[0x80]; 8344 }; 8345 8346 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8347 u8 status[0x8]; 8348 u8 reserved_at_8[0x18]; 8349 8350 u8 syndrome[0x20]; 8351 8352 u8 reserved_at_40[0x40]; 8353 8354 u8 packet_headers_log[128][0x8]; 8355 8356 u8 packet_syndrome[64][0x8]; 8357 }; 8358 8359 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8360 u8 opcode[0x10]; 8361 u8 reserved_at_10[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 reserved_at_40[0x40]; 8367 }; 8368 8369 struct mlx5_ifc_gen_eqe_in_bits { 8370 u8 opcode[0x10]; 8371 u8 reserved_at_10[0x10]; 8372 8373 u8 reserved_at_20[0x10]; 8374 u8 op_mod[0x10]; 8375 8376 u8 reserved_at_40[0x18]; 8377 u8 eq_number[0x8]; 8378 8379 u8 reserved_at_60[0x20]; 8380 8381 u8 eqe[64][0x8]; 8382 }; 8383 8384 struct mlx5_ifc_gen_eq_out_bits { 8385 u8 status[0x8]; 8386 u8 reserved_at_8[0x18]; 8387 8388 u8 syndrome[0x20]; 8389 8390 u8 reserved_at_40[0x40]; 8391 }; 8392 8393 struct mlx5_ifc_enable_hca_out_bits { 8394 u8 status[0x8]; 8395 u8 reserved_at_8[0x18]; 8396 8397 u8 syndrome[0x20]; 8398 8399 u8 reserved_at_40[0x20]; 8400 }; 8401 8402 struct mlx5_ifc_enable_hca_in_bits { 8403 u8 opcode[0x10]; 8404 u8 reserved_at_10[0x10]; 8405 8406 u8 reserved_at_20[0x10]; 8407 u8 op_mod[0x10]; 8408 8409 u8 embedded_cpu_function[0x1]; 8410 u8 reserved_at_41[0xf]; 8411 u8 function_id[0x10]; 8412 8413 u8 reserved_at_60[0x20]; 8414 }; 8415 8416 struct mlx5_ifc_drain_dct_out_bits { 8417 u8 status[0x8]; 8418 u8 reserved_at_8[0x18]; 8419 8420 u8 syndrome[0x20]; 8421 8422 u8 reserved_at_40[0x40]; 8423 }; 8424 8425 struct mlx5_ifc_drain_dct_in_bits { 8426 u8 opcode[0x10]; 8427 u8 uid[0x10]; 8428 8429 u8 reserved_at_20[0x10]; 8430 u8 op_mod[0x10]; 8431 8432 u8 reserved_at_40[0x8]; 8433 u8 dctn[0x18]; 8434 8435 u8 reserved_at_60[0x20]; 8436 }; 8437 8438 struct mlx5_ifc_disable_hca_out_bits { 8439 u8 status[0x8]; 8440 u8 reserved_at_8[0x18]; 8441 8442 u8 syndrome[0x20]; 8443 8444 u8 reserved_at_40[0x20]; 8445 }; 8446 8447 struct mlx5_ifc_disable_hca_in_bits { 8448 u8 opcode[0x10]; 8449 u8 reserved_at_10[0x10]; 8450 8451 u8 reserved_at_20[0x10]; 8452 u8 op_mod[0x10]; 8453 8454 u8 embedded_cpu_function[0x1]; 8455 u8 reserved_at_41[0xf]; 8456 u8 function_id[0x10]; 8457 8458 u8 reserved_at_60[0x20]; 8459 }; 8460 8461 struct mlx5_ifc_detach_from_mcg_out_bits { 8462 u8 status[0x8]; 8463 u8 reserved_at_8[0x18]; 8464 8465 u8 syndrome[0x20]; 8466 8467 u8 reserved_at_40[0x40]; 8468 }; 8469 8470 struct mlx5_ifc_detach_from_mcg_in_bits { 8471 u8 opcode[0x10]; 8472 u8 uid[0x10]; 8473 8474 u8 reserved_at_20[0x10]; 8475 u8 op_mod[0x10]; 8476 8477 u8 reserved_at_40[0x8]; 8478 u8 qpn[0x18]; 8479 8480 u8 reserved_at_60[0x20]; 8481 8482 u8 multicast_gid[16][0x8]; 8483 }; 8484 8485 struct mlx5_ifc_destroy_xrq_out_bits { 8486 u8 status[0x8]; 8487 u8 reserved_at_8[0x18]; 8488 8489 u8 syndrome[0x20]; 8490 8491 u8 reserved_at_40[0x40]; 8492 }; 8493 8494 struct mlx5_ifc_destroy_xrq_in_bits { 8495 u8 opcode[0x10]; 8496 u8 uid[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x8]; 8502 u8 xrqn[0x18]; 8503 8504 u8 reserved_at_60[0x20]; 8505 }; 8506 8507 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8508 u8 status[0x8]; 8509 u8 reserved_at_8[0x18]; 8510 8511 u8 syndrome[0x20]; 8512 8513 u8 reserved_at_40[0x40]; 8514 }; 8515 8516 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8517 u8 opcode[0x10]; 8518 u8 uid[0x10]; 8519 8520 u8 reserved_at_20[0x10]; 8521 u8 op_mod[0x10]; 8522 8523 u8 reserved_at_40[0x8]; 8524 u8 xrc_srqn[0x18]; 8525 8526 u8 reserved_at_60[0x20]; 8527 }; 8528 8529 struct mlx5_ifc_destroy_tis_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x40]; 8536 }; 8537 8538 struct mlx5_ifc_destroy_tis_in_bits { 8539 u8 opcode[0x10]; 8540 u8 uid[0x10]; 8541 8542 u8 reserved_at_20[0x10]; 8543 u8 op_mod[0x10]; 8544 8545 u8 reserved_at_40[0x8]; 8546 u8 tisn[0x18]; 8547 8548 u8 reserved_at_60[0x20]; 8549 }; 8550 8551 struct mlx5_ifc_destroy_tir_out_bits { 8552 u8 status[0x8]; 8553 u8 reserved_at_8[0x18]; 8554 8555 u8 syndrome[0x20]; 8556 8557 u8 reserved_at_40[0x40]; 8558 }; 8559 8560 struct mlx5_ifc_destroy_tir_in_bits { 8561 u8 opcode[0x10]; 8562 u8 uid[0x10]; 8563 8564 u8 reserved_at_20[0x10]; 8565 u8 op_mod[0x10]; 8566 8567 u8 reserved_at_40[0x8]; 8568 u8 tirn[0x18]; 8569 8570 u8 reserved_at_60[0x20]; 8571 }; 8572 8573 struct mlx5_ifc_destroy_srq_out_bits { 8574 u8 status[0x8]; 8575 u8 reserved_at_8[0x18]; 8576 8577 u8 syndrome[0x20]; 8578 8579 u8 reserved_at_40[0x40]; 8580 }; 8581 8582 struct mlx5_ifc_destroy_srq_in_bits { 8583 u8 opcode[0x10]; 8584 u8 uid[0x10]; 8585 8586 u8 reserved_at_20[0x10]; 8587 u8 op_mod[0x10]; 8588 8589 u8 reserved_at_40[0x8]; 8590 u8 srqn[0x18]; 8591 8592 u8 reserved_at_60[0x20]; 8593 }; 8594 8595 struct mlx5_ifc_destroy_sq_out_bits { 8596 u8 status[0x8]; 8597 u8 reserved_at_8[0x18]; 8598 8599 u8 syndrome[0x20]; 8600 8601 u8 reserved_at_40[0x40]; 8602 }; 8603 8604 struct mlx5_ifc_destroy_sq_in_bits { 8605 u8 opcode[0x10]; 8606 u8 uid[0x10]; 8607 8608 u8 reserved_at_20[0x10]; 8609 u8 op_mod[0x10]; 8610 8611 u8 reserved_at_40[0x8]; 8612 u8 sqn[0x18]; 8613 8614 u8 reserved_at_60[0x20]; 8615 }; 8616 8617 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8618 u8 status[0x8]; 8619 u8 reserved_at_8[0x18]; 8620 8621 u8 syndrome[0x20]; 8622 8623 u8 reserved_at_40[0x1c0]; 8624 }; 8625 8626 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8627 u8 opcode[0x10]; 8628 u8 reserved_at_10[0x10]; 8629 8630 u8 reserved_at_20[0x10]; 8631 u8 op_mod[0x10]; 8632 8633 u8 scheduling_hierarchy[0x8]; 8634 u8 reserved_at_48[0x18]; 8635 8636 u8 scheduling_element_id[0x20]; 8637 8638 u8 reserved_at_80[0x180]; 8639 }; 8640 8641 struct mlx5_ifc_destroy_rqt_out_bits { 8642 u8 status[0x8]; 8643 u8 reserved_at_8[0x18]; 8644 8645 u8 syndrome[0x20]; 8646 8647 u8 reserved_at_40[0x40]; 8648 }; 8649 8650 struct mlx5_ifc_destroy_rqt_in_bits { 8651 u8 opcode[0x10]; 8652 u8 uid[0x10]; 8653 8654 u8 reserved_at_20[0x10]; 8655 u8 op_mod[0x10]; 8656 8657 u8 reserved_at_40[0x8]; 8658 u8 rqtn[0x18]; 8659 8660 u8 reserved_at_60[0x20]; 8661 }; 8662 8663 struct mlx5_ifc_destroy_rq_out_bits { 8664 u8 status[0x8]; 8665 u8 reserved_at_8[0x18]; 8666 8667 u8 syndrome[0x20]; 8668 8669 u8 reserved_at_40[0x40]; 8670 }; 8671 8672 struct mlx5_ifc_destroy_rq_in_bits { 8673 u8 opcode[0x10]; 8674 u8 uid[0x10]; 8675 8676 u8 reserved_at_20[0x10]; 8677 u8 op_mod[0x10]; 8678 8679 u8 reserved_at_40[0x8]; 8680 u8 rqn[0x18]; 8681 8682 u8 reserved_at_60[0x20]; 8683 }; 8684 8685 struct mlx5_ifc_set_delay_drop_params_in_bits { 8686 u8 opcode[0x10]; 8687 u8 reserved_at_10[0x10]; 8688 8689 u8 reserved_at_20[0x10]; 8690 u8 op_mod[0x10]; 8691 8692 u8 reserved_at_40[0x20]; 8693 8694 u8 reserved_at_60[0x10]; 8695 u8 delay_drop_timeout[0x10]; 8696 }; 8697 8698 struct mlx5_ifc_set_delay_drop_params_out_bits { 8699 u8 status[0x8]; 8700 u8 reserved_at_8[0x18]; 8701 8702 u8 syndrome[0x20]; 8703 8704 u8 reserved_at_40[0x40]; 8705 }; 8706 8707 struct mlx5_ifc_destroy_rmp_out_bits { 8708 u8 status[0x8]; 8709 u8 reserved_at_8[0x18]; 8710 8711 u8 syndrome[0x20]; 8712 8713 u8 reserved_at_40[0x40]; 8714 }; 8715 8716 struct mlx5_ifc_destroy_rmp_in_bits { 8717 u8 opcode[0x10]; 8718 u8 uid[0x10]; 8719 8720 u8 reserved_at_20[0x10]; 8721 u8 op_mod[0x10]; 8722 8723 u8 reserved_at_40[0x8]; 8724 u8 rmpn[0x18]; 8725 8726 u8 reserved_at_60[0x20]; 8727 }; 8728 8729 struct mlx5_ifc_destroy_qp_out_bits { 8730 u8 status[0x8]; 8731 u8 reserved_at_8[0x18]; 8732 8733 u8 syndrome[0x20]; 8734 8735 u8 reserved_at_40[0x40]; 8736 }; 8737 8738 struct mlx5_ifc_destroy_qp_in_bits { 8739 u8 opcode[0x10]; 8740 u8 uid[0x10]; 8741 8742 u8 reserved_at_20[0x10]; 8743 u8 op_mod[0x10]; 8744 8745 u8 reserved_at_40[0x8]; 8746 u8 qpn[0x18]; 8747 8748 u8 reserved_at_60[0x20]; 8749 }; 8750 8751 struct mlx5_ifc_destroy_psv_out_bits { 8752 u8 status[0x8]; 8753 u8 reserved_at_8[0x18]; 8754 8755 u8 syndrome[0x20]; 8756 8757 u8 reserved_at_40[0x40]; 8758 }; 8759 8760 struct mlx5_ifc_destroy_psv_in_bits { 8761 u8 opcode[0x10]; 8762 u8 reserved_at_10[0x10]; 8763 8764 u8 reserved_at_20[0x10]; 8765 u8 op_mod[0x10]; 8766 8767 u8 reserved_at_40[0x8]; 8768 u8 psvn[0x18]; 8769 8770 u8 reserved_at_60[0x20]; 8771 }; 8772 8773 struct mlx5_ifc_destroy_mkey_out_bits { 8774 u8 status[0x8]; 8775 u8 reserved_at_8[0x18]; 8776 8777 u8 syndrome[0x20]; 8778 8779 u8 reserved_at_40[0x40]; 8780 }; 8781 8782 struct mlx5_ifc_destroy_mkey_in_bits { 8783 u8 opcode[0x10]; 8784 u8 uid[0x10]; 8785 8786 u8 reserved_at_20[0x10]; 8787 u8 op_mod[0x10]; 8788 8789 u8 reserved_at_40[0x8]; 8790 u8 mkey_index[0x18]; 8791 8792 u8 reserved_at_60[0x20]; 8793 }; 8794 8795 struct mlx5_ifc_destroy_flow_table_out_bits { 8796 u8 status[0x8]; 8797 u8 reserved_at_8[0x18]; 8798 8799 u8 syndrome[0x20]; 8800 8801 u8 reserved_at_40[0x40]; 8802 }; 8803 8804 struct mlx5_ifc_destroy_flow_table_in_bits { 8805 u8 opcode[0x10]; 8806 u8 reserved_at_10[0x10]; 8807 8808 u8 reserved_at_20[0x10]; 8809 u8 op_mod[0x10]; 8810 8811 u8 other_vport[0x1]; 8812 u8 reserved_at_41[0xf]; 8813 u8 vport_number[0x10]; 8814 8815 u8 reserved_at_60[0x20]; 8816 8817 u8 table_type[0x8]; 8818 u8 reserved_at_88[0x18]; 8819 8820 u8 reserved_at_a0[0x8]; 8821 u8 table_id[0x18]; 8822 8823 u8 reserved_at_c0[0x140]; 8824 }; 8825 8826 struct mlx5_ifc_destroy_flow_group_out_bits { 8827 u8 status[0x8]; 8828 u8 reserved_at_8[0x18]; 8829 8830 u8 syndrome[0x20]; 8831 8832 u8 reserved_at_40[0x40]; 8833 }; 8834 8835 struct mlx5_ifc_destroy_flow_group_in_bits { 8836 u8 opcode[0x10]; 8837 u8 reserved_at_10[0x10]; 8838 8839 u8 reserved_at_20[0x10]; 8840 u8 op_mod[0x10]; 8841 8842 u8 other_vport[0x1]; 8843 u8 reserved_at_41[0xf]; 8844 u8 vport_number[0x10]; 8845 8846 u8 reserved_at_60[0x20]; 8847 8848 u8 table_type[0x8]; 8849 u8 reserved_at_88[0x18]; 8850 8851 u8 reserved_at_a0[0x8]; 8852 u8 table_id[0x18]; 8853 8854 u8 group_id[0x20]; 8855 8856 u8 reserved_at_e0[0x120]; 8857 }; 8858 8859 struct mlx5_ifc_destroy_eq_out_bits { 8860 u8 status[0x8]; 8861 u8 reserved_at_8[0x18]; 8862 8863 u8 syndrome[0x20]; 8864 8865 u8 reserved_at_40[0x40]; 8866 }; 8867 8868 struct mlx5_ifc_destroy_eq_in_bits { 8869 u8 opcode[0x10]; 8870 u8 reserved_at_10[0x10]; 8871 8872 u8 reserved_at_20[0x10]; 8873 u8 op_mod[0x10]; 8874 8875 u8 reserved_at_40[0x18]; 8876 u8 eq_number[0x8]; 8877 8878 u8 reserved_at_60[0x20]; 8879 }; 8880 8881 struct mlx5_ifc_destroy_dct_out_bits { 8882 u8 status[0x8]; 8883 u8 reserved_at_8[0x18]; 8884 8885 u8 syndrome[0x20]; 8886 8887 u8 reserved_at_40[0x40]; 8888 }; 8889 8890 struct mlx5_ifc_destroy_dct_in_bits { 8891 u8 opcode[0x10]; 8892 u8 uid[0x10]; 8893 8894 u8 reserved_at_20[0x10]; 8895 u8 op_mod[0x10]; 8896 8897 u8 reserved_at_40[0x8]; 8898 u8 dctn[0x18]; 8899 8900 u8 reserved_at_60[0x20]; 8901 }; 8902 8903 struct mlx5_ifc_destroy_cq_out_bits { 8904 u8 status[0x8]; 8905 u8 reserved_at_8[0x18]; 8906 8907 u8 syndrome[0x20]; 8908 8909 u8 reserved_at_40[0x40]; 8910 }; 8911 8912 struct mlx5_ifc_destroy_cq_in_bits { 8913 u8 opcode[0x10]; 8914 u8 uid[0x10]; 8915 8916 u8 reserved_at_20[0x10]; 8917 u8 op_mod[0x10]; 8918 8919 u8 reserved_at_40[0x8]; 8920 u8 cqn[0x18]; 8921 8922 u8 reserved_at_60[0x20]; 8923 }; 8924 8925 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8926 u8 status[0x8]; 8927 u8 reserved_at_8[0x18]; 8928 8929 u8 syndrome[0x20]; 8930 8931 u8 reserved_at_40[0x40]; 8932 }; 8933 8934 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8935 u8 opcode[0x10]; 8936 u8 reserved_at_10[0x10]; 8937 8938 u8 reserved_at_20[0x10]; 8939 u8 op_mod[0x10]; 8940 8941 u8 reserved_at_40[0x20]; 8942 8943 u8 reserved_at_60[0x10]; 8944 u8 vxlan_udp_port[0x10]; 8945 }; 8946 8947 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8948 u8 status[0x8]; 8949 u8 reserved_at_8[0x18]; 8950 8951 u8 syndrome[0x20]; 8952 8953 u8 reserved_at_40[0x40]; 8954 }; 8955 8956 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8957 u8 opcode[0x10]; 8958 u8 reserved_at_10[0x10]; 8959 8960 u8 reserved_at_20[0x10]; 8961 u8 op_mod[0x10]; 8962 8963 u8 reserved_at_40[0x60]; 8964 8965 u8 reserved_at_a0[0x8]; 8966 u8 table_index[0x18]; 8967 8968 u8 reserved_at_c0[0x140]; 8969 }; 8970 8971 struct mlx5_ifc_delete_fte_out_bits { 8972 u8 status[0x8]; 8973 u8 reserved_at_8[0x18]; 8974 8975 u8 syndrome[0x20]; 8976 8977 u8 reserved_at_40[0x40]; 8978 }; 8979 8980 struct mlx5_ifc_delete_fte_in_bits { 8981 u8 opcode[0x10]; 8982 u8 reserved_at_10[0x10]; 8983 8984 u8 reserved_at_20[0x10]; 8985 u8 op_mod[0x10]; 8986 8987 u8 other_vport[0x1]; 8988 u8 reserved_at_41[0xf]; 8989 u8 vport_number[0x10]; 8990 8991 u8 reserved_at_60[0x20]; 8992 8993 u8 table_type[0x8]; 8994 u8 reserved_at_88[0x18]; 8995 8996 u8 reserved_at_a0[0x8]; 8997 u8 table_id[0x18]; 8998 8999 u8 reserved_at_c0[0x40]; 9000 9001 u8 flow_index[0x20]; 9002 9003 u8 reserved_at_120[0xe0]; 9004 }; 9005 9006 struct mlx5_ifc_dealloc_xrcd_out_bits { 9007 u8 status[0x8]; 9008 u8 reserved_at_8[0x18]; 9009 9010 u8 syndrome[0x20]; 9011 9012 u8 reserved_at_40[0x40]; 9013 }; 9014 9015 struct mlx5_ifc_dealloc_xrcd_in_bits { 9016 u8 opcode[0x10]; 9017 u8 uid[0x10]; 9018 9019 u8 reserved_at_20[0x10]; 9020 u8 op_mod[0x10]; 9021 9022 u8 reserved_at_40[0x8]; 9023 u8 xrcd[0x18]; 9024 9025 u8 reserved_at_60[0x20]; 9026 }; 9027 9028 struct mlx5_ifc_dealloc_uar_out_bits { 9029 u8 status[0x8]; 9030 u8 reserved_at_8[0x18]; 9031 9032 u8 syndrome[0x20]; 9033 9034 u8 reserved_at_40[0x40]; 9035 }; 9036 9037 struct mlx5_ifc_dealloc_uar_in_bits { 9038 u8 opcode[0x10]; 9039 u8 uid[0x10]; 9040 9041 u8 reserved_at_20[0x10]; 9042 u8 op_mod[0x10]; 9043 9044 u8 reserved_at_40[0x8]; 9045 u8 uar[0x18]; 9046 9047 u8 reserved_at_60[0x20]; 9048 }; 9049 9050 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9051 u8 status[0x8]; 9052 u8 reserved_at_8[0x18]; 9053 9054 u8 syndrome[0x20]; 9055 9056 u8 reserved_at_40[0x40]; 9057 }; 9058 9059 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9060 u8 opcode[0x10]; 9061 u8 uid[0x10]; 9062 9063 u8 reserved_at_20[0x10]; 9064 u8 op_mod[0x10]; 9065 9066 u8 reserved_at_40[0x8]; 9067 u8 transport_domain[0x18]; 9068 9069 u8 reserved_at_60[0x20]; 9070 }; 9071 9072 struct mlx5_ifc_dealloc_q_counter_out_bits { 9073 u8 status[0x8]; 9074 u8 reserved_at_8[0x18]; 9075 9076 u8 syndrome[0x20]; 9077 9078 u8 reserved_at_40[0x40]; 9079 }; 9080 9081 struct mlx5_ifc_dealloc_q_counter_in_bits { 9082 u8 opcode[0x10]; 9083 u8 reserved_at_10[0x10]; 9084 9085 u8 reserved_at_20[0x10]; 9086 u8 op_mod[0x10]; 9087 9088 u8 reserved_at_40[0x18]; 9089 u8 counter_set_id[0x8]; 9090 9091 u8 reserved_at_60[0x20]; 9092 }; 9093 9094 struct mlx5_ifc_dealloc_pd_out_bits { 9095 u8 status[0x8]; 9096 u8 reserved_at_8[0x18]; 9097 9098 u8 syndrome[0x20]; 9099 9100 u8 reserved_at_40[0x40]; 9101 }; 9102 9103 struct mlx5_ifc_dealloc_pd_in_bits { 9104 u8 opcode[0x10]; 9105 u8 uid[0x10]; 9106 9107 u8 reserved_at_20[0x10]; 9108 u8 op_mod[0x10]; 9109 9110 u8 reserved_at_40[0x8]; 9111 u8 pd[0x18]; 9112 9113 u8 reserved_at_60[0x20]; 9114 }; 9115 9116 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9117 u8 status[0x8]; 9118 u8 reserved_at_8[0x18]; 9119 9120 u8 syndrome[0x20]; 9121 9122 u8 reserved_at_40[0x40]; 9123 }; 9124 9125 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9126 u8 opcode[0x10]; 9127 u8 reserved_at_10[0x10]; 9128 9129 u8 reserved_at_20[0x10]; 9130 u8 op_mod[0x10]; 9131 9132 u8 flow_counter_id[0x20]; 9133 9134 u8 reserved_at_60[0x20]; 9135 }; 9136 9137 struct mlx5_ifc_create_xrq_out_bits { 9138 u8 status[0x8]; 9139 u8 reserved_at_8[0x18]; 9140 9141 u8 syndrome[0x20]; 9142 9143 u8 reserved_at_40[0x8]; 9144 u8 xrqn[0x18]; 9145 9146 u8 reserved_at_60[0x20]; 9147 }; 9148 9149 struct mlx5_ifc_create_xrq_in_bits { 9150 u8 opcode[0x10]; 9151 u8 uid[0x10]; 9152 9153 u8 reserved_at_20[0x10]; 9154 u8 op_mod[0x10]; 9155 9156 u8 reserved_at_40[0x40]; 9157 9158 struct mlx5_ifc_xrqc_bits xrq_context; 9159 }; 9160 9161 struct mlx5_ifc_create_xrc_srq_out_bits { 9162 u8 status[0x8]; 9163 u8 reserved_at_8[0x18]; 9164 9165 u8 syndrome[0x20]; 9166 9167 u8 reserved_at_40[0x8]; 9168 u8 xrc_srqn[0x18]; 9169 9170 u8 reserved_at_60[0x20]; 9171 }; 9172 9173 struct mlx5_ifc_create_xrc_srq_in_bits { 9174 u8 opcode[0x10]; 9175 u8 uid[0x10]; 9176 9177 u8 reserved_at_20[0x10]; 9178 u8 op_mod[0x10]; 9179 9180 u8 reserved_at_40[0x40]; 9181 9182 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9183 9184 u8 reserved_at_280[0x60]; 9185 9186 u8 xrc_srq_umem_valid[0x1]; 9187 u8 reserved_at_2e1[0x1f]; 9188 9189 u8 reserved_at_300[0x580]; 9190 9191 u8 pas[][0x40]; 9192 }; 9193 9194 struct mlx5_ifc_create_tis_out_bits { 9195 u8 status[0x8]; 9196 u8 reserved_at_8[0x18]; 9197 9198 u8 syndrome[0x20]; 9199 9200 u8 reserved_at_40[0x8]; 9201 u8 tisn[0x18]; 9202 9203 u8 reserved_at_60[0x20]; 9204 }; 9205 9206 struct mlx5_ifc_create_tis_in_bits { 9207 u8 opcode[0x10]; 9208 u8 uid[0x10]; 9209 9210 u8 reserved_at_20[0x10]; 9211 u8 op_mod[0x10]; 9212 9213 u8 reserved_at_40[0xc0]; 9214 9215 struct mlx5_ifc_tisc_bits ctx; 9216 }; 9217 9218 struct mlx5_ifc_create_tir_out_bits { 9219 u8 status[0x8]; 9220 u8 icm_address_63_40[0x18]; 9221 9222 u8 syndrome[0x20]; 9223 9224 u8 icm_address_39_32[0x8]; 9225 u8 tirn[0x18]; 9226 9227 u8 icm_address_31_0[0x20]; 9228 }; 9229 9230 struct mlx5_ifc_create_tir_in_bits { 9231 u8 opcode[0x10]; 9232 u8 uid[0x10]; 9233 9234 u8 reserved_at_20[0x10]; 9235 u8 op_mod[0x10]; 9236 9237 u8 reserved_at_40[0xc0]; 9238 9239 struct mlx5_ifc_tirc_bits ctx; 9240 }; 9241 9242 struct mlx5_ifc_create_srq_out_bits { 9243 u8 status[0x8]; 9244 u8 reserved_at_8[0x18]; 9245 9246 u8 syndrome[0x20]; 9247 9248 u8 reserved_at_40[0x8]; 9249 u8 srqn[0x18]; 9250 9251 u8 reserved_at_60[0x20]; 9252 }; 9253 9254 struct mlx5_ifc_create_srq_in_bits { 9255 u8 opcode[0x10]; 9256 u8 uid[0x10]; 9257 9258 u8 reserved_at_20[0x10]; 9259 u8 op_mod[0x10]; 9260 9261 u8 reserved_at_40[0x40]; 9262 9263 struct mlx5_ifc_srqc_bits srq_context_entry; 9264 9265 u8 reserved_at_280[0x600]; 9266 9267 u8 pas[][0x40]; 9268 }; 9269 9270 struct mlx5_ifc_create_sq_out_bits { 9271 u8 status[0x8]; 9272 u8 reserved_at_8[0x18]; 9273 9274 u8 syndrome[0x20]; 9275 9276 u8 reserved_at_40[0x8]; 9277 u8 sqn[0x18]; 9278 9279 u8 reserved_at_60[0x20]; 9280 }; 9281 9282 struct mlx5_ifc_create_sq_in_bits { 9283 u8 opcode[0x10]; 9284 u8 uid[0x10]; 9285 9286 u8 reserved_at_20[0x10]; 9287 u8 op_mod[0x10]; 9288 9289 u8 reserved_at_40[0xc0]; 9290 9291 struct mlx5_ifc_sqc_bits ctx; 9292 }; 9293 9294 struct mlx5_ifc_create_scheduling_element_out_bits { 9295 u8 status[0x8]; 9296 u8 reserved_at_8[0x18]; 9297 9298 u8 syndrome[0x20]; 9299 9300 u8 reserved_at_40[0x40]; 9301 9302 u8 scheduling_element_id[0x20]; 9303 9304 u8 reserved_at_a0[0x160]; 9305 }; 9306 9307 struct mlx5_ifc_create_scheduling_element_in_bits { 9308 u8 opcode[0x10]; 9309 u8 reserved_at_10[0x10]; 9310 9311 u8 reserved_at_20[0x10]; 9312 u8 op_mod[0x10]; 9313 9314 u8 scheduling_hierarchy[0x8]; 9315 u8 reserved_at_48[0x18]; 9316 9317 u8 reserved_at_60[0xa0]; 9318 9319 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9320 9321 u8 reserved_at_300[0x100]; 9322 }; 9323 9324 struct mlx5_ifc_create_rqt_out_bits { 9325 u8 status[0x8]; 9326 u8 reserved_at_8[0x18]; 9327 9328 u8 syndrome[0x20]; 9329 9330 u8 reserved_at_40[0x8]; 9331 u8 rqtn[0x18]; 9332 9333 u8 reserved_at_60[0x20]; 9334 }; 9335 9336 struct mlx5_ifc_create_rqt_in_bits { 9337 u8 opcode[0x10]; 9338 u8 uid[0x10]; 9339 9340 u8 reserved_at_20[0x10]; 9341 u8 op_mod[0x10]; 9342 9343 u8 reserved_at_40[0xc0]; 9344 9345 struct mlx5_ifc_rqtc_bits rqt_context; 9346 }; 9347 9348 struct mlx5_ifc_create_rq_out_bits { 9349 u8 status[0x8]; 9350 u8 reserved_at_8[0x18]; 9351 9352 u8 syndrome[0x20]; 9353 9354 u8 reserved_at_40[0x8]; 9355 u8 rqn[0x18]; 9356 9357 u8 reserved_at_60[0x20]; 9358 }; 9359 9360 struct mlx5_ifc_create_rq_in_bits { 9361 u8 opcode[0x10]; 9362 u8 uid[0x10]; 9363 9364 u8 reserved_at_20[0x10]; 9365 u8 op_mod[0x10]; 9366 9367 u8 reserved_at_40[0xc0]; 9368 9369 struct mlx5_ifc_rqc_bits ctx; 9370 }; 9371 9372 struct mlx5_ifc_create_rmp_out_bits { 9373 u8 status[0x8]; 9374 u8 reserved_at_8[0x18]; 9375 9376 u8 syndrome[0x20]; 9377 9378 u8 reserved_at_40[0x8]; 9379 u8 rmpn[0x18]; 9380 9381 u8 reserved_at_60[0x20]; 9382 }; 9383 9384 struct mlx5_ifc_create_rmp_in_bits { 9385 u8 opcode[0x10]; 9386 u8 uid[0x10]; 9387 9388 u8 reserved_at_20[0x10]; 9389 u8 op_mod[0x10]; 9390 9391 u8 reserved_at_40[0xc0]; 9392 9393 struct mlx5_ifc_rmpc_bits ctx; 9394 }; 9395 9396 struct mlx5_ifc_create_qp_out_bits { 9397 u8 status[0x8]; 9398 u8 reserved_at_8[0x18]; 9399 9400 u8 syndrome[0x20]; 9401 9402 u8 reserved_at_40[0x8]; 9403 u8 qpn[0x18]; 9404 9405 u8 ece[0x20]; 9406 }; 9407 9408 struct mlx5_ifc_create_qp_in_bits { 9409 u8 opcode[0x10]; 9410 u8 uid[0x10]; 9411 9412 u8 reserved_at_20[0x10]; 9413 u8 op_mod[0x10]; 9414 9415 u8 qpc_ext[0x1]; 9416 u8 reserved_at_41[0x7]; 9417 u8 input_qpn[0x18]; 9418 9419 u8 reserved_at_60[0x20]; 9420 u8 opt_param_mask[0x20]; 9421 9422 u8 ece[0x20]; 9423 9424 struct mlx5_ifc_qpc_bits qpc; 9425 9426 u8 wq_umem_offset[0x40]; 9427 9428 u8 wq_umem_id[0x20]; 9429 9430 u8 wq_umem_valid[0x1]; 9431 u8 reserved_at_861[0x1f]; 9432 9433 u8 pas[][0x40]; 9434 }; 9435 9436 struct mlx5_ifc_create_psv_out_bits { 9437 u8 status[0x8]; 9438 u8 reserved_at_8[0x18]; 9439 9440 u8 syndrome[0x20]; 9441 9442 u8 reserved_at_40[0x40]; 9443 9444 u8 reserved_at_80[0x8]; 9445 u8 psv0_index[0x18]; 9446 9447 u8 reserved_at_a0[0x8]; 9448 u8 psv1_index[0x18]; 9449 9450 u8 reserved_at_c0[0x8]; 9451 u8 psv2_index[0x18]; 9452 9453 u8 reserved_at_e0[0x8]; 9454 u8 psv3_index[0x18]; 9455 }; 9456 9457 struct mlx5_ifc_create_psv_in_bits { 9458 u8 opcode[0x10]; 9459 u8 reserved_at_10[0x10]; 9460 9461 u8 reserved_at_20[0x10]; 9462 u8 op_mod[0x10]; 9463 9464 u8 num_psv[0x4]; 9465 u8 reserved_at_44[0x4]; 9466 u8 pd[0x18]; 9467 9468 u8 reserved_at_60[0x20]; 9469 }; 9470 9471 struct mlx5_ifc_create_mkey_out_bits { 9472 u8 status[0x8]; 9473 u8 reserved_at_8[0x18]; 9474 9475 u8 syndrome[0x20]; 9476 9477 u8 reserved_at_40[0x8]; 9478 u8 mkey_index[0x18]; 9479 9480 u8 reserved_at_60[0x20]; 9481 }; 9482 9483 struct mlx5_ifc_create_mkey_in_bits { 9484 u8 opcode[0x10]; 9485 u8 uid[0x10]; 9486 9487 u8 reserved_at_20[0x10]; 9488 u8 op_mod[0x10]; 9489 9490 u8 reserved_at_40[0x20]; 9491 9492 u8 pg_access[0x1]; 9493 u8 mkey_umem_valid[0x1]; 9494 u8 data_direct[0x1]; 9495 u8 reserved_at_63[0x1d]; 9496 9497 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9498 9499 u8 reserved_at_280[0x80]; 9500 9501 u8 translations_octword_actual_size[0x20]; 9502 9503 u8 reserved_at_320[0x560]; 9504 9505 u8 klm_pas_mtt[][0x20]; 9506 }; 9507 9508 enum { 9509 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9510 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9511 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9512 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9513 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9514 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9515 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9516 }; 9517 9518 struct mlx5_ifc_create_flow_table_out_bits { 9519 u8 status[0x8]; 9520 u8 icm_address_63_40[0x18]; 9521 9522 u8 syndrome[0x20]; 9523 9524 u8 icm_address_39_32[0x8]; 9525 u8 table_id[0x18]; 9526 9527 u8 icm_address_31_0[0x20]; 9528 }; 9529 9530 struct mlx5_ifc_create_flow_table_in_bits { 9531 u8 opcode[0x10]; 9532 u8 uid[0x10]; 9533 9534 u8 reserved_at_20[0x10]; 9535 u8 op_mod[0x10]; 9536 9537 u8 other_vport[0x1]; 9538 u8 reserved_at_41[0xf]; 9539 u8 vport_number[0x10]; 9540 9541 u8 reserved_at_60[0x20]; 9542 9543 u8 table_type[0x8]; 9544 u8 reserved_at_88[0x18]; 9545 9546 u8 reserved_at_a0[0x20]; 9547 9548 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9549 }; 9550 9551 struct mlx5_ifc_create_flow_group_out_bits { 9552 u8 status[0x8]; 9553 u8 reserved_at_8[0x18]; 9554 9555 u8 syndrome[0x20]; 9556 9557 u8 reserved_at_40[0x8]; 9558 u8 group_id[0x18]; 9559 9560 u8 reserved_at_60[0x20]; 9561 }; 9562 9563 enum { 9564 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9565 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9566 }; 9567 9568 enum { 9569 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9570 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9571 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9572 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9573 }; 9574 9575 struct mlx5_ifc_create_flow_group_in_bits { 9576 u8 opcode[0x10]; 9577 u8 reserved_at_10[0x10]; 9578 9579 u8 reserved_at_20[0x10]; 9580 u8 op_mod[0x10]; 9581 9582 u8 other_vport[0x1]; 9583 u8 reserved_at_41[0xf]; 9584 u8 vport_number[0x10]; 9585 9586 u8 reserved_at_60[0x20]; 9587 9588 u8 table_type[0x8]; 9589 u8 reserved_at_88[0x4]; 9590 u8 group_type[0x4]; 9591 u8 reserved_at_90[0x10]; 9592 9593 u8 reserved_at_a0[0x8]; 9594 u8 table_id[0x18]; 9595 9596 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9597 9598 u8 reserved_at_c1[0x1f]; 9599 9600 u8 start_flow_index[0x20]; 9601 9602 u8 reserved_at_100[0x20]; 9603 9604 u8 end_flow_index[0x20]; 9605 9606 u8 reserved_at_140[0x10]; 9607 u8 match_definer_id[0x10]; 9608 9609 u8 reserved_at_160[0x80]; 9610 9611 u8 reserved_at_1e0[0x18]; 9612 u8 match_criteria_enable[0x8]; 9613 9614 struct mlx5_ifc_fte_match_param_bits match_criteria; 9615 9616 u8 reserved_at_1200[0xe00]; 9617 }; 9618 9619 struct mlx5_ifc_create_eq_out_bits { 9620 u8 status[0x8]; 9621 u8 reserved_at_8[0x18]; 9622 9623 u8 syndrome[0x20]; 9624 9625 u8 reserved_at_40[0x18]; 9626 u8 eq_number[0x8]; 9627 9628 u8 reserved_at_60[0x20]; 9629 }; 9630 9631 struct mlx5_ifc_create_eq_in_bits { 9632 u8 opcode[0x10]; 9633 u8 uid[0x10]; 9634 9635 u8 reserved_at_20[0x10]; 9636 u8 op_mod[0x10]; 9637 9638 u8 reserved_at_40[0x40]; 9639 9640 struct mlx5_ifc_eqc_bits eq_context_entry; 9641 9642 u8 reserved_at_280[0x40]; 9643 9644 u8 event_bitmask[4][0x40]; 9645 9646 u8 reserved_at_3c0[0x4c0]; 9647 9648 u8 pas[][0x40]; 9649 }; 9650 9651 struct mlx5_ifc_create_dct_out_bits { 9652 u8 status[0x8]; 9653 u8 reserved_at_8[0x18]; 9654 9655 u8 syndrome[0x20]; 9656 9657 u8 reserved_at_40[0x8]; 9658 u8 dctn[0x18]; 9659 9660 u8 ece[0x20]; 9661 }; 9662 9663 struct mlx5_ifc_create_dct_in_bits { 9664 u8 opcode[0x10]; 9665 u8 uid[0x10]; 9666 9667 u8 reserved_at_20[0x10]; 9668 u8 op_mod[0x10]; 9669 9670 u8 reserved_at_40[0x40]; 9671 9672 struct mlx5_ifc_dctc_bits dct_context_entry; 9673 9674 u8 reserved_at_280[0x180]; 9675 }; 9676 9677 struct mlx5_ifc_create_cq_out_bits { 9678 u8 status[0x8]; 9679 u8 reserved_at_8[0x18]; 9680 9681 u8 syndrome[0x20]; 9682 9683 u8 reserved_at_40[0x8]; 9684 u8 cqn[0x18]; 9685 9686 u8 reserved_at_60[0x20]; 9687 }; 9688 9689 struct mlx5_ifc_create_cq_in_bits { 9690 u8 opcode[0x10]; 9691 u8 uid[0x10]; 9692 9693 u8 reserved_at_20[0x10]; 9694 u8 op_mod[0x10]; 9695 9696 u8 reserved_at_40[0x40]; 9697 9698 struct mlx5_ifc_cqc_bits cq_context; 9699 9700 u8 reserved_at_280[0x60]; 9701 9702 u8 cq_umem_valid[0x1]; 9703 u8 reserved_at_2e1[0x59f]; 9704 9705 u8 pas[][0x40]; 9706 }; 9707 9708 struct mlx5_ifc_config_int_moderation_out_bits { 9709 u8 status[0x8]; 9710 u8 reserved_at_8[0x18]; 9711 9712 u8 syndrome[0x20]; 9713 9714 u8 reserved_at_40[0x4]; 9715 u8 min_delay[0xc]; 9716 u8 int_vector[0x10]; 9717 9718 u8 reserved_at_60[0x20]; 9719 }; 9720 9721 enum { 9722 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9723 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9724 }; 9725 9726 struct mlx5_ifc_config_int_moderation_in_bits { 9727 u8 opcode[0x10]; 9728 u8 reserved_at_10[0x10]; 9729 9730 u8 reserved_at_20[0x10]; 9731 u8 op_mod[0x10]; 9732 9733 u8 reserved_at_40[0x4]; 9734 u8 min_delay[0xc]; 9735 u8 int_vector[0x10]; 9736 9737 u8 reserved_at_60[0x20]; 9738 }; 9739 9740 struct mlx5_ifc_attach_to_mcg_out_bits { 9741 u8 status[0x8]; 9742 u8 reserved_at_8[0x18]; 9743 9744 u8 syndrome[0x20]; 9745 9746 u8 reserved_at_40[0x40]; 9747 }; 9748 9749 struct mlx5_ifc_attach_to_mcg_in_bits { 9750 u8 opcode[0x10]; 9751 u8 uid[0x10]; 9752 9753 u8 reserved_at_20[0x10]; 9754 u8 op_mod[0x10]; 9755 9756 u8 reserved_at_40[0x8]; 9757 u8 qpn[0x18]; 9758 9759 u8 reserved_at_60[0x20]; 9760 9761 u8 multicast_gid[16][0x8]; 9762 }; 9763 9764 struct mlx5_ifc_arm_xrq_out_bits { 9765 u8 status[0x8]; 9766 u8 reserved_at_8[0x18]; 9767 9768 u8 syndrome[0x20]; 9769 9770 u8 reserved_at_40[0x40]; 9771 }; 9772 9773 struct mlx5_ifc_arm_xrq_in_bits { 9774 u8 opcode[0x10]; 9775 u8 reserved_at_10[0x10]; 9776 9777 u8 reserved_at_20[0x10]; 9778 u8 op_mod[0x10]; 9779 9780 u8 reserved_at_40[0x8]; 9781 u8 xrqn[0x18]; 9782 9783 u8 reserved_at_60[0x10]; 9784 u8 lwm[0x10]; 9785 }; 9786 9787 struct mlx5_ifc_arm_xrc_srq_out_bits { 9788 u8 status[0x8]; 9789 u8 reserved_at_8[0x18]; 9790 9791 u8 syndrome[0x20]; 9792 9793 u8 reserved_at_40[0x40]; 9794 }; 9795 9796 enum { 9797 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9798 }; 9799 9800 struct mlx5_ifc_arm_xrc_srq_in_bits { 9801 u8 opcode[0x10]; 9802 u8 uid[0x10]; 9803 9804 u8 reserved_at_20[0x10]; 9805 u8 op_mod[0x10]; 9806 9807 u8 reserved_at_40[0x8]; 9808 u8 xrc_srqn[0x18]; 9809 9810 u8 reserved_at_60[0x10]; 9811 u8 lwm[0x10]; 9812 }; 9813 9814 struct mlx5_ifc_arm_rq_out_bits { 9815 u8 status[0x8]; 9816 u8 reserved_at_8[0x18]; 9817 9818 u8 syndrome[0x20]; 9819 9820 u8 reserved_at_40[0x40]; 9821 }; 9822 9823 enum { 9824 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9825 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9826 }; 9827 9828 struct mlx5_ifc_arm_rq_in_bits { 9829 u8 opcode[0x10]; 9830 u8 uid[0x10]; 9831 9832 u8 reserved_at_20[0x10]; 9833 u8 op_mod[0x10]; 9834 9835 u8 reserved_at_40[0x8]; 9836 u8 srq_number[0x18]; 9837 9838 u8 reserved_at_60[0x10]; 9839 u8 lwm[0x10]; 9840 }; 9841 9842 struct mlx5_ifc_arm_dct_out_bits { 9843 u8 status[0x8]; 9844 u8 reserved_at_8[0x18]; 9845 9846 u8 syndrome[0x20]; 9847 9848 u8 reserved_at_40[0x40]; 9849 }; 9850 9851 struct mlx5_ifc_arm_dct_in_bits { 9852 u8 opcode[0x10]; 9853 u8 reserved_at_10[0x10]; 9854 9855 u8 reserved_at_20[0x10]; 9856 u8 op_mod[0x10]; 9857 9858 u8 reserved_at_40[0x8]; 9859 u8 dct_number[0x18]; 9860 9861 u8 reserved_at_60[0x20]; 9862 }; 9863 9864 struct mlx5_ifc_alloc_xrcd_out_bits { 9865 u8 status[0x8]; 9866 u8 reserved_at_8[0x18]; 9867 9868 u8 syndrome[0x20]; 9869 9870 u8 reserved_at_40[0x8]; 9871 u8 xrcd[0x18]; 9872 9873 u8 reserved_at_60[0x20]; 9874 }; 9875 9876 struct mlx5_ifc_alloc_xrcd_in_bits { 9877 u8 opcode[0x10]; 9878 u8 uid[0x10]; 9879 9880 u8 reserved_at_20[0x10]; 9881 u8 op_mod[0x10]; 9882 9883 u8 reserved_at_40[0x40]; 9884 }; 9885 9886 struct mlx5_ifc_alloc_uar_out_bits { 9887 u8 status[0x8]; 9888 u8 reserved_at_8[0x18]; 9889 9890 u8 syndrome[0x20]; 9891 9892 u8 reserved_at_40[0x8]; 9893 u8 uar[0x18]; 9894 9895 u8 reserved_at_60[0x20]; 9896 }; 9897 9898 struct mlx5_ifc_alloc_uar_in_bits { 9899 u8 opcode[0x10]; 9900 u8 uid[0x10]; 9901 9902 u8 reserved_at_20[0x10]; 9903 u8 op_mod[0x10]; 9904 9905 u8 reserved_at_40[0x40]; 9906 }; 9907 9908 struct mlx5_ifc_alloc_transport_domain_out_bits { 9909 u8 status[0x8]; 9910 u8 reserved_at_8[0x18]; 9911 9912 u8 syndrome[0x20]; 9913 9914 u8 reserved_at_40[0x8]; 9915 u8 transport_domain[0x18]; 9916 9917 u8 reserved_at_60[0x20]; 9918 }; 9919 9920 struct mlx5_ifc_alloc_transport_domain_in_bits { 9921 u8 opcode[0x10]; 9922 u8 uid[0x10]; 9923 9924 u8 reserved_at_20[0x10]; 9925 u8 op_mod[0x10]; 9926 9927 u8 reserved_at_40[0x40]; 9928 }; 9929 9930 struct mlx5_ifc_alloc_q_counter_out_bits { 9931 u8 status[0x8]; 9932 u8 reserved_at_8[0x18]; 9933 9934 u8 syndrome[0x20]; 9935 9936 u8 reserved_at_40[0x18]; 9937 u8 counter_set_id[0x8]; 9938 9939 u8 reserved_at_60[0x20]; 9940 }; 9941 9942 struct mlx5_ifc_alloc_q_counter_in_bits { 9943 u8 opcode[0x10]; 9944 u8 uid[0x10]; 9945 9946 u8 reserved_at_20[0x10]; 9947 u8 op_mod[0x10]; 9948 9949 u8 reserved_at_40[0x40]; 9950 }; 9951 9952 struct mlx5_ifc_alloc_pd_out_bits { 9953 u8 status[0x8]; 9954 u8 reserved_at_8[0x18]; 9955 9956 u8 syndrome[0x20]; 9957 9958 u8 reserved_at_40[0x8]; 9959 u8 pd[0x18]; 9960 9961 u8 reserved_at_60[0x20]; 9962 }; 9963 9964 struct mlx5_ifc_alloc_pd_in_bits { 9965 u8 opcode[0x10]; 9966 u8 uid[0x10]; 9967 9968 u8 reserved_at_20[0x10]; 9969 u8 op_mod[0x10]; 9970 9971 u8 reserved_at_40[0x40]; 9972 }; 9973 9974 struct mlx5_ifc_alloc_flow_counter_out_bits { 9975 u8 status[0x8]; 9976 u8 reserved_at_8[0x18]; 9977 9978 u8 syndrome[0x20]; 9979 9980 u8 flow_counter_id[0x20]; 9981 9982 u8 reserved_at_60[0x20]; 9983 }; 9984 9985 struct mlx5_ifc_alloc_flow_counter_in_bits { 9986 u8 opcode[0x10]; 9987 u8 reserved_at_10[0x10]; 9988 9989 u8 reserved_at_20[0x10]; 9990 u8 op_mod[0x10]; 9991 9992 u8 reserved_at_40[0x33]; 9993 u8 flow_counter_bulk_log_size[0x5]; 9994 u8 flow_counter_bulk[0x8]; 9995 }; 9996 9997 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9998 u8 status[0x8]; 9999 u8 reserved_at_8[0x18]; 10000 10001 u8 syndrome[0x20]; 10002 10003 u8 reserved_at_40[0x40]; 10004 }; 10005 10006 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 10007 u8 opcode[0x10]; 10008 u8 reserved_at_10[0x10]; 10009 10010 u8 reserved_at_20[0x10]; 10011 u8 op_mod[0x10]; 10012 10013 u8 reserved_at_40[0x20]; 10014 10015 u8 reserved_at_60[0x10]; 10016 u8 vxlan_udp_port[0x10]; 10017 }; 10018 10019 struct mlx5_ifc_set_pp_rate_limit_out_bits { 10020 u8 status[0x8]; 10021 u8 reserved_at_8[0x18]; 10022 10023 u8 syndrome[0x20]; 10024 10025 u8 reserved_at_40[0x40]; 10026 }; 10027 10028 struct mlx5_ifc_set_pp_rate_limit_context_bits { 10029 u8 rate_limit[0x20]; 10030 10031 u8 burst_upper_bound[0x20]; 10032 10033 u8 reserved_at_40[0x10]; 10034 u8 typical_packet_size[0x10]; 10035 10036 u8 reserved_at_60[0x120]; 10037 }; 10038 10039 struct mlx5_ifc_set_pp_rate_limit_in_bits { 10040 u8 opcode[0x10]; 10041 u8 uid[0x10]; 10042 10043 u8 reserved_at_20[0x10]; 10044 u8 op_mod[0x10]; 10045 10046 u8 reserved_at_40[0x10]; 10047 u8 rate_limit_index[0x10]; 10048 10049 u8 reserved_at_60[0x20]; 10050 10051 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10052 }; 10053 10054 struct mlx5_ifc_access_register_out_bits { 10055 u8 status[0x8]; 10056 u8 reserved_at_8[0x18]; 10057 10058 u8 syndrome[0x20]; 10059 10060 u8 reserved_at_40[0x40]; 10061 10062 u8 register_data[][0x20]; 10063 }; 10064 10065 enum { 10066 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10067 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10068 }; 10069 10070 struct mlx5_ifc_access_register_in_bits { 10071 u8 opcode[0x10]; 10072 u8 reserved_at_10[0x10]; 10073 10074 u8 reserved_at_20[0x10]; 10075 u8 op_mod[0x10]; 10076 10077 u8 reserved_at_40[0x10]; 10078 u8 register_id[0x10]; 10079 10080 u8 argument[0x20]; 10081 10082 u8 register_data[][0x20]; 10083 }; 10084 10085 struct mlx5_ifc_sltp_reg_bits { 10086 u8 status[0x4]; 10087 u8 version[0x4]; 10088 u8 local_port[0x8]; 10089 u8 pnat[0x2]; 10090 u8 reserved_at_12[0x2]; 10091 u8 lane[0x4]; 10092 u8 reserved_at_18[0x8]; 10093 10094 u8 reserved_at_20[0x20]; 10095 10096 u8 reserved_at_40[0x7]; 10097 u8 polarity[0x1]; 10098 u8 ob_tap0[0x8]; 10099 u8 ob_tap1[0x8]; 10100 u8 ob_tap2[0x8]; 10101 10102 u8 reserved_at_60[0xc]; 10103 u8 ob_preemp_mode[0x4]; 10104 u8 ob_reg[0x8]; 10105 u8 ob_bias[0x8]; 10106 10107 u8 reserved_at_80[0x20]; 10108 }; 10109 10110 struct mlx5_ifc_slrg_reg_bits { 10111 u8 status[0x4]; 10112 u8 version[0x4]; 10113 u8 local_port[0x8]; 10114 u8 pnat[0x2]; 10115 u8 reserved_at_12[0x2]; 10116 u8 lane[0x4]; 10117 u8 reserved_at_18[0x8]; 10118 10119 u8 time_to_link_up[0x10]; 10120 u8 reserved_at_30[0xc]; 10121 u8 grade_lane_speed[0x4]; 10122 10123 u8 grade_version[0x8]; 10124 u8 grade[0x18]; 10125 10126 u8 reserved_at_60[0x4]; 10127 u8 height_grade_type[0x4]; 10128 u8 height_grade[0x18]; 10129 10130 u8 height_dz[0x10]; 10131 u8 height_dv[0x10]; 10132 10133 u8 reserved_at_a0[0x10]; 10134 u8 height_sigma[0x10]; 10135 10136 u8 reserved_at_c0[0x20]; 10137 10138 u8 reserved_at_e0[0x4]; 10139 u8 phase_grade_type[0x4]; 10140 u8 phase_grade[0x18]; 10141 10142 u8 reserved_at_100[0x8]; 10143 u8 phase_eo_pos[0x8]; 10144 u8 reserved_at_110[0x8]; 10145 u8 phase_eo_neg[0x8]; 10146 10147 u8 ffe_set_tested[0x10]; 10148 u8 test_errors_per_lane[0x10]; 10149 }; 10150 10151 struct mlx5_ifc_pvlc_reg_bits { 10152 u8 reserved_at_0[0x8]; 10153 u8 local_port[0x8]; 10154 u8 reserved_at_10[0x10]; 10155 10156 u8 reserved_at_20[0x1c]; 10157 u8 vl_hw_cap[0x4]; 10158 10159 u8 reserved_at_40[0x1c]; 10160 u8 vl_admin[0x4]; 10161 10162 u8 reserved_at_60[0x1c]; 10163 u8 vl_operational[0x4]; 10164 }; 10165 10166 struct mlx5_ifc_pude_reg_bits { 10167 u8 swid[0x8]; 10168 u8 local_port[0x8]; 10169 u8 reserved_at_10[0x4]; 10170 u8 admin_status[0x4]; 10171 u8 reserved_at_18[0x4]; 10172 u8 oper_status[0x4]; 10173 10174 u8 reserved_at_20[0x60]; 10175 }; 10176 10177 enum { 10178 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10179 }; 10180 10181 struct mlx5_ifc_ptys_reg_bits { 10182 u8 reserved_at_0[0x1]; 10183 u8 an_disable_admin[0x1]; 10184 u8 an_disable_cap[0x1]; 10185 u8 reserved_at_3[0x5]; 10186 u8 local_port[0x8]; 10187 u8 reserved_at_10[0x8]; 10188 u8 plane_ind[0x4]; 10189 u8 reserved_at_1c[0x1]; 10190 u8 proto_mask[0x3]; 10191 10192 u8 an_status[0x4]; 10193 u8 reserved_at_24[0xc]; 10194 u8 data_rate_oper[0x10]; 10195 10196 u8 ext_eth_proto_capability[0x20]; 10197 10198 u8 eth_proto_capability[0x20]; 10199 10200 u8 ib_link_width_capability[0x10]; 10201 u8 ib_proto_capability[0x10]; 10202 10203 u8 ext_eth_proto_admin[0x20]; 10204 10205 u8 eth_proto_admin[0x20]; 10206 10207 u8 ib_link_width_admin[0x10]; 10208 u8 ib_proto_admin[0x10]; 10209 10210 u8 ext_eth_proto_oper[0x20]; 10211 10212 u8 eth_proto_oper[0x20]; 10213 10214 u8 ib_link_width_oper[0x10]; 10215 u8 ib_proto_oper[0x10]; 10216 10217 u8 reserved_at_160[0x8]; 10218 u8 lane_rate_oper[0x14]; 10219 u8 connector_type[0x4]; 10220 10221 u8 eth_proto_lp_advertise[0x20]; 10222 10223 u8 reserved_at_1a0[0x60]; 10224 }; 10225 10226 struct mlx5_ifc_mlcr_reg_bits { 10227 u8 reserved_at_0[0x8]; 10228 u8 local_port[0x8]; 10229 u8 reserved_at_10[0x20]; 10230 10231 u8 beacon_duration[0x10]; 10232 u8 reserved_at_40[0x10]; 10233 10234 u8 beacon_remain[0x10]; 10235 }; 10236 10237 struct mlx5_ifc_ptas_reg_bits { 10238 u8 reserved_at_0[0x20]; 10239 10240 u8 algorithm_options[0x10]; 10241 u8 reserved_at_30[0x4]; 10242 u8 repetitions_mode[0x4]; 10243 u8 num_of_repetitions[0x8]; 10244 10245 u8 grade_version[0x8]; 10246 u8 height_grade_type[0x4]; 10247 u8 phase_grade_type[0x4]; 10248 u8 height_grade_weight[0x8]; 10249 u8 phase_grade_weight[0x8]; 10250 10251 u8 gisim_measure_bits[0x10]; 10252 u8 adaptive_tap_measure_bits[0x10]; 10253 10254 u8 ber_bath_high_error_threshold[0x10]; 10255 u8 ber_bath_mid_error_threshold[0x10]; 10256 10257 u8 ber_bath_low_error_threshold[0x10]; 10258 u8 one_ratio_high_threshold[0x10]; 10259 10260 u8 one_ratio_high_mid_threshold[0x10]; 10261 u8 one_ratio_low_mid_threshold[0x10]; 10262 10263 u8 one_ratio_low_threshold[0x10]; 10264 u8 ndeo_error_threshold[0x10]; 10265 10266 u8 mixer_offset_step_size[0x10]; 10267 u8 reserved_at_110[0x8]; 10268 u8 mix90_phase_for_voltage_bath[0x8]; 10269 10270 u8 mixer_offset_start[0x10]; 10271 u8 mixer_offset_end[0x10]; 10272 10273 u8 reserved_at_140[0x15]; 10274 u8 ber_test_time[0xb]; 10275 }; 10276 10277 struct mlx5_ifc_pspa_reg_bits { 10278 u8 swid[0x8]; 10279 u8 local_port[0x8]; 10280 u8 sub_port[0x8]; 10281 u8 reserved_at_18[0x8]; 10282 10283 u8 reserved_at_20[0x20]; 10284 }; 10285 10286 struct mlx5_ifc_pqdr_reg_bits { 10287 u8 reserved_at_0[0x8]; 10288 u8 local_port[0x8]; 10289 u8 reserved_at_10[0x5]; 10290 u8 prio[0x3]; 10291 u8 reserved_at_18[0x6]; 10292 u8 mode[0x2]; 10293 10294 u8 reserved_at_20[0x20]; 10295 10296 u8 reserved_at_40[0x10]; 10297 u8 min_threshold[0x10]; 10298 10299 u8 reserved_at_60[0x10]; 10300 u8 max_threshold[0x10]; 10301 10302 u8 reserved_at_80[0x10]; 10303 u8 mark_probability_denominator[0x10]; 10304 10305 u8 reserved_at_a0[0x60]; 10306 }; 10307 10308 struct mlx5_ifc_ppsc_reg_bits { 10309 u8 reserved_at_0[0x8]; 10310 u8 local_port[0x8]; 10311 u8 reserved_at_10[0x10]; 10312 10313 u8 reserved_at_20[0x60]; 10314 10315 u8 reserved_at_80[0x1c]; 10316 u8 wrps_admin[0x4]; 10317 10318 u8 reserved_at_a0[0x1c]; 10319 u8 wrps_status[0x4]; 10320 10321 u8 reserved_at_c0[0x8]; 10322 u8 up_threshold[0x8]; 10323 u8 reserved_at_d0[0x8]; 10324 u8 down_threshold[0x8]; 10325 10326 u8 reserved_at_e0[0x20]; 10327 10328 u8 reserved_at_100[0x1c]; 10329 u8 srps_admin[0x4]; 10330 10331 u8 reserved_at_120[0x1c]; 10332 u8 srps_status[0x4]; 10333 10334 u8 reserved_at_140[0x40]; 10335 }; 10336 10337 struct mlx5_ifc_pplr_reg_bits { 10338 u8 reserved_at_0[0x8]; 10339 u8 local_port[0x8]; 10340 u8 reserved_at_10[0x10]; 10341 10342 u8 reserved_at_20[0x8]; 10343 u8 lb_cap[0x8]; 10344 u8 reserved_at_30[0x8]; 10345 u8 lb_en[0x8]; 10346 }; 10347 10348 struct mlx5_ifc_pplm_reg_bits { 10349 u8 reserved_at_0[0x8]; 10350 u8 local_port[0x8]; 10351 u8 reserved_at_10[0x10]; 10352 10353 u8 reserved_at_20[0x20]; 10354 10355 u8 port_profile_mode[0x8]; 10356 u8 static_port_profile[0x8]; 10357 u8 active_port_profile[0x8]; 10358 u8 reserved_at_58[0x8]; 10359 10360 u8 retransmission_active[0x8]; 10361 u8 fec_mode_active[0x18]; 10362 10363 u8 rs_fec_correction_bypass_cap[0x4]; 10364 u8 reserved_at_84[0x8]; 10365 u8 fec_override_cap_56g[0x4]; 10366 u8 fec_override_cap_100g[0x4]; 10367 u8 fec_override_cap_50g[0x4]; 10368 u8 fec_override_cap_25g[0x4]; 10369 u8 fec_override_cap_10g_40g[0x4]; 10370 10371 u8 rs_fec_correction_bypass_admin[0x4]; 10372 u8 reserved_at_a4[0x8]; 10373 u8 fec_override_admin_56g[0x4]; 10374 u8 fec_override_admin_100g[0x4]; 10375 u8 fec_override_admin_50g[0x4]; 10376 u8 fec_override_admin_25g[0x4]; 10377 u8 fec_override_admin_10g_40g[0x4]; 10378 10379 u8 fec_override_cap_400g_8x[0x10]; 10380 u8 fec_override_cap_200g_4x[0x10]; 10381 10382 u8 fec_override_cap_100g_2x[0x10]; 10383 u8 fec_override_cap_50g_1x[0x10]; 10384 10385 u8 fec_override_admin_400g_8x[0x10]; 10386 u8 fec_override_admin_200g_4x[0x10]; 10387 10388 u8 fec_override_admin_100g_2x[0x10]; 10389 u8 fec_override_admin_50g_1x[0x10]; 10390 10391 u8 fec_override_cap_800g_8x[0x10]; 10392 u8 fec_override_cap_400g_4x[0x10]; 10393 10394 u8 fec_override_cap_200g_2x[0x10]; 10395 u8 fec_override_cap_100g_1x[0x10]; 10396 10397 u8 reserved_at_180[0xa0]; 10398 10399 u8 fec_override_admin_800g_8x[0x10]; 10400 u8 fec_override_admin_400g_4x[0x10]; 10401 10402 u8 fec_override_admin_200g_2x[0x10]; 10403 u8 fec_override_admin_100g_1x[0x10]; 10404 10405 u8 reserved_at_260[0x60]; 10406 10407 u8 fec_override_cap_1600g_8x[0x10]; 10408 u8 fec_override_cap_800g_4x[0x10]; 10409 10410 u8 fec_override_cap_400g_2x[0x10]; 10411 u8 fec_override_cap_200g_1x[0x10]; 10412 10413 u8 fec_override_admin_1600g_8x[0x10]; 10414 u8 fec_override_admin_800g_4x[0x10]; 10415 10416 u8 fec_override_admin_400g_2x[0x10]; 10417 u8 fec_override_admin_200g_1x[0x10]; 10418 10419 u8 reserved_at_340[0x80]; 10420 }; 10421 10422 struct mlx5_ifc_ppcnt_reg_bits { 10423 u8 swid[0x8]; 10424 u8 local_port[0x8]; 10425 u8 pnat[0x2]; 10426 u8 reserved_at_12[0x8]; 10427 u8 grp[0x6]; 10428 10429 u8 clr[0x1]; 10430 u8 reserved_at_21[0x13]; 10431 u8 plane_ind[0x4]; 10432 u8 reserved_at_38[0x3]; 10433 u8 prio_tc[0x5]; 10434 10435 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10436 }; 10437 10438 struct mlx5_ifc_mpein_reg_bits { 10439 u8 reserved_at_0[0x2]; 10440 u8 depth[0x6]; 10441 u8 pcie_index[0x8]; 10442 u8 node[0x8]; 10443 u8 reserved_at_18[0x8]; 10444 10445 u8 capability_mask[0x20]; 10446 10447 u8 reserved_at_40[0x8]; 10448 u8 link_width_enabled[0x8]; 10449 u8 link_speed_enabled[0x10]; 10450 10451 u8 lane0_physical_position[0x8]; 10452 u8 link_width_active[0x8]; 10453 u8 link_speed_active[0x10]; 10454 10455 u8 num_of_pfs[0x10]; 10456 u8 num_of_vfs[0x10]; 10457 10458 u8 bdf0[0x10]; 10459 u8 reserved_at_b0[0x10]; 10460 10461 u8 max_read_request_size[0x4]; 10462 u8 max_payload_size[0x4]; 10463 u8 reserved_at_c8[0x5]; 10464 u8 pwr_status[0x3]; 10465 u8 port_type[0x4]; 10466 u8 reserved_at_d4[0xb]; 10467 u8 lane_reversal[0x1]; 10468 10469 u8 reserved_at_e0[0x14]; 10470 u8 pci_power[0xc]; 10471 10472 u8 reserved_at_100[0x20]; 10473 10474 u8 device_status[0x10]; 10475 u8 port_state[0x8]; 10476 u8 reserved_at_138[0x8]; 10477 10478 u8 reserved_at_140[0x10]; 10479 u8 receiver_detect_result[0x10]; 10480 10481 u8 reserved_at_160[0x20]; 10482 }; 10483 10484 struct mlx5_ifc_mpcnt_reg_bits { 10485 u8 reserved_at_0[0x8]; 10486 u8 pcie_index[0x8]; 10487 u8 reserved_at_10[0xa]; 10488 u8 grp[0x6]; 10489 10490 u8 clr[0x1]; 10491 u8 reserved_at_21[0x1f]; 10492 10493 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10494 }; 10495 10496 struct mlx5_ifc_ppad_reg_bits { 10497 u8 reserved_at_0[0x3]; 10498 u8 single_mac[0x1]; 10499 u8 reserved_at_4[0x4]; 10500 u8 local_port[0x8]; 10501 u8 mac_47_32[0x10]; 10502 10503 u8 mac_31_0[0x20]; 10504 10505 u8 reserved_at_40[0x40]; 10506 }; 10507 10508 struct mlx5_ifc_pmtu_reg_bits { 10509 u8 reserved_at_0[0x8]; 10510 u8 local_port[0x8]; 10511 u8 reserved_at_10[0x10]; 10512 10513 u8 max_mtu[0x10]; 10514 u8 reserved_at_30[0x10]; 10515 10516 u8 admin_mtu[0x10]; 10517 u8 reserved_at_50[0x10]; 10518 10519 u8 oper_mtu[0x10]; 10520 u8 reserved_at_70[0x10]; 10521 }; 10522 10523 struct mlx5_ifc_pmpr_reg_bits { 10524 u8 reserved_at_0[0x8]; 10525 u8 module[0x8]; 10526 u8 reserved_at_10[0x10]; 10527 10528 u8 reserved_at_20[0x18]; 10529 u8 attenuation_5g[0x8]; 10530 10531 u8 reserved_at_40[0x18]; 10532 u8 attenuation_7g[0x8]; 10533 10534 u8 reserved_at_60[0x18]; 10535 u8 attenuation_12g[0x8]; 10536 }; 10537 10538 struct mlx5_ifc_pmpe_reg_bits { 10539 u8 reserved_at_0[0x8]; 10540 u8 module[0x8]; 10541 u8 reserved_at_10[0xc]; 10542 u8 module_status[0x4]; 10543 10544 u8 reserved_at_20[0x60]; 10545 }; 10546 10547 struct mlx5_ifc_pmpc_reg_bits { 10548 u8 module_state_updated[32][0x8]; 10549 }; 10550 10551 struct mlx5_ifc_pmlpn_reg_bits { 10552 u8 reserved_at_0[0x4]; 10553 u8 mlpn_status[0x4]; 10554 u8 local_port[0x8]; 10555 u8 reserved_at_10[0x10]; 10556 10557 u8 e[0x1]; 10558 u8 reserved_at_21[0x1f]; 10559 }; 10560 10561 struct mlx5_ifc_pmlp_reg_bits { 10562 u8 rxtx[0x1]; 10563 u8 reserved_at_1[0x7]; 10564 u8 local_port[0x8]; 10565 u8 reserved_at_10[0x8]; 10566 u8 width[0x8]; 10567 10568 u8 lane0_module_mapping[0x20]; 10569 10570 u8 lane1_module_mapping[0x20]; 10571 10572 u8 lane2_module_mapping[0x20]; 10573 10574 u8 lane3_module_mapping[0x20]; 10575 10576 u8 reserved_at_a0[0x160]; 10577 }; 10578 10579 struct mlx5_ifc_pmaos_reg_bits { 10580 u8 reserved_at_0[0x8]; 10581 u8 module[0x8]; 10582 u8 reserved_at_10[0x4]; 10583 u8 admin_status[0x4]; 10584 u8 reserved_at_18[0x4]; 10585 u8 oper_status[0x4]; 10586 10587 u8 ase[0x1]; 10588 u8 ee[0x1]; 10589 u8 reserved_at_22[0x1c]; 10590 u8 e[0x2]; 10591 10592 u8 reserved_at_40[0x40]; 10593 }; 10594 10595 struct mlx5_ifc_plpc_reg_bits { 10596 u8 reserved_at_0[0x4]; 10597 u8 profile_id[0xc]; 10598 u8 reserved_at_10[0x4]; 10599 u8 proto_mask[0x4]; 10600 u8 reserved_at_18[0x8]; 10601 10602 u8 reserved_at_20[0x10]; 10603 u8 lane_speed[0x10]; 10604 10605 u8 reserved_at_40[0x17]; 10606 u8 lpbf[0x1]; 10607 u8 fec_mode_policy[0x8]; 10608 10609 u8 retransmission_capability[0x8]; 10610 u8 fec_mode_capability[0x18]; 10611 10612 u8 retransmission_support_admin[0x8]; 10613 u8 fec_mode_support_admin[0x18]; 10614 10615 u8 retransmission_request_admin[0x8]; 10616 u8 fec_mode_request_admin[0x18]; 10617 10618 u8 reserved_at_c0[0x80]; 10619 }; 10620 10621 struct mlx5_ifc_plib_reg_bits { 10622 u8 reserved_at_0[0x8]; 10623 u8 local_port[0x8]; 10624 u8 reserved_at_10[0x8]; 10625 u8 ib_port[0x8]; 10626 10627 u8 reserved_at_20[0x60]; 10628 }; 10629 10630 struct mlx5_ifc_plbf_reg_bits { 10631 u8 reserved_at_0[0x8]; 10632 u8 local_port[0x8]; 10633 u8 reserved_at_10[0xd]; 10634 u8 lbf_mode[0x3]; 10635 10636 u8 reserved_at_20[0x20]; 10637 }; 10638 10639 struct mlx5_ifc_pipg_reg_bits { 10640 u8 reserved_at_0[0x8]; 10641 u8 local_port[0x8]; 10642 u8 reserved_at_10[0x10]; 10643 10644 u8 dic[0x1]; 10645 u8 reserved_at_21[0x19]; 10646 u8 ipg[0x4]; 10647 u8 reserved_at_3e[0x2]; 10648 }; 10649 10650 struct mlx5_ifc_pifr_reg_bits { 10651 u8 reserved_at_0[0x8]; 10652 u8 local_port[0x8]; 10653 u8 reserved_at_10[0x10]; 10654 10655 u8 reserved_at_20[0xe0]; 10656 10657 u8 port_filter[8][0x20]; 10658 10659 u8 port_filter_update_en[8][0x20]; 10660 }; 10661 10662 enum { 10663 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10664 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10665 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10666 }; 10667 10668 struct mlx5_ifc_pfcc_reg_bits { 10669 u8 reserved_at_0[0x4]; 10670 u8 buf_ownership[0x2]; 10671 u8 reserved_at_6[0x2]; 10672 u8 local_port[0x8]; 10673 u8 reserved_at_10[0xa]; 10674 u8 cable_length_mask[0x1]; 10675 u8 ppan_mask_n[0x1]; 10676 u8 minor_stall_mask[0x1]; 10677 u8 critical_stall_mask[0x1]; 10678 u8 reserved_at_1e[0x2]; 10679 10680 u8 ppan[0x4]; 10681 u8 reserved_at_24[0x4]; 10682 u8 prio_mask_tx[0x8]; 10683 u8 reserved_at_30[0x8]; 10684 u8 prio_mask_rx[0x8]; 10685 10686 u8 pptx[0x1]; 10687 u8 aptx[0x1]; 10688 u8 pptx_mask_n[0x1]; 10689 u8 reserved_at_43[0x5]; 10690 u8 pfctx[0x8]; 10691 u8 reserved_at_50[0x10]; 10692 10693 u8 pprx[0x1]; 10694 u8 aprx[0x1]; 10695 u8 pprx_mask_n[0x1]; 10696 u8 reserved_at_63[0x5]; 10697 u8 pfcrx[0x8]; 10698 u8 reserved_at_70[0x10]; 10699 10700 u8 device_stall_minor_watermark[0x10]; 10701 u8 device_stall_critical_watermark[0x10]; 10702 10703 u8 reserved_at_a0[0x18]; 10704 u8 cable_length[0x8]; 10705 10706 u8 reserved_at_c0[0x40]; 10707 }; 10708 10709 struct mlx5_ifc_pelc_reg_bits { 10710 u8 op[0x4]; 10711 u8 reserved_at_4[0x4]; 10712 u8 local_port[0x8]; 10713 u8 reserved_at_10[0x10]; 10714 10715 u8 op_admin[0x8]; 10716 u8 op_capability[0x8]; 10717 u8 op_request[0x8]; 10718 u8 op_active[0x8]; 10719 10720 u8 admin[0x40]; 10721 10722 u8 capability[0x40]; 10723 10724 u8 request[0x40]; 10725 10726 u8 active[0x40]; 10727 10728 u8 reserved_at_140[0x80]; 10729 }; 10730 10731 struct mlx5_ifc_peir_reg_bits { 10732 u8 reserved_at_0[0x8]; 10733 u8 local_port[0x8]; 10734 u8 reserved_at_10[0x10]; 10735 10736 u8 reserved_at_20[0xc]; 10737 u8 error_count[0x4]; 10738 u8 reserved_at_30[0x10]; 10739 10740 u8 reserved_at_40[0xc]; 10741 u8 lane[0x4]; 10742 u8 reserved_at_50[0x8]; 10743 u8 error_type[0x8]; 10744 }; 10745 10746 struct mlx5_ifc_mpegc_reg_bits { 10747 u8 reserved_at_0[0x30]; 10748 u8 field_select[0x10]; 10749 10750 u8 tx_overflow_sense[0x1]; 10751 u8 mark_cqe[0x1]; 10752 u8 mark_cnp[0x1]; 10753 u8 reserved_at_43[0x1b]; 10754 u8 tx_lossy_overflow_oper[0x2]; 10755 10756 u8 reserved_at_60[0x100]; 10757 }; 10758 10759 struct mlx5_ifc_mpir_reg_bits { 10760 u8 sdm[0x1]; 10761 u8 reserved_at_1[0x1b]; 10762 u8 host_buses[0x4]; 10763 10764 u8 reserved_at_20[0x20]; 10765 10766 u8 local_port[0x8]; 10767 u8 reserved_at_28[0x18]; 10768 10769 u8 reserved_at_60[0x20]; 10770 }; 10771 10772 enum { 10773 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10774 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10775 }; 10776 10777 enum { 10778 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10779 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10780 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10781 }; 10782 10783 struct mlx5_ifc_mtutc_reg_bits { 10784 u8 reserved_at_0[0x5]; 10785 u8 freq_adj_units[0x3]; 10786 u8 reserved_at_8[0x3]; 10787 u8 log_max_freq_adjustment[0x5]; 10788 10789 u8 reserved_at_10[0xc]; 10790 u8 operation[0x4]; 10791 10792 u8 freq_adjustment[0x20]; 10793 10794 u8 reserved_at_40[0x40]; 10795 10796 u8 utc_sec[0x20]; 10797 10798 u8 reserved_at_a0[0x2]; 10799 u8 utc_nsec[0x1e]; 10800 10801 u8 time_adjustment[0x20]; 10802 }; 10803 10804 struct mlx5_ifc_pcam_enhanced_features_bits { 10805 u8 reserved_at_0[0x10]; 10806 u8 ppcnt_recovery_counters[0x1]; 10807 u8 reserved_at_11[0x7]; 10808 u8 cable_length[0x1]; 10809 u8 reserved_at_19[0x4]; 10810 u8 fec_200G_per_lane_in_pplm[0x1]; 10811 u8 reserved_at_1e[0x2a]; 10812 u8 fec_100G_per_lane_in_pplm[0x1]; 10813 u8 reserved_at_49[0xa]; 10814 u8 buffer_ownership[0x1]; 10815 u8 resereved_at_54[0x14]; 10816 u8 fec_50G_per_lane_in_pplm[0x1]; 10817 u8 reserved_at_69[0x4]; 10818 u8 rx_icrc_encapsulated_counter[0x1]; 10819 u8 reserved_at_6e[0x4]; 10820 u8 ptys_extended_ethernet[0x1]; 10821 u8 reserved_at_73[0x3]; 10822 u8 pfcc_mask[0x1]; 10823 u8 reserved_at_77[0x3]; 10824 u8 per_lane_error_counters[0x1]; 10825 u8 rx_buffer_fullness_counters[0x1]; 10826 u8 ptys_connector_type[0x1]; 10827 u8 reserved_at_7d[0x1]; 10828 u8 ppcnt_discard_group[0x1]; 10829 u8 ppcnt_statistical_group[0x1]; 10830 }; 10831 10832 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10833 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10834 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10835 10836 u8 port_access_reg_cap_mask_63[0x1]; 10837 u8 pphcr[0x1]; 10838 u8 port_access_reg_cap_mask_61_to_36[0x1a]; 10839 u8 pplm[0x1]; 10840 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10841 10842 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10843 u8 pbmc[0x1]; 10844 u8 pptb[0x1]; 10845 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10846 u8 ppcnt[0x1]; 10847 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10848 }; 10849 10850 struct mlx5_ifc_pcam_reg_bits { 10851 u8 reserved_at_0[0x8]; 10852 u8 feature_group[0x8]; 10853 u8 reserved_at_10[0x8]; 10854 u8 access_reg_group[0x8]; 10855 10856 u8 reserved_at_20[0x20]; 10857 10858 union { 10859 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10860 u8 reserved_at_0[0x80]; 10861 } port_access_reg_cap_mask; 10862 10863 u8 reserved_at_c0[0x80]; 10864 10865 union { 10866 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10867 u8 reserved_at_0[0x80]; 10868 } feature_cap_mask; 10869 10870 u8 reserved_at_1c0[0xc0]; 10871 }; 10872 10873 struct mlx5_ifc_mcam_enhanced_features_bits { 10874 u8 reserved_at_0[0x50]; 10875 u8 mtutc_freq_adj_units[0x1]; 10876 u8 mtutc_time_adjustment_extended_range[0x1]; 10877 u8 reserved_at_52[0xb]; 10878 u8 mcia_32dwords[0x1]; 10879 u8 out_pulse_duration_ns[0x1]; 10880 u8 npps_period[0x1]; 10881 u8 reserved_at_60[0xa]; 10882 u8 reset_state[0x1]; 10883 u8 ptpcyc2realtime_modify[0x1]; 10884 u8 reserved_at_6c[0x2]; 10885 u8 pci_status_and_power[0x1]; 10886 u8 reserved_at_6f[0x5]; 10887 u8 mark_tx_action_cnp[0x1]; 10888 u8 mark_tx_action_cqe[0x1]; 10889 u8 dynamic_tx_overflow[0x1]; 10890 u8 reserved_at_77[0x4]; 10891 u8 pcie_outbound_stalled[0x1]; 10892 u8 tx_overflow_buffer_pkt[0x1]; 10893 u8 mtpps_enh_out_per_adj[0x1]; 10894 u8 mtpps_fs[0x1]; 10895 u8 pcie_performance_group[0x1]; 10896 }; 10897 10898 struct mlx5_ifc_mcam_access_reg_bits { 10899 u8 reserved_at_0[0x1c]; 10900 u8 mcda[0x1]; 10901 u8 mcc[0x1]; 10902 u8 mcqi[0x1]; 10903 u8 mcqs[0x1]; 10904 10905 u8 regs_95_to_90[0x6]; 10906 u8 mpir[0x1]; 10907 u8 regs_88_to_87[0x2]; 10908 u8 mpegc[0x1]; 10909 u8 mtutc[0x1]; 10910 u8 regs_84_to_68[0x11]; 10911 u8 tracer_registers[0x4]; 10912 10913 u8 regs_63_to_46[0x12]; 10914 u8 mrtc[0x1]; 10915 u8 regs_44_to_41[0x4]; 10916 u8 mfrl[0x1]; 10917 u8 regs_39_to_32[0x8]; 10918 10919 u8 regs_31_to_11[0x15]; 10920 u8 mtmp[0x1]; 10921 u8 regs_9_to_0[0xa]; 10922 }; 10923 10924 struct mlx5_ifc_mcam_access_reg_bits1 { 10925 u8 regs_127_to_96[0x20]; 10926 10927 u8 regs_95_to_64[0x20]; 10928 10929 u8 regs_63_to_32[0x20]; 10930 10931 u8 regs_31_to_0[0x20]; 10932 }; 10933 10934 struct mlx5_ifc_mcam_access_reg_bits2 { 10935 u8 regs_127_to_99[0x1d]; 10936 u8 mirc[0x1]; 10937 u8 regs_97_to_96[0x2]; 10938 10939 u8 regs_95_to_87[0x09]; 10940 u8 synce_registers[0x2]; 10941 u8 regs_84_to_64[0x15]; 10942 10943 u8 regs_63_to_32[0x20]; 10944 10945 u8 regs_31_to_0[0x20]; 10946 }; 10947 10948 struct mlx5_ifc_mcam_access_reg_bits3 { 10949 u8 regs_127_to_96[0x20]; 10950 10951 u8 regs_95_to_64[0x20]; 10952 10953 u8 regs_63_to_32[0x20]; 10954 10955 u8 regs_31_to_3[0x1d]; 10956 u8 mrtcq[0x1]; 10957 u8 mtctr[0x1]; 10958 u8 mtptm[0x1]; 10959 }; 10960 10961 struct mlx5_ifc_mcam_reg_bits { 10962 u8 reserved_at_0[0x8]; 10963 u8 feature_group[0x8]; 10964 u8 reserved_at_10[0x8]; 10965 u8 access_reg_group[0x8]; 10966 10967 u8 reserved_at_20[0x20]; 10968 10969 union { 10970 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10971 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10972 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10973 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10974 u8 reserved_at_0[0x80]; 10975 } mng_access_reg_cap_mask; 10976 10977 u8 reserved_at_c0[0x80]; 10978 10979 union { 10980 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10981 u8 reserved_at_0[0x80]; 10982 } mng_feature_cap_mask; 10983 10984 u8 reserved_at_1c0[0x80]; 10985 }; 10986 10987 struct mlx5_ifc_qcam_access_reg_cap_mask { 10988 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10989 u8 qpdpm[0x1]; 10990 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10991 u8 qdpm[0x1]; 10992 u8 qpts[0x1]; 10993 u8 qcap[0x1]; 10994 u8 qcam_access_reg_cap_mask_0[0x1]; 10995 }; 10996 10997 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10998 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10999 u8 qpts_trust_both[0x1]; 11000 }; 11001 11002 struct mlx5_ifc_qcam_reg_bits { 11003 u8 reserved_at_0[0x8]; 11004 u8 feature_group[0x8]; 11005 u8 reserved_at_10[0x8]; 11006 u8 access_reg_group[0x8]; 11007 u8 reserved_at_20[0x20]; 11008 11009 union { 11010 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 11011 u8 reserved_at_0[0x80]; 11012 } qos_access_reg_cap_mask; 11013 11014 u8 reserved_at_c0[0x80]; 11015 11016 union { 11017 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 11018 u8 reserved_at_0[0x80]; 11019 } qos_feature_cap_mask; 11020 11021 u8 reserved_at_1c0[0x80]; 11022 }; 11023 11024 struct mlx5_ifc_core_dump_reg_bits { 11025 u8 reserved_at_0[0x18]; 11026 u8 core_dump_type[0x8]; 11027 11028 u8 reserved_at_20[0x30]; 11029 u8 vhca_id[0x10]; 11030 11031 u8 reserved_at_60[0x8]; 11032 u8 qpn[0x18]; 11033 u8 reserved_at_80[0x180]; 11034 }; 11035 11036 struct mlx5_ifc_pcap_reg_bits { 11037 u8 reserved_at_0[0x8]; 11038 u8 local_port[0x8]; 11039 u8 reserved_at_10[0x10]; 11040 11041 u8 port_capability_mask[4][0x20]; 11042 }; 11043 11044 struct mlx5_ifc_paos_reg_bits { 11045 u8 swid[0x8]; 11046 u8 local_port[0x8]; 11047 u8 reserved_at_10[0x4]; 11048 u8 admin_status[0x4]; 11049 u8 reserved_at_18[0x4]; 11050 u8 oper_status[0x4]; 11051 11052 u8 ase[0x1]; 11053 u8 ee[0x1]; 11054 u8 reserved_at_22[0x1c]; 11055 u8 e[0x2]; 11056 11057 u8 reserved_at_40[0x40]; 11058 }; 11059 11060 struct mlx5_ifc_pamp_reg_bits { 11061 u8 reserved_at_0[0x8]; 11062 u8 opamp_group[0x8]; 11063 u8 reserved_at_10[0xc]; 11064 u8 opamp_group_type[0x4]; 11065 11066 u8 start_index[0x10]; 11067 u8 reserved_at_30[0x4]; 11068 u8 num_of_indices[0xc]; 11069 11070 u8 index_data[18][0x10]; 11071 }; 11072 11073 struct mlx5_ifc_pcmr_reg_bits { 11074 u8 reserved_at_0[0x8]; 11075 u8 local_port[0x8]; 11076 u8 reserved_at_10[0x10]; 11077 11078 u8 entropy_force_cap[0x1]; 11079 u8 entropy_calc_cap[0x1]; 11080 u8 entropy_gre_calc_cap[0x1]; 11081 u8 reserved_at_23[0xf]; 11082 u8 rx_ts_over_crc_cap[0x1]; 11083 u8 reserved_at_33[0xb]; 11084 u8 fcs_cap[0x1]; 11085 u8 reserved_at_3f[0x1]; 11086 11087 u8 entropy_force[0x1]; 11088 u8 entropy_calc[0x1]; 11089 u8 entropy_gre_calc[0x1]; 11090 u8 reserved_at_43[0xf]; 11091 u8 rx_ts_over_crc[0x1]; 11092 u8 reserved_at_53[0xb]; 11093 u8 fcs_chk[0x1]; 11094 u8 reserved_at_5f[0x1]; 11095 }; 11096 11097 struct mlx5_ifc_lane_2_module_mapping_bits { 11098 u8 reserved_at_0[0x4]; 11099 u8 rx_lane[0x4]; 11100 u8 reserved_at_8[0x4]; 11101 u8 tx_lane[0x4]; 11102 u8 reserved_at_10[0x8]; 11103 u8 module[0x8]; 11104 }; 11105 11106 struct mlx5_ifc_bufferx_reg_bits { 11107 u8 reserved_at_0[0x6]; 11108 u8 lossy[0x1]; 11109 u8 epsb[0x1]; 11110 u8 reserved_at_8[0x8]; 11111 u8 size[0x10]; 11112 11113 u8 xoff_threshold[0x10]; 11114 u8 xon_threshold[0x10]; 11115 }; 11116 11117 struct mlx5_ifc_set_node_in_bits { 11118 u8 node_description[64][0x8]; 11119 }; 11120 11121 struct mlx5_ifc_register_power_settings_bits { 11122 u8 reserved_at_0[0x18]; 11123 u8 power_settings_level[0x8]; 11124 11125 u8 reserved_at_20[0x60]; 11126 }; 11127 11128 struct mlx5_ifc_register_host_endianness_bits { 11129 u8 he[0x1]; 11130 u8 reserved_at_1[0x1f]; 11131 11132 u8 reserved_at_20[0x60]; 11133 }; 11134 11135 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11136 u8 reserved_at_0[0x20]; 11137 11138 u8 mkey[0x20]; 11139 11140 u8 addressh_63_32[0x20]; 11141 11142 u8 addressl_31_0[0x20]; 11143 }; 11144 11145 struct mlx5_ifc_ud_adrs_vector_bits { 11146 u8 dc_key[0x40]; 11147 11148 u8 ext[0x1]; 11149 u8 reserved_at_41[0x7]; 11150 u8 destination_qp_dct[0x18]; 11151 11152 u8 static_rate[0x4]; 11153 u8 sl_eth_prio[0x4]; 11154 u8 fl[0x1]; 11155 u8 mlid[0x7]; 11156 u8 rlid_udp_sport[0x10]; 11157 11158 u8 reserved_at_80[0x20]; 11159 11160 u8 rmac_47_16[0x20]; 11161 11162 u8 rmac_15_0[0x10]; 11163 u8 tclass[0x8]; 11164 u8 hop_limit[0x8]; 11165 11166 u8 reserved_at_e0[0x1]; 11167 u8 grh[0x1]; 11168 u8 reserved_at_e2[0x2]; 11169 u8 src_addr_index[0x8]; 11170 u8 flow_label[0x14]; 11171 11172 u8 rgid_rip[16][0x8]; 11173 }; 11174 11175 struct mlx5_ifc_pages_req_event_bits { 11176 u8 reserved_at_0[0x10]; 11177 u8 function_id[0x10]; 11178 11179 u8 num_pages[0x20]; 11180 11181 u8 reserved_at_40[0xa0]; 11182 }; 11183 11184 struct mlx5_ifc_eqe_bits { 11185 u8 reserved_at_0[0x8]; 11186 u8 event_type[0x8]; 11187 u8 reserved_at_10[0x8]; 11188 u8 event_sub_type[0x8]; 11189 11190 u8 reserved_at_20[0xe0]; 11191 11192 union mlx5_ifc_event_auto_bits event_data; 11193 11194 u8 reserved_at_1e0[0x10]; 11195 u8 signature[0x8]; 11196 u8 reserved_at_1f8[0x7]; 11197 u8 owner[0x1]; 11198 }; 11199 11200 enum { 11201 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11202 }; 11203 11204 struct mlx5_ifc_cmd_queue_entry_bits { 11205 u8 type[0x8]; 11206 u8 reserved_at_8[0x18]; 11207 11208 u8 input_length[0x20]; 11209 11210 u8 input_mailbox_pointer_63_32[0x20]; 11211 11212 u8 input_mailbox_pointer_31_9[0x17]; 11213 u8 reserved_at_77[0x9]; 11214 11215 u8 command_input_inline_data[16][0x8]; 11216 11217 u8 command_output_inline_data[16][0x8]; 11218 11219 u8 output_mailbox_pointer_63_32[0x20]; 11220 11221 u8 output_mailbox_pointer_31_9[0x17]; 11222 u8 reserved_at_1b7[0x9]; 11223 11224 u8 output_length[0x20]; 11225 11226 u8 token[0x8]; 11227 u8 signature[0x8]; 11228 u8 reserved_at_1f0[0x8]; 11229 u8 status[0x7]; 11230 u8 ownership[0x1]; 11231 }; 11232 11233 struct mlx5_ifc_cmd_out_bits { 11234 u8 status[0x8]; 11235 u8 reserved_at_8[0x18]; 11236 11237 u8 syndrome[0x20]; 11238 11239 u8 command_output[0x20]; 11240 }; 11241 11242 struct mlx5_ifc_cmd_in_bits { 11243 u8 opcode[0x10]; 11244 u8 reserved_at_10[0x10]; 11245 11246 u8 reserved_at_20[0x10]; 11247 u8 op_mod[0x10]; 11248 11249 u8 command[][0x20]; 11250 }; 11251 11252 struct mlx5_ifc_cmd_if_box_bits { 11253 u8 mailbox_data[512][0x8]; 11254 11255 u8 reserved_at_1000[0x180]; 11256 11257 u8 next_pointer_63_32[0x20]; 11258 11259 u8 next_pointer_31_10[0x16]; 11260 u8 reserved_at_11b6[0xa]; 11261 11262 u8 block_number[0x20]; 11263 11264 u8 reserved_at_11e0[0x8]; 11265 u8 token[0x8]; 11266 u8 ctrl_signature[0x8]; 11267 u8 signature[0x8]; 11268 }; 11269 11270 struct mlx5_ifc_mtt_bits { 11271 u8 ptag_63_32[0x20]; 11272 11273 u8 ptag_31_8[0x18]; 11274 u8 reserved_at_38[0x6]; 11275 u8 wr_en[0x1]; 11276 u8 rd_en[0x1]; 11277 }; 11278 11279 struct mlx5_ifc_query_wol_rol_out_bits { 11280 u8 status[0x8]; 11281 u8 reserved_at_8[0x18]; 11282 11283 u8 syndrome[0x20]; 11284 11285 u8 reserved_at_40[0x10]; 11286 u8 rol_mode[0x8]; 11287 u8 wol_mode[0x8]; 11288 11289 u8 reserved_at_60[0x20]; 11290 }; 11291 11292 struct mlx5_ifc_query_wol_rol_in_bits { 11293 u8 opcode[0x10]; 11294 u8 reserved_at_10[0x10]; 11295 11296 u8 reserved_at_20[0x10]; 11297 u8 op_mod[0x10]; 11298 11299 u8 reserved_at_40[0x40]; 11300 }; 11301 11302 struct mlx5_ifc_set_wol_rol_out_bits { 11303 u8 status[0x8]; 11304 u8 reserved_at_8[0x18]; 11305 11306 u8 syndrome[0x20]; 11307 11308 u8 reserved_at_40[0x40]; 11309 }; 11310 11311 struct mlx5_ifc_set_wol_rol_in_bits { 11312 u8 opcode[0x10]; 11313 u8 reserved_at_10[0x10]; 11314 11315 u8 reserved_at_20[0x10]; 11316 u8 op_mod[0x10]; 11317 11318 u8 rol_mode_valid[0x1]; 11319 u8 wol_mode_valid[0x1]; 11320 u8 reserved_at_42[0xe]; 11321 u8 rol_mode[0x8]; 11322 u8 wol_mode[0x8]; 11323 11324 u8 reserved_at_60[0x20]; 11325 }; 11326 11327 enum { 11328 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11329 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11330 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11331 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11332 }; 11333 11334 enum { 11335 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11336 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11337 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11338 }; 11339 11340 enum { 11341 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11342 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11343 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11344 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11345 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11346 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11347 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11348 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11349 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11350 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11351 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11352 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11353 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11354 }; 11355 11356 struct mlx5_ifc_initial_seg_bits { 11357 u8 fw_rev_minor[0x10]; 11358 u8 fw_rev_major[0x10]; 11359 11360 u8 cmd_interface_rev[0x10]; 11361 u8 fw_rev_subminor[0x10]; 11362 11363 u8 reserved_at_40[0x40]; 11364 11365 u8 cmdq_phy_addr_63_32[0x20]; 11366 11367 u8 cmdq_phy_addr_31_12[0x14]; 11368 u8 reserved_at_b4[0x2]; 11369 u8 nic_interface[0x2]; 11370 u8 log_cmdq_size[0x4]; 11371 u8 log_cmdq_stride[0x4]; 11372 11373 u8 command_doorbell_vector[0x20]; 11374 11375 u8 reserved_at_e0[0xf00]; 11376 11377 u8 initializing[0x1]; 11378 u8 reserved_at_fe1[0x4]; 11379 u8 nic_interface_supported[0x3]; 11380 u8 embedded_cpu[0x1]; 11381 u8 reserved_at_fe9[0x17]; 11382 11383 struct mlx5_ifc_health_buffer_bits health_buffer; 11384 11385 u8 no_dram_nic_offset[0x20]; 11386 11387 u8 reserved_at_1220[0x6e40]; 11388 11389 u8 reserved_at_8060[0x1f]; 11390 u8 clear_int[0x1]; 11391 11392 u8 health_syndrome[0x8]; 11393 u8 health_counter[0x18]; 11394 11395 u8 reserved_at_80a0[0x17fc0]; 11396 }; 11397 11398 struct mlx5_ifc_mtpps_reg_bits { 11399 u8 reserved_at_0[0xc]; 11400 u8 cap_number_of_pps_pins[0x4]; 11401 u8 reserved_at_10[0x4]; 11402 u8 cap_max_num_of_pps_in_pins[0x4]; 11403 u8 reserved_at_18[0x4]; 11404 u8 cap_max_num_of_pps_out_pins[0x4]; 11405 11406 u8 reserved_at_20[0x13]; 11407 u8 cap_log_min_npps_period[0x5]; 11408 u8 reserved_at_38[0x3]; 11409 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11410 11411 u8 reserved_at_40[0x4]; 11412 u8 cap_pin_3_mode[0x4]; 11413 u8 reserved_at_48[0x4]; 11414 u8 cap_pin_2_mode[0x4]; 11415 u8 reserved_at_50[0x4]; 11416 u8 cap_pin_1_mode[0x4]; 11417 u8 reserved_at_58[0x4]; 11418 u8 cap_pin_0_mode[0x4]; 11419 11420 u8 reserved_at_60[0x4]; 11421 u8 cap_pin_7_mode[0x4]; 11422 u8 reserved_at_68[0x4]; 11423 u8 cap_pin_6_mode[0x4]; 11424 u8 reserved_at_70[0x4]; 11425 u8 cap_pin_5_mode[0x4]; 11426 u8 reserved_at_78[0x4]; 11427 u8 cap_pin_4_mode[0x4]; 11428 11429 u8 field_select[0x20]; 11430 u8 reserved_at_a0[0x20]; 11431 11432 u8 npps_period[0x40]; 11433 11434 u8 enable[0x1]; 11435 u8 reserved_at_101[0xb]; 11436 u8 pattern[0x4]; 11437 u8 reserved_at_110[0x4]; 11438 u8 pin_mode[0x4]; 11439 u8 pin[0x8]; 11440 11441 u8 reserved_at_120[0x2]; 11442 u8 out_pulse_duration_ns[0x1e]; 11443 11444 u8 time_stamp[0x40]; 11445 11446 u8 out_pulse_duration[0x10]; 11447 u8 out_periodic_adjustment[0x10]; 11448 u8 enhanced_out_periodic_adjustment[0x20]; 11449 11450 u8 reserved_at_1c0[0x20]; 11451 }; 11452 11453 struct mlx5_ifc_mtppse_reg_bits { 11454 u8 reserved_at_0[0x18]; 11455 u8 pin[0x8]; 11456 u8 event_arm[0x1]; 11457 u8 reserved_at_21[0x1b]; 11458 u8 event_generation_mode[0x4]; 11459 u8 reserved_at_40[0x40]; 11460 }; 11461 11462 struct mlx5_ifc_mcqs_reg_bits { 11463 u8 last_index_flag[0x1]; 11464 u8 reserved_at_1[0x7]; 11465 u8 fw_device[0x8]; 11466 u8 component_index[0x10]; 11467 11468 u8 reserved_at_20[0x10]; 11469 u8 identifier[0x10]; 11470 11471 u8 reserved_at_40[0x17]; 11472 u8 component_status[0x5]; 11473 u8 component_update_state[0x4]; 11474 11475 u8 last_update_state_changer_type[0x4]; 11476 u8 last_update_state_changer_host_id[0x4]; 11477 u8 reserved_at_68[0x18]; 11478 }; 11479 11480 struct mlx5_ifc_mcqi_cap_bits { 11481 u8 supported_info_bitmask[0x20]; 11482 11483 u8 component_size[0x20]; 11484 11485 u8 max_component_size[0x20]; 11486 11487 u8 log_mcda_word_size[0x4]; 11488 u8 reserved_at_64[0xc]; 11489 u8 mcda_max_write_size[0x10]; 11490 11491 u8 rd_en[0x1]; 11492 u8 reserved_at_81[0x1]; 11493 u8 match_chip_id[0x1]; 11494 u8 match_psid[0x1]; 11495 u8 check_user_timestamp[0x1]; 11496 u8 match_base_guid_mac[0x1]; 11497 u8 reserved_at_86[0x1a]; 11498 }; 11499 11500 struct mlx5_ifc_mcqi_version_bits { 11501 u8 reserved_at_0[0x2]; 11502 u8 build_time_valid[0x1]; 11503 u8 user_defined_time_valid[0x1]; 11504 u8 reserved_at_4[0x14]; 11505 u8 version_string_length[0x8]; 11506 11507 u8 version[0x20]; 11508 11509 u8 build_time[0x40]; 11510 11511 u8 user_defined_time[0x40]; 11512 11513 u8 build_tool_version[0x20]; 11514 11515 u8 reserved_at_e0[0x20]; 11516 11517 u8 version_string[92][0x8]; 11518 }; 11519 11520 struct mlx5_ifc_mcqi_activation_method_bits { 11521 u8 pending_server_ac_power_cycle[0x1]; 11522 u8 pending_server_dc_power_cycle[0x1]; 11523 u8 pending_server_reboot[0x1]; 11524 u8 pending_fw_reset[0x1]; 11525 u8 auto_activate[0x1]; 11526 u8 all_hosts_sync[0x1]; 11527 u8 device_hw_reset[0x1]; 11528 u8 reserved_at_7[0x19]; 11529 }; 11530 11531 union mlx5_ifc_mcqi_reg_data_bits { 11532 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11533 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11534 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11535 }; 11536 11537 struct mlx5_ifc_mcqi_reg_bits { 11538 u8 read_pending_component[0x1]; 11539 u8 reserved_at_1[0xf]; 11540 u8 component_index[0x10]; 11541 11542 u8 reserved_at_20[0x20]; 11543 11544 u8 reserved_at_40[0x1b]; 11545 u8 info_type[0x5]; 11546 11547 u8 info_size[0x20]; 11548 11549 u8 offset[0x20]; 11550 11551 u8 reserved_at_a0[0x10]; 11552 u8 data_size[0x10]; 11553 11554 union mlx5_ifc_mcqi_reg_data_bits data[]; 11555 }; 11556 11557 struct mlx5_ifc_mcc_reg_bits { 11558 u8 reserved_at_0[0x4]; 11559 u8 time_elapsed_since_last_cmd[0xc]; 11560 u8 reserved_at_10[0x8]; 11561 u8 instruction[0x8]; 11562 11563 u8 reserved_at_20[0x10]; 11564 u8 component_index[0x10]; 11565 11566 u8 reserved_at_40[0x8]; 11567 u8 update_handle[0x18]; 11568 11569 u8 handle_owner_type[0x4]; 11570 u8 handle_owner_host_id[0x4]; 11571 u8 reserved_at_68[0x1]; 11572 u8 control_progress[0x7]; 11573 u8 error_code[0x8]; 11574 u8 reserved_at_78[0x4]; 11575 u8 control_state[0x4]; 11576 11577 u8 component_size[0x20]; 11578 11579 u8 reserved_at_a0[0x60]; 11580 }; 11581 11582 struct mlx5_ifc_mcda_reg_bits { 11583 u8 reserved_at_0[0x8]; 11584 u8 update_handle[0x18]; 11585 11586 u8 offset[0x20]; 11587 11588 u8 reserved_at_40[0x10]; 11589 u8 size[0x10]; 11590 11591 u8 reserved_at_60[0x20]; 11592 11593 u8 data[][0x20]; 11594 }; 11595 11596 enum { 11597 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11598 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11599 }; 11600 11601 enum { 11602 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11603 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11604 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11605 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11606 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11607 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11608 }; 11609 11610 enum { 11611 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11612 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11613 }; 11614 11615 enum { 11616 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11617 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11618 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11619 }; 11620 11621 struct mlx5_ifc_mfrl_reg_bits { 11622 u8 reserved_at_0[0x20]; 11623 11624 u8 reserved_at_20[0x2]; 11625 u8 pci_sync_for_fw_update_start[0x1]; 11626 u8 pci_sync_for_fw_update_resp[0x2]; 11627 u8 rst_type_sel[0x3]; 11628 u8 pci_reset_req_method[0x3]; 11629 u8 reserved_at_2b[0x1]; 11630 u8 reset_state[0x4]; 11631 u8 reset_type[0x8]; 11632 u8 reset_level[0x8]; 11633 }; 11634 11635 struct mlx5_ifc_mirc_reg_bits { 11636 u8 reserved_at_0[0x18]; 11637 u8 status_code[0x8]; 11638 11639 u8 reserved_at_20[0x20]; 11640 }; 11641 11642 struct mlx5_ifc_pddr_monitor_opcode_bits { 11643 u8 reserved_at_0[0x10]; 11644 u8 monitor_opcode[0x10]; 11645 }; 11646 11647 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11648 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11649 u8 reserved_at_0[0x20]; 11650 }; 11651 11652 enum { 11653 /* Monitor opcodes */ 11654 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11655 }; 11656 11657 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11658 u8 reserved_at_0[0x10]; 11659 u8 group_opcode[0x10]; 11660 11661 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11662 11663 u8 reserved_at_40[0x20]; 11664 11665 u8 status_message[59][0x20]; 11666 }; 11667 11668 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11669 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11670 u8 reserved_at_0[0x7c0]; 11671 }; 11672 11673 enum { 11674 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11675 }; 11676 11677 struct mlx5_ifc_pddr_reg_bits { 11678 u8 reserved_at_0[0x8]; 11679 u8 local_port[0x8]; 11680 u8 pnat[0x2]; 11681 u8 reserved_at_12[0xe]; 11682 11683 u8 reserved_at_20[0x18]; 11684 u8 page_select[0x8]; 11685 11686 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11687 }; 11688 11689 struct mlx5_ifc_mrtc_reg_bits { 11690 u8 time_synced[0x1]; 11691 u8 reserved_at_1[0x1f]; 11692 11693 u8 reserved_at_20[0x20]; 11694 11695 u8 time_h[0x20]; 11696 11697 u8 time_l[0x20]; 11698 }; 11699 11700 struct mlx5_ifc_mtcap_reg_bits { 11701 u8 reserved_at_0[0x19]; 11702 u8 sensor_count[0x7]; 11703 11704 u8 reserved_at_20[0x20]; 11705 11706 u8 sensor_map[0x40]; 11707 }; 11708 11709 struct mlx5_ifc_mtmp_reg_bits { 11710 u8 reserved_at_0[0x14]; 11711 u8 sensor_index[0xc]; 11712 11713 u8 reserved_at_20[0x10]; 11714 u8 temperature[0x10]; 11715 11716 u8 mte[0x1]; 11717 u8 mtr[0x1]; 11718 u8 reserved_at_42[0xe]; 11719 u8 max_temperature[0x10]; 11720 11721 u8 tee[0x2]; 11722 u8 reserved_at_62[0xe]; 11723 u8 temp_threshold_hi[0x10]; 11724 11725 u8 reserved_at_80[0x10]; 11726 u8 temp_threshold_lo[0x10]; 11727 11728 u8 reserved_at_a0[0x20]; 11729 11730 u8 sensor_name_hi[0x20]; 11731 u8 sensor_name_lo[0x20]; 11732 }; 11733 11734 struct mlx5_ifc_mtptm_reg_bits { 11735 u8 reserved_at_0[0x10]; 11736 u8 psta[0x1]; 11737 u8 reserved_at_11[0xf]; 11738 11739 u8 reserved_at_20[0x60]; 11740 }; 11741 11742 enum { 11743 MLX5_MTCTR_REQUEST_NOP = 0x0, 11744 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11745 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11746 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11747 }; 11748 11749 struct mlx5_ifc_mtctr_reg_bits { 11750 u8 first_clock_timestamp_request[0x8]; 11751 u8 second_clock_timestamp_request[0x8]; 11752 u8 reserved_at_10[0x10]; 11753 11754 u8 first_clock_valid[0x1]; 11755 u8 second_clock_valid[0x1]; 11756 u8 reserved_at_22[0x1e]; 11757 11758 u8 first_clock_timestamp[0x40]; 11759 u8 second_clock_timestamp[0x40]; 11760 }; 11761 11762 struct mlx5_ifc_bin_range_layout_bits { 11763 u8 reserved_at_0[0xa]; 11764 u8 high_val[0x6]; 11765 u8 reserved_at_10[0xa]; 11766 u8 low_val[0x6]; 11767 }; 11768 11769 struct mlx5_ifc_pphcr_reg_bits { 11770 u8 active_hist_type[0x4]; 11771 u8 reserved_at_4[0x4]; 11772 u8 local_port[0x8]; 11773 u8 reserved_at_10[0x10]; 11774 11775 u8 reserved_at_20[0x8]; 11776 u8 num_of_bins[0x8]; 11777 u8 reserved_at_30[0x10]; 11778 11779 u8 reserved_at_40[0x40]; 11780 11781 struct mlx5_ifc_bin_range_layout_bits bin_range[16]; 11782 }; 11783 11784 union mlx5_ifc_ports_control_registers_document_bits { 11785 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11786 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11787 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11788 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11789 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11790 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11791 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11792 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11793 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11794 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11795 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11796 struct mlx5_ifc_paos_reg_bits paos_reg; 11797 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11798 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11799 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11800 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11801 struct mlx5_ifc_peir_reg_bits peir_reg; 11802 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11803 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11804 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11805 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11806 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11807 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11808 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11809 struct mlx5_ifc_plib_reg_bits plib_reg; 11810 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11811 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11812 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11813 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11814 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11815 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11816 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11817 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11818 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11819 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11820 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11821 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11822 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11823 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11824 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11825 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11826 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11827 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11828 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11829 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11830 struct mlx5_ifc_pude_reg_bits pude_reg; 11831 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11832 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11833 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11834 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11835 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11836 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11837 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11838 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11839 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11840 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11841 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11842 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11843 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11844 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11845 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11846 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11847 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11848 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11849 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11850 struct mlx5_ifc_pphcr_reg_bits pphcr_reg; 11851 u8 reserved_at_0[0x60e0]; 11852 }; 11853 11854 union mlx5_ifc_debug_enhancements_document_bits { 11855 struct mlx5_ifc_health_buffer_bits health_buffer; 11856 u8 reserved_at_0[0x200]; 11857 }; 11858 11859 union mlx5_ifc_uplink_pci_interface_document_bits { 11860 struct mlx5_ifc_initial_seg_bits initial_seg; 11861 u8 reserved_at_0[0x20060]; 11862 }; 11863 11864 struct mlx5_ifc_set_flow_table_root_out_bits { 11865 u8 status[0x8]; 11866 u8 reserved_at_8[0x18]; 11867 11868 u8 syndrome[0x20]; 11869 11870 u8 reserved_at_40[0x40]; 11871 }; 11872 11873 struct mlx5_ifc_set_flow_table_root_in_bits { 11874 u8 opcode[0x10]; 11875 u8 reserved_at_10[0x10]; 11876 11877 u8 reserved_at_20[0x10]; 11878 u8 op_mod[0x10]; 11879 11880 u8 other_vport[0x1]; 11881 u8 reserved_at_41[0xf]; 11882 u8 vport_number[0x10]; 11883 11884 u8 reserved_at_60[0x20]; 11885 11886 u8 table_type[0x8]; 11887 u8 reserved_at_88[0x7]; 11888 u8 table_of_other_vport[0x1]; 11889 u8 table_vport_number[0x10]; 11890 11891 u8 reserved_at_a0[0x8]; 11892 u8 table_id[0x18]; 11893 11894 u8 reserved_at_c0[0x8]; 11895 u8 underlay_qpn[0x18]; 11896 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11897 u8 reserved_at_e1[0xf]; 11898 u8 table_eswitch_owner_vhca_id[0x10]; 11899 u8 reserved_at_100[0x100]; 11900 }; 11901 11902 enum { 11903 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11904 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11905 }; 11906 11907 struct mlx5_ifc_modify_flow_table_out_bits { 11908 u8 status[0x8]; 11909 u8 reserved_at_8[0x18]; 11910 11911 u8 syndrome[0x20]; 11912 11913 u8 reserved_at_40[0x40]; 11914 }; 11915 11916 struct mlx5_ifc_modify_flow_table_in_bits { 11917 u8 opcode[0x10]; 11918 u8 reserved_at_10[0x10]; 11919 11920 u8 reserved_at_20[0x10]; 11921 u8 op_mod[0x10]; 11922 11923 u8 other_vport[0x1]; 11924 u8 reserved_at_41[0xf]; 11925 u8 vport_number[0x10]; 11926 11927 u8 reserved_at_60[0x10]; 11928 u8 modify_field_select[0x10]; 11929 11930 u8 table_type[0x8]; 11931 u8 reserved_at_88[0x18]; 11932 11933 u8 reserved_at_a0[0x8]; 11934 u8 table_id[0x18]; 11935 11936 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11937 }; 11938 11939 struct mlx5_ifc_ets_tcn_config_reg_bits { 11940 u8 g[0x1]; 11941 u8 b[0x1]; 11942 u8 r[0x1]; 11943 u8 reserved_at_3[0x9]; 11944 u8 group[0x4]; 11945 u8 reserved_at_10[0x9]; 11946 u8 bw_allocation[0x7]; 11947 11948 u8 reserved_at_20[0xc]; 11949 u8 max_bw_units[0x4]; 11950 u8 reserved_at_30[0x8]; 11951 u8 max_bw_value[0x8]; 11952 }; 11953 11954 struct mlx5_ifc_ets_global_config_reg_bits { 11955 u8 reserved_at_0[0x2]; 11956 u8 r[0x1]; 11957 u8 reserved_at_3[0x1d]; 11958 11959 u8 reserved_at_20[0xc]; 11960 u8 max_bw_units[0x4]; 11961 u8 reserved_at_30[0x8]; 11962 u8 max_bw_value[0x8]; 11963 }; 11964 11965 struct mlx5_ifc_qetc_reg_bits { 11966 u8 reserved_at_0[0x8]; 11967 u8 port_number[0x8]; 11968 u8 reserved_at_10[0x30]; 11969 11970 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11971 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11972 }; 11973 11974 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11975 u8 e[0x1]; 11976 u8 reserved_at_01[0x0b]; 11977 u8 prio[0x04]; 11978 }; 11979 11980 struct mlx5_ifc_qpdpm_reg_bits { 11981 u8 reserved_at_0[0x8]; 11982 u8 local_port[0x8]; 11983 u8 reserved_at_10[0x10]; 11984 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11985 }; 11986 11987 struct mlx5_ifc_qpts_reg_bits { 11988 u8 reserved_at_0[0x8]; 11989 u8 local_port[0x8]; 11990 u8 reserved_at_10[0x2d]; 11991 u8 trust_state[0x3]; 11992 }; 11993 11994 struct mlx5_ifc_pptb_reg_bits { 11995 u8 reserved_at_0[0x2]; 11996 u8 mm[0x2]; 11997 u8 reserved_at_4[0x4]; 11998 u8 local_port[0x8]; 11999 u8 reserved_at_10[0x6]; 12000 u8 cm[0x1]; 12001 u8 um[0x1]; 12002 u8 pm[0x8]; 12003 12004 u8 prio_x_buff[0x20]; 12005 12006 u8 pm_msb[0x8]; 12007 u8 reserved_at_48[0x10]; 12008 u8 ctrl_buff[0x4]; 12009 u8 untagged_buff[0x4]; 12010 }; 12011 12012 struct mlx5_ifc_sbcam_reg_bits { 12013 u8 reserved_at_0[0x8]; 12014 u8 feature_group[0x8]; 12015 u8 reserved_at_10[0x8]; 12016 u8 access_reg_group[0x8]; 12017 12018 u8 reserved_at_20[0x20]; 12019 12020 u8 sb_access_reg_cap_mask[4][0x20]; 12021 12022 u8 reserved_at_c0[0x80]; 12023 12024 u8 sb_feature_cap_mask[4][0x20]; 12025 12026 u8 reserved_at_1c0[0x40]; 12027 12028 u8 cap_total_buffer_size[0x20]; 12029 12030 u8 cap_cell_size[0x10]; 12031 u8 cap_max_pg_buffers[0x8]; 12032 u8 cap_num_pool_supported[0x8]; 12033 12034 u8 reserved_at_240[0x8]; 12035 u8 cap_sbsr_stat_size[0x8]; 12036 u8 cap_max_tclass_data[0x8]; 12037 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 12038 }; 12039 12040 struct mlx5_ifc_pbmc_reg_bits { 12041 u8 reserved_at_0[0x8]; 12042 u8 local_port[0x8]; 12043 u8 reserved_at_10[0x10]; 12044 12045 u8 xoff_timer_value[0x10]; 12046 u8 xoff_refresh[0x10]; 12047 12048 u8 reserved_at_40[0x9]; 12049 u8 fullness_threshold[0x7]; 12050 u8 port_buffer_size[0x10]; 12051 12052 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 12053 12054 u8 reserved_at_2e0[0x80]; 12055 }; 12056 12057 struct mlx5_ifc_sbpr_reg_bits { 12058 u8 desc[0x1]; 12059 u8 snap[0x1]; 12060 u8 reserved_at_2[0x4]; 12061 u8 dir[0x2]; 12062 u8 reserved_at_8[0x14]; 12063 u8 pool[0x4]; 12064 12065 u8 infi_size[0x1]; 12066 u8 reserved_at_21[0x7]; 12067 u8 size[0x18]; 12068 12069 u8 reserved_at_40[0x1c]; 12070 u8 mode[0x4]; 12071 12072 u8 reserved_at_60[0x8]; 12073 u8 buff_occupancy[0x18]; 12074 12075 u8 clr[0x1]; 12076 u8 reserved_at_81[0x7]; 12077 u8 max_buff_occupancy[0x18]; 12078 12079 u8 reserved_at_a0[0x8]; 12080 u8 ext_buff_occupancy[0x18]; 12081 }; 12082 12083 struct mlx5_ifc_sbcm_reg_bits { 12084 u8 desc[0x1]; 12085 u8 snap[0x1]; 12086 u8 reserved_at_2[0x6]; 12087 u8 local_port[0x8]; 12088 u8 pnat[0x2]; 12089 u8 pg_buff[0x6]; 12090 u8 reserved_at_18[0x6]; 12091 u8 dir[0x2]; 12092 12093 u8 reserved_at_20[0x1f]; 12094 u8 exc[0x1]; 12095 12096 u8 reserved_at_40[0x40]; 12097 12098 u8 reserved_at_80[0x8]; 12099 u8 buff_occupancy[0x18]; 12100 12101 u8 clr[0x1]; 12102 u8 reserved_at_a1[0x7]; 12103 u8 max_buff_occupancy[0x18]; 12104 12105 u8 reserved_at_c0[0x8]; 12106 u8 min_buff[0x18]; 12107 12108 u8 infi_max[0x1]; 12109 u8 reserved_at_e1[0x7]; 12110 u8 max_buff[0x18]; 12111 12112 u8 reserved_at_100[0x20]; 12113 12114 u8 reserved_at_120[0x1c]; 12115 u8 pool[0x4]; 12116 }; 12117 12118 struct mlx5_ifc_qtct_reg_bits { 12119 u8 reserved_at_0[0x8]; 12120 u8 port_number[0x8]; 12121 u8 reserved_at_10[0xd]; 12122 u8 prio[0x3]; 12123 12124 u8 reserved_at_20[0x1d]; 12125 u8 tclass[0x3]; 12126 }; 12127 12128 struct mlx5_ifc_mcia_reg_bits { 12129 u8 l[0x1]; 12130 u8 reserved_at_1[0x7]; 12131 u8 module[0x8]; 12132 u8 reserved_at_10[0x8]; 12133 u8 status[0x8]; 12134 12135 u8 i2c_device_address[0x8]; 12136 u8 page_number[0x8]; 12137 u8 device_address[0x10]; 12138 12139 u8 reserved_at_40[0x10]; 12140 u8 size[0x10]; 12141 12142 u8 reserved_at_60[0x20]; 12143 12144 u8 dword_0[0x20]; 12145 u8 dword_1[0x20]; 12146 u8 dword_2[0x20]; 12147 u8 dword_3[0x20]; 12148 u8 dword_4[0x20]; 12149 u8 dword_5[0x20]; 12150 u8 dword_6[0x20]; 12151 u8 dword_7[0x20]; 12152 u8 dword_8[0x20]; 12153 u8 dword_9[0x20]; 12154 u8 dword_10[0x20]; 12155 u8 dword_11[0x20]; 12156 }; 12157 12158 struct mlx5_ifc_dcbx_param_bits { 12159 u8 dcbx_cee_cap[0x1]; 12160 u8 dcbx_ieee_cap[0x1]; 12161 u8 dcbx_standby_cap[0x1]; 12162 u8 reserved_at_3[0x5]; 12163 u8 port_number[0x8]; 12164 u8 reserved_at_10[0xa]; 12165 u8 max_application_table_size[6]; 12166 u8 reserved_at_20[0x15]; 12167 u8 version_oper[0x3]; 12168 u8 reserved_at_38[5]; 12169 u8 version_admin[0x3]; 12170 u8 willing_admin[0x1]; 12171 u8 reserved_at_41[0x3]; 12172 u8 pfc_cap_oper[0x4]; 12173 u8 reserved_at_48[0x4]; 12174 u8 pfc_cap_admin[0x4]; 12175 u8 reserved_at_50[0x4]; 12176 u8 num_of_tc_oper[0x4]; 12177 u8 reserved_at_58[0x4]; 12178 u8 num_of_tc_admin[0x4]; 12179 u8 remote_willing[0x1]; 12180 u8 reserved_at_61[3]; 12181 u8 remote_pfc_cap[4]; 12182 u8 reserved_at_68[0x14]; 12183 u8 remote_num_of_tc[0x4]; 12184 u8 reserved_at_80[0x18]; 12185 u8 error[0x8]; 12186 u8 reserved_at_a0[0x160]; 12187 }; 12188 12189 enum { 12190 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12191 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12192 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12193 }; 12194 12195 struct mlx5_ifc_lagc_bits { 12196 u8 fdb_selection_mode[0x1]; 12197 u8 reserved_at_1[0x14]; 12198 u8 port_select_mode[0x3]; 12199 u8 reserved_at_18[0x5]; 12200 u8 lag_state[0x3]; 12201 12202 u8 reserved_at_20[0xc]; 12203 u8 active_port[0x4]; 12204 u8 reserved_at_30[0x4]; 12205 u8 tx_remap_affinity_2[0x4]; 12206 u8 reserved_at_38[0x4]; 12207 u8 tx_remap_affinity_1[0x4]; 12208 }; 12209 12210 struct mlx5_ifc_create_lag_out_bits { 12211 u8 status[0x8]; 12212 u8 reserved_at_8[0x18]; 12213 12214 u8 syndrome[0x20]; 12215 12216 u8 reserved_at_40[0x40]; 12217 }; 12218 12219 struct mlx5_ifc_create_lag_in_bits { 12220 u8 opcode[0x10]; 12221 u8 reserved_at_10[0x10]; 12222 12223 u8 reserved_at_20[0x10]; 12224 u8 op_mod[0x10]; 12225 12226 struct mlx5_ifc_lagc_bits ctx; 12227 }; 12228 12229 struct mlx5_ifc_modify_lag_out_bits { 12230 u8 status[0x8]; 12231 u8 reserved_at_8[0x18]; 12232 12233 u8 syndrome[0x20]; 12234 12235 u8 reserved_at_40[0x40]; 12236 }; 12237 12238 struct mlx5_ifc_modify_lag_in_bits { 12239 u8 opcode[0x10]; 12240 u8 reserved_at_10[0x10]; 12241 12242 u8 reserved_at_20[0x10]; 12243 u8 op_mod[0x10]; 12244 12245 u8 reserved_at_40[0x20]; 12246 u8 field_select[0x20]; 12247 12248 struct mlx5_ifc_lagc_bits ctx; 12249 }; 12250 12251 struct mlx5_ifc_query_lag_out_bits { 12252 u8 status[0x8]; 12253 u8 reserved_at_8[0x18]; 12254 12255 u8 syndrome[0x20]; 12256 12257 struct mlx5_ifc_lagc_bits ctx; 12258 }; 12259 12260 struct mlx5_ifc_query_lag_in_bits { 12261 u8 opcode[0x10]; 12262 u8 reserved_at_10[0x10]; 12263 12264 u8 reserved_at_20[0x10]; 12265 u8 op_mod[0x10]; 12266 12267 u8 reserved_at_40[0x40]; 12268 }; 12269 12270 struct mlx5_ifc_destroy_lag_out_bits { 12271 u8 status[0x8]; 12272 u8 reserved_at_8[0x18]; 12273 12274 u8 syndrome[0x20]; 12275 12276 u8 reserved_at_40[0x40]; 12277 }; 12278 12279 struct mlx5_ifc_destroy_lag_in_bits { 12280 u8 opcode[0x10]; 12281 u8 reserved_at_10[0x10]; 12282 12283 u8 reserved_at_20[0x10]; 12284 u8 op_mod[0x10]; 12285 12286 u8 reserved_at_40[0x40]; 12287 }; 12288 12289 struct mlx5_ifc_create_vport_lag_out_bits { 12290 u8 status[0x8]; 12291 u8 reserved_at_8[0x18]; 12292 12293 u8 syndrome[0x20]; 12294 12295 u8 reserved_at_40[0x40]; 12296 }; 12297 12298 struct mlx5_ifc_create_vport_lag_in_bits { 12299 u8 opcode[0x10]; 12300 u8 reserved_at_10[0x10]; 12301 12302 u8 reserved_at_20[0x10]; 12303 u8 op_mod[0x10]; 12304 12305 u8 reserved_at_40[0x40]; 12306 }; 12307 12308 struct mlx5_ifc_destroy_vport_lag_out_bits { 12309 u8 status[0x8]; 12310 u8 reserved_at_8[0x18]; 12311 12312 u8 syndrome[0x20]; 12313 12314 u8 reserved_at_40[0x40]; 12315 }; 12316 12317 struct mlx5_ifc_destroy_vport_lag_in_bits { 12318 u8 opcode[0x10]; 12319 u8 reserved_at_10[0x10]; 12320 12321 u8 reserved_at_20[0x10]; 12322 u8 op_mod[0x10]; 12323 12324 u8 reserved_at_40[0x40]; 12325 }; 12326 12327 enum { 12328 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12329 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12330 }; 12331 12332 struct mlx5_ifc_modify_memic_in_bits { 12333 u8 opcode[0x10]; 12334 u8 uid[0x10]; 12335 12336 u8 reserved_at_20[0x10]; 12337 u8 op_mod[0x10]; 12338 12339 u8 reserved_at_40[0x20]; 12340 12341 u8 reserved_at_60[0x18]; 12342 u8 memic_operation_type[0x8]; 12343 12344 u8 memic_start_addr[0x40]; 12345 12346 u8 reserved_at_c0[0x140]; 12347 }; 12348 12349 struct mlx5_ifc_modify_memic_out_bits { 12350 u8 status[0x8]; 12351 u8 reserved_at_8[0x18]; 12352 12353 u8 syndrome[0x20]; 12354 12355 u8 reserved_at_40[0x40]; 12356 12357 u8 memic_operation_addr[0x40]; 12358 12359 u8 reserved_at_c0[0x140]; 12360 }; 12361 12362 struct mlx5_ifc_alloc_memic_in_bits { 12363 u8 opcode[0x10]; 12364 u8 reserved_at_10[0x10]; 12365 12366 u8 reserved_at_20[0x10]; 12367 u8 op_mod[0x10]; 12368 12369 u8 reserved_at_30[0x20]; 12370 12371 u8 reserved_at_40[0x18]; 12372 u8 log_memic_addr_alignment[0x8]; 12373 12374 u8 range_start_addr[0x40]; 12375 12376 u8 range_size[0x20]; 12377 12378 u8 memic_size[0x20]; 12379 }; 12380 12381 struct mlx5_ifc_alloc_memic_out_bits { 12382 u8 status[0x8]; 12383 u8 reserved_at_8[0x18]; 12384 12385 u8 syndrome[0x20]; 12386 12387 u8 memic_start_addr[0x40]; 12388 }; 12389 12390 struct mlx5_ifc_dealloc_memic_in_bits { 12391 u8 opcode[0x10]; 12392 u8 reserved_at_10[0x10]; 12393 12394 u8 reserved_at_20[0x10]; 12395 u8 op_mod[0x10]; 12396 12397 u8 reserved_at_40[0x40]; 12398 12399 u8 memic_start_addr[0x40]; 12400 12401 u8 memic_size[0x20]; 12402 12403 u8 reserved_at_e0[0x20]; 12404 }; 12405 12406 struct mlx5_ifc_dealloc_memic_out_bits { 12407 u8 status[0x8]; 12408 u8 reserved_at_8[0x18]; 12409 12410 u8 syndrome[0x20]; 12411 12412 u8 reserved_at_40[0x40]; 12413 }; 12414 12415 struct mlx5_ifc_umem_bits { 12416 u8 reserved_at_0[0x80]; 12417 12418 u8 ats[0x1]; 12419 u8 reserved_at_81[0x1a]; 12420 u8 log_page_size[0x5]; 12421 12422 u8 page_offset[0x20]; 12423 12424 u8 num_of_mtt[0x40]; 12425 12426 struct mlx5_ifc_mtt_bits mtt[]; 12427 }; 12428 12429 struct mlx5_ifc_uctx_bits { 12430 u8 cap[0x20]; 12431 12432 u8 reserved_at_20[0x160]; 12433 }; 12434 12435 struct mlx5_ifc_sw_icm_bits { 12436 u8 modify_field_select[0x40]; 12437 12438 u8 reserved_at_40[0x18]; 12439 u8 log_sw_icm_size[0x8]; 12440 12441 u8 reserved_at_60[0x20]; 12442 12443 u8 sw_icm_start_addr[0x40]; 12444 12445 u8 reserved_at_c0[0x140]; 12446 }; 12447 12448 struct mlx5_ifc_geneve_tlv_option_bits { 12449 u8 modify_field_select[0x40]; 12450 12451 u8 reserved_at_40[0x18]; 12452 u8 geneve_option_fte_index[0x8]; 12453 12454 u8 option_class[0x10]; 12455 u8 option_type[0x8]; 12456 u8 reserved_at_78[0x3]; 12457 u8 option_data_length[0x5]; 12458 12459 u8 reserved_at_80[0x180]; 12460 }; 12461 12462 struct mlx5_ifc_create_umem_in_bits { 12463 u8 opcode[0x10]; 12464 u8 uid[0x10]; 12465 12466 u8 reserved_at_20[0x10]; 12467 u8 op_mod[0x10]; 12468 12469 u8 reserved_at_40[0x40]; 12470 12471 struct mlx5_ifc_umem_bits umem; 12472 }; 12473 12474 struct mlx5_ifc_create_umem_out_bits { 12475 u8 status[0x8]; 12476 u8 reserved_at_8[0x18]; 12477 12478 u8 syndrome[0x20]; 12479 12480 u8 reserved_at_40[0x8]; 12481 u8 umem_id[0x18]; 12482 12483 u8 reserved_at_60[0x20]; 12484 }; 12485 12486 struct mlx5_ifc_destroy_umem_in_bits { 12487 u8 opcode[0x10]; 12488 u8 uid[0x10]; 12489 12490 u8 reserved_at_20[0x10]; 12491 u8 op_mod[0x10]; 12492 12493 u8 reserved_at_40[0x8]; 12494 u8 umem_id[0x18]; 12495 12496 u8 reserved_at_60[0x20]; 12497 }; 12498 12499 struct mlx5_ifc_destroy_umem_out_bits { 12500 u8 status[0x8]; 12501 u8 reserved_at_8[0x18]; 12502 12503 u8 syndrome[0x20]; 12504 12505 u8 reserved_at_40[0x40]; 12506 }; 12507 12508 struct mlx5_ifc_create_uctx_in_bits { 12509 u8 opcode[0x10]; 12510 u8 reserved_at_10[0x10]; 12511 12512 u8 reserved_at_20[0x10]; 12513 u8 op_mod[0x10]; 12514 12515 u8 reserved_at_40[0x40]; 12516 12517 struct mlx5_ifc_uctx_bits uctx; 12518 }; 12519 12520 struct mlx5_ifc_create_uctx_out_bits { 12521 u8 status[0x8]; 12522 u8 reserved_at_8[0x18]; 12523 12524 u8 syndrome[0x20]; 12525 12526 u8 reserved_at_40[0x10]; 12527 u8 uid[0x10]; 12528 12529 u8 reserved_at_60[0x20]; 12530 }; 12531 12532 struct mlx5_ifc_destroy_uctx_in_bits { 12533 u8 opcode[0x10]; 12534 u8 reserved_at_10[0x10]; 12535 12536 u8 reserved_at_20[0x10]; 12537 u8 op_mod[0x10]; 12538 12539 u8 reserved_at_40[0x10]; 12540 u8 uid[0x10]; 12541 12542 u8 reserved_at_60[0x20]; 12543 }; 12544 12545 struct mlx5_ifc_destroy_uctx_out_bits { 12546 u8 status[0x8]; 12547 u8 reserved_at_8[0x18]; 12548 12549 u8 syndrome[0x20]; 12550 12551 u8 reserved_at_40[0x40]; 12552 }; 12553 12554 struct mlx5_ifc_create_sw_icm_in_bits { 12555 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12556 struct mlx5_ifc_sw_icm_bits sw_icm; 12557 }; 12558 12559 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12560 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12561 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12562 }; 12563 12564 struct mlx5_ifc_mtrc_string_db_param_bits { 12565 u8 string_db_base_address[0x20]; 12566 12567 u8 reserved_at_20[0x8]; 12568 u8 string_db_size[0x18]; 12569 }; 12570 12571 struct mlx5_ifc_mtrc_cap_bits { 12572 u8 trace_owner[0x1]; 12573 u8 trace_to_memory[0x1]; 12574 u8 reserved_at_2[0x4]; 12575 u8 trc_ver[0x2]; 12576 u8 reserved_at_8[0x14]; 12577 u8 num_string_db[0x4]; 12578 12579 u8 first_string_trace[0x8]; 12580 u8 num_string_trace[0x8]; 12581 u8 reserved_at_30[0x28]; 12582 12583 u8 log_max_trace_buffer_size[0x8]; 12584 12585 u8 reserved_at_60[0x20]; 12586 12587 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12588 12589 u8 reserved_at_280[0x180]; 12590 }; 12591 12592 struct mlx5_ifc_mtrc_conf_bits { 12593 u8 reserved_at_0[0x1c]; 12594 u8 trace_mode[0x4]; 12595 u8 reserved_at_20[0x18]; 12596 u8 log_trace_buffer_size[0x8]; 12597 u8 trace_mkey[0x20]; 12598 u8 reserved_at_60[0x3a0]; 12599 }; 12600 12601 struct mlx5_ifc_mtrc_stdb_bits { 12602 u8 string_db_index[0x4]; 12603 u8 reserved_at_4[0x4]; 12604 u8 read_size[0x18]; 12605 u8 start_offset[0x20]; 12606 u8 string_db_data[]; 12607 }; 12608 12609 struct mlx5_ifc_mtrc_ctrl_bits { 12610 u8 trace_status[0x2]; 12611 u8 reserved_at_2[0x2]; 12612 u8 arm_event[0x1]; 12613 u8 reserved_at_5[0xb]; 12614 u8 modify_field_select[0x10]; 12615 u8 reserved_at_20[0x2b]; 12616 u8 current_timestamp52_32[0x15]; 12617 u8 current_timestamp31_0[0x20]; 12618 u8 reserved_at_80[0x180]; 12619 }; 12620 12621 struct mlx5_ifc_host_params_context_bits { 12622 u8 host_number[0x8]; 12623 u8 reserved_at_8[0x5]; 12624 u8 host_pf_not_exist[0x1]; 12625 u8 reserved_at_14[0x1]; 12626 u8 host_pf_disabled[0x1]; 12627 u8 host_num_of_vfs[0x10]; 12628 12629 u8 host_total_vfs[0x10]; 12630 u8 host_pci_bus[0x10]; 12631 12632 u8 reserved_at_40[0x10]; 12633 u8 host_pci_device[0x10]; 12634 12635 u8 reserved_at_60[0x10]; 12636 u8 host_pci_function[0x10]; 12637 12638 u8 reserved_at_80[0x180]; 12639 }; 12640 12641 struct mlx5_ifc_query_esw_functions_in_bits { 12642 u8 opcode[0x10]; 12643 u8 reserved_at_10[0x10]; 12644 12645 u8 reserved_at_20[0x10]; 12646 u8 op_mod[0x10]; 12647 12648 u8 reserved_at_40[0x40]; 12649 }; 12650 12651 struct mlx5_ifc_query_esw_functions_out_bits { 12652 u8 status[0x8]; 12653 u8 reserved_at_8[0x18]; 12654 12655 u8 syndrome[0x20]; 12656 12657 u8 reserved_at_40[0x40]; 12658 12659 struct mlx5_ifc_host_params_context_bits host_params_context; 12660 12661 u8 reserved_at_280[0x180]; 12662 u8 host_sf_enable[][0x40]; 12663 }; 12664 12665 struct mlx5_ifc_sf_partition_bits { 12666 u8 reserved_at_0[0x10]; 12667 u8 log_num_sf[0x8]; 12668 u8 log_sf_bar_size[0x8]; 12669 }; 12670 12671 struct mlx5_ifc_query_sf_partitions_out_bits { 12672 u8 status[0x8]; 12673 u8 reserved_at_8[0x18]; 12674 12675 u8 syndrome[0x20]; 12676 12677 u8 reserved_at_40[0x18]; 12678 u8 num_sf_partitions[0x8]; 12679 12680 u8 reserved_at_60[0x20]; 12681 12682 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12683 }; 12684 12685 struct mlx5_ifc_query_sf_partitions_in_bits { 12686 u8 opcode[0x10]; 12687 u8 reserved_at_10[0x10]; 12688 12689 u8 reserved_at_20[0x10]; 12690 u8 op_mod[0x10]; 12691 12692 u8 reserved_at_40[0x40]; 12693 }; 12694 12695 struct mlx5_ifc_dealloc_sf_out_bits { 12696 u8 status[0x8]; 12697 u8 reserved_at_8[0x18]; 12698 12699 u8 syndrome[0x20]; 12700 12701 u8 reserved_at_40[0x40]; 12702 }; 12703 12704 struct mlx5_ifc_dealloc_sf_in_bits { 12705 u8 opcode[0x10]; 12706 u8 reserved_at_10[0x10]; 12707 12708 u8 reserved_at_20[0x10]; 12709 u8 op_mod[0x10]; 12710 12711 u8 reserved_at_40[0x10]; 12712 u8 function_id[0x10]; 12713 12714 u8 reserved_at_60[0x20]; 12715 }; 12716 12717 struct mlx5_ifc_alloc_sf_out_bits { 12718 u8 status[0x8]; 12719 u8 reserved_at_8[0x18]; 12720 12721 u8 syndrome[0x20]; 12722 12723 u8 reserved_at_40[0x40]; 12724 }; 12725 12726 struct mlx5_ifc_alloc_sf_in_bits { 12727 u8 opcode[0x10]; 12728 u8 reserved_at_10[0x10]; 12729 12730 u8 reserved_at_20[0x10]; 12731 u8 op_mod[0x10]; 12732 12733 u8 reserved_at_40[0x10]; 12734 u8 function_id[0x10]; 12735 12736 u8 reserved_at_60[0x20]; 12737 }; 12738 12739 struct mlx5_ifc_affiliated_event_header_bits { 12740 u8 reserved_at_0[0x10]; 12741 u8 obj_type[0x10]; 12742 12743 u8 obj_id[0x20]; 12744 }; 12745 12746 enum { 12747 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12748 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12749 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12750 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12751 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12752 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12753 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12754 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12755 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12756 }; 12757 12758 enum { 12759 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12760 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12761 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12762 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12763 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12764 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12765 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12766 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12767 }; 12768 12769 enum { 12770 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12771 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12772 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12773 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12774 }; 12775 12776 enum { 12777 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12778 }; 12779 12780 enum { 12781 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12782 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12783 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12784 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12785 }; 12786 12787 enum { 12788 MLX5_IPSEC_ASO_MODE = 0x0, 12789 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12790 MLX5_IPSEC_ASO_INC_SN = 0x2, 12791 }; 12792 12793 enum { 12794 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12795 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12796 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12797 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12798 }; 12799 12800 struct mlx5_ifc_ipsec_aso_bits { 12801 u8 valid[0x1]; 12802 u8 reserved_at_201[0x1]; 12803 u8 mode[0x2]; 12804 u8 window_sz[0x2]; 12805 u8 soft_lft_arm[0x1]; 12806 u8 hard_lft_arm[0x1]; 12807 u8 remove_flow_enable[0x1]; 12808 u8 esn_event_arm[0x1]; 12809 u8 reserved_at_20a[0x16]; 12810 12811 u8 remove_flow_pkt_cnt[0x20]; 12812 12813 u8 remove_flow_soft_lft[0x20]; 12814 12815 u8 reserved_at_260[0x80]; 12816 12817 u8 mode_parameter[0x20]; 12818 12819 u8 replay_protection_window[0x100]; 12820 }; 12821 12822 struct mlx5_ifc_ipsec_obj_bits { 12823 u8 modify_field_select[0x40]; 12824 u8 full_offload[0x1]; 12825 u8 reserved_at_41[0x1]; 12826 u8 esn_en[0x1]; 12827 u8 esn_overlap[0x1]; 12828 u8 reserved_at_44[0x2]; 12829 u8 icv_length[0x2]; 12830 u8 reserved_at_48[0x4]; 12831 u8 aso_return_reg[0x4]; 12832 u8 reserved_at_50[0x10]; 12833 12834 u8 esn_msb[0x20]; 12835 12836 u8 reserved_at_80[0x8]; 12837 u8 dekn[0x18]; 12838 12839 u8 salt[0x20]; 12840 12841 u8 implicit_iv[0x40]; 12842 12843 u8 reserved_at_100[0x8]; 12844 u8 ipsec_aso_access_pd[0x18]; 12845 u8 reserved_at_120[0xe0]; 12846 12847 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12848 }; 12849 12850 struct mlx5_ifc_create_ipsec_obj_in_bits { 12851 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12852 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12853 }; 12854 12855 enum { 12856 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12857 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12858 }; 12859 12860 struct mlx5_ifc_query_ipsec_obj_out_bits { 12861 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12862 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12863 }; 12864 12865 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12866 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12867 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12868 }; 12869 12870 enum { 12871 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12872 }; 12873 12874 enum { 12875 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12876 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12877 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12878 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12879 }; 12880 12881 #define MLX5_MACSEC_ASO_INC_SN 0x2 12882 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12883 12884 struct mlx5_ifc_macsec_aso_bits { 12885 u8 valid[0x1]; 12886 u8 reserved_at_1[0x1]; 12887 u8 mode[0x2]; 12888 u8 window_size[0x2]; 12889 u8 soft_lifetime_arm[0x1]; 12890 u8 hard_lifetime_arm[0x1]; 12891 u8 remove_flow_enable[0x1]; 12892 u8 epn_event_arm[0x1]; 12893 u8 reserved_at_a[0x16]; 12894 12895 u8 remove_flow_packet_count[0x20]; 12896 12897 u8 remove_flow_soft_lifetime[0x20]; 12898 12899 u8 reserved_at_60[0x80]; 12900 12901 u8 mode_parameter[0x20]; 12902 12903 u8 replay_protection_window[8][0x20]; 12904 }; 12905 12906 struct mlx5_ifc_macsec_offload_obj_bits { 12907 u8 modify_field_select[0x40]; 12908 12909 u8 confidentiality_en[0x1]; 12910 u8 reserved_at_41[0x1]; 12911 u8 epn_en[0x1]; 12912 u8 epn_overlap[0x1]; 12913 u8 reserved_at_44[0x2]; 12914 u8 confidentiality_offset[0x2]; 12915 u8 reserved_at_48[0x4]; 12916 u8 aso_return_reg[0x4]; 12917 u8 reserved_at_50[0x10]; 12918 12919 u8 epn_msb[0x20]; 12920 12921 u8 reserved_at_80[0x8]; 12922 u8 dekn[0x18]; 12923 12924 u8 reserved_at_a0[0x20]; 12925 12926 u8 sci[0x40]; 12927 12928 u8 reserved_at_100[0x8]; 12929 u8 macsec_aso_access_pd[0x18]; 12930 12931 u8 reserved_at_120[0x60]; 12932 12933 u8 salt[3][0x20]; 12934 12935 u8 reserved_at_1e0[0x20]; 12936 12937 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12938 }; 12939 12940 struct mlx5_ifc_create_macsec_obj_in_bits { 12941 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12942 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12943 }; 12944 12945 struct mlx5_ifc_modify_macsec_obj_in_bits { 12946 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12947 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12948 }; 12949 12950 enum { 12951 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12952 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12953 }; 12954 12955 struct mlx5_ifc_query_macsec_obj_out_bits { 12956 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12957 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12958 }; 12959 12960 struct mlx5_ifc_wrapped_dek_bits { 12961 u8 gcm_iv[0x60]; 12962 12963 u8 reserved_at_60[0x20]; 12964 12965 u8 const0[0x1]; 12966 u8 key_size[0x1]; 12967 u8 reserved_at_82[0x2]; 12968 u8 key2_invalid[0x1]; 12969 u8 reserved_at_85[0x3]; 12970 u8 pd[0x18]; 12971 12972 u8 key_purpose[0x5]; 12973 u8 reserved_at_a5[0x13]; 12974 u8 kek_id[0x8]; 12975 12976 u8 reserved_at_c0[0x40]; 12977 12978 u8 key1[0x8][0x20]; 12979 12980 u8 key2[0x8][0x20]; 12981 12982 u8 reserved_at_300[0x40]; 12983 12984 u8 const1[0x1]; 12985 u8 reserved_at_341[0x1f]; 12986 12987 u8 reserved_at_360[0x20]; 12988 12989 u8 auth_tag[0x80]; 12990 }; 12991 12992 struct mlx5_ifc_encryption_key_obj_bits { 12993 u8 modify_field_select[0x40]; 12994 12995 u8 state[0x8]; 12996 u8 sw_wrapped[0x1]; 12997 u8 reserved_at_49[0xb]; 12998 u8 key_size[0x4]; 12999 u8 reserved_at_58[0x4]; 13000 u8 key_purpose[0x4]; 13001 13002 u8 reserved_at_60[0x8]; 13003 u8 pd[0x18]; 13004 13005 u8 reserved_at_80[0x100]; 13006 13007 u8 opaque[0x40]; 13008 13009 u8 reserved_at_1c0[0x40]; 13010 13011 u8 key[8][0x80]; 13012 13013 u8 sw_wrapped_dek[8][0x80]; 13014 13015 u8 reserved_at_a00[0x600]; 13016 }; 13017 13018 struct mlx5_ifc_create_encryption_key_in_bits { 13019 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13020 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13021 }; 13022 13023 struct mlx5_ifc_modify_encryption_key_in_bits { 13024 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13025 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13026 }; 13027 13028 enum { 13029 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 13030 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 13031 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 13032 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 13033 }; 13034 13035 struct mlx5_ifc_flow_meter_parameters_bits { 13036 u8 valid[0x1]; 13037 u8 bucket_overflow[0x1]; 13038 u8 start_color[0x2]; 13039 u8 both_buckets_on_green[0x1]; 13040 u8 reserved_at_5[0x1]; 13041 u8 meter_mode[0x2]; 13042 u8 reserved_at_8[0x18]; 13043 13044 u8 reserved_at_20[0x20]; 13045 13046 u8 reserved_at_40[0x3]; 13047 u8 cbs_exponent[0x5]; 13048 u8 cbs_mantissa[0x8]; 13049 u8 reserved_at_50[0x3]; 13050 u8 cir_exponent[0x5]; 13051 u8 cir_mantissa[0x8]; 13052 13053 u8 reserved_at_60[0x20]; 13054 13055 u8 reserved_at_80[0x3]; 13056 u8 ebs_exponent[0x5]; 13057 u8 ebs_mantissa[0x8]; 13058 u8 reserved_at_90[0x3]; 13059 u8 eir_exponent[0x5]; 13060 u8 eir_mantissa[0x8]; 13061 13062 u8 reserved_at_a0[0x60]; 13063 }; 13064 13065 struct mlx5_ifc_flow_meter_aso_obj_bits { 13066 u8 modify_field_select[0x40]; 13067 13068 u8 reserved_at_40[0x40]; 13069 13070 u8 reserved_at_80[0x8]; 13071 u8 meter_aso_access_pd[0x18]; 13072 13073 u8 reserved_at_a0[0x160]; 13074 13075 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13076 }; 13077 13078 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13079 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13080 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13081 }; 13082 13083 struct mlx5_ifc_int_kek_obj_bits { 13084 u8 modify_field_select[0x40]; 13085 13086 u8 state[0x8]; 13087 u8 auto_gen[0x1]; 13088 u8 reserved_at_49[0xb]; 13089 u8 key_size[0x4]; 13090 u8 reserved_at_58[0x8]; 13091 13092 u8 reserved_at_60[0x8]; 13093 u8 pd[0x18]; 13094 13095 u8 reserved_at_80[0x180]; 13096 u8 key[8][0x80]; 13097 13098 u8 reserved_at_600[0x200]; 13099 }; 13100 13101 struct mlx5_ifc_create_int_kek_obj_in_bits { 13102 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13103 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13104 }; 13105 13106 struct mlx5_ifc_create_int_kek_obj_out_bits { 13107 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13108 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13109 }; 13110 13111 struct mlx5_ifc_sampler_obj_bits { 13112 u8 modify_field_select[0x40]; 13113 13114 u8 table_type[0x8]; 13115 u8 level[0x8]; 13116 u8 reserved_at_50[0xf]; 13117 u8 ignore_flow_level[0x1]; 13118 13119 u8 sample_ratio[0x20]; 13120 13121 u8 reserved_at_80[0x8]; 13122 u8 sample_table_id[0x18]; 13123 13124 u8 reserved_at_a0[0x8]; 13125 u8 default_table_id[0x18]; 13126 13127 u8 sw_steering_icm_address_rx[0x40]; 13128 u8 sw_steering_icm_address_tx[0x40]; 13129 13130 u8 reserved_at_140[0xa0]; 13131 }; 13132 13133 struct mlx5_ifc_create_sampler_obj_in_bits { 13134 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13135 struct mlx5_ifc_sampler_obj_bits sampler_object; 13136 }; 13137 13138 struct mlx5_ifc_query_sampler_obj_out_bits { 13139 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13140 struct mlx5_ifc_sampler_obj_bits sampler_object; 13141 }; 13142 13143 enum { 13144 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13145 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13146 }; 13147 13148 enum { 13149 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13150 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13151 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13152 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13153 }; 13154 13155 struct mlx5_ifc_tls_static_params_bits { 13156 u8 const_2[0x2]; 13157 u8 tls_version[0x4]; 13158 u8 const_1[0x2]; 13159 u8 reserved_at_8[0x14]; 13160 u8 encryption_standard[0x4]; 13161 13162 u8 reserved_at_20[0x20]; 13163 13164 u8 initial_record_number[0x40]; 13165 13166 u8 resync_tcp_sn[0x20]; 13167 13168 u8 gcm_iv[0x20]; 13169 13170 u8 implicit_iv[0x40]; 13171 13172 u8 reserved_at_100[0x8]; 13173 u8 dek_index[0x18]; 13174 13175 u8 reserved_at_120[0xe0]; 13176 }; 13177 13178 struct mlx5_ifc_tls_progress_params_bits { 13179 u8 next_record_tcp_sn[0x20]; 13180 13181 u8 hw_resync_tcp_sn[0x20]; 13182 13183 u8 record_tracker_state[0x2]; 13184 u8 auth_state[0x2]; 13185 u8 reserved_at_44[0x4]; 13186 u8 hw_offset_record_number[0x18]; 13187 }; 13188 13189 enum { 13190 MLX5_MTT_PERM_READ = 1 << 0, 13191 MLX5_MTT_PERM_WRITE = 1 << 1, 13192 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13193 }; 13194 13195 enum { 13196 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13197 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13198 }; 13199 13200 struct mlx5_ifc_suspend_vhca_in_bits { 13201 u8 opcode[0x10]; 13202 u8 uid[0x10]; 13203 13204 u8 reserved_at_20[0x10]; 13205 u8 op_mod[0x10]; 13206 13207 u8 reserved_at_40[0x10]; 13208 u8 vhca_id[0x10]; 13209 13210 u8 reserved_at_60[0x20]; 13211 }; 13212 13213 struct mlx5_ifc_suspend_vhca_out_bits { 13214 u8 status[0x8]; 13215 u8 reserved_at_8[0x18]; 13216 13217 u8 syndrome[0x20]; 13218 13219 u8 reserved_at_40[0x40]; 13220 }; 13221 13222 enum { 13223 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13224 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13225 }; 13226 13227 struct mlx5_ifc_resume_vhca_in_bits { 13228 u8 opcode[0x10]; 13229 u8 uid[0x10]; 13230 13231 u8 reserved_at_20[0x10]; 13232 u8 op_mod[0x10]; 13233 13234 u8 reserved_at_40[0x10]; 13235 u8 vhca_id[0x10]; 13236 13237 u8 reserved_at_60[0x20]; 13238 }; 13239 13240 struct mlx5_ifc_resume_vhca_out_bits { 13241 u8 status[0x8]; 13242 u8 reserved_at_8[0x18]; 13243 13244 u8 syndrome[0x20]; 13245 13246 u8 reserved_at_40[0x40]; 13247 }; 13248 13249 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13250 u8 opcode[0x10]; 13251 u8 uid[0x10]; 13252 13253 u8 reserved_at_20[0x10]; 13254 u8 op_mod[0x10]; 13255 13256 u8 incremental[0x1]; 13257 u8 chunk[0x1]; 13258 u8 reserved_at_42[0xe]; 13259 u8 vhca_id[0x10]; 13260 13261 u8 reserved_at_60[0x20]; 13262 }; 13263 13264 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13265 u8 status[0x8]; 13266 u8 reserved_at_8[0x18]; 13267 13268 u8 syndrome[0x20]; 13269 13270 u8 reserved_at_40[0x40]; 13271 13272 u8 required_umem_size[0x20]; 13273 13274 u8 reserved_at_a0[0x20]; 13275 13276 u8 remaining_total_size[0x40]; 13277 13278 u8 reserved_at_100[0x100]; 13279 }; 13280 13281 struct mlx5_ifc_save_vhca_state_in_bits { 13282 u8 opcode[0x10]; 13283 u8 uid[0x10]; 13284 13285 u8 reserved_at_20[0x10]; 13286 u8 op_mod[0x10]; 13287 13288 u8 incremental[0x1]; 13289 u8 set_track[0x1]; 13290 u8 reserved_at_42[0xe]; 13291 u8 vhca_id[0x10]; 13292 13293 u8 reserved_at_60[0x20]; 13294 13295 u8 va[0x40]; 13296 13297 u8 mkey[0x20]; 13298 13299 u8 size[0x20]; 13300 }; 13301 13302 struct mlx5_ifc_save_vhca_state_out_bits { 13303 u8 status[0x8]; 13304 u8 reserved_at_8[0x18]; 13305 13306 u8 syndrome[0x20]; 13307 13308 u8 actual_image_size[0x20]; 13309 13310 u8 next_required_umem_size[0x20]; 13311 }; 13312 13313 struct mlx5_ifc_load_vhca_state_in_bits { 13314 u8 opcode[0x10]; 13315 u8 uid[0x10]; 13316 13317 u8 reserved_at_20[0x10]; 13318 u8 op_mod[0x10]; 13319 13320 u8 reserved_at_40[0x10]; 13321 u8 vhca_id[0x10]; 13322 13323 u8 reserved_at_60[0x20]; 13324 13325 u8 va[0x40]; 13326 13327 u8 mkey[0x20]; 13328 13329 u8 size[0x20]; 13330 }; 13331 13332 struct mlx5_ifc_load_vhca_state_out_bits { 13333 u8 status[0x8]; 13334 u8 reserved_at_8[0x18]; 13335 13336 u8 syndrome[0x20]; 13337 13338 u8 reserved_at_40[0x40]; 13339 }; 13340 13341 struct mlx5_ifc_adv_rdma_cap_bits { 13342 u8 rdma_transport_manager[0x1]; 13343 u8 rdma_transport_manager_other_eswitch[0x1]; 13344 u8 reserved_at_2[0x1e]; 13345 13346 u8 rcx_type[0x8]; 13347 u8 reserved_at_28[0x2]; 13348 u8 ps_entry_log_max_value[0x6]; 13349 u8 reserved_at_30[0x6]; 13350 u8 qp_max_ps_num_entry[0xa]; 13351 13352 u8 mp_max_num_queues[0x8]; 13353 u8 ps_user_context_max_log_size[0x8]; 13354 u8 message_based_qp_and_striding_wq[0x8]; 13355 u8 reserved_at_58[0x8]; 13356 13357 u8 max_receive_send_message_size_stride[0x10]; 13358 u8 reserved_at_70[0x10]; 13359 13360 u8 max_receive_send_message_size_byte[0x20]; 13361 13362 u8 reserved_at_a0[0x160]; 13363 13364 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13365 13366 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13367 13368 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13369 13370 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13371 13372 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13373 13374 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13375 13376 u8 reserved_at_800[0x3800]; 13377 }; 13378 13379 struct mlx5_ifc_adv_virtualization_cap_bits { 13380 u8 reserved_at_0[0x3]; 13381 u8 pg_track_log_max_num[0x5]; 13382 u8 pg_track_max_num_range[0x8]; 13383 u8 pg_track_log_min_addr_space[0x8]; 13384 u8 pg_track_log_max_addr_space[0x8]; 13385 13386 u8 reserved_at_20[0x3]; 13387 u8 pg_track_log_min_msg_size[0x5]; 13388 u8 reserved_at_28[0x3]; 13389 u8 pg_track_log_max_msg_size[0x5]; 13390 u8 reserved_at_30[0x3]; 13391 u8 pg_track_log_min_page_size[0x5]; 13392 u8 reserved_at_38[0x3]; 13393 u8 pg_track_log_max_page_size[0x5]; 13394 13395 u8 reserved_at_40[0x7c0]; 13396 }; 13397 13398 struct mlx5_ifc_page_track_report_entry_bits { 13399 u8 dirty_address_high[0x20]; 13400 13401 u8 dirty_address_low[0x20]; 13402 }; 13403 13404 enum { 13405 MLX5_PAGE_TRACK_STATE_TRACKING, 13406 MLX5_PAGE_TRACK_STATE_REPORTING, 13407 MLX5_PAGE_TRACK_STATE_ERROR, 13408 }; 13409 13410 struct mlx5_ifc_page_track_range_bits { 13411 u8 start_address[0x40]; 13412 13413 u8 length[0x40]; 13414 }; 13415 13416 struct mlx5_ifc_page_track_bits { 13417 u8 modify_field_select[0x40]; 13418 13419 u8 reserved_at_40[0x10]; 13420 u8 vhca_id[0x10]; 13421 13422 u8 reserved_at_60[0x20]; 13423 13424 u8 state[0x4]; 13425 u8 track_type[0x4]; 13426 u8 log_addr_space_size[0x8]; 13427 u8 reserved_at_90[0x3]; 13428 u8 log_page_size[0x5]; 13429 u8 reserved_at_98[0x3]; 13430 u8 log_msg_size[0x5]; 13431 13432 u8 reserved_at_a0[0x8]; 13433 u8 reporting_qpn[0x18]; 13434 13435 u8 reserved_at_c0[0x18]; 13436 u8 num_ranges[0x8]; 13437 13438 u8 reserved_at_e0[0x20]; 13439 13440 u8 range_start_address[0x40]; 13441 13442 u8 length[0x40]; 13443 13444 struct mlx5_ifc_page_track_range_bits track_range[0]; 13445 }; 13446 13447 struct mlx5_ifc_create_page_track_obj_in_bits { 13448 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13449 struct mlx5_ifc_page_track_bits obj_context; 13450 }; 13451 13452 struct mlx5_ifc_modify_page_track_obj_in_bits { 13453 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13454 struct mlx5_ifc_page_track_bits obj_context; 13455 }; 13456 13457 struct mlx5_ifc_query_page_track_obj_out_bits { 13458 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13459 struct mlx5_ifc_page_track_bits obj_context; 13460 }; 13461 13462 struct mlx5_ifc_msecq_reg_bits { 13463 u8 reserved_at_0[0x20]; 13464 13465 u8 reserved_at_20[0x12]; 13466 u8 network_option[0x2]; 13467 u8 local_ssm_code[0x4]; 13468 u8 local_enhanced_ssm_code[0x8]; 13469 13470 u8 local_clock_identity[0x40]; 13471 13472 u8 reserved_at_80[0x180]; 13473 }; 13474 13475 enum { 13476 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13477 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13478 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13479 }; 13480 13481 enum mlx5_msees_admin_status { 13482 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13483 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13484 }; 13485 13486 enum mlx5_msees_oper_status { 13487 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13488 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13489 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13490 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13491 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13492 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13493 }; 13494 13495 enum mlx5_msees_failure_reason { 13496 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13497 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13498 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13499 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13500 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13501 }; 13502 13503 struct mlx5_ifc_msees_reg_bits { 13504 u8 reserved_at_0[0x8]; 13505 u8 local_port[0x8]; 13506 u8 pnat[0x2]; 13507 u8 lp_msb[0x2]; 13508 u8 reserved_at_14[0xc]; 13509 13510 u8 field_select[0x20]; 13511 13512 u8 admin_status[0x4]; 13513 u8 oper_status[0x4]; 13514 u8 ho_acq[0x1]; 13515 u8 reserved_at_49[0xc]; 13516 u8 admin_freq_measure[0x1]; 13517 u8 oper_freq_measure[0x1]; 13518 u8 failure_reason[0x9]; 13519 13520 u8 frequency_diff[0x20]; 13521 13522 u8 reserved_at_80[0x180]; 13523 }; 13524 13525 struct mlx5_ifc_mrtcq_reg_bits { 13526 u8 reserved_at_0[0x40]; 13527 13528 u8 rt_clock_identity[0x40]; 13529 13530 u8 reserved_at_80[0x180]; 13531 }; 13532 13533 struct mlx5_ifc_pcie_cong_event_obj_bits { 13534 u8 modify_select_field[0x40]; 13535 13536 u8 inbound_event_en[0x1]; 13537 u8 outbound_event_en[0x1]; 13538 u8 reserved_at_42[0x1e]; 13539 13540 u8 reserved_at_60[0x1]; 13541 u8 inbound_cong_state[0x3]; 13542 u8 reserved_at_64[0x1]; 13543 u8 outbound_cong_state[0x3]; 13544 u8 reserved_at_68[0x18]; 13545 13546 u8 inbound_cong_low_threshold[0x10]; 13547 u8 inbound_cong_high_threshold[0x10]; 13548 13549 u8 outbound_cong_low_threshold[0x10]; 13550 u8 outbound_cong_high_threshold[0x10]; 13551 13552 u8 reserved_at_e0[0x340]; 13553 }; 13554 13555 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13556 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13557 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13558 }; 13559 13560 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13561 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13562 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13563 }; 13564 13565 enum mlx5e_pcie_cong_event_mod_field { 13566 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13567 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13568 }; 13569 13570 struct mlx5_ifc_psp_rotate_key_in_bits { 13571 u8 opcode[0x10]; 13572 u8 uid[0x10]; 13573 13574 u8 reserved_at_20[0x10]; 13575 u8 op_mod[0x10]; 13576 13577 u8 reserved_at_40[0x40]; 13578 }; 13579 13580 struct mlx5_ifc_psp_rotate_key_out_bits { 13581 u8 status[0x8]; 13582 u8 reserved_at_8[0x18]; 13583 13584 u8 syndrome[0x20]; 13585 13586 u8 reserved_at_40[0x40]; 13587 }; 13588 13589 enum mlx5_psp_gen_spi_in_key_size { 13590 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13591 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13592 }; 13593 13594 struct mlx5_ifc_key_spi_bits { 13595 u8 spi[0x20]; 13596 13597 u8 reserved_at_20[0x60]; 13598 13599 u8 key[8][0x20]; 13600 }; 13601 13602 struct mlx5_ifc_psp_gen_spi_in_bits { 13603 u8 opcode[0x10]; 13604 u8 uid[0x10]; 13605 13606 u8 reserved_at_20[0x10]; 13607 u8 op_mod[0x10]; 13608 13609 u8 reserved_at_40[0x20]; 13610 13611 u8 key_size[0x2]; 13612 u8 reserved_at_62[0xe]; 13613 u8 num_of_spi[0x10]; 13614 }; 13615 13616 struct mlx5_ifc_psp_gen_spi_out_bits { 13617 u8 status[0x8]; 13618 u8 reserved_at_8[0x18]; 13619 13620 u8 syndrome[0x20]; 13621 13622 u8 reserved_at_40[0x10]; 13623 u8 num_of_spi[0x10]; 13624 13625 u8 reserved_at_60[0x20]; 13626 13627 struct mlx5_ifc_key_spi_bits key_spi[]; 13628 }; 13629 13630 #endif /* MLX5_IFC_H */ 13631